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5a3af129 MB |
1 | /* |
2 | * Driver for the PCM512x CODECs | |
3 | * | |
4 | * Author: Mark Brown <broonie@linaro.org> | |
5 | * Copyright 2014 Linaro Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * version 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | */ | |
16 | ||
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/clk.h> | |
d48502ea | 21 | #include <linux/kernel.h> |
5a3af129 MB |
22 | #include <linux/pm_runtime.h> |
23 | #include <linux/regmap.h> | |
24 | #include <linux/regulator/consumer.h> | |
f086ba9d | 25 | #include <linux/gcd.h> |
5a3af129 MB |
26 | #include <sound/soc.h> |
27 | #include <sound/soc-dapm.h> | |
81249307 | 28 | #include <sound/pcm_params.h> |
5a3af129 MB |
29 | #include <sound/tlv.h> |
30 | ||
31 | #include "pcm512x.h" | |
32 | ||
f086ba9d PR |
33 | #define DIV_ROUND_DOWN_ULL(ll, d) \ |
34 | ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) | |
f086ba9d | 35 | |
5a3af129 | 36 | #define PCM512x_NUM_SUPPLIES 3 |
06d0ffcc | 37 | static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { |
5a3af129 MB |
38 | "AVDD", |
39 | "DVDD", | |
40 | "CPVDD", | |
41 | }; | |
42 | ||
43 | struct pcm512x_priv { | |
44 | struct regmap *regmap; | |
45 | struct clk *sclk; | |
46 | struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; | |
47 | struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; | |
81249307 | 48 | int fmt; |
f086ba9d PR |
49 | int pll_in; |
50 | int pll_out; | |
51 | int pll_r; | |
52 | int pll_j; | |
53 | int pll_d; | |
54 | int pll_p; | |
55 | unsigned long real_pll; | |
f29933c9 PR |
56 | unsigned long overclock_pll; |
57 | unsigned long overclock_dac; | |
58 | unsigned long overclock_dsp; | |
5a3af129 MB |
59 | }; |
60 | ||
61 | /* | |
62 | * We can't use the same notifier block for more than one supply and | |
63 | * there's no way I can see to get from a callback to the caller | |
64 | * except container_of(). | |
65 | */ | |
66 | #define PCM512x_REGULATOR_EVENT(n) \ | |
67 | static int pcm512x_regulator_event_##n(struct notifier_block *nb, \ | |
68 | unsigned long event, void *data) \ | |
69 | { \ | |
70 | struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \ | |
71 | supply_nb[n]); \ | |
72 | if (event & REGULATOR_EVENT_DISABLE) { \ | |
73 | regcache_mark_dirty(pcm512x->regmap); \ | |
74 | regcache_cache_only(pcm512x->regmap, true); \ | |
75 | } \ | |
76 | return 0; \ | |
77 | } | |
78 | ||
79 | PCM512x_REGULATOR_EVENT(0) | |
80 | PCM512x_REGULATOR_EVENT(1) | |
81 | PCM512x_REGULATOR_EVENT(2) | |
82 | ||
83 | static const struct reg_default pcm512x_reg_defaults[] = { | |
806d6466 MB |
84 | { PCM512x_RESET, 0x00 }, |
85 | { PCM512x_POWER, 0x00 }, | |
86 | { PCM512x_MUTE, 0x00 }, | |
87 | { PCM512x_DSP, 0x00 }, | |
88 | { PCM512x_PLL_REF, 0x00 }, | |
81249307 | 89 | { PCM512x_DAC_REF, 0x00 }, |
806d6466 MB |
90 | { PCM512x_DAC_ROUTING, 0x11 }, |
91 | { PCM512x_DSP_PROGRAM, 0x01 }, | |
92 | { PCM512x_CLKDET, 0x00 }, | |
93 | { PCM512x_AUTO_MUTE, 0x00 }, | |
94 | { PCM512x_ERROR_DETECT, 0x00 }, | |
95 | { PCM512x_DIGITAL_VOLUME_1, 0x00 }, | |
96 | { PCM512x_DIGITAL_VOLUME_2, 0x30 }, | |
97 | { PCM512x_DIGITAL_VOLUME_3, 0x30 }, | |
98 | { PCM512x_DIGITAL_MUTE_1, 0x22 }, | |
99 | { PCM512x_DIGITAL_MUTE_2, 0x00 }, | |
100 | { PCM512x_DIGITAL_MUTE_3, 0x07 }, | |
101 | { PCM512x_OUTPUT_AMPLITUDE, 0x00 }, | |
102 | { PCM512x_ANALOG_GAIN_CTRL, 0x00 }, | |
103 | { PCM512x_UNDERVOLTAGE_PROT, 0x00 }, | |
104 | { PCM512x_ANALOG_MUTE_CTRL, 0x00 }, | |
105 | { PCM512x_ANALOG_GAIN_BOOST, 0x00 }, | |
106 | { PCM512x_VCOM_CTRL_1, 0x00 }, | |
107 | { PCM512x_VCOM_CTRL_2, 0x01 }, | |
81249307 PR |
108 | { PCM512x_BCLK_LRCLK_CFG, 0x00 }, |
109 | { PCM512x_MASTER_MODE, 0x7c }, | |
7c4e1119 | 110 | { PCM512x_GPIO_DACIN, 0x00 }, |
f086ba9d | 111 | { PCM512x_GPIO_PLLIN, 0x00 }, |
81249307 | 112 | { PCM512x_SYNCHRONIZE, 0x10 }, |
f086ba9d PR |
113 | { PCM512x_PLL_COEFF_0, 0x00 }, |
114 | { PCM512x_PLL_COEFF_1, 0x00 }, | |
115 | { PCM512x_PLL_COEFF_2, 0x00 }, | |
116 | { PCM512x_PLL_COEFF_3, 0x00 }, | |
117 | { PCM512x_PLL_COEFF_4, 0x00 }, | |
81249307 PR |
118 | { PCM512x_DSP_CLKDIV, 0x00 }, |
119 | { PCM512x_DAC_CLKDIV, 0x00 }, | |
120 | { PCM512x_NCP_CLKDIV, 0x00 }, | |
121 | { PCM512x_OSR_CLKDIV, 0x00 }, | |
122 | { PCM512x_MASTER_CLKDIV_1, 0x00 }, | |
123 | { PCM512x_MASTER_CLKDIV_2, 0x00 }, | |
124 | { PCM512x_FS_SPEED_MODE, 0x00 }, | |
125 | { PCM512x_IDAC_1, 0x01 }, | |
126 | { PCM512x_IDAC_2, 0x00 }, | |
5a3af129 MB |
127 | }; |
128 | ||
129 | static bool pcm512x_readable(struct device *dev, unsigned int reg) | |
130 | { | |
131 | switch (reg) { | |
132 | case PCM512x_RESET: | |
133 | case PCM512x_POWER: | |
134 | case PCM512x_MUTE: | |
135 | case PCM512x_PLL_EN: | |
136 | case PCM512x_SPI_MISO_FUNCTION: | |
137 | case PCM512x_DSP: | |
138 | case PCM512x_GPIO_EN: | |
139 | case PCM512x_BCLK_LRCLK_CFG: | |
140 | case PCM512x_DSP_GPIO_INPUT: | |
141 | case PCM512x_MASTER_MODE: | |
142 | case PCM512x_PLL_REF: | |
81249307 | 143 | case PCM512x_DAC_REF: |
7c4e1119 | 144 | case PCM512x_GPIO_DACIN: |
f086ba9d | 145 | case PCM512x_GPIO_PLLIN: |
81249307 | 146 | case PCM512x_SYNCHRONIZE: |
5a3af129 MB |
147 | case PCM512x_PLL_COEFF_0: |
148 | case PCM512x_PLL_COEFF_1: | |
149 | case PCM512x_PLL_COEFF_2: | |
150 | case PCM512x_PLL_COEFF_3: | |
151 | case PCM512x_PLL_COEFF_4: | |
152 | case PCM512x_DSP_CLKDIV: | |
153 | case PCM512x_DAC_CLKDIV: | |
154 | case PCM512x_NCP_CLKDIV: | |
155 | case PCM512x_OSR_CLKDIV: | |
156 | case PCM512x_MASTER_CLKDIV_1: | |
157 | case PCM512x_MASTER_CLKDIV_2: | |
158 | case PCM512x_FS_SPEED_MODE: | |
159 | case PCM512x_IDAC_1: | |
160 | case PCM512x_IDAC_2: | |
161 | case PCM512x_ERROR_DETECT: | |
162 | case PCM512x_I2S_1: | |
163 | case PCM512x_I2S_2: | |
164 | case PCM512x_DAC_ROUTING: | |
165 | case PCM512x_DSP_PROGRAM: | |
166 | case PCM512x_CLKDET: | |
167 | case PCM512x_AUTO_MUTE: | |
168 | case PCM512x_DIGITAL_VOLUME_1: | |
169 | case PCM512x_DIGITAL_VOLUME_2: | |
170 | case PCM512x_DIGITAL_VOLUME_3: | |
171 | case PCM512x_DIGITAL_MUTE_1: | |
172 | case PCM512x_DIGITAL_MUTE_2: | |
173 | case PCM512x_DIGITAL_MUTE_3: | |
174 | case PCM512x_GPIO_OUTPUT_1: | |
175 | case PCM512x_GPIO_OUTPUT_2: | |
176 | case PCM512x_GPIO_OUTPUT_3: | |
177 | case PCM512x_GPIO_OUTPUT_4: | |
178 | case PCM512x_GPIO_OUTPUT_5: | |
179 | case PCM512x_GPIO_OUTPUT_6: | |
180 | case PCM512x_GPIO_CONTROL_1: | |
181 | case PCM512x_GPIO_CONTROL_2: | |
182 | case PCM512x_OVERFLOW: | |
183 | case PCM512x_RATE_DET_1: | |
184 | case PCM512x_RATE_DET_2: | |
185 | case PCM512x_RATE_DET_3: | |
186 | case PCM512x_RATE_DET_4: | |
f086ba9d | 187 | case PCM512x_CLOCK_STATUS: |
5a3af129 MB |
188 | case PCM512x_ANALOG_MUTE_DET: |
189 | case PCM512x_GPIN: | |
190 | case PCM512x_DIGITAL_MUTE_DET: | |
806d6466 MB |
191 | case PCM512x_OUTPUT_AMPLITUDE: |
192 | case PCM512x_ANALOG_GAIN_CTRL: | |
193 | case PCM512x_UNDERVOLTAGE_PROT: | |
194 | case PCM512x_ANALOG_MUTE_CTRL: | |
195 | case PCM512x_ANALOG_GAIN_BOOST: | |
196 | case PCM512x_VCOM_CTRL_1: | |
197 | case PCM512x_VCOM_CTRL_2: | |
198 | case PCM512x_CRAM_CTRL: | |
f086ba9d PR |
199 | case PCM512x_FLEX_A: |
200 | case PCM512x_FLEX_B: | |
5a3af129 MB |
201 | return true; |
202 | default: | |
806d6466 MB |
203 | /* There are 256 raw register addresses */ |
204 | return reg < 0xff; | |
5a3af129 MB |
205 | } |
206 | } | |
207 | ||
208 | static bool pcm512x_volatile(struct device *dev, unsigned int reg) | |
209 | { | |
210 | switch (reg) { | |
211 | case PCM512x_PLL_EN: | |
212 | case PCM512x_OVERFLOW: | |
213 | case PCM512x_RATE_DET_1: | |
214 | case PCM512x_RATE_DET_2: | |
215 | case PCM512x_RATE_DET_3: | |
216 | case PCM512x_RATE_DET_4: | |
f086ba9d | 217 | case PCM512x_CLOCK_STATUS: |
5a3af129 MB |
218 | case PCM512x_ANALOG_MUTE_DET: |
219 | case PCM512x_GPIN: | |
220 | case PCM512x_DIGITAL_MUTE_DET: | |
806d6466 | 221 | case PCM512x_CRAM_CTRL: |
5a3af129 MB |
222 | return true; |
223 | default: | |
806d6466 MB |
224 | /* There are 256 raw register addresses */ |
225 | return reg < 0xff; | |
5a3af129 MB |
226 | } |
227 | } | |
228 | ||
f29933c9 PR |
229 | static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol, |
230 | struct snd_ctl_elem_value *ucontrol) | |
231 | { | |
232 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
233 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
234 | ||
235 | ucontrol->value.integer.value[0] = pcm512x->overclock_pll; | |
236 | return 0; | |
237 | } | |
238 | ||
239 | static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol, | |
240 | struct snd_ctl_elem_value *ucontrol) | |
241 | { | |
242 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
243 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
244 | ||
b6070c11 | 245 | switch (snd_soc_codec_get_bias_level(codec)) { |
f29933c9 PR |
246 | case SND_SOC_BIAS_OFF: |
247 | case SND_SOC_BIAS_STANDBY: | |
248 | break; | |
249 | default: | |
250 | return -EBUSY; | |
251 | } | |
252 | ||
253 | pcm512x->overclock_pll = ucontrol->value.integer.value[0]; | |
254 | return 0; | |
255 | } | |
256 | ||
257 | static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol, | |
258 | struct snd_ctl_elem_value *ucontrol) | |
259 | { | |
260 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
261 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
262 | ||
263 | ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol, | |
268 | struct snd_ctl_elem_value *ucontrol) | |
269 | { | |
270 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
271 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
272 | ||
b6070c11 | 273 | switch (snd_soc_codec_get_bias_level(codec)) { |
f29933c9 PR |
274 | case SND_SOC_BIAS_OFF: |
275 | case SND_SOC_BIAS_STANDBY: | |
276 | break; | |
277 | default: | |
278 | return -EBUSY; | |
279 | } | |
280 | ||
281 | pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; | |
282 | return 0; | |
283 | } | |
284 | ||
285 | static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol, | |
286 | struct snd_ctl_elem_value *ucontrol) | |
287 | { | |
288 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
289 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
290 | ||
291 | ucontrol->value.integer.value[0] = pcm512x->overclock_dac; | |
292 | return 0; | |
293 | } | |
294 | ||
295 | static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol, | |
296 | struct snd_ctl_elem_value *ucontrol) | |
297 | { | |
298 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
299 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
300 | ||
b6070c11 | 301 | switch (snd_soc_codec_get_bias_level(codec)) { |
f29933c9 PR |
302 | case SND_SOC_BIAS_OFF: |
303 | case SND_SOC_BIAS_STANDBY: | |
304 | break; | |
305 | default: | |
306 | return -EBUSY; | |
307 | } | |
308 | ||
309 | pcm512x->overclock_dac = ucontrol->value.integer.value[0]; | |
310 | return 0; | |
311 | } | |
312 | ||
5a3af129 | 313 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1); |
5be2fc20 MB |
314 | static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0); |
315 | static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0); | |
5a3af129 | 316 | |
06d0ffcc | 317 | static const char * const pcm512x_dsp_program_texts[] = { |
5a3af129 MB |
318 | "FIR interpolation with de-emphasis", |
319 | "Low latency IIR with de-emphasis", | |
5a3af129 | 320 | "High attenuation with de-emphasis", |
3a8e5019 | 321 | "Fixed process flow", |
5a3af129 MB |
322 | "Ringing-less low latency FIR", |
323 | }; | |
324 | ||
325 | static const unsigned int pcm512x_dsp_program_values[] = { | |
326 | 1, | |
327 | 2, | |
328 | 3, | |
329 | 5, | |
330 | 7, | |
331 | }; | |
332 | ||
e97db9ab MB |
333 | static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program, |
334 | PCM512x_DSP_PROGRAM, 0, 0x1f, | |
335 | pcm512x_dsp_program_texts, | |
336 | pcm512x_dsp_program_values); | |
5a3af129 | 337 | |
06d0ffcc | 338 | static const char * const pcm512x_clk_missing_text[] = { |
5a3af129 MB |
339 | "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s" |
340 | }; | |
341 | ||
342 | static const struct soc_enum pcm512x_clk_missing = | |
343 | SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text); | |
344 | ||
06d0ffcc | 345 | static const char * const pcm512x_autom_text[] = { |
5a3af129 MB |
346 | "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s" |
347 | }; | |
348 | ||
349 | static const struct soc_enum pcm512x_autom_l = | |
350 | SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8, | |
351 | pcm512x_autom_text); | |
352 | ||
353 | static const struct soc_enum pcm512x_autom_r = | |
354 | SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8, | |
355 | pcm512x_autom_text); | |
356 | ||
06d0ffcc | 357 | static const char * const pcm512x_ramp_rate_text[] = { |
5a3af129 MB |
358 | "1 sample/update", "2 samples/update", "4 samples/update", |
359 | "Immediate" | |
360 | }; | |
361 | ||
362 | static const struct soc_enum pcm512x_vndf = | |
363 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4, | |
364 | pcm512x_ramp_rate_text); | |
365 | ||
366 | static const struct soc_enum pcm512x_vnuf = | |
367 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4, | |
368 | pcm512x_ramp_rate_text); | |
369 | ||
370 | static const struct soc_enum pcm512x_vedf = | |
371 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4, | |
372 | pcm512x_ramp_rate_text); | |
373 | ||
06d0ffcc | 374 | static const char * const pcm512x_ramp_step_text[] = { |
5a3af129 MB |
375 | "4dB/step", "2dB/step", "1dB/step", "0.5dB/step" |
376 | }; | |
377 | ||
378 | static const struct soc_enum pcm512x_vnds = | |
379 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4, | |
380 | pcm512x_ramp_step_text); | |
381 | ||
382 | static const struct soc_enum pcm512x_vnus = | |
383 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4, | |
384 | pcm512x_ramp_step_text); | |
385 | ||
386 | static const struct soc_enum pcm512x_veds = | |
387 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4, | |
388 | pcm512x_ramp_step_text); | |
389 | ||
390 | static const struct snd_kcontrol_new pcm512x_controls[] = { | |
1c6d3680 | 391 | SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, |
5a3af129 | 392 | PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), |
4d9b13c7 | 393 | SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL, |
5be2fc20 | 394 | PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), |
4d9b13c7 | 395 | SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, |
5be2fc20 | 396 | PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), |
1c6d3680 | 397 | SOC_DOUBLE("Digital Playback Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT, |
5a3af129 MB |
398 | PCM512x_RQMR_SHIFT, 1, 1), |
399 | ||
400 | SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), | |
54581be7 | 401 | SOC_ENUM("DSP Program", pcm512x_dsp_program), |
5a3af129 MB |
402 | |
403 | SOC_ENUM("Clock Missing Period", pcm512x_clk_missing), | |
404 | SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l), | |
405 | SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r), | |
406 | SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3, | |
407 | PCM512x_ACTL_SHIFT, 1, 0), | |
408 | SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, | |
376dc490 | 409 | PCM512x_AMRE_SHIFT, 1, 0), |
5a3af129 MB |
410 | |
411 | SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf), | |
412 | SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds), | |
413 | SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf), | |
414 | SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus), | |
415 | SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf), | |
416 | SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds), | |
f29933c9 PR |
417 | |
418 | SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0, | |
419 | pcm512x_overclock_pll_get, pcm512x_overclock_pll_put), | |
420 | SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0, | |
421 | pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put), | |
422 | SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0, | |
423 | pcm512x_overclock_dac_get, pcm512x_overclock_dac_put), | |
5a3af129 MB |
424 | }; |
425 | ||
426 | static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = { | |
427 | SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), | |
428 | SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), | |
429 | ||
430 | SND_SOC_DAPM_OUTPUT("OUTL"), | |
431 | SND_SOC_DAPM_OUTPUT("OUTR"), | |
432 | }; | |
433 | ||
434 | static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = { | |
435 | { "DACL", NULL, "Playback" }, | |
436 | { "DACR", NULL, "Playback" }, | |
437 | ||
438 | { "OUTL", NULL, "DACL" }, | |
439 | { "OUTR", NULL, "DACR" }, | |
440 | }; | |
441 | ||
f29933c9 PR |
442 | static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x) |
443 | { | |
444 | return 25000000 + 25000000 * pcm512x->overclock_pll / 100; | |
445 | } | |
446 | ||
447 | static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x) | |
448 | { | |
449 | return 50000000 + 50000000 * pcm512x->overclock_dsp / 100; | |
450 | } | |
451 | ||
452 | static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x, | |
453 | unsigned long rate) | |
454 | { | |
455 | return rate + rate * pcm512x->overclock_dac / 100; | |
456 | } | |
457 | ||
458 | static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x) | |
459 | { | |
460 | if (!pcm512x->pll_out) | |
461 | return 25000000; | |
462 | return pcm512x_pll_max(pcm512x); | |
463 | } | |
464 | ||
465 | static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x, | |
466 | unsigned long dac_rate) | |
467 | { | |
468 | /* | |
469 | * If the DAC is not actually overclocked, use the good old | |
470 | * NCP target rate... | |
471 | */ | |
472 | if (dac_rate <= 6144000) | |
473 | return 1536000; | |
474 | /* | |
475 | * ...but if the DAC is in fact overclocked, bump the NCP target | |
476 | * rate to get the recommended dividers even when overclocking. | |
477 | */ | |
478 | return pcm512x_dac_max(pcm512x, 1536000); | |
479 | } | |
480 | ||
81249307 PR |
481 | static const u32 pcm512x_dai_rates[] = { |
482 | 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, | |
483 | 88200, 96000, 176400, 192000, 384000, | |
484 | }; | |
485 | ||
486 | static const struct snd_pcm_hw_constraint_list constraints_slave = { | |
487 | .count = ARRAY_SIZE(pcm512x_dai_rates), | |
488 | .list = pcm512x_dai_rates, | |
489 | }; | |
490 | ||
f086ba9d PR |
491 | static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, |
492 | struct snd_pcm_hw_rule *rule) | |
493 | { | |
f29933c9 | 494 | struct pcm512x_priv *pcm512x = rule->private; |
9c7da1a5 | 495 | struct snd_interval ranges[2]; |
f086ba9d PR |
496 | int frame_size; |
497 | ||
498 | frame_size = snd_soc_params_to_frame_size(params); | |
499 | if (frame_size < 0) | |
500 | return frame_size; | |
501 | ||
9c7da1a5 PR |
502 | switch (frame_size) { |
503 | case 32: | |
504 | /* No hole when the frame size is 32. */ | |
f086ba9d | 505 | return 0; |
9c7da1a5 PR |
506 | case 48: |
507 | case 64: | |
508 | /* There is only one hole in the range of supported | |
509 | * rates, but it moves with the frame size. | |
510 | */ | |
511 | memset(ranges, 0, sizeof(ranges)); | |
512 | ranges[0].min = 8000; | |
f29933c9 | 513 | ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; |
9c7da1a5 PR |
514 | ranges[1].min = DIV_ROUND_UP(16000000, frame_size); |
515 | ranges[1].max = 384000; | |
516 | break; | |
517 | default: | |
518 | return -EINVAL; | |
519 | } | |
f086ba9d PR |
520 | |
521 | return snd_interval_ranges(hw_param_interval(params, rule->var), | |
9c7da1a5 | 522 | ARRAY_SIZE(ranges), ranges, 0); |
f086ba9d PR |
523 | } |
524 | ||
81249307 PR |
525 | static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, |
526 | struct snd_soc_dai *dai) | |
527 | { | |
528 | struct snd_soc_codec *codec = dai->codec; | |
529 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
530 | struct device *dev = dai->dev; | |
531 | struct snd_pcm_hw_constraint_ratnums *constraints_no_pll; | |
532 | struct snd_ratnum *rats_no_pll; | |
533 | ||
534 | if (IS_ERR(pcm512x->sclk)) { | |
535 | dev_err(dev, "Need SCLK for master mode: %ld\n", | |
536 | PTR_ERR(pcm512x->sclk)); | |
537 | return PTR_ERR(pcm512x->sclk); | |
538 | } | |
539 | ||
f086ba9d PR |
540 | if (pcm512x->pll_out) |
541 | return snd_pcm_hw_rule_add(substream->runtime, 0, | |
542 | SNDRV_PCM_HW_PARAM_RATE, | |
543 | pcm512x_hw_rule_rate, | |
f29933c9 | 544 | pcm512x, |
f086ba9d PR |
545 | SNDRV_PCM_HW_PARAM_FRAME_BITS, |
546 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
547 | ||
81249307 PR |
548 | constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll), |
549 | GFP_KERNEL); | |
550 | if (!constraints_no_pll) | |
551 | return -ENOMEM; | |
552 | constraints_no_pll->nrats = 1; | |
553 | rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL); | |
554 | if (!rats_no_pll) | |
555 | return -ENOMEM; | |
556 | constraints_no_pll->rats = rats_no_pll; | |
557 | rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; | |
558 | rats_no_pll->den_min = 1; | |
559 | rats_no_pll->den_max = 128; | |
560 | rats_no_pll->den_step = 1; | |
561 | ||
562 | return snd_pcm_hw_constraint_ratnums(substream->runtime, 0, | |
563 | SNDRV_PCM_HW_PARAM_RATE, | |
564 | constraints_no_pll); | |
565 | } | |
566 | ||
567 | static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream, | |
568 | struct snd_soc_dai *dai) | |
569 | { | |
570 | struct snd_soc_codec *codec = dai->codec; | |
571 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
572 | struct device *dev = dai->dev; | |
573 | struct regmap *regmap = pcm512x->regmap; | |
574 | ||
575 | if (IS_ERR(pcm512x->sclk)) { | |
576 | dev_info(dev, "No SCLK, using BCLK: %ld\n", | |
577 | PTR_ERR(pcm512x->sclk)); | |
578 | ||
579 | /* Disable reporting of missing SCLK as an error */ | |
580 | regmap_update_bits(regmap, PCM512x_ERROR_DETECT, | |
581 | PCM512x_IDCH, PCM512x_IDCH); | |
582 | ||
583 | /* Switch PLL input to BCLK */ | |
584 | regmap_update_bits(regmap, PCM512x_PLL_REF, | |
585 | PCM512x_SREF, PCM512x_SREF_BCK); | |
586 | } | |
587 | ||
588 | return snd_pcm_hw_constraint_list(substream->runtime, 0, | |
589 | SNDRV_PCM_HW_PARAM_RATE, | |
590 | &constraints_slave); | |
591 | } | |
592 | ||
593 | static int pcm512x_dai_startup(struct snd_pcm_substream *substream, | |
594 | struct snd_soc_dai *dai) | |
595 | { | |
596 | struct snd_soc_codec *codec = dai->codec; | |
597 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
598 | ||
599 | switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
600 | case SND_SOC_DAIFMT_CBM_CFM: | |
d11c2978 | 601 | case SND_SOC_DAIFMT_CBM_CFS: |
81249307 PR |
602 | return pcm512x_dai_startup_master(substream, dai); |
603 | ||
604 | case SND_SOC_DAIFMT_CBS_CFS: | |
605 | return pcm512x_dai_startup_slave(substream, dai); | |
606 | ||
607 | default: | |
608 | return -EINVAL; | |
609 | } | |
610 | } | |
611 | ||
5a3af129 MB |
612 | static int pcm512x_set_bias_level(struct snd_soc_codec *codec, |
613 | enum snd_soc_bias_level level) | |
614 | { | |
615 | struct pcm512x_priv *pcm512x = dev_get_drvdata(codec->dev); | |
616 | int ret; | |
617 | ||
618 | switch (level) { | |
619 | case SND_SOC_BIAS_ON: | |
620 | case SND_SOC_BIAS_PREPARE: | |
621 | break; | |
622 | ||
623 | case SND_SOC_BIAS_STANDBY: | |
624 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
625 | PCM512x_RQST, 0); | |
626 | if (ret != 0) { | |
627 | dev_err(codec->dev, "Failed to remove standby: %d\n", | |
628 | ret); | |
629 | return ret; | |
630 | } | |
631 | break; | |
632 | ||
633 | case SND_SOC_BIAS_OFF: | |
634 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
635 | PCM512x_RQST, PCM512x_RQST); | |
636 | if (ret != 0) { | |
637 | dev_err(codec->dev, "Failed to request standby: %d\n", | |
638 | ret); | |
639 | return ret; | |
640 | } | |
641 | break; | |
642 | } | |
643 | ||
5a3af129 MB |
644 | return 0; |
645 | } | |
646 | ||
f086ba9d PR |
647 | static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, |
648 | unsigned long bclk_rate) | |
649 | { | |
650 | struct device *dev = dai->dev; | |
f29933c9 PR |
651 | struct snd_soc_codec *codec = dai->codec; |
652 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
f086ba9d PR |
653 | unsigned long sck_rate; |
654 | int pow2; | |
655 | ||
656 | /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ | |
657 | /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ | |
658 | ||
659 | /* select sck_rate as a multiple of bclk_rate but still with | |
660 | * as many factors of 2 as possible, as that makes it easier | |
661 | * to find a fast DAC rate | |
662 | */ | |
f29933c9 | 663 | pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate); |
f086ba9d | 664 | for (; pow2; pow2 >>= 1) { |
f29933c9 PR |
665 | sck_rate = rounddown(pcm512x_pll_max(pcm512x), |
666 | bclk_rate * pow2); | |
f086ba9d PR |
667 | if (sck_rate >= 16000000) |
668 | break; | |
669 | } | |
670 | if (!pow2) { | |
671 | dev_err(dev, "Impossible to generate a suitable SCK\n"); | |
672 | return 0; | |
673 | } | |
674 | ||
675 | dev_dbg(dev, "sck_rate %lu\n", sck_rate); | |
676 | return sck_rate; | |
677 | } | |
678 | ||
679 | /* pll_rate = pllin_rate * R * J.D / P | |
680 | * 1 <= R <= 16 | |
681 | * 1 <= J <= 63 | |
682 | * 0 <= D <= 9999 | |
683 | * 1 <= P <= 15 | |
684 | * 64 MHz <= pll_rate <= 100 MHz | |
685 | * if D == 0 | |
686 | * 1 MHz <= pllin_rate / P <= 20 MHz | |
687 | * else if D > 0 | |
688 | * 6.667 MHz <= pllin_rate / P <= 20 MHz | |
689 | * 4 <= J <= 11 | |
690 | * R = 1 | |
691 | */ | |
692 | static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, | |
693 | unsigned long pllin_rate, | |
694 | unsigned long pll_rate) | |
695 | { | |
696 | struct device *dev = dai->dev; | |
697 | struct snd_soc_codec *codec = dai->codec; | |
698 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
699 | unsigned long common; | |
700 | int R, J, D, P; | |
701 | unsigned long K; /* 10000 * J.D */ | |
702 | unsigned long num; | |
703 | unsigned long den; | |
704 | ||
705 | common = gcd(pll_rate, pllin_rate); | |
706 | dev_dbg(dev, "pll %lu pllin %lu common %lu\n", | |
707 | pll_rate, pllin_rate, common); | |
708 | num = pll_rate / common; | |
709 | den = pllin_rate / common; | |
710 | ||
711 | /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ | |
712 | if (pllin_rate / den > 20000000 && num < 8) { | |
f073faa7 HM |
713 | num *= DIV_ROUND_UP(pllin_rate / den, 20000000); |
714 | den *= DIV_ROUND_UP(pllin_rate / den, 20000000); | |
f086ba9d PR |
715 | } |
716 | dev_dbg(dev, "num / den = %lu / %lu\n", num, den); | |
717 | ||
718 | P = den; | |
719 | if (den <= 15 && num <= 16 * 63 | |
720 | && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { | |
721 | /* Try the case with D = 0 */ | |
722 | D = 0; | |
723 | /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ | |
724 | for (R = 16; R; R--) { | |
725 | if (num % R) | |
726 | continue; | |
727 | J = num / R; | |
728 | if (J == 0 || J > 63) | |
729 | continue; | |
730 | ||
731 | dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P); | |
732 | pcm512x->real_pll = pll_rate; | |
733 | goto done; | |
734 | } | |
735 | /* no luck */ | |
736 | } | |
737 | ||
738 | R = 1; | |
739 | ||
740 | if (num > 0xffffffffUL / 10000) | |
741 | goto fallback; | |
742 | ||
743 | /* Try to find an exact pll_rate using the D > 0 case */ | |
744 | common = gcd(10000 * num, den); | |
745 | num = 10000 * num / common; | |
746 | den /= common; | |
747 | dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common); | |
748 | ||
749 | for (P = den; P <= 15; P++) { | |
750 | if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) | |
751 | continue; | |
752 | if (num * P % den) | |
753 | continue; | |
754 | K = num * P / den; | |
755 | /* J == 12 is ok if D == 0 */ | |
756 | if (K < 40000 || K > 120000) | |
757 | continue; | |
758 | ||
759 | J = K / 10000; | |
760 | D = K % 10000; | |
761 | dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P); | |
762 | pcm512x->real_pll = pll_rate; | |
763 | goto done; | |
764 | } | |
765 | ||
766 | /* Fall back to an approximate pll_rate */ | |
767 | ||
768 | fallback: | |
769 | /* find smallest possible P */ | |
770 | P = DIV_ROUND_UP(pllin_rate, 20000000); | |
771 | if (!P) | |
772 | P = 1; | |
773 | else if (P > 15) { | |
774 | dev_err(dev, "Need a slower clock as pll-input\n"); | |
775 | return -EINVAL; | |
776 | } | |
777 | if (pllin_rate / P < 6667000) { | |
778 | dev_err(dev, "Need a faster clock as pll-input\n"); | |
779 | return -EINVAL; | |
780 | } | |
781 | K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); | |
782 | if (K < 40000) | |
783 | K = 40000; | |
784 | /* J == 12 is ok if D == 0 */ | |
785 | if (K > 120000) | |
786 | K = 120000; | |
787 | J = K / 10000; | |
788 | D = K % 10000; | |
789 | dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P); | |
790 | pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); | |
791 | ||
792 | done: | |
793 | pcm512x->pll_r = R; | |
794 | pcm512x->pll_j = J; | |
795 | pcm512x->pll_d = D; | |
796 | pcm512x->pll_p = P; | |
797 | return 0; | |
798 | } | |
799 | ||
7c4e1119 PR |
800 | static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai, |
801 | unsigned long osr_rate, | |
802 | unsigned long pllin_rate) | |
803 | { | |
804 | struct snd_soc_codec *codec = dai->codec; | |
805 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
806 | unsigned long dac_rate; | |
807 | ||
808 | if (!pcm512x->pll_out) | |
809 | return 0; /* no PLL to bypass, force SCK as DAC input */ | |
810 | ||
811 | if (pllin_rate % osr_rate) | |
812 | return 0; /* futile, quit early */ | |
813 | ||
814 | /* run DAC no faster than 6144000 Hz */ | |
f29933c9 | 815 | for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate); |
7c4e1119 PR |
816 | dac_rate; |
817 | dac_rate -= osr_rate) { | |
818 | ||
819 | if (pllin_rate / dac_rate > 128) | |
820 | return 0; /* DAC divider would be too big */ | |
821 | ||
822 | if (!(pllin_rate % dac_rate)) | |
823 | return dac_rate; | |
824 | ||
825 | dac_rate -= osr_rate; | |
826 | } | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
81249307 PR |
831 | static int pcm512x_set_dividers(struct snd_soc_dai *dai, |
832 | struct snd_pcm_hw_params *params) | |
833 | { | |
834 | struct device *dev = dai->dev; | |
835 | struct snd_soc_codec *codec = dai->codec; | |
836 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
f086ba9d PR |
837 | unsigned long pllin_rate = 0; |
838 | unsigned long pll_rate; | |
81249307 PR |
839 | unsigned long sck_rate; |
840 | unsigned long mck_rate; | |
841 | unsigned long bclk_rate; | |
842 | unsigned long sample_rate; | |
843 | unsigned long osr_rate; | |
7c4e1119 | 844 | unsigned long dacsrc_rate; |
81249307 PR |
845 | int bclk_div; |
846 | int lrclk_div; | |
847 | int dsp_div; | |
848 | int dac_div; | |
849 | unsigned long dac_rate; | |
850 | int ncp_div; | |
851 | int osr_div; | |
81249307 PR |
852 | int ret; |
853 | int idac; | |
854 | int fssp; | |
7c4e1119 | 855 | int gpio; |
81249307 PR |
856 | |
857 | lrclk_div = snd_soc_params_to_frame_size(params); | |
858 | if (lrclk_div == 0) { | |
859 | dev_err(dev, "No LRCLK?\n"); | |
860 | return -EINVAL; | |
861 | } | |
862 | ||
f086ba9d PR |
863 | if (!pcm512x->pll_out) { |
864 | sck_rate = clk_get_rate(pcm512x->sclk); | |
865 | bclk_div = params->rate_den * 64 / lrclk_div; | |
866 | bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div); | |
867 | ||
868 | mck_rate = sck_rate; | |
869 | } else { | |
870 | ret = snd_soc_params_to_bclk(params); | |
871 | if (ret < 0) { | |
872 | dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); | |
873 | return ret; | |
874 | } | |
875 | if (ret == 0) { | |
876 | dev_err(dev, "No BCLK?\n"); | |
877 | return -EINVAL; | |
878 | } | |
879 | bclk_rate = ret; | |
880 | ||
881 | pllin_rate = clk_get_rate(pcm512x->sclk); | |
882 | ||
883 | sck_rate = pcm512x_find_sck(dai, bclk_rate); | |
884 | if (!sck_rate) | |
885 | return -EINVAL; | |
886 | pll_rate = 4 * sck_rate; | |
887 | ||
888 | ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); | |
889 | if (ret != 0) | |
890 | return ret; | |
891 | ||
892 | ret = regmap_write(pcm512x->regmap, | |
893 | PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); | |
894 | if (ret != 0) { | |
895 | dev_err(dev, "Failed to write PLL P: %d\n", ret); | |
896 | return ret; | |
897 | } | |
898 | ||
899 | ret = regmap_write(pcm512x->regmap, | |
900 | PCM512x_PLL_COEFF_1, pcm512x->pll_j); | |
901 | if (ret != 0) { | |
902 | dev_err(dev, "Failed to write PLL J: %d\n", ret); | |
903 | return ret; | |
904 | } | |
905 | ||
906 | ret = regmap_write(pcm512x->regmap, | |
907 | PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); | |
908 | if (ret != 0) { | |
909 | dev_err(dev, "Failed to write PLL D msb: %d\n", ret); | |
910 | return ret; | |
911 | } | |
912 | ||
913 | ret = regmap_write(pcm512x->regmap, | |
914 | PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); | |
915 | if (ret != 0) { | |
916 | dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); | |
917 | return ret; | |
918 | } | |
919 | ||
920 | ret = regmap_write(pcm512x->regmap, | |
921 | PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); | |
922 | if (ret != 0) { | |
923 | dev_err(dev, "Failed to write PLL R: %d\n", ret); | |
924 | return ret; | |
925 | } | |
926 | ||
927 | mck_rate = pcm512x->real_pll; | |
81249307 | 928 | |
f086ba9d PR |
929 | bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); |
930 | } | |
81249307 PR |
931 | |
932 | if (bclk_div > 128) { | |
933 | dev_err(dev, "Failed to find BCLK divider\n"); | |
934 | return -EINVAL; | |
935 | } | |
936 | ||
937 | /* the actual rate */ | |
938 | sample_rate = sck_rate / bclk_div / lrclk_div; | |
939 | osr_rate = 16 * sample_rate; | |
940 | ||
941 | /* run DSP no faster than 50 MHz */ | |
f29933c9 | 942 | dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; |
81249307 | 943 | |
7c4e1119 PR |
944 | dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); |
945 | if (dac_rate) { | |
946 | /* the desired clock rate is "compatible" with the pll input | |
947 | * clock, so use that clock as dac input instead of the pll | |
948 | * output clock since the pll will introduce jitter and thus | |
949 | * noise. | |
950 | */ | |
951 | dev_dbg(dev, "using pll input as dac input\n"); | |
952 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, | |
953 | PCM512x_SDAC, PCM512x_SDAC_GPIO); | |
954 | if (ret != 0) { | |
955 | dev_err(codec->dev, | |
956 | "Failed to set gpio as dacref: %d\n", ret); | |
957 | return ret; | |
958 | } | |
81249307 | 959 | |
7c4e1119 PR |
960 | gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; |
961 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN, | |
962 | PCM512x_GREF, gpio); | |
963 | if (ret != 0) { | |
964 | dev_err(codec->dev, | |
965 | "Failed to set gpio %d as dacin: %d\n", | |
966 | pcm512x->pll_in, ret); | |
967 | return ret; | |
968 | } | |
969 | ||
970 | dacsrc_rate = pllin_rate; | |
971 | } else { | |
972 | /* run DAC no faster than 6144000 Hz */ | |
f29933c9 PR |
973 | unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000) |
974 | / osr_rate; | |
7c4e1119 PR |
975 | unsigned long sck_mul = sck_rate / osr_rate; |
976 | ||
977 | for (; dac_mul; dac_mul--) { | |
978 | if (!(sck_mul % dac_mul)) | |
979 | break; | |
980 | } | |
981 | if (!dac_mul) { | |
982 | dev_err(dev, "Failed to find DAC rate\n"); | |
983 | return -EINVAL; | |
984 | } | |
81249307 | 985 | |
7c4e1119 PR |
986 | dac_rate = dac_mul * osr_rate; |
987 | dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", | |
988 | dac_rate, sample_rate); | |
989 | ||
990 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, | |
991 | PCM512x_SDAC, PCM512x_SDAC_SCK); | |
992 | if (ret != 0) { | |
993 | dev_err(codec->dev, | |
994 | "Failed to set sck as dacref: %d\n", ret); | |
995 | return ret; | |
996 | } | |
997 | ||
998 | dacsrc_rate = sck_rate; | |
999 | } | |
1000 | ||
5890bd52 PR |
1001 | osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); |
1002 | if (osr_div > 128) { | |
1003 | dev_err(dev, "Failed to find OSR divider\n"); | |
1004 | return -EINVAL; | |
1005 | } | |
1006 | ||
7c4e1119 | 1007 | dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); |
81249307 PR |
1008 | if (dac_div > 128) { |
1009 | dev_err(dev, "Failed to find DAC divider\n"); | |
1010 | return -EINVAL; | |
1011 | } | |
5890bd52 | 1012 | dac_rate = dacsrc_rate / dac_div; |
81249307 | 1013 | |
f29933c9 PR |
1014 | ncp_div = DIV_ROUND_CLOSEST(dac_rate, |
1015 | pcm512x_ncp_target(pcm512x, dac_rate)); | |
5890bd52 | 1016 | if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { |
81249307 | 1017 | /* run NCP no faster than 2048000 Hz, but why? */ |
5890bd52 | 1018 | ncp_div = DIV_ROUND_UP(dac_rate, 2048000); |
81249307 PR |
1019 | if (ncp_div > 128) { |
1020 | dev_err(dev, "Failed to find NCP divider\n"); | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | } | |
1024 | ||
81249307 PR |
1025 | idac = mck_rate / (dsp_div * sample_rate); |
1026 | ||
1027 | ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1); | |
1028 | if (ret != 0) { | |
1029 | dev_err(dev, "Failed to write DSP divider: %d\n", ret); | |
1030 | return ret; | |
1031 | } | |
1032 | ||
1033 | ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1); | |
1034 | if (ret != 0) { | |
1035 | dev_err(dev, "Failed to write DAC divider: %d\n", ret); | |
1036 | return ret; | |
1037 | } | |
1038 | ||
1039 | ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1); | |
1040 | if (ret != 0) { | |
1041 | dev_err(dev, "Failed to write NCP divider: %d\n", ret); | |
1042 | return ret; | |
1043 | } | |
1044 | ||
1045 | ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1); | |
1046 | if (ret != 0) { | |
1047 | dev_err(dev, "Failed to write OSR divider: %d\n", ret); | |
1048 | return ret; | |
1049 | } | |
1050 | ||
1051 | ret = regmap_write(pcm512x->regmap, | |
1052 | PCM512x_MASTER_CLKDIV_1, bclk_div - 1); | |
1053 | if (ret != 0) { | |
1054 | dev_err(dev, "Failed to write BCLK divider: %d\n", ret); | |
1055 | return ret; | |
1056 | } | |
1057 | ||
1058 | ret = regmap_write(pcm512x->regmap, | |
1059 | PCM512x_MASTER_CLKDIV_2, lrclk_div - 1); | |
1060 | if (ret != 0) { | |
1061 | dev_err(dev, "Failed to write LRCLK divider: %d\n", ret); | |
1062 | return ret; | |
1063 | } | |
1064 | ||
1065 | ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8); | |
1066 | if (ret != 0) { | |
1067 | dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret); | |
1068 | return ret; | |
1069 | } | |
1070 | ||
1071 | ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff); | |
1072 | if (ret != 0) { | |
1073 | dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret); | |
1074 | return ret; | |
1075 | } | |
1076 | ||
f29933c9 | 1077 | if (sample_rate <= pcm512x_dac_max(pcm512x, 48000)) |
81249307 | 1078 | fssp = PCM512x_FSSP_48KHZ; |
f29933c9 | 1079 | else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000)) |
81249307 | 1080 | fssp = PCM512x_FSSP_96KHZ; |
f29933c9 | 1081 | else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000)) |
81249307 PR |
1082 | fssp = PCM512x_FSSP_192KHZ; |
1083 | else | |
1084 | fssp = PCM512x_FSSP_384KHZ; | |
1085 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE, | |
1086 | PCM512x_FSSP, fssp); | |
1087 | if (ret != 0) { | |
1088 | dev_err(codec->dev, "Failed to set fs speed: %d\n", ret); | |
1089 | return ret; | |
1090 | } | |
1091 | ||
1092 | dev_dbg(codec->dev, "DSP divider %d\n", dsp_div); | |
1093 | dev_dbg(codec->dev, "DAC divider %d\n", dac_div); | |
1094 | dev_dbg(codec->dev, "NCP divider %d\n", ncp_div); | |
1095 | dev_dbg(codec->dev, "OSR divider %d\n", osr_div); | |
1096 | dev_dbg(codec->dev, "BCK divider %d\n", bclk_div); | |
1097 | dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div); | |
1098 | dev_dbg(codec->dev, "IDAC %d\n", idac); | |
1099 | dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp); | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | static int pcm512x_hw_params(struct snd_pcm_substream *substream, | |
1105 | struct snd_pcm_hw_params *params, | |
1106 | struct snd_soc_dai *dai) | |
1107 | { | |
1108 | struct snd_soc_codec *codec = dai->codec; | |
1109 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
1110 | int alen; | |
f086ba9d | 1111 | int gpio; |
d11c2978 PR |
1112 | int clock_output; |
1113 | int master_mode; | |
81249307 PR |
1114 | int ret; |
1115 | ||
1116 | dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n", | |
1117 | params_rate(params), | |
1118 | params_channels(params)); | |
1119 | ||
0a3dcb50 | 1120 | switch (params_width(params)) { |
81249307 PR |
1121 | case 16: |
1122 | alen = PCM512x_ALEN_16; | |
1123 | break; | |
1124 | case 20: | |
1125 | alen = PCM512x_ALEN_20; | |
1126 | break; | |
1127 | case 24: | |
1128 | alen = PCM512x_ALEN_24; | |
1129 | break; | |
1130 | case 32: | |
1131 | alen = PCM512x_ALEN_32; | |
1132 | break; | |
1133 | default: | |
1134 | dev_err(codec->dev, "Bad frame size: %d\n", | |
0a3dcb50 | 1135 | params_width(params)); |
81249307 PR |
1136 | return -EINVAL; |
1137 | } | |
1138 | ||
1139 | switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1140 | case SND_SOC_DAIFMT_CBS_CFS: | |
1141 | ret = regmap_update_bits(pcm512x->regmap, | |
1142 | PCM512x_BCLK_LRCLK_CFG, | |
1143 | PCM512x_BCKP | |
1144 | | PCM512x_BCKO | PCM512x_LRKO, | |
1145 | 0); | |
1146 | if (ret != 0) { | |
1147 | dev_err(codec->dev, | |
1148 | "Failed to enable slave mode: %d\n", ret); | |
1149 | return ret; | |
1150 | } | |
1151 | ||
1152 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, | |
1153 | PCM512x_DCAS, 0); | |
1154 | if (ret != 0) { | |
1155 | dev_err(codec->dev, | |
1156 | "Failed to enable clock divider autoset: %d\n", | |
1157 | ret); | |
1158 | return ret; | |
1159 | } | |
1160 | return 0; | |
1161 | case SND_SOC_DAIFMT_CBM_CFM: | |
d11c2978 PR |
1162 | clock_output = PCM512x_BCKO | PCM512x_LRKO; |
1163 | master_mode = PCM512x_RLRK | PCM512x_RBCK; | |
1164 | break; | |
1165 | case SND_SOC_DAIFMT_CBM_CFS: | |
1166 | clock_output = PCM512x_BCKO; | |
1167 | master_mode = PCM512x_RBCK; | |
81249307 PR |
1168 | break; |
1169 | default: | |
1170 | return -EINVAL; | |
1171 | } | |
1172 | ||
1173 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, | |
1174 | PCM512x_ALEN, alen); | |
1175 | if (ret != 0) { | |
1176 | dev_err(codec->dev, "Failed to set frame size: %d\n", ret); | |
1177 | return ret; | |
1178 | } | |
1179 | ||
f086ba9d PR |
1180 | if (pcm512x->pll_out) { |
1181 | ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11); | |
1182 | if (ret != 0) { | |
1183 | dev_err(codec->dev, "Failed to set FLEX_A: %d\n", ret); | |
1184 | return ret; | |
1185 | } | |
81249307 | 1186 | |
f086ba9d PR |
1187 | ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff); |
1188 | if (ret != 0) { | |
1189 | dev_err(codec->dev, "Failed to set FLEX_B: %d\n", ret); | |
1190 | return ret; | |
1191 | } | |
1192 | ||
1193 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, | |
1194 | PCM512x_IDFS | PCM512x_IDBK | |
1195 | | PCM512x_IDSK | PCM512x_IDCH | |
1196 | | PCM512x_IDCM | PCM512x_DCAS | |
1197 | | PCM512x_IPLK, | |
1198 | PCM512x_IDFS | PCM512x_IDBK | |
1199 | | PCM512x_IDSK | PCM512x_IDCH | |
1200 | | PCM512x_DCAS); | |
1201 | if (ret != 0) { | |
1202 | dev_err(codec->dev, | |
1203 | "Failed to ignore auto-clock failures: %d\n", | |
1204 | ret); | |
1205 | return ret; | |
1206 | } | |
1207 | } else { | |
1208 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, | |
1209 | PCM512x_IDFS | PCM512x_IDBK | |
1210 | | PCM512x_IDSK | PCM512x_IDCH | |
1211 | | PCM512x_IDCM | PCM512x_DCAS | |
1212 | | PCM512x_IPLK, | |
1213 | PCM512x_IDFS | PCM512x_IDBK | |
1214 | | PCM512x_IDSK | PCM512x_IDCH | |
1215 | | PCM512x_DCAS | PCM512x_IPLK); | |
1216 | if (ret != 0) { | |
1217 | dev_err(codec->dev, | |
1218 | "Failed to ignore auto-clock failures: %d\n", | |
1219 | ret); | |
1220 | return ret; | |
1221 | } | |
1222 | ||
1223 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, | |
1224 | PCM512x_PLLE, 0); | |
1225 | if (ret != 0) { | |
1226 | dev_err(codec->dev, "Failed to disable pll: %d\n", ret); | |
1227 | return ret; | |
1228 | } | |
81249307 PR |
1229 | } |
1230 | ||
1231 | ret = pcm512x_set_dividers(dai, params); | |
1232 | if (ret != 0) | |
1233 | return ret; | |
1234 | ||
f086ba9d PR |
1235 | if (pcm512x->pll_out) { |
1236 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF, | |
1237 | PCM512x_SREF, PCM512x_SREF_GPIO); | |
1238 | if (ret != 0) { | |
1239 | dev_err(codec->dev, | |
1240 | "Failed to set gpio as pllref: %d\n", ret); | |
1241 | return ret; | |
1242 | } | |
1243 | ||
1244 | gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; | |
1245 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN, | |
1246 | PCM512x_GREF, gpio); | |
1247 | if (ret != 0) { | |
1248 | dev_err(codec->dev, | |
1249 | "Failed to set gpio %d as pllin: %d\n", | |
1250 | pcm512x->pll_in, ret); | |
1251 | return ret; | |
1252 | } | |
1253 | ||
1254 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, | |
1255 | PCM512x_PLLE, PCM512x_PLLE); | |
1256 | if (ret != 0) { | |
1257 | dev_err(codec->dev, "Failed to enable pll: %d\n", ret); | |
1258 | return ret; | |
1259 | } | |
1260 | } | |
1261 | ||
81249307 PR |
1262 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, |
1263 | PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, | |
d11c2978 | 1264 | clock_output); |
81249307 PR |
1265 | if (ret != 0) { |
1266 | dev_err(codec->dev, "Failed to enable clock output: %d\n", ret); | |
1267 | return ret; | |
1268 | } | |
1269 | ||
1270 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE, | |
1271 | PCM512x_RLRK | PCM512x_RBCK, | |
d11c2978 | 1272 | master_mode); |
81249307 PR |
1273 | if (ret != 0) { |
1274 | dev_err(codec->dev, "Failed to enable master mode: %d\n", ret); | |
1275 | return ret; | |
1276 | } | |
1277 | ||
f086ba9d PR |
1278 | if (pcm512x->pll_out) { |
1279 | gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); | |
1280 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, | |
1281 | gpio, gpio); | |
1282 | if (ret != 0) { | |
1283 | dev_err(codec->dev, "Failed to enable gpio %d: %d\n", | |
1284 | pcm512x->pll_out, ret); | |
1285 | return ret; | |
1286 | } | |
1287 | ||
1288 | gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; | |
1289 | ret = regmap_update_bits(pcm512x->regmap, gpio, | |
1290 | PCM512x_GxSL, PCM512x_GxSL_PLLCK); | |
1291 | if (ret != 0) { | |
1292 | dev_err(codec->dev, "Failed to output pll on %d: %d\n", | |
1293 | ret, pcm512x->pll_out); | |
1294 | return ret; | |
1295 | } | |
f086ba9d PR |
1296 | } |
1297 | ||
81249307 PR |
1298 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, |
1299 | PCM512x_RQSY, PCM512x_RQSY_HALT); | |
1300 | if (ret != 0) { | |
1301 | dev_err(codec->dev, "Failed to halt clocks: %d\n", ret); | |
1302 | return ret; | |
1303 | } | |
1304 | ||
1305 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, | |
1306 | PCM512x_RQSY, PCM512x_RQSY_RESUME); | |
1307 | if (ret != 0) { | |
1308 | dev_err(codec->dev, "Failed to resume clocks: %d\n", ret); | |
1309 | return ret; | |
1310 | } | |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | ||
1315 | static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1316 | { | |
1317 | struct snd_soc_codec *codec = dai->codec; | |
1318 | struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); | |
1319 | ||
1320 | pcm512x->fmt = fmt; | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
1325 | static const struct snd_soc_dai_ops pcm512x_dai_ops = { | |
1326 | .startup = pcm512x_dai_startup, | |
1327 | .hw_params = pcm512x_hw_params, | |
1328 | .set_fmt = pcm512x_set_fmt, | |
1329 | }; | |
1330 | ||
5a3af129 MB |
1331 | static struct snd_soc_dai_driver pcm512x_dai = { |
1332 | .name = "pcm512x-hifi", | |
1333 | .playback = { | |
1334 | .stream_name = "Playback", | |
1335 | .channels_min = 2, | |
1336 | .channels_max = 2, | |
81249307 PR |
1337 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
1338 | .rate_min = 8000, | |
1339 | .rate_max = 384000, | |
5a3af129 MB |
1340 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
1341 | SNDRV_PCM_FMTBIT_S24_LE | | |
1342 | SNDRV_PCM_FMTBIT_S32_LE | |
1343 | }, | |
81249307 | 1344 | .ops = &pcm512x_dai_ops, |
5a3af129 MB |
1345 | }; |
1346 | ||
a180ba45 | 1347 | static const struct snd_soc_codec_driver pcm512x_codec_driver = { |
5a3af129 MB |
1348 | .set_bias_level = pcm512x_set_bias_level, |
1349 | .idle_bias_off = true, | |
1350 | ||
d25f113f KM |
1351 | .component_driver = { |
1352 | .controls = pcm512x_controls, | |
1353 | .num_controls = ARRAY_SIZE(pcm512x_controls), | |
1354 | .dapm_widgets = pcm512x_dapm_widgets, | |
1355 | .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets), | |
1356 | .dapm_routes = pcm512x_dapm_routes, | |
1357 | .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes), | |
1358 | }, | |
5a3af129 MB |
1359 | }; |
1360 | ||
806d6466 MB |
1361 | static const struct regmap_range_cfg pcm512x_range = { |
1362 | .name = "Pages", .range_min = PCM512x_VIRT_BASE, | |
1363 | .range_max = PCM512x_MAX_REGISTER, | |
1364 | .selector_reg = PCM512x_PAGE, | |
1365 | .selector_mask = 0xff, | |
1366 | .window_start = 0, .window_len = 0x100, | |
1367 | }; | |
1368 | ||
22066226 | 1369 | const struct regmap_config pcm512x_regmap = { |
5a3af129 MB |
1370 | .reg_bits = 8, |
1371 | .val_bits = 8, | |
1372 | ||
1373 | .readable_reg = pcm512x_readable, | |
1374 | .volatile_reg = pcm512x_volatile, | |
1375 | ||
806d6466 MB |
1376 | .ranges = &pcm512x_range, |
1377 | .num_ranges = 1, | |
1378 | ||
5a3af129 MB |
1379 | .max_register = PCM512x_MAX_REGISTER, |
1380 | .reg_defaults = pcm512x_reg_defaults, | |
1381 | .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults), | |
1382 | .cache_type = REGCACHE_RBTREE, | |
1383 | }; | |
22066226 | 1384 | EXPORT_SYMBOL_GPL(pcm512x_regmap); |
5a3af129 | 1385 | |
22066226 | 1386 | int pcm512x_probe(struct device *dev, struct regmap *regmap) |
5a3af129 MB |
1387 | { |
1388 | struct pcm512x_priv *pcm512x; | |
1389 | int i, ret; | |
1390 | ||
1391 | pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL); | |
1392 | if (!pcm512x) | |
1393 | return -ENOMEM; | |
1394 | ||
1395 | dev_set_drvdata(dev, pcm512x); | |
1396 | pcm512x->regmap = regmap; | |
1397 | ||
1398 | for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) | |
1399 | pcm512x->supplies[i].supply = pcm512x_supply_names[i]; | |
1400 | ||
1401 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies), | |
1402 | pcm512x->supplies); | |
1403 | if (ret != 0) { | |
1404 | dev_err(dev, "Failed to get supplies: %d\n", ret); | |
1405 | return ret; | |
1406 | } | |
1407 | ||
1408 | pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0; | |
1409 | pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1; | |
1410 | pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2; | |
1411 | ||
1412 | for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) { | |
1413 | ret = regulator_register_notifier(pcm512x->supplies[i].consumer, | |
1414 | &pcm512x->supply_nb[i]); | |
1415 | if (ret != 0) { | |
1416 | dev_err(dev, | |
1417 | "Failed to register regulator notifier: %d\n", | |
1418 | ret); | |
1419 | } | |
1420 | } | |
1421 | ||
1422 | ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), | |
1423 | pcm512x->supplies); | |
1424 | if (ret != 0) { | |
1425 | dev_err(dev, "Failed to enable supplies: %d\n", ret); | |
1426 | return ret; | |
1427 | } | |
1428 | ||
1429 | /* Reset the device, verifying I/O in the process for I2C */ | |
1430 | ret = regmap_write(regmap, PCM512x_RESET, | |
1431 | PCM512x_RSTM | PCM512x_RSTR); | |
1432 | if (ret != 0) { | |
1433 | dev_err(dev, "Failed to reset device: %d\n", ret); | |
1434 | goto err; | |
1435 | } | |
1436 | ||
1437 | ret = regmap_write(regmap, PCM512x_RESET, 0); | |
1438 | if (ret != 0) { | |
1439 | dev_err(dev, "Failed to reset device: %d\n", ret); | |
1440 | goto err; | |
1441 | } | |
1442 | ||
1443 | pcm512x->sclk = devm_clk_get(dev, NULL); | |
81249307 PR |
1444 | if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) |
1445 | return -EPROBE_DEFER; | |
1446 | if (!IS_ERR(pcm512x->sclk)) { | |
5a3af129 MB |
1447 | ret = clk_prepare_enable(pcm512x->sclk); |
1448 | if (ret != 0) { | |
1449 | dev_err(dev, "Failed to enable SCLK: %d\n", ret); | |
1450 | return ret; | |
1451 | } | |
1452 | } | |
1453 | ||
1454 | /* Default to standby mode */ | |
1455 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
1456 | PCM512x_RQST, PCM512x_RQST); | |
1457 | if (ret != 0) { | |
1458 | dev_err(dev, "Failed to request standby: %d\n", | |
1459 | ret); | |
1460 | goto err_clk; | |
1461 | } | |
1462 | ||
1463 | pm_runtime_set_active(dev); | |
1464 | pm_runtime_enable(dev); | |
1465 | pm_runtime_idle(dev); | |
1466 | ||
f086ba9d PR |
1467 | #ifdef CONFIG_OF |
1468 | if (dev->of_node) { | |
1469 | const struct device_node *np = dev->of_node; | |
2599a960 | 1470 | u32 val; |
f086ba9d PR |
1471 | |
1472 | if (of_property_read_u32(np, "pll-in", &val) >= 0) { | |
1473 | if (val > 6) { | |
1474 | dev_err(dev, "Invalid pll-in\n"); | |
1475 | ret = -EINVAL; | |
1476 | goto err_clk; | |
1477 | } | |
1478 | pcm512x->pll_in = val; | |
1479 | } | |
1480 | ||
1481 | if (of_property_read_u32(np, "pll-out", &val) >= 0) { | |
1482 | if (val > 6) { | |
1483 | dev_err(dev, "Invalid pll-out\n"); | |
1484 | ret = -EINVAL; | |
1485 | goto err_clk; | |
1486 | } | |
1487 | pcm512x->pll_out = val; | |
1488 | } | |
1489 | ||
1490 | if (!pcm512x->pll_in != !pcm512x->pll_out) { | |
1491 | dev_err(dev, | |
1492 | "Error: both pll-in and pll-out, or none\n"); | |
1493 | ret = -EINVAL; | |
1494 | goto err_clk; | |
1495 | } | |
1496 | if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { | |
1497 | dev_err(dev, "Error: pll-in == pll-out\n"); | |
1498 | ret = -EINVAL; | |
1499 | goto err_clk; | |
1500 | } | |
1501 | } | |
1502 | #endif | |
1503 | ||
5a3af129 MB |
1504 | ret = snd_soc_register_codec(dev, &pcm512x_codec_driver, |
1505 | &pcm512x_dai, 1); | |
1506 | if (ret != 0) { | |
1507 | dev_err(dev, "Failed to register CODEC: %d\n", ret); | |
1508 | goto err_pm; | |
1509 | } | |
1510 | ||
1511 | return 0; | |
1512 | ||
1513 | err_pm: | |
1514 | pm_runtime_disable(dev); | |
1515 | err_clk: | |
1516 | if (!IS_ERR(pcm512x->sclk)) | |
1517 | clk_disable_unprepare(pcm512x->sclk); | |
1518 | err: | |
1519 | regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), | |
1520 | pcm512x->supplies); | |
1521 | return ret; | |
1522 | } | |
22066226 | 1523 | EXPORT_SYMBOL_GPL(pcm512x_probe); |
5a3af129 | 1524 | |
22066226 | 1525 | void pcm512x_remove(struct device *dev) |
5a3af129 MB |
1526 | { |
1527 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); | |
1528 | ||
1529 | snd_soc_unregister_codec(dev); | |
1530 | pm_runtime_disable(dev); | |
1531 | if (!IS_ERR(pcm512x->sclk)) | |
1532 | clk_disable_unprepare(pcm512x->sclk); | |
1533 | regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), | |
1534 | pcm512x->supplies); | |
1535 | } | |
22066226 | 1536 | EXPORT_SYMBOL_GPL(pcm512x_remove); |
5a3af129 | 1537 | |
641d334b | 1538 | #ifdef CONFIG_PM |
5a3af129 MB |
1539 | static int pcm512x_suspend(struct device *dev) |
1540 | { | |
1541 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); | |
1542 | int ret; | |
1543 | ||
1544 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
1545 | PCM512x_RQPD, PCM512x_RQPD); | |
1546 | if (ret != 0) { | |
1547 | dev_err(dev, "Failed to request power down: %d\n", ret); | |
1548 | return ret; | |
1549 | } | |
1550 | ||
1551 | ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), | |
1552 | pcm512x->supplies); | |
1553 | if (ret != 0) { | |
1554 | dev_err(dev, "Failed to disable supplies: %d\n", ret); | |
1555 | return ret; | |
1556 | } | |
1557 | ||
1558 | if (!IS_ERR(pcm512x->sclk)) | |
1559 | clk_disable_unprepare(pcm512x->sclk); | |
1560 | ||
1561 | return 0; | |
1562 | } | |
1563 | ||
1564 | static int pcm512x_resume(struct device *dev) | |
1565 | { | |
1566 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); | |
1567 | int ret; | |
1568 | ||
1569 | if (!IS_ERR(pcm512x->sclk)) { | |
1570 | ret = clk_prepare_enable(pcm512x->sclk); | |
1571 | if (ret != 0) { | |
1572 | dev_err(dev, "Failed to enable SCLK: %d\n", ret); | |
1573 | return ret; | |
1574 | } | |
1575 | } | |
1576 | ||
1577 | ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), | |
1578 | pcm512x->supplies); | |
1579 | if (ret != 0) { | |
1580 | dev_err(dev, "Failed to enable supplies: %d\n", ret); | |
1581 | return ret; | |
1582 | } | |
1583 | ||
1584 | regcache_cache_only(pcm512x->regmap, false); | |
1585 | ret = regcache_sync(pcm512x->regmap); | |
1586 | if (ret != 0) { | |
1587 | dev_err(dev, "Failed to sync cache: %d\n", ret); | |
1588 | return ret; | |
1589 | } | |
1590 | ||
1591 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
1592 | PCM512x_RQPD, 0); | |
1593 | if (ret != 0) { | |
1594 | dev_err(dev, "Failed to remove power down: %d\n", ret); | |
1595 | return ret; | |
1596 | } | |
1597 | ||
1598 | return 0; | |
1599 | } | |
ccffbd27 | 1600 | #endif |
5a3af129 | 1601 | |
22066226 | 1602 | const struct dev_pm_ops pcm512x_pm_ops = { |
5a3af129 MB |
1603 | SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) |
1604 | }; | |
22066226 | 1605 | EXPORT_SYMBOL_GPL(pcm512x_pm_ops); |
5a3af129 MB |
1606 | |
1607 | MODULE_DESCRIPTION("ASoC PCM512x codec driver"); | |
1608 | MODULE_AUTHOR("Mark Brown <broonie@linaro.org>"); | |
1609 | MODULE_LICENSE("GPL v2"); |