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d8085222 | 1 | #ifndef __RTCODEC5631_H__ |
2 | #define __RTCODEC5631_H__ | |
3 | ||
4 | ||
5 | #define RT5631_RESET 0x00 | |
6 | #define RT5631_SPK_OUT_VOL 0x02 | |
7 | #define RT5631_HP_OUT_VOL 0x04 | |
8 | #define RT5631_MONO_AXO_1_2_VOL 0x06 | |
9 | #define RT5631_AUX_IN_VOL 0x0A | |
10 | #define RT5631_STEREO_DAC_VOL_1 0x0C | |
11 | #define RT5631_MIC_CTRL_1 0x0E | |
12 | #define RT5631_STEREO_DAC_VOL_2 0x10 | |
13 | #define RT5631_ADC_CTRL_1 0x12 | |
14 | #define RT5631_ADC_REC_MIXER 0x14 | |
15 | #define RT5631_ADC_CTRL_2 0x16 | |
16 | #define RT5631_VDAC_DIG_VOL 0x18 | |
17 | #define RT5631_OUTMIXER_L_CTRL 0x1A | |
18 | #define RT5631_OUTMIXER_R_CTRL 0x1C | |
19 | #define RT5631_AXO1MIXER_CTRL 0x1E | |
20 | #define RT5631_AXO2MIXER_CTRL 0x20 | |
21 | #define RT5631_MIC_CTRL_2 0x22 | |
22 | #define RT5631_DIG_MIC_CTRL 0x24 | |
23 | #define RT5631_MONO_INPUT_VOL 0x26 | |
24 | #define RT5631_SPK_MIXER_CTRL 0x28 | |
25 | #define RT5631_SPK_MONO_OUT_CTRL 0x2A | |
26 | #define RT5631_SPK_MONO_HP_OUT_CTRL 0x2C | |
27 | #define RT5631_SDP_CTRL 0x34 | |
28 | #define RT5631_MONO_SDP_CTRL 0x36 | |
29 | #define RT5631_STEREO_AD_DA_CLK_CTRL 0x38 | |
30 | #define RT5631_PWR_MANAG_ADD1 0x3A | |
31 | #define RT5631_PWR_MANAG_ADD2 0x3B | |
32 | #define RT5631_PWR_MANAG_ADD3 0x3C | |
33 | #define RT5631_PWR_MANAG_ADD4 0x3E | |
34 | #define RT5631_GEN_PUR_CTRL_REG 0x40 | |
35 | #define RT5631_GLOBAL_CLK_CTRL 0x42 | |
36 | #define RT5631_PLL_CTRL 0x44 | |
37 | #define RT5631_INT_ST_IRQ_CTRL_1 0x48 | |
38 | #define RT5631_INT_ST_IRQ_CTRL_2 0x4A | |
39 | #define RT5631_GPIO_CTRL 0x4C | |
40 | #define RT5631_MISC_CTRL 0x52 | |
41 | #define RT5631_DEPOP_FUN_CTRL_1 0x54 | |
42 | #define RT5631_DEPOP_FUN_CTRL_2 0x56 | |
43 | #define RT5631_JACK_DET_CTRL 0x5A | |
44 | #define RT5631_SOFT_VOL_CTRL 0x5C | |
45 | #define RT5631_ALC_CTRL_1 0x64 | |
46 | #define RT5631_ALC_CTRL_2 0x65 | |
47 | #define RT5631_ALC_CTRL_3 0x66 | |
48 | #define RT5631_PSEUDO_SPATL_CTRL 0x68 | |
49 | #define RT5631_INDEX_ADD 0x6A | |
50 | #define RT5631_INDEX_DATA 0x6C | |
51 | #define RT5631_EQ_CTRL 0x6E | |
52 | #define RT5631_VENDOR_ID 0x7A | |
53 | #define RT5631_VENDOR_ID1 0x7C | |
54 | #define RT5631_VENDOR_ID2 0x7E | |
55 | ||
56 | /* Index of Codec Private Register definition */ | |
57 | #define RT5631_EQ_BW_LOP 0x00 | |
58 | #define RT5631_EQ_GAIN_LOP 0x01 | |
59 | #define RT5631_EQ_FC_BP1 0x02 | |
60 | #define RT5631_EQ_BW_BP1 0x03 | |
61 | #define RT5631_EQ_GAIN_BP1 0x04 | |
62 | #define RT5631_EQ_FC_BP2 0x05 | |
63 | #define RT5631_EQ_BW_BP2 0x06 | |
64 | #define RT5631_EQ_GAIN_BP2 0x07 | |
65 | #define RT5631_EQ_FC_BP3 0x08 | |
66 | #define RT5631_EQ_BW_BP3 0x09 | |
67 | #define RT5631_EQ_GAIN_BP3 0x0a | |
68 | #define RT5631_EQ_BW_HIP 0x0b | |
69 | #define RT5631_EQ_GAIN_HIP 0x0c | |
70 | #define RT5631_EQ_HPF_A1 0x0d | |
71 | #define RT5631_EQ_HPF_A2 0x0e | |
72 | #define RT5631_EQ_HPF_GAIN 0x0f | |
73 | #define RT5631_EQ_PRE_VOL_CTRL 0x11 | |
74 | #define RT5631_EQ_POST_VOL_CTRL 0x12 | |
75 | #define RT5631_TEST_MODE_CTRL 0x39 | |
76 | #define RT5631_CP_INTL_REG2 0x45 | |
77 | #define RT5631_ADDA_MIXER_INTL_REG3 0x52 | |
78 | #define RT5631_SPK_INTL_CTRL 0x56 | |
79 | ||
80 | ||
81 | /* global definition */ | |
82 | #define RT5631_L_MUTE (0x1 << 15) | |
83 | #define RT5631_L_MUTE_SHIFT 15 | |
84 | #define RT5631_L_EN (0x1 << 14) | |
85 | #define RT5631_L_EN_SHIFT 14 | |
86 | #define RT5631_R_MUTE (0x1 << 7) | |
87 | #define RT5631_R_MUTE_SHIFT 7 | |
88 | #define RT5631_R_EN (0x1 << 6) | |
89 | #define RT5631_R_EN_SHIFT 6 | |
90 | #define RT5631_VOL_MASK 0x1f | |
91 | #define RT5631_L_VOL_SHIFT 8 | |
92 | #define RT5631_R_VOL_SHIFT 0 | |
93 | ||
94 | /* Speaker Output Control(0x02) */ | |
95 | #define RT5631_SPK_L_VOL_SEL_MASK (0x1 << 14) | |
96 | #define RT5631_SPK_L_VOL_SEL_VMID (0x0 << 14) | |
97 | #define RT5631_SPK_L_VOL_SEL_SPKMIX_L (0x1 << 14) | |
98 | #define RT5631_SPK_R_VOL_SEL_MASK (0x1 << 6) | |
99 | #define RT5631_SPK_R_VOL_SEL_VMID (0x0 << 6) | |
100 | #define RT5631_SPK_R_VOL_SEL_SPKMIX_R (0x1 << 6) | |
101 | ||
102 | /* Headphone Output Control(0x04) */ | |
103 | #define RT5631_HP_L_VOL_SEL_MASK (0x1 << 14) | |
104 | #define RT5631_HP_L_VOL_SEL_VMID (0x0 << 14) | |
105 | #define RT5631_HP_L_VOL_SEL_OUTMIX_L (0x1 << 14) | |
106 | #define RT5631_HP_R_VOL_SEL_MASK (0x1 << 6) | |
107 | #define RT5631_HP_R_VOL_SEL_VMID (0x0 << 6) | |
108 | #define RT5631_HP_R_VOL_SEL_OUTMIX_R (0x1 << 6) | |
109 | ||
110 | /* Output Control for AUXOUT/MONO(0x06) */ | |
111 | #define RT5631_AUXOUT_1_VOL_SEL_MASK (0x1 << 14) | |
112 | #define RT5631_AUXOUT_1_VOL_SEL_VMID (0x0 << 14) | |
113 | #define RT5631_AUXOUT_1_VOL_SEL_OUTMIX_L (0x1 << 14) | |
114 | #define RT5631_MUTE_MONO (0x1 << 13) | |
115 | #define RT5631_MUTE_MONO_SHIFT 13 | |
116 | #define RT5631_AUXOUT_2_VOL_SEL_MASK (0x1 << 6) | |
117 | #define RT5631_AUXOUT_2_VOL_SEL_VMID (0x0 << 6) | |
118 | #define RT5631_AUXOUT_2_VOL_SEL_OUTMIX_R (0x1 << 6) | |
119 | ||
120 | /* Microphone Input Control 1(0x0E) */ | |
121 | #define RT5631_MIC1_DIFF_INPUT_CTRL (0x1 << 15) | |
122 | #define RT5631_MIC1_DIFF_INPUT_SHIFT 15 | |
123 | #define RT5631_MIC2_DIFF_INPUT_CTRL (0x1 << 7) | |
124 | #define RT5631_MIC2_DIFF_INPUT_SHIFT 7 | |
125 | ||
126 | /* Stereo DAC Digital Volume2(0x10) */ | |
127 | #define RT5631_DAC_VOL_MASK 0xff | |
128 | ||
129 | /* ADC Recording Mixer Control(0x14) */ | |
130 | #define RT5631_M_OUTMIXER_L_TO_RECMIXER_L (0x1 << 15) | |
131 | #define RT5631_M_OUTMIXL_RECMIXL_BIT 15 | |
132 | #define RT5631_M_MIC1_TO_RECMIXER_L (0x1 << 14) | |
133 | #define RT5631_M_MIC1_RECMIXL_BIT 14 | |
134 | #define RT5631_M_AXIL_TO_RECMIXER_L (0x1 << 13) | |
135 | #define RT5631_M_AXIL_RECMIXL_BIT 13 | |
136 | #define RT5631_M_MONO_IN_TO_RECMIXER_L (0x1 << 12) | |
137 | #define RT5631_M_MONO_IN_RECMIXL_BIT 12 | |
138 | #define RT5631_M_OUTMIXER_R_TO_RECMIXER_R (0x1 << 7) | |
139 | #define RT5631_M_OUTMIXR_RECMIXR_BIT 7 | |
140 | #define RT5631_M_MIC2_TO_RECMIXER_R (0x1 << 6) | |
141 | #define RT5631_M_MIC2_RECMIXR_BIT 6 | |
142 | #define RT5631_M_AXIR_TO_RECMIXER_R (0x1 << 5) | |
143 | #define RT5631_M_AXIR_RECMIXR_BIT 5 | |
144 | #define RT5631_M_MONO_IN_TO_RECMIXER_R (0x1 << 4) | |
145 | #define RT5631_M_MONO_IN_RECMIXR_BIT 4 | |
146 | ||
147 | /* Left Output Mixer Control(0x1A) */ | |
148 | #define RT5631_M_RECMIXER_L_TO_OUTMIXER_L (0x1 << 15) | |
149 | #define RT5631_M_RECMIXL_OUTMIXL_BIT 15 | |
150 | #define RT5631_M_RECMIXER_R_TO_OUTMIXER_L (0x1 << 14) | |
151 | #define RT5631_M_RECMIXR_OUTMIXL_BIT 14 | |
152 | #define RT5631_M_DAC_L_TO_OUTMIXER_L (0x1 << 13) | |
153 | #define RT5631_M_DACL_OUTMIXL_BIT 13 | |
154 | #define RT5631_M_MIC1_TO_OUTMIXER_L (0x1 << 12) | |
155 | #define RT5631_M_MIC1_OUTMIXL_BIT 12 | |
156 | #define RT5631_M_MIC2_TO_OUTMIXER_L (0x1 << 11) | |
157 | #define RT5631_M_MIC2_OUTMIXL_BIT 11 | |
158 | #define RT5631_M_MONO_IN_P_TO_OUTMIXER_L (0x1 << 10) | |
159 | #define RT5631_M_MONO_INP_OUTMIXL_BIT 10 | |
160 | #define RT5631_M_AXIL_TO_OUTMIXER_L (0x1 << 9) | |
161 | #define RT5631_M_AXIL_OUTMIXL_BIT 9 | |
162 | #define RT5631_M_AXIR_TO_OUTMIXER_L (0x1 << 8) | |
163 | #define RT5631_M_AXIR_OUTMIXL_BIT 8 | |
164 | #define RT5631_M_VDAC_TO_OUTMIXER_L (0x1 << 7) | |
165 | #define RT5631_M_VDAC_OUTMIXL_BIT 7 | |
166 | ||
167 | /* Right Output Mixer Control(0x1C) */ | |
168 | #define RT5631_M_RECMIXER_L_TO_OUTMIXER_R (0x1 << 15) | |
169 | #define RT5631_M_RECMIXL_OUTMIXR_BIT 15 | |
170 | #define RT5631_M_RECMIXER_R_TO_OUTMIXER_R (0x1 << 14) | |
171 | #define RT5631_M_RECMIXR_OUTMIXR_BIT 14 | |
172 | #define RT5631_M_DAC_R_TO_OUTMIXER_R (0x1 << 13) | |
173 | #define RT5631_M_DACR_OUTMIXR_BIT 13 | |
174 | #define RT5631_M_MIC1_TO_OUTMIXER_R (0x1 << 12) | |
175 | #define RT5631_M_MIC1_OUTMIXR_BIT 12 | |
176 | #define RT5631_M_MIC2_TO_OUTMIXER_R (0x1 << 11) | |
177 | #define RT5631_M_MIC2_OUTMIXR_BIT 11 | |
178 | #define RT5631_M_MONO_IN_N_TO_OUTMIXER_R (0x1 << 10) | |
179 | #define RT5631_M_MONO_INN_OUTMIXR_BIT 10 | |
180 | #define RT5631_M_AXIL_TO_OUTMIXER_R (0x1 << 9) | |
181 | #define RT5631_M_AXIL_OUTMIXR_BIT 9 | |
182 | #define RT5631_M_AXIR_TO_OUTMIXER_R (0x1 << 8) | |
183 | #define RT5631_M_AXIR_OUTMIXR_BIT 8 | |
184 | #define RT5631_M_VDAC_TO_OUTMIXER_R (0x1 << 7) | |
185 | #define RT5631_M_VDAC_OUTMIXR_BIT 7 | |
186 | ||
187 | /* Lout Mixer Control(0x1E) */ | |
188 | #define RT5631_M_MIC1_TO_AXO1MIXER (0x1 << 15) | |
189 | #define RT5631_M_MIC1_AXO1MIX_BIT 15 | |
190 | #define RT5631_M_MIC2_TO_AXO1MIXER (0x1 << 11) | |
191 | #define RT5631_M_MIC2_AXO1MIX_BIT 11 | |
192 | #define RT5631_M_OUTMIXER_L_TO_AXO1MIXER (0x1 << 7) | |
193 | #define RT5631_M_OUTMIXL_AXO1MIX_BIT 7 | |
194 | #define RT5631_M_OUTMIXER_R_TO_AXO1MIXER (0x1 << 6) | |
195 | #define RT5631_M_OUTMIXR_AXO1MIX_BIT 6 | |
196 | ||
197 | /* Rout Mixer Control(0x20) */ | |
198 | #define RT5631_M_MIC1_TO_AXO2MIXER (0x1 << 15) | |
199 | #define RT5631_M_MIC1_AXO2MIX_BIT 15 | |
200 | #define RT5631_M_MIC2_TO_AXO2MIXER (0x1 << 11) | |
201 | #define RT5631_M_MIC2_AXO2MIX_BIT 11 | |
202 | #define RT5631_M_OUTMIXER_L_TO_AXO2MIXER (0x1 << 7) | |
203 | #define RT5631_M_OUTMIXL_AXO2MIX_BIT 7 | |
204 | #define RT5631_M_OUTMIXER_R_TO_AXO2MIXER (0x1 << 6) | |
205 | #define RT5631_M_OUTMIXR_AXO2MIX_BIT 6 | |
206 | ||
207 | /* Micphone Input Control 2(0x22) */ | |
208 | #define RT5631_MIC_BIAS_90_PRECNET_AVDD 1 | |
209 | #define RT5631_MIC_BIAS_75_PRECNET_AVDD 2 | |
210 | ||
211 | #define RT5631_MIC1_BOOST_CTRL_MASK (0xf << 12) | |
212 | #define RT5631_MIC1_BOOST_CTRL_BYPASS (0x0 << 12) | |
213 | #define RT5631_MIC1_BOOST_CTRL_20DB (0x1 << 12) | |
214 | #define RT5631_MIC1_BOOST_CTRL_24DB (0x2 << 12) | |
215 | #define RT5631_MIC1_BOOST_CTRL_30DB (0x3 << 12) | |
216 | #define RT5631_MIC1_BOOST_CTRL_35DB (0x4 << 12) | |
217 | #define RT5631_MIC1_BOOST_CTRL_40DB (0x5 << 12) | |
218 | #define RT5631_MIC1_BOOST_CTRL_34DB (0x6 << 12) | |
219 | #define RT5631_MIC1_BOOST_CTRL_50DB (0x7 << 12) | |
220 | #define RT5631_MIC1_BOOST_CTRL_52DB (0x8 << 12) | |
221 | #define RT5631_MIC1_BOOST_SHIFT 12 | |
222 | ||
223 | #define RT5631_MIC2_BOOST_CTRL_MASK (0xf << 8) | |
224 | #define RT5631_MIC2_BOOST_CTRL_BYPASS (0x0 << 8) | |
225 | #define RT5631_MIC2_BOOST_CTRL_20DB (0x1 << 8) | |
226 | #define RT5631_MIC2_BOOST_CTRL_24DB (0x2 << 8) | |
227 | #define RT5631_MIC2_BOOST_CTRL_30DB (0x3 << 8) | |
228 | #define RT5631_MIC2_BOOST_CTRL_35DB (0x4 << 8) | |
229 | #define RT5631_MIC2_BOOST_CTRL_40DB (0x5 << 8) | |
230 | #define RT5631_MIC2_BOOST_CTRL_34DB (0x6 << 8) | |
231 | #define RT5631_MIC2_BOOST_CTRL_50DB (0x7 << 8) | |
232 | #define RT5631_MIC2_BOOST_CTRL_52DB (0x8 << 8) | |
233 | #define RT5631_MIC2_BOOST_SHIFT 8 | |
234 | ||
235 | #define RT5631_MICBIAS1_VOLT_CTRL_MASK (0x1 << 7) | |
236 | #define RT5631_MICBIAS1_VOLT_CTRL_90P (0x0 << 7) | |
237 | #define RT5631_MICBIAS1_VOLT_CTRL_75P (0x1 << 7) | |
238 | ||
239 | #define RT5631_MICBIAS1_S_C_DET_MASK (0x1 << 6) | |
240 | #define RT5631_MICBIAS1_S_C_DET_DIS (0x0 << 6) | |
241 | #define RT5631_MICBIAS1_S_C_DET_ENA (0x1 << 6) | |
242 | ||
243 | #define RT5631_MICBIAS1_SHORT_CURR_DET_MASK (0x3 << 4) | |
244 | #define RT5631_MICBIAS1_SHORT_CURR_DET_600UA (0x0 << 4) | |
245 | #define RT5631_MICBIAS1_SHORT_CURR_DET_1500UA (0x1 << 4) | |
246 | #define RT5631_MICBIAS1_SHORT_CURR_DET_2000UA (0x2 << 4) | |
247 | ||
248 | #define RT5631_MICBIAS2_VOLT_CTRL_MASK (0x1 << 3) | |
249 | #define RT5631_MICBIAS2_VOLT_CTRL_90P (0x0 << 3) | |
250 | #define RT5631_MICBIAS2_VOLT_CTRL_75P (0x1 << 3) | |
251 | ||
252 | #define RT5631_MICBIAS2_S_C_DET_MASK (0x1 << 2) | |
253 | #define RT5631_MICBIAS2_S_C_DET_DIS (0x0 << 2) | |
254 | #define RT5631_MICBIAS2_S_C_DET_ENA (0x1 << 2) | |
255 | ||
256 | #define RT5631_MICBIAS2_SHORT_CURR_DET_MASK (0x3) | |
257 | #define RT5631_MICBIAS2_SHORT_CURR_DET_600UA (0x0) | |
258 | #define RT5631_MICBIAS2_SHORT_CURR_DET_1500UA (0x1) | |
259 | #define RT5631_MICBIAS2_SHORT_CURR_DET_2000UA (0x2) | |
260 | ||
261 | ||
262 | /* Digital Microphone Control(0x24) */ | |
263 | #define RT5631_DMIC_ENA_MASK (0x1 << 15) | |
264 | #define RT5631_DMIC_ENA_SHIFT 15 | |
265 | /* DMIC_ENA: DMIC to ADC Digital filter */ | |
266 | #define RT5631_DMIC_ENA (0x1 << 15) | |
267 | /* DMIC_DIS: ADC mixer to ADC Digital filter */ | |
268 | #define RT5631_DMIC_DIS (0x0 << 15) | |
269 | #define RT5631_DMIC_L_CH_MUTE (0x1 << 13) | |
270 | #define RT5631_DMIC_L_CH_MUTE_SHIFT 13 | |
271 | #define RT5631_DMIC_R_CH_MUTE (0x1 << 12) | |
272 | #define RT5631_DMIC_R_CH_MUTE_SHIFT 12 | |
273 | #define RT5631_DMIC_L_CH_LATCH_MASK (0x1 << 9) | |
274 | #define RT5631_DMIC_L_CH_LATCH_RISING (0x1 << 9) | |
275 | #define RT5631_DMIC_L_CH_LATCH_FALLING (0x0 << 9) | |
276 | #define RT5631_DMIC_R_CH_LATCH_MASK (0x1 << 8) | |
277 | #define RT5631_DMIC_R_CH_LATCH_RISING (0x1 << 8) | |
278 | #define RT5631_DMIC_R_CH_LATCH_FALLING (0x0 << 8) | |
279 | #define RT5631_DMIC_CLK_CTRL_MASK (0x3 << 4) | |
280 | #define RT5631_DMIC_CLK_CTRL_TO_128FS (0x0 << 4) | |
281 | #define RT5631_DMIC_CLK_CTRL_TO_64FS (0x1 << 4) | |
282 | #define RT5631_DMIC_CLK_CTRL_TO_32FS (0x2 << 4) | |
283 | ||
284 | /* Microphone Input Volume(0x26) */ | |
285 | #define RT5631_MONO_DIFF_INPUT_SHIFT 15 | |
286 | ||
287 | /* Speaker Mixer Control(0x28) */ | |
288 | #define RT5631_M_RECMIXER_L_TO_SPKMIXER_L (0x1 << 15) | |
289 | #define RT5631_M_RECMIXL_SPKMIXL_BIT 15 | |
290 | #define RT5631_M_MIC1_P_TO_SPKMIXER_L (0x1 << 14) | |
291 | #define RT5631_M_MIC1P_SPKMIXL_BIT 14 | |
292 | #define RT5631_M_DAC_L_TO_SPKMIXER_L (0x1 << 13) | |
293 | #define RT5631_M_DACL_SPKMIXL_BIT 13 | |
294 | #define RT5631_M_OUTMIXER_L_TO_SPKMIXER_L (0x1 << 12) | |
295 | #define RT5631_M_OUTMIXL_SPKMIXL_BIT 12 | |
296 | ||
297 | #define RT5631_M_RECMIXER_R_TO_SPKMIXER_R (0x1 << 7) | |
298 | #define RT5631_M_RECMIXR_SPKMIXR_BIT 7 | |
299 | #define RT5631_M_MIC2_P_TO_SPKMIXER_R (0x1 << 6) | |
300 | #define RT5631_M_MIC2P_SPKMIXR_BIT 6 | |
301 | #define RT5631_M_DAC_R_TO_SPKMIXER_R (0x1 << 5) | |
302 | #define RT5631_M_DACR_SPKMIXR_BIT 5 | |
303 | #define RT5631_M_OUTMIXER_R_TO_SPKMIXER_R (0x1 << 4) | |
304 | #define RT5631_M_OUTMIXR_SPKMIXR_BIT 4 | |
305 | ||
306 | /* Speaker/Mono Output Control(0x2A) */ | |
307 | #define RT5631_M_SPKVOL_L_TO_SPOL_MIXER (0x1 << 15) | |
308 | #define RT5631_M_SPKVOLL_SPOLMIX_BIT 15 | |
309 | #define RT5631_M_SPKVOL_R_TO_SPOL_MIXER (0x1 << 14) | |
310 | #define RT5631_M_SPKVOLR_SPOLMIX_BIT 14 | |
311 | #define RT5631_M_SPKVOL_L_TO_SPOR_MIXER (0x1 << 13) | |
312 | #define RT5631_M_SPKVOLL_SPORMIX_BIT 13 | |
313 | #define RT5631_M_SPKVOL_R_TO_SPOR_MIXER (0x1 << 12) | |
314 | #define RT5631_M_SPKVOLR_SPORMIX_BIT 12 | |
315 | #define RT5631_M_OUTVOL_L_TO_MONOMIXER (0x1 << 11) | |
316 | #define RT5631_M_OUTVOLL_MONOMIX_BIT 11 | |
317 | #define RT5631_M_OUTVOL_R_TO_MONOMIXER (0x1 << 10) | |
318 | #define RT5631_M_OUTVOLR_MONOMIX_BIT 10 | |
319 | ||
320 | /* Speaker/Mono/HP Output Control(0x2C) */ | |
321 | #define RT5631_SPK_L_MUX_SEL_MASK (0x3 << 14) | |
322 | #define RT5631_SPK_L_MUX_SEL_SPKMIXER_L (0x0 << 14) | |
323 | #define RT5631_SPK_L_MUX_SEL_MONO_IN (0x1 << 14) | |
324 | #define RT5631_SPK_L_MUX_SEL_DAC_L (0x3 << 14) | |
325 | #define RT5631_SPK_L_MUX_SEL_SHIFT 14 | |
326 | ||
327 | #define RT5631_SPK_R_MUX_SEL_MASK (0x3 << 10) | |
328 | #define RT5631_SPK_R_MUX_SEL_SPKMIXER_R (0x0 << 10) | |
329 | #define RT5631_SPK_R_MUX_SEL_MONO_IN (0x1 << 10) | |
330 | #define RT5631_SPK_R_MUX_SEL_DAC_R (0x3 << 10) | |
331 | #define RT5631_SPK_R_MUX_SEL_SHIFT 10 | |
332 | ||
333 | #define RT5631_MONO_MUX_SEL_MASK (0x3 << 6) | |
334 | #define RT5631_MONO_MUX_SEL_MONOMIXER (0x0 << 6) | |
335 | #define RT5631_MONO_MUX_SEL_MONO_IN (0x1 << 6) | |
336 | #define RT5631_MONO_MUX_SEL_SHIFT 6 | |
337 | ||
338 | #define RT5631_HP_L_MUX_SEL_MASK (0x1 << 3) | |
339 | #define RT5631_HP_L_MUX_SEL_HPVOL_L (0x0 << 3) | |
340 | #define RT5631_HP_L_MUX_SEL_DAC_L (0x1 << 3) | |
341 | #define RT5631_HP_L_MUX_SEL_SHIFT 3 | |
342 | ||
343 | #define RT5631_HP_R_MUX_SEL_MASK (0x1 << 2) | |
344 | #define RT5631_HP_R_MUX_SEL_HPVOL_R (0x0 << 2) | |
345 | #define RT5631_HP_R_MUX_SEL_DAC_R (0x1 << 2) | |
346 | #define RT5631_HP_R_MUX_SEL_SHIFT 2 | |
347 | ||
348 | /* Stereo I2S Serial Data Port Control(0x34) */ | |
349 | #define RT5631_SDP_MODE_SEL_MASK (0x1 << 15) | |
350 | #define RT5631_SDP_MODE_SEL_MASTER (0x0 << 15) | |
351 | #define RT5631_SDP_MODE_SEL_SLAVE (0x1 << 15) | |
352 | ||
353 | #define RT5631_SDP_ADC_CPS_SEL_MASK (0x3 << 10) | |
354 | #define RT5631_SDP_ADC_CPS_SEL_OFF (0x0 << 10) | |
355 | #define RT5631_SDP_ADC_CPS_SEL_U_LAW (0x1 << 10) | |
356 | #define RT5631_SDP_ADC_CPS_SEL_A_LAW (0x2 << 10) | |
357 | ||
358 | #define RT5631_SDP_DAC_CPS_SEL_MASK (0x3 << 8) | |
359 | #define RT5631_SDP_DAC_CPS_SEL_OFF (0x0 << 8) | |
360 | #define RT5631_SDP_DAC_CPS_SEL_U_LAW (0x1 << 8) | |
361 | #define RT5631_SDP_DAC_CPS_SEL_A_LAW (0x2 << 8) | |
362 | /* 0:Normal 1:Invert */ | |
363 | #define RT5631_SDP_I2S_BCLK_POL_CTRL (0x1 << 7) | |
364 | /* 0:Normal 1:Invert */ | |
365 | #define RT5631_SDP_DAC_R_INV (0x1 << 6) | |
366 | /* 0:ADC data appear at left phase of LRCK | |
367 | * 1:ADC data appear at right phase of LRCK | |
368 | */ | |
369 | #define RT5631_SDP_ADC_DATA_L_R_SWAP (0x1 << 5) | |
370 | /* 0:DAC data appear at left phase of LRCK | |
371 | * 1:DAC data appear at right phase of LRCK | |
372 | */ | |
373 | #define RT5631_SDP_DAC_DATA_L_R_SWAP (0x1 << 4) | |
374 | ||
375 | /* Data Length Slection */ | |
376 | #define RT5631_SDP_I2S_DL_MASK (0x3 << 2) | |
377 | #define RT5631_SDP_I2S_DL_16 (0x0 << 2) | |
378 | #define RT5631_SDP_I2S_DL_20 (0x1 << 2) | |
379 | #define RT5631_SDP_I2S_DL_24 (0x2 << 2) | |
380 | #define RT5631_SDP_I2S_DL_8 (0x3 << 2) | |
381 | ||
382 | /* PCM Data Format Selection */ | |
383 | #define RT5631_SDP_I2S_DF_MASK (0x3) | |
384 | #define RT5631_SDP_I2S_DF_I2S (0x0) | |
385 | #define RT5631_SDP_I2S_DF_LEFT (0x1) | |
386 | #define RT5631_SDP_I2S_DF_PCM_A (0x2) | |
387 | #define RT5631_SDP_I2S_DF_PCM_B (0x3) | |
388 | ||
389 | /* Stereo AD/DA Clock Control(0x38h) */ | |
390 | #define RT5631_I2S_PRE_DIV_MASK (0x7 << 13) | |
391 | #define RT5631_I2S_PRE_DIV_1 (0x0 << 13) | |
392 | #define RT5631_I2S_PRE_DIV_2 (0x1 << 13) | |
393 | #define RT5631_I2S_PRE_DIV_4 (0x2 << 13) | |
394 | #define RT5631_I2S_PRE_DIV_8 (0x3 << 13) | |
395 | #define RT5631_I2S_PRE_DIV_16 (0x4 << 13) | |
396 | #define RT5631_I2S_PRE_DIV_32 (0x5 << 13) | |
397 | /* CLOCK RELATIVE OF BCLK AND LCRK */ | |
398 | #define RT5631_I2S_LRCK_SEL_N_BCLK_MASK (0x1 << 12) | |
399 | #define RT5631_I2S_LRCK_SEL_64_BCLK (0x0 << 12) /* 64FS */ | |
400 | #define RT5631_I2S_LRCK_SEL_32_BCLK (0x1 << 12) /* 32FS */ | |
401 | ||
402 | #define RT5631_DAC_OSR_SEL_MASK (0x3 << 10) | |
403 | #define RT5631_DAC_OSR_SEL_128FS (0x3 << 10) | |
404 | #define RT5631_DAC_OSR_SEL_64FS (0x3 << 10) | |
405 | #define RT5631_DAC_OSR_SEL_32FS (0x3 << 10) | |
406 | #define RT5631_DAC_OSR_SEL_16FS (0x3 << 10) | |
407 | ||
408 | #define RT5631_ADC_OSR_SEL_MASK (0x3 << 8) | |
409 | #define RT5631_ADC_OSR_SEL_128FS (0x3 << 8) | |
410 | #define RT5631_ADC_OSR_SEL_64FS (0x3 << 8) | |
411 | #define RT5631_ADC_OSR_SEL_32FS (0x3 << 8) | |
412 | #define RT5631_ADC_OSR_SEL_16FS (0x3 << 8) | |
413 | ||
414 | #define RT5631_ADDA_FILTER_CLK_SEL_256FS (0 << 7) /* 256FS */ | |
415 | #define RT5631_ADDA_FILTER_CLK_SEL_384FS (1 << 7) /* 384FS */ | |
416 | ||
417 | /* Power managment addition 1 (0x3A) */ | |
418 | #define RT5631_PWR_MAIN_I2S_EN (0x1 << 15) | |
419 | #define RT5631_PWR_MAIN_I2S_BIT 15 | |
420 | #define RT5631_PWR_CLASS_D (0x1 << 12) | |
421 | #define RT5631_PWR_CLASS_D_BIT 12 | |
422 | #define RT5631_PWR_ADC_L_CLK (0x1 << 11) | |
423 | #define RT5631_PWR_ADC_L_CLK_BIT 11 | |
424 | #define RT5631_PWR_ADC_R_CLK (0x1 << 10) | |
425 | #define RT5631_PWR_ADC_R_CLK_BIT 10 | |
426 | #define RT5631_PWR_DAC_L_CLK (0x1 << 9) | |
427 | #define RT5631_PWR_DAC_L_CLK_BIT 9 | |
428 | #define RT5631_PWR_DAC_R_CLK (0x1 << 8) | |
429 | #define RT5631_PWR_DAC_R_CLK_BIT 8 | |
430 | #define RT5631_PWR_DAC_REF (0x1 << 7) | |
431 | #define RT5631_PWR_DAC_REF_BIT 7 | |
432 | #define RT5631_PWR_DAC_L_TO_MIXER (0x1 << 6) | |
433 | #define RT5631_PWR_DAC_L_TO_MIXER_BIT 6 | |
434 | #define RT5631_PWR_DAC_R_TO_MIXER (0x1 << 5) | |
435 | #define RT5631_PWR_DAC_R_TO_MIXER_BIT 5 | |
436 | ||
437 | /* Power managment addition 2 (0x3B) */ | |
438 | #define RT5631_PWR_OUTMIXER_L (0x1 << 15) | |
439 | #define RT5631_PWR_OUTMIXER_L_BIT 15 | |
440 | #define RT5631_PWR_OUTMIXER_R (0x1 << 14) | |
441 | #define RT5631_PWR_OUTMIXER_R_BIT 14 | |
442 | #define RT5631_PWR_SPKMIXER_L (0x1 << 13) | |
443 | #define RT5631_PWR_SPKMIXER_L_BIT 13 | |
444 | #define RT5631_PWR_SPKMIXER_R (0x1 << 12) | |
445 | #define RT5631_PWR_SPKMIXER_R_BIT 12 | |
446 | #define RT5631_PWR_RECMIXER_L (0x1 << 11) | |
447 | #define RT5631_PWR_RECMIXER_L_BIT 11 | |
448 | #define RT5631_PWR_RECMIXER_R (0x1 << 10) | |
449 | #define RT5631_PWR_RECMIXER_R_BIT 10 | |
450 | #define RT5631_PWR_MIC1_BOOT_GAIN (0x1 << 5) | |
451 | #define RT5631_PWR_MIC1_BOOT_GAIN_BIT 5 | |
452 | #define RT5631_PWR_MIC2_BOOT_GAIN (0x1 << 4) | |
453 | #define RT5631_PWR_MIC2_BOOT_GAIN_BIT 4 | |
454 | #define RT5631_PWR_MICBIAS1_VOL (0x1 << 3) | |
455 | #define RT5631_PWR_MICBIAS1_VOL_BIT 3 | |
456 | #define RT5631_PWR_MICBIAS2_VOL (0x1 << 2) | |
457 | #define RT5631_PWR_MICBIAS2_VOL_BIT 2 | |
458 | #define RT5631_PWR_PLL1 (0x1 << 1) | |
459 | #define RT5631_PWR_PLL1_BIT 1 | |
460 | #define RT5631_PWR_PLL2 (0x1 << 0) | |
461 | #define RT5631_PWR_PLL2_BIT 0 | |
462 | ||
463 | /* Power managment addition 3(0x3C) */ | |
464 | #define RT5631_PWR_VREF (0x1 << 15) | |
465 | #define RT5631_PWR_VREF_BIT 15 | |
466 | #define RT5631_PWR_FAST_VREF_CTRL (0x1 << 14) | |
467 | #define RT5631_PWR_FAST_VREF_CTRL_BIT 14 | |
468 | #define RT5631_PWR_MAIN_BIAS (0x1 << 13) | |
469 | #define RT5631_PWR_MAIN_BIAS_BIT 13 | |
470 | #define RT5631_PWR_AXO1MIXER (0x1 << 11) | |
471 | #define RT5631_PWR_AXO1MIXER_BIT 11 | |
472 | #define RT5631_PWR_AXO2MIXER (0x1 << 10) | |
473 | #define RT5631_PWR_AXO2MIXER_BIT 10 | |
474 | #define RT5631_PWR_MONOMIXER (0x1 << 9) | |
475 | #define RT5631_PWR_MONOMIXER_BIT 9 | |
476 | #define RT5631_PWR_MONO_DEPOP_DIS (0x1 << 8) | |
477 | #define RT5631_PWR_MONO_DEPOP_DIS_BIT 8 | |
478 | #define RT5631_PWR_MONO_AMP_EN (0x1 << 7) | |
479 | #define RT5631_PWR_MONO_AMP_EN_BIT 7 | |
480 | #define RT5631_PWR_CHARGE_PUMP (0x1 << 4) | |
481 | #define RT5631_PWR_CHARGE_PUMP_BIT 4 | |
482 | #define RT5631_PWR_HP_L_AMP (0x1 << 3) | |
483 | #define RT5631_PWR_HP_L_AMP_BIT 3 | |
484 | #define RT5631_PWR_HP_R_AMP (0x1 << 2) | |
485 | #define RT5631_PWR_HP_R_AMP_BIT 2 | |
486 | #define RT5631_PWR_HP_DEPOP_DIS (0x1 << 1) | |
487 | #define RT5631_PWR_HP_DEPOP_DIS_BIT 1 | |
488 | #define RT5631_PWR_HP_AMP_DRIVING (0x1 << 0) | |
489 | #define RT5631_PWR_HP_AMP_DRIVING_BIT 0 | |
490 | ||
491 | /* Power managment addition 4(0x3E) */ | |
492 | #define RT5631_PWR_SPK_L_VOL (0x1 << 15) | |
493 | #define RT5631_PWR_SPK_L_VOL_BIT 15 | |
494 | #define RT5631_PWR_SPK_R_VOL (0x1 << 14) | |
495 | #define RT5631_PWR_SPK_R_VOL_BIT 14 | |
496 | #define RT5631_PWR_LOUT_VOL (0x1 << 13) | |
497 | #define RT5631_PWR_LOUT_VOL_BIT 13 | |
498 | #define RT5631_PWR_ROUT_VOL (0x1 << 12) | |
499 | #define RT5631_PWR_ROUT_VOL_BIT 12 | |
500 | #define RT5631_PWR_HP_L_OUT_VOL (0x1 << 11) | |
501 | #define RT5631_PWR_HP_L_OUT_VOL_BIT 11 | |
502 | #define RT5631_PWR_HP_R_OUT_VOL (0x1 << 10) | |
503 | #define RT5631_PWR_HP_R_OUT_VOL_BIT 10 | |
504 | #define RT5631_PWR_AXIL_IN_VOL (0x1 << 9) | |
505 | #define RT5631_PWR_AXIL_IN_VOL_BIT 9 | |
506 | #define RT5631_PWR_AXIR_IN_VOL (0x1 << 8) | |
507 | #define RT5631_PWR_AXIR_IN_VOL_BIT 8 | |
508 | #define RT5631_PWR_MONO_IN_P_VOL (0x1 << 7) | |
509 | #define RT5631_PWR_MONO_IN_P_VOL_BIT 7 | |
510 | #define RT5631_PWR_MONO_IN_N_VOL (0x1 << 6) | |
511 | #define RT5631_PWR_MONO_IN_N_VOL_BIT 6 | |
512 | ||
513 | /* General Purpose Control Register(0x40) */ | |
514 | #define RT5631_SPK_AMP_AUTO_RATIO_EN (0x1 << 15) | |
515 | ||
516 | #define RT5631_SPK_AMP_RATIO_CTRL_MASK (0x7 << 12) | |
517 | #define RT5631_SPK_AMP_RATIO_CTRL_2_34 (0x0 << 12) /* 7.40DB */ | |
518 | #define RT5631_SPK_AMP_RATIO_CTRL_1_99 (0x1 << 12) /* 5.99DB */ | |
519 | #define RT5631_SPK_AMP_RATIO_CTRL_1_68 (0x2 << 12) /* 4.50DB */ | |
520 | #define RT5631_SPK_AMP_RATIO_CTRL_1_56 (0x3 << 12) /* 3.86DB */ | |
521 | #define RT5631_SPK_AMP_RATIO_CTRL_1_44 (0x4 << 12) /* 3.16DB */ | |
522 | #define RT5631_SPK_AMP_RATIO_CTRL_1_27 (0x5 << 12) /* 2.10DB */ | |
523 | #define RT5631_SPK_AMP_RATIO_CTRL_1_09 (0x6 << 12) /* 0.80DB */ | |
524 | #define RT5631_SPK_AMP_RATIO_CTRL_1_00 (0x7 << 12) /* 0.00DB */ | |
525 | #define RT5631_SPK_AMP_RATIO_CTRL_SHIFT 12 | |
526 | ||
527 | #define RT5631_STEREO_DAC_HI_PASS_FILT_EN (0x1 << 11) | |
528 | #define RT5631_STEREO_ADC_HI_PASS_FILT_EN (0x1 << 10) | |
529 | /* Select ADC Wind Filter Clock type */ | |
530 | #define RT5631_ADC_WIND_FILT_MASK (0x3 << 4) | |
531 | #define RT5631_ADC_WIND_FILT_8_16_32K (0x0 << 4) /*8/16/32k*/ | |
532 | #define RT5631_ADC_WIND_FILT_11_22_44K (0x1 << 4) /*11/22/44k*/ | |
533 | #define RT5631_ADC_WIND_FILT_12_24_48K (0x2 << 4) /*12/24/48k*/ | |
534 | #define RT5631_ADC_WIND_FILT_EN (0x1 << 3) | |
535 | /* SelectADC Wind Filter Corner Frequency */ | |
536 | #define RT5631_ADC_WIND_CNR_FREQ_MASK (0x7 << 0) | |
537 | #define RT5631_ADC_WIND_CNR_FREQ_82_113_122 (0x0 << 0) /* 82/113/122 Hz */ | |
538 | #define RT5631_ADC_WIND_CNR_FREQ_102_141_153 (0x1 << 0) /* 102/141/153 Hz */ | |
539 | #define RT5631_ADC_WIND_CNR_FREQ_131_180_156 (0x2 << 0) /* 131/180/156 Hz */ | |
540 | #define RT5631_ADC_WIND_CNR_FREQ_163_225_245 (0x3 << 0) /* 163/225/245 Hz */ | |
541 | #define RT5631_ADC_WIND_CNR_FREQ_204_281_306 (0x4 << 0) /* 204/281/306 Hz */ | |
542 | #define RT5631_ADC_WIND_CNR_FREQ_261_360_392 (0x5 << 0) /* 261/360/392 Hz */ | |
543 | #define RT5631_ADC_WIND_CNR_FREQ_327_450_490 (0x6 << 0) /* 327/450/490 Hz */ | |
544 | #define RT5631_ADC_WIND_CNR_FREQ_408_563_612 (0x7 << 0) /* 408/563/612 Hz */ | |
545 | ||
546 | /* Global Clock Control Register(0x42) */ | |
547 | #define RT5631_SYSCLK_SOUR_SEL_MASK (0x3 << 14) | |
548 | #define RT5631_SYSCLK_SOUR_SEL_MCLK (0x0 << 14) | |
549 | #define RT5631_SYSCLK_SOUR_SEL_PLL (0x1 << 14) | |
550 | #define RT5631_SYSCLK_SOUR_SEL_PLL_TCK (0x2 << 14) | |
551 | ||
552 | #define RT5631_PLLCLK_SOUR_SEL_MASK (0x3 << 12) | |
553 | #define RT5631_PLLCLK_SOUR_SEL_MCLK (0x0 << 12) | |
554 | #define RT5631_PLLCLK_SOUR_SEL_BCLK (0x1 << 12) | |
555 | #define RT5631_PLLCLK_SOUR_SEL_VBCLK (0x2 << 12) | |
556 | ||
557 | #define RT5631_PLLCLK_PRE_DIV1 (0x0 << 11) | |
558 | #define RT5631_PLLCLK_PRE_DIV2 (0x1 << 11) | |
559 | ||
560 | /* PLL Control(0x44) */ | |
561 | #define RT5631_PLL_CTRL_M_VAL(m) ((m)&0xf) | |
562 | #define RT5631_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4) | |
563 | #define RT5631_PLL_CTRL_N_VAL(n) (((n)&0xff) << 8) | |
564 | ||
565 | /* Internal Status and IRQ Control2(0x4A) */ | |
566 | #define RT5631_ADC_DATA_SEL_MASK (0x3 << 14) | |
567 | #define RT5631_ADC_DATA_SEL_Disable (0x0 << 14) | |
568 | #define RT5631_ADC_DATA_SEL_MIC1 (0x1 << 14) | |
569 | #define RT5631_ADC_DATA_SEL_MIC1_SHIFT 14 | |
570 | #define RT5631_ADC_DATA_SEL_MIC2 (0x2 << 14) | |
571 | #define RT5631_ADC_DATA_SEL_MIC2_SHIFT 15 | |
572 | #define RT5631_ADC_DATA_SEL_STO (0x3 << 14) | |
573 | #define RT5631_ADC_DATA_SEL_SHIFT 14 | |
574 | ||
575 | /* GPIO Pin Configuration(0x4C) */ | |
576 | #define RT5631_GPIO_PIN_FUN_SEL_MASK (0x1 << 15) | |
577 | #define RT5631_GPIO_PIN_FUN_SEL_IRQ (0x1 << 15) | |
578 | #define RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC (0x0 << 15) | |
579 | ||
580 | #define RT5631_GPIO_DMIC_FUN_SEL_MASK (0x1 << 3) | |
581 | #define RT5631_GPIO_DMIC_FUN_SEL_DIMC (0x1 << 3) | |
582 | #define RT5631_GPIO_DMIC_FUN_SEL_GPIO (0x0 << 3) | |
583 | ||
584 | #define RT5631_GPIO_PIN_CON_MASK (0x1 << 2) | |
585 | #define RT5631_GPIO_PIN_SET_INPUT (0x0 << 2) | |
586 | #define RT5631_GPIO_PIN_SET_OUTPUT (0x1 << 2) | |
587 | ||
588 | /* De-POP function Control 1(0x54) */ | |
589 | #define RT5631_POW_ON_SOFT_GEN (0x1 << 15) | |
590 | #define RT5631_EN_MUTE_UNMUTE_DEPOP (0x1 << 14) | |
591 | #define RT5631_EN_DEPOP2_FOR_HP (0x1 << 7) | |
592 | /* Power Down HPAMP_L Starts Up Signal */ | |
593 | #define RT5631_PD_HPAMP_L_ST_UP (0x1 << 5) | |
594 | /* Power Down HPAMP_R Starts Up Signal */ | |
595 | #define RT5631_PD_HPAMP_R_ST_UP (0x1 << 4) | |
596 | /* Enable left HP mute/unmute depop */ | |
597 | #define RT5631_EN_HP_L_M_UN_MUTE_DEPOP (0x1 << 1) | |
598 | /* Enable right HP mute/unmute depop */ | |
599 | #define RT5631_EN_HP_R_M_UN_MUTE_DEPOP (0x1 << 0) | |
600 | ||
601 | /* De-POP Fnction Control(0x56) */ | |
602 | #define RT5631_EN_ONE_BIT_DEPOP (0x1 << 15) | |
603 | #define RT5631_EN_CAP_FREE_DEPOP (0x1 << 14) | |
604 | ||
605 | /* Jack Detect Control Register(0x5A) */ | |
606 | #define RT5631_JD_USE_MASK (0x3 << 14) | |
607 | #define RT5631_JD_USE_JD2 (0x3 << 14) | |
608 | #define RT5631_JD_USE_JD1 (0x2 << 14) | |
609 | #define RT5631_JD_USE_GPIO (0x1 << 14) | |
610 | #define RT5631_JD_OFF (0x0 << 14) | |
611 | /* JD trigger enable for HP */ | |
612 | #define RT5631_JD_HP_EN (0x1 << 11) | |
613 | #define RT5631_JD_HP_TRI_MASK (0x1 << 10) | |
614 | #define RT5631_JD_HP_TRI_HI (0x1 << 10) | |
615 | #define RT5631_JD_HP_TRI_LO (0x1 << 10) | |
616 | /* JD trigger enable for speaker LP/LN */ | |
617 | #define RT5631_JD_SPK_L_EN (0x1 << 9) | |
618 | #define RT5631_JD_SPK_L_TRI_MASK (0x1 << 8) | |
619 | #define RT5631_JD_SPK_L_TRI_HI (0x1 << 8) | |
620 | #define RT5631_JD_SPK_L_TRI_LO (0x0 << 8) | |
621 | /* JD trigger enable for speaker RP/RN */ | |
622 | #define RT5631_JD_SPK_R_EN (0x1 << 7) | |
623 | #define RT5631_JD_SPK_R_TRI_MASK (0x1 << 6) | |
624 | #define RT5631_JD_SPK_R_TRI_HI (0x1 << 6) | |
625 | #define RT5631_JD_SPK_R_TRI_LO (0x0 << 6) | |
626 | /* JD trigger enable for monoout */ | |
627 | #define RT5631_JD_MONO_EN (0x1 << 5) | |
628 | #define RT5631_JD_MONO_TRI_MASK (0x1 << 4) | |
629 | #define RT5631_JD_MONO_TRI_HI (0x1 << 4) | |
630 | #define RT5631_JD_MONO_TRI_LO (0x0 << 4) | |
631 | /* JD trigger enable for Lout */ | |
632 | #define RT5631_JD_AUX_1_EN (0x1 << 3) | |
633 | #define RT5631_JD_AUX_1_MASK (0x1 << 2) | |
634 | #define RT5631_JD_AUX_1_TRI_HI (0x1 << 2) | |
635 | #define RT5631_JD_AUX_1_TRI_LO (0x0 << 2) | |
636 | /* JD trigger enable for Rout */ | |
637 | #define RT5631_JD_AUX_2_EN (0x1 << 1) | |
638 | #define RT5631_JD_AUX_2_MASK (0x1 << 0) | |
639 | #define RT5631_JD_AUX_2_TRI_HI (0x1 << 0) | |
640 | #define RT5631_JD_AUX_2_TRI_LO (0x0 << 0) | |
641 | ||
642 | /* ALC CONTROL 1(0x64) */ | |
643 | #define RT5631_ALC_ATTACK_RATE_MASK (0x1F << 8) | |
644 | #define RT5631_ALC_RECOVERY_RATE_MASK (0x1F << 0) | |
645 | ||
646 | /* ALC CONTROL 2(0x65) */ | |
647 | /* select Compensation gain for Noise gate function */ | |
648 | #define RT5631_ALC_COM_NOISE_GATE_MASK (0xF << 0) | |
649 | ||
650 | /* ALC CONTROL 3(0x66) */ | |
651 | #define RT5631_ALC_FUN_MASK (0x3 << 14) | |
652 | #define RT5631_ALC_FUN_DIS (0x0 << 14) | |
653 | #define RT5631_ALC_ENA_DAC_PATH (0x1 << 14) | |
654 | #define RT5631_ALC_ENA_ADC_PATH (0x3 << 14) | |
655 | #define RT5631_ALC_PARA_UPDATE (0x1 << 13) | |
656 | #define RT5631_ALC_LIMIT_LEVEL_MASK (0x1F << 8) | |
657 | #define RT5631_ALC_NOISE_GATE_FUN_MASK (0x1 << 7) | |
658 | #define RT5631_ALC_NOISE_GATE_FUN_DIS (0x0 << 7) | |
659 | #define RT5631_ALC_NOISE_GATE_FUN_ENA (0x1 << 7) | |
660 | /* ALC noise gate hold data function */ | |
661 | #define RT5631_ALC_NOISE_GATE_H_D_MASK (0x1 << 6) | |
662 | #define RT5631_ALC_NOISE_GATE_H_D_DIS (0x0 << 6) | |
663 | #define RT5631_ALC_NOISE_GATE_H_D_ENA (0x1 << 6) | |
664 | ||
665 | /* Psedueo Stereo & Spatial Effect Block Control(0x68) */ | |
666 | #define RT5631_SPATIAL_CTRL_EN (0x1 << 15) | |
667 | #define RT5631_ALL_PASS_FILTER_EN (0x1 << 14) | |
668 | #define RT5631_PSEUDO_STEREO_EN (0x1 << 13) | |
669 | #define RT5631_STEREO_EXPENSION_EN (0x1 << 12) | |
670 | /* 3D gain parameter */ | |
671 | #define RT5631_GAIN_3D_PARA_MASK (0x3 << 6) | |
672 | #define RT5631_GAIN_3D_PARA_1_00 (0x0 << 6) /* 3D gain 1.0 */ | |
673 | #define RT5631_GAIN_3D_PARA_1_50 (0x1 << 6) /* 3D gain 1.5 */ | |
674 | #define RT5631_GAIN_3D_PARA_2_00 (0x2 << 6) /* 3D gain 2.0 */ | |
675 | /* 3D ratio parameter */ | |
676 | #define RT5631_RATIO_3D_MASK (0x3 << 4) | |
677 | #define RT5631_RATIO_3D_0_0 (0x0 << 4) /* 3D ratio 0.0 */ | |
678 | #define RT5631_RATIO_3D_0_66 (0x1 << 4) /* 3D ratio 0.66 */ | |
679 | #define RT5631_RATIO_3D_1_0 (0x2 << 4) /* 3D ratio 1.0 */ | |
680 | /* select samplerate for all pass filter */ | |
681 | #define RT5631_APF_FUN_SLE_MASK (0x3 << 0) | |
682 | #define RT5631_APF_FUN_SEL_48K (0x3 << 0) | |
683 | #define RT5631_APF_FUN_SEL_44_1K (0x2 << 0) | |
684 | #define RT5631_APF_FUN_SEL_32K (0x1 << 0) | |
685 | #define RT5631_APF_FUN_DIS (0x0 << 0) | |
686 | ||
687 | /* EQ CONTROL 1(0x6E) */ | |
688 | #define RT5631_HW_EQ_PATH_SEL_MASK (0x1 << 15) | |
689 | #define RT5631_HW_EQ_PATH_SEL_DAC (0x0 << 15) | |
690 | #define RT5631_HW_EQ_PATH_SEL_ADC (0x1 << 15) | |
691 | #define RT5631_HW_EQ_UPDATE_CTRL (0x1 << 14) | |
692 | ||
693 | #define RT5631_EN_HW_EQ_HPF2 (0x1 << 5) | |
694 | #define RT5631_EN_HW_EQ_HPF1 (0x1 << 4) | |
695 | #define RT5631_EN_HW_EQ_BP3 (0x1 << 3) | |
696 | #define RT5631_EN_HW_EQ_BP2 (0x1 << 2) | |
697 | #define RT5631_EN_HW_EQ_BP1 (0x1 << 1) | |
698 | #define RT5631_EN_HW_EQ_LPF (0x1 << 0) | |
699 | ||
700 | ||
701 | #endif /* __RTCODEC5631_H__ */ |