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[mirror_ubuntu-zesty-kernel.git] / sound / soc / codecs / rt5645.c
CommitLineData
1319b2f6
OC		 1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
f3fa1bbd 20#include <linux/gpio.h>
baf2a0e1 21#include <linux/gpio/consumer.h>
3168c201 22#include <linux/acpi.h>
78c34fd4 23#include <linux/dmi.h>
9fc114c5 24#include <linux/regulator/consumer.h>
1319b2f6
OC		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
49ef7925 34#include "rl6231.h"
1319b2f6
OC		 35#include "rt5645.h"
36
37#define RT5645_DEVICE_ID 0x6308
5c4ca99d 38#define RT5650_DEVICE_ID 0x6419
1319b2f6
OC		 39
40#define RT5645_PR_RANGE_BASE (0xff + 1)
41#define RT5645_PR_SPACING 0x100
42
43#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
44
be77b38a
OC		 45#define RT5645_HWEQ_NUM 57
46
1319b2f6
OC		 47static const struct regmap_range_cfg rt5645_ranges[] = {
48 {
49 .name = "PR",
50 .range_min = RT5645_PR_BASE,
51 .range_max = RT5645_PR_BASE + 0xf8,
52 .selector_reg = RT5645_PRIV_INDEX,
53 .selector_mask = 0xff,
54 .selector_shift = 0x0,
55 .window_start = RT5645_PRIV_DATA,
56 .window_len = 0x1,
57 },
58};
59
8019ff6c 60static const struct reg_sequence init_list[] = {
1319b2f6 61 {RT5645_PR_BASE + 0x3d, 0x3600},
4809b96e
OC		 62 {RT5645_PR_BASE + 0x1c, 0xfd20},
63 {RT5645_PR_BASE + 0x20, 0x611f},
64 {RT5645_PR_BASE + 0x21, 0x4040},
65 {RT5645_PR_BASE + 0x23, 0x0004},
e62ebf15 66 {RT5645_ASRC_4, 0x0120},
1319b2f6 67};
1319b2f6 68
8019ff6c 69static const struct reg_sequence rt5650_init_list[] = {
5c4ca99d
BL		 70 {0xf6, 0x0100},
71};
72
1319b2f6
OC		 73static const struct reg_default rt5645_reg[] = {
74 { 0x00, 0x0000 },
75 { 0x01, 0xc8c8 },
76 { 0x02, 0xc8c8 },
77 { 0x03, 0xc8c8 },
78 { 0x0a, 0x0002 },
79 { 0x0b, 0x2827 },
80 { 0x0c, 0xe000 },
81 { 0x0d, 0x0000 },
82 { 0x0e, 0x0000 },
83 { 0x0f, 0x0808 },
84 { 0x14, 0x3333 },
85 { 0x16, 0x4b00 },
86 { 0x18, 0x018b },
87 { 0x19, 0xafaf },
88 { 0x1a, 0xafaf },
89 { 0x1b, 0x0001 },
90 { 0x1c, 0x2f2f },
91 { 0x1d, 0x2f2f },
92 { 0x1e, 0x0000 },
93 { 0x20, 0x0000 },
94 { 0x27, 0x7060 },
95 { 0x28, 0x7070 },
96 { 0x29, 0x8080 },
97 { 0x2a, 0x5656 },
98 { 0x2b, 0x5454 },
99 { 0x2c, 0xaaa0 },
5c4ca99d 100 { 0x2d, 0x0000 },
1319b2f6
OC		 101 { 0x2f, 0x1002 },
102 { 0x31, 0x5000 },
103 { 0x32, 0x0000 },
104 { 0x33, 0x0000 },
105 { 0x34, 0x0000 },
106 { 0x35, 0x0000 },
107 { 0x3b, 0x0000 },
108 { 0x3c, 0x007f },
109 { 0x3d, 0x0000 },
110 { 0x3e, 0x007f },
111 { 0x3f, 0x0000 },
112 { 0x40, 0x001f },
113 { 0x41, 0x0000 },
114 { 0x42, 0x001f },
115 { 0x45, 0x6000 },
116 { 0x46, 0x003e },
117 { 0x47, 0x003e },
118 { 0x48, 0xf807 },
119 { 0x4a, 0x0004 },
120 { 0x4d, 0x0000 },
121 { 0x4e, 0x0000 },
122 { 0x4f, 0x01ff },
123 { 0x50, 0x0000 },
124 { 0x51, 0x0000 },
125 { 0x52, 0x01ff },
126 { 0x53, 0xf000 },
127 { 0x56, 0x0111 },
128 { 0x57, 0x0064 },
129 { 0x58, 0xef0e },
130 { 0x59, 0xf0f0 },
131 { 0x5a, 0xef0e },
132 { 0x5b, 0xf0f0 },
133 { 0x5c, 0xef0e },
134 { 0x5d, 0xf0f0 },
135 { 0x5e, 0xf000 },
136 { 0x5f, 0x0000 },
137 { 0x61, 0x0300 },
138 { 0x62, 0x0000 },
139 { 0x63, 0x00c2 },
140 { 0x64, 0x0000 },
141 { 0x65, 0x0000 },
142 { 0x66, 0x0000 },
143 { 0x6a, 0x0000 },
144 { 0x6c, 0x0aaa },
145 { 0x70, 0x8000 },
146 { 0x71, 0x8000 },
147 { 0x72, 0x8000 },
148 { 0x73, 0x7770 },
149 { 0x74, 0x3e00 },
150 { 0x75, 0x2409 },
151 { 0x76, 0x000a },
152 { 0x77, 0x0c00 },
153 { 0x78, 0x0000 },
df078d29 154 { 0x79, 0x0123 },
1319b2f6
OC		 155 { 0x80, 0x0000 },
156 { 0x81, 0x0000 },
157 { 0x82, 0x0000 },
158 { 0x83, 0x0000 },
159 { 0x84, 0x0000 },
160 { 0x85, 0x0000 },
e62ebf15 161 { 0x8a, 0x0120 },
1319b2f6
OC		 162 { 0x8e, 0x0004 },
163 { 0x8f, 0x1100 },
164 { 0x90, 0x0646 },
165 { 0x91, 0x0c06 },
166 { 0x93, 0x0000 },
167 { 0x94, 0x0200 },
168 { 0x95, 0x0000 },
169 { 0x9a, 0x2184 },
170 { 0x9b, 0x010a },
171 { 0x9c, 0x0aea },
172 { 0x9d, 0x000c },
173 { 0x9e, 0x0400 },
174 { 0xa0, 0xa0a8 },
175 { 0xa1, 0x0059 },
176 { 0xa2, 0x0001 },
177 { 0xae, 0x6000 },
178 { 0xaf, 0x0000 },
179 { 0xb0, 0x6000 },
180 { 0xb1, 0x0000 },
181 { 0xb2, 0x0000 },
182 { 0xb3, 0x001f },
183 { 0xb4, 0x020c },
184 { 0xb5, 0x1f00 },
185 { 0xb6, 0x0000 },
186 { 0xbb, 0x0000 },
187 { 0xbc, 0x0000 },
188 { 0xbd, 0x0000 },
189 { 0xbe, 0x0000 },
190 { 0xbf, 0x3100 },
191 { 0xc0, 0x0000 },
192 { 0xc1, 0x0000 },
193 { 0xc2, 0x0000 },
194 { 0xc3, 0x2000 },
195 { 0xcd, 0x0000 },
196 { 0xce, 0x0000 },
197 { 0xcf, 0x1813 },
198 { 0xd0, 0x0690 },
199 { 0xd1, 0x1c17 },
200 { 0xd3, 0xb320 },
201 { 0xd4, 0x0000 },
202 { 0xd6, 0x0400 },
203 { 0xd9, 0x0809 },
204 { 0xda, 0x0000 },
205 { 0xdb, 0x0003 },
206 { 0xdc, 0x0049 },
207 { 0xdd, 0x001b },
5c4ca99d
BL		 208 { 0xdf, 0x0008 },
209 { 0xe0, 0x4000 },
1319b2f6
OC		 210 { 0xe6, 0x8000 },
211 { 0xe7, 0x0200 },
212 { 0xec, 0xb300 },
213 { 0xed, 0x0000 },
214 { 0xf0, 0x001f },
215 { 0xf1, 0x020c },
216 { 0xf2, 0x1f00 },
217 { 0xf3, 0x0000 },
218 { 0xf4, 0x4000 },
219 { 0xf8, 0x0000 },
220 { 0xf9, 0x0000 },
221 { 0xfa, 0x2060 },
222 { 0xfb, 0x4040 },
223 { 0xfc, 0x0000 },
224 { 0xfd, 0x0002 },
225 { 0xfe, 0x10ec },
226 { 0xff, 0x6308 },
227};
228
49abc6cd
BL		 229static const struct reg_default rt5650_reg[] = {
230 { 0x00, 0x0000 },
231 { 0x01, 0xc8c8 },
232 { 0x02, 0xc8c8 },
233 { 0x03, 0xc8c8 },
234 { 0x0a, 0x0002 },
235 { 0x0b, 0x2827 },
236 { 0x0c, 0xe000 },
237 { 0x0d, 0x0000 },
238 { 0x0e, 0x0000 },
239 { 0x0f, 0x0808 },
240 { 0x14, 0x3333 },
241 { 0x16, 0x4b00 },
242 { 0x18, 0x018b },
243 { 0x19, 0xafaf },
244 { 0x1a, 0xafaf },
245 { 0x1b, 0x0001 },
246 { 0x1c, 0x2f2f },
247 { 0x1d, 0x2f2f },
248 { 0x1e, 0x0000 },
249 { 0x20, 0x0000 },
250 { 0x27, 0x7060 },
251 { 0x28, 0x7070 },
252 { 0x29, 0x8080 },
253 { 0x2a, 0x5656 },
254 { 0x2b, 0x5454 },
255 { 0x2c, 0xaaa0 },
256 { 0x2d, 0x0000 },
fdfe3b32 257 { 0x2f, 0x5002 },
49abc6cd
BL		 258 { 0x31, 0x5000 },
259 { 0x32, 0x0000 },
260 { 0x33, 0x0000 },
261 { 0x34, 0x0000 },
262 { 0x35, 0x0000 },
263 { 0x3b, 0x0000 },
264 { 0x3c, 0x007f },
265 { 0x3d, 0x0000 },
266 { 0x3e, 0x007f },
267 { 0x3f, 0x0000 },
268 { 0x40, 0x001f },
269 { 0x41, 0x0000 },
270 { 0x42, 0x001f },
271 { 0x45, 0x6000 },
272 { 0x46, 0x003e },
273 { 0x47, 0x003e },
274 { 0x48, 0xf807 },
275 { 0x4a, 0x0004 },
276 { 0x4d, 0x0000 },
277 { 0x4e, 0x0000 },
278 { 0x4f, 0x01ff },
279 { 0x50, 0x0000 },
280 { 0x51, 0x0000 },
281 { 0x52, 0x01ff },
282 { 0x53, 0xf000 },
283 { 0x56, 0x0111 },
284 { 0x57, 0x0064 },
285 { 0x58, 0xef0e },
286 { 0x59, 0xf0f0 },
287 { 0x5a, 0xef0e },
288 { 0x5b, 0xf0f0 },
289 { 0x5c, 0xef0e },
290 { 0x5d, 0xf0f0 },
291 { 0x5e, 0xf000 },
292 { 0x5f, 0x0000 },
293 { 0x61, 0x0300 },
294 { 0x62, 0x0000 },
295 { 0x63, 0x00c2 },
296 { 0x64, 0x0000 },
297 { 0x65, 0x0000 },
298 { 0x66, 0x0000 },
299 { 0x6a, 0x0000 },
300 { 0x6c, 0x0aaa },
301 { 0x70, 0x8000 },
302 { 0x71, 0x8000 },
303 { 0x72, 0x8000 },
304 { 0x73, 0x7770 },
305 { 0x74, 0x3e00 },
306 { 0x75, 0x2409 },
307 { 0x76, 0x000a },
308 { 0x77, 0x0c00 },
309 { 0x78, 0x0000 },
310 { 0x79, 0x0123 },
311 { 0x7a, 0x0123 },
312 { 0x80, 0x0000 },
313 { 0x81, 0x0000 },
314 { 0x82, 0x0000 },
315 { 0x83, 0x0000 },
316 { 0x84, 0x0000 },
317 { 0x85, 0x0000 },
e62ebf15 318 { 0x8a, 0x0120 },
49abc6cd
BL		 319 { 0x8e, 0x0004 },
320 { 0x8f, 0x1100 },
321 { 0x90, 0x0646 },
322 { 0x91, 0x0c06 },
323 { 0x93, 0x0000 },
324 { 0x94, 0x0200 },
325 { 0x95, 0x0000 },
326 { 0x9a, 0x2184 },
327 { 0x9b, 0x010a },
328 { 0x9c, 0x0aea },
329 { 0x9d, 0x000c },
330 { 0x9e, 0x0400 },
331 { 0xa0, 0xa0a8 },
332 { 0xa1, 0x0059 },
333 { 0xa2, 0x0001 },
334 { 0xae, 0x6000 },
335 { 0xaf, 0x0000 },
336 { 0xb0, 0x6000 },
337 { 0xb1, 0x0000 },
338 { 0xb2, 0x0000 },
339 { 0xb3, 0x001f },
340 { 0xb4, 0x020c },
341 { 0xb5, 0x1f00 },
342 { 0xb6, 0x0000 },
343 { 0xbb, 0x0000 },
344 { 0xbc, 0x0000 },
345 { 0xbd, 0x0000 },
346 { 0xbe, 0x0000 },
347 { 0xbf, 0x3100 },
348 { 0xc0, 0x0000 },
349 { 0xc1, 0x0000 },
350 { 0xc2, 0x0000 },
351 { 0xc3, 0x2000 },
352 { 0xcd, 0x0000 },
353 { 0xce, 0x0000 },
354 { 0xcf, 0x1813 },
355 { 0xd0, 0x0690 },
356 { 0xd1, 0x1c17 },
357 { 0xd3, 0xb320 },
358 { 0xd4, 0x0000 },
359 { 0xd6, 0x0400 },
360 { 0xd9, 0x0809 },
361 { 0xda, 0x0000 },
362 { 0xdb, 0x0003 },
363 { 0xdc, 0x0049 },
364 { 0xdd, 0x001b },
365 { 0xdf, 0x0008 },
366 { 0xe0, 0x4000 },
367 { 0xe6, 0x8000 },
368 { 0xe7, 0x0200 },
369 { 0xec, 0xb300 },
370 { 0xed, 0x0000 },
371 { 0xf0, 0x001f },
372 { 0xf1, 0x020c },
373 { 0xf2, 0x1f00 },
374 { 0xf3, 0x0000 },
375 { 0xf4, 0x4000 },
376 { 0xf8, 0x0000 },
377 { 0xf9, 0x0000 },
378 { 0xfa, 0x2060 },
379 { 0xfb, 0x4040 },
380 { 0xfc, 0x0000 },
381 { 0xfd, 0x0002 },
382 { 0xfe, 0x10ec },
383 { 0xff, 0x6308 },
384};
385
be77b38a
OC		 386struct rt5645_eq_param_s {
387 unsigned short reg;
388 unsigned short val;
389};
390
9fc114c5
KC		 391static const char *const rt5645_supply_names[] = {
392 "avdd",
393 "cpvdd",
394};
395
396struct rt5645_priv {
397 struct snd_soc_codec *codec;
398 struct rt5645_platform_data pdata;
399 struct regmap *regmap;
400 struct i2c_client *i2c;
401 struct gpio_desc *gpiod_hp_det;
402 struct snd_soc_jack *hp_jack;
403 struct snd_soc_jack *mic_jack;
404 struct snd_soc_jack *btn_jack;
7099ee85 405 struct delayed_work jack_detect_work, rcclock_work;
9fc114c5 406 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
be77b38a 407 struct rt5645_eq_param_s *eq_param;
7ff6319e 408 struct timer_list btn_check_timer;
9fc114c5
KC		 409
410 int codec_type;
411 int sysclk;
412 int sysclk_src;
413 int lrck[RT5645_AIFS];
414 int bclk[RT5645_AIFS];
415 int master[RT5645_AIFS];
416
417 int pll_src;
418 int pll_in;
419 int pll_out;
420
421 int jack_type;
422 bool en_button_func;
588cd850 423 bool hp_on;
9fc114c5
KC		 424};
425
1319b2f6
OC		 426static int rt5645_reset(struct snd_soc_codec *codec)
427{
428 return snd_soc_write(codec, RT5645_RESET, 0);
429}
430
431static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
432{
433 int i;
434
435 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
436 if (reg >= rt5645_ranges[i].range_min &&
437 reg <= rt5645_ranges[i].range_max) {
438 return true;
439 }
440 }
441
442 switch (reg) {
443 case RT5645_RESET:
81467efc 444 case RT5645_PRIV_INDEX:
1319b2f6
OC		 445 case RT5645_PRIV_DATA:
446 case RT5645_IN1_CTRL1:
447 case RT5645_IN1_CTRL2:
448 case RT5645_IN1_CTRL3:
449 case RT5645_A_JD_CTRL1:
450 case RT5645_ADC_EQ_CTRL1:
451 case RT5645_EQ_CTRL1:
452 case RT5645_ALC_CTRL_1:
453 case RT5645_IRQ_CTRL2:
454 case RT5645_IRQ_CTRL3:
455 case RT5645_INT_IRQ_ST:
456 case RT5645_IL_CMD:
5c4ca99d 457 case RT5650_4BTN_IL_CMD1:
1319b2f6
OC		 458 case RT5645_VENDOR_ID:
459 case RT5645_VENDOR_ID1:
460 case RT5645_VENDOR_ID2:
71bfa9b4 461 return true;
1319b2f6 462 default:
71bfa9b4 463 return false;
1319b2f6
OC		 464 }
465}
466
467static bool rt5645_readable_register(struct device *dev, unsigned int reg)
468{
469 int i;
470
471 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
472 if (reg >= rt5645_ranges[i].range_min &&
473 reg <= rt5645_ranges[i].range_max) {
474 return true;
475 }
476 }
477
478 switch (reg) {
479 case RT5645_RESET:
480 case RT5645_SPK_VOL:
481 case RT5645_HP_VOL:
482 case RT5645_LOUT1:
483 case RT5645_IN1_CTRL1:
484 case RT5645_IN1_CTRL2:
485 case RT5645_IN1_CTRL3:
486 case RT5645_IN2_CTRL:
487 case RT5645_INL1_INR1_VOL:
488 case RT5645_SPK_FUNC_LIM:
489 case RT5645_ADJ_HPF_CTRL:
490 case RT5645_DAC1_DIG_VOL:
491 case RT5645_DAC2_DIG_VOL:
492 case RT5645_DAC_CTRL:
493 case RT5645_STO1_ADC_DIG_VOL:
494 case RT5645_MONO_ADC_DIG_VOL:
495 case RT5645_ADC_BST_VOL1:
496 case RT5645_ADC_BST_VOL2:
497 case RT5645_STO1_ADC_MIXER:
498 case RT5645_MONO_ADC_MIXER:
499 case RT5645_AD_DA_MIXER:
500 case RT5645_STO_DAC_MIXER:
501 case RT5645_MONO_DAC_MIXER:
502 case RT5645_DIG_MIXER:
5c4ca99d 503 case RT5650_A_DAC_SOUR:
1319b2f6
OC		 504 case RT5645_DIG_INF1_DATA:
505 case RT5645_PDM_OUT_CTRL:
506 case RT5645_REC_L1_MIXER:
507 case RT5645_REC_L2_MIXER:
508 case RT5645_REC_R1_MIXER:
509 case RT5645_REC_R2_MIXER:
510 case RT5645_HPMIXL_CTRL:
511 case RT5645_HPOMIXL_CTRL:
512 case RT5645_HPMIXR_CTRL:
513 case RT5645_HPOMIXR_CTRL:
514 case RT5645_HPO_MIXER:
515 case RT5645_SPK_L_MIXER:
516 case RT5645_SPK_R_MIXER:
517 case RT5645_SPO_MIXER:
518 case RT5645_SPO_CLSD_RATIO:
519 case RT5645_OUT_L1_MIXER:
520 case RT5645_OUT_R1_MIXER:
521 case RT5645_OUT_L_GAIN1:
522 case RT5645_OUT_L_GAIN2:
523 case RT5645_OUT_R_GAIN1:
524 case RT5645_OUT_R_GAIN2:
525 case RT5645_LOUT_MIXER:
526 case RT5645_HAPTIC_CTRL1:
527 case RT5645_HAPTIC_CTRL2:
528 case RT5645_HAPTIC_CTRL3:
529 case RT5645_HAPTIC_CTRL4:
530 case RT5645_HAPTIC_CTRL5:
531 case RT5645_HAPTIC_CTRL6:
532 case RT5645_HAPTIC_CTRL7:
533 case RT5645_HAPTIC_CTRL8:
534 case RT5645_HAPTIC_CTRL9:
535 case RT5645_HAPTIC_CTRL10:
536 case RT5645_PWR_DIG1:
537 case RT5645_PWR_DIG2:
538 case RT5645_PWR_ANLG1:
539 case RT5645_PWR_ANLG2:
540 case RT5645_PWR_MIXER:
541 case RT5645_PWR_VOL:
542 case RT5645_PRIV_INDEX:
543 case RT5645_PRIV_DATA:
544 case RT5645_I2S1_SDP:
545 case RT5645_I2S2_SDP:
546 case RT5645_ADDA_CLK1:
547 case RT5645_ADDA_CLK2:
548 case RT5645_DMIC_CTRL1:
549 case RT5645_DMIC_CTRL2:
550 case RT5645_TDM_CTRL_1:
551 case RT5645_TDM_CTRL_2:
df078d29 552 case RT5645_TDM_CTRL_3:
1fcb76db 553 case RT5650_TDM_CTRL_4:
1319b2f6
OC		 554 case RT5645_GLB_CLK:
555 case RT5645_PLL_CTRL1:
556 case RT5645_PLL_CTRL2:
557 case RT5645_ASRC_1:
558 case RT5645_ASRC_2:
559 case RT5645_ASRC_3:
560 case RT5645_ASRC_4:
561 case RT5645_DEPOP_M1:
562 case RT5645_DEPOP_M2:
563 case RT5645_DEPOP_M3:
b1d42598 564 case RT5645_CHARGE_PUMP:
1319b2f6
OC		 565 case RT5645_MICBIAS:
566 case RT5645_A_JD_CTRL1:
567 case RT5645_VAD_CTRL4:
568 case RT5645_CLSD_OUT_CTRL:
569 case RT5645_ADC_EQ_CTRL1:
570 case RT5645_ADC_EQ_CTRL2:
571 case RT5645_EQ_CTRL1:
572 case RT5645_EQ_CTRL2:
573 case RT5645_ALC_CTRL_1:
574 case RT5645_ALC_CTRL_2:
575 case RT5645_ALC_CTRL_3:
576 case RT5645_ALC_CTRL_4:
577 case RT5645_ALC_CTRL_5:
578 case RT5645_JD_CTRL:
579 case RT5645_IRQ_CTRL1:
580 case RT5645_IRQ_CTRL2:
581 case RT5645_IRQ_CTRL3:
582 case RT5645_INT_IRQ_ST:
583 case RT5645_GPIO_CTRL1:
584 case RT5645_GPIO_CTRL2:
585 case RT5645_GPIO_CTRL3:
586 case RT5645_BASS_BACK:
587 case RT5645_MP3_PLUS1:
588 case RT5645_MP3_PLUS2:
589 case RT5645_ADJ_HPF1:
590 case RT5645_ADJ_HPF2:
591 case RT5645_HP_CALIB_AMP_DET:
592 case RT5645_SV_ZCD1:
593 case RT5645_SV_ZCD2:
594 case RT5645_IL_CMD:
595 case RT5645_IL_CMD2:
596 case RT5645_IL_CMD3:
5c4ca99d
BL		 597 case RT5650_4BTN_IL_CMD1:
598 case RT5650_4BTN_IL_CMD2:
1319b2f6
OC		 599 case RT5645_DRC1_HL_CTRL1:
600 case RT5645_DRC2_HL_CTRL1:
601 case RT5645_ADC_MONO_HP_CTRL1:
602 case RT5645_ADC_MONO_HP_CTRL2:
603 case RT5645_DRC2_CTRL1:
604 case RT5645_DRC2_CTRL2:
605 case RT5645_DRC2_CTRL3:
606 case RT5645_DRC2_CTRL4:
607 case RT5645_DRC2_CTRL5:
608 case RT5645_JD_CTRL3:
609 case RT5645_JD_CTRL4:
610 case RT5645_GEN_CTRL1:
611 case RT5645_GEN_CTRL2:
612 case RT5645_GEN_CTRL3:
613 case RT5645_VENDOR_ID:
614 case RT5645_VENDOR_ID1:
615 case RT5645_VENDOR_ID2:
71bfa9b4 616 return true;
1319b2f6 617 default:
71bfa9b4 618 return false;
1319b2f6
OC		 619 }
620}
621
622static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
177e1e1f 623static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1319b2f6 624static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
177e1e1f 625static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1319b2f6
OC		 626static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
627
628/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
6d698a83 629static const DECLARE_TLV_DB_RANGE(bst_tlv,
1319b2f6
OC		 630 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
631 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
632 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
633 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
634 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
635 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
6d698a83
LPC		 636 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
637);
1319b2f6 638
e29fd55d
OC		 639/* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
640static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
641 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
642 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
643 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
644 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
645);
646
be77b38a
OC		 647static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
648 struct snd_ctl_elem_info *uinfo)
649{
650 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
651 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
652
653 return 0;
654}
655
656static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
657 struct snd_ctl_elem_value *ucontrol)
658{
659 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
660 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
661 struct rt5645_eq_param_s *eq_param =
662 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data;
663 int i;
664
665 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
666 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
667 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
668 }
669
670 return 0;
671}
672
673static bool rt5645_validate_hweq(unsigned short reg)
674{
675 if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) |
676 (reg == RT5645_EQ_CTRL2))
677 return true;
678
679 return false;
680}
681
682static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
683 struct snd_ctl_elem_value *ucontrol)
684{
685 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
686 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
687 struct rt5645_eq_param_s *eq_param =
688 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data;
689 int i;
690
691 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
692 eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
693 eq_param[i].val = be16_to_cpu(eq_param[i].val);
694 }
695
696 /* The final setting of the table should be RT5645_EQ_CTRL2 */
697 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
698 if (eq_param[i].reg == 0)
699 continue;
700 else if (eq_param[i].reg != RT5645_EQ_CTRL2)
701 return 0;
702 else
703 break;
704 }
705
706 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
707 if (!rt5645_validate_hweq(eq_param[i].reg) &&
708 eq_param[i].reg != 0)
709 return 0;
710 else if (eq_param[i].reg == 0)
711 break;
712 }
713
714 memcpy(rt5645->eq_param, eq_param,
715 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s));
716
717 return 0;
718}
719
720#define RT5645_HWEQ(xname) \
721{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
722 .info = rt5645_hweq_info, \
723 .get = rt5645_hweq_get, \
724 .put = rt5645_hweq_put \
725}
726
7099ee85
OC		 727static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
728 struct snd_ctl_elem_value *ucontrol)
729{
730 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
731 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
732 int ret;
733
7099ee85
OC		 734 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
735 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
736
737 ret = snd_soc_put_volsw(kcontrol, ucontrol);
738
6e5b143c 739 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
7099ee85
OC		 740 msecs_to_jiffies(200));
741
742 return ret;
743}
744
467b1479
BL		 745static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
746 "immediately", "zero crossing", "soft ramp"
747};
748
749static SOC_ENUM_SINGLE_DECL(
750 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
751 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
752
1319b2f6
OC		 753static const struct snd_kcontrol_new rt5645_snd_controls[] = {
754 /* Speaker Output Volume */
755 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
756 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
7099ee85
OC		 757 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
758 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
759 rt5645_spk_put_volsw, out_vol_tlv),
1319b2f6 760
e29fd55d
OC		 761 /* ClassD modulator Speaker Gain Ratio */
762 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
763 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
764
1319b2f6 765 /* Headphone Output Volume */
692768c4 766 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
1319b2f6 767 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
692768c4 768 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
1319b2f6
OC		 769 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
770
771 /* OUTPUT Control */
772 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
773 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
774 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
775 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
776 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
777 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
778
779 /* DAC Digital Volume */
780 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
781 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
782 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
177e1e1f 783 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6 784 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
177e1e1f 785 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6
OC		 786
787 /* IN1/IN2 Control */
788 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
b28785fa 789 RT5645_BST_SFT1, 12, 0, bst_tlv),
1319b2f6
OC		 790 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
791 RT5645_BST_SFT2, 8, 0, bst_tlv),
792
793 /* INL/INR Volume Control */
794 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
795 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
796
797 /* ADC Digital Volume Control */
798 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
799 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
800 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
177e1e1f 801 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 802 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
803 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
804 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
177e1e1f 805 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 806
807 /* ADC Boost Volume Control */
8c1a9d63 808 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
1319b2f6
OC		 809 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
810 adc_bst_tlv),
8c1a9d63
OC		 811 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
812 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
1319b2f6
OC		 813 adc_bst_tlv),
814
815 /* I2S2 function select */
816 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
817 1, 1),
be77b38a 818 RT5645_HWEQ("Speaker HWEQ"),
467b1479
BL		 819
820 /* Digital Soft Volume Control */
821 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
1319b2f6
OC		 822};
823
824/**
825 * set_dmic_clk - Set parameter of dmic.
826 *
827 * @w: DAPM widget.
828 * @kcontrol: The kcontrol of this widget.
829 * @event: Event id.
830 *
1319b2f6
OC		 831 */
832static int set_dmic_clk(struct snd_soc_dapm_widget *w,
833 struct snd_kcontrol *kcontrol, int event)
834{
c5f596cb 835 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6 836 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
00a6d6e5 837 int idx, rate;
1319b2f6 838
00a6d6e5
OC		 839 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
840 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
841 idx = rl6231_calc_dmic_clk(rate);
1319b2f6
OC		 842 if (idx < 0)
843 dev_err(codec->dev, "Failed to set DMIC clock\n");
844 else
845 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
846 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
847 return idx;
848}
849
850static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
851 struct snd_soc_dapm_widget *sink)
852{
c5f596cb 853 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1319b2f6
OC		 854 unsigned int val;
855
c5f596cb 856 val = snd_soc_read(codec, RT5645_GLB_CLK);
1319b2f6
OC		 857 val &= RT5645_SCLK_SRC_MASK;
858 if (val == RT5645_SCLK_SRC_PLL1)
859 return 1;
860 else
861 return 0;
862}
863
9e268353
BL		 864static int is_using_asrc(struct snd_soc_dapm_widget *source,
865 struct snd_soc_dapm_widget *sink)
866{
c5f596cb 867 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
9e268353
BL		 868 unsigned int reg, shift, val;
869
870 switch (source->shift) {
871 case 0:
872 reg = RT5645_ASRC_3;
873 shift = 0;
874 break;
875 case 1:
876 reg = RT5645_ASRC_3;
877 shift = 4;
878 break;
879 case 3:
880 reg = RT5645_ASRC_2;
881 shift = 0;
882 break;
883 case 8:
884 reg = RT5645_ASRC_2;
885 shift = 4;
886 break;
887 case 9:
888 reg = RT5645_ASRC_2;
889 shift = 8;
890 break;
891 case 10:
892 reg = RT5645_ASRC_2;
893 shift = 12;
894 break;
895 default:
896 return 0;
897 }
898
c5f596cb 899 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
9e268353
BL		 900 switch (val) {
901 case 1:
902 case 2:
903 case 3:
904 case 4:
905 return 1;
906 default:
907 return 0;
908 }
909
910}
911
be77b38a
OC		 912static int rt5645_enable_hweq(struct snd_soc_codec *codec)
913{
914 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
915 int i;
916
917 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
918 if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
919 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
920 rt5645->eq_param[i].val);
921 else
922 break;
923 }
924
925 return 0;
926}
927
79080a8b
FY		 928/**
929 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
930 * @codec: SoC audio codec device.
931 * @filter_mask: mask of filters.
932 * @clk_src: clock source
933 *
934 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
935 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
936 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
937 * ASRC function will track i2s clock and generate a corresponding system clock
938 * for codec. This function provides an API to select the clock source for a
939 * set of filters specified by the mask. And the codec driver will turn on ASRC
940 * for these filters if ASRC is selected as their clock source.
941 */
942int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
943 unsigned int filter_mask, unsigned int clk_src)
944{
945 unsigned int asrc2_mask = 0;
946 unsigned int asrc2_value = 0;
947 unsigned int asrc3_mask = 0;
948 unsigned int asrc3_value = 0;
949
950 switch (clk_src) {
951 case RT5645_CLK_SEL_SYS:
952 case RT5645_CLK_SEL_I2S1_ASRC:
953 case RT5645_CLK_SEL_I2S2_ASRC:
954 case RT5645_CLK_SEL_SYS2:
955 break;
956
957 default:
958 return -EINVAL;
959 }
960
961 if (filter_mask & RT5645_DA_STEREO_FILTER) {
962 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
963 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
964 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
965 }
966
967 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
968 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
969 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
970 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
971 }
972
973 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
974 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
975 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
976 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
977 }
978
979 if (filter_mask & RT5645_AD_STEREO_FILTER) {
980 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
981 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
982 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
983 }
984
985 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
986 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
987 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
988 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
989 }
990
991 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
992 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
993 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
994 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
995 }
996
997 if (asrc2_mask)
998 snd_soc_update_bits(codec, RT5645_ASRC_2,
999 asrc2_mask, asrc2_value);
1000
1001 if (asrc3_mask)
1002 snd_soc_update_bits(codec, RT5645_ASRC_3,
1003 asrc3_mask, asrc3_value);
1004
1005 return 0;
1006}
1007EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
1008
1319b2f6
OC		 1009/* Digital Mixer */
1010static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
1011 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1012 RT5645_M_ADC_L1_SFT, 1, 1),
1013 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1014 RT5645_M_ADC_L2_SFT, 1, 1),
1015};
1016
1017static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
1018 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1019 RT5645_M_ADC_R1_SFT, 1, 1),
1020 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1021 RT5645_M_ADC_R2_SFT, 1, 1),
1022};
1023
1024static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
1025 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1026 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
1027 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1028 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
1029};
1030
1031static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
1032 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1033 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
1034 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1035 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
1036};
1037
1038static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
1039 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1040 RT5645_M_ADCMIX_L_SFT, 1, 1),
21cb13e7 1041 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1319b2f6
OC		 1042 RT5645_M_DAC1_L_SFT, 1, 1),
1043};
1044
1045static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
1046 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1047 RT5645_M_ADCMIX_R_SFT, 1, 1),
21cb13e7 1048 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1319b2f6
OC		 1049 RT5645_M_DAC1_R_SFT, 1, 1),
1050};
1051
1052static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
1053 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1054 RT5645_M_DAC_L1_SFT, 1, 1),
1055 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
1056 RT5645_M_DAC_L2_SFT, 1, 1),
1057 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1058 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
1059};
1060
1061static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
1062 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1063 RT5645_M_DAC_R1_SFT, 1, 1),
1064 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
1065 RT5645_M_DAC_R2_SFT, 1, 1),
1066 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1067 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
1068};
1069
1070static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
1071 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
1072 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
1073 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1074 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
1075 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1076 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
1077};
1078
1079static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
1080 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
1081 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
1082 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1083 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
1084 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1085 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
1086};
1087
1088static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
1089 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
1090 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
1091 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1092 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
1093 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1094 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
1095};
1096
1097static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
1098 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
1099 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
1100 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1101 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
1102 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1103 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
1104};
1105
1106/* Analog Input Mixer */
1107static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
1108 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
1109 RT5645_M_HP_L_RM_L_SFT, 1, 1),
1110 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
1111 RT5645_M_IN_L_RM_L_SFT, 1, 1),
1112 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
1113 RT5645_M_BST2_RM_L_SFT, 1, 1),
1114 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
1115 RT5645_M_BST1_RM_L_SFT, 1, 1),
1116 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
1117 RT5645_M_OM_L_RM_L_SFT, 1, 1),
1118};
1119
1120static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
1121 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
1122 RT5645_M_HP_R_RM_R_SFT, 1, 1),
1123 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
1124 RT5645_M_IN_R_RM_R_SFT, 1, 1),
1125 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
1126 RT5645_M_BST2_RM_R_SFT, 1, 1),
1127 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
1128 RT5645_M_BST1_RM_R_SFT, 1, 1),
1129 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
1130 RT5645_M_OM_R_RM_R_SFT, 1, 1),
1131};
1132
1133static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
1134 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
1135 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
1136 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
1137 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
1138 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
1139 RT5645_M_IN_L_SM_L_SFT, 1, 1),
1140 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
1141 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
1142};
1143
1144static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
1145 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1146 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
1147 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1148 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
1149 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
1150 RT5645_M_IN_R_SM_R_SFT, 1, 1),
1151 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
1152 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
1153};
1154
1155static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
1156 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
1157 RT5645_M_BST1_OM_L_SFT, 1, 1),
1158 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
1159 RT5645_M_IN_L_OM_L_SFT, 1, 1),
1160 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1161 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
1162 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
1163 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
1164};
1165
1166static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
1167 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1168 RT5645_M_BST2_OM_R_SFT, 1, 1),
1169 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1170 RT5645_M_IN_R_OM_R_SFT, 1, 1),
1171 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1172 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1173 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1174 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1175};
1176
1177static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1178 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1179 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1180 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1181 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1182 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1183 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1184 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1185 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1186};
1187
1188static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1189 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1190 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1191 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1192 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1193};
1194
1195static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1196 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1197 RT5645_M_DAC1_HM_SFT, 1, 1),
1198 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1199 RT5645_M_HPVOL_HM_SFT, 1, 1),
1200};
1201
1202static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1203 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1204 RT5645_M_DAC1_HV_SFT, 1, 1),
1205 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1206 RT5645_M_DAC2_HV_SFT, 1, 1),
1207 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1208 RT5645_M_IN_HV_SFT, 1, 1),
1209 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1210 RT5645_M_BST1_HV_SFT, 1, 1),
1211};
1212
1213static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1214 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1215 RT5645_M_DAC1_HV_SFT, 1, 1),
1216 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1217 RT5645_M_DAC2_HV_SFT, 1, 1),
1218 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1219 RT5645_M_IN_HV_SFT, 1, 1),
1220 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1221 RT5645_M_BST2_HV_SFT, 1, 1),
1222};
1223
1224static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1225 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1226 RT5645_M_DAC_L1_LM_SFT, 1, 1),
1227 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1228 RT5645_M_DAC_R1_LM_SFT, 1, 1),
1229 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1230 RT5645_M_OV_L_LM_SFT, 1, 1),
1231 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1232 RT5645_M_OV_R_LM_SFT, 1, 1),
1233};
1234
1235/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1236static const char * const rt5645_dac1_src[] = {
1237 "IF1 DAC", "IF2 DAC", "IF3 DAC"
1238};
1239
1240static SOC_ENUM_SINGLE_DECL(
1241 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1242 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1243
1244static const struct snd_kcontrol_new rt5645_dac1l_mux =
1245 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1246
1247static SOC_ENUM_SINGLE_DECL(
1248 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1249 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1250
1251static const struct snd_kcontrol_new rt5645_dac1r_mux =
1252 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1253
1254/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1255static const char * const rt5645_dac12_src[] = {
1256 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1257};
1258
1259static SOC_ENUM_SINGLE_DECL(
1260 rt5645_dac2l_enum, RT5645_DAC_CTRL,
1261 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1262
1263static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1264 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1265
1266static const char * const rt5645_dacr2_src[] = {
1267 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1268};
1269
1270static SOC_ENUM_SINGLE_DECL(
1271 rt5645_dac2r_enum, RT5645_DAC_CTRL,
1272 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1273
1274static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1275 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1276
1277
1278/* INL/R source */
1279static const char * const rt5645_inl_src[] = {
1280 "IN2P", "MonoP"
1281};
1282
1283static SOC_ENUM_SINGLE_DECL(
1284 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
1285 RT5645_INL_SEL_SFT, rt5645_inl_src);
1286
1287static const struct snd_kcontrol_new rt5645_inl_mux =
1288 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
1289
1290static const char * const rt5645_inr_src[] = {
1291 "IN2N", "MonoN"
1292};
1293
1294static SOC_ENUM_SINGLE_DECL(
1295 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
1296 RT5645_INR_SEL_SFT, rt5645_inr_src);
1297
1298static const struct snd_kcontrol_new rt5645_inr_mux =
1299 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
1300
1301/* Stereo1 ADC source */
1302/* MX-27 [12] */
1303static const char * const rt5645_stereo_adc1_src[] = {
1304 "DAC MIX", "ADC"
1305};
1306
1307static SOC_ENUM_SINGLE_DECL(
1308 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1309 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1310
1311static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1312 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1313
1314/* MX-27 [11] */
1315static const char * const rt5645_stereo_adc2_src[] = {
1316 "DAC MIX", "DMIC"
1317};
1318
1319static SOC_ENUM_SINGLE_DECL(
1320 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1321 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1322
1323static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1324 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1325
1326/* MX-27 [8] */
1327static const char * const rt5645_stereo_dmic_src[] = {
1328 "DMIC1", "DMIC2"
1329};
1330
1331static SOC_ENUM_SINGLE_DECL(
1332 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1333 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1334
1335static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1336 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1337
1338/* Mono ADC source */
1339/* MX-28 [12] */
1340static const char * const rt5645_mono_adc_l1_src[] = {
1341 "Mono DAC MIXL", "ADC"
1342};
1343
1344static SOC_ENUM_SINGLE_DECL(
1345 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1346 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1347
1348static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1349 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1350/* MX-28 [11] */
1351static const char * const rt5645_mono_adc_l2_src[] = {
1352 "Mono DAC MIXL", "DMIC"
1353};
1354
1355static SOC_ENUM_SINGLE_DECL(
1356 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1357 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1358
1359static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1360 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1361
1362/* MX-28 [8] */
1363static const char * const rt5645_mono_dmic_src[] = {
1364 "DMIC1", "DMIC2"
1365};
1366
1367static SOC_ENUM_SINGLE_DECL(
1368 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1369 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1370
1371static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1372 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1373/* MX-28 [1:0] */
1374static SOC_ENUM_SINGLE_DECL(
1375 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1376 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1377
1378static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1379 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1380/* MX-28 [4] */
1381static const char * const rt5645_mono_adc_r1_src[] = {
1382 "Mono DAC MIXR", "ADC"
1383};
1384
1385static SOC_ENUM_SINGLE_DECL(
1386 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1387 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1388
1389static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1390 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1391/* MX-28 [3] */
1392static const char * const rt5645_mono_adc_r2_src[] = {
1393 "Mono DAC MIXR", "DMIC"
1394};
1395
1396static SOC_ENUM_SINGLE_DECL(
1397 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1398 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1399
1400static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1401 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1402
1403/* MX-77 [9:8] */
1404static const char * const rt5645_if1_adc_in_src[] = {
21ab3f2b
BL		 1405 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1406 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1319b2f6
OC		 1407};
1408
1409static SOC_ENUM_SINGLE_DECL(
1410 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1411 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1412
1413static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1414 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1415
21ab3f2b
BL		 1416/* MX-78 [4:0] */
1417static const char * const rt5650_if1_adc_in_src[] = {
1418 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1419 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1420 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1421 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1422 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1423 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1424
1425 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1426 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1427 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1428 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1429 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1430 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1431
1432 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1433 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1434 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1435 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1436 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1437 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1438
1439 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1440 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1441 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1442 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1443 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1444 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1445};
1446
1447static SOC_ENUM_SINGLE_DECL(
1448 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1449 0, rt5650_if1_adc_in_src);
1450
1451static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1452 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1453
1454/* MX-78 [15:14][13:12][11:10] */
1455static const char * const rt5645_tdm_adc_swap_select[] = {
1456 "L/R", "R/L", "L/L", "R/R"
1457};
1458
1459static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1460 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1461
1462static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1463 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1464
1465static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1466 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1467
1468static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1469 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1470
1471static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1472 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1473
1474static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1475 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1476
1477/* MX-77 [7:6][5:4][3:2] */
1478static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1479 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1480
1481static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1482 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1483
1484static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1485 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1486
1487static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1488 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1489
1490static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1491 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1492
1493static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1494 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1495
1496/* MX-79 [14:12][10:8][6:4][2:0] */
1497static const char * const rt5645_tdm_dac_swap_select[] = {
1498 "Slot0", "Slot1", "Slot2", "Slot3"
1499};
1500
1501static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1502 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1503
1504static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1505 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1506
1507static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1508 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1509
1510static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1511 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1512
1513static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1514 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1515
1516static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1517 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1518
1519static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1520 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1521
1522static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1523 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1524
1525/* MX-7a [14:12][10:8][6:4][2:0] */
1526static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1527 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1528
1529static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1530 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1531
1532static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1533 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1534
1535static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1536 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1537
1538static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1539 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1540
1541static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1542 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1543
1544static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1545 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1546
1547static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1548 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1549
5c4ca99d
BL		 1550/* MX-2d [3] [2] */
1551static const char * const rt5650_a_dac1_src[] = {
1552 "DAC1", "Stereo DAC Mixer"
1553};
1554
1555static SOC_ENUM_SINGLE_DECL(
1556 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1557 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1558
1559static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1560 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1561
1562static SOC_ENUM_SINGLE_DECL(
1563 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1564 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1565
1566static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1567 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1568
1569/* MX-2d [1] [0] */
1570static const char * const rt5650_a_dac2_src[] = {
1571 "Stereo DAC Mixer", "Mono DAC Mixer"
1572};
1573
1574static SOC_ENUM_SINGLE_DECL(
1575 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1576 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1577
1578static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1579 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1580
1581static SOC_ENUM_SINGLE_DECL(
1582 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1583 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1584
1585static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1586 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1587
1319b2f6
OC		 1588/* MX-2F [13:12] */
1589static const char * const rt5645_if2_adc_in_src[] = {
1590 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1591};
1592
1593static SOC_ENUM_SINGLE_DECL(
1594 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1595 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1596
1597static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1598 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1599
1600/* MX-2F [1:0] */
1601static const char * const rt5645_if3_adc_in_src[] = {
1602 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1603};
1604
1605static SOC_ENUM_SINGLE_DECL(
1606 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1607 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1608
1609static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1610 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1611
1612/* MX-31 [15] [13] [11] [9] */
1613static const char * const rt5645_pdm_src[] = {
1614 "Mono DAC", "Stereo DAC"
1615};
1616
1617static SOC_ENUM_SINGLE_DECL(
1618 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1619 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1620
1621static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1622 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1623
1624static SOC_ENUM_SINGLE_DECL(
1625 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1626 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1627
1628static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1629 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1630
1631/* MX-9D [9:8] */
1632static const char * const rt5645_vad_adc_src[] = {
1633 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1634};
1635
1636static SOC_ENUM_SINGLE_DECL(
1637 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1638 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1639
1640static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1641 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1642
1643static const struct snd_kcontrol_new spk_l_vol_control =
1644 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1645 RT5645_L_MUTE_SFT, 1, 1);
1646
1647static const struct snd_kcontrol_new spk_r_vol_control =
1648 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1649 RT5645_R_MUTE_SFT, 1, 1);
1650
1651static const struct snd_kcontrol_new hp_l_vol_control =
1652 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1653 RT5645_L_MUTE_SFT, 1, 1);
1654
1655static const struct snd_kcontrol_new hp_r_vol_control =
1656 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1657 RT5645_R_MUTE_SFT, 1, 1);
1658
1659static const struct snd_kcontrol_new pdm1_l_vol_control =
1660 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1661 RT5645_M_PDM1_L, 1, 1);
1662
1663static const struct snd_kcontrol_new pdm1_r_vol_control =
1664 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1665 RT5645_M_PDM1_R, 1, 1);
1666
1667static void hp_amp_power(struct snd_soc_codec *codec, int on)
1668{
1669 static int hp_amp_power_count;
1670 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1671
1672 if (on) {
1673 if (hp_amp_power_count <= 0) {
d12d6c4e 1674 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
588cd850 1675 snd_soc_write(codec, RT5645_DEPOP_M2, 0x3100);
d12d6c4e
JL		 1676 snd_soc_write(codec, RT5645_CHARGE_PUMP,
1677 0x0e06);
588cd850
OC		 1678 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1679 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1680 RT5645_HP_DCC_INT1, 0x9f01);
1681 msleep(20);
1682 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1683 RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
d12d6c4e
JL		 1684 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1685 0x3e, 0x7400);
1686 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1687 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1688 RT5645_MAMP_INT_REG2, 0xfc00);
1689 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
3524be4b 1690 msleep(90);
588cd850 1691 rt5645->hp_on = true;
d12d6c4e
JL		 1692 } else {
1693 /* depop parameters */
1694 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1695 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1696 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1697 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1698 RT5645_HP_DCC_INT1, 0x9f01);
1699 mdelay(150);
1700 /* headphone amp power on */
1701 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1702 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1703 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1704 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1705 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1706 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1707 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1708 RT5645_PWR_HA,
1709 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1710 RT5645_PWR_HA);
1711 mdelay(5);
1712 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1713 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1714 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1715
1716 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1717 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1718 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1719 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1720 0x14, 0x1aaa);
1721 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1722 0x24, 0x0430);
1723 }
1319b2f6
OC		 1724 }
1725 hp_amp_power_count++;
1726 } else {
1727 hp_amp_power_count--;
1728 if (hp_amp_power_count <= 0) {
d12d6c4e
JL		 1729 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1730 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1731 0x3e, 0x7400);
1732 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1733 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1734 RT5645_MAMP_INT_REG2, 0xfc00);
1735 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1736 msleep(100);
1737 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1738
1739 } else {
1740 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1741 RT5645_HP_SG_MASK |
1742 RT5645_HP_L_SMT_MASK |
1743 RT5645_HP_R_SMT_MASK,
1744 RT5645_HP_SG_DIS |
1745 RT5645_HP_L_SMT_DIS |
1746 RT5645_HP_R_SMT_DIS);
1747 /* headphone amp power down */
1748 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1749 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1750 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1751 RT5645_PWR_HA, 0);
1752 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1753 RT5645_DEPOP_MASK, 0);
1754 }
1319b2f6
OC		 1755 }
1756 }
1757}
1758
1759static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1760 struct snd_kcontrol *kcontrol, int event)
1761{
c5f596cb 1762 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1763 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1764
1765 switch (event) {
1766 case SND_SOC_DAPM_POST_PMU:
1767 hp_amp_power(codec, 1);
1768 /* headphone unmute sequence */
d12d6c4e 1769 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1770 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1771 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1772 RT5645_CP_FQ3_MASK,
1773 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1774 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1775 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1776 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1777 RT5645_MAMP_INT_REG2, 0xfc00);
1778 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1779 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1780 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1781 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1782 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1783 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1784 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1785 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1786 msleep(40);
1787 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1788 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1789 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1790 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
5c4ca99d 1791 }
1319b2f6
OC		 1792 break;
1793
1794 case SND_SOC_DAPM_PRE_PMD:
1795 /* headphone mute sequence */
d12d6c4e 1796 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1797 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1798 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1799 RT5645_CP_FQ3_MASK,
1800 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1801 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1802 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1803 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1804 RT5645_MAMP_INT_REG2, 0xfc00);
1805 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1806 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1807 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1808 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1809 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1810 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1811 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1812 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1813 msleep(30);
5c4ca99d 1814 }
1319b2f6
OC		 1815 hp_amp_power(codec, 0);
1816 break;
1817
1818 default:
1819 return 0;
1820 }
1821
1822 return 0;
1823}
1824
1825static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1826 struct snd_kcontrol *kcontrol, int event)
1827{
c5f596cb 1828 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1829
1830 switch (event) {
1831 case SND_SOC_DAPM_POST_PMU:
be77b38a 1832 rt5645_enable_hweq(codec);
1319b2f6
OC		 1833 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1834 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1835 RT5645_PWR_CLS_D_L,
1836 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1837 RT5645_PWR_CLS_D_L);
ca8457bb
BL		 1838 snd_soc_update_bits(codec, RT5645_GEN_CTRL3,
1839 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
1319b2f6
OC		 1840 break;
1841
1842 case SND_SOC_DAPM_PRE_PMD:
ca8457bb
BL		 1843 snd_soc_update_bits(codec, RT5645_GEN_CTRL3,
1844 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
be77b38a 1845 snd_soc_write(codec, RT5645_EQ_CTRL2, 0);
1319b2f6
OC		 1846 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1847 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1848 RT5645_PWR_CLS_D_L, 0);
1849 break;
1850
1851 default:
1852 return 0;
1853 }
1854
1855 return 0;
1856}
1857
1858static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1859 struct snd_kcontrol *kcontrol, int event)
1860{
c5f596cb 1861 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1862
1863 switch (event) {
1864 case SND_SOC_DAPM_POST_PMU:
1865 hp_amp_power(codec, 1);
1866 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1867 RT5645_PWR_LM, RT5645_PWR_LM);
1868 snd_soc_update_bits(codec, RT5645_LOUT1,
1869 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1870 break;
1871
1872 case SND_SOC_DAPM_PRE_PMD:
1873 snd_soc_update_bits(codec, RT5645_LOUT1,
1874 RT5645_L_MUTE | RT5645_R_MUTE,
1875 RT5645_L_MUTE | RT5645_R_MUTE);
1876 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1877 RT5645_PWR_LM, 0);
1878 hp_amp_power(codec, 0);
1879 break;
1880
1881 default:
1882 return 0;
1883 }
1884
1885 return 0;
1886}
1887
1888static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1889 struct snd_kcontrol *kcontrol, int event)
1890{
c5f596cb 1891 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1892
1893 switch (event) {
1894 case SND_SOC_DAPM_POST_PMU:
1895 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1896 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1897 break;
1898
1899 case SND_SOC_DAPM_PRE_PMD:
1900 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1901 RT5645_PWR_BST2_P, 0);
1902 break;
1903
1904 default:
1905 return 0;
1906 }
1907
1908 return 0;
1909}
1910
588cd850
OC		 1911static int rt5650_hp_event(struct snd_soc_dapm_widget *w,
1912 struct snd_kcontrol *k, int event)
1913{
1914 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1915 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1916
1917 switch (event) {
1918 case SND_SOC_DAPM_POST_PMU:
1919 if (rt5645->hp_on) {
1920 msleep(100);
1921 rt5645->hp_on = false;
1922 }
1923 break;
1924
1925 default:
1926 return 0;
1927 }
1928
1929 return 0;
1930}
1931
1319b2f6
OC		 1932static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1933 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1934 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1935 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1936 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1937
1938 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1939 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1940 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1941 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1942
9e268353
BL		 1943 /* ASRC */
1944 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1945 11, 0, NULL, 0),
1946 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1947 12, 0, NULL, 0),
1948 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1949 10, 0, NULL, 0),
1950 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1951 9, 0, NULL, 0),
1952 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1953 8, 0, NULL, 0),
1954 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1955 7, 0, NULL, 0),
1956 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1957 5, 0, NULL, 0),
1958 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1959 4, 0, NULL, 0),
1960 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1961 3, 0, NULL, 0),
1962 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1963 1, 0, NULL, 0),
1964 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1965 0, 0, NULL, 0),
1966
1319b2f6
OC		 1967 /* Input Side */
1968 /* micbias */
1969 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1970 RT5645_PWR_MB1_BIT, 0),
1971 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1972 RT5645_PWR_MB2_BIT, 0),
1973 /* Input Lines */
1974 SND_SOC_DAPM_INPUT("DMIC L1"),
1975 SND_SOC_DAPM_INPUT("DMIC R1"),
1976 SND_SOC_DAPM_INPUT("DMIC L2"),
1977 SND_SOC_DAPM_INPUT("DMIC R2"),
1978
1979 SND_SOC_DAPM_INPUT("IN1P"),
1980 SND_SOC_DAPM_INPUT("IN1N"),
1981 SND_SOC_DAPM_INPUT("IN2P"),
1982 SND_SOC_DAPM_INPUT("IN2N"),
1983
1984 SND_SOC_DAPM_INPUT("Haptic Generator"),
1985
1986 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1987 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1988 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1989 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1990 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1991 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1992 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1993 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1994 /* Boost */
1995 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1996 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1997 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1998 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1999 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2000 /* Input Volume */
2001 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
2002 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
2003 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
2004 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
2005 /* REC Mixer */
2006 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
2007 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
2008 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
2009 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
2010 /* ADCs */
2011 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2012 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2013
2014 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
2015 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
2016 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
2017 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
2018
2019 /* ADC Mux */
2020 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2021 &rt5645_sto1_dmic_mux),
2022 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2023 &rt5645_sto_adc2_mux),
2024 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2025 &rt5645_sto_adc2_mux),
2026 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2027 &rt5645_sto_adc1_mux),
2028 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2029 &rt5645_sto_adc1_mux),
2030 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2031 &rt5645_mono_dmic_l_mux),
2032 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2033 &rt5645_mono_dmic_r_mux),
2034 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2035 &rt5645_mono_adc_l2_mux),
2036 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2037 &rt5645_mono_adc_l1_mux),
2038 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2039 &rt5645_mono_adc_r1_mux),
2040 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2041 &rt5645_mono_adc_r2_mux),
2042 /* ADC Mixer */
2043
2044 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
2045 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1319b2f6
OC		 2046 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2047 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
2048 NULL, 0),
2049 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2050 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
2051 NULL, 0),
2052 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
2053 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2054 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2055 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
2056 NULL, 0),
2057 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
2058 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2059 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2060 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
2061 NULL, 0),
2062
2063 /* ADC PGA */
2064 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2065 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2066 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2067 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2068 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2069 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2070 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2071 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2072 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2073 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2074
2075 /* IF1 2 Mux */
1319b2f6
OC		 2076 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
2077 0, 0, &rt5645_if2_adc_in_mux),
2078
2079 /* Digital Interface */
2080 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
2081 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
786aa09b 2082 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 2083 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2084 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
786aa09b 2085 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 2086 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2087 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2088 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2089 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
2090 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
2091 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2092 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2093 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2094 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2095
2096 /* Digital Interface Select */
2097 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
2098 0, 0, &rt5645_vad_adc_mux),
2099
2100 /* Audio Interface */
2101 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2102 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2103 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2104 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2105
2106 /* Output Side */
2107 /* DAC mixer before sound effect */
2108 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2109 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
2110 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2111 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
2112
2113 /* DAC2 channel Mux */
2114 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
2115 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
2116 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
2117 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
2118 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
2119 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
2120
2121 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
2122 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
2123
2124 /* DAC Mixer */
2125 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
2126 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
2127 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
2128 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2129 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
2130 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2131 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2132 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
2133 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2134 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
2135 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2136 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
2137 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2138 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
2139 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2140 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
2141 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2142 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
2143
2144 /* DACs */
2145 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
2146 0),
2147 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2148 0),
2149 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2150 0),
2151 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2152 0),
2153 /* OUT Mixer */
2154 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
2155 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
2156 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
2157 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
2158 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
2159 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
2160 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
2161 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
2162 /* Ouput Volume */
2163 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
2164 &spk_l_vol_control),
2165 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
2166 &spk_r_vol_control),
2167 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2168 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2169 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2170 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2171 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2172 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2173 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2174 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2175 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2176 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2177 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2178 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2179 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2180
2181 /* HPO/LOUT/Mono Mixer */
2182 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2183 ARRAY_SIZE(rt5645_spo_l_mix)),
2184 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2185 ARRAY_SIZE(rt5645_spo_r_mix)),
2186 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2187 ARRAY_SIZE(rt5645_hpo_mix)),
2188 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2189 ARRAY_SIZE(rt5645_lout_mix)),
2190
2191 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2192 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2193 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2194 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2195 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2196 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2197
2198 /* PDM */
2199 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2200 0, NULL, 0),
2201 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2202 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2203
2204 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2205 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2206
2207 /* Output Lines */
2208 SND_SOC_DAPM_OUTPUT("HPOL"),
2209 SND_SOC_DAPM_OUTPUT("HPOR"),
2210 SND_SOC_DAPM_OUTPUT("LOUTL"),
2211 SND_SOC_DAPM_OUTPUT("LOUTR"),
2212 SND_SOC_DAPM_OUTPUT("PDM1L"),
2213 SND_SOC_DAPM_OUTPUT("PDM1R"),
2214 SND_SOC_DAPM_OUTPUT("SPOL"),
2215 SND_SOC_DAPM_OUTPUT("SPOR"),
588cd850 2216 SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event),
1319b2f6
OC		 2217};
2218
83c09290
BL		 2219static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2220 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2221 &rt5645_if1_dac0_tdm_sel_mux),
2222 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2223 &rt5645_if1_dac1_tdm_sel_mux),
2224 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2225 &rt5645_if1_dac2_tdm_sel_mux),
2226 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2227 &rt5645_if1_dac3_tdm_sel_mux),
2228 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2229 0, 0, &rt5645_if1_adc_in_mux),
2230 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2231 0, 0, &rt5645_if1_adc1_in_mux),
2232 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2233 0, 0, &rt5645_if1_adc2_in_mux),
2234 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2235 0, 0, &rt5645_if1_adc3_in_mux),
1319b2f6
OC		 2236};
2237
5c4ca99d
BL		 2238static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2239 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2240 0, 0, &rt5650_a_dac1_l_mux),
2241 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2242 0, 0, &rt5650_a_dac1_r_mux),
2243 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2244 0, 0, &rt5650_a_dac2_l_mux),
2245 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2246 0, 0, &rt5650_a_dac2_r_mux),
851b81e8
MC		 2247
2248 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2249 0, 0, &rt5650_if1_adc1_in_mux),
2250 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2251 0, 0, &rt5650_if1_adc2_in_mux),
2252 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2253 0, 0, &rt5650_if1_adc3_in_mux),
2254 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2255 0, 0, &rt5650_if1_adc_in_mux),
2256
2257 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2258 &rt5650_if1_dac0_tdm_sel_mux),
2259 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2260 &rt5650_if1_dac1_tdm_sel_mux),
2261 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2262 &rt5650_if1_dac2_tdm_sel_mux),
2263 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2264 &rt5650_if1_dac3_tdm_sel_mux),
5c4ca99d
BL		 2265};
2266
1319b2f6 2267static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
9e268353 2268 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
9e268353
BL		 2269 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2270 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2271 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2272 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2273 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2274
2275 { "I2S1", NULL, "I2S1 ASRC" },
2276 { "I2S2", NULL, "I2S2 ASRC" },
2277
1319b2f6
OC		 2278 { "IN1P", NULL, "LDO2" },
2279 { "IN2P", NULL, "LDO2" },
2280
2281 { "DMIC1", NULL, "DMIC L1" },
2282 { "DMIC1", NULL, "DMIC R1" },
2283 { "DMIC2", NULL, "DMIC L2" },
2284 { "DMIC2", NULL, "DMIC R2" },
2285
2286 { "BST1", NULL, "IN1P" },
2287 { "BST1", NULL, "IN1N" },
2288 { "BST1", NULL, "JD Power" },
2289 { "BST1", NULL, "Mic Det Power" },
2290 { "BST2", NULL, "IN2P" },
2291 { "BST2", NULL, "IN2N" },
2292
2293 { "INL VOL", NULL, "IN2P" },
2294 { "INR VOL", NULL, "IN2N" },
2295
2296 { "RECMIXL", "HPOL Switch", "HPOL" },
2297 { "RECMIXL", "INL Switch", "INL VOL" },
2298 { "RECMIXL", "BST2 Switch", "BST2" },
2299 { "RECMIXL", "BST1 Switch", "BST1" },
2300 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2301
2302 { "RECMIXR", "HPOR Switch", "HPOR" },
2303 { "RECMIXR", "INR Switch", "INR VOL" },
2304 { "RECMIXR", "BST2 Switch", "BST2" },
2305 { "RECMIXR", "BST1 Switch", "BST1" },
2306 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2307
2308 { "ADC L", NULL, "RECMIXL" },
2309 { "ADC L", NULL, "ADC L power" },
2310 { "ADC R", NULL, "RECMIXR" },
2311 { "ADC R", NULL, "ADC R power" },
2312
2313 {"DMIC L1", NULL, "DMIC CLK"},
2314 {"DMIC L1", NULL, "DMIC1 Power"},
2315 {"DMIC R1", NULL, "DMIC CLK"},
2316 {"DMIC R1", NULL, "DMIC1 Power"},
2317 {"DMIC L2", NULL, "DMIC CLK"},
2318 {"DMIC L2", NULL, "DMIC2 Power"},
2319 {"DMIC R2", NULL, "DMIC CLK"},
2320 {"DMIC R2", NULL, "DMIC2 Power"},
2321
2322 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2323 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
9e268353 2324 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1319b2f6
OC		 2325
2326 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2327 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
9e268353 2328 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1319b2f6
OC		 2329
2330 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2331 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
9e268353 2332 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1319b2f6
OC		 2333
2334 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2335 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2336 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2337 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2338
2339 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2340 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2341 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2342 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2343
2344 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2345 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2346 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2347 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2348
2349 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2350 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2351 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2352 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2353
2354 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2355 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2356 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2357 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2358
2359 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2360 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2361 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2362
2363 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2364 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2365 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2366
2367 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2368 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2369 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2370 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2371
2372 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2373 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2374 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2375 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2376
2377 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2378 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2379 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2380
2381 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2382 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2383 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2384 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2385 { "VAD_ADC", NULL, "VAD ADC Mux" },
2386
1319b2f6
OC		 2387 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2388 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2389 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2390
2391 { "IF1 ADC", NULL, "I2S1" },
1319b2f6
OC		 2392 { "IF2 ADC", NULL, "I2S2" },
2393 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2394
1319b2f6
OC		 2395 { "AIF2TX", NULL, "IF2 ADC" },
2396
21ab3f2b 2397 { "IF1 DAC0", NULL, "AIF1RX" },
1319b2f6
OC		 2398 { "IF1 DAC1", NULL, "AIF1RX" },
2399 { "IF1 DAC2", NULL, "AIF1RX" },
21ab3f2b 2400 { "IF1 DAC3", NULL, "AIF1RX" },
1319b2f6
OC		 2401 { "IF2 DAC", NULL, "AIF2RX" },
2402
21ab3f2b 2403 { "IF1 DAC0", NULL, "I2S1" },
1319b2f6
OC		 2404 { "IF1 DAC1", NULL, "I2S1" },
2405 { "IF1 DAC2", NULL, "I2S1" },
21ab3f2b 2406 { "IF1 DAC3", NULL, "I2S1" },
1319b2f6
OC		 2407 { "IF2 DAC", NULL, "I2S2" },
2408
1319b2f6
OC		 2409 { "IF2 DAC L", NULL, "IF2 DAC" },
2410 { "IF2 DAC R", NULL, "IF2 DAC" },
2411
1319b2f6 2412 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1319b2f6
OC		 2413 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2414
2415 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2416 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2417 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2418 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2419 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2420 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2421
1319b2f6
OC		 2422 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2423 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2424 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2425 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2426 { "DAC L2 Volume", NULL, "dac mono left filter" },
2427
1319b2f6
OC		 2428 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2429 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2430 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2431 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2432 { "DAC R2 Volume", NULL, "dac mono right filter" },
2433
2434 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2435 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2436 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2437 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2438 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2439 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2440 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2441 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2442
2443 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2444 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2445 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2446 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2447 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2448 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2449 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2450 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2451
2452 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2453 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2454 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2455 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2456 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2457 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2458
1319b2f6 2459 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2460 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2461 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6
OC		 2462 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2463
2464 { "SPK MIXL", "BST1 Switch", "BST1" },
2465 { "SPK MIXL", "INL Switch", "INL VOL" },
2466 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2467 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2468 { "SPK MIXR", "BST2 Switch", "BST2" },
2469 { "SPK MIXR", "INR Switch", "INR VOL" },
2470 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2471 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2472
2473 { "OUT MIXL", "BST1 Switch", "BST1" },
2474 { "OUT MIXL", "INL Switch", "INL VOL" },
2475 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2476 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2477
2478 { "OUT MIXR", "BST2 Switch", "BST2" },
2479 { "OUT MIXR", "INR Switch", "INR VOL" },
2480 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2481 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2482
2483 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2484 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2485 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2486 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2487 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2488 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2489 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2490 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2491 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2492 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2493
2494 { "DAC 2", NULL, "DAC L2" },
2495 { "DAC 2", NULL, "DAC R2" },
2496 { "DAC 1", NULL, "DAC L1" },
2497 { "DAC 1", NULL, "DAC R1" },
2498 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2499 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2500 { "HPOVOL", NULL, "HPOVOL L" },
2501 { "HPOVOL", NULL, "HPOVOL R" },
2502 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2503 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2504
2505 { "SPKVOL L", "Switch", "SPK MIXL" },
2506 { "SPKVOL R", "Switch", "SPK MIXR" },
2507
2508 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2509 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2510 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2511 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2512 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2513 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2514
2515 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2516 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2517 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2518 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2519
2520 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2521 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2522 { "PDM1 L Mux", NULL, "PDM1 Power" },
2523 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2524 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2525 { "PDM1 R Mux", NULL, "PDM1 Power" },
2526
2527 { "HP amp", NULL, "HPO MIX" },
2528 { "HP amp", NULL, "JD Power" },
2529 { "HP amp", NULL, "Mic Det Power" },
2530 { "HP amp", NULL, "LDO2" },
2531 { "HPOL", NULL, "HP amp" },
2532 { "HPOR", NULL, "HP amp" },
2533
2534 { "LOUT amp", NULL, "LOUT MIX" },
2535 { "LOUTL", NULL, "LOUT amp" },
2536 { "LOUTR", NULL, "LOUT amp" },
2537
2538 { "PDM1 L", "Switch", "PDM1 L Mux" },
2539 { "PDM1 R", "Switch", "PDM1 R Mux" },
2540
2541 { "PDM1L", NULL, "PDM1 L" },
2542 { "PDM1R", NULL, "PDM1 R" },
2543
2544 { "SPK amp", NULL, "SPOL MIX" },
2545 { "SPK amp", NULL, "SPOR MIX" },
2546 { "SPOL", NULL, "SPK amp" },
2547 { "SPOR", NULL, "SPK amp" },
2548};
2549
5c4ca99d
BL		 2550static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2551 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2552 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2553 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2554 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2555
2556 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2557 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2558 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2559 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2560
2561 { "DAC L1", NULL, "A DAC1 L Mux" },
2562 { "DAC R1", NULL, "A DAC1 R Mux" },
2563 { "DAC L2", NULL, "A DAC2 L Mux" },
2564 { "DAC R2", NULL, "A DAC2 R Mux" },
21ab3f2b
BL		 2565
2566 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2567 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2568 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2569 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2570
2571 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2572 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2573 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2574 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2575
2576 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2577 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2578 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2579 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2580
2581 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2582 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2583 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2584
2585 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2586 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2587 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2588 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2589 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2590 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2591
2592 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2593 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2594 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2595 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2596 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2597 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2598
2599 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2600 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2601 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2602 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2603 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2604 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2605
2606 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2607 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2608 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2609 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2610 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2611 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2612 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2613
2614 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2615 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2616 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2617 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2618
2619 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2620 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2621 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2622 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2623
2624 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2625 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2626 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2627 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2628
2629 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2630 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2631 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2632 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2633
2634 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2635 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2636
2637 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2638 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2639};
2640
2641static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2642 { "DAC L1", NULL, "Stereo DAC MIXL" },
2643 { "DAC R1", NULL, "Stereo DAC MIXR" },
2644 { "DAC L2", NULL, "Mono DAC MIXL" },
2645 { "DAC R2", NULL, "Mono DAC MIXR" },
21ab3f2b
BL		 2646
2647 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2648 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2649 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2650 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2651
2652 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2653 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2654 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2655 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2656
2657 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2658 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2659 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2660 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2661
2662 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2663 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2664 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2665
2666 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2667 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2668 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2669 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2670 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2671
2672 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2673 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2674 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2675 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2676
2677 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2678 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2679 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2680 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2681
2682 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2683 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2684 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2685 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2686
2687 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2688 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2689 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2690 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2691
2692 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2693 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2694
2695 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2696 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2697};
2698
1319b2f6
OC		 2699static int rt5645_hw_params(struct snd_pcm_substream *substream,
2700 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2701{
2702 struct snd_soc_codec *codec = dai->codec;
2703 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736 2704 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
1319b2f6
OC		 2705 int pre_div, bclk_ms, frame_size;
2706
2707 rt5645->lrck[dai->id] = params_rate(params);
d92950e7 2708 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1319b2f6
OC		 2709 if (pre_div < 0) {
2710 dev_err(codec->dev, "Unsupported clock setting\n");
2711 return -EINVAL;
2712 }
2713 frame_size = snd_soc_params_to_frame_size(params);
2714 if (frame_size < 0) {
2715 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2716 return -EINVAL;
2717 }
57bf2736
BL		 2718
2719 switch (rt5645->codec_type) {
2720 case CODEC_TYPE_RT5650:
2721 dl_sft = 4;
2722 break;
2723 default:
2724 dl_sft = 2;
2725 break;
2726 }
2727
1319b2f6
OC		 2728 bclk_ms = frame_size > 32;
2729 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2730
2731 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2732 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2733 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2734 bclk_ms, pre_div, dai->id);
2735
2736 switch (params_width(params)) {
2737 case 16:
2738 break;
2739 case 20:
57bf2736 2740 val_len = 0x1;
1319b2f6
OC		 2741 break;
2742 case 24:
57bf2736 2743 val_len = 0x2;
1319b2f6
OC		 2744 break;
2745 case 8:
57bf2736 2746 val_len = 0x3;
1319b2f6
OC		 2747 break;
2748 default:
2749 return -EINVAL;
2750 }
2751
2752 switch (dai->id) {
2753 case RT5645_AIF1:
33de3d54
BL		 2754 mask_clk = RT5645_I2S_PD1_MASK;
2755 val_clk = pre_div << RT5645_I2S_PD1_SFT;
1319b2f6 2756 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2757 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2758 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2759 break;
2760 case RT5645_AIF2:
2761 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2762 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2763 pre_div << RT5645_I2S_PD2_SFT;
2764 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2765 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2766 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2767 break;
2768 default:
2769 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2770 return -EINVAL;
2771 }
2772
2773 return 0;
2774}
2775
2776static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2777{
2778 struct snd_soc_codec *codec = dai->codec;
2779 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736
BL		 2780 unsigned int reg_val = 0, pol_sft;
2781
2782 switch (rt5645->codec_type) {
2783 case CODEC_TYPE_RT5650:
2784 pol_sft = 8;
2785 break;
2786 default:
2787 pol_sft = 7;
2788 break;
2789 }
1319b2f6
OC		 2790
2791 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2792 case SND_SOC_DAIFMT_CBM_CFM:
2793 rt5645->master[dai->id] = 1;
2794 break;
2795 case SND_SOC_DAIFMT_CBS_CFS:
2796 reg_val |= RT5645_I2S_MS_S;
2797 rt5645->master[dai->id] = 0;
2798 break;
2799 default:
2800 return -EINVAL;
2801 }
2802
2803 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2804 case SND_SOC_DAIFMT_NB_NF:
2805 break;
2806 case SND_SOC_DAIFMT_IB_NF:
57bf2736 2807 reg_val |= (1 << pol_sft);
1319b2f6
OC		 2808 break;
2809 default:
2810 return -EINVAL;
2811 }
2812
2813 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2814 case SND_SOC_DAIFMT_I2S:
2815 break;
2816 case SND_SOC_DAIFMT_LEFT_J:
2817 reg_val |= RT5645_I2S_DF_LEFT;
2818 break;
2819 case SND_SOC_DAIFMT_DSP_A:
2820 reg_val |= RT5645_I2S_DF_PCM_A;
2821 break;
2822 case SND_SOC_DAIFMT_DSP_B:
2823 reg_val |= RT5645_I2S_DF_PCM_B;
2824 break;
2825 default:
2826 return -EINVAL;
2827 }
2828 switch (dai->id) {
2829 case RT5645_AIF1:
2830 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2831 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2832 RT5645_I2S_DF_MASK, reg_val);
2833 break;
8c325704
AL		 2834 case RT5645_AIF2:
2835 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2836 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2837 RT5645_I2S_DF_MASK, reg_val);
2838 break;
2839 default:
2840 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2841 return -EINVAL;
2842 }
2843 return 0;
2844}
2845
2846static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2847 int clk_id, unsigned int freq, int dir)
2848{
2849 struct snd_soc_codec *codec = dai->codec;
2850 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2851 unsigned int reg_val = 0;
2852
2853 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2854 return 0;
2855
2856 switch (clk_id) {
2857 case RT5645_SCLK_S_MCLK:
2858 reg_val |= RT5645_SCLK_SRC_MCLK;
2859 break;
2860 case RT5645_SCLK_S_PLL1:
2861 reg_val |= RT5645_SCLK_SRC_PLL1;
2862 break;
2863 case RT5645_SCLK_S_RCCLK:
2864 reg_val |= RT5645_SCLK_SRC_RCCLK;
2865 break;
2866 default:
2867 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2868 return -EINVAL;
2869 }
2870 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2871 RT5645_SCLK_SRC_MASK, reg_val);
2872 rt5645->sysclk = freq;
2873 rt5645->sysclk_src = clk_id;
2874
2875 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2876
2877 return 0;
2878}
2879
1319b2f6
OC		 2880static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2881 unsigned int freq_in, unsigned int freq_out)
2882{
2883 struct snd_soc_codec *codec = dai->codec;
2884 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
71c7a2d6 2885 struct rl6231_pll_code pll_code;
1319b2f6
OC		 2886 int ret;
2887
2888 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2889 freq_out == rt5645->pll_out)
2890 return 0;
2891
2892 if (!freq_in || !freq_out) {
2893 dev_dbg(codec->dev, "PLL disabled\n");
2894
2895 rt5645->pll_in = 0;
2896 rt5645->pll_out = 0;
2897 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2898 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2899 return 0;
2900 }
2901
2902 switch (source) {
2903 case RT5645_PLL1_S_MCLK:
2904 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2905 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2906 break;
2907 case RT5645_PLL1_S_BCLK1:
2908 case RT5645_PLL1_S_BCLK2:
2909 switch (dai->id) {
2910 case RT5645_AIF1:
2911 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2912 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2913 break;
2914 case RT5645_AIF2:
2915 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2916 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2917 break;
2918 default:
2919 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2920 return -EINVAL;
2921 }
2922 break;
2923 default:
2924 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2925 return -EINVAL;
2926 }
2927
71c7a2d6 2928 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1319b2f6
OC		 2929 if (ret < 0) {
2930 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2931 return ret;
2932 }
2933
2934 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2935 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2936 pll_code.n_code, pll_code.k_code);
2937
2938 snd_soc_write(codec, RT5645_PLL_CTRL1,
2939 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2940 snd_soc_write(codec, RT5645_PLL_CTRL2,
2941 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2942 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2943
2944 rt5645->pll_in = freq_in;
2945 rt5645->pll_out = freq_out;
2946 rt5645->pll_src = source;
2947
2948 return 0;
2949}
2950
2951static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2952 unsigned int rx_mask, int slots, int slot_width)
2953{
2954 struct snd_soc_codec *codec = dai->codec;
42ce5b8a
BL		 2955 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2956 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2957 unsigned int mask, val = 0;
2958
2959 switch (rt5645->codec_type) {
2960 case CODEC_TYPE_RT5650:
2961 en_sft = 15;
2962 i_slot_sft = 10;
2963 o_slot_sft = 8;
2964 i_width_sht = 6;
2965 o_width_sht = 4;
2966 mask = 0x8ff0;
2967 break;
2968 default:
2969 en_sft = 14;
2970 i_slot_sft = o_slot_sft = 12;
2971 i_width_sht = o_width_sht = 10;
2972 mask = 0x7c00;
2973 break;
2974 }
850577db 2975 if (rx_mask || tx_mask) {
42ce5b8a
BL		 2976 val |= (1 << en_sft);
2977 if (rt5645->codec_type == CODEC_TYPE_RT5645)
2978 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2979 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
850577db 2980 }
1319b2f6
OC		 2981
2982 switch (slots) {
2983 case 4:
42ce5b8a 2984 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
1319b2f6
OC		 2985 break;
2986 case 6:
42ce5b8a 2987 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
1319b2f6
OC		 2988 break;
2989 case 8:
42ce5b8a 2990 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
1319b2f6
OC		 2991 break;
2992 case 2:
2993 default:
2994 break;
2995 }
2996
2997 switch (slot_width) {
2998 case 20:
42ce5b8a 2999 val |= (1 << i_width_sht) | (1 << o_width_sht);
1319b2f6
OC		 3000 break;
3001 case 24:
42ce5b8a 3002 val |= (2 << i_width_sht) | (2 << o_width_sht);
1319b2f6
OC		 3003 break;
3004 case 32:
42ce5b8a 3005 val |= (3 << i_width_sht) | (3 << o_width_sht);
1319b2f6
OC		 3006 break;
3007 case 16:
3008 default:
3009 break;
3010 }
3011
42ce5b8a 3012 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
1319b2f6
OC		 3013
3014 return 0;
3015}
3016
3017static int rt5645_set_bias_level(struct snd_soc_codec *codec,
3018 enum snd_soc_bias_level level)
3019{
6e747d53
BL		 3020 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3021
1319b2f6 3022 switch (level) {
0b2e4959 3023 case SND_SOC_BIAS_PREPARE:
e2ada818 3024 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
1319b2f6
OC		 3025 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3026 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3027 RT5645_PWR_BG | RT5645_PWR_VREF2,
3028 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3029 RT5645_PWR_BG | RT5645_PWR_VREF2);
3030 mdelay(10);
3031 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3032 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3033 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3034 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
3035 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3036 }
3037 break;
3038
0b2e4959
BL		 3039 case SND_SOC_BIAS_STANDBY:
3040 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3041 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3042 RT5645_PWR_BG | RT5645_PWR_VREF2,
3043 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3044 RT5645_PWR_BG | RT5645_PWR_VREF2);
0150e8c0 3045 mdelay(10);
0b2e4959
BL		 3046 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3047 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3048 RT5645_PWR_FV1 | RT5645_PWR_FV2);
0150e8c0
JL		 3049 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
3050 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
3051 msleep(40);
3052 if (rt5645->en_button_func)
3053 queue_delayed_work(system_power_efficient_wq,
3054 &rt5645->jack_detect_work,
3055 msecs_to_jiffies(0));
3056 }
0b2e4959
BL		 3057 break;
3058
1319b2f6
OC		 3059 case SND_SOC_BIAS_OFF:
3060 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
6e747d53
BL		 3061 if (!rt5645->en_button_func)
3062 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
3063 RT5645_DIG_GATE_CTRL, 0);
0b2e4959
BL		 3064 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3065 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3066 RT5645_PWR_BG | RT5645_PWR_VREF2 |
3067 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
1319b2f6
OC		 3068 break;
3069
3070 default:
3071 break;
3072 }
1319b2f6
OC		 3073
3074 return 0;
3075}
3076
6e747d53
BL		 3077static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
3078 bool enable)
f3fa1bbd 3079{
e2ada818 3080 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
f3fa1bbd 3081
6e747d53 3082 if (enable) {
a4e3c5fa
NB		 3083 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
3084 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
3085 snd_soc_dapm_sync(dapm);
22f5d9f8 3086
15b0f4d4 3087 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
6e747d53
BL		 3088 snd_soc_update_bits(codec,
3089 RT5645_INT_IRQ_ST, 0x8, 0x8);
3090 snd_soc_update_bits(codec,
3091 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
3092 snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
3093 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
3094 snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
3095 } else {
3096 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
3097 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
22f5d9f8 3098
a4e3c5fa
NB		 3099 snd_soc_dapm_disable_pin(dapm, "ADC L power");
3100 snd_soc_dapm_disable_pin(dapm, "ADC R power");
3101 snd_soc_dapm_sync(dapm);
75945896 3102 }
6e747d53 3103}
f3fa1bbd 3104
6e747d53
BL		 3105static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
3106{
e2ada818 3107 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
6e747d53
BL		 3108 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3109 unsigned int val;
f3fa1bbd 3110
6e747d53 3111 if (jack_insert) {
05a9b46a
JL		 3112 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
3113
b14c9174
NB		 3114 /* for jack type detect */
3115 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3116 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
3117 snd_soc_dapm_sync(dapm);
3118 if (!dapm->card->instantiated) {
6e747d53
BL		 3119 /* Power up necessary bits for JD if dapm is
3120 not ready yet */
05a9b46a
JL		 3121 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
3122 RT5645_PWR_MB | RT5645_PWR_VREF2,
3123 RT5645_PWR_MB | RT5645_PWR_VREF2);
3124 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
6e747d53 3125 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
05a9b46a 3126 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
6e747d53
BL		 3127 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
3128 }
f3fa1bbd 3129
05a9b46a 3130 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
f2988afe
OC		 3131 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3132 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3133 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3134 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
05a9b46a 3135 msleep(100);
f2988afe
OC		 3136 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3137 RT5645_CBJ_MN_JD, 0);
05a9b46a 3138
8db7f56d 3139 msleep(600);
05a9b46a
JL		 3140 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
3141 val &= 0x7;
f3fa1bbd
OC		 3142 dev_dbg(codec->dev, "val = %d\n", val);
3143
6e747d53
BL		 3144 if (val == 1 || val == 2) {
3145 rt5645->jack_type = SND_JACK_HEADSET;
3146 if (rt5645->en_button_func) {
6e747d53
BL		 3147 rt5645_enable_push_button_irq(codec, true);
3148 }
3149 } else {
b14c9174
NB		 3150 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3151 snd_soc_dapm_sync(dapm);
6e747d53
BL		 3152 rt5645->jack_type = SND_JACK_HEADPHONE;
3153 }
917536ae
JL		 3154 if (rt5645->pdata.jd_invert)
3155 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
7ff6319e 3156 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
6e747d53
BL		 3157 } else { /* jack out */
3158 rt5645->jack_type = 0;
a4e3c5fa 3159
fce97b4d
OC		 3160 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
3161 RT5645_L_MUTE | RT5645_R_MUTE,
3162 RT5645_L_MUTE | RT5645_R_MUTE);
f2988afe
OC		 3163 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3164 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3165 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3166 RT5645_CBJ_BST1_EN, 0);
8db7f56d 3167
6e747d53
BL		 3168 if (rt5645->en_button_func)
3169 rt5645_enable_push_button_irq(codec, false);
a4e3c5fa
NB		 3170
3171 if (rt5645->pdata.jd_mode == 0)
3172 snd_soc_dapm_disable_pin(dapm, "LDO2");
3173 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3174 snd_soc_dapm_sync(dapm);
917536ae
JL		 3175 if (rt5645->pdata.jd_invert)
3176 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
7ff6319e 3177 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
f3fa1bbd
OC		 3178 }
3179
6e747d53 3180 return rt5645->jack_type;
f3fa1bbd
OC		 3181}
3182
f312bc59
NB		 3183static int rt5645_button_detect(struct snd_soc_codec *codec)
3184{
3185 int btn_type, val;
3186
3187 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
3188 pr_debug("val=0x%x\n", val);
3189 btn_type = val & 0xfff0;
3190 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
3191
3192 return btn_type;
3193}
3194
345b0f50 3195static irqreturn_t rt5645_irq(int irq, void *data);
d5660422 3196
f3fa1bbd 3197int rt5645_set_jack_detect(struct snd_soc_codec *codec,
6e747d53
BL		 3198 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3199 struct snd_soc_jack *btn_jack)
f3fa1bbd
OC		 3200{
3201 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3202
471f208a
BL		 3203 rt5645->hp_jack = hp_jack;
3204 rt5645->mic_jack = mic_jack;
6e747d53
BL		 3205 rt5645->btn_jack = btn_jack;
3206 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3207 rt5645->en_button_func = true;
3208 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3209 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
6e747d53
BL		 3210 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3211 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3212 }
345b0f50 3213 rt5645_irq(0, rt5645);
f3fa1bbd
OC		 3214
3215 return 0;
3216}
3217EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3218
cd6e82b8
OC		 3219static void rt5645_jack_detect_work(struct work_struct *work)
3220{
3221 struct rt5645_priv *rt5645 =
3222 container_of(work, struct rt5645_priv, jack_detect_work.work);
6e747d53
BL		 3223 int val, btn_type, gpio_state = 0, report = 0;
3224
f2a5ded3 3225 if (!rt5645->codec)
f136dce4 3226 return;
f2a5ded3 3227
6e747d53
BL		 3228 switch (rt5645->pdata.jd_mode) {
3229 case 0: /* Not using rt5645 JD */
0b0cefc8
OC		 3230 if (rt5645->gpiod_hp_det) {
3231 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3232 dev_dbg(rt5645->codec->dev, "gpio_state = %d\n",
3233 gpio_state);
3234 report = rt5645_jack_detect(rt5645->codec, gpio_state);
6e747d53
BL		 3235 }
3236 snd_soc_jack_report(rt5645->hp_jack,
3237 report, SND_JACK_HEADPHONE);
3238 snd_soc_jack_report(rt5645->mic_jack,
3239 report, SND_JACK_MICROPHONE);
f312bc59 3240 return;
6e747d53
BL		 3241 case 1: /* 2 port */
3242 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070;
3243 break;
3244 default: /* 1 port */
3245 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020;
3246 break;
3247
3248 }
3249
3250 switch (val) {
3251 /* jack in */
3252 case 0x30: /* 2 port */
3253 case 0x0: /* 1 port or 2 port */
3254 if (rt5645->jack_type == 0) {
3255 report = rt5645_jack_detect(rt5645->codec, 1);
3256 /* for push button and jack out */
3257 break;
3258 }
3259 btn_type = 0;
3260 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
3261 /* button pressed */
3262 report = SND_JACK_HEADSET;
3263 btn_type = rt5645_button_detect(rt5645->codec);
3264 /* rt5650 can report three kinds of button behavior,
3265 one click, double click and hold. However,
3266 currently we will report button pressed/released
3267 event. So all the three button behaviors are
3268 treated as button pressed. */
3269 switch (btn_type) {
3270 case 0x8000:
3271 case 0x4000:
3272 case 0x2000:
3273 report |= SND_JACK_BTN_0;
3274 break;
3275 case 0x1000:
3276 case 0x0800:
3277 case 0x0400:
3278 report |= SND_JACK_BTN_1;
3279 break;
3280 case 0x0200:
3281 case 0x0100:
3282 case 0x0080:
3283 report |= SND_JACK_BTN_2;
3284 break;
3285 case 0x0040:
3286 case 0x0020:
3287 case 0x0010:
3288 report |= SND_JACK_BTN_3;
3289 break;
3290 case 0x0000: /* unpressed */
3291 break;
3292 default:
3293 dev_err(rt5645->codec->dev,
3294 "Unexpected button code 0x%04x\n",
3295 btn_type);
3296 break;
3297 }
3298 }
3299 if (btn_type == 0)/* button release */
3300 report = rt5645->jack_type;
7ff6319e 3301 else {
381437dd
BL		 3302 mod_timer(&rt5645->btn_check_timer,
3303 msecs_to_jiffies(100));
7ff6319e 3304 }
6e747d53
BL		 3305
3306 break;
3307 /* jack out */
3308 case 0x70: /* 2 port */
3309 case 0x10: /* 2 port */
3310 case 0x20: /* 1 port */
3311 report = 0;
3312 snd_soc_update_bits(rt5645->codec,
3313 RT5645_INT_IRQ_ST, 0x1, 0x0);
3314 rt5645_jack_detect(rt5645->codec, 0);
3315 break;
3316 default:
3317 break;
3318 }
3319
3320 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3321 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3322 if (rt5645->en_button_func)
3323 snd_soc_jack_report(rt5645->btn_jack,
e0b5d906
BL		 3324 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3325 SND_JACK_BTN_2 | SND_JACK_BTN_3);
f312bc59 3326}
6e747d53 3327
7099ee85
OC		 3328static void rt5645_rcclock_work(struct work_struct *work)
3329{
3330 struct rt5645_priv *rt5645 =
3331 container_of(work, struct rt5645_priv, rcclock_work.work);
3332
3333 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3334 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3335}
3336
f312bc59
NB		 3337static irqreturn_t rt5645_irq(int irq, void *data)
3338{
3339 struct rt5645_priv *rt5645 = data;
3340
3341 queue_delayed_work(system_power_efficient_wq,
3342 &rt5645->jack_detect_work, msecs_to_jiffies(250));
6e747d53 3343
f312bc59 3344 return IRQ_HANDLED;
6e747d53
BL		 3345}
3346
7ff6319e
BL		 3347static void rt5645_btn_check_callback(unsigned long data)
3348{
3349 struct rt5645_priv *rt5645 = (struct rt5645_priv *)data;
3350
3351 queue_delayed_work(system_power_efficient_wq,
3352 &rt5645->jack_detect_work, msecs_to_jiffies(5));
3353}
3354
1319b2f6
OC		 3355static int rt5645_probe(struct snd_soc_codec *codec)
3356{
e2ada818 3357 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1319b2f6
OC		 3358 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3359
3360 rt5645->codec = codec;
3361
5c4ca99d
BL		 3362 switch (rt5645->codec_type) {
3363 case CODEC_TYPE_RT5645:
f2a76385 3364 snd_soc_dapm_new_controls(dapm,
83c09290
BL		 3365 rt5645_specific_dapm_widgets,
3366 ARRAY_SIZE(rt5645_specific_dapm_widgets));
e2ada818 3367 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3368 rt5645_specific_dapm_routes,
3369 ARRAY_SIZE(rt5645_specific_dapm_routes));
3370 break;
3371 case CODEC_TYPE_RT5650:
e2ada818 3372 snd_soc_dapm_new_controls(dapm,
5c4ca99d
BL		 3373 rt5650_specific_dapm_widgets,
3374 ARRAY_SIZE(rt5650_specific_dapm_widgets));
e2ada818 3375 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3376 rt5650_specific_dapm_routes,
3377 ARRAY_SIZE(rt5650_specific_dapm_routes));
3378 break;
3379 }
3380
bd1204cb 3381 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
1319b2f6 3382
bb656add 3383 /* for JD function */
ac4fc3ee 3384 if (rt5645->pdata.jd_mode) {
e2ada818
LPC		 3385 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3386 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3387 snd_soc_dapm_sync(dapm);
bb656add
BL		 3388 }
3389
be77b38a
OC		 3390 rt5645->eq_param = devm_kzalloc(codec->dev,
3391 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s), GFP_KERNEL);
3392
1319b2f6
OC		 3393 return 0;
3394}
3395
3396static int rt5645_remove(struct snd_soc_codec *codec)
3397{
3398 rt5645_reset(codec);
3399 return 0;
3400}
3401
3402#ifdef CONFIG_PM
3403static int rt5645_suspend(struct snd_soc_codec *codec)
3404{
3405 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3406
3407 regcache_cache_only(rt5645->regmap, true);
3408 regcache_mark_dirty(rt5645->regmap);
3409
3410 return 0;
3411}
3412
3413static int rt5645_resume(struct snd_soc_codec *codec)
3414{
3415 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3416
3417 regcache_cache_only(rt5645->regmap, false);
0f776efd 3418 regcache_sync(rt5645->regmap);
1319b2f6
OC		 3419
3420 return 0;
3421}
3422#else
3423#define rt5645_suspend NULL
3424#define rt5645_resume NULL
3425#endif
3426
3427#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3428#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3429 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3430
64793047 3431static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
1319b2f6
OC		 3432 .hw_params = rt5645_hw_params,
3433 .set_fmt = rt5645_set_dai_fmt,
3434 .set_sysclk = rt5645_set_dai_sysclk,
3435 .set_tdm_slot = rt5645_set_tdm_slot,
3436 .set_pll = rt5645_set_dai_pll,
3437};
3438
9e22f782 3439static struct snd_soc_dai_driver rt5645_dai[] = {
1319b2f6
OC		 3440 {
3441 .name = "rt5645-aif1",
3442 .id = RT5645_AIF1,
3443 .playback = {
3444 .stream_name = "AIF1 Playback",
3445 .channels_min = 1,
3446 .channels_max = 2,
3447 .rates = RT5645_STEREO_RATES,
3448 .formats = RT5645_FORMATS,
3449 },
3450 .capture = {
3451 .stream_name = "AIF1 Capture",
3452 .channels_min = 1,
fbe039bb 3453 .channels_max = 4,
1319b2f6
OC		 3454 .rates = RT5645_STEREO_RATES,
3455 .formats = RT5645_FORMATS,
3456 },
3457 .ops = &rt5645_aif_dai_ops,
3458 },
3459 {
3460 .name = "rt5645-aif2",
3461 .id = RT5645_AIF2,
3462 .playback = {
3463 .stream_name = "AIF2 Playback",
3464 .channels_min = 1,
3465 .channels_max = 2,
3466 .rates = RT5645_STEREO_RATES,
3467 .formats = RT5645_FORMATS,
3468 },
3469 .capture = {
3470 .stream_name = "AIF2 Capture",
3471 .channels_min = 1,
3472 .channels_max = 2,
3473 .rates = RT5645_STEREO_RATES,
3474 .formats = RT5645_FORMATS,
3475 },
3476 .ops = &rt5645_aif_dai_ops,
3477 },
3478};
3479
3480static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
3481 .probe = rt5645_probe,
3482 .remove = rt5645_remove,
3483 .suspend = rt5645_suspend,
3484 .resume = rt5645_resume,
3485 .set_bias_level = rt5645_set_bias_level,
3486 .idle_bias_off = true,
51712de1
KM		 3487 .component_driver = {
3488 .controls = rt5645_snd_controls,
3489 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3490 .dapm_widgets = rt5645_dapm_widgets,
3491 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3492 .dapm_routes = rt5645_dapm_routes,
3493 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3494 },
1319b2f6
OC		 3495};
3496
3497static const struct regmap_config rt5645_regmap = {
3498 .reg_bits = 8,
3499 .val_bits = 16,
afefc128 3500 .use_single_rw = true,
1319b2f6
OC		 3501 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3502 RT5645_PR_SPACING),
3503 .volatile_reg = rt5645_volatile_register,
3504 .readable_reg = rt5645_readable_register,
3505
3506 .cache_type = REGCACHE_RBTREE,
3507 .reg_defaults = rt5645_reg,
3508 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3509 .ranges = rt5645_ranges,
3510 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3511};
3512
49abc6cd
BL		 3513static const struct regmap_config rt5650_regmap = {
3514 .reg_bits = 8,
3515 .val_bits = 16,
3516 .use_single_rw = true,
3517 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3518 RT5645_PR_SPACING),
3519 .volatile_reg = rt5645_volatile_register,
3520 .readable_reg = rt5645_readable_register,
3521
3522 .cache_type = REGCACHE_RBTREE,
3523 .reg_defaults = rt5650_reg,
3524 .num_reg_defaults = ARRAY_SIZE(rt5650_reg),
3525 .ranges = rt5645_ranges,
3526 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3527};
3528
3529static const struct regmap_config temp_regmap = {
3530 .name="nocache",
3531 .reg_bits = 8,
3532 .val_bits = 16,
3533 .use_single_rw = true,
3534 .max_register = RT5645_VENDOR_ID2 + 1,
3535 .cache_type = REGCACHE_NONE,
3536};
3537
1319b2f6
OC		 3538static const struct i2c_device_id rt5645_i2c_id[] = {
3539 { "rt5645", 0 },
5c4ca99d 3540 { "rt5650", 0 },
1319b2f6
OC		 3541 { }
3542};
3543MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3544
3168c201 3545#ifdef CONFIG_ACPI
e2973769 3546static const struct acpi_device_id rt5645_acpi_match[] = {
3168c201
FY		 3547 { "10EC5645", 0 },
3548 { "10EC5650", 0 },
79c89031 3549 { "10EC5640", 0 },
3168c201
FY		 3550 {},
3551};
3552MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3553#endif
3554
9761c0f6 3555static struct rt5645_platform_data general_platform_data = {
ac4fc3ee 3556 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
78c34fd4 3557 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
78c34fd4
FY		 3558 .jd_mode = 3,
3559};
3560
0bc7d10c 3561static const struct dmi_system_id dmi_platform_intel_braswell[] = {
78c34fd4
FY		 3562 {
3563 .ident = "Intel Strago",
78c34fd4
FY		 3564 .matches = {
3565 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3566 },
3567 },
c1713485 3568 {
9761c0f6 3569 .ident = "Google Chrome",
6b3cecd1 3570 .matches = {
9761c0f6 3571 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
6b3cecd1
BL		 3572 },
3573 },
178ff7c6
JL		 3574 {
3575 .ident = "Google Setzer",
3576 .matches = {
3577 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
3578 },
3579 },
79c89031
VK		 3580 {
3581 .ident = "Microsoft Surface 3",
3582 .matches = {
3583 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
3584 },
3585 },
78c34fd4
FY		 3586 { }
3587};
3588
e9159e75
JL		 3589static struct rt5645_platform_data buddy_platform_data = {
3590 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3591 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3592 .jd_mode = 3,
917536ae 3593 .jd_invert = true,
e9159e75
JL		 3594};
3595
dc542fb4 3596static struct dmi_system_id dmi_platform_intel_broadwell[] = {
e9159e75
JL		 3597 {
3598 .ident = "Chrome Buddy",
e9159e75
JL		 3599 .matches = {
3600 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3601 },
3602 },
3603 { }
3604};
3605
9761c0f6
BL		 3606static bool rt5645_check_dp(struct device *dev)
3607{
3608 if (device_property_present(dev, "realtek,in2-differential") ||
3609 device_property_present(dev, "realtek,dmic1-data-pin") ||
3610 device_property_present(dev, "realtek,dmic2-data-pin") ||
3611 device_property_present(dev, "realtek,jd-mode"))
3612 return true;
3613
3614 return false;
3615}
e9159e75 3616
48edaa4b
OC		 3617static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3618{
3619 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3620 "realtek,in2-differential");
3621 device_property_read_u32(dev,
3622 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3623 device_property_read_u32(dev,
3624 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3625 device_property_read_u32(dev,
3626 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3627
3628 return 0;
3629}
3630
1319b2f6
OC		 3631static int rt5645_i2c_probe(struct i2c_client *i2c,
3632 const struct i2c_device_id *id)
3633{
3634 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3635 struct rt5645_priv *rt5645;
9fc114c5 3636 int ret, i;
1319b2f6 3637 unsigned int val;
49abc6cd 3638 struct regmap *regmap;
1319b2f6
OC		 3639
3640 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3641 GFP_KERNEL);
3642 if (rt5645 == NULL)
3643 return -ENOMEM;
3644
f3fa1bbd 3645 rt5645->i2c = i2c;
1319b2f6
OC		 3646 i2c_set_clientdata(i2c, rt5645);
3647
48edaa4b 3648 if (pdata)
1319b2f6 3649 rt5645->pdata = *pdata;
9761c0f6
BL		 3650 else if (dmi_check_system(dmi_platform_intel_broadwell))
3651 rt5645->pdata = buddy_platform_data;
3652 else if (rt5645_check_dp(&i2c->dev))
48edaa4b 3653 rt5645_parse_dt(rt5645, &i2c->dev);
9761c0f6
BL		 3654 else if (dmi_check_system(dmi_platform_intel_braswell))
3655 rt5645->pdata = general_platform_data;
1319b2f6 3656
25c8888a
AL		 3657 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3658 GPIOD_IN);
0b0cefc8
OC		 3659
3660 if (IS_ERR(rt5645->gpiod_hp_det)) {
0b0cefc8 3661 dev_err(&i2c->dev, "failed to initialize gpiod\n");
25c8888a 3662 return PTR_ERR(rt5645->gpiod_hp_det);
0b0cefc8
OC		 3663 }
3664
9fc114c5
KC		 3665 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3666 rt5645->supplies[i].supply = rt5645_supply_names[i];
3667
3668 ret = devm_regulator_bulk_get(&i2c->dev,
3669 ARRAY_SIZE(rt5645->supplies),
3670 rt5645->supplies);
3671 if (ret) {
3672 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3673 return ret;
3674 }
3675
3676 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3677 rt5645->supplies);
3678 if (ret) {
3679 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3680 return ret;
3681 }
3682
49abc6cd
BL		 3683 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3684 if (IS_ERR(regmap)) {
3685 ret = PTR_ERR(regmap);
3686 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3687 ret);
3688 return ret;
3689 }
3690 regmap_read(regmap, RT5645_VENDOR_ID2, &val);
5c4ca99d
BL		 3691
3692 switch (val) {
3693 case RT5645_DEVICE_ID:
49abc6cd 3694 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
5c4ca99d
BL		 3695 rt5645->codec_type = CODEC_TYPE_RT5645;
3696 break;
3697 case RT5650_DEVICE_ID:
49abc6cd 3698 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
5c4ca99d
BL		 3699 rt5645->codec_type = CODEC_TYPE_RT5650;
3700 break;
3701 default:
1319b2f6 3702 dev_err(&i2c->dev,
8f68e80f 3703 "Device with ID register %#x is not rt5645 or rt5650\n",
5c4ca99d 3704 val);
9fc114c5
KC		 3705 ret = -ENODEV;
3706 goto err_enable;
d12d6c4e
JL		 3707 }
3708
49abc6cd
BL		 3709 if (IS_ERR(rt5645->regmap)) {
3710 ret = PTR_ERR(rt5645->regmap);
3711 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3712 ret);
3713 return ret;
3714 }
3715
1319b2f6
OC		 3716 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3717
3718 ret = regmap_register_patch(rt5645->regmap, init_list,
3719 ARRAY_SIZE(init_list));
3720 if (ret != 0)
3721 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3722
5c4ca99d
BL		 3723 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3724 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3725 ARRAY_SIZE(rt5650_init_list));
3726 if (ret != 0)
3727 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3728 ret);
3729 }
3730
1319b2f6
OC		 3731 if (rt5645->pdata.in2_diff)
3732 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3733 RT5645_IN_DF2, RT5645_IN_DF2);
3734
ac4fc3ee 3735 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
1319b2f6
OC		 3736 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3737 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
ac4fc3ee
BL		 3738 }
3739 switch (rt5645->pdata.dmic1_data_pin) {
3740 case RT5645_DMIC_DATA_IN2N:
3741 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3742 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3743 break;
1319b2f6 3744
ac4fc3ee 3745 case RT5645_DMIC_DATA_GPIO5:
a094935e
BL		 3746 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3747 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
ac4fc3ee
BL		 3748 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3749 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3750 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3751 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3752 break;
1319b2f6 3753
ac4fc3ee
BL		 3754 case RT5645_DMIC_DATA_GPIO11:
3755 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3756 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3757 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3758 RT5645_GP11_PIN_MASK,
3759 RT5645_GP11_PIN_DMIC1_SDA);
3760 break;
1319b2f6 3761
ac4fc3ee
BL		 3762 default:
3763 break;
3764 }
1319b2f6 3765
ac4fc3ee
BL		 3766 switch (rt5645->pdata.dmic2_data_pin) {
3767 case RT5645_DMIC_DATA_IN2P:
3768 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3769 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3770 break;
1319b2f6 3771
ac4fc3ee
BL		 3772 case RT5645_DMIC_DATA_GPIO6:
3773 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3774 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3775 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3776 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3777 break;
1319b2f6 3778
ac4fc3ee
BL		 3779 case RT5645_DMIC_DATA_GPIO10:
3780 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3781 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3782 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3783 RT5645_GP10_PIN_MASK,
3784 RT5645_GP10_PIN_DMIC2_SDA);
3785 break;
1319b2f6 3786
ac4fc3ee
BL		 3787 case RT5645_DMIC_DATA_GPIO12:
3788 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3789 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3790 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3791 RT5645_GP12_PIN_MASK,
3792 RT5645_GP12_PIN_DMIC2_SDA);
3793 break;
1319b2f6 3794
ac4fc3ee
BL		 3795 default:
3796 break;
1319b2f6
OC		 3797 }
3798
ac4fc3ee 3799 if (rt5645->pdata.jd_mode) {
bb656add 3800 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
ac4fc3ee
BL		 3801 RT5645_IRQ_CLK_GATE_CTRL,
3802 RT5645_IRQ_CLK_GATE_CTRL);
bb656add 3803 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
ac4fc3ee 3804 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2d4e2d02
BL		 3805 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3806 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3807 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3808 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3809 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3810 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3811 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3812 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
3813 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3814 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3815 switch (rt5645->pdata.jd_mode) {
3816 case 1:
3817 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3818 RT5645_JD1_MODE_MASK,
3819 RT5645_JD1_MODE_0);
3820 break;
3821 case 2:
3822 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3823 RT5645_JD1_MODE_MASK,
3824 RT5645_JD1_MODE_1);
3825 break;
3826 case 3:
3827 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3828 RT5645_JD1_MODE_MASK,
3829 RT5645_JD1_MODE_2);
3830 break;
3831 default:
3832 break;
3833 }
3834 }
3835
7ff6319e
BL		 3836 if (rt5645->pdata.jd_invert) {
3837 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3838 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
7ff6319e 3839 }
381437dd
BL		 3840 setup_timer(&rt5645->btn_check_timer,
3841 rt5645_btn_check_callback, (unsigned long)rt5645);
7ff6319e 3842
7ea3470a 3843 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
7099ee85 3844 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
7ea3470a 3845
f3fa1bbd
OC		 3846 if (rt5645->i2c->irq) {
3847 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
3848 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3849 | IRQF_ONESHOT, "rt5645", rt5645);
5168c547 3850 if (ret) {
f3fa1bbd 3851 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
9fc114c5 3852 goto err_enable;
5168c547 3853 }
f3fa1bbd
OC		 3854 }
3855
5168c547
KC		 3856 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
3857 rt5645_dai, ARRAY_SIZE(rt5645_dai));
3858 if (ret)
3859 goto err_irq;
3860
3861 return 0;
3862
3863err_irq:
3864 if (rt5645->i2c->irq)
3865 free_irq(rt5645->i2c->irq, rt5645);
9fc114c5
KC		 3866err_enable:
3867 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
5168c547 3868 return ret;
1319b2f6
OC		 3869}
3870
3871static int rt5645_i2c_remove(struct i2c_client *i2c)
3872{
f3fa1bbd
OC		 3873 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3874
3875 if (i2c->irq)
3876 free_irq(i2c->irq, rt5645);
3877
cd6e82b8 3878 cancel_delayed_work_sync(&rt5645->jack_detect_work);
7099ee85 3879 cancel_delayed_work_sync(&rt5645->rcclock_work);
cd6e82b8 3880
1319b2f6 3881 snd_soc_unregister_codec(&i2c->dev);
9fc114c5 3882 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
1319b2f6
OC		 3883
3884 return 0;
3885}
3886
f2988afe
OC		 3887static void rt5645_i2c_shutdown(struct i2c_client *i2c)
3888{
3889 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3890
3891 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3892 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
3893 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
3894 RT5645_CBJ_MN_JD);
3895 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
3896 0);
a2c026cf
OC		 3897 msleep(20);
3898 regmap_write(rt5645->regmap, RT5645_RESET, 0);
f2988afe
OC		 3899}
3900
9e22f782 3901static struct i2c_driver rt5645_i2c_driver = {
1319b2f6
OC		 3902 .driver = {
3903 .name = "rt5645",
3168c201 3904 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
1319b2f6
OC		 3905 },
3906 .probe = rt5645_i2c_probe,
f2988afe
OC		 3907 .remove = rt5645_i2c_remove,
3908 .shutdown = rt5645_i2c_shutdown,
1319b2f6
OC		 3909 .id_table = rt5645_i2c_id,
3910};
3911module_i2c_driver(rt5645_i2c_driver);
3912
3913MODULE_DESCRIPTION("ASoC RT5645 driver");
3914MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3915MODULE_LICENSE("GPL v2");
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