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ASoC: rt5645: add API to select ASRC clock source
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / rt5645.c
CommitLineData
1319b2f6
OC		 1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
f3fa1bbd 20#include <linux/gpio.h>
1319b2f6
OC		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
49ef7925 30#include "rl6231.h"
1319b2f6
OC		 31#include "rt5645.h"
32
33#define RT5645_DEVICE_ID 0x6308
5c4ca99d 34#define RT5650_DEVICE_ID 0x6419
1319b2f6
OC		 35
36#define RT5645_PR_RANGE_BASE (0xff + 1)
37#define RT5645_PR_SPACING 0x100
38
39#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
40
41static const struct regmap_range_cfg rt5645_ranges[] = {
42 {
43 .name = "PR",
44 .range_min = RT5645_PR_BASE,
45 .range_max = RT5645_PR_BASE + 0xf8,
46 .selector_reg = RT5645_PRIV_INDEX,
47 .selector_mask = 0xff,
48 .selector_shift = 0x0,
49 .window_start = RT5645_PRIV_DATA,
50 .window_len = 0x1,
51 },
52};
53
54static const struct reg_default init_list[] = {
55 {RT5645_PR_BASE + 0x3d, 0x3600},
4809b96e
OC		 56 {RT5645_PR_BASE + 0x1c, 0xfd20},
57 {RT5645_PR_BASE + 0x20, 0x611f},
58 {RT5645_PR_BASE + 0x21, 0x4040},
59 {RT5645_PR_BASE + 0x23, 0x0004},
1319b2f6
OC		 60};
61#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
62
5c4ca99d
BL		 63static const struct reg_default rt5650_init_list[] = {
64 {0xf6, 0x0100},
65};
66
1319b2f6
OC		 67static const struct reg_default rt5645_reg[] = {
68 { 0x00, 0x0000 },
69 { 0x01, 0xc8c8 },
70 { 0x02, 0xc8c8 },
71 { 0x03, 0xc8c8 },
72 { 0x0a, 0x0002 },
73 { 0x0b, 0x2827 },
74 { 0x0c, 0xe000 },
75 { 0x0d, 0x0000 },
76 { 0x0e, 0x0000 },
77 { 0x0f, 0x0808 },
78 { 0x14, 0x3333 },
79 { 0x16, 0x4b00 },
80 { 0x18, 0x018b },
81 { 0x19, 0xafaf },
82 { 0x1a, 0xafaf },
83 { 0x1b, 0x0001 },
84 { 0x1c, 0x2f2f },
85 { 0x1d, 0x2f2f },
86 { 0x1e, 0x0000 },
87 { 0x20, 0x0000 },
88 { 0x27, 0x7060 },
89 { 0x28, 0x7070 },
90 { 0x29, 0x8080 },
91 { 0x2a, 0x5656 },
92 { 0x2b, 0x5454 },
93 { 0x2c, 0xaaa0 },
5c4ca99d 94 { 0x2d, 0x0000 },
1319b2f6
OC		 95 { 0x2f, 0x1002 },
96 { 0x31, 0x5000 },
97 { 0x32, 0x0000 },
98 { 0x33, 0x0000 },
99 { 0x34, 0x0000 },
100 { 0x35, 0x0000 },
101 { 0x3b, 0x0000 },
102 { 0x3c, 0x007f },
103 { 0x3d, 0x0000 },
104 { 0x3e, 0x007f },
105 { 0x3f, 0x0000 },
106 { 0x40, 0x001f },
107 { 0x41, 0x0000 },
108 { 0x42, 0x001f },
109 { 0x45, 0x6000 },
110 { 0x46, 0x003e },
111 { 0x47, 0x003e },
112 { 0x48, 0xf807 },
113 { 0x4a, 0x0004 },
114 { 0x4d, 0x0000 },
115 { 0x4e, 0x0000 },
116 { 0x4f, 0x01ff },
117 { 0x50, 0x0000 },
118 { 0x51, 0x0000 },
119 { 0x52, 0x01ff },
120 { 0x53, 0xf000 },
121 { 0x56, 0x0111 },
122 { 0x57, 0x0064 },
123 { 0x58, 0xef0e },
124 { 0x59, 0xf0f0 },
125 { 0x5a, 0xef0e },
126 { 0x5b, 0xf0f0 },
127 { 0x5c, 0xef0e },
128 { 0x5d, 0xf0f0 },
129 { 0x5e, 0xf000 },
130 { 0x5f, 0x0000 },
131 { 0x61, 0x0300 },
132 { 0x62, 0x0000 },
133 { 0x63, 0x00c2 },
134 { 0x64, 0x0000 },
135 { 0x65, 0x0000 },
136 { 0x66, 0x0000 },
137 { 0x6a, 0x0000 },
138 { 0x6c, 0x0aaa },
139 { 0x70, 0x8000 },
140 { 0x71, 0x8000 },
141 { 0x72, 0x8000 },
142 { 0x73, 0x7770 },
143 { 0x74, 0x3e00 },
144 { 0x75, 0x2409 },
145 { 0x76, 0x000a },
146 { 0x77, 0x0c00 },
147 { 0x78, 0x0000 },
df078d29 148 { 0x79, 0x0123 },
1319b2f6
OC		 149 { 0x80, 0x0000 },
150 { 0x81, 0x0000 },
151 { 0x82, 0x0000 },
152 { 0x83, 0x0000 },
153 { 0x84, 0x0000 },
154 { 0x85, 0x0000 },
155 { 0x8a, 0x0000 },
156 { 0x8e, 0x0004 },
157 { 0x8f, 0x1100 },
158 { 0x90, 0x0646 },
159 { 0x91, 0x0c06 },
160 { 0x93, 0x0000 },
161 { 0x94, 0x0200 },
162 { 0x95, 0x0000 },
163 { 0x9a, 0x2184 },
164 { 0x9b, 0x010a },
165 { 0x9c, 0x0aea },
166 { 0x9d, 0x000c },
167 { 0x9e, 0x0400 },
168 { 0xa0, 0xa0a8 },
169 { 0xa1, 0x0059 },
170 { 0xa2, 0x0001 },
171 { 0xae, 0x6000 },
172 { 0xaf, 0x0000 },
173 { 0xb0, 0x6000 },
174 { 0xb1, 0x0000 },
175 { 0xb2, 0x0000 },
176 { 0xb3, 0x001f },
177 { 0xb4, 0x020c },
178 { 0xb5, 0x1f00 },
179 { 0xb6, 0x0000 },
180 { 0xbb, 0x0000 },
181 { 0xbc, 0x0000 },
182 { 0xbd, 0x0000 },
183 { 0xbe, 0x0000 },
184 { 0xbf, 0x3100 },
185 { 0xc0, 0x0000 },
186 { 0xc1, 0x0000 },
187 { 0xc2, 0x0000 },
188 { 0xc3, 0x2000 },
189 { 0xcd, 0x0000 },
190 { 0xce, 0x0000 },
191 { 0xcf, 0x1813 },
192 { 0xd0, 0x0690 },
193 { 0xd1, 0x1c17 },
194 { 0xd3, 0xb320 },
195 { 0xd4, 0x0000 },
196 { 0xd6, 0x0400 },
197 { 0xd9, 0x0809 },
198 { 0xda, 0x0000 },
199 { 0xdb, 0x0003 },
200 { 0xdc, 0x0049 },
201 { 0xdd, 0x001b },
5c4ca99d
BL		 202 { 0xdf, 0x0008 },
203 { 0xe0, 0x4000 },
1319b2f6
OC		 204 { 0xe6, 0x8000 },
205 { 0xe7, 0x0200 },
206 { 0xec, 0xb300 },
207 { 0xed, 0x0000 },
208 { 0xf0, 0x001f },
209 { 0xf1, 0x020c },
210 { 0xf2, 0x1f00 },
211 { 0xf3, 0x0000 },
212 { 0xf4, 0x4000 },
213 { 0xf8, 0x0000 },
214 { 0xf9, 0x0000 },
215 { 0xfa, 0x2060 },
216 { 0xfb, 0x4040 },
217 { 0xfc, 0x0000 },
218 { 0xfd, 0x0002 },
219 { 0xfe, 0x10ec },
220 { 0xff, 0x6308 },
221};
222
223static int rt5645_reset(struct snd_soc_codec *codec)
224{
225 return snd_soc_write(codec, RT5645_RESET, 0);
226}
227
228static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
229{
230 int i;
231
232 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
233 if (reg >= rt5645_ranges[i].range_min &&
234 reg <= rt5645_ranges[i].range_max) {
235 return true;
236 }
237 }
238
239 switch (reg) {
240 case RT5645_RESET:
241 case RT5645_PRIV_DATA:
242 case RT5645_IN1_CTRL1:
243 case RT5645_IN1_CTRL2:
244 case RT5645_IN1_CTRL3:
245 case RT5645_A_JD_CTRL1:
246 case RT5645_ADC_EQ_CTRL1:
247 case RT5645_EQ_CTRL1:
248 case RT5645_ALC_CTRL_1:
249 case RT5645_IRQ_CTRL2:
250 case RT5645_IRQ_CTRL3:
251 case RT5645_INT_IRQ_ST:
252 case RT5645_IL_CMD:
5c4ca99d 253 case RT5650_4BTN_IL_CMD1:
1319b2f6
OC		 254 case RT5645_VENDOR_ID:
255 case RT5645_VENDOR_ID1:
256 case RT5645_VENDOR_ID2:
71bfa9b4 257 return true;
1319b2f6 258 default:
71bfa9b4 259 return false;
1319b2f6
OC		 260 }
261}
262
263static bool rt5645_readable_register(struct device *dev, unsigned int reg)
264{
265 int i;
266
267 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
268 if (reg >= rt5645_ranges[i].range_min &&
269 reg <= rt5645_ranges[i].range_max) {
270 return true;
271 }
272 }
273
274 switch (reg) {
275 case RT5645_RESET:
276 case RT5645_SPK_VOL:
277 case RT5645_HP_VOL:
278 case RT5645_LOUT1:
279 case RT5645_IN1_CTRL1:
280 case RT5645_IN1_CTRL2:
281 case RT5645_IN1_CTRL3:
282 case RT5645_IN2_CTRL:
283 case RT5645_INL1_INR1_VOL:
284 case RT5645_SPK_FUNC_LIM:
285 case RT5645_ADJ_HPF_CTRL:
286 case RT5645_DAC1_DIG_VOL:
287 case RT5645_DAC2_DIG_VOL:
288 case RT5645_DAC_CTRL:
289 case RT5645_STO1_ADC_DIG_VOL:
290 case RT5645_MONO_ADC_DIG_VOL:
291 case RT5645_ADC_BST_VOL1:
292 case RT5645_ADC_BST_VOL2:
293 case RT5645_STO1_ADC_MIXER:
294 case RT5645_MONO_ADC_MIXER:
295 case RT5645_AD_DA_MIXER:
296 case RT5645_STO_DAC_MIXER:
297 case RT5645_MONO_DAC_MIXER:
298 case RT5645_DIG_MIXER:
5c4ca99d 299 case RT5650_A_DAC_SOUR:
1319b2f6
OC		 300 case RT5645_DIG_INF1_DATA:
301 case RT5645_PDM_OUT_CTRL:
302 case RT5645_REC_L1_MIXER:
303 case RT5645_REC_L2_MIXER:
304 case RT5645_REC_R1_MIXER:
305 case RT5645_REC_R2_MIXER:
306 case RT5645_HPMIXL_CTRL:
307 case RT5645_HPOMIXL_CTRL:
308 case RT5645_HPMIXR_CTRL:
309 case RT5645_HPOMIXR_CTRL:
310 case RT5645_HPO_MIXER:
311 case RT5645_SPK_L_MIXER:
312 case RT5645_SPK_R_MIXER:
313 case RT5645_SPO_MIXER:
314 case RT5645_SPO_CLSD_RATIO:
315 case RT5645_OUT_L1_MIXER:
316 case RT5645_OUT_R1_MIXER:
317 case RT5645_OUT_L_GAIN1:
318 case RT5645_OUT_L_GAIN2:
319 case RT5645_OUT_R_GAIN1:
320 case RT5645_OUT_R_GAIN2:
321 case RT5645_LOUT_MIXER:
322 case RT5645_HAPTIC_CTRL1:
323 case RT5645_HAPTIC_CTRL2:
324 case RT5645_HAPTIC_CTRL3:
325 case RT5645_HAPTIC_CTRL4:
326 case RT5645_HAPTIC_CTRL5:
327 case RT5645_HAPTIC_CTRL6:
328 case RT5645_HAPTIC_CTRL7:
329 case RT5645_HAPTIC_CTRL8:
330 case RT5645_HAPTIC_CTRL9:
331 case RT5645_HAPTIC_CTRL10:
332 case RT5645_PWR_DIG1:
333 case RT5645_PWR_DIG2:
334 case RT5645_PWR_ANLG1:
335 case RT5645_PWR_ANLG2:
336 case RT5645_PWR_MIXER:
337 case RT5645_PWR_VOL:
338 case RT5645_PRIV_INDEX:
339 case RT5645_PRIV_DATA:
340 case RT5645_I2S1_SDP:
341 case RT5645_I2S2_SDP:
342 case RT5645_ADDA_CLK1:
343 case RT5645_ADDA_CLK2:
344 case RT5645_DMIC_CTRL1:
345 case RT5645_DMIC_CTRL2:
346 case RT5645_TDM_CTRL_1:
347 case RT5645_TDM_CTRL_2:
df078d29 348 case RT5645_TDM_CTRL_3:
1319b2f6
OC		 349 case RT5645_GLB_CLK:
350 case RT5645_PLL_CTRL1:
351 case RT5645_PLL_CTRL2:
352 case RT5645_ASRC_1:
353 case RT5645_ASRC_2:
354 case RT5645_ASRC_3:
355 case RT5645_ASRC_4:
356 case RT5645_DEPOP_M1:
357 case RT5645_DEPOP_M2:
358 case RT5645_DEPOP_M3:
359 case RT5645_MICBIAS:
360 case RT5645_A_JD_CTRL1:
361 case RT5645_VAD_CTRL4:
362 case RT5645_CLSD_OUT_CTRL:
363 case RT5645_ADC_EQ_CTRL1:
364 case RT5645_ADC_EQ_CTRL2:
365 case RT5645_EQ_CTRL1:
366 case RT5645_EQ_CTRL2:
367 case RT5645_ALC_CTRL_1:
368 case RT5645_ALC_CTRL_2:
369 case RT5645_ALC_CTRL_3:
370 case RT5645_ALC_CTRL_4:
371 case RT5645_ALC_CTRL_5:
372 case RT5645_JD_CTRL:
373 case RT5645_IRQ_CTRL1:
374 case RT5645_IRQ_CTRL2:
375 case RT5645_IRQ_CTRL3:
376 case RT5645_INT_IRQ_ST:
377 case RT5645_GPIO_CTRL1:
378 case RT5645_GPIO_CTRL2:
379 case RT5645_GPIO_CTRL3:
380 case RT5645_BASS_BACK:
381 case RT5645_MP3_PLUS1:
382 case RT5645_MP3_PLUS2:
383 case RT5645_ADJ_HPF1:
384 case RT5645_ADJ_HPF2:
385 case RT5645_HP_CALIB_AMP_DET:
386 case RT5645_SV_ZCD1:
387 case RT5645_SV_ZCD2:
388 case RT5645_IL_CMD:
389 case RT5645_IL_CMD2:
390 case RT5645_IL_CMD3:
5c4ca99d
BL		 391 case RT5650_4BTN_IL_CMD1:
392 case RT5650_4BTN_IL_CMD2:
1319b2f6
OC		 393 case RT5645_DRC1_HL_CTRL1:
394 case RT5645_DRC2_HL_CTRL1:
395 case RT5645_ADC_MONO_HP_CTRL1:
396 case RT5645_ADC_MONO_HP_CTRL2:
397 case RT5645_DRC2_CTRL1:
398 case RT5645_DRC2_CTRL2:
399 case RT5645_DRC2_CTRL3:
400 case RT5645_DRC2_CTRL4:
401 case RT5645_DRC2_CTRL5:
402 case RT5645_JD_CTRL3:
403 case RT5645_JD_CTRL4:
404 case RT5645_GEN_CTRL1:
405 case RT5645_GEN_CTRL2:
406 case RT5645_GEN_CTRL3:
407 case RT5645_VENDOR_ID:
408 case RT5645_VENDOR_ID1:
409 case RT5645_VENDOR_ID2:
71bfa9b4 410 return true;
1319b2f6 411 default:
71bfa9b4 412 return false;
1319b2f6
OC		 413 }
414}
415
416static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
417static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
418static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
419static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
420static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
421
422/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
423static unsigned int bst_tlv[] = {
424 TLV_DB_RANGE_HEAD(7),
425 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
426 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
427 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
428 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
429 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
430 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
431 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
432};
433
434static const char * const rt5645_tdm_data_swap_select[] = {
435 "L/R", "R/L", "L/L", "R/R"
436};
437
438static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
439 RT5645_TDM_CTRL_1, 6, rt5645_tdm_data_swap_select);
440
441static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
442 RT5645_TDM_CTRL_1, 4, rt5645_tdm_data_swap_select);
443
444static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
445 RT5645_TDM_CTRL_1, 2, rt5645_tdm_data_swap_select);
446
447static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot6_7_enum,
448 RT5645_TDM_CTRL_1, 0, rt5645_tdm_data_swap_select);
449
450static const char * const rt5645_tdm_adc_data_select[] = {
451 "1/2/R", "2/1/R", "R/1/2", "R/2/1"
452};
453
454static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum,
455 RT5645_TDM_CTRL_1, 8,
456 rt5645_tdm_adc_data_select);
457
458static const struct snd_kcontrol_new rt5645_snd_controls[] = {
459 /* Speaker Output Volume */
460 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
461 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
462 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
463 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
464
465 /* Headphone Output Volume */
466 SOC_DOUBLE("HP Channel Switch", RT5645_HP_VOL,
467 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
468 SOC_DOUBLE_TLV("HP Playback Volume", RT5645_HP_VOL,
469 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
470
471 /* OUTPUT Control */
472 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
473 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
474 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
475 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
476 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
477 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
478
479 /* DAC Digital Volume */
480 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
481 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
482 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
483 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
484 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
485 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
486
487 /* IN1/IN2 Control */
488 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
489 RT5645_BST_SFT1, 8, 0, bst_tlv),
490 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
491 RT5645_BST_SFT2, 8, 0, bst_tlv),
492
493 /* INL/INR Volume Control */
494 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
495 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
496
497 /* ADC Digital Volume Control */
498 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
499 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
500 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
501 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
502 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
503 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
504 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
505 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
506
507 /* ADC Boost Volume Control */
508 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
509 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
510 adc_bst_tlv),
511 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
512 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
513 adc_bst_tlv),
514
515 /* I2S2 function select */
516 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
517 1, 1),
518
519 /* TDM */
520 SOC_ENUM("TDM Adc Slot0 1 Data", rt5645_tdm_adc_slot0_1_enum),
521 SOC_ENUM("TDM Adc Slot2 3 Data", rt5645_tdm_adc_slot2_3_enum),
522 SOC_ENUM("TDM Adc Slot4 5 Data", rt5645_tdm_adc_slot4_5_enum),
523 SOC_ENUM("TDM Adc Slot6 7 Data", rt5645_tdm_adc_slot6_7_enum),
524 SOC_ENUM("TDM IF1 ADC DATA Sel", rt5645_tdm_adc_sel_enum),
525 SOC_SINGLE("TDM IF1_DAC1_L Sel", RT5645_TDM_CTRL_3, 12, 7, 0),
526 SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0),
527 SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0),
528 SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0),
529};
530
531/**
532 * set_dmic_clk - Set parameter of dmic.
533 *
534 * @w: DAPM widget.
535 * @kcontrol: The kcontrol of this widget.
536 * @event: Event id.
537 *
1319b2f6
OC		 538 */
539static int set_dmic_clk(struct snd_soc_dapm_widget *w,
540 struct snd_kcontrol *kcontrol, int event)
541{
542 struct snd_soc_codec *codec = w->codec;
543 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
49ef7925
OC		 544 int idx = -EINVAL;
545
546 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
1319b2f6
OC		 547
548 if (idx < 0)
549 dev_err(codec->dev, "Failed to set DMIC clock\n");
550 else
551 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
552 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
553 return idx;
554}
555
556static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
557 struct snd_soc_dapm_widget *sink)
558{
559 unsigned int val;
560
561 val = snd_soc_read(source->codec, RT5645_GLB_CLK);
562 val &= RT5645_SCLK_SRC_MASK;
563 if (val == RT5645_SCLK_SRC_PLL1)
564 return 1;
565 else
566 return 0;
567}
568
9e268353
BL		 569static int is_using_asrc(struct snd_soc_dapm_widget *source,
570 struct snd_soc_dapm_widget *sink)
571{
572 unsigned int reg, shift, val;
573
574 switch (source->shift) {
575 case 0:
576 reg = RT5645_ASRC_3;
577 shift = 0;
578 break;
579 case 1:
580 reg = RT5645_ASRC_3;
581 shift = 4;
582 break;
583 case 3:
584 reg = RT5645_ASRC_2;
585 shift = 0;
586 break;
587 case 8:
588 reg = RT5645_ASRC_2;
589 shift = 4;
590 break;
591 case 9:
592 reg = RT5645_ASRC_2;
593 shift = 8;
594 break;
595 case 10:
596 reg = RT5645_ASRC_2;
597 shift = 12;
598 break;
599 default:
600 return 0;
601 }
602
603 val = (snd_soc_read(source->codec, reg) >> shift) & 0xf;
604 switch (val) {
605 case 1:
606 case 2:
607 case 3:
608 case 4:
609 return 1;
610 default:
611 return 0;
612 }
613
614}
615
79080a8b
FY		 616/**
617 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
618 * @codec: SoC audio codec device.
619 * @filter_mask: mask of filters.
620 * @clk_src: clock source
621 *
622 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
623 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
624 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
625 * ASRC function will track i2s clock and generate a corresponding system clock
626 * for codec. This function provides an API to select the clock source for a
627 * set of filters specified by the mask. And the codec driver will turn on ASRC
628 * for these filters if ASRC is selected as their clock source.
629 */
630int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
631 unsigned int filter_mask, unsigned int clk_src)
632{
633 unsigned int asrc2_mask = 0;
634 unsigned int asrc2_value = 0;
635 unsigned int asrc3_mask = 0;
636 unsigned int asrc3_value = 0;
637
638 switch (clk_src) {
639 case RT5645_CLK_SEL_SYS:
640 case RT5645_CLK_SEL_I2S1_ASRC:
641 case RT5645_CLK_SEL_I2S2_ASRC:
642 case RT5645_CLK_SEL_SYS2:
643 break;
644
645 default:
646 return -EINVAL;
647 }
648
649 if (filter_mask & RT5645_DA_STEREO_FILTER) {
650 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
651 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
652 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
653 }
654
655 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
656 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
657 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
658 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
659 }
660
661 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
662 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
663 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
664 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
665 }
666
667 if (filter_mask & RT5645_AD_STEREO_FILTER) {
668 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
669 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
670 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
671 }
672
673 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
674 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
675 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
676 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
677 }
678
679 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
680 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
681 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
682 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
683 }
684
685 if (asrc2_mask)
686 snd_soc_update_bits(codec, RT5645_ASRC_2,
687 asrc2_mask, asrc2_value);
688
689 if (asrc3_mask)
690 snd_soc_update_bits(codec, RT5645_ASRC_3,
691 asrc3_mask, asrc3_value);
692
693 return 0;
694}
695EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
696
1319b2f6
OC		 697/* Digital Mixer */
698static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
699 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
700 RT5645_M_ADC_L1_SFT, 1, 1),
701 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
702 RT5645_M_ADC_L2_SFT, 1, 1),
703};
704
705static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
706 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
707 RT5645_M_ADC_R1_SFT, 1, 1),
708 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
709 RT5645_M_ADC_R2_SFT, 1, 1),
710};
711
712static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
713 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
714 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
715 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
716 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
717};
718
719static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
720 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
721 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
722 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
723 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
724};
725
726static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
727 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
728 RT5645_M_ADCMIX_L_SFT, 1, 1),
729 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
730 RT5645_M_DAC1_L_SFT, 1, 1),
731};
732
733static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
734 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
735 RT5645_M_ADCMIX_R_SFT, 1, 1),
736 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
737 RT5645_M_DAC1_R_SFT, 1, 1),
738};
739
740static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
741 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
742 RT5645_M_DAC_L1_SFT, 1, 1),
743 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
744 RT5645_M_DAC_L2_SFT, 1, 1),
745 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
746 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
747};
748
749static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
750 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
751 RT5645_M_DAC_R1_SFT, 1, 1),
752 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
753 RT5645_M_DAC_R2_SFT, 1, 1),
754 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
755 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
756};
757
758static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
759 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
760 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
761 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
762 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
763 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
764 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
765};
766
767static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
768 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
769 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
770 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
771 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
772 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
773 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
774};
775
776static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
777 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
778 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
779 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
780 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
781 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
782 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
783};
784
785static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
786 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
787 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
788 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
789 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
790 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
791 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
792};
793
794/* Analog Input Mixer */
795static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
796 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
797 RT5645_M_HP_L_RM_L_SFT, 1, 1),
798 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
799 RT5645_M_IN_L_RM_L_SFT, 1, 1),
800 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
801 RT5645_M_BST2_RM_L_SFT, 1, 1),
802 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
803 RT5645_M_BST1_RM_L_SFT, 1, 1),
804 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
805 RT5645_M_OM_L_RM_L_SFT, 1, 1),
806};
807
808static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
809 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
810 RT5645_M_HP_R_RM_R_SFT, 1, 1),
811 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
812 RT5645_M_IN_R_RM_R_SFT, 1, 1),
813 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
814 RT5645_M_BST2_RM_R_SFT, 1, 1),
815 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
816 RT5645_M_BST1_RM_R_SFT, 1, 1),
817 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
818 RT5645_M_OM_R_RM_R_SFT, 1, 1),
819};
820
821static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
822 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
823 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
824 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
825 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
826 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
827 RT5645_M_IN_L_SM_L_SFT, 1, 1),
828 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
829 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
830};
831
832static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
833 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
834 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
835 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
836 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
837 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
838 RT5645_M_IN_R_SM_R_SFT, 1, 1),
839 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
840 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
841};
842
843static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
844 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
845 RT5645_M_BST1_OM_L_SFT, 1, 1),
846 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
847 RT5645_M_IN_L_OM_L_SFT, 1, 1),
848 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
849 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
850 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
851 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
852};
853
854static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
855 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
856 RT5645_M_BST2_OM_R_SFT, 1, 1),
857 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
858 RT5645_M_IN_R_OM_R_SFT, 1, 1),
859 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
860 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
861 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
862 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
863};
864
865static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
866 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
867 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
868 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
869 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
870 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
871 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
872 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
873 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
874};
875
876static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
877 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
878 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
879 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
880 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
881};
882
883static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
884 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
885 RT5645_M_DAC1_HM_SFT, 1, 1),
886 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
887 RT5645_M_HPVOL_HM_SFT, 1, 1),
888};
889
890static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
891 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
892 RT5645_M_DAC1_HV_SFT, 1, 1),
893 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
894 RT5645_M_DAC2_HV_SFT, 1, 1),
895 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
896 RT5645_M_IN_HV_SFT, 1, 1),
897 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
898 RT5645_M_BST1_HV_SFT, 1, 1),
899};
900
901static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
902 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
903 RT5645_M_DAC1_HV_SFT, 1, 1),
904 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
905 RT5645_M_DAC2_HV_SFT, 1, 1),
906 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
907 RT5645_M_IN_HV_SFT, 1, 1),
908 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
909 RT5645_M_BST2_HV_SFT, 1, 1),
910};
911
912static const struct snd_kcontrol_new rt5645_lout_mix[] = {
913 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
914 RT5645_M_DAC_L1_LM_SFT, 1, 1),
915 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
916 RT5645_M_DAC_R1_LM_SFT, 1, 1),
917 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
918 RT5645_M_OV_L_LM_SFT, 1, 1),
919 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
920 RT5645_M_OV_R_LM_SFT, 1, 1),
921};
922
923/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
924static const char * const rt5645_dac1_src[] = {
925 "IF1 DAC", "IF2 DAC", "IF3 DAC"
926};
927
928static SOC_ENUM_SINGLE_DECL(
929 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
930 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
931
932static const struct snd_kcontrol_new rt5645_dac1l_mux =
933 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
934
935static SOC_ENUM_SINGLE_DECL(
936 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
937 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
938
939static const struct snd_kcontrol_new rt5645_dac1r_mux =
940 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
941
942/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
943static const char * const rt5645_dac12_src[] = {
944 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
945};
946
947static SOC_ENUM_SINGLE_DECL(
948 rt5645_dac2l_enum, RT5645_DAC_CTRL,
949 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
950
951static const struct snd_kcontrol_new rt5645_dac_l2_mux =
952 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
953
954static const char * const rt5645_dacr2_src[] = {
955 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
956};
957
958static SOC_ENUM_SINGLE_DECL(
959 rt5645_dac2r_enum, RT5645_DAC_CTRL,
960 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
961
962static const struct snd_kcontrol_new rt5645_dac_r2_mux =
963 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
964
965
966/* INL/R source */
967static const char * const rt5645_inl_src[] = {
968 "IN2P", "MonoP"
969};
970
971static SOC_ENUM_SINGLE_DECL(
972 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
973 RT5645_INL_SEL_SFT, rt5645_inl_src);
974
975static const struct snd_kcontrol_new rt5645_inl_mux =
976 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
977
978static const char * const rt5645_inr_src[] = {
979 "IN2N", "MonoN"
980};
981
982static SOC_ENUM_SINGLE_DECL(
983 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
984 RT5645_INR_SEL_SFT, rt5645_inr_src);
985
986static const struct snd_kcontrol_new rt5645_inr_mux =
987 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
988
989/* Stereo1 ADC source */
990/* MX-27 [12] */
991static const char * const rt5645_stereo_adc1_src[] = {
992 "DAC MIX", "ADC"
993};
994
995static SOC_ENUM_SINGLE_DECL(
996 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
997 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
998
999static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1000 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1001
1002/* MX-27 [11] */
1003static const char * const rt5645_stereo_adc2_src[] = {
1004 "DAC MIX", "DMIC"
1005};
1006
1007static SOC_ENUM_SINGLE_DECL(
1008 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1009 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1010
1011static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1012 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1013
1014/* MX-27 [8] */
1015static const char * const rt5645_stereo_dmic_src[] = {
1016 "DMIC1", "DMIC2"
1017};
1018
1019static SOC_ENUM_SINGLE_DECL(
1020 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1021 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1022
1023static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1024 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1025
1026/* Mono ADC source */
1027/* MX-28 [12] */
1028static const char * const rt5645_mono_adc_l1_src[] = {
1029 "Mono DAC MIXL", "ADC"
1030};
1031
1032static SOC_ENUM_SINGLE_DECL(
1033 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1034 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1035
1036static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1037 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1038/* MX-28 [11] */
1039static const char * const rt5645_mono_adc_l2_src[] = {
1040 "Mono DAC MIXL", "DMIC"
1041};
1042
1043static SOC_ENUM_SINGLE_DECL(
1044 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1045 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1046
1047static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1048 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1049
1050/* MX-28 [8] */
1051static const char * const rt5645_mono_dmic_src[] = {
1052 "DMIC1", "DMIC2"
1053};
1054
1055static SOC_ENUM_SINGLE_DECL(
1056 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1057 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1058
1059static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1060 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1061/* MX-28 [1:0] */
1062static SOC_ENUM_SINGLE_DECL(
1063 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1064 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1065
1066static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1067 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1068/* MX-28 [4] */
1069static const char * const rt5645_mono_adc_r1_src[] = {
1070 "Mono DAC MIXR", "ADC"
1071};
1072
1073static SOC_ENUM_SINGLE_DECL(
1074 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1075 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1076
1077static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1078 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1079/* MX-28 [3] */
1080static const char * const rt5645_mono_adc_r2_src[] = {
1081 "Mono DAC MIXR", "DMIC"
1082};
1083
1084static SOC_ENUM_SINGLE_DECL(
1085 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1086 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1087
1088static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1089 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1090
1091/* MX-77 [9:8] */
1092static const char * const rt5645_if1_adc_in_src[] = {
1093 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1094};
1095
1096static SOC_ENUM_SINGLE_DECL(
1097 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1098 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1099
1100static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1101 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1102
5c4ca99d
BL		 1103/* MX-2d [3] [2] */
1104static const char * const rt5650_a_dac1_src[] = {
1105 "DAC1", "Stereo DAC Mixer"
1106};
1107
1108static SOC_ENUM_SINGLE_DECL(
1109 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1110 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1111
1112static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1113 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1114
1115static SOC_ENUM_SINGLE_DECL(
1116 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1117 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1118
1119static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1120 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1121
1122/* MX-2d [1] [0] */
1123static const char * const rt5650_a_dac2_src[] = {
1124 "Stereo DAC Mixer", "Mono DAC Mixer"
1125};
1126
1127static SOC_ENUM_SINGLE_DECL(
1128 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1129 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1130
1131static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1132 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1133
1134static SOC_ENUM_SINGLE_DECL(
1135 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1136 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1137
1138static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1139 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1140
1319b2f6
OC		 1141/* MX-2F [13:12] */
1142static const char * const rt5645_if2_adc_in_src[] = {
1143 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1144};
1145
1146static SOC_ENUM_SINGLE_DECL(
1147 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1148 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1149
1150static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1151 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1152
1153/* MX-2F [1:0] */
1154static const char * const rt5645_if3_adc_in_src[] = {
1155 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1156};
1157
1158static SOC_ENUM_SINGLE_DECL(
1159 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1160 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1161
1162static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1163 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1164
1165/* MX-31 [15] [13] [11] [9] */
1166static const char * const rt5645_pdm_src[] = {
1167 "Mono DAC", "Stereo DAC"
1168};
1169
1170static SOC_ENUM_SINGLE_DECL(
1171 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1172 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1173
1174static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1175 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1176
1177static SOC_ENUM_SINGLE_DECL(
1178 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1179 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1180
1181static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1182 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1183
1184/* MX-9D [9:8] */
1185static const char * const rt5645_vad_adc_src[] = {
1186 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1187};
1188
1189static SOC_ENUM_SINGLE_DECL(
1190 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1191 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1192
1193static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1194 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1195
1196static const struct snd_kcontrol_new spk_l_vol_control =
1197 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1198 RT5645_L_MUTE_SFT, 1, 1);
1199
1200static const struct snd_kcontrol_new spk_r_vol_control =
1201 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1202 RT5645_R_MUTE_SFT, 1, 1);
1203
1204static const struct snd_kcontrol_new hp_l_vol_control =
1205 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1206 RT5645_L_MUTE_SFT, 1, 1);
1207
1208static const struct snd_kcontrol_new hp_r_vol_control =
1209 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1210 RT5645_R_MUTE_SFT, 1, 1);
1211
1212static const struct snd_kcontrol_new pdm1_l_vol_control =
1213 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1214 RT5645_M_PDM1_L, 1, 1);
1215
1216static const struct snd_kcontrol_new pdm1_r_vol_control =
1217 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1218 RT5645_M_PDM1_R, 1, 1);
1219
1220static void hp_amp_power(struct snd_soc_codec *codec, int on)
1221{
1222 static int hp_amp_power_count;
1223 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1224
1225 if (on) {
1226 if (hp_amp_power_count <= 0) {
1227 /* depop parameters */
1228 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1229 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1230 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1231 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1232 RT5645_HP_DCC_INT1, 0x9f01);
1233 mdelay(150);
1234 /* headphone amp power on */
1235 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1236 RT5645_PWR_FV1 | RT5645_PWR_FV2 , 0);
1237 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1238 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1239 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1240 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1241 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1242 RT5645_PWR_HA,
1243 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1244 RT5645_PWR_HA);
1245 mdelay(5);
1246 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1247 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1248 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1249
1250 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1251 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1252 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1253 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1254 0x14, 0x1aaa);
1255 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1256 0x24, 0x0430);
1257 }
1258 hp_amp_power_count++;
1259 } else {
1260 hp_amp_power_count--;
1261 if (hp_amp_power_count <= 0) {
1262 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1263 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1264 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1265 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1266 /* headphone amp power down */
1267 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1268 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1269 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1270 RT5645_PWR_HA, 0);
1271 }
1272 }
1273}
1274
1275static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1276 struct snd_kcontrol *kcontrol, int event)
1277{
1278 struct snd_soc_codec *codec = w->codec;
1279 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1280
1281 switch (event) {
1282 case SND_SOC_DAPM_POST_PMU:
1283 hp_amp_power(codec, 1);
1284 /* headphone unmute sequence */
5c4ca99d
BL		 1285 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1286 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1287 } else {
1288 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1289 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1290 RT5645_CP_FQ3_MASK,
1291 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1292 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1293 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1294 }
1319b2f6
OC		 1295 regmap_write(rt5645->regmap,
1296 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1297 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1298 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1299 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1300 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1301 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1302 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1303 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1304 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1305 msleep(40);
1306 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1307 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1308 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1309 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1310 break;
1311
1312 case SND_SOC_DAPM_PRE_PMD:
1313 /* headphone mute sequence */
5c4ca99d
BL		 1314 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1315 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1316 } else {
1317 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1318 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1319 RT5645_CP_FQ3_MASK,
1320 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1321 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1322 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1323 }
1319b2f6
OC		 1324 regmap_write(rt5645->regmap,
1325 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1326 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1327 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1328 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1329 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1330 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1331 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1332 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1333 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1334 msleep(30);
1335 hp_amp_power(codec, 0);
1336 break;
1337
1338 default:
1339 return 0;
1340 }
1341
1342 return 0;
1343}
1344
1345static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1346 struct snd_kcontrol *kcontrol, int event)
1347{
1348 struct snd_soc_codec *codec = w->codec;
1319b2f6
OC		 1349
1350 switch (event) {
1351 case SND_SOC_DAPM_POST_PMU:
1352 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1353 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1354 RT5645_PWR_CLS_D_L,
1355 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1356 RT5645_PWR_CLS_D_L);
1357 break;
1358
1359 case SND_SOC_DAPM_PRE_PMD:
1360 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1361 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1362 RT5645_PWR_CLS_D_L, 0);
1363 break;
1364
1365 default:
1366 return 0;
1367 }
1368
1369 return 0;
1370}
1371
1372static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1373 struct snd_kcontrol *kcontrol, int event)
1374{
1375 struct snd_soc_codec *codec = w->codec;
1376
1377 switch (event) {
1378 case SND_SOC_DAPM_POST_PMU:
1379 hp_amp_power(codec, 1);
1380 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1381 RT5645_PWR_LM, RT5645_PWR_LM);
1382 snd_soc_update_bits(codec, RT5645_LOUT1,
1383 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1384 break;
1385
1386 case SND_SOC_DAPM_PRE_PMD:
1387 snd_soc_update_bits(codec, RT5645_LOUT1,
1388 RT5645_L_MUTE | RT5645_R_MUTE,
1389 RT5645_L_MUTE | RT5645_R_MUTE);
1390 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1391 RT5645_PWR_LM, 0);
1392 hp_amp_power(codec, 0);
1393 break;
1394
1395 default:
1396 return 0;
1397 }
1398
1399 return 0;
1400}
1401
1402static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1403 struct snd_kcontrol *kcontrol, int event)
1404{
1405 struct snd_soc_codec *codec = w->codec;
1406
1407 switch (event) {
1408 case SND_SOC_DAPM_POST_PMU:
1409 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1410 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1411 break;
1412
1413 case SND_SOC_DAPM_PRE_PMD:
1414 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1415 RT5645_PWR_BST2_P, 0);
1416 break;
1417
1418 default:
1419 return 0;
1420 }
1421
1422 return 0;
1423}
1424
1425static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1426 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1427 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1428 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1429 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1430
1431 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1432 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1433 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1434 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1435
9e268353
BL		 1436 /* ASRC */
1437 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1438 11, 0, NULL, 0),
1439 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1440 12, 0, NULL, 0),
1441 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1442 10, 0, NULL, 0),
1443 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1444 9, 0, NULL, 0),
1445 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1446 8, 0, NULL, 0),
1447 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1448 7, 0, NULL, 0),
1449 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1450 5, 0, NULL, 0),
1451 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1452 4, 0, NULL, 0),
1453 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1454 3, 0, NULL, 0),
1455 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1456 1, 0, NULL, 0),
1457 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1458 0, 0, NULL, 0),
1459
1319b2f6
OC		 1460 /* Input Side */
1461 /* micbias */
1462 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1463 RT5645_PWR_MB1_BIT, 0),
1464 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1465 RT5645_PWR_MB2_BIT, 0),
1466 /* Input Lines */
1467 SND_SOC_DAPM_INPUT("DMIC L1"),
1468 SND_SOC_DAPM_INPUT("DMIC R1"),
1469 SND_SOC_DAPM_INPUT("DMIC L2"),
1470 SND_SOC_DAPM_INPUT("DMIC R2"),
1471
1472 SND_SOC_DAPM_INPUT("IN1P"),
1473 SND_SOC_DAPM_INPUT("IN1N"),
1474 SND_SOC_DAPM_INPUT("IN2P"),
1475 SND_SOC_DAPM_INPUT("IN2N"),
1476
1477 SND_SOC_DAPM_INPUT("Haptic Generator"),
1478
1479 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1480 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1481 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1482 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1483 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1484 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1485 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1486 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1487 /* Boost */
1488 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1489 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1490 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1491 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1492 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1493 /* Input Volume */
1494 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1495 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1496 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1497 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1498 /* REC Mixer */
1499 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1500 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1501 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1502 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1503 /* ADCs */
1504 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1505 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1506
1507 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1508 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1509 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1510 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1511
1512 /* ADC Mux */
1513 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1514 &rt5645_sto1_dmic_mux),
1515 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1516 &rt5645_sto_adc2_mux),
1517 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1518 &rt5645_sto_adc2_mux),
1519 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1520 &rt5645_sto_adc1_mux),
1521 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1522 &rt5645_sto_adc1_mux),
1523 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1524 &rt5645_mono_dmic_l_mux),
1525 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1526 &rt5645_mono_dmic_r_mux),
1527 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1528 &rt5645_mono_adc_l2_mux),
1529 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1530 &rt5645_mono_adc_l1_mux),
1531 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1532 &rt5645_mono_adc_r1_mux),
1533 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1534 &rt5645_mono_adc_r2_mux),
1535 /* ADC Mixer */
1536
1537 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1538 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1539 SND_SOC_DAPM_SUPPLY_S("adc stereo2 filter", 1, RT5645_PWR_DIG2,
1540 RT5645_PWR_ADC_S2F_BIT, 0, NULL, 0),
1541 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1542 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1543 NULL, 0),
1544 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1545 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1546 NULL, 0),
1547 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1548 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1549 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1550 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1551 NULL, 0),
1552 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1553 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1554 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1555 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1556 NULL, 0),
1557
1558 /* ADC PGA */
1559 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1560 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1561 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1562 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1563 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1564 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1565 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1566 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1567 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1568 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1569
1570 /* IF1 2 Mux */
1571 SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM,
1572 0, 0, &rt5645_if1_adc_in_mux),
1573 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1574 0, 0, &rt5645_if2_adc_in_mux),
1575
1576 /* Digital Interface */
1577 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1578 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1579 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1580 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1581 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1582 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1583 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1584 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1585 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1586 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1587 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1588 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1589 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1590 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1591 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1592 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1593 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1594
1595 /* Digital Interface Select */
1596 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1597 0, 0, &rt5645_vad_adc_mux),
1598
1599 /* Audio Interface */
1600 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1601 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1602 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1603 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1604
1605 /* Output Side */
1606 /* DAC mixer before sound effect */
1607 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1608 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1609 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1610 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1611
1612 /* DAC2 channel Mux */
1613 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1614 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1615 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1616 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1617 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1618 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1619
1620 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1621 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1622
1623 /* DAC Mixer */
1624 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1625 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1626 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1627 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1628 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1629 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1630 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1631 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1632 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1633 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1634 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1635 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1636 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1637 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1638 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1639 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1640 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1641 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1642
1643 /* DACs */
1644 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1645 0),
1646 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1647 0),
1648 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1649 0),
1650 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1651 0),
1652 /* OUT Mixer */
1653 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1654 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1655 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1656 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1657 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1658 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1659 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1660 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1661 /* Ouput Volume */
1662 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1663 &spk_l_vol_control),
1664 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1665 &spk_r_vol_control),
1666 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1667 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1668 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1669 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1670 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1671 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1672 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1673 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1674 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1675 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1676 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1677 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1678 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1679
1680 /* HPO/LOUT/Mono Mixer */
1681 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1682 ARRAY_SIZE(rt5645_spo_l_mix)),
1683 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1684 ARRAY_SIZE(rt5645_spo_r_mix)),
1685 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1686 ARRAY_SIZE(rt5645_hpo_mix)),
1687 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1688 ARRAY_SIZE(rt5645_lout_mix)),
1689
1690 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1691 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1692 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1693 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1694 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1695 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1696
1697 /* PDM */
1698 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1699 0, NULL, 0),
1700 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1701 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1702
1703 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1704 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1705
1706 /* Output Lines */
1707 SND_SOC_DAPM_OUTPUT("HPOL"),
1708 SND_SOC_DAPM_OUTPUT("HPOR"),
1709 SND_SOC_DAPM_OUTPUT("LOUTL"),
1710 SND_SOC_DAPM_OUTPUT("LOUTR"),
1711 SND_SOC_DAPM_OUTPUT("PDM1L"),
1712 SND_SOC_DAPM_OUTPUT("PDM1R"),
1713 SND_SOC_DAPM_OUTPUT("SPOL"),
1714 SND_SOC_DAPM_OUTPUT("SPOR"),
1715};
1716
5c4ca99d
BL		 1717static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
1718 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
1719 0, 0, &rt5650_a_dac1_l_mux),
1720 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
1721 0, 0, &rt5650_a_dac1_r_mux),
1722 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
1723 0, 0, &rt5650_a_dac2_l_mux),
1724 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
1725 0, 0, &rt5650_a_dac2_r_mux),
1726};
1727
1319b2f6 1728static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
9e268353
BL		 1729 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
1730 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
1731 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1732 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1733 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1734 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1735 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1736
1737 { "I2S1", NULL, "I2S1 ASRC" },
1738 { "I2S2", NULL, "I2S2 ASRC" },
1739
1319b2f6
OC		 1740 { "IN1P", NULL, "LDO2" },
1741 { "IN2P", NULL, "LDO2" },
1742
1743 { "DMIC1", NULL, "DMIC L1" },
1744 { "DMIC1", NULL, "DMIC R1" },
1745 { "DMIC2", NULL, "DMIC L2" },
1746 { "DMIC2", NULL, "DMIC R2" },
1747
1748 { "BST1", NULL, "IN1P" },
1749 { "BST1", NULL, "IN1N" },
1750 { "BST1", NULL, "JD Power" },
1751 { "BST1", NULL, "Mic Det Power" },
1752 { "BST2", NULL, "IN2P" },
1753 { "BST2", NULL, "IN2N" },
1754
1755 { "INL VOL", NULL, "IN2P" },
1756 { "INR VOL", NULL, "IN2N" },
1757
1758 { "RECMIXL", "HPOL Switch", "HPOL" },
1759 { "RECMIXL", "INL Switch", "INL VOL" },
1760 { "RECMIXL", "BST2 Switch", "BST2" },
1761 { "RECMIXL", "BST1 Switch", "BST1" },
1762 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1763
1764 { "RECMIXR", "HPOR Switch", "HPOR" },
1765 { "RECMIXR", "INR Switch", "INR VOL" },
1766 { "RECMIXR", "BST2 Switch", "BST2" },
1767 { "RECMIXR", "BST1 Switch", "BST1" },
1768 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1769
1770 { "ADC L", NULL, "RECMIXL" },
1771 { "ADC L", NULL, "ADC L power" },
1772 { "ADC R", NULL, "RECMIXR" },
1773 { "ADC R", NULL, "ADC R power" },
1774
1775 {"DMIC L1", NULL, "DMIC CLK"},
1776 {"DMIC L1", NULL, "DMIC1 Power"},
1777 {"DMIC R1", NULL, "DMIC CLK"},
1778 {"DMIC R1", NULL, "DMIC1 Power"},
1779 {"DMIC L2", NULL, "DMIC CLK"},
1780 {"DMIC L2", NULL, "DMIC2 Power"},
1781 {"DMIC R2", NULL, "DMIC CLK"},
1782 {"DMIC R2", NULL, "DMIC2 Power"},
1783
1784 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1785 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
9e268353 1786 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1319b2f6
OC		 1787
1788 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1789 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
9e268353 1790 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1319b2f6
OC		 1791
1792 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1793 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
9e268353 1794 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1319b2f6
OC		 1795
1796 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1797 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1798 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1799 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1800
1801 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1802 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1803 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1804 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1805
1806 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1807 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1808 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1809 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1810
1811 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1812 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1813 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1814 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1815
1816 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1817 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1818 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1819 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1820
1821 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1822 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1823 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1824
1825 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1826 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1827 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1828
1829 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1830 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1831 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1832 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1833
1834 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1835 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1836 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1837 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1838
1839 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1840 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1841 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1842
1843 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1844 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1845 { "IF_ADC2", NULL, "Mono ADC MIXL" },
1846 { "IF_ADC2", NULL, "Mono ADC MIXR" },
1847 { "VAD_ADC", NULL, "VAD ADC Mux" },
1848
1849 { "IF1 ADC Mux", "IF_ADC1", "IF_ADC1" },
1850 { "IF1 ADC Mux", "IF_ADC2", "IF_ADC2" },
1851 { "IF1 ADC Mux", "VAD_ADC", "VAD_ADC" },
1852
1853 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1854 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1855 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1856
1857 { "IF1 ADC", NULL, "I2S1" },
1858 { "IF1 ADC", NULL, "IF1 ADC Mux" },
1859 { "IF2 ADC", NULL, "I2S2" },
1860 { "IF2 ADC", NULL, "IF2 ADC Mux" },
1861
1862 { "AIF1TX", NULL, "IF1 ADC" },
1863 { "AIF1TX", NULL, "IF2 ADC" },
1864 { "AIF2TX", NULL, "IF2 ADC" },
1865
1866 { "IF1 DAC1", NULL, "AIF1RX" },
1867 { "IF1 DAC2", NULL, "AIF1RX" },
1868 { "IF2 DAC", NULL, "AIF2RX" },
1869
1870 { "IF1 DAC1", NULL, "I2S1" },
1871 { "IF1 DAC2", NULL, "I2S1" },
1872 { "IF2 DAC", NULL, "I2S2" },
1873
1874 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
1875 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
1876 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
1877 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
1878 { "IF2 DAC L", NULL, "IF2 DAC" },
1879 { "IF2 DAC R", NULL, "IF2 DAC" },
1880
1881 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1882 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1883
1884 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1885 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1886
1887 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1888 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1889 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
1890 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1891 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1892 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
1893
1894 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1895 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1896 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
1897 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1898 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
1899 { "DAC L2 Volume", NULL, "dac mono left filter" },
1900
1901 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1902 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1903 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
1904 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
1905 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
1906 { "DAC R2 Volume", NULL, "dac mono right filter" },
1907
1908 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1909 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1910 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1911 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
1912 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1913 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1914 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1915 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
1916
1917 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1918 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1919 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1920 { "Mono DAC MIXL", NULL, "dac mono left filter" },
1921 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1922 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1923 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1924 { "Mono DAC MIXR", NULL, "dac mono right filter" },
1925
1926 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1927 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1928 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1929 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1930 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1931 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1932
1319b2f6 1933 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 1934 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 1935 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6
OC		 1936 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1937
1938 { "SPK MIXL", "BST1 Switch", "BST1" },
1939 { "SPK MIXL", "INL Switch", "INL VOL" },
1940 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
1941 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
1942 { "SPK MIXR", "BST2 Switch", "BST2" },
1943 { "SPK MIXR", "INR Switch", "INR VOL" },
1944 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
1945 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
1946
1947 { "OUT MIXL", "BST1 Switch", "BST1" },
1948 { "OUT MIXL", "INL Switch", "INL VOL" },
1949 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1950 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1951
1952 { "OUT MIXR", "BST2 Switch", "BST2" },
1953 { "OUT MIXR", "INR Switch", "INR VOL" },
1954 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1955 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1956
1957 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1958 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
1959 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
1960 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
1961 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
1962 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1963 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
1964 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
1965 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
1966 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
1967
1968 { "DAC 2", NULL, "DAC L2" },
1969 { "DAC 2", NULL, "DAC R2" },
1970 { "DAC 1", NULL, "DAC L1" },
1971 { "DAC 1", NULL, "DAC R1" },
1972 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
1973 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
1974 { "HPOVOL", NULL, "HPOVOL L" },
1975 { "HPOVOL", NULL, "HPOVOL R" },
1976 { "HPO MIX", "DAC1 Switch", "DAC 1" },
1977 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
1978
1979 { "SPKVOL L", "Switch", "SPK MIXL" },
1980 { "SPKVOL R", "Switch", "SPK MIXR" },
1981
1982 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
1983 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
1984 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
1985 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
1986 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
1987 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
1988
1989 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1990 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1991 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
1992 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
1993
1994 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1995 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
1996 { "PDM1 L Mux", NULL, "PDM1 Power" },
1997 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
1998 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
1999 { "PDM1 R Mux", NULL, "PDM1 Power" },
2000
2001 { "HP amp", NULL, "HPO MIX" },
2002 { "HP amp", NULL, "JD Power" },
2003 { "HP amp", NULL, "Mic Det Power" },
2004 { "HP amp", NULL, "LDO2" },
2005 { "HPOL", NULL, "HP amp" },
2006 { "HPOR", NULL, "HP amp" },
2007
2008 { "LOUT amp", NULL, "LOUT MIX" },
2009 { "LOUTL", NULL, "LOUT amp" },
2010 { "LOUTR", NULL, "LOUT amp" },
2011
2012 { "PDM1 L", "Switch", "PDM1 L Mux" },
2013 { "PDM1 R", "Switch", "PDM1 R Mux" },
2014
2015 { "PDM1L", NULL, "PDM1 L" },
2016 { "PDM1R", NULL, "PDM1 R" },
2017
2018 { "SPK amp", NULL, "SPOL MIX" },
2019 { "SPK amp", NULL, "SPOR MIX" },
2020 { "SPOL", NULL, "SPK amp" },
2021 { "SPOR", NULL, "SPK amp" },
2022};
2023
5c4ca99d
BL		 2024static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2025 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2026 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2027 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2028 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2029
2030 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2031 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2032 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2033 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2034
2035 { "DAC L1", NULL, "A DAC1 L Mux" },
2036 { "DAC R1", NULL, "A DAC1 R Mux" },
2037 { "DAC L2", NULL, "A DAC2 L Mux" },
2038 { "DAC R2", NULL, "A DAC2 R Mux" },
2039};
2040
2041static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2042 { "DAC L1", NULL, "Stereo DAC MIXL" },
2043 { "DAC R1", NULL, "Stereo DAC MIXR" },
2044 { "DAC L2", NULL, "Mono DAC MIXL" },
2045 { "DAC R2", NULL, "Mono DAC MIXR" },
2046};
2047
1319b2f6
OC		 2048static int rt5645_hw_params(struct snd_pcm_substream *substream,
2049 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2050{
2051 struct snd_soc_codec *codec = dai->codec;
2052 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2053 unsigned int val_len = 0, val_clk, mask_clk;
2054 int pre_div, bclk_ms, frame_size;
2055
2056 rt5645->lrck[dai->id] = params_rate(params);
d92950e7 2057 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1319b2f6
OC		 2058 if (pre_div < 0) {
2059 dev_err(codec->dev, "Unsupported clock setting\n");
2060 return -EINVAL;
2061 }
2062 frame_size = snd_soc_params_to_frame_size(params);
2063 if (frame_size < 0) {
2064 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2065 return -EINVAL;
2066 }
2067 bclk_ms = frame_size > 32;
2068 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2069
2070 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2071 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2072 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2073 bclk_ms, pre_div, dai->id);
2074
2075 switch (params_width(params)) {
2076 case 16:
2077 break;
2078 case 20:
2079 val_len |= RT5645_I2S_DL_20;
2080 break;
2081 case 24:
2082 val_len |= RT5645_I2S_DL_24;
2083 break;
2084 case 8:
2085 val_len |= RT5645_I2S_DL_8;
2086 break;
2087 default:
2088 return -EINVAL;
2089 }
2090
2091 switch (dai->id) {
2092 case RT5645_AIF1:
2093 mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK;
2094 val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT |
2095 pre_div << RT5645_I2S_PD1_SFT;
2096 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2097 RT5645_I2S_DL_MASK, val_len);
2098 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2099 break;
2100 case RT5645_AIF2:
2101 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2102 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2103 pre_div << RT5645_I2S_PD2_SFT;
2104 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
2105 RT5645_I2S_DL_MASK, val_len);
2106 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2107 break;
2108 default:
2109 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2110 return -EINVAL;
2111 }
2112
2113 return 0;
2114}
2115
2116static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2117{
2118 struct snd_soc_codec *codec = dai->codec;
2119 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2120 unsigned int reg_val = 0;
2121
2122 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2123 case SND_SOC_DAIFMT_CBM_CFM:
2124 rt5645->master[dai->id] = 1;
2125 break;
2126 case SND_SOC_DAIFMT_CBS_CFS:
2127 reg_val |= RT5645_I2S_MS_S;
2128 rt5645->master[dai->id] = 0;
2129 break;
2130 default:
2131 return -EINVAL;
2132 }
2133
2134 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2135 case SND_SOC_DAIFMT_NB_NF:
2136 break;
2137 case SND_SOC_DAIFMT_IB_NF:
2138 reg_val |= RT5645_I2S_BP_INV;
2139 break;
2140 default:
2141 return -EINVAL;
2142 }
2143
2144 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2145 case SND_SOC_DAIFMT_I2S:
2146 break;
2147 case SND_SOC_DAIFMT_LEFT_J:
2148 reg_val |= RT5645_I2S_DF_LEFT;
2149 break;
2150 case SND_SOC_DAIFMT_DSP_A:
2151 reg_val |= RT5645_I2S_DF_PCM_A;
2152 break;
2153 case SND_SOC_DAIFMT_DSP_B:
2154 reg_val |= RT5645_I2S_DF_PCM_B;
2155 break;
2156 default:
2157 return -EINVAL;
2158 }
2159 switch (dai->id) {
2160 case RT5645_AIF1:
2161 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2162 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
2163 RT5645_I2S_DF_MASK, reg_val);
2164 break;
8c325704
AL		 2165 case RT5645_AIF2:
2166 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
1319b2f6
OC		 2167 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
2168 RT5645_I2S_DF_MASK, reg_val);
2169 break;
2170 default:
2171 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2172 return -EINVAL;
2173 }
2174 return 0;
2175}
2176
2177static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2178 int clk_id, unsigned int freq, int dir)
2179{
2180 struct snd_soc_codec *codec = dai->codec;
2181 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2182 unsigned int reg_val = 0;
2183
2184 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2185 return 0;
2186
2187 switch (clk_id) {
2188 case RT5645_SCLK_S_MCLK:
2189 reg_val |= RT5645_SCLK_SRC_MCLK;
2190 break;
2191 case RT5645_SCLK_S_PLL1:
2192 reg_val |= RT5645_SCLK_SRC_PLL1;
2193 break;
2194 case RT5645_SCLK_S_RCCLK:
2195 reg_val |= RT5645_SCLK_SRC_RCCLK;
2196 break;
2197 default:
2198 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2199 return -EINVAL;
2200 }
2201 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2202 RT5645_SCLK_SRC_MASK, reg_val);
2203 rt5645->sysclk = freq;
2204 rt5645->sysclk_src = clk_id;
2205
2206 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2207
2208 return 0;
2209}
2210
1319b2f6
OC		 2211static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2212 unsigned int freq_in, unsigned int freq_out)
2213{
2214 struct snd_soc_codec *codec = dai->codec;
2215 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
71c7a2d6 2216 struct rl6231_pll_code pll_code;
1319b2f6
OC		 2217 int ret;
2218
2219 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2220 freq_out == rt5645->pll_out)
2221 return 0;
2222
2223 if (!freq_in || !freq_out) {
2224 dev_dbg(codec->dev, "PLL disabled\n");
2225
2226 rt5645->pll_in = 0;
2227 rt5645->pll_out = 0;
2228 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2229 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2230 return 0;
2231 }
2232
2233 switch (source) {
2234 case RT5645_PLL1_S_MCLK:
2235 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2236 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2237 break;
2238 case RT5645_PLL1_S_BCLK1:
2239 case RT5645_PLL1_S_BCLK2:
2240 switch (dai->id) {
2241 case RT5645_AIF1:
2242 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2243 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2244 break;
2245 case RT5645_AIF2:
2246 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2247 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2248 break;
2249 default:
2250 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2251 return -EINVAL;
2252 }
2253 break;
2254 default:
2255 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2256 return -EINVAL;
2257 }
2258
71c7a2d6 2259 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1319b2f6
OC		 2260 if (ret < 0) {
2261 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2262 return ret;
2263 }
2264
2265 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2266 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2267 pll_code.n_code, pll_code.k_code);
2268
2269 snd_soc_write(codec, RT5645_PLL_CTRL1,
2270 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2271 snd_soc_write(codec, RT5645_PLL_CTRL2,
2272 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2273 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2274
2275 rt5645->pll_in = freq_in;
2276 rt5645->pll_out = freq_out;
2277 rt5645->pll_src = source;
2278
2279 return 0;
2280}
2281
2282static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2283 unsigned int rx_mask, int slots, int slot_width)
2284{
2285 struct snd_soc_codec *codec = dai->codec;
2286 unsigned int val = 0;
2287
850577db 2288 if (rx_mask || tx_mask) {
1319b2f6 2289 val |= (1 << 14);
850577db
BL		 2290 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2291 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
2292 }
1319b2f6
OC		 2293
2294 switch (slots) {
2295 case 4:
2296 val |= (1 << 12);
2297 break;
2298 case 6:
2299 val |= (2 << 12);
2300 break;
2301 case 8:
2302 val |= (3 << 12);
2303 break;
2304 case 2:
2305 default:
2306 break;
2307 }
2308
2309 switch (slot_width) {
2310 case 20:
2311 val |= (1 << 10);
2312 break;
2313 case 24:
2314 val |= (2 << 10);
2315 break;
2316 case 32:
2317 val |= (3 << 10);
2318 break;
2319 case 16:
2320 default:
2321 break;
2322 }
2323
2324 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, 0x7c00, val);
2325
2326 return 0;
2327}
2328
2329static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2330 enum snd_soc_bias_level level)
2331{
2332 switch (level) {
0b2e4959
BL		 2333 case SND_SOC_BIAS_PREPARE:
2334 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
1319b2f6
OC		 2335 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2336 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2337 RT5645_PWR_BG | RT5645_PWR_VREF2,
2338 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2339 RT5645_PWR_BG | RT5645_PWR_VREF2);
2340 mdelay(10);
2341 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2342 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2343 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2344 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2345 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2346 }
2347 break;
2348
0b2e4959
BL		 2349 case SND_SOC_BIAS_STANDBY:
2350 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2351 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2352 RT5645_PWR_BG | RT5645_PWR_VREF2,
2353 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2354 RT5645_PWR_BG | RT5645_PWR_VREF2);
2355 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2356 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2357 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2358 break;
2359
1319b2f6
OC		 2360 case SND_SOC_BIAS_OFF:
2361 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
2362 snd_soc_write(codec, RT5645_GEN_CTRL1, 0x0128);
0b2e4959
BL		 2363 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2364 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2365 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2366 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
1319b2f6
OC		 2367 break;
2368
2369 default:
2370 break;
2371 }
2372 codec->dapm.bias_level = level;
2373
2374 return 0;
2375}
2376
471f208a 2377static int rt5645_jack_detect(struct snd_soc_codec *codec)
f3fa1bbd
OC		 2378{
2379 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2380 int gpio_state, jack_type = 0;
2381 unsigned int val;
2382
75945896
BL		 2383 if (!gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2384 dev_err(codec->dev, "invalid gpio\n");
2385 return -EINVAL;
2386 }
f3fa1bbd
OC		 2387 gpio_state = gpio_get_value(rt5645->pdata.hp_det_gpio);
2388
2389 dev_dbg(codec->dev, "gpio = %d(%d)\n", rt5645->pdata.hp_det_gpio,
2390 gpio_state);
2391
2392 if ((rt5645->pdata.gpio_hp_det_active_high && gpio_state) ||
2393 (!rt5645->pdata.gpio_hp_det_active_high && !gpio_state)) {
2394 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias1");
2395 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias2");
2396 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2397 snd_soc_dapm_force_enable_pin(&codec->dapm, "Mic Det Power");
2398 snd_soc_dapm_sync(&codec->dapm);
2399
2400 snd_soc_write(codec, RT5645_IN1_CTRL1, 0x0006);
2401 snd_soc_write(codec, RT5645_JD_CTRL3, 0x00b0);
2402
2403 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2404 RT5645_CBJ_MN_JD, 0);
2405 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2406 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
2407
2408 msleep(400);
2409 val = snd_soc_read(codec, RT5645_IN1_CTRL3) & 0x7;
2410 dev_dbg(codec->dev, "val = %d\n", val);
2411
2412 if (val == 1 || val == 2)
2413 jack_type = SND_JACK_HEADSET;
2414 else
2415 jack_type = SND_JACK_HEADPHONE;
2416
2417 snd_soc_dapm_disable_pin(&codec->dapm, "micbias1");
2418 snd_soc_dapm_disable_pin(&codec->dapm, "micbias2");
2d4e2d02
BL		 2419 if (rt5645->pdata.jd_mode == 0)
2420 snd_soc_dapm_disable_pin(&codec->dapm, "LDO2");
f3fa1bbd
OC		 2421 snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power");
2422 snd_soc_dapm_sync(&codec->dapm);
2423 }
2424
471f208a
BL		 2425 snd_soc_jack_report(rt5645->hp_jack, jack_type, SND_JACK_HEADPHONE);
2426 snd_soc_jack_report(rt5645->mic_jack, jack_type, SND_JACK_MICROPHONE);
f3fa1bbd
OC		 2427 return 0;
2428}
2429
2430int rt5645_set_jack_detect(struct snd_soc_codec *codec,
471f208a 2431 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
f3fa1bbd
OC		 2432{
2433 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2434
471f208a
BL		 2435 rt5645->hp_jack = hp_jack;
2436 rt5645->mic_jack = mic_jack;
2437 rt5645_jack_detect(codec);
f3fa1bbd
OC		 2438
2439 return 0;
2440}
2441EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2442
cd6e82b8
OC		 2443static void rt5645_jack_detect_work(struct work_struct *work)
2444{
2445 struct rt5645_priv *rt5645 =
2446 container_of(work, struct rt5645_priv, jack_detect_work.work);
2447
471f208a 2448 rt5645_jack_detect(rt5645->codec);
cd6e82b8
OC		 2449}
2450
f3fa1bbd
OC		 2451static irqreturn_t rt5645_irq(int irq, void *data)
2452{
2453 struct rt5645_priv *rt5645 = data;
2454
cd6e82b8
OC		 2455 queue_delayed_work(system_power_efficient_wq,
2456 &rt5645->jack_detect_work, msecs_to_jiffies(250));
f3fa1bbd
OC		 2457
2458 return IRQ_HANDLED;
2459}
2460
1319b2f6
OC		 2461static int rt5645_probe(struct snd_soc_codec *codec)
2462{
2463 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2464
2465 rt5645->codec = codec;
2466
5c4ca99d
BL		 2467 switch (rt5645->codec_type) {
2468 case CODEC_TYPE_RT5645:
2469 snd_soc_dapm_add_routes(&codec->dapm,
2470 rt5645_specific_dapm_routes,
2471 ARRAY_SIZE(rt5645_specific_dapm_routes));
2472 break;
2473 case CODEC_TYPE_RT5650:
2474 snd_soc_dapm_new_controls(&codec->dapm,
2475 rt5650_specific_dapm_widgets,
2476 ARRAY_SIZE(rt5650_specific_dapm_widgets));
2477 snd_soc_dapm_add_routes(&codec->dapm,
2478 rt5650_specific_dapm_routes,
2479 ARRAY_SIZE(rt5650_specific_dapm_routes));
2480 break;
2481 }
2482
1319b2f6
OC		 2483 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2484
2485 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
1319b2f6 2486
bb656add
BL		 2487 /* for JD function */
2488 if (rt5645->pdata.en_jd_func) {
2489 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
2490 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2491 snd_soc_dapm_sync(&codec->dapm);
2492 }
2493
1319b2f6
OC		 2494 return 0;
2495}
2496
2497static int rt5645_remove(struct snd_soc_codec *codec)
2498{
2499 rt5645_reset(codec);
2500 return 0;
2501}
2502
2503#ifdef CONFIG_PM
2504static int rt5645_suspend(struct snd_soc_codec *codec)
2505{
2506 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2507
2508 regcache_cache_only(rt5645->regmap, true);
2509 regcache_mark_dirty(rt5645->regmap);
2510
2511 return 0;
2512}
2513
2514static int rt5645_resume(struct snd_soc_codec *codec)
2515{
2516 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2517
2518 regcache_cache_only(rt5645->regmap, false);
0f776efd 2519 regcache_sync(rt5645->regmap);
1319b2f6
OC		 2520
2521 return 0;
2522}
2523#else
2524#define rt5645_suspend NULL
2525#define rt5645_resume NULL
2526#endif
2527
2528#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2529#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2530 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2531
9e22f782 2532static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
1319b2f6
OC		 2533 .hw_params = rt5645_hw_params,
2534 .set_fmt = rt5645_set_dai_fmt,
2535 .set_sysclk = rt5645_set_dai_sysclk,
2536 .set_tdm_slot = rt5645_set_tdm_slot,
2537 .set_pll = rt5645_set_dai_pll,
2538};
2539
9e22f782 2540static struct snd_soc_dai_driver rt5645_dai[] = {
1319b2f6
OC		 2541 {
2542 .name = "rt5645-aif1",
2543 .id = RT5645_AIF1,
2544 .playback = {
2545 .stream_name = "AIF1 Playback",
2546 .channels_min = 1,
2547 .channels_max = 2,
2548 .rates = RT5645_STEREO_RATES,
2549 .formats = RT5645_FORMATS,
2550 },
2551 .capture = {
2552 .stream_name = "AIF1 Capture",
2553 .channels_min = 1,
2554 .channels_max = 2,
2555 .rates = RT5645_STEREO_RATES,
2556 .formats = RT5645_FORMATS,
2557 },
2558 .ops = &rt5645_aif_dai_ops,
2559 },
2560 {
2561 .name = "rt5645-aif2",
2562 .id = RT5645_AIF2,
2563 .playback = {
2564 .stream_name = "AIF2 Playback",
2565 .channels_min = 1,
2566 .channels_max = 2,
2567 .rates = RT5645_STEREO_RATES,
2568 .formats = RT5645_FORMATS,
2569 },
2570 .capture = {
2571 .stream_name = "AIF2 Capture",
2572 .channels_min = 1,
2573 .channels_max = 2,
2574 .rates = RT5645_STEREO_RATES,
2575 .formats = RT5645_FORMATS,
2576 },
2577 .ops = &rt5645_aif_dai_ops,
2578 },
2579};
2580
2581static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
2582 .probe = rt5645_probe,
2583 .remove = rt5645_remove,
2584 .suspend = rt5645_suspend,
2585 .resume = rt5645_resume,
2586 .set_bias_level = rt5645_set_bias_level,
2587 .idle_bias_off = true,
2588 .controls = rt5645_snd_controls,
2589 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
2590 .dapm_widgets = rt5645_dapm_widgets,
2591 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
2592 .dapm_routes = rt5645_dapm_routes,
2593 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
2594};
2595
2596static const struct regmap_config rt5645_regmap = {
2597 .reg_bits = 8,
2598 .val_bits = 16,
2599
2600 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
2601 RT5645_PR_SPACING),
2602 .volatile_reg = rt5645_volatile_register,
2603 .readable_reg = rt5645_readable_register,
2604
2605 .cache_type = REGCACHE_RBTREE,
2606 .reg_defaults = rt5645_reg,
2607 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
2608 .ranges = rt5645_ranges,
2609 .num_ranges = ARRAY_SIZE(rt5645_ranges),
2610};
2611
2612static const struct i2c_device_id rt5645_i2c_id[] = {
2613 { "rt5645", 0 },
5c4ca99d 2614 { "rt5650", 0 },
1319b2f6
OC		 2615 { }
2616};
2617MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
2618
2619static int rt5645_i2c_probe(struct i2c_client *i2c,
2620 const struct i2c_device_id *id)
2621{
2622 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
2623 struct rt5645_priv *rt5645;
2624 int ret;
2625 unsigned int val;
2626
2627 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
2628 GFP_KERNEL);
2629 if (rt5645 == NULL)
2630 return -ENOMEM;
2631
f3fa1bbd 2632 rt5645->i2c = i2c;
1319b2f6
OC		 2633 i2c_set_clientdata(i2c, rt5645);
2634
2635 if (pdata)
2636 rt5645->pdata = *pdata;
2637
2638 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
2639 if (IS_ERR(rt5645->regmap)) {
2640 ret = PTR_ERR(rt5645->regmap);
2641 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2642 ret);
2643 return ret;
2644 }
2645
2646 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
5c4ca99d
BL		 2647
2648 switch (val) {
2649 case RT5645_DEVICE_ID:
2650 rt5645->codec_type = CODEC_TYPE_RT5645;
2651 break;
2652 case RT5650_DEVICE_ID:
2653 rt5645->codec_type = CODEC_TYPE_RT5650;
2654 break;
2655 default:
1319b2f6 2656 dev_err(&i2c->dev,
5c4ca99d
BL		 2657 "Device with ID register %x is not rt5645 or rt5650\n",
2658 val);
1319b2f6
OC		 2659 return -ENODEV;
2660 }
2661
2662 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2663
2664 ret = regmap_register_patch(rt5645->regmap, init_list,
2665 ARRAY_SIZE(init_list));
2666 if (ret != 0)
2667 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2668
5c4ca99d
BL		 2669 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
2670 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
2671 ARRAY_SIZE(rt5650_init_list));
2672 if (ret != 0)
2673 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
2674 ret);
2675 }
2676
1319b2f6
OC		 2677 if (rt5645->pdata.in2_diff)
2678 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
2679 RT5645_IN_DF2, RT5645_IN_DF2);
2680
2681 if (rt5645->pdata.dmic_en) {
2682 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2683 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
2684
2685 switch (rt5645->pdata.dmic1_data_pin) {
2686 case RT5645_DMIC_DATA_IN2N:
2687 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2688 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
2689 break;
2690
2691 case RT5645_DMIC_DATA_GPIO5:
2692 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2693 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2694 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2695 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2696 break;
2697
2698 case RT5645_DMIC_DATA_GPIO11:
2699 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2700 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
2701 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2702 RT5645_GP11_PIN_MASK,
2703 RT5645_GP11_PIN_DMIC1_SDA);
2704 break;
2705
2706 default:
2707 break;
2708 }
2709
2710 switch (rt5645->pdata.dmic2_data_pin) {
2711 case RT5645_DMIC_DATA_IN2P:
2712 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2713 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2714 break;
2715
2716 case RT5645_DMIC_DATA_GPIO6:
2717 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2718 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
2719 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2720 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
2721 break;
2722
2723 case RT5645_DMIC_DATA_GPIO10:
2724 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2725 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
2726 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2727 RT5645_GP10_PIN_MASK,
2728 RT5645_GP10_PIN_DMIC2_SDA);
2729 break;
2730
2731 case RT5645_DMIC_DATA_GPIO12:
2732 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2733 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
2734 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2735 RT5645_GP12_PIN_MASK,
2736 RT5645_GP12_PIN_DMIC2_SDA);
2737 break;
2738
2739 default:
2740 break;
2741 }
2742
2743 }
2744
bb656add
BL		 2745 if (rt5645->pdata.en_jd_func) {
2746 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2747 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU,
2748 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU);
2749 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
2750 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
2751 regmap_update_bits(rt5645->regmap, RT5645_JD_CTRL3,
2752 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL,
2753 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL);
2754 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2755 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2756 }
2757
2d4e2d02
BL		 2758 if (rt5645->pdata.jd_mode) {
2759 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
2760 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
2761 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2762 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
2763 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
2764 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
2765 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2766 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
2767 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2768 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2769 switch (rt5645->pdata.jd_mode) {
2770 case 1:
2771 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2772 RT5645_JD1_MODE_MASK,
2773 RT5645_JD1_MODE_0);
2774 break;
2775 case 2:
2776 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2777 RT5645_JD1_MODE_MASK,
2778 RT5645_JD1_MODE_1);
2779 break;
2780 case 3:
2781 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2782 RT5645_JD1_MODE_MASK,
2783 RT5645_JD1_MODE_2);
2784 break;
2785 default:
2786 break;
2787 }
2788 }
2789
f3fa1bbd
OC		 2790 if (rt5645->i2c->irq) {
2791 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
2792 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2793 | IRQF_ONESHOT, "rt5645", rt5645);
2794 if (ret)
2795 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2796 }
2797
2798 if (gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2799 ret = gpio_request(rt5645->pdata.hp_det_gpio, "rt5645");
2800 if (ret)
2801 dev_err(&i2c->dev, "Fail gpio_request hp_det_gpio\n");
2802
2803 ret = gpio_direction_input(rt5645->pdata.hp_det_gpio);
2804 if (ret)
2805 dev_err(&i2c->dev, "Fail gpio_direction hp_det_gpio\n");
2806 }
2807
cd6e82b8
OC		 2808 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
2809
dd56ebad
AL		 2810 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
2811 rt5645_dai, ARRAY_SIZE(rt5645_dai));
1319b2f6
OC		 2812}
2813
2814static int rt5645_i2c_remove(struct i2c_client *i2c)
2815{
f3fa1bbd
OC		 2816 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
2817
2818 if (i2c->irq)
2819 free_irq(i2c->irq, rt5645);
2820
cd6e82b8
OC		 2821 cancel_delayed_work_sync(&rt5645->jack_detect_work);
2822
f3fa1bbd
OC		 2823 if (gpio_is_valid(rt5645->pdata.hp_det_gpio))
2824 gpio_free(rt5645->pdata.hp_det_gpio);
2825
1319b2f6
OC		 2826 snd_soc_unregister_codec(&i2c->dev);
2827
2828 return 0;
2829}
2830
9e22f782 2831static struct i2c_driver rt5645_i2c_driver = {
1319b2f6
OC		 2832 .driver = {
2833 .name = "rt5645",
2834 .owner = THIS_MODULE,
2835 },
2836 .probe = rt5645_i2c_probe,
2837 .remove = rt5645_i2c_remove,
2838 .id_table = rt5645_i2c_id,
2839};
2840module_i2c_driver(rt5645_i2c_driver);
2841
2842MODULE_DESCRIPTION("ASoC RT5645 driver");
2843MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2844MODULE_LICENSE("GPL v2");
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