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ASoC: Add helper functions bias level management
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / rt5645.c
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1319b2f6
OC		 1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
f3fa1bbd 20#include <linux/gpio.h>
1319b2f6
OC		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
49ef7925 30#include "rl6231.h"
1319b2f6
OC		 31#include "rt5645.h"
32
33#define RT5645_DEVICE_ID 0x6308
5c4ca99d 34#define RT5650_DEVICE_ID 0x6419
1319b2f6
OC		 35
36#define RT5645_PR_RANGE_BASE (0xff + 1)
37#define RT5645_PR_SPACING 0x100
38
39#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
40
41static const struct regmap_range_cfg rt5645_ranges[] = {
42 {
43 .name = "PR",
44 .range_min = RT5645_PR_BASE,
45 .range_max = RT5645_PR_BASE + 0xf8,
46 .selector_reg = RT5645_PRIV_INDEX,
47 .selector_mask = 0xff,
48 .selector_shift = 0x0,
49 .window_start = RT5645_PRIV_DATA,
50 .window_len = 0x1,
51 },
52};
53
54static const struct reg_default init_list[] = {
55 {RT5645_PR_BASE + 0x3d, 0x3600},
4809b96e
OC		 56 {RT5645_PR_BASE + 0x1c, 0xfd20},
57 {RT5645_PR_BASE + 0x20, 0x611f},
58 {RT5645_PR_BASE + 0x21, 0x4040},
59 {RT5645_PR_BASE + 0x23, 0x0004},
1319b2f6
OC		 60};
61#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
62
5c4ca99d
BL		 63static const struct reg_default rt5650_init_list[] = {
64 {0xf6, 0x0100},
65};
66
1319b2f6
OC		 67static const struct reg_default rt5645_reg[] = {
68 { 0x00, 0x0000 },
69 { 0x01, 0xc8c8 },
70 { 0x02, 0xc8c8 },
71 { 0x03, 0xc8c8 },
72 { 0x0a, 0x0002 },
73 { 0x0b, 0x2827 },
74 { 0x0c, 0xe000 },
75 { 0x0d, 0x0000 },
76 { 0x0e, 0x0000 },
77 { 0x0f, 0x0808 },
78 { 0x14, 0x3333 },
79 { 0x16, 0x4b00 },
80 { 0x18, 0x018b },
81 { 0x19, 0xafaf },
82 { 0x1a, 0xafaf },
83 { 0x1b, 0x0001 },
84 { 0x1c, 0x2f2f },
85 { 0x1d, 0x2f2f },
86 { 0x1e, 0x0000 },
87 { 0x20, 0x0000 },
88 { 0x27, 0x7060 },
89 { 0x28, 0x7070 },
90 { 0x29, 0x8080 },
91 { 0x2a, 0x5656 },
92 { 0x2b, 0x5454 },
93 { 0x2c, 0xaaa0 },
5c4ca99d 94 { 0x2d, 0x0000 },
1319b2f6
OC		 95 { 0x2f, 0x1002 },
96 { 0x31, 0x5000 },
97 { 0x32, 0x0000 },
98 { 0x33, 0x0000 },
99 { 0x34, 0x0000 },
100 { 0x35, 0x0000 },
101 { 0x3b, 0x0000 },
102 { 0x3c, 0x007f },
103 { 0x3d, 0x0000 },
104 { 0x3e, 0x007f },
105 { 0x3f, 0x0000 },
106 { 0x40, 0x001f },
107 { 0x41, 0x0000 },
108 { 0x42, 0x001f },
109 { 0x45, 0x6000 },
110 { 0x46, 0x003e },
111 { 0x47, 0x003e },
112 { 0x48, 0xf807 },
113 { 0x4a, 0x0004 },
114 { 0x4d, 0x0000 },
115 { 0x4e, 0x0000 },
116 { 0x4f, 0x01ff },
117 { 0x50, 0x0000 },
118 { 0x51, 0x0000 },
119 { 0x52, 0x01ff },
120 { 0x53, 0xf000 },
121 { 0x56, 0x0111 },
122 { 0x57, 0x0064 },
123 { 0x58, 0xef0e },
124 { 0x59, 0xf0f0 },
125 { 0x5a, 0xef0e },
126 { 0x5b, 0xf0f0 },
127 { 0x5c, 0xef0e },
128 { 0x5d, 0xf0f0 },
129 { 0x5e, 0xf000 },
130 { 0x5f, 0x0000 },
131 { 0x61, 0x0300 },
132 { 0x62, 0x0000 },
133 { 0x63, 0x00c2 },
134 { 0x64, 0x0000 },
135 { 0x65, 0x0000 },
136 { 0x66, 0x0000 },
137 { 0x6a, 0x0000 },
138 { 0x6c, 0x0aaa },
139 { 0x70, 0x8000 },
140 { 0x71, 0x8000 },
141 { 0x72, 0x8000 },
142 { 0x73, 0x7770 },
143 { 0x74, 0x3e00 },
144 { 0x75, 0x2409 },
145 { 0x76, 0x000a },
146 { 0x77, 0x0c00 },
147 { 0x78, 0x0000 },
df078d29 148 { 0x79, 0x0123 },
1319b2f6
OC		 149 { 0x80, 0x0000 },
150 { 0x81, 0x0000 },
151 { 0x82, 0x0000 },
152 { 0x83, 0x0000 },
153 { 0x84, 0x0000 },
154 { 0x85, 0x0000 },
155 { 0x8a, 0x0000 },
156 { 0x8e, 0x0004 },
157 { 0x8f, 0x1100 },
158 { 0x90, 0x0646 },
159 { 0x91, 0x0c06 },
160 { 0x93, 0x0000 },
161 { 0x94, 0x0200 },
162 { 0x95, 0x0000 },
163 { 0x9a, 0x2184 },
164 { 0x9b, 0x010a },
165 { 0x9c, 0x0aea },
166 { 0x9d, 0x000c },
167 { 0x9e, 0x0400 },
168 { 0xa0, 0xa0a8 },
169 { 0xa1, 0x0059 },
170 { 0xa2, 0x0001 },
171 { 0xae, 0x6000 },
172 { 0xaf, 0x0000 },
173 { 0xb0, 0x6000 },
174 { 0xb1, 0x0000 },
175 { 0xb2, 0x0000 },
176 { 0xb3, 0x001f },
177 { 0xb4, 0x020c },
178 { 0xb5, 0x1f00 },
179 { 0xb6, 0x0000 },
180 { 0xbb, 0x0000 },
181 { 0xbc, 0x0000 },
182 { 0xbd, 0x0000 },
183 { 0xbe, 0x0000 },
184 { 0xbf, 0x3100 },
185 { 0xc0, 0x0000 },
186 { 0xc1, 0x0000 },
187 { 0xc2, 0x0000 },
188 { 0xc3, 0x2000 },
189 { 0xcd, 0x0000 },
190 { 0xce, 0x0000 },
191 { 0xcf, 0x1813 },
192 { 0xd0, 0x0690 },
193 { 0xd1, 0x1c17 },
194 { 0xd3, 0xb320 },
195 { 0xd4, 0x0000 },
196 { 0xd6, 0x0400 },
197 { 0xd9, 0x0809 },
198 { 0xda, 0x0000 },
199 { 0xdb, 0x0003 },
200 { 0xdc, 0x0049 },
201 { 0xdd, 0x001b },
5c4ca99d
BL		 202 { 0xdf, 0x0008 },
203 { 0xe0, 0x4000 },
1319b2f6
OC		 204 { 0xe6, 0x8000 },
205 { 0xe7, 0x0200 },
206 { 0xec, 0xb300 },
207 { 0xed, 0x0000 },
208 { 0xf0, 0x001f },
209 { 0xf1, 0x020c },
210 { 0xf2, 0x1f00 },
211 { 0xf3, 0x0000 },
212 { 0xf4, 0x4000 },
213 { 0xf8, 0x0000 },
214 { 0xf9, 0x0000 },
215 { 0xfa, 0x2060 },
216 { 0xfb, 0x4040 },
217 { 0xfc, 0x0000 },
218 { 0xfd, 0x0002 },
219 { 0xfe, 0x10ec },
220 { 0xff, 0x6308 },
221};
222
223static int rt5645_reset(struct snd_soc_codec *codec)
224{
225 return snd_soc_write(codec, RT5645_RESET, 0);
226}
227
228static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
229{
230 int i;
231
232 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
233 if (reg >= rt5645_ranges[i].range_min &&
234 reg <= rt5645_ranges[i].range_max) {
235 return true;
236 }
237 }
238
239 switch (reg) {
240 case RT5645_RESET:
241 case RT5645_PRIV_DATA:
242 case RT5645_IN1_CTRL1:
243 case RT5645_IN1_CTRL2:
244 case RT5645_IN1_CTRL3:
245 case RT5645_A_JD_CTRL1:
246 case RT5645_ADC_EQ_CTRL1:
247 case RT5645_EQ_CTRL1:
248 case RT5645_ALC_CTRL_1:
249 case RT5645_IRQ_CTRL2:
250 case RT5645_IRQ_CTRL3:
251 case RT5645_INT_IRQ_ST:
252 case RT5645_IL_CMD:
5c4ca99d 253 case RT5650_4BTN_IL_CMD1:
1319b2f6
OC		 254 case RT5645_VENDOR_ID:
255 case RT5645_VENDOR_ID1:
256 case RT5645_VENDOR_ID2:
71bfa9b4 257 return true;
1319b2f6 258 default:
71bfa9b4 259 return false;
1319b2f6
OC		 260 }
261}
262
263static bool rt5645_readable_register(struct device *dev, unsigned int reg)
264{
265 int i;
266
267 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
268 if (reg >= rt5645_ranges[i].range_min &&
269 reg <= rt5645_ranges[i].range_max) {
270 return true;
271 }
272 }
273
274 switch (reg) {
275 case RT5645_RESET:
276 case RT5645_SPK_VOL:
277 case RT5645_HP_VOL:
278 case RT5645_LOUT1:
279 case RT5645_IN1_CTRL1:
280 case RT5645_IN1_CTRL2:
281 case RT5645_IN1_CTRL3:
282 case RT5645_IN2_CTRL:
283 case RT5645_INL1_INR1_VOL:
284 case RT5645_SPK_FUNC_LIM:
285 case RT5645_ADJ_HPF_CTRL:
286 case RT5645_DAC1_DIG_VOL:
287 case RT5645_DAC2_DIG_VOL:
288 case RT5645_DAC_CTRL:
289 case RT5645_STO1_ADC_DIG_VOL:
290 case RT5645_MONO_ADC_DIG_VOL:
291 case RT5645_ADC_BST_VOL1:
292 case RT5645_ADC_BST_VOL2:
293 case RT5645_STO1_ADC_MIXER:
294 case RT5645_MONO_ADC_MIXER:
295 case RT5645_AD_DA_MIXER:
296 case RT5645_STO_DAC_MIXER:
297 case RT5645_MONO_DAC_MIXER:
298 case RT5645_DIG_MIXER:
5c4ca99d 299 case RT5650_A_DAC_SOUR:
1319b2f6
OC		 300 case RT5645_DIG_INF1_DATA:
301 case RT5645_PDM_OUT_CTRL:
302 case RT5645_REC_L1_MIXER:
303 case RT5645_REC_L2_MIXER:
304 case RT5645_REC_R1_MIXER:
305 case RT5645_REC_R2_MIXER:
306 case RT5645_HPMIXL_CTRL:
307 case RT5645_HPOMIXL_CTRL:
308 case RT5645_HPMIXR_CTRL:
309 case RT5645_HPOMIXR_CTRL:
310 case RT5645_HPO_MIXER:
311 case RT5645_SPK_L_MIXER:
312 case RT5645_SPK_R_MIXER:
313 case RT5645_SPO_MIXER:
314 case RT5645_SPO_CLSD_RATIO:
315 case RT5645_OUT_L1_MIXER:
316 case RT5645_OUT_R1_MIXER:
317 case RT5645_OUT_L_GAIN1:
318 case RT5645_OUT_L_GAIN2:
319 case RT5645_OUT_R_GAIN1:
320 case RT5645_OUT_R_GAIN2:
321 case RT5645_LOUT_MIXER:
322 case RT5645_HAPTIC_CTRL1:
323 case RT5645_HAPTIC_CTRL2:
324 case RT5645_HAPTIC_CTRL3:
325 case RT5645_HAPTIC_CTRL4:
326 case RT5645_HAPTIC_CTRL5:
327 case RT5645_HAPTIC_CTRL6:
328 case RT5645_HAPTIC_CTRL7:
329 case RT5645_HAPTIC_CTRL8:
330 case RT5645_HAPTIC_CTRL9:
331 case RT5645_HAPTIC_CTRL10:
332 case RT5645_PWR_DIG1:
333 case RT5645_PWR_DIG2:
334 case RT5645_PWR_ANLG1:
335 case RT5645_PWR_ANLG2:
336 case RT5645_PWR_MIXER:
337 case RT5645_PWR_VOL:
338 case RT5645_PRIV_INDEX:
339 case RT5645_PRIV_DATA:
340 case RT5645_I2S1_SDP:
341 case RT5645_I2S2_SDP:
342 case RT5645_ADDA_CLK1:
343 case RT5645_ADDA_CLK2:
344 case RT5645_DMIC_CTRL1:
345 case RT5645_DMIC_CTRL2:
346 case RT5645_TDM_CTRL_1:
347 case RT5645_TDM_CTRL_2:
df078d29 348 case RT5645_TDM_CTRL_3:
1319b2f6
OC		 349 case RT5645_GLB_CLK:
350 case RT5645_PLL_CTRL1:
351 case RT5645_PLL_CTRL2:
352 case RT5645_ASRC_1:
353 case RT5645_ASRC_2:
354 case RT5645_ASRC_3:
355 case RT5645_ASRC_4:
356 case RT5645_DEPOP_M1:
357 case RT5645_DEPOP_M2:
358 case RT5645_DEPOP_M3:
359 case RT5645_MICBIAS:
360 case RT5645_A_JD_CTRL1:
361 case RT5645_VAD_CTRL4:
362 case RT5645_CLSD_OUT_CTRL:
363 case RT5645_ADC_EQ_CTRL1:
364 case RT5645_ADC_EQ_CTRL2:
365 case RT5645_EQ_CTRL1:
366 case RT5645_EQ_CTRL2:
367 case RT5645_ALC_CTRL_1:
368 case RT5645_ALC_CTRL_2:
369 case RT5645_ALC_CTRL_3:
370 case RT5645_ALC_CTRL_4:
371 case RT5645_ALC_CTRL_5:
372 case RT5645_JD_CTRL:
373 case RT5645_IRQ_CTRL1:
374 case RT5645_IRQ_CTRL2:
375 case RT5645_IRQ_CTRL3:
376 case RT5645_INT_IRQ_ST:
377 case RT5645_GPIO_CTRL1:
378 case RT5645_GPIO_CTRL2:
379 case RT5645_GPIO_CTRL3:
380 case RT5645_BASS_BACK:
381 case RT5645_MP3_PLUS1:
382 case RT5645_MP3_PLUS2:
383 case RT5645_ADJ_HPF1:
384 case RT5645_ADJ_HPF2:
385 case RT5645_HP_CALIB_AMP_DET:
386 case RT5645_SV_ZCD1:
387 case RT5645_SV_ZCD2:
388 case RT5645_IL_CMD:
389 case RT5645_IL_CMD2:
390 case RT5645_IL_CMD3:
5c4ca99d
BL		 391 case RT5650_4BTN_IL_CMD1:
392 case RT5650_4BTN_IL_CMD2:
1319b2f6
OC		 393 case RT5645_DRC1_HL_CTRL1:
394 case RT5645_DRC2_HL_CTRL1:
395 case RT5645_ADC_MONO_HP_CTRL1:
396 case RT5645_ADC_MONO_HP_CTRL2:
397 case RT5645_DRC2_CTRL1:
398 case RT5645_DRC2_CTRL2:
399 case RT5645_DRC2_CTRL3:
400 case RT5645_DRC2_CTRL4:
401 case RT5645_DRC2_CTRL5:
402 case RT5645_JD_CTRL3:
403 case RT5645_JD_CTRL4:
404 case RT5645_GEN_CTRL1:
405 case RT5645_GEN_CTRL2:
406 case RT5645_GEN_CTRL3:
407 case RT5645_VENDOR_ID:
408 case RT5645_VENDOR_ID1:
409 case RT5645_VENDOR_ID2:
71bfa9b4 410 return true;
1319b2f6 411 default:
71bfa9b4 412 return false;
1319b2f6
OC		 413 }
414}
415
416static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
417static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
418static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
419static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
420static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
421
422/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
423static unsigned int bst_tlv[] = {
424 TLV_DB_RANGE_HEAD(7),
425 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
426 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
427 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
428 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
429 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
430 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
431 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
432};
433
434static const char * const rt5645_tdm_data_swap_select[] = {
435 "L/R", "R/L", "L/L", "R/R"
436};
437
438static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
439 RT5645_TDM_CTRL_1, 6, rt5645_tdm_data_swap_select);
440
441static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
442 RT5645_TDM_CTRL_1, 4, rt5645_tdm_data_swap_select);
443
444static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
445 RT5645_TDM_CTRL_1, 2, rt5645_tdm_data_swap_select);
446
447static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot6_7_enum,
448 RT5645_TDM_CTRL_1, 0, rt5645_tdm_data_swap_select);
449
450static const char * const rt5645_tdm_adc_data_select[] = {
451 "1/2/R", "2/1/R", "R/1/2", "R/2/1"
452};
453
454static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum,
455 RT5645_TDM_CTRL_1, 8,
456 rt5645_tdm_adc_data_select);
457
458static const struct snd_kcontrol_new rt5645_snd_controls[] = {
459 /* Speaker Output Volume */
460 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
461 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
462 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
463 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
464
465 /* Headphone Output Volume */
466 SOC_DOUBLE("HP Channel Switch", RT5645_HP_VOL,
467 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
468 SOC_DOUBLE_TLV("HP Playback Volume", RT5645_HP_VOL,
469 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
470
471 /* OUTPUT Control */
472 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
473 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
474 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
475 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
476 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
477 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
478
479 /* DAC Digital Volume */
480 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
481 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
482 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
483 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
484 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
485 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
486
487 /* IN1/IN2 Control */
488 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
489 RT5645_BST_SFT1, 8, 0, bst_tlv),
490 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
491 RT5645_BST_SFT2, 8, 0, bst_tlv),
492
493 /* INL/INR Volume Control */
494 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
495 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
496
497 /* ADC Digital Volume Control */
498 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
499 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
500 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
501 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
502 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
503 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
504 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
505 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
506
507 /* ADC Boost Volume Control */
508 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
509 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
510 adc_bst_tlv),
511 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
512 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
513 adc_bst_tlv),
514
515 /* I2S2 function select */
516 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
517 1, 1),
518
519 /* TDM */
520 SOC_ENUM("TDM Adc Slot0 1 Data", rt5645_tdm_adc_slot0_1_enum),
521 SOC_ENUM("TDM Adc Slot2 3 Data", rt5645_tdm_adc_slot2_3_enum),
522 SOC_ENUM("TDM Adc Slot4 5 Data", rt5645_tdm_adc_slot4_5_enum),
523 SOC_ENUM("TDM Adc Slot6 7 Data", rt5645_tdm_adc_slot6_7_enum),
524 SOC_ENUM("TDM IF1 ADC DATA Sel", rt5645_tdm_adc_sel_enum),
525 SOC_SINGLE("TDM IF1_DAC1_L Sel", RT5645_TDM_CTRL_3, 12, 7, 0),
526 SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0),
527 SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0),
528 SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0),
529};
530
531/**
532 * set_dmic_clk - Set parameter of dmic.
533 *
534 * @w: DAPM widget.
535 * @kcontrol: The kcontrol of this widget.
536 * @event: Event id.
537 *
1319b2f6
OC		 538 */
539static int set_dmic_clk(struct snd_soc_dapm_widget *w,
540 struct snd_kcontrol *kcontrol, int event)
541{
c5f596cb 542 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6 543 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
49ef7925
OC		 544 int idx = -EINVAL;
545
546 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
1319b2f6
OC		 547
548 if (idx < 0)
549 dev_err(codec->dev, "Failed to set DMIC clock\n");
550 else
551 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
552 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
553 return idx;
554}
555
556static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
557 struct snd_soc_dapm_widget *sink)
558{
c5f596cb 559 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1319b2f6
OC		 560 unsigned int val;
561
c5f596cb 562 val = snd_soc_read(codec, RT5645_GLB_CLK);
1319b2f6
OC		 563 val &= RT5645_SCLK_SRC_MASK;
564 if (val == RT5645_SCLK_SRC_PLL1)
565 return 1;
566 else
567 return 0;
568}
569
9e268353
BL		 570static int is_using_asrc(struct snd_soc_dapm_widget *source,
571 struct snd_soc_dapm_widget *sink)
572{
c5f596cb 573 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
9e268353
BL		 574 unsigned int reg, shift, val;
575
576 switch (source->shift) {
577 case 0:
578 reg = RT5645_ASRC_3;
579 shift = 0;
580 break;
581 case 1:
582 reg = RT5645_ASRC_3;
583 shift = 4;
584 break;
585 case 3:
586 reg = RT5645_ASRC_2;
587 shift = 0;
588 break;
589 case 8:
590 reg = RT5645_ASRC_2;
591 shift = 4;
592 break;
593 case 9:
594 reg = RT5645_ASRC_2;
595 shift = 8;
596 break;
597 case 10:
598 reg = RT5645_ASRC_2;
599 shift = 12;
600 break;
601 default:
602 return 0;
603 }
604
c5f596cb 605 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
9e268353
BL		 606 switch (val) {
607 case 1:
608 case 2:
609 case 3:
610 case 4:
611 return 1;
612 default:
613 return 0;
614 }
615
616}
617
79080a8b
FY		 618/**
619 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
620 * @codec: SoC audio codec device.
621 * @filter_mask: mask of filters.
622 * @clk_src: clock source
623 *
624 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
625 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
626 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
627 * ASRC function will track i2s clock and generate a corresponding system clock
628 * for codec. This function provides an API to select the clock source for a
629 * set of filters specified by the mask. And the codec driver will turn on ASRC
630 * for these filters if ASRC is selected as their clock source.
631 */
632int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
633 unsigned int filter_mask, unsigned int clk_src)
634{
635 unsigned int asrc2_mask = 0;
636 unsigned int asrc2_value = 0;
637 unsigned int asrc3_mask = 0;
638 unsigned int asrc3_value = 0;
639
640 switch (clk_src) {
641 case RT5645_CLK_SEL_SYS:
642 case RT5645_CLK_SEL_I2S1_ASRC:
643 case RT5645_CLK_SEL_I2S2_ASRC:
644 case RT5645_CLK_SEL_SYS2:
645 break;
646
647 default:
648 return -EINVAL;
649 }
650
651 if (filter_mask & RT5645_DA_STEREO_FILTER) {
652 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
653 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
654 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
655 }
656
657 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
658 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
659 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
660 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
661 }
662
663 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
664 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
665 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
666 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
667 }
668
669 if (filter_mask & RT5645_AD_STEREO_FILTER) {
670 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
671 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
672 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
673 }
674
675 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
676 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
677 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
678 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
679 }
680
681 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
682 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
683 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
684 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
685 }
686
687 if (asrc2_mask)
688 snd_soc_update_bits(codec, RT5645_ASRC_2,
689 asrc2_mask, asrc2_value);
690
691 if (asrc3_mask)
692 snd_soc_update_bits(codec, RT5645_ASRC_3,
693 asrc3_mask, asrc3_value);
694
695 return 0;
696}
697EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
698
1319b2f6
OC		 699/* Digital Mixer */
700static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
701 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
702 RT5645_M_ADC_L1_SFT, 1, 1),
703 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
704 RT5645_M_ADC_L2_SFT, 1, 1),
705};
706
707static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
708 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
709 RT5645_M_ADC_R1_SFT, 1, 1),
710 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
711 RT5645_M_ADC_R2_SFT, 1, 1),
712};
713
714static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
715 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
716 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
717 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
718 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
719};
720
721static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
722 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
723 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
724 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
725 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
726};
727
728static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
729 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
730 RT5645_M_ADCMIX_L_SFT, 1, 1),
731 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
732 RT5645_M_DAC1_L_SFT, 1, 1),
733};
734
735static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
736 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
737 RT5645_M_ADCMIX_R_SFT, 1, 1),
738 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
739 RT5645_M_DAC1_R_SFT, 1, 1),
740};
741
742static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
743 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
744 RT5645_M_DAC_L1_SFT, 1, 1),
745 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
746 RT5645_M_DAC_L2_SFT, 1, 1),
747 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
748 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
749};
750
751static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
752 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
753 RT5645_M_DAC_R1_SFT, 1, 1),
754 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
755 RT5645_M_DAC_R2_SFT, 1, 1),
756 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
757 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
758};
759
760static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
761 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
762 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
763 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
764 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
765 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
766 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
767};
768
769static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
770 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
771 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
772 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
773 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
774 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
775 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
776};
777
778static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
779 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
780 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
781 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
782 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
783 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
784 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
785};
786
787static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
788 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
789 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
790 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
791 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
792 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
793 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
794};
795
796/* Analog Input Mixer */
797static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
798 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
799 RT5645_M_HP_L_RM_L_SFT, 1, 1),
800 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
801 RT5645_M_IN_L_RM_L_SFT, 1, 1),
802 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
803 RT5645_M_BST2_RM_L_SFT, 1, 1),
804 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
805 RT5645_M_BST1_RM_L_SFT, 1, 1),
806 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
807 RT5645_M_OM_L_RM_L_SFT, 1, 1),
808};
809
810static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
811 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
812 RT5645_M_HP_R_RM_R_SFT, 1, 1),
813 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
814 RT5645_M_IN_R_RM_R_SFT, 1, 1),
815 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
816 RT5645_M_BST2_RM_R_SFT, 1, 1),
817 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
818 RT5645_M_BST1_RM_R_SFT, 1, 1),
819 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
820 RT5645_M_OM_R_RM_R_SFT, 1, 1),
821};
822
823static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
824 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
825 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
826 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
827 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
828 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
829 RT5645_M_IN_L_SM_L_SFT, 1, 1),
830 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
831 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
832};
833
834static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
835 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
836 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
837 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
838 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
839 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
840 RT5645_M_IN_R_SM_R_SFT, 1, 1),
841 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
842 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
843};
844
845static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
846 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
847 RT5645_M_BST1_OM_L_SFT, 1, 1),
848 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
849 RT5645_M_IN_L_OM_L_SFT, 1, 1),
850 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
851 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
852 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
853 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
854};
855
856static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
857 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
858 RT5645_M_BST2_OM_R_SFT, 1, 1),
859 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
860 RT5645_M_IN_R_OM_R_SFT, 1, 1),
861 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
862 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
863 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
864 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
865};
866
867static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
868 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
869 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
870 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
871 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
872 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
873 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
874 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
875 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
876};
877
878static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
879 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
880 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
881 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
882 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
883};
884
885static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
886 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
887 RT5645_M_DAC1_HM_SFT, 1, 1),
888 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
889 RT5645_M_HPVOL_HM_SFT, 1, 1),
890};
891
892static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
893 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
894 RT5645_M_DAC1_HV_SFT, 1, 1),
895 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
896 RT5645_M_DAC2_HV_SFT, 1, 1),
897 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
898 RT5645_M_IN_HV_SFT, 1, 1),
899 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
900 RT5645_M_BST1_HV_SFT, 1, 1),
901};
902
903static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
904 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
905 RT5645_M_DAC1_HV_SFT, 1, 1),
906 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
907 RT5645_M_DAC2_HV_SFT, 1, 1),
908 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
909 RT5645_M_IN_HV_SFT, 1, 1),
910 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
911 RT5645_M_BST2_HV_SFT, 1, 1),
912};
913
914static const struct snd_kcontrol_new rt5645_lout_mix[] = {
915 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
916 RT5645_M_DAC_L1_LM_SFT, 1, 1),
917 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
918 RT5645_M_DAC_R1_LM_SFT, 1, 1),
919 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
920 RT5645_M_OV_L_LM_SFT, 1, 1),
921 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
922 RT5645_M_OV_R_LM_SFT, 1, 1),
923};
924
925/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
926static const char * const rt5645_dac1_src[] = {
927 "IF1 DAC", "IF2 DAC", "IF3 DAC"
928};
929
930static SOC_ENUM_SINGLE_DECL(
931 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
932 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
933
934static const struct snd_kcontrol_new rt5645_dac1l_mux =
935 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
936
937static SOC_ENUM_SINGLE_DECL(
938 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
939 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
940
941static const struct snd_kcontrol_new rt5645_dac1r_mux =
942 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
943
944/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
945static const char * const rt5645_dac12_src[] = {
946 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
947};
948
949static SOC_ENUM_SINGLE_DECL(
950 rt5645_dac2l_enum, RT5645_DAC_CTRL,
951 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
952
953static const struct snd_kcontrol_new rt5645_dac_l2_mux =
954 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
955
956static const char * const rt5645_dacr2_src[] = {
957 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
958};
959
960static SOC_ENUM_SINGLE_DECL(
961 rt5645_dac2r_enum, RT5645_DAC_CTRL,
962 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
963
964static const struct snd_kcontrol_new rt5645_dac_r2_mux =
965 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
966
967
968/* INL/R source */
969static const char * const rt5645_inl_src[] = {
970 "IN2P", "MonoP"
971};
972
973static SOC_ENUM_SINGLE_DECL(
974 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
975 RT5645_INL_SEL_SFT, rt5645_inl_src);
976
977static const struct snd_kcontrol_new rt5645_inl_mux =
978 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
979
980static const char * const rt5645_inr_src[] = {
981 "IN2N", "MonoN"
982};
983
984static SOC_ENUM_SINGLE_DECL(
985 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
986 RT5645_INR_SEL_SFT, rt5645_inr_src);
987
988static const struct snd_kcontrol_new rt5645_inr_mux =
989 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
990
991/* Stereo1 ADC source */
992/* MX-27 [12] */
993static const char * const rt5645_stereo_adc1_src[] = {
994 "DAC MIX", "ADC"
995};
996
997static SOC_ENUM_SINGLE_DECL(
998 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
999 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1000
1001static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1002 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1003
1004/* MX-27 [11] */
1005static const char * const rt5645_stereo_adc2_src[] = {
1006 "DAC MIX", "DMIC"
1007};
1008
1009static SOC_ENUM_SINGLE_DECL(
1010 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1011 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1012
1013static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1014 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1015
1016/* MX-27 [8] */
1017static const char * const rt5645_stereo_dmic_src[] = {
1018 "DMIC1", "DMIC2"
1019};
1020
1021static SOC_ENUM_SINGLE_DECL(
1022 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1023 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1024
1025static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1026 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1027
1028/* Mono ADC source */
1029/* MX-28 [12] */
1030static const char * const rt5645_mono_adc_l1_src[] = {
1031 "Mono DAC MIXL", "ADC"
1032};
1033
1034static SOC_ENUM_SINGLE_DECL(
1035 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1036 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1037
1038static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1039 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1040/* MX-28 [11] */
1041static const char * const rt5645_mono_adc_l2_src[] = {
1042 "Mono DAC MIXL", "DMIC"
1043};
1044
1045static SOC_ENUM_SINGLE_DECL(
1046 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1047 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1048
1049static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1050 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1051
1052/* MX-28 [8] */
1053static const char * const rt5645_mono_dmic_src[] = {
1054 "DMIC1", "DMIC2"
1055};
1056
1057static SOC_ENUM_SINGLE_DECL(
1058 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1059 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1060
1061static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1062 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1063/* MX-28 [1:0] */
1064static SOC_ENUM_SINGLE_DECL(
1065 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1066 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1067
1068static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1069 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1070/* MX-28 [4] */
1071static const char * const rt5645_mono_adc_r1_src[] = {
1072 "Mono DAC MIXR", "ADC"
1073};
1074
1075static SOC_ENUM_SINGLE_DECL(
1076 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1077 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1078
1079static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1080 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1081/* MX-28 [3] */
1082static const char * const rt5645_mono_adc_r2_src[] = {
1083 "Mono DAC MIXR", "DMIC"
1084};
1085
1086static SOC_ENUM_SINGLE_DECL(
1087 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1088 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1089
1090static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1091 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1092
1093/* MX-77 [9:8] */
1094static const char * const rt5645_if1_adc_in_src[] = {
1095 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1096};
1097
1098static SOC_ENUM_SINGLE_DECL(
1099 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1100 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1101
1102static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1103 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1104
5c4ca99d
BL		 1105/* MX-2d [3] [2] */
1106static const char * const rt5650_a_dac1_src[] = {
1107 "DAC1", "Stereo DAC Mixer"
1108};
1109
1110static SOC_ENUM_SINGLE_DECL(
1111 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1112 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1113
1114static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1115 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1116
1117static SOC_ENUM_SINGLE_DECL(
1118 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1119 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1120
1121static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1122 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1123
1124/* MX-2d [1] [0] */
1125static const char * const rt5650_a_dac2_src[] = {
1126 "Stereo DAC Mixer", "Mono DAC Mixer"
1127};
1128
1129static SOC_ENUM_SINGLE_DECL(
1130 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1131 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1132
1133static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1134 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1135
1136static SOC_ENUM_SINGLE_DECL(
1137 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1138 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1139
1140static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1141 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1142
1319b2f6
OC		 1143/* MX-2F [13:12] */
1144static const char * const rt5645_if2_adc_in_src[] = {
1145 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1146};
1147
1148static SOC_ENUM_SINGLE_DECL(
1149 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1150 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1151
1152static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1153 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1154
1155/* MX-2F [1:0] */
1156static const char * const rt5645_if3_adc_in_src[] = {
1157 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1158};
1159
1160static SOC_ENUM_SINGLE_DECL(
1161 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1162 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1163
1164static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1165 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1166
1167/* MX-31 [15] [13] [11] [9] */
1168static const char * const rt5645_pdm_src[] = {
1169 "Mono DAC", "Stereo DAC"
1170};
1171
1172static SOC_ENUM_SINGLE_DECL(
1173 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1174 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1175
1176static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1177 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1178
1179static SOC_ENUM_SINGLE_DECL(
1180 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1181 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1182
1183static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1184 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1185
1186/* MX-9D [9:8] */
1187static const char * const rt5645_vad_adc_src[] = {
1188 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1189};
1190
1191static SOC_ENUM_SINGLE_DECL(
1192 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1193 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1194
1195static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1196 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1197
1198static const struct snd_kcontrol_new spk_l_vol_control =
1199 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1200 RT5645_L_MUTE_SFT, 1, 1);
1201
1202static const struct snd_kcontrol_new spk_r_vol_control =
1203 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1204 RT5645_R_MUTE_SFT, 1, 1);
1205
1206static const struct snd_kcontrol_new hp_l_vol_control =
1207 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1208 RT5645_L_MUTE_SFT, 1, 1);
1209
1210static const struct snd_kcontrol_new hp_r_vol_control =
1211 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1212 RT5645_R_MUTE_SFT, 1, 1);
1213
1214static const struct snd_kcontrol_new pdm1_l_vol_control =
1215 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1216 RT5645_M_PDM1_L, 1, 1);
1217
1218static const struct snd_kcontrol_new pdm1_r_vol_control =
1219 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1220 RT5645_M_PDM1_R, 1, 1);
1221
1222static void hp_amp_power(struct snd_soc_codec *codec, int on)
1223{
1224 static int hp_amp_power_count;
1225 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1226
1227 if (on) {
1228 if (hp_amp_power_count <= 0) {
1229 /* depop parameters */
1230 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1231 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1232 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1233 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1234 RT5645_HP_DCC_INT1, 0x9f01);
1235 mdelay(150);
1236 /* headphone amp power on */
1237 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1238 RT5645_PWR_FV1 | RT5645_PWR_FV2 , 0);
1239 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1240 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1241 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1242 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1243 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1244 RT5645_PWR_HA,
1245 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1246 RT5645_PWR_HA);
1247 mdelay(5);
1248 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1249 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1250 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1251
1252 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1253 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1254 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1255 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1256 0x14, 0x1aaa);
1257 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1258 0x24, 0x0430);
1259 }
1260 hp_amp_power_count++;
1261 } else {
1262 hp_amp_power_count--;
1263 if (hp_amp_power_count <= 0) {
1264 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1265 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1266 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1267 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1268 /* headphone amp power down */
1269 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1270 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1271 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1272 RT5645_PWR_HA, 0);
37322551
BL		 1273 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1274 RT5645_DEPOP_MASK, 0);
1319b2f6
OC		 1275 }
1276 }
1277}
1278
1279static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1280 struct snd_kcontrol *kcontrol, int event)
1281{
c5f596cb 1282 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1283 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1284
1285 switch (event) {
1286 case SND_SOC_DAPM_POST_PMU:
1287 hp_amp_power(codec, 1);
1288 /* headphone unmute sequence */
5c4ca99d
BL		 1289 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1290 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1291 } else {
1292 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1293 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1294 RT5645_CP_FQ3_MASK,
1295 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1296 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1297 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1298 }
1319b2f6
OC		 1299 regmap_write(rt5645->regmap,
1300 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1301 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1302 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1303 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1304 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1305 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1306 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1307 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1308 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1309 msleep(40);
1310 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1311 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1312 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1313 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1314 break;
1315
1316 case SND_SOC_DAPM_PRE_PMD:
1317 /* headphone mute sequence */
5c4ca99d
BL		 1318 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1319 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1320 } else {
1321 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1322 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1323 RT5645_CP_FQ3_MASK,
1324 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1325 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1326 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1327 }
1319b2f6
OC		 1328 regmap_write(rt5645->regmap,
1329 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1330 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1331 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1332 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1333 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1334 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1335 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1336 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1337 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1338 msleep(30);
1339 hp_amp_power(codec, 0);
1340 break;
1341
1342 default:
1343 return 0;
1344 }
1345
1346 return 0;
1347}
1348
1349static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1350 struct snd_kcontrol *kcontrol, int event)
1351{
c5f596cb 1352 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1353
1354 switch (event) {
1355 case SND_SOC_DAPM_POST_PMU:
1356 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1357 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1358 RT5645_PWR_CLS_D_L,
1359 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1360 RT5645_PWR_CLS_D_L);
1361 break;
1362
1363 case SND_SOC_DAPM_PRE_PMD:
1364 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1365 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1366 RT5645_PWR_CLS_D_L, 0);
1367 break;
1368
1369 default:
1370 return 0;
1371 }
1372
1373 return 0;
1374}
1375
1376static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1377 struct snd_kcontrol *kcontrol, int event)
1378{
c5f596cb 1379 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1380
1381 switch (event) {
1382 case SND_SOC_DAPM_POST_PMU:
1383 hp_amp_power(codec, 1);
1384 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1385 RT5645_PWR_LM, RT5645_PWR_LM);
1386 snd_soc_update_bits(codec, RT5645_LOUT1,
1387 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1388 break;
1389
1390 case SND_SOC_DAPM_PRE_PMD:
1391 snd_soc_update_bits(codec, RT5645_LOUT1,
1392 RT5645_L_MUTE | RT5645_R_MUTE,
1393 RT5645_L_MUTE | RT5645_R_MUTE);
1394 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1395 RT5645_PWR_LM, 0);
1396 hp_amp_power(codec, 0);
1397 break;
1398
1399 default:
1400 return 0;
1401 }
1402
1403 return 0;
1404}
1405
1406static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1407 struct snd_kcontrol *kcontrol, int event)
1408{
c5f596cb 1409 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1410
1411 switch (event) {
1412 case SND_SOC_DAPM_POST_PMU:
1413 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1414 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1415 break;
1416
1417 case SND_SOC_DAPM_PRE_PMD:
1418 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1419 RT5645_PWR_BST2_P, 0);
1420 break;
1421
1422 default:
1423 return 0;
1424 }
1425
1426 return 0;
1427}
1428
1429static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1430 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1431 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1432 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1433 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1434
1435 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1436 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1437 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1438 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1439
9e268353
BL		 1440 /* ASRC */
1441 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1442 11, 0, NULL, 0),
1443 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1444 12, 0, NULL, 0),
1445 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1446 10, 0, NULL, 0),
1447 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1448 9, 0, NULL, 0),
1449 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1450 8, 0, NULL, 0),
1451 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1452 7, 0, NULL, 0),
1453 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1454 5, 0, NULL, 0),
1455 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1456 4, 0, NULL, 0),
1457 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1458 3, 0, NULL, 0),
1459 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1460 1, 0, NULL, 0),
1461 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1462 0, 0, NULL, 0),
1463
1319b2f6
OC		 1464 /* Input Side */
1465 /* micbias */
1466 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1467 RT5645_PWR_MB1_BIT, 0),
1468 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1469 RT5645_PWR_MB2_BIT, 0),
1470 /* Input Lines */
1471 SND_SOC_DAPM_INPUT("DMIC L1"),
1472 SND_SOC_DAPM_INPUT("DMIC R1"),
1473 SND_SOC_DAPM_INPUT("DMIC L2"),
1474 SND_SOC_DAPM_INPUT("DMIC R2"),
1475
1476 SND_SOC_DAPM_INPUT("IN1P"),
1477 SND_SOC_DAPM_INPUT("IN1N"),
1478 SND_SOC_DAPM_INPUT("IN2P"),
1479 SND_SOC_DAPM_INPUT("IN2N"),
1480
1481 SND_SOC_DAPM_INPUT("Haptic Generator"),
1482
1483 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1484 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1485 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1486 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1487 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1488 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1489 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1490 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1491 /* Boost */
1492 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1493 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1494 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1495 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1496 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1497 /* Input Volume */
1498 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1499 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1500 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1501 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1502 /* REC Mixer */
1503 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1504 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1505 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1506 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1507 /* ADCs */
1508 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1509 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1510
1511 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1512 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1513 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1514 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1515
1516 /* ADC Mux */
1517 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1518 &rt5645_sto1_dmic_mux),
1519 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1520 &rt5645_sto_adc2_mux),
1521 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1522 &rt5645_sto_adc2_mux),
1523 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1524 &rt5645_sto_adc1_mux),
1525 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1526 &rt5645_sto_adc1_mux),
1527 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1528 &rt5645_mono_dmic_l_mux),
1529 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1530 &rt5645_mono_dmic_r_mux),
1531 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1532 &rt5645_mono_adc_l2_mux),
1533 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1534 &rt5645_mono_adc_l1_mux),
1535 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1536 &rt5645_mono_adc_r1_mux),
1537 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1538 &rt5645_mono_adc_r2_mux),
1539 /* ADC Mixer */
1540
1541 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1542 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1319b2f6
OC		 1543 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1544 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1545 NULL, 0),
1546 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1547 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1548 NULL, 0),
1549 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1550 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1551 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1552 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1553 NULL, 0),
1554 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1555 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1556 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1557 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1558 NULL, 0),
1559
1560 /* ADC PGA */
1561 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1562 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1563 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1564 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1565 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1566 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1567 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1568 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1569 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1570 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1571
1572 /* IF1 2 Mux */
1573 SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM,
1574 0, 0, &rt5645_if1_adc_in_mux),
1575 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1576 0, 0, &rt5645_if2_adc_in_mux),
1577
1578 /* Digital Interface */
1579 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1580 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1581 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1582 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1583 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1584 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1585 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1586 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1587 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1588 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1589 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1590 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1591 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1592 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1593 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1594 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1595 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1596
1597 /* Digital Interface Select */
1598 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1599 0, 0, &rt5645_vad_adc_mux),
1600
1601 /* Audio Interface */
1602 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1603 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1604 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1605 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1606
1607 /* Output Side */
1608 /* DAC mixer before sound effect */
1609 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1610 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1611 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1612 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1613
1614 /* DAC2 channel Mux */
1615 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1616 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1617 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1618 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1619 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1620 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1621
1622 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1623 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1624
1625 /* DAC Mixer */
1626 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1627 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1628 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1629 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1630 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1631 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1632 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1633 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1634 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1635 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1636 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1637 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1638 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1639 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1640 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1641 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1642 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1643 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1644
1645 /* DACs */
1646 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1647 0),
1648 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1649 0),
1650 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1651 0),
1652 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1653 0),
1654 /* OUT Mixer */
1655 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1656 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1657 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1658 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1659 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1660 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1661 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1662 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1663 /* Ouput Volume */
1664 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1665 &spk_l_vol_control),
1666 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1667 &spk_r_vol_control),
1668 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1669 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1670 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1671 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1672 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1673 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1674 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1675 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1676 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1677 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1678 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1679 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1680 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1681
1682 /* HPO/LOUT/Mono Mixer */
1683 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1684 ARRAY_SIZE(rt5645_spo_l_mix)),
1685 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1686 ARRAY_SIZE(rt5645_spo_r_mix)),
1687 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1688 ARRAY_SIZE(rt5645_hpo_mix)),
1689 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1690 ARRAY_SIZE(rt5645_lout_mix)),
1691
1692 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1693 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1694 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1695 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1696 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1697 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1698
1699 /* PDM */
1700 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1701 0, NULL, 0),
1702 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1703 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1704
1705 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1706 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1707
1708 /* Output Lines */
1709 SND_SOC_DAPM_OUTPUT("HPOL"),
1710 SND_SOC_DAPM_OUTPUT("HPOR"),
1711 SND_SOC_DAPM_OUTPUT("LOUTL"),
1712 SND_SOC_DAPM_OUTPUT("LOUTR"),
1713 SND_SOC_DAPM_OUTPUT("PDM1L"),
1714 SND_SOC_DAPM_OUTPUT("PDM1R"),
1715 SND_SOC_DAPM_OUTPUT("SPOL"),
1716 SND_SOC_DAPM_OUTPUT("SPOR"),
1717};
1718
5c4ca99d
BL		 1719static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
1720 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
1721 0, 0, &rt5650_a_dac1_l_mux),
1722 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
1723 0, 0, &rt5650_a_dac1_r_mux),
1724 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
1725 0, 0, &rt5650_a_dac2_l_mux),
1726 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
1727 0, 0, &rt5650_a_dac2_r_mux),
1728};
1729
1319b2f6 1730static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
9e268353 1731 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
9e268353
BL		 1732 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1733 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1734 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1735 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1736 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1737
1738 { "I2S1", NULL, "I2S1 ASRC" },
1739 { "I2S2", NULL, "I2S2 ASRC" },
1740
1319b2f6
OC		 1741 { "IN1P", NULL, "LDO2" },
1742 { "IN2P", NULL, "LDO2" },
1743
1744 { "DMIC1", NULL, "DMIC L1" },
1745 { "DMIC1", NULL, "DMIC R1" },
1746 { "DMIC2", NULL, "DMIC L2" },
1747 { "DMIC2", NULL, "DMIC R2" },
1748
1749 { "BST1", NULL, "IN1P" },
1750 { "BST1", NULL, "IN1N" },
1751 { "BST1", NULL, "JD Power" },
1752 { "BST1", NULL, "Mic Det Power" },
1753 { "BST2", NULL, "IN2P" },
1754 { "BST2", NULL, "IN2N" },
1755
1756 { "INL VOL", NULL, "IN2P" },
1757 { "INR VOL", NULL, "IN2N" },
1758
1759 { "RECMIXL", "HPOL Switch", "HPOL" },
1760 { "RECMIXL", "INL Switch", "INL VOL" },
1761 { "RECMIXL", "BST2 Switch", "BST2" },
1762 { "RECMIXL", "BST1 Switch", "BST1" },
1763 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1764
1765 { "RECMIXR", "HPOR Switch", "HPOR" },
1766 { "RECMIXR", "INR Switch", "INR VOL" },
1767 { "RECMIXR", "BST2 Switch", "BST2" },
1768 { "RECMIXR", "BST1 Switch", "BST1" },
1769 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1770
1771 { "ADC L", NULL, "RECMIXL" },
1772 { "ADC L", NULL, "ADC L power" },
1773 { "ADC R", NULL, "RECMIXR" },
1774 { "ADC R", NULL, "ADC R power" },
1775
1776 {"DMIC L1", NULL, "DMIC CLK"},
1777 {"DMIC L1", NULL, "DMIC1 Power"},
1778 {"DMIC R1", NULL, "DMIC CLK"},
1779 {"DMIC R1", NULL, "DMIC1 Power"},
1780 {"DMIC L2", NULL, "DMIC CLK"},
1781 {"DMIC L2", NULL, "DMIC2 Power"},
1782 {"DMIC R2", NULL, "DMIC CLK"},
1783 {"DMIC R2", NULL, "DMIC2 Power"},
1784
1785 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1786 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
9e268353 1787 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1319b2f6
OC		 1788
1789 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1790 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
9e268353 1791 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1319b2f6
OC		 1792
1793 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1794 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
9e268353 1795 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1319b2f6
OC		 1796
1797 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1798 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1799 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1800 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1801
1802 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1803 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1804 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1805 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1806
1807 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1808 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1809 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1810 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1811
1812 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1813 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1814 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1815 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1816
1817 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1818 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1819 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1820 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1821
1822 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1823 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1824 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1825
1826 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1827 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1828 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1829
1830 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1831 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1832 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1833 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1834
1835 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1836 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1837 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1838 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1839
1840 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1841 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1842 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1843
1844 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1845 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1846 { "IF_ADC2", NULL, "Mono ADC MIXL" },
1847 { "IF_ADC2", NULL, "Mono ADC MIXR" },
1848 { "VAD_ADC", NULL, "VAD ADC Mux" },
1849
1850 { "IF1 ADC Mux", "IF_ADC1", "IF_ADC1" },
1851 { "IF1 ADC Mux", "IF_ADC2", "IF_ADC2" },
1852 { "IF1 ADC Mux", "VAD_ADC", "VAD_ADC" },
1853
1854 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1855 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1856 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1857
1858 { "IF1 ADC", NULL, "I2S1" },
1859 { "IF1 ADC", NULL, "IF1 ADC Mux" },
1860 { "IF2 ADC", NULL, "I2S2" },
1861 { "IF2 ADC", NULL, "IF2 ADC Mux" },
1862
1863 { "AIF1TX", NULL, "IF1 ADC" },
1864 { "AIF1TX", NULL, "IF2 ADC" },
1865 { "AIF2TX", NULL, "IF2 ADC" },
1866
1867 { "IF1 DAC1", NULL, "AIF1RX" },
1868 { "IF1 DAC2", NULL, "AIF1RX" },
1869 { "IF2 DAC", NULL, "AIF2RX" },
1870
1871 { "IF1 DAC1", NULL, "I2S1" },
1872 { "IF1 DAC2", NULL, "I2S1" },
1873 { "IF2 DAC", NULL, "I2S2" },
1874
1875 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
1876 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
1877 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
1878 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
1879 { "IF2 DAC L", NULL, "IF2 DAC" },
1880 { "IF2 DAC R", NULL, "IF2 DAC" },
1881
1882 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1883 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1884
1885 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1886 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1887
1888 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1889 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1890 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
1891 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1892 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1893 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
1894
1895 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1896 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1897 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
1898 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1899 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
1900 { "DAC L2 Volume", NULL, "dac mono left filter" },
1901
1902 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1903 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1904 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
1905 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
1906 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
1907 { "DAC R2 Volume", NULL, "dac mono right filter" },
1908
1909 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1910 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1911 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1912 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
1913 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1914 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1915 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1916 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
1917
1918 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1919 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1920 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1921 { "Mono DAC MIXL", NULL, "dac mono left filter" },
1922 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1923 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1924 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1925 { "Mono DAC MIXR", NULL, "dac mono right filter" },
1926
1927 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1928 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1929 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1930 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1931 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1932 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1933
1319b2f6 1934 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 1935 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 1936 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6
OC		 1937 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1938
1939 { "SPK MIXL", "BST1 Switch", "BST1" },
1940 { "SPK MIXL", "INL Switch", "INL VOL" },
1941 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
1942 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
1943 { "SPK MIXR", "BST2 Switch", "BST2" },
1944 { "SPK MIXR", "INR Switch", "INR VOL" },
1945 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
1946 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
1947
1948 { "OUT MIXL", "BST1 Switch", "BST1" },
1949 { "OUT MIXL", "INL Switch", "INL VOL" },
1950 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1951 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1952
1953 { "OUT MIXR", "BST2 Switch", "BST2" },
1954 { "OUT MIXR", "INR Switch", "INR VOL" },
1955 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1956 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1957
1958 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1959 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
1960 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
1961 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
1962 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
1963 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1964 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
1965 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
1966 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
1967 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
1968
1969 { "DAC 2", NULL, "DAC L2" },
1970 { "DAC 2", NULL, "DAC R2" },
1971 { "DAC 1", NULL, "DAC L1" },
1972 { "DAC 1", NULL, "DAC R1" },
1973 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
1974 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
1975 { "HPOVOL", NULL, "HPOVOL L" },
1976 { "HPOVOL", NULL, "HPOVOL R" },
1977 { "HPO MIX", "DAC1 Switch", "DAC 1" },
1978 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
1979
1980 { "SPKVOL L", "Switch", "SPK MIXL" },
1981 { "SPKVOL R", "Switch", "SPK MIXR" },
1982
1983 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
1984 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
1985 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
1986 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
1987 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
1988 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
1989
1990 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1991 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1992 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
1993 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
1994
1995 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1996 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
1997 { "PDM1 L Mux", NULL, "PDM1 Power" },
1998 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
1999 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2000 { "PDM1 R Mux", NULL, "PDM1 Power" },
2001
2002 { "HP amp", NULL, "HPO MIX" },
2003 { "HP amp", NULL, "JD Power" },
2004 { "HP amp", NULL, "Mic Det Power" },
2005 { "HP amp", NULL, "LDO2" },
2006 { "HPOL", NULL, "HP amp" },
2007 { "HPOR", NULL, "HP amp" },
2008
2009 { "LOUT amp", NULL, "LOUT MIX" },
2010 { "LOUTL", NULL, "LOUT amp" },
2011 { "LOUTR", NULL, "LOUT amp" },
2012
2013 { "PDM1 L", "Switch", "PDM1 L Mux" },
2014 { "PDM1 R", "Switch", "PDM1 R Mux" },
2015
2016 { "PDM1L", NULL, "PDM1 L" },
2017 { "PDM1R", NULL, "PDM1 R" },
2018
2019 { "SPK amp", NULL, "SPOL MIX" },
2020 { "SPK amp", NULL, "SPOR MIX" },
2021 { "SPOL", NULL, "SPK amp" },
2022 { "SPOR", NULL, "SPK amp" },
2023};
2024
5c4ca99d
BL		 2025static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2026 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2027 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2028 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2029 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2030
2031 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2032 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2033 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2034 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2035
2036 { "DAC L1", NULL, "A DAC1 L Mux" },
2037 { "DAC R1", NULL, "A DAC1 R Mux" },
2038 { "DAC L2", NULL, "A DAC2 L Mux" },
2039 { "DAC R2", NULL, "A DAC2 R Mux" },
2040};
2041
2042static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2043 { "DAC L1", NULL, "Stereo DAC MIXL" },
2044 { "DAC R1", NULL, "Stereo DAC MIXR" },
2045 { "DAC L2", NULL, "Mono DAC MIXL" },
2046 { "DAC R2", NULL, "Mono DAC MIXR" },
2047};
2048
1319b2f6
OC		 2049static int rt5645_hw_params(struct snd_pcm_substream *substream,
2050 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2051{
2052 struct snd_soc_codec *codec = dai->codec;
2053 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736 2054 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
1319b2f6
OC		 2055 int pre_div, bclk_ms, frame_size;
2056
2057 rt5645->lrck[dai->id] = params_rate(params);
d92950e7 2058 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1319b2f6
OC		 2059 if (pre_div < 0) {
2060 dev_err(codec->dev, "Unsupported clock setting\n");
2061 return -EINVAL;
2062 }
2063 frame_size = snd_soc_params_to_frame_size(params);
2064 if (frame_size < 0) {
2065 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2066 return -EINVAL;
2067 }
57bf2736
BL		 2068
2069 switch (rt5645->codec_type) {
2070 case CODEC_TYPE_RT5650:
2071 dl_sft = 4;
2072 break;
2073 default:
2074 dl_sft = 2;
2075 break;
2076 }
2077
1319b2f6
OC		 2078 bclk_ms = frame_size > 32;
2079 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2080
2081 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2082 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2083 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2084 bclk_ms, pre_div, dai->id);
2085
2086 switch (params_width(params)) {
2087 case 16:
2088 break;
2089 case 20:
57bf2736 2090 val_len = 0x1;
1319b2f6
OC		 2091 break;
2092 case 24:
57bf2736 2093 val_len = 0x2;
1319b2f6
OC		 2094 break;
2095 case 8:
57bf2736 2096 val_len = 0x3;
1319b2f6
OC		 2097 break;
2098 default:
2099 return -EINVAL;
2100 }
2101
2102 switch (dai->id) {
2103 case RT5645_AIF1:
2104 mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK;
2105 val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT |
2106 pre_div << RT5645_I2S_PD1_SFT;
2107 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2108 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2109 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2110 break;
2111 case RT5645_AIF2:
2112 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2113 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2114 pre_div << RT5645_I2S_PD2_SFT;
2115 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2116 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2117 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2118 break;
2119 default:
2120 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2121 return -EINVAL;
2122 }
2123
2124 return 0;
2125}
2126
2127static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2128{
2129 struct snd_soc_codec *codec = dai->codec;
2130 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736
BL		 2131 unsigned int reg_val = 0, pol_sft;
2132
2133 switch (rt5645->codec_type) {
2134 case CODEC_TYPE_RT5650:
2135 pol_sft = 8;
2136 break;
2137 default:
2138 pol_sft = 7;
2139 break;
2140 }
1319b2f6
OC		 2141
2142 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2143 case SND_SOC_DAIFMT_CBM_CFM:
2144 rt5645->master[dai->id] = 1;
2145 break;
2146 case SND_SOC_DAIFMT_CBS_CFS:
2147 reg_val |= RT5645_I2S_MS_S;
2148 rt5645->master[dai->id] = 0;
2149 break;
2150 default:
2151 return -EINVAL;
2152 }
2153
2154 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2155 case SND_SOC_DAIFMT_NB_NF:
2156 break;
2157 case SND_SOC_DAIFMT_IB_NF:
57bf2736 2158 reg_val |= (1 << pol_sft);
1319b2f6
OC		 2159 break;
2160 default:
2161 return -EINVAL;
2162 }
2163
2164 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2165 case SND_SOC_DAIFMT_I2S:
2166 break;
2167 case SND_SOC_DAIFMT_LEFT_J:
2168 reg_val |= RT5645_I2S_DF_LEFT;
2169 break;
2170 case SND_SOC_DAIFMT_DSP_A:
2171 reg_val |= RT5645_I2S_DF_PCM_A;
2172 break;
2173 case SND_SOC_DAIFMT_DSP_B:
2174 reg_val |= RT5645_I2S_DF_PCM_B;
2175 break;
2176 default:
2177 return -EINVAL;
2178 }
2179 switch (dai->id) {
2180 case RT5645_AIF1:
2181 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2182 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2183 RT5645_I2S_DF_MASK, reg_val);
2184 break;
8c325704
AL		 2185 case RT5645_AIF2:
2186 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2187 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2188 RT5645_I2S_DF_MASK, reg_val);
2189 break;
2190 default:
2191 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2192 return -EINVAL;
2193 }
2194 return 0;
2195}
2196
2197static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2198 int clk_id, unsigned int freq, int dir)
2199{
2200 struct snd_soc_codec *codec = dai->codec;
2201 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2202 unsigned int reg_val = 0;
2203
2204 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2205 return 0;
2206
2207 switch (clk_id) {
2208 case RT5645_SCLK_S_MCLK:
2209 reg_val |= RT5645_SCLK_SRC_MCLK;
2210 break;
2211 case RT5645_SCLK_S_PLL1:
2212 reg_val |= RT5645_SCLK_SRC_PLL1;
2213 break;
2214 case RT5645_SCLK_S_RCCLK:
2215 reg_val |= RT5645_SCLK_SRC_RCCLK;
2216 break;
2217 default:
2218 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2219 return -EINVAL;
2220 }
2221 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2222 RT5645_SCLK_SRC_MASK, reg_val);
2223 rt5645->sysclk = freq;
2224 rt5645->sysclk_src = clk_id;
2225
2226 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2227
2228 return 0;
2229}
2230
1319b2f6
OC		 2231static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2232 unsigned int freq_in, unsigned int freq_out)
2233{
2234 struct snd_soc_codec *codec = dai->codec;
2235 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
71c7a2d6 2236 struct rl6231_pll_code pll_code;
1319b2f6
OC		 2237 int ret;
2238
2239 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2240 freq_out == rt5645->pll_out)
2241 return 0;
2242
2243 if (!freq_in || !freq_out) {
2244 dev_dbg(codec->dev, "PLL disabled\n");
2245
2246 rt5645->pll_in = 0;
2247 rt5645->pll_out = 0;
2248 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2249 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2250 return 0;
2251 }
2252
2253 switch (source) {
2254 case RT5645_PLL1_S_MCLK:
2255 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2256 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2257 break;
2258 case RT5645_PLL1_S_BCLK1:
2259 case RT5645_PLL1_S_BCLK2:
2260 switch (dai->id) {
2261 case RT5645_AIF1:
2262 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2263 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2264 break;
2265 case RT5645_AIF2:
2266 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2267 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2268 break;
2269 default:
2270 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2271 return -EINVAL;
2272 }
2273 break;
2274 default:
2275 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2276 return -EINVAL;
2277 }
2278
71c7a2d6 2279 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1319b2f6
OC		 2280 if (ret < 0) {
2281 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2282 return ret;
2283 }
2284
2285 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2286 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2287 pll_code.n_code, pll_code.k_code);
2288
2289 snd_soc_write(codec, RT5645_PLL_CTRL1,
2290 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2291 snd_soc_write(codec, RT5645_PLL_CTRL2,
2292 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2293 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2294
2295 rt5645->pll_in = freq_in;
2296 rt5645->pll_out = freq_out;
2297 rt5645->pll_src = source;
2298
2299 return 0;
2300}
2301
2302static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2303 unsigned int rx_mask, int slots, int slot_width)
2304{
2305 struct snd_soc_codec *codec = dai->codec;
42ce5b8a
BL		 2306 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2307 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2308 unsigned int mask, val = 0;
2309
2310 switch (rt5645->codec_type) {
2311 case CODEC_TYPE_RT5650:
2312 en_sft = 15;
2313 i_slot_sft = 10;
2314 o_slot_sft = 8;
2315 i_width_sht = 6;
2316 o_width_sht = 4;
2317 mask = 0x8ff0;
2318 break;
2319 default:
2320 en_sft = 14;
2321 i_slot_sft = o_slot_sft = 12;
2322 i_width_sht = o_width_sht = 10;
2323 mask = 0x7c00;
2324 break;
2325 }
850577db 2326 if (rx_mask || tx_mask) {
42ce5b8a
BL		 2327 val |= (1 << en_sft);
2328 if (rt5645->codec_type == CODEC_TYPE_RT5645)
2329 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2330 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
850577db 2331 }
1319b2f6
OC		 2332
2333 switch (slots) {
2334 case 4:
42ce5b8a 2335 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
1319b2f6
OC		 2336 break;
2337 case 6:
42ce5b8a 2338 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
1319b2f6
OC		 2339 break;
2340 case 8:
42ce5b8a 2341 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
1319b2f6
OC		 2342 break;
2343 case 2:
2344 default:
2345 break;
2346 }
2347
2348 switch (slot_width) {
2349 case 20:
42ce5b8a 2350 val |= (1 << i_width_sht) | (1 << o_width_sht);
1319b2f6
OC		 2351 break;
2352 case 24:
42ce5b8a 2353 val |= (2 << i_width_sht) | (2 << o_width_sht);
1319b2f6
OC		 2354 break;
2355 case 32:
42ce5b8a 2356 val |= (3 << i_width_sht) | (3 << o_width_sht);
1319b2f6
OC		 2357 break;
2358 case 16:
2359 default:
2360 break;
2361 }
2362
42ce5b8a 2363 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
1319b2f6
OC		 2364
2365 return 0;
2366}
2367
2368static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2369 enum snd_soc_bias_level level)
2370{
2371 switch (level) {
0b2e4959
BL		 2372 case SND_SOC_BIAS_PREPARE:
2373 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
1319b2f6
OC		 2374 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2375 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2376 RT5645_PWR_BG | RT5645_PWR_VREF2,
2377 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2378 RT5645_PWR_BG | RT5645_PWR_VREF2);
2379 mdelay(10);
2380 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2381 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2382 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2383 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2384 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2385 }
2386 break;
2387
0b2e4959
BL		 2388 case SND_SOC_BIAS_STANDBY:
2389 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2390 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2391 RT5645_PWR_BG | RT5645_PWR_VREF2,
2392 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2393 RT5645_PWR_BG | RT5645_PWR_VREF2);
2394 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2395 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2396 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2397 break;
2398
1319b2f6
OC		 2399 case SND_SOC_BIAS_OFF:
2400 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
1b5d0160
BL		 2401 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2402 RT5645_DIG_GATE_CTRL, 0);
0b2e4959
BL		 2403 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2404 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2405 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2406 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
1319b2f6
OC		 2407 break;
2408
2409 default:
2410 break;
2411 }
2412 codec->dapm.bias_level = level;
2413
2414 return 0;
2415}
2416
471f208a 2417static int rt5645_jack_detect(struct snd_soc_codec *codec)
f3fa1bbd
OC		 2418{
2419 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2420 int gpio_state, jack_type = 0;
2421 unsigned int val;
2422
75945896
BL		 2423 if (!gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2424 dev_err(codec->dev, "invalid gpio\n");
2425 return -EINVAL;
2426 }
f3fa1bbd
OC		 2427 gpio_state = gpio_get_value(rt5645->pdata.hp_det_gpio);
2428
2429 dev_dbg(codec->dev, "gpio = %d(%d)\n", rt5645->pdata.hp_det_gpio,
2430 gpio_state);
2431
2432 if ((rt5645->pdata.gpio_hp_det_active_high && gpio_state) ||
2433 (!rt5645->pdata.gpio_hp_det_active_high && !gpio_state)) {
2434 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias1");
2435 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias2");
2436 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2437 snd_soc_dapm_force_enable_pin(&codec->dapm, "Mic Det Power");
2438 snd_soc_dapm_sync(&codec->dapm);
2439
2440 snd_soc_write(codec, RT5645_IN1_CTRL1, 0x0006);
2441 snd_soc_write(codec, RT5645_JD_CTRL3, 0x00b0);
2442
2443 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2444 RT5645_CBJ_MN_JD, 0);
2445 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2446 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
2447
2448 msleep(400);
2449 val = snd_soc_read(codec, RT5645_IN1_CTRL3) & 0x7;
2450 dev_dbg(codec->dev, "val = %d\n", val);
2451
2452 if (val == 1 || val == 2)
2453 jack_type = SND_JACK_HEADSET;
2454 else
2455 jack_type = SND_JACK_HEADPHONE;
2456
2457 snd_soc_dapm_disable_pin(&codec->dapm, "micbias1");
2458 snd_soc_dapm_disable_pin(&codec->dapm, "micbias2");
2d4e2d02
BL		 2459 if (rt5645->pdata.jd_mode == 0)
2460 snd_soc_dapm_disable_pin(&codec->dapm, "LDO2");
f3fa1bbd
OC		 2461 snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power");
2462 snd_soc_dapm_sync(&codec->dapm);
2463 }
2464
471f208a
BL		 2465 snd_soc_jack_report(rt5645->hp_jack, jack_type, SND_JACK_HEADPHONE);
2466 snd_soc_jack_report(rt5645->mic_jack, jack_type, SND_JACK_MICROPHONE);
f3fa1bbd
OC		 2467 return 0;
2468}
2469
2470int rt5645_set_jack_detect(struct snd_soc_codec *codec,
471f208a 2471 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
f3fa1bbd
OC		 2472{
2473 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2474
471f208a
BL		 2475 rt5645->hp_jack = hp_jack;
2476 rt5645->mic_jack = mic_jack;
2477 rt5645_jack_detect(codec);
f3fa1bbd
OC		 2478
2479 return 0;
2480}
2481EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2482
cd6e82b8
OC		 2483static void rt5645_jack_detect_work(struct work_struct *work)
2484{
2485 struct rt5645_priv *rt5645 =
2486 container_of(work, struct rt5645_priv, jack_detect_work.work);
2487
471f208a 2488 rt5645_jack_detect(rt5645->codec);
cd6e82b8
OC		 2489}
2490
f3fa1bbd
OC		 2491static irqreturn_t rt5645_irq(int irq, void *data)
2492{
2493 struct rt5645_priv *rt5645 = data;
2494
cd6e82b8
OC		 2495 queue_delayed_work(system_power_efficient_wq,
2496 &rt5645->jack_detect_work, msecs_to_jiffies(250));
f3fa1bbd
OC		 2497
2498 return IRQ_HANDLED;
2499}
2500
1319b2f6
OC		 2501static int rt5645_probe(struct snd_soc_codec *codec)
2502{
2503 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2504
2505 rt5645->codec = codec;
2506
5c4ca99d
BL		 2507 switch (rt5645->codec_type) {
2508 case CODEC_TYPE_RT5645:
2509 snd_soc_dapm_add_routes(&codec->dapm,
2510 rt5645_specific_dapm_routes,
2511 ARRAY_SIZE(rt5645_specific_dapm_routes));
2512 break;
2513 case CODEC_TYPE_RT5650:
2514 snd_soc_dapm_new_controls(&codec->dapm,
2515 rt5650_specific_dapm_widgets,
2516 ARRAY_SIZE(rt5650_specific_dapm_widgets));
2517 snd_soc_dapm_add_routes(&codec->dapm,
2518 rt5650_specific_dapm_routes,
2519 ARRAY_SIZE(rt5650_specific_dapm_routes));
2520 break;
2521 }
2522
1319b2f6
OC		 2523 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2524
2525 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
1319b2f6 2526
bb656add
BL		 2527 /* for JD function */
2528 if (rt5645->pdata.en_jd_func) {
2529 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
2530 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2531 snd_soc_dapm_sync(&codec->dapm);
2532 }
2533
1319b2f6
OC		 2534 return 0;
2535}
2536
2537static int rt5645_remove(struct snd_soc_codec *codec)
2538{
2539 rt5645_reset(codec);
2540 return 0;
2541}
2542
2543#ifdef CONFIG_PM
2544static int rt5645_suspend(struct snd_soc_codec *codec)
2545{
2546 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2547
2548 regcache_cache_only(rt5645->regmap, true);
2549 regcache_mark_dirty(rt5645->regmap);
2550
2551 return 0;
2552}
2553
2554static int rt5645_resume(struct snd_soc_codec *codec)
2555{
2556 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2557
2558 regcache_cache_only(rt5645->regmap, false);
0f776efd 2559 regcache_sync(rt5645->regmap);
1319b2f6
OC		 2560
2561 return 0;
2562}
2563#else
2564#define rt5645_suspend NULL
2565#define rt5645_resume NULL
2566#endif
2567
2568#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2569#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2570 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2571
9e22f782 2572static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
1319b2f6
OC		 2573 .hw_params = rt5645_hw_params,
2574 .set_fmt = rt5645_set_dai_fmt,
2575 .set_sysclk = rt5645_set_dai_sysclk,
2576 .set_tdm_slot = rt5645_set_tdm_slot,
2577 .set_pll = rt5645_set_dai_pll,
2578};
2579
9e22f782 2580static struct snd_soc_dai_driver rt5645_dai[] = {
1319b2f6
OC		 2581 {
2582 .name = "rt5645-aif1",
2583 .id = RT5645_AIF1,
2584 .playback = {
2585 .stream_name = "AIF1 Playback",
2586 .channels_min = 1,
2587 .channels_max = 2,
2588 .rates = RT5645_STEREO_RATES,
2589 .formats = RT5645_FORMATS,
2590 },
2591 .capture = {
2592 .stream_name = "AIF1 Capture",
2593 .channels_min = 1,
2594 .channels_max = 2,
2595 .rates = RT5645_STEREO_RATES,
2596 .formats = RT5645_FORMATS,
2597 },
2598 .ops = &rt5645_aif_dai_ops,
2599 },
2600 {
2601 .name = "rt5645-aif2",
2602 .id = RT5645_AIF2,
2603 .playback = {
2604 .stream_name = "AIF2 Playback",
2605 .channels_min = 1,
2606 .channels_max = 2,
2607 .rates = RT5645_STEREO_RATES,
2608 .formats = RT5645_FORMATS,
2609 },
2610 .capture = {
2611 .stream_name = "AIF2 Capture",
2612 .channels_min = 1,
2613 .channels_max = 2,
2614 .rates = RT5645_STEREO_RATES,
2615 .formats = RT5645_FORMATS,
2616 },
2617 .ops = &rt5645_aif_dai_ops,
2618 },
2619};
2620
2621static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
2622 .probe = rt5645_probe,
2623 .remove = rt5645_remove,
2624 .suspend = rt5645_suspend,
2625 .resume = rt5645_resume,
2626 .set_bias_level = rt5645_set_bias_level,
2627 .idle_bias_off = true,
2628 .controls = rt5645_snd_controls,
2629 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
2630 .dapm_widgets = rt5645_dapm_widgets,
2631 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
2632 .dapm_routes = rt5645_dapm_routes,
2633 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
2634};
2635
2636static const struct regmap_config rt5645_regmap = {
2637 .reg_bits = 8,
2638 .val_bits = 16,
afefc128 2639 .use_single_rw = true,
1319b2f6
OC		 2640 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
2641 RT5645_PR_SPACING),
2642 .volatile_reg = rt5645_volatile_register,
2643 .readable_reg = rt5645_readable_register,
2644
2645 .cache_type = REGCACHE_RBTREE,
2646 .reg_defaults = rt5645_reg,
2647 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
2648 .ranges = rt5645_ranges,
2649 .num_ranges = ARRAY_SIZE(rt5645_ranges),
2650};
2651
2652static const struct i2c_device_id rt5645_i2c_id[] = {
2653 { "rt5645", 0 },
5c4ca99d 2654 { "rt5650", 0 },
1319b2f6
OC		 2655 { }
2656};
2657MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
2658
2659static int rt5645_i2c_probe(struct i2c_client *i2c,
2660 const struct i2c_device_id *id)
2661{
2662 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
2663 struct rt5645_priv *rt5645;
2664 int ret;
2665 unsigned int val;
2666
2667 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
2668 GFP_KERNEL);
2669 if (rt5645 == NULL)
2670 return -ENOMEM;
2671
f3fa1bbd 2672 rt5645->i2c = i2c;
1319b2f6
OC		 2673 i2c_set_clientdata(i2c, rt5645);
2674
2675 if (pdata)
2676 rt5645->pdata = *pdata;
2677
2678 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
2679 if (IS_ERR(rt5645->regmap)) {
2680 ret = PTR_ERR(rt5645->regmap);
2681 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2682 ret);
2683 return ret;
2684 }
2685
2686 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
5c4ca99d
BL		 2687
2688 switch (val) {
2689 case RT5645_DEVICE_ID:
2690 rt5645->codec_type = CODEC_TYPE_RT5645;
2691 break;
2692 case RT5650_DEVICE_ID:
2693 rt5645->codec_type = CODEC_TYPE_RT5650;
2694 break;
2695 default:
1319b2f6 2696 dev_err(&i2c->dev,
5c4ca99d
BL		 2697 "Device with ID register %x is not rt5645 or rt5650\n",
2698 val);
1319b2f6
OC		 2699 return -ENODEV;
2700 }
2701
2702 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2703
2704 ret = regmap_register_patch(rt5645->regmap, init_list,
2705 ARRAY_SIZE(init_list));
2706 if (ret != 0)
2707 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2708
5c4ca99d
BL		 2709 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
2710 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
2711 ARRAY_SIZE(rt5650_init_list));
2712 if (ret != 0)
2713 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
2714 ret);
2715 }
2716
1319b2f6
OC		 2717 if (rt5645->pdata.in2_diff)
2718 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
2719 RT5645_IN_DF2, RT5645_IN_DF2);
2720
2721 if (rt5645->pdata.dmic_en) {
2722 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2723 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
2724
2725 switch (rt5645->pdata.dmic1_data_pin) {
2726 case RT5645_DMIC_DATA_IN2N:
2727 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2728 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
2729 break;
2730
2731 case RT5645_DMIC_DATA_GPIO5:
2732 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2733 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2734 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2735 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2736 break;
2737
2738 case RT5645_DMIC_DATA_GPIO11:
2739 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2740 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
2741 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2742 RT5645_GP11_PIN_MASK,
2743 RT5645_GP11_PIN_DMIC1_SDA);
2744 break;
2745
2746 default:
2747 break;
2748 }
2749
2750 switch (rt5645->pdata.dmic2_data_pin) {
2751 case RT5645_DMIC_DATA_IN2P:
2752 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2753 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2754 break;
2755
2756 case RT5645_DMIC_DATA_GPIO6:
2757 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2758 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
2759 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2760 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
2761 break;
2762
2763 case RT5645_DMIC_DATA_GPIO10:
2764 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2765 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
2766 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2767 RT5645_GP10_PIN_MASK,
2768 RT5645_GP10_PIN_DMIC2_SDA);
2769 break;
2770
2771 case RT5645_DMIC_DATA_GPIO12:
2772 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2773 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
2774 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2775 RT5645_GP12_PIN_MASK,
2776 RT5645_GP12_PIN_DMIC2_SDA);
2777 break;
2778
2779 default:
2780 break;
2781 }
2782
2783 }
2784
bb656add
BL		 2785 if (rt5645->pdata.en_jd_func) {
2786 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2787 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU,
2788 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU);
2789 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
2790 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
2791 regmap_update_bits(rt5645->regmap, RT5645_JD_CTRL3,
2792 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL,
2793 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL);
2794 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2795 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2796 }
2797
2d4e2d02
BL		 2798 if (rt5645->pdata.jd_mode) {
2799 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
2800 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
2801 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2802 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
2803 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
2804 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
2805 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2806 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
2807 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2808 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2809 switch (rt5645->pdata.jd_mode) {
2810 case 1:
2811 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2812 RT5645_JD1_MODE_MASK,
2813 RT5645_JD1_MODE_0);
2814 break;
2815 case 2:
2816 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2817 RT5645_JD1_MODE_MASK,
2818 RT5645_JD1_MODE_1);
2819 break;
2820 case 3:
2821 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2822 RT5645_JD1_MODE_MASK,
2823 RT5645_JD1_MODE_2);
2824 break;
2825 default:
2826 break;
2827 }
2828 }
2829
f3fa1bbd
OC		 2830 if (rt5645->i2c->irq) {
2831 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
2832 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2833 | IRQF_ONESHOT, "rt5645", rt5645);
2834 if (ret)
2835 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2836 }
2837
2838 if (gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2839 ret = gpio_request(rt5645->pdata.hp_det_gpio, "rt5645");
2840 if (ret)
2841 dev_err(&i2c->dev, "Fail gpio_request hp_det_gpio\n");
2842
2843 ret = gpio_direction_input(rt5645->pdata.hp_det_gpio);
2844 if (ret)
2845 dev_err(&i2c->dev, "Fail gpio_direction hp_det_gpio\n");
2846 }
2847
cd6e82b8
OC		 2848 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
2849
dd56ebad
AL		 2850 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
2851 rt5645_dai, ARRAY_SIZE(rt5645_dai));
1319b2f6
OC		 2852}
2853
2854static int rt5645_i2c_remove(struct i2c_client *i2c)
2855{
f3fa1bbd
OC		 2856 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
2857
2858 if (i2c->irq)
2859 free_irq(i2c->irq, rt5645);
2860
cd6e82b8
OC		 2861 cancel_delayed_work_sync(&rt5645->jack_detect_work);
2862
f3fa1bbd
OC		 2863 if (gpio_is_valid(rt5645->pdata.hp_det_gpio))
2864 gpio_free(rt5645->pdata.hp_det_gpio);
2865
1319b2f6
OC		 2866 snd_soc_unregister_codec(&i2c->dev);
2867
2868 return 0;
2869}
2870
9e22f782 2871static struct i2c_driver rt5645_i2c_driver = {
1319b2f6
OC		 2872 .driver = {
2873 .name = "rt5645",
2874 .owner = THIS_MODULE,
2875 },
2876 .probe = rt5645_i2c_probe,
2877 .remove = rt5645_i2c_remove,
2878 .id_table = rt5645_i2c_id,
2879};
2880module_i2c_driver(rt5645_i2c_driver);
2881
2882MODULE_DESCRIPTION("ASoC RT5645 driver");
2883MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2884MODULE_LICENSE("GPL v2");
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