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ASoC: rt5651: Enable LDO and micbias1 supplies for jack-type detection
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / rt5651.c
CommitLineData
40bc18a2
BL		 1/*
2 * rt5651.c -- RT5651 ALSA SoC audio codec driver
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
3ae08dc0 21#include <linux/acpi.h>
b4435130 22#include <linux/dmi.h>
40bc18a2
BL		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
80bbe4a3 30#include <sound/jack.h>
40bc18a2 31
49ef7925 32#include "rl6231.h"
40bc18a2
BL		 33#include "rt5651.h"
34
b4435130 35#define RT5651_JD_MAP(quirk) ((quirk) & GENMASK(7, 0))
b4435130 36
40bc18a2
BL		 37#define RT5651_DEVICE_ID_VALUE 0x6281
38
39#define RT5651_PR_RANGE_BASE (0xff + 1)
40#define RT5651_PR_SPACING 0x100
41
42#define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
43
b4435130
CC		 44static unsigned long rt5651_quirk;
45
40bc18a2
BL		 46static const struct regmap_range_cfg rt5651_ranges[] = {
47 { .name = "PR", .range_min = RT5651_PR_BASE,
48 .range_max = RT5651_PR_BASE + 0xb4,
49 .selector_reg = RT5651_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5651_PRIV_DATA,
53 .window_len = 0x1, },
54};
55
41a5fefe 56static const struct reg_sequence init_list[] = {
40bc18a2
BL		 57 {RT5651_PR_BASE + 0x3d, 0x3e00},
58};
59
60static const struct reg_default rt5651_reg[] = {
61 { 0x00, 0x0000 },
62 { 0x02, 0xc8c8 },
63 { 0x03, 0xc8c8 },
64 { 0x05, 0x0000 },
65 { 0x0d, 0x0000 },
66 { 0x0e, 0x0000 },
67 { 0x0f, 0x0808 },
68 { 0x10, 0x0808 },
69 { 0x19, 0xafaf },
70 { 0x1a, 0xafaf },
71 { 0x1b, 0x0c00 },
72 { 0x1c, 0x2f2f },
73 { 0x1d, 0x2f2f },
74 { 0x1e, 0x0000 },
75 { 0x27, 0x7860 },
76 { 0x28, 0x7070 },
77 { 0x29, 0x8080 },
78 { 0x2a, 0x5252 },
79 { 0x2b, 0x5454 },
80 { 0x2f, 0x0000 },
81 { 0x30, 0x5000 },
82 { 0x3b, 0x0000 },
83 { 0x3c, 0x006f },
84 { 0x3d, 0x0000 },
85 { 0x3e, 0x006f },
86 { 0x45, 0x6000 },
87 { 0x4d, 0x0000 },
88 { 0x4e, 0x0000 },
89 { 0x4f, 0x0279 },
90 { 0x50, 0x0000 },
91 { 0x51, 0x0000 },
92 { 0x52, 0x0279 },
93 { 0x53, 0xf000 },
94 { 0x61, 0x0000 },
95 { 0x62, 0x0000 },
96 { 0x63, 0x00c0 },
97 { 0x64, 0x0000 },
98 { 0x65, 0x0000 },
99 { 0x66, 0x0000 },
100 { 0x70, 0x8000 },
101 { 0x71, 0x8000 },
102 { 0x73, 0x1104 },
103 { 0x74, 0x0c00 },
104 { 0x75, 0x1400 },
105 { 0x77, 0x0c00 },
106 { 0x78, 0x4000 },
107 { 0x79, 0x0123 },
108 { 0x80, 0x0000 },
109 { 0x81, 0x0000 },
110 { 0x82, 0x0000 },
111 { 0x83, 0x0800 },
112 { 0x84, 0x0000 },
113 { 0x85, 0x0008 },
114 { 0x89, 0x0000 },
115 { 0x8e, 0x0004 },
116 { 0x8f, 0x1100 },
117 { 0x90, 0x0000 },
118 { 0x93, 0x2000 },
119 { 0x94, 0x0200 },
120 { 0xb0, 0x2080 },
121 { 0xb1, 0x0000 },
122 { 0xb4, 0x2206 },
123 { 0xb5, 0x1f00 },
124 { 0xb6, 0x0000 },
125 { 0xbb, 0x0000 },
126 { 0xbc, 0x0000 },
127 { 0xbd, 0x0000 },
128 { 0xbe, 0x0000 },
129 { 0xbf, 0x0000 },
130 { 0xc0, 0x0400 },
131 { 0xc1, 0x0000 },
132 { 0xc2, 0x0000 },
133 { 0xcf, 0x0013 },
134 { 0xd0, 0x0680 },
135 { 0xd1, 0x1c17 },
136 { 0xd3, 0xb320 },
137 { 0xd9, 0x0809 },
138 { 0xfa, 0x0010 },
139 { 0xfe, 0x10ec },
140 { 0xff, 0x6281 },
141};
142
143static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
144{
145 int i;
146
147 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
148 if ((reg >= rt5651_ranges[i].window_start &&
149 reg <= rt5651_ranges[i].window_start +
150 rt5651_ranges[i].window_len) ||
151 (reg >= rt5651_ranges[i].range_min &&
152 reg <= rt5651_ranges[i].range_max)) {
153 return true;
154 }
155 }
156
157 switch (reg) {
158 case RT5651_RESET:
159 case RT5651_PRIV_DATA:
160 case RT5651_EQ_CTRL1:
161 case RT5651_ALC_1:
162 case RT5651_IRQ_CTRL2:
163 case RT5651_INT_IRQ_ST:
164 case RT5651_PGM_REG_ARR1:
165 case RT5651_PGM_REG_ARR3:
166 case RT5651_VENDOR_ID:
167 case RT5651_DEVICE_ID:
168 return true;
169 default:
170 return false;
171 }
172}
173
174static bool rt5651_readable_register(struct device *dev, unsigned int reg)
175{
176 int i;
177
178 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
179 if ((reg >= rt5651_ranges[i].window_start &&
180 reg <= rt5651_ranges[i].window_start +
181 rt5651_ranges[i].window_len) ||
182 (reg >= rt5651_ranges[i].range_min &&
183 reg <= rt5651_ranges[i].range_max)) {
184 return true;
185 }
186 }
187
188 switch (reg) {
189 case RT5651_RESET:
190 case RT5651_VERSION_ID:
191 case RT5651_VENDOR_ID:
192 case RT5651_DEVICE_ID:
193 case RT5651_HP_VOL:
194 case RT5651_LOUT_CTRL1:
195 case RT5651_LOUT_CTRL2:
196 case RT5651_IN1_IN2:
197 case RT5651_IN3:
198 case RT5651_INL1_INR1_VOL:
199 case RT5651_INL2_INR2_VOL:
200 case RT5651_DAC1_DIG_VOL:
201 case RT5651_DAC2_DIG_VOL:
202 case RT5651_DAC2_CTRL:
203 case RT5651_ADC_DIG_VOL:
204 case RT5651_ADC_DATA:
205 case RT5651_ADC_BST_VOL:
206 case RT5651_STO1_ADC_MIXER:
207 case RT5651_STO2_ADC_MIXER:
208 case RT5651_AD_DA_MIXER:
209 case RT5651_STO_DAC_MIXER:
210 case RT5651_DD_MIXER:
211 case RT5651_DIG_INF_DATA:
212 case RT5651_PDM_CTL:
213 case RT5651_REC_L1_MIXER:
214 case RT5651_REC_L2_MIXER:
215 case RT5651_REC_R1_MIXER:
216 case RT5651_REC_R2_MIXER:
217 case RT5651_HPO_MIXER:
218 case RT5651_OUT_L1_MIXER:
219 case RT5651_OUT_L2_MIXER:
220 case RT5651_OUT_L3_MIXER:
221 case RT5651_OUT_R1_MIXER:
222 case RT5651_OUT_R2_MIXER:
223 case RT5651_OUT_R3_MIXER:
224 case RT5651_LOUT_MIXER:
225 case RT5651_PWR_DIG1:
226 case RT5651_PWR_DIG2:
227 case RT5651_PWR_ANLG1:
228 case RT5651_PWR_ANLG2:
229 case RT5651_PWR_MIXER:
230 case RT5651_PWR_VOL:
231 case RT5651_PRIV_INDEX:
232 case RT5651_PRIV_DATA:
233 case RT5651_I2S1_SDP:
234 case RT5651_I2S2_SDP:
235 case RT5651_ADDA_CLK1:
236 case RT5651_ADDA_CLK2:
237 case RT5651_DMIC:
238 case RT5651_TDM_CTL_1:
239 case RT5651_TDM_CTL_2:
240 case RT5651_TDM_CTL_3:
241 case RT5651_GLB_CLK:
242 case RT5651_PLL_CTRL1:
243 case RT5651_PLL_CTRL2:
244 case RT5651_PLL_MODE_1:
245 case RT5651_PLL_MODE_2:
246 case RT5651_PLL_MODE_3:
247 case RT5651_PLL_MODE_4:
248 case RT5651_PLL_MODE_5:
249 case RT5651_PLL_MODE_6:
250 case RT5651_PLL_MODE_7:
251 case RT5651_DEPOP_M1:
252 case RT5651_DEPOP_M2:
253 case RT5651_DEPOP_M3:
254 case RT5651_CHARGE_PUMP:
255 case RT5651_MICBIAS:
256 case RT5651_A_JD_CTL1:
257 case RT5651_EQ_CTRL1:
258 case RT5651_EQ_CTRL2:
259 case RT5651_ALC_1:
260 case RT5651_ALC_2:
261 case RT5651_ALC_3:
262 case RT5651_JD_CTRL1:
263 case RT5651_JD_CTRL2:
264 case RT5651_IRQ_CTRL1:
265 case RT5651_IRQ_CTRL2:
266 case RT5651_INT_IRQ_ST:
267 case RT5651_GPIO_CTRL1:
268 case RT5651_GPIO_CTRL2:
269 case RT5651_GPIO_CTRL3:
270 case RT5651_PGM_REG_ARR1:
271 case RT5651_PGM_REG_ARR2:
272 case RT5651_PGM_REG_ARR3:
273 case RT5651_PGM_REG_ARR4:
274 case RT5651_PGM_REG_ARR5:
275 case RT5651_SCB_FUNC:
276 case RT5651_SCB_CTRL:
277 case RT5651_BASE_BACK:
278 case RT5651_MP3_PLUS1:
279 case RT5651_MP3_PLUS2:
280 case RT5651_ADJ_HPF_CTRL1:
281 case RT5651_ADJ_HPF_CTRL2:
282 case RT5651_HP_CALIB_AMP_DET:
283 case RT5651_HP_CALIB2:
284 case RT5651_SV_ZCD1:
285 case RT5651_SV_ZCD2:
286 case RT5651_D_MISC:
287 case RT5651_DUMMY2:
288 case RT5651_DUMMY3:
289 return true;
290 default:
291 return false;
292 }
293}
294
295static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
296static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
297static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
298static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
299static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
300
301/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
8e3648e1 302static const DECLARE_TLV_DB_RANGE(bst_tlv,
40bc18a2
BL		 303 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
304 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
305 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
306 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
307 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
308 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8e3648e1
LPC		 309 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
310);
40bc18a2
BL		 311
312/* Interface data select */
313static const char * const rt5651_data_select[] = {
314 "Normal", "Swap", "left copy to right", "right copy to left"};
315
316static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
317 RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
318
319static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
320 RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
321
322static const struct snd_kcontrol_new rt5651_snd_controls[] = {
323 /* Headphone Output Volume */
324 SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
325 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
326 /* OUTPUT Control */
327 SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
328 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
329
330 /* DAC Digital Volume */
331 SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
332 RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
333 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
334 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
335 175, 0, dac_vol_tlv),
336 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
337 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
338 175, 0, dac_vol_tlv),
339 /* IN1/IN2 Control */
340 SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
341 RT5651_BST_SFT1, 8, 0, bst_tlv),
342 SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
343 RT5651_BST_SFT2, 8, 0, bst_tlv),
344 /* INL/INR Volume Control */
345 SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
346 RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
347 31, 1, in_vol_tlv),
348 /* ADC Digital Volume Control */
349 SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
350 RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
351 SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
352 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
353 127, 0, adc_vol_tlv),
354 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
355 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
356 127, 0, adc_vol_tlv),
357 /* ADC Boost Volume Control */
358 SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
359 RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
360 3, 0, adc_bst_tlv),
361
362 /* ASRC */
363 SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
364 RT5651_STO1_T_SFT, 1, 0),
365 SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
366 RT5651_STO2_T_SFT, 1, 0),
367 SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
368 RT5651_DMIC_1_M_SFT, 1, 0),
369
370 SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
371 SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
372};
373
374/**
375 * set_dmic_clk - Set parameter of dmic.
376 *
377 * @w: DAPM widget.
378 * @kcontrol: The kcontrol of this widget.
379 * @event: Event id.
380 *
40bc18a2
BL		 381 */
382static int set_dmic_clk(struct snd_soc_dapm_widget *w,
383 struct snd_kcontrol *kcontrol, int event)
384{
17b52010
KM		 385 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
386 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
00a6d6e5 387 int idx, rate;
40bc18a2 388
00a6d6e5
OC		 389 rate = rt5651->sysclk / rl6231_get_pre_div(rt5651->regmap,
390 RT5651_ADDA_CLK1, RT5651_I2S_PD1_SFT);
391 idx = rl6231_calc_dmic_clk(rate);
40bc18a2 392 if (idx < 0)
17b52010 393 dev_err(component->dev, "Failed to set DMIC clock\n");
40bc18a2 394 else
17b52010 395 snd_soc_component_update_bits(component, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
40bc18a2
BL		 396 idx << RT5651_DMIC_CLK_SFT);
397
398 return idx;
399}
400
40bc18a2
BL		 401/* Digital Mixer */
402static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
403 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
404 RT5651_M_STO1_ADC_L1_SFT, 1, 1),
405 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
406 RT5651_M_STO1_ADC_L2_SFT, 1, 1),
407};
408
409static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
410 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
411 RT5651_M_STO1_ADC_R1_SFT, 1, 1),
412 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
413 RT5651_M_STO1_ADC_R2_SFT, 1, 1),
414};
415
416static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
417 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
418 RT5651_M_STO2_ADC_L1_SFT, 1, 1),
419 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
420 RT5651_M_STO2_ADC_L2_SFT, 1, 1),
421};
422
423static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
424 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
425 RT5651_M_STO2_ADC_R1_SFT, 1, 1),
426 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
427 RT5651_M_STO2_ADC_R2_SFT, 1, 1),
428};
429
430static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
431 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
432 RT5651_M_ADCMIX_L_SFT, 1, 1),
433 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
434 RT5651_M_IF1_DAC_L_SFT, 1, 1),
435};
436
437static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
438 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
439 RT5651_M_ADCMIX_R_SFT, 1, 1),
440 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
441 RT5651_M_IF1_DAC_R_SFT, 1, 1),
442};
443
444static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
445 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
446 RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
447 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
448 RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
449 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
450 RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
451};
452
453static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
454 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
455 RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
456 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
457 RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
458 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
459 RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
460};
461
462static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
463 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
464 RT5651_M_STO_DD_L1_SFT, 1, 1),
465 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
466 RT5651_M_STO_DD_L2_SFT, 1, 1),
467 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
468 RT5651_M_STO_DD_R2_L_SFT, 1, 1),
469};
470
471static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
472 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
473 RT5651_M_STO_DD_R1_SFT, 1, 1),
474 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
475 RT5651_M_STO_DD_R2_SFT, 1, 1),
476 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
477 RT5651_M_STO_DD_L2_R_SFT, 1, 1),
478};
479
480/* Analog Input Mixer */
481static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
482 SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
483 RT5651_M_IN1_L_RM_L_SFT, 1, 1),
484 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
485 RT5651_M_BST3_RM_L_SFT, 1, 1),
486 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
487 RT5651_M_BST2_RM_L_SFT, 1, 1),
488 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
489 RT5651_M_BST1_RM_L_SFT, 1, 1),
490};
491
492static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
493 SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
494 RT5651_M_IN1_R_RM_R_SFT, 1, 1),
495 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
496 RT5651_M_BST3_RM_R_SFT, 1, 1),
497 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
498 RT5651_M_BST2_RM_R_SFT, 1, 1),
499 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
500 RT5651_M_BST1_RM_R_SFT, 1, 1),
501};
502
503/* Analog Output Mixer */
504
505static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
506 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
507 RT5651_M_BST1_OM_L_SFT, 1, 1),
508 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
509 RT5651_M_BST2_OM_L_SFT, 1, 1),
510 SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
511 RT5651_M_IN1_L_OM_L_SFT, 1, 1),
512 SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
513 RT5651_M_RM_L_OM_L_SFT, 1, 1),
514 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
515 RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
516};
517
518static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
519 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
520 RT5651_M_BST2_OM_R_SFT, 1, 1),
521 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
522 RT5651_M_BST1_OM_R_SFT, 1, 1),
523 SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
524 RT5651_M_IN1_R_OM_R_SFT, 1, 1),
525 SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
526 RT5651_M_RM_R_OM_R_SFT, 1, 1),
527 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
528 RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
529};
530
531static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
532 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
533 RT5651_M_DAC1_HM_SFT, 1, 1),
534 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
535 RT5651_M_HPVOL_HM_SFT, 1, 1),
536};
537
538static const struct snd_kcontrol_new rt5651_lout_mix[] = {
539 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
540 RT5651_M_DAC_L1_LM_SFT, 1, 1),
541 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
542 RT5651_M_DAC_R1_LM_SFT, 1, 1),
543 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
544 RT5651_M_OV_L_LM_SFT, 1, 1),
545 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
546 RT5651_M_OV_R_LM_SFT, 1, 1),
547};
548
549static const struct snd_kcontrol_new outvol_l_control =
550 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
551 RT5651_VOL_L_SFT, 1, 1);
552
553static const struct snd_kcontrol_new outvol_r_control =
554 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
555 RT5651_VOL_R_SFT, 1, 1);
556
557static const struct snd_kcontrol_new lout_l_mute_control =
558 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
559 RT5651_L_MUTE_SFT, 1, 1);
560
561static const struct snd_kcontrol_new lout_r_mute_control =
562 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
563 RT5651_R_MUTE_SFT, 1, 1);
564
565static const struct snd_kcontrol_new hpovol_l_control =
566 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
567 RT5651_VOL_L_SFT, 1, 1);
568
569static const struct snd_kcontrol_new hpovol_r_control =
570 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
571 RT5651_VOL_R_SFT, 1, 1);
572
573static const struct snd_kcontrol_new hpo_l_mute_control =
574 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
575 RT5651_L_MUTE_SFT, 1, 1);
576
577static const struct snd_kcontrol_new hpo_r_mute_control =
578 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
579 RT5651_R_MUTE_SFT, 1, 1);
580
40bc18a2
BL		 581/* Stereo ADC source */
582static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
583
584static SOC_ENUM_SINGLE_DECL(
585 rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
586 RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
587
588static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
589 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
590
591static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
592 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
593
594static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
595
596static SOC_ENUM_SINGLE_DECL(
597 rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
598 RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
599
600static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
601 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
602
603static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
604 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
605
606/* Mono ADC source */
607static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
608
609static SOC_ENUM_SINGLE_DECL(
610 rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
611 RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
612
613static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
614 SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
615
616static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
617
618static SOC_ENUM_SINGLE_DECL(
619 rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
620 RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
621
622static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
623 SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
624
625static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
626
627static SOC_ENUM_SINGLE_DECL(
628 rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
629 RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
630
631static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
632 SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
633
634static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
635
636static SOC_ENUM_SINGLE_DECL(
637 rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
638 RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
639
640static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
641 SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
642
643/* DAC2 channel source */
644
645static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
646
647static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
648 RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
649
650static const struct snd_kcontrol_new rt5651_dac_l2_mux =
651 SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
652
653static SOC_ENUM_SINGLE_DECL(
654 rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
655 RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
656
657static const struct snd_kcontrol_new rt5651_dac_r2_mux =
658 SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
659
660/* IF2_ADC channel source */
661
662static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
663
664static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
665 RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
666
667static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
668 SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
669
670/* PDM select */
671static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
672
673static SOC_ENUM_SINGLE_DECL(
674 rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
675 RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
676
677static SOC_ENUM_SINGLE_DECL(
678 rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
679 RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
680
681static const struct snd_kcontrol_new rt5651_pdm_l_mux =
682 SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
683
684static const struct snd_kcontrol_new rt5651_pdm_r_mux =
685 SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
686
687static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
688 struct snd_kcontrol *kcontrol, int event)
689{
17b52010
KM		 690 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
691 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
40bc18a2
BL		 692
693 switch (event) {
694 case SND_SOC_DAPM_POST_PMU:
695 /* depop parameters */
696 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
697 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
698 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
699 RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
700 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
701 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
702 RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
703 RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
704 regmap_write(rt5651->regmap, RT5651_PR_BASE +
705 RT5651_HP_DCC_INT1, 0x9f00);
706 /* headphone amp power on */
707 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
708 RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
709 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
710 RT5651_PWR_HA,
711 RT5651_PWR_HA);
712 usleep_range(10000, 15000);
713 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
714 RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
715 RT5651_PWR_FV1 | RT5651_PWR_FV2);
716 break;
717
718 default:
719 return 0;
720 }
721
722 return 0;
723}
724
725static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
726 struct snd_kcontrol *kcontrol, int event)
727{
17b52010
KM		 728 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
729 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
40bc18a2
BL		 730
731 switch (event) {
732 case SND_SOC_DAPM_POST_PMU:
733 /* headphone unmute sequence */
734 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
735 RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
736 RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
737 regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
738 RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
739
740 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
741 RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
742 RT5651_CP_FQ3_MASK,
743 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
744 (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
745 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
746
747 regmap_write(rt5651->regmap, RT5651_PR_BASE +
748 RT5651_MAMP_INT_REG2, 0x1c00);
749 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
750 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
751 RT5651_HP_CP_PD | RT5651_HP_SG_EN);
752 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
753 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
754 rt5651->hp_mute = 0;
755 break;
756
757 case SND_SOC_DAPM_PRE_PMD:
758 rt5651->hp_mute = 1;
759 usleep_range(70000, 75000);
760 break;
761
762 default:
763 return 0;
764 }
765
766 return 0;
767}
768
769static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
770 struct snd_kcontrol *kcontrol, int event)
771{
30c173ed 772
17b52010
KM		 773 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
774 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
40bc18a2
BL		 775
776 switch (event) {
777 case SND_SOC_DAPM_POST_PMU:
778 if (!rt5651->hp_mute)
779 usleep_range(80000, 85000);
780
781 break;
782
783 default:
784 return 0;
785 }
786
787 return 0;
788}
789
790static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
791 struct snd_kcontrol *kcontrol, int event)
792{
17b52010 793 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
40bc18a2
BL		 794
795 switch (event) {
796 case SND_SOC_DAPM_POST_PMU:
17b52010 797 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
40bc18a2
BL		 798 RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
799 break;
800
801 case SND_SOC_DAPM_PRE_PMD:
17b52010 802 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
40bc18a2
BL		 803 RT5651_PWR_BST1_OP2, 0);
804 break;
805
806 default:
807 return 0;
808 }
809
810 return 0;
811}
812
813static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
814 struct snd_kcontrol *kcontrol, int event)
815{
17b52010 816 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
40bc18a2
BL		 817
818 switch (event) {
819 case SND_SOC_DAPM_POST_PMU:
17b52010 820 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
40bc18a2
BL		 821 RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
822 break;
823
824 case SND_SOC_DAPM_PRE_PMD:
17b52010 825 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
40bc18a2
BL		 826 RT5651_PWR_BST2_OP2, 0);
827 break;
828
829 default:
830 return 0;
831 }
832
833 return 0;
834}
835
836static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
837 struct snd_kcontrol *kcontrol, int event)
838{
17b52010 839 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
40bc18a2
BL		 840
841 switch (event) {
842 case SND_SOC_DAPM_POST_PMU:
17b52010 843 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
40bc18a2
BL		 844 RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
845 break;
846
847 case SND_SOC_DAPM_PRE_PMD:
17b52010 848 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
40bc18a2
BL		 849 RT5651_PWR_BST3_OP2, 0);
850 break;
851
852 default:
853 return 0;
854 }
855
856 return 0;
857}
858
859static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
860 /* ASRC */
861 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
862 15, 0, NULL, 0),
863 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
864 14, 0, NULL, 0),
865 SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
866 13, 0, NULL, 0),
867 SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
868 12, 0, NULL, 0),
869 SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
870 11, 0, NULL, 0),
871
40bc18a2
BL		 872 /* micbias */
873 SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
874 RT5651_PWR_LDO_BIT, 0, NULL, 0),
be96fc54
CC		 875 SND_SOC_DAPM_SUPPLY("micbias1", RT5651_PWR_ANLG2,
876 RT5651_PWR_MB1_BIT, 0, NULL, 0),
40bc18a2
BL		 877 /* Input Lines */
878 SND_SOC_DAPM_INPUT("MIC1"),
879 SND_SOC_DAPM_INPUT("MIC2"),
880 SND_SOC_DAPM_INPUT("MIC3"),
881
882 SND_SOC_DAPM_INPUT("IN1P"),
883 SND_SOC_DAPM_INPUT("IN2P"),
884 SND_SOC_DAPM_INPUT("IN2N"),
885 SND_SOC_DAPM_INPUT("IN3P"),
886 SND_SOC_DAPM_INPUT("DMIC L1"),
887 SND_SOC_DAPM_INPUT("DMIC R1"),
888 SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
889 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
890 /* Boost */
891 SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
892 RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
893 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
894 SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
895 RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
896 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
897 SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
898 RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
899 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
900 /* Input Volume */
901 SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
902 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
903 SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
904 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
905 SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
906 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
907 SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
908 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
5800b697 909
40bc18a2
BL		 910 /* REC Mixer */
911 SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
912 rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
913 SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
914 rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
915 /* ADCs */
916 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
917 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
918 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
919 RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
920 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
921 RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
922 /* ADC Mux */
923 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
924 &rt5651_sto1_adc_l2_mux),
925 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
926 &rt5651_sto1_adc_r2_mux),
927 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
928 &rt5651_sto1_adc_l1_mux),
929 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
930 &rt5651_sto1_adc_r1_mux),
931 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
932 &rt5651_sto2_adc_l2_mux),
933 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
934 &rt5651_sto2_adc_l1_mux),
935 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
936 &rt5651_sto2_adc_r1_mux),
937 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
938 &rt5651_sto2_adc_r2_mux),
939 /* ADC Mixer */
940 SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
941 RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
942 SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
943 RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
944 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
945 rt5651_sto1_adc_l_mix,
946 ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
947 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
948 rt5651_sto1_adc_r_mix,
949 ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
950 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
951 rt5651_sto2_adc_l_mix,
952 ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
953 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
954 rt5651_sto2_adc_r_mix,
955 ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
956
957 /* Digital Interface */
958 SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
959 RT5651_PWR_I2S1_BIT, 0, NULL, 0),
960 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
961 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
962 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
963 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
964 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
965 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
966 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
967 SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
968 RT5651_PWR_I2S2_BIT, 0, NULL, 0),
969 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
970 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
971 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
972 SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
973 &rt5651_if2_adc_src_mux),
974
975 /* Digital Interface Select */
976
977 SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
978 RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
979 SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
980 RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
981 /* Audio Interface */
982 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
983 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
984 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
985 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
986
987 /* Audio DSP */
988 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
989
990 /* Output Side */
991 /* DAC mixer before sound effect */
992 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
993 rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
994 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
995 rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
996
997 /* DAC2 channel Mux */
998 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
999 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
1000 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1001 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1002
1003 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
1004 RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
1005 SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
1006 RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
1007 /* DAC Mixer */
1008 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1009 rt5651_sto_dac_l_mix,
1010 ARRAY_SIZE(rt5651_sto_dac_l_mix)),
1011 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1012 rt5651_sto_dac_r_mix,
1013 ARRAY_SIZE(rt5651_sto_dac_r_mix)),
1014 SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
1015 rt5651_dd_dac_l_mix,
1016 ARRAY_SIZE(rt5651_dd_dac_l_mix)),
1017 SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
1018 rt5651_dd_dac_r_mix,
1019 ARRAY_SIZE(rt5651_dd_dac_r_mix)),
1020
1021 /* DACs */
1022 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1023 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1024 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
1025 RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
1026 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
1027 RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
1028 /* OUT Mixer */
1029 SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
1030 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
1031 SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
1032 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
1033 /* Ouput Volume */
1034 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
1035 RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
1036 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
1037 RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
1038 SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
1039 RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
1040 SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
1041 RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
1042 SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
1043 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
1044 SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
1045 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
1046 SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
1047 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
1048 SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
1049 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
1050 /* HPO/LOUT/Mono Mixer */
1051 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1052 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1053 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1054 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1055 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
1056 RT5651_PWR_HP_L_BIT, 0, NULL, 0),
1057 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
1058 RT5651_PWR_HP_R_BIT, 0, NULL, 0),
1059 SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
1060 rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
1061
1062 SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
1063 RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
1064 SND_SOC_DAPM_POST_PMU),
1065 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
1066 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1067 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
1068 &hpo_l_mute_control),
1069 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
1070 &hpo_r_mute_control),
1071 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1072 &lout_l_mute_control),
1073 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1074 &lout_r_mute_control),
1075 SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
1076
1077 /* Output Lines */
1078 SND_SOC_DAPM_OUTPUT("HPOL"),
1079 SND_SOC_DAPM_OUTPUT("HPOR"),
1080 SND_SOC_DAPM_OUTPUT("LOUTL"),
1081 SND_SOC_DAPM_OUTPUT("LOUTR"),
1082 SND_SOC_DAPM_OUTPUT("PDML"),
1083 SND_SOC_DAPM_OUTPUT("PDMR"),
1084};
1085
1086static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
1087 {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
1088 {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
1089 {"I2S1", NULL, "I2S1 ASRC"},
1090 {"I2S2", NULL, "I2S2 ASRC"},
1091
1092 {"IN1P", NULL, "LDO"},
1093 {"IN2P", NULL, "LDO"},
1094 {"IN3P", NULL, "LDO"},
1095
1096 {"IN1P", NULL, "MIC1"},
1097 {"IN2P", NULL, "MIC2"},
1098 {"IN2N", NULL, "MIC2"},
1099 {"IN3P", NULL, "MIC3"},
1100
1101 {"BST1", NULL, "IN1P"},
1102 {"BST2", NULL, "IN2P"},
1103 {"BST2", NULL, "IN2N"},
1104 {"BST3", NULL, "IN3P"},
1105
1106 {"INL1 VOL", NULL, "IN2P"},
1107 {"INR1 VOL", NULL, "IN2N"},
1108
1109 {"RECMIXL", "INL1 Switch", "INL1 VOL"},
1110 {"RECMIXL", "BST3 Switch", "BST3"},
1111 {"RECMIXL", "BST2 Switch", "BST2"},
1112 {"RECMIXL", "BST1 Switch", "BST1"},
1113
1114 {"RECMIXR", "INR1 Switch", "INR1 VOL"},
1115 {"RECMIXR", "BST3 Switch", "BST3"},
1116 {"RECMIXR", "BST2 Switch", "BST2"},
1117 {"RECMIXR", "BST1 Switch", "BST1"},
1118
1119 {"ADC L", NULL, "RECMIXL"},
1120 {"ADC L", NULL, "ADC L Power"},
1121 {"ADC R", NULL, "RECMIXR"},
1122 {"ADC R", NULL, "ADC R Power"},
1123
1124 {"DMIC L1", NULL, "DMIC CLK"},
1125 {"DMIC R1", NULL, "DMIC CLK"},
1126
1127 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1128 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
1129 {"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
1130 {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
1131
1132 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
1133 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
1134 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1135 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
1136
1137 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
1138 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
1139 {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
1140 {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
1141
1142 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
1143 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
1144 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1145 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
1146
1147 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1148 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1149 {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
40bc18a2
BL		 1150 {"Stereo1 Filter", NULL, "ADC ASRC"},
1151
1152 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1153 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1154 {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
1155
1156 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
1157 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
1158 {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
40bc18a2
BL		 1159 {"Stereo2 Filter", NULL, "ADC ASRC"},
1160
1161 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
1162 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
1163 {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
1164
1165 {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
1166 {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
1167 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
1168 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
1169
1170 {"IF1 ADC1", NULL, "I2S1"},
1171
1172 {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
1173 {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
1174 {"IF2 ADC", NULL, "I2S2"},
1175
1176 {"AIF1TX", NULL, "IF1 ADC1"},
1177 {"AIF1TX", NULL, "IF1 ADC2"},
1178 {"AIF2TX", NULL, "IF2 ADC"},
1179
1180 {"IF1 DAC", NULL, "AIF1RX"},
1181 {"IF1 DAC", NULL, "I2S1"},
1182 {"IF2 DAC", NULL, "AIF2RX"},
1183 {"IF2 DAC", NULL, "I2S2"},
1184
1185 {"IF1 DAC1 L", NULL, "IF1 DAC"},
1186 {"IF1 DAC1 R", NULL, "IF1 DAC"},
1187 {"IF1 DAC2 L", NULL, "IF1 DAC"},
1188 {"IF1 DAC2 R", NULL, "IF1 DAC"},
1189 {"IF2 DAC L", NULL, "IF2 DAC"},
1190 {"IF2 DAC R", NULL, "IF2 DAC"},
1191
1192 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1193 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
1194 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1195 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
1196
1197 {"Audio DSP", NULL, "DAC MIXL"},
1198 {"Audio DSP", NULL, "DAC MIXR"},
1199
1200 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
1201 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1202 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
1203
1204 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
1205 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1206 {"DAC R2 Volume", NULL, "DAC R2 Mux"},
1207
1208 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
1209 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1210 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
1211 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
1212 {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
1213 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
1214 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1215 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
1216 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
1217 {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
1218
1219 {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
1220 {"PDM L Mux", "DD MIX", "DAC MIXL"},
1221 {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
1222 {"PDM R Mux", "DD MIX", "DAC MIXR"},
1223
1224 {"DAC L1", NULL, "Stereo DAC MIXL"},
40bc18a2
BL		 1225 {"DAC L1", NULL, "DAC L1 Power"},
1226 {"DAC R1", NULL, "Stereo DAC MIXR"},
40bc18a2
BL		 1227 {"DAC R1", NULL, "DAC R1 Power"},
1228
1229 {"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
1230 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1231 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
1232 {"DD MIXL", NULL, "Stero2 DAC Power"},
1233
1234 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
1235 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1236 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
1237 {"DD MIXR", NULL, "Stero2 DAC Power"},
1238
1239 {"OUT MIXL", "BST1 Switch", "BST1"},
1240 {"OUT MIXL", "BST2 Switch", "BST2"},
1241 {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
1242 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1243 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1244
1245 {"OUT MIXR", "BST2 Switch", "BST2"},
1246 {"OUT MIXR", "BST1 Switch", "BST1"},
1247 {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
1248 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1249 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1250
1251 {"HPOVOL L", "Switch", "OUT MIXL"},
1252 {"HPOVOL R", "Switch", "OUT MIXR"},
1253 {"OUTVOL L", "Switch", "OUT MIXL"},
1254 {"OUTVOL R", "Switch", "OUT MIXR"},
1255
1256 {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
1257 {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
1258 {"HPOL MIX", NULL, "HP L Amp"},
1259 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
1260 {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
1261 {"HPOR MIX", NULL, "HP R Amp"},
1262
1263 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1264 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1265 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1266 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1267
1268 {"HP Amp", NULL, "HPOL MIX"},
1269 {"HP Amp", NULL, "HPOR MIX"},
1270 {"HP Amp", NULL, "Amp Power"},
1271 {"HPO L Playback", "Switch", "HP Amp"},
1272 {"HPO R Playback", "Switch", "HP Amp"},
1273 {"HPOL", NULL, "HPO L Playback"},
1274 {"HPOR", NULL, "HPO R Playback"},
1275
1276 {"LOUT L Playback", "Switch", "LOUT MIX"},
1277 {"LOUT R Playback", "Switch", "LOUT MIX"},
1278 {"LOUTL", NULL, "LOUT L Playback"},
1279 {"LOUTL", NULL, "Amp Power"},
1280 {"LOUTR", NULL, "LOUT R Playback"},
1281 {"LOUTR", NULL, "Amp Power"},
1282
1283 {"PDML", NULL, "PDM L Mux"},
1284 {"PDMR", NULL, "PDM R Mux"},
1285};
1286
40bc18a2
BL		 1287static int rt5651_hw_params(struct snd_pcm_substream *substream,
1288 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1289{
17b52010
KM		 1290 struct snd_soc_component *component = dai->component;
1291 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
40bc18a2
BL		 1292 unsigned int val_len = 0, val_clk, mask_clk;
1293 int pre_div, bclk_ms, frame_size;
1294
1295 rt5651->lrck[dai->id] = params_rate(params);
d92950e7 1296 pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
40bc18a2
BL		 1297
1298 if (pre_div < 0) {
17b52010 1299 dev_err(component->dev, "Unsupported clock setting\n");
40bc18a2
BL		 1300 return -EINVAL;
1301 }
1302 frame_size = snd_soc_params_to_frame_size(params);
1303 if (frame_size < 0) {
17b52010 1304 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
40bc18a2
BL		 1305 return -EINVAL;
1306 }
1307 bclk_ms = frame_size > 32 ? 1 : 0;
1308 rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
1309
1310 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1311 rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
1312 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1313 bclk_ms, pre_div, dai->id);
1314
794f33d2
MB		 1315 switch (params_width(params)) {
1316 case 16:
40bc18a2 1317 break;
794f33d2 1318 case 20:
40bc18a2
BL		 1319 val_len |= RT5651_I2S_DL_20;
1320 break;
794f33d2 1321 case 24:
40bc18a2
BL		 1322 val_len |= RT5651_I2S_DL_24;
1323 break;
794f33d2 1324 case 8:
40bc18a2
BL		 1325 val_len |= RT5651_I2S_DL_8;
1326 break;
1327 default:
1328 return -EINVAL;
1329 }
1330
1331 switch (dai->id) {
1332 case RT5651_AIF1:
1333 mask_clk = RT5651_I2S_PD1_MASK;
1334 val_clk = pre_div << RT5651_I2S_PD1_SFT;
17b52010 1335 snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
40bc18a2 1336 RT5651_I2S_DL_MASK, val_len);
17b52010 1337 snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
40bc18a2
BL		 1338 break;
1339 case RT5651_AIF2:
1340 mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
1341 val_clk = pre_div << RT5651_I2S_PD2_SFT;
17b52010 1342 snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
40bc18a2 1343 RT5651_I2S_DL_MASK, val_len);
17b52010 1344 snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
40bc18a2
BL		 1345 break;
1346 default:
17b52010 1347 dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
40bc18a2
BL		 1348 return -EINVAL;
1349 }
1350
1351 return 0;
1352}
1353
1354static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1355{
17b52010
KM		 1356 struct snd_soc_component *component = dai->component;
1357 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
40bc18a2
BL		 1358 unsigned int reg_val = 0;
1359
1360 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1361 case SND_SOC_DAIFMT_CBM_CFM:
1362 rt5651->master[dai->id] = 1;
1363 break;
1364 case SND_SOC_DAIFMT_CBS_CFS:
1365 reg_val |= RT5651_I2S_MS_S;
1366 rt5651->master[dai->id] = 0;
1367 break;
1368 default:
1369 return -EINVAL;
1370 }
1371
1372 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1373 case SND_SOC_DAIFMT_NB_NF:
1374 break;
1375 case SND_SOC_DAIFMT_IB_NF:
1376 reg_val |= RT5651_I2S_BP_INV;
1377 break;
1378 default:
1379 return -EINVAL;
1380 }
1381
1382 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1383 case SND_SOC_DAIFMT_I2S:
1384 break;
1385 case SND_SOC_DAIFMT_LEFT_J:
1386 reg_val |= RT5651_I2S_DF_LEFT;
1387 break;
1388 case SND_SOC_DAIFMT_DSP_A:
1389 reg_val |= RT5651_I2S_DF_PCM_A;
1390 break;
1391 case SND_SOC_DAIFMT_DSP_B:
1392 reg_val |= RT5651_I2S_DF_PCM_B;
1393 break;
1394 default:
1395 return -EINVAL;
1396 }
1397
1398 switch (dai->id) {
1399 case RT5651_AIF1:
17b52010 1400 snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
40bc18a2
BL		 1401 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1402 RT5651_I2S_DF_MASK, reg_val);
1403 break;
1404 case RT5651_AIF2:
17b52010 1405 snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
40bc18a2
BL		 1406 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1407 RT5651_I2S_DF_MASK, reg_val);
1408 break;
1409 default:
17b52010 1410 dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
40bc18a2
BL		 1411 return -EINVAL;
1412 }
1413 return 0;
1414}
1415
1416static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
1417 int clk_id, unsigned int freq, int dir)
1418{
17b52010
KM		 1419 struct snd_soc_component *component = dai->component;
1420 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
40bc18a2 1421 unsigned int reg_val = 0;
d082174c 1422 unsigned int pll_bit = 0;
40bc18a2
BL		 1423
1424 if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
1425 return 0;
1426
1427 switch (clk_id) {
1428 case RT5651_SCLK_S_MCLK:
1429 reg_val |= RT5651_SCLK_SRC_MCLK;
1430 break;
1431 case RT5651_SCLK_S_PLL1:
1432 reg_val |= RT5651_SCLK_SRC_PLL1;
d082174c 1433 pll_bit |= RT5651_PWR_PLL;
40bc18a2
BL		 1434 break;
1435 case RT5651_SCLK_S_RCCLK:
1436 reg_val |= RT5651_SCLK_SRC_RCCLK;
1437 break;
1438 default:
17b52010 1439 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
40bc18a2
BL		 1440 return -EINVAL;
1441 }
d082174c
HG		 1442 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
1443 RT5651_PWR_PLL, pll_bit);
17b52010 1444 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
40bc18a2
BL		 1445 RT5651_SCLK_SRC_MASK, reg_val);
1446 rt5651->sysclk = freq;
1447 rt5651->sysclk_src = clk_id;
1448
1449 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1450
1451 return 0;
1452}
1453
40bc18a2
BL		 1454static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1455 unsigned int freq_in, unsigned int freq_out)
1456{
17b52010
KM		 1457 struct snd_soc_component *component = dai->component;
1458 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
71c7a2d6 1459 struct rl6231_pll_code pll_code;
40bc18a2
BL		 1460 int ret;
1461
1462 if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
1463 freq_out == rt5651->pll_out)
1464 return 0;
1465
1466 if (!freq_in || !freq_out) {
17b52010 1467 dev_dbg(component->dev, "PLL disabled\n");
40bc18a2
BL		 1468
1469 rt5651->pll_in = 0;
1470 rt5651->pll_out = 0;
17b52010 1471 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
40bc18a2
BL		 1472 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
1473 return 0;
1474 }
1475
1476 switch (source) {
1477 case RT5651_PLL1_S_MCLK:
17b52010 1478 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
40bc18a2
BL		 1479 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
1480 break;
1481 case RT5651_PLL1_S_BCLK1:
17b52010 1482 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
40bc18a2
BL		 1483 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
1484 break;
1485 case RT5651_PLL1_S_BCLK2:
17b52010 1486 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
40bc18a2
BL		 1487 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
1488 break;
1489 default:
17b52010 1490 dev_err(component->dev, "Unknown PLL source %d\n", source);
40bc18a2
BL		 1491 return -EINVAL;
1492 }
1493
71c7a2d6 1494 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
40bc18a2 1495 if (ret < 0) {
17b52010 1496 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
40bc18a2
BL		 1497 return ret;
1498 }
1499
17b52010 1500 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
71c7a2d6
OC		 1501 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1502 pll_code.n_code, pll_code.k_code);
40bc18a2 1503
17b52010 1504 snd_soc_component_write(component, RT5651_PLL_CTRL1,
71c7a2d6 1505 pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
17b52010 1506 snd_soc_component_write(component, RT5651_PLL_CTRL2,
71c7a2d6
OC		 1507 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT |
1508 pll_code.m_bp << RT5651_PLL_M_BP_SFT);
40bc18a2
BL		 1509
1510 rt5651->pll_in = freq_in;
1511 rt5651->pll_out = freq_out;
1512 rt5651->pll_src = source;
1513
1514 return 0;
1515}
1516
17b52010 1517static int rt5651_set_bias_level(struct snd_soc_component *component,
40bc18a2
BL		 1518 enum snd_soc_bias_level level)
1519{
1520 switch (level) {
1521 case SND_SOC_BIAS_PREPARE:
17b52010 1522 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
984c803f
HG		 1523 if (snd_soc_component_read32(component, RT5651_PLL_MODE_1) & 0x9200)
1524 snd_soc_component_update_bits(component, RT5651_D_MISC,
1525 0xc00, 0xc00);
1526 }
1527 break;
1528 case SND_SOC_BIAS_STANDBY:
1529 if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
17b52010 1530 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
40bc18a2
BL		 1531 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1532 RT5651_PWR_BG | RT5651_PWR_VREF2,
1533 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1534 RT5651_PWR_BG | RT5651_PWR_VREF2);
1535 usleep_range(10000, 15000);
17b52010 1536 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
40bc18a2
BL		 1537 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1538 RT5651_PWR_FV1 | RT5651_PWR_FV2);
17b52010 1539 snd_soc_component_update_bits(component, RT5651_D_MISC, 0x1, 0x1);
40bc18a2
BL		 1540 }
1541 break;
1542
984c803f 1543 case SND_SOC_BIAS_OFF:
17b52010
KM		 1544 snd_soc_component_write(component, RT5651_D_MISC, 0x0010);
1545 snd_soc_component_write(component, RT5651_PWR_DIG1, 0x0000);
1546 snd_soc_component_write(component, RT5651_PWR_DIG2, 0x0000);
1547 snd_soc_component_write(component, RT5651_PWR_VOL, 0x0000);
1548 snd_soc_component_write(component, RT5651_PWR_MIXER, 0x0000);
bba4e685
HG		 1549 /* Do not touch the LDO voltage select bits on bias-off */
1550 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
1551 ~RT5651_PWR_LDO_DVO_MASK, 0);
887fcc6f
HG		 1552 /* Leave PLL1 and jack-detect power as is, all others off */
1553 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
1554 ~(RT5651_PWR_PLL | RT5651_PWR_JD_M), 0);
40bc18a2
BL		 1555 break;
1556
1557 default:
1558 break;
1559 }
40bc18a2
BL		 1560
1561 return 0;
1562}
1563
1310e737
HG		 1564static void rt5651_enable_micbias1_for_ovcd(struct snd_soc_component *component)
1565{
1566 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1567
1568 snd_soc_dapm_mutex_lock(dapm);
1569 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO");
1570 snd_soc_dapm_force_enable_pin_unlocked(dapm, "micbias1");
1571 snd_soc_dapm_sync_unlocked(dapm);
1572 snd_soc_dapm_mutex_unlock(dapm);
1573}
1574
1575static void rt5651_disable_micbias1_for_ovcd(struct snd_soc_component *component)
1576{
1577 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1578
1579 snd_soc_dapm_mutex_lock(dapm);
1580 snd_soc_dapm_disable_pin_unlocked(dapm, "micbias1");
1581 snd_soc_dapm_disable_pin_unlocked(dapm, "LDO");
1582 snd_soc_dapm_sync_unlocked(dapm);
1583 snd_soc_dapm_mutex_unlock(dapm);
1584}
1585
d8b8c878
HG		 1586static irqreturn_t rt5651_irq(int irq, void *data)
1587{
1588 struct rt5651_priv *rt5651 = data;
1589
1590 queue_delayed_work(system_power_efficient_wq,
1591 &rt5651->jack_detect_work, msecs_to_jiffies(250));
1592
1593 return IRQ_HANDLED;
1594}
1595
6f0b819a
HG		 1596static int rt5651_set_jack(struct snd_soc_component *component,
1597 struct snd_soc_jack *hp_jack, void *data)
d8b8c878 1598{
d8b8c878
HG		 1599 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1600 int ret;
1601
1602 if (!rt5651->irq)
1603 return -EINVAL;
1604
1605 /* IRQ output on GPIO1 */
1606 snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
1607 RT5651_GP1_PIN_MASK, RT5651_GP1_PIN_IRQ);
1608
1609 /* Select jack detect source */
1610 switch (rt5651->jd_src) {
1611 case RT5651_JD1_1:
1612 snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
1613 RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_1);
1614 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL1,
1615 RT5651_JD1_1_IRQ_EN, RT5651_JD1_1_IRQ_EN);
1616 break;
1617 case RT5651_JD1_2:
1618 snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
1619 RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_2);
1620 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL1,
1621 RT5651_JD1_2_IRQ_EN, RT5651_JD1_2_IRQ_EN);
1622 break;
1623 case RT5651_JD2:
1624 snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
1625 RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD2);
1626 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL1,
1627 RT5651_JD2_IRQ_EN, RT5651_JD2_IRQ_EN);
1628 break;
1629 case RT5651_JD_NULL:
1630 return 0;
1631 default:
1632 dev_err(component->dev, "Currently only JD1_1 / JD1_2 / JD2 are supported\n");
1633 return -EINVAL;
1634 }
1635
57d9d7c3
HG		 1636 /* Enable jack detect power */
1637 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
1638 RT5651_PWR_JD_M, RT5651_PWR_JD_M);
1639
d8b8c878
HG		 1640 snd_soc_component_update_bits(component, RT5651_MICBIAS, 0x38, 0x38);
1641
1642 rt5651->hp_jack = hp_jack;
1643
1644 ret = devm_request_threaded_irq(component->dev, rt5651->irq, NULL,
1645 rt5651_irq,
1646 IRQF_TRIGGER_RISING |
1647 IRQF_TRIGGER_FALLING |
1648 IRQF_ONESHOT, "rt5651", rt5651);
1649 if (ret) {
1650 dev_err(component->dev, "Failed to reguest IRQ: %d\n", ret);
1651 return ret;
1652 }
1653
1654 /* sync initial jack state */
1655 queue_delayed_work(system_power_efficient_wq,
1656 &rt5651->jack_detect_work, 0);
1657
1658 return 0;
1659}
d8b8c878 1660
5f293d43
HG		 1661void rt5651_apply_properties(struct snd_soc_component *component)
1662{
1663 if (device_property_read_bool(component->dev, "realtek,in2-differential"))
1664 snd_soc_component_update_bits(component, RT5651_IN1_IN2,
1665 RT5651_IN_DF2, RT5651_IN_DF2);
1666
1667 if (device_property_read_bool(component->dev, "realtek,dmic-en"))
1668 snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
1669 RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
1670}
1671EXPORT_SYMBOL_GPL(rt5651_apply_properties);
1672
17b52010 1673static int rt5651_probe(struct snd_soc_component *component)
40bc18a2 1674{
17b52010 1675 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
40bc18a2 1676
17b52010 1677 rt5651->component = component;
40bc18a2 1678
3d7719d3
HG		 1679 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
1680 RT5651_PWR_LDO_DVO_MASK, RT5651_PWR_LDO_DVO_1_2V);
1681
17b52010 1682 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
40bc18a2 1683
5f293d43
HG		 1684 rt5651_apply_properties(component);
1685
40bc18a2
BL		 1686 return 0;
1687}
1688
1689#ifdef CONFIG_PM
17b52010 1690static int rt5651_suspend(struct snd_soc_component *component)
40bc18a2 1691{
17b52010 1692 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
40bc18a2
BL		 1693
1694 regcache_cache_only(rt5651->regmap, true);
1695 regcache_mark_dirty(rt5651->regmap);
1696 return 0;
1697}
1698
17b52010 1699static int rt5651_resume(struct snd_soc_component *component)
40bc18a2 1700{
17b52010 1701 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
40bc18a2
BL		 1702
1703 regcache_cache_only(rt5651->regmap, false);
17b52010 1704 snd_soc_component_cache_sync(component);
40bc18a2
BL		 1705
1706 return 0;
1707}
1708#else
1709#define rt5651_suspend NULL
1710#define rt5651_resume NULL
1711#endif
1712
1713#define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1714#define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1715 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1716
871c131d 1717static const struct snd_soc_dai_ops rt5651_aif_dai_ops = {
40bc18a2
BL		 1718 .hw_params = rt5651_hw_params,
1719 .set_fmt = rt5651_set_dai_fmt,
1720 .set_sysclk = rt5651_set_dai_sysclk,
1721 .set_pll = rt5651_set_dai_pll,
1722};
1723
871c131d 1724static struct snd_soc_dai_driver rt5651_dai[] = {
40bc18a2
BL		 1725 {
1726 .name = "rt5651-aif1",
1727 .id = RT5651_AIF1,
1728 .playback = {
1729 .stream_name = "AIF1 Playback",
1730 .channels_min = 1,
1731 .channels_max = 2,
1732 .rates = RT5651_STEREO_RATES,
1733 .formats = RT5651_FORMATS,
1734 },
1735 .capture = {
1736 .stream_name = "AIF1 Capture",
1737 .channels_min = 1,
1738 .channels_max = 2,
1739 .rates = RT5651_STEREO_RATES,
1740 .formats = RT5651_FORMATS,
1741 },
1742 .ops = &rt5651_aif_dai_ops,
1743 },
1744 {
1745 .name = "rt5651-aif2",
1746 .id = RT5651_AIF2,
1747 .playback = {
1748 .stream_name = "AIF2 Playback",
1749 .channels_min = 1,
1750 .channels_max = 2,
1751 .rates = RT5651_STEREO_RATES,
1752 .formats = RT5651_FORMATS,
1753 },
1754 .capture = {
1755 .stream_name = "AIF2 Capture",
1756 .channels_min = 1,
1757 .channels_max = 2,
1758 .rates = RT5651_STEREO_RATES,
1759 .formats = RT5651_FORMATS,
1760 },
1761 .ops = &rt5651_aif_dai_ops,
1762 },
1763};
1764
17b52010
KM		 1765static const struct snd_soc_component_driver soc_component_dev_rt5651 = {
1766 .probe = rt5651_probe,
1767 .suspend = rt5651_suspend,
1768 .resume = rt5651_resume,
1769 .set_bias_level = rt5651_set_bias_level,
6f0b819a 1770 .set_jack = rt5651_set_jack,
17b52010
KM		 1771 .controls = rt5651_snd_controls,
1772 .num_controls = ARRAY_SIZE(rt5651_snd_controls),
1773 .dapm_widgets = rt5651_dapm_widgets,
1774 .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
1775 .dapm_routes = rt5651_dapm_routes,
1776 .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
1777 .use_pmdown_time = 1,
1778 .endianness = 1,
1779 .non_legacy_dai_naming = 1,
40bc18a2
BL		 1780};
1781
1782static const struct regmap_config rt5651_regmap = {
1783 .reg_bits = 8,
1784 .val_bits = 16,
1785
1786 .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
1787 RT5651_PR_SPACING),
1788 .volatile_reg = rt5651_volatile_register,
1789 .readable_reg = rt5651_readable_register,
1790
1791 .cache_type = REGCACHE_RBTREE,
1792 .reg_defaults = rt5651_reg,
1793 .num_reg_defaults = ARRAY_SIZE(rt5651_reg),
1794 .ranges = rt5651_ranges,
1795 .num_ranges = ARRAY_SIZE(rt5651_ranges),
1796};
1797
3ae08dc0
BL		 1798#if defined(CONFIG_OF)
1799static const struct of_device_id rt5651_of_match[] = {
1800 { .compatible = "realtek,rt5651", },
1801 {},
1802};
1803MODULE_DEVICE_TABLE(of, rt5651_of_match);
1804#endif
1805
1806#ifdef CONFIG_ACPI
1807static const struct acpi_device_id rt5651_acpi_match[] = {
1808 { "10EC5651", 0 },
1809 { },
1810};
1811MODULE_DEVICE_TABLE(acpi, rt5651_acpi_match);
1812#endif
1813
40bc18a2
BL		 1814static const struct i2c_device_id rt5651_i2c_id[] = {
1815 { "rt5651", 0 },
1816 { }
1817};
1818MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
1819
b4435130
CC		 1820static int rt5651_quirk_cb(const struct dmi_system_id *id)
1821{
1822 rt5651_quirk = (unsigned long) id->driver_data;
1823 return 1;
1824}
1825
1826static const struct dmi_system_id rt5651_quirk_table[] = {
f85353fd
CC		 1827 {
1828 .callback = rt5651_quirk_cb,
1829 .matches = {
1830 DMI_MATCH(DMI_SYS_VENDOR, "KIANO"),
1831 DMI_MATCH(DMI_PRODUCT_NAME, "KIANO SlimNote 14.2"),
1832 },
1833 .driver_data = (unsigned long *) RT5651_JD1_1,
1834 },
b4435130
CC		 1835 {}
1836};
1837
17b52010 1838static int rt5651_jack_detect(struct snd_soc_component *component, int jack_insert)
80bbe4a3 1839{
80bbe4a3
CC		 1840 int jack_type;
1841
1842 if (jack_insert) {
1310e737 1843 rt5651_enable_micbias1_for_ovcd(component);
17b52010 1844 snd_soc_component_update_bits(component, RT5651_MICBIAS,
80bbe4a3
CC		 1845 RT5651_MIC1_OVCD_MASK |
1846 RT5651_MIC1_OVTH_MASK |
1847 RT5651_PWR_CLK12M_MASK |
1848 RT5651_PWR_MB_MASK,
1849 RT5651_MIC1_OVCD_EN |
1850 RT5651_MIC1_OVTH_600UA |
1851 RT5651_PWR_MB_PU |
1852 RT5651_PWR_CLK12M_PU);
1853 msleep(100);
17b52010 1854 if (snd_soc_component_read32(component, RT5651_IRQ_CTRL2) & RT5651_MB1_OC_CLR)
80bbe4a3
CC		 1855 jack_type = SND_JACK_HEADPHONE;
1856 else
1857 jack_type = SND_JACK_HEADSET;
17b52010 1858 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
80bbe4a3 1859 RT5651_MB1_OC_CLR, 0);
1310e737 1860 rt5651_disable_micbias1_for_ovcd(component);
80bbe4a3
CC		 1861 } else { /* jack out */
1862 jack_type = 0;
1863
17b52010 1864 snd_soc_component_update_bits(component, RT5651_MICBIAS,
80bbe4a3
CC		 1865 RT5651_MIC1_OVCD_MASK,
1866 RT5651_MIC1_OVCD_DIS);
1867 }
1868
1869 return jack_type;
1870}
1871
1872static void rt5651_jack_detect_work(struct work_struct *work)
1873{
1874 struct rt5651_priv *rt5651 =
1875 container_of(work, struct rt5651_priv, jack_detect_work.work);
1876
1877 int report, val = 0;
1878
17b52010 1879 if (!rt5651->component)
80bbe4a3
CC		 1880 return;
1881
54e3a3a1 1882 switch (rt5651->jd_src) {
80bbe4a3 1883 case RT5651_JD1_1:
17b52010 1884 val = snd_soc_component_read32(rt5651->component, RT5651_INT_IRQ_ST) & 0x1000;
80bbe4a3
CC		 1885 break;
1886 case RT5651_JD1_2:
17b52010 1887 val = snd_soc_component_read32(rt5651->component, RT5651_INT_IRQ_ST) & 0x2000;
80bbe4a3
CC		 1888 break;
1889 case RT5651_JD2:
17b52010 1890 val = snd_soc_component_read32(rt5651->component, RT5651_INT_IRQ_ST) & 0x4000;
80bbe4a3
CC		 1891 break;
1892 default:
1893 break;
1894 }
1895
17b52010 1896 report = rt5651_jack_detect(rt5651->component, !val);
80bbe4a3
CC		 1897
1898 snd_soc_jack_report(rt5651->hp_jack, report, SND_JACK_HEADSET);
1899}
1900
40bc18a2
BL		 1901static int rt5651_i2c_probe(struct i2c_client *i2c,
1902 const struct i2c_device_id *id)
1903{
40bc18a2
BL		 1904 struct rt5651_priv *rt5651;
1905 int ret;
1906
1907 rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
1908 GFP_KERNEL);
1909 if (NULL == rt5651)
1910 return -ENOMEM;
1911
1912 i2c_set_clientdata(i2c, rt5651);
1913
54e3a3a1
HG		 1914 dmi_check_system(rt5651_quirk_table);
1915 rt5651->jd_src = RT5651_JD_MAP(rt5651_quirk);
40bc18a2
BL		 1916
1917 rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
1918 if (IS_ERR(rt5651->regmap)) {
1919 ret = PTR_ERR(rt5651->regmap);
1920 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1921 ret);
1922 return ret;
1923 }
1924
1925 regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
1926 if (ret != RT5651_DEVICE_ID_VALUE) {
1927 dev_err(&i2c->dev,
469444fb 1928 "Device with ID register %#x is not rt5651\n", ret);
40bc18a2
BL		 1929 return -ENODEV;
1930 }
1931
1932 regmap_write(rt5651->regmap, RT5651_RESET, 0);
1933
1934 ret = regmap_register_patch(rt5651->regmap, init_list,
1935 ARRAY_SIZE(init_list));
1936 if (ret != 0)
1937 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1938
f06da4fd 1939 rt5651->irq = i2c->irq;
40bc18a2
BL		 1940 rt5651->hp_mute = 1;
1941
80bbe4a3
CC		 1942 INIT_DELAYED_WORK(&rt5651->jack_detect_work, rt5651_jack_detect_work);
1943
17b52010
KM		 1944 ret = devm_snd_soc_register_component(&i2c->dev,
1945 &soc_component_dev_rt5651,
40bc18a2
BL		 1946 rt5651_dai, ARRAY_SIZE(rt5651_dai));
1947
1948 return ret;
1949}
1950
1951static int rt5651_i2c_remove(struct i2c_client *i2c)
1952{
80bbe4a3
CC		 1953 struct rt5651_priv *rt5651 = i2c_get_clientdata(i2c);
1954
1955 cancel_delayed_work_sync(&rt5651->jack_detect_work);
40bc18a2
BL		 1956
1957 return 0;
1958}
1959
871c131d 1960static struct i2c_driver rt5651_i2c_driver = {
40bc18a2
BL		 1961 .driver = {
1962 .name = "rt5651",
3ae08dc0
BL		 1963 .acpi_match_table = ACPI_PTR(rt5651_acpi_match),
1964 .of_match_table = of_match_ptr(rt5651_of_match),
40bc18a2
BL		 1965 },
1966 .probe = rt5651_i2c_probe,
1967 .remove = rt5651_i2c_remove,
1968 .id_table = rt5651_i2c_id,
1969};
1970module_i2c_driver(rt5651_i2c_driver);
1971
1972MODULE_DESCRIPTION("ASoC RT5651 driver");
1973MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1974MODULE_LICENSE("GPL v2");
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