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ASoC: rt5663: Correct the mixer switch setting and remove redundant routing path
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / rt5663.c
CommitLineData
df7c5216 1/*
73444723 2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
df7c5216
BL		 3 *
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/i2c.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19#include <linux/acpi.h>
20#include <linux/workqueue.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include "rt5663.h"
31#include "rl6231.h"
32
73444723
BL		 33#define RT5663_DEVICE_ID_2 0x6451
34#define RT5663_DEVICE_ID_1 0x6406
df7c5216
BL		 35
36enum {
73444723
BL		 37 CODEC_VER_1,
38 CODEC_VER_0,
df7c5216
BL		 39};
40
41struct rt5663_priv {
42 struct snd_soc_codec *codec;
450f0f6a 43 struct rt5663_platform_data pdata;
df7c5216
BL		 44 struct regmap *regmap;
45 struct delayed_work jack_detect_work;
46 struct snd_soc_jack *hs_jack;
47 struct timer_list btn_check_timer;
48
73444723 49 int codec_ver;
df7c5216
BL		 50 int sysclk;
51 int sysclk_src;
52 int lrck;
53
54 int pll_src;
55 int pll_in;
56 int pll_out;
57
58 int jack_type;
59};
60
450f0f6a 61static const struct reg_sequence rt5663_patch_list[] = {
1d5c5b65 62 { 0x002a, 0x8020 },
d26ed933 63 { 0x0086, 0x0028 },
450f0f6a 64};
65
73444723 66static const struct reg_default rt5663_v2_reg[] = {
df7c5216
BL		 67 { 0x0000, 0x0000 },
68 { 0x0001, 0xc8c8 },
69 { 0x0002, 0x8080 },
70 { 0x0003, 0x8000 },
71 { 0x0004, 0xc80a },
72 { 0x0005, 0x0000 },
73 { 0x0006, 0x0000 },
74 { 0x0007, 0x0000 },
75 { 0x000a, 0x0000 },
76 { 0x000b, 0x0000 },
77 { 0x000c, 0x0000 },
78 { 0x000d, 0x0000 },
79 { 0x000f, 0x0808 },
80 { 0x0010, 0x4000 },
81 { 0x0011, 0x0000 },
82 { 0x0012, 0x1404 },
83 { 0x0013, 0x1000 },
84 { 0x0014, 0xa00a },
85 { 0x0015, 0x0404 },
86 { 0x0016, 0x0404 },
87 { 0x0017, 0x0011 },
88 { 0x0018, 0xafaf },
89 { 0x0019, 0xafaf },
90 { 0x001a, 0xafaf },
91 { 0x001b, 0x0011 },
92 { 0x001c, 0x2f2f },
93 { 0x001d, 0x2f2f },
94 { 0x001e, 0x2f2f },
95 { 0x001f, 0x0000 },
96 { 0x0020, 0x0000 },
97 { 0x0021, 0x0000 },
98 { 0x0022, 0x5757 },
99 { 0x0023, 0x0039 },
100 { 0x0024, 0x000b },
101 { 0x0026, 0xc0c0 },
102 { 0x0027, 0xc0c0 },
103 { 0x0028, 0xc0c0 },
104 { 0x0029, 0x8080 },
105 { 0x002a, 0xaaaa },
106 { 0x002b, 0xaaaa },
107 { 0x002c, 0xaba8 },
108 { 0x002d, 0x0000 },
109 { 0x002e, 0x0000 },
110 { 0x002f, 0x0000 },
111 { 0x0030, 0x0000 },
112 { 0x0031, 0x5000 },
113 { 0x0032, 0x0000 },
114 { 0x0033, 0x0000 },
115 { 0x0034, 0x0000 },
116 { 0x0035, 0x0000 },
117 { 0x003a, 0x0000 },
118 { 0x003b, 0x0000 },
119 { 0x003c, 0x00ff },
120 { 0x003d, 0x0000 },
121 { 0x003e, 0x00ff },
122 { 0x003f, 0x0000 },
123 { 0x0040, 0x0000 },
124 { 0x0041, 0x00ff },
125 { 0x0042, 0x0000 },
126 { 0x0043, 0x00ff },
127 { 0x0044, 0x0c0c },
128 { 0x0049, 0xc00b },
129 { 0x004a, 0x0000 },
130 { 0x004b, 0x031f },
131 { 0x004d, 0x0000 },
132 { 0x004e, 0x001f },
133 { 0x004f, 0x0000 },
134 { 0x0050, 0x001f },
135 { 0x0052, 0xf000 },
136 { 0x0061, 0x0000 },
137 { 0x0062, 0x0000 },
138 { 0x0063, 0x003e },
139 { 0x0064, 0x0000 },
140 { 0x0065, 0x0000 },
141 { 0x0066, 0x003f },
142 { 0x0067, 0x0000 },
143 { 0x006b, 0x0000 },
144 { 0x006d, 0xff00 },
145 { 0x006e, 0x2808 },
146 { 0x006f, 0x000a },
147 { 0x0070, 0x8000 },
148 { 0x0071, 0x8000 },
149 { 0x0072, 0x8000 },
150 { 0x0073, 0x7000 },
151 { 0x0074, 0x7770 },
152 { 0x0075, 0x0002 },
153 { 0x0076, 0x0001 },
154 { 0x0078, 0x00f0 },
155 { 0x0079, 0x0000 },
156 { 0x007a, 0x0000 },
157 { 0x007b, 0x0000 },
158 { 0x007c, 0x0000 },
159 { 0x007d, 0x0123 },
160 { 0x007e, 0x4500 },
161 { 0x007f, 0x8003 },
162 { 0x0080, 0x0000 },
163 { 0x0081, 0x0000 },
164 { 0x0082, 0x0000 },
165 { 0x0083, 0x0000 },
166 { 0x0084, 0x0000 },
167 { 0x0085, 0x0000 },
168 { 0x0086, 0x0008 },
169 { 0x0087, 0x0000 },
170 { 0x0088, 0x0000 },
171 { 0x0089, 0x0000 },
172 { 0x008a, 0x0000 },
173 { 0x008b, 0x0000 },
174 { 0x008c, 0x0003 },
175 { 0x008e, 0x0060 },
176 { 0x008f, 0x1000 },
177 { 0x0091, 0x0c26 },
178 { 0x0092, 0x0073 },
179 { 0x0093, 0x0000 },
180 { 0x0094, 0x0080 },
181 { 0x0098, 0x0000 },
182 { 0x0099, 0x0000 },
183 { 0x009a, 0x0007 },
184 { 0x009f, 0x0000 },
185 { 0x00a0, 0x0000 },
186 { 0x00a1, 0x0002 },
187 { 0x00a2, 0x0001 },
188 { 0x00a3, 0x0002 },
189 { 0x00a4, 0x0001 },
190 { 0x00ae, 0x2040 },
191 { 0x00af, 0x0000 },
192 { 0x00b6, 0x0000 },
193 { 0x00b7, 0x0000 },
194 { 0x00b8, 0x0000 },
195 { 0x00b9, 0x0000 },
196 { 0x00ba, 0x0002 },
197 { 0x00bb, 0x0000 },
198 { 0x00be, 0x0000 },
199 { 0x00c0, 0x0000 },
200 { 0x00c1, 0x0aaa },
201 { 0x00c2, 0xaa80 },
202 { 0x00c3, 0x0003 },
203 { 0x00c4, 0x0000 },
204 { 0x00d0, 0x0000 },
205 { 0x00d1, 0x2244 },
206 { 0x00d2, 0x0000 },
207 { 0x00d3, 0x3300 },
208 { 0x00d4, 0x2200 },
209 { 0x00d9, 0x0809 },
210 { 0x00da, 0x0000 },
211 { 0x00db, 0x0008 },
212 { 0x00dc, 0x00c0 },
213 { 0x00dd, 0x6724 },
214 { 0x00de, 0x3131 },
215 { 0x00df, 0x0008 },
216 { 0x00e0, 0x4000 },
217 { 0x00e1, 0x3131 },
218 { 0x00e2, 0x600c },
219 { 0x00ea, 0xb320 },
220 { 0x00eb, 0x0000 },
221 { 0x00ec, 0xb300 },
222 { 0x00ed, 0x0000 },
223 { 0x00ee, 0xb320 },
224 { 0x00ef, 0x0000 },
225 { 0x00f0, 0x0201 },
226 { 0x00f1, 0x0ddd },
227 { 0x00f2, 0x0ddd },
228 { 0x00f6, 0x0000 },
229 { 0x00f7, 0x0000 },
230 { 0x00f8, 0x0000 },
231 { 0x00fa, 0x0000 },
232 { 0x00fb, 0x0000 },
233 { 0x00fc, 0x0000 },
234 { 0x00fd, 0x0000 },
235 { 0x00fe, 0x10ec },
236 { 0x00ff, 0x6451 },
237 { 0x0100, 0xaaaa },
238 { 0x0101, 0x000a },
239 { 0x010a, 0xaaaa },
240 { 0x010b, 0xa0a0 },
241 { 0x010c, 0xaeae },
242 { 0x010d, 0xaaaa },
243 { 0x010e, 0xaaaa },
244 { 0x010f, 0xaaaa },
245 { 0x0110, 0xe002 },
246 { 0x0111, 0xa602 },
247 { 0x0112, 0xaaaa },
248 { 0x0113, 0x2000 },
249 { 0x0117, 0x0f00 },
250 { 0x0125, 0x0420 },
251 { 0x0132, 0x0000 },
252 { 0x0133, 0x0000 },
253 { 0x0136, 0x5555 },
254 { 0x0137, 0x5540 },
255 { 0x0138, 0x3700 },
256 { 0x0139, 0x79a1 },
257 { 0x013a, 0x2020 },
258 { 0x013b, 0x2020 },
259 { 0x013c, 0x2005 },
260 { 0x013f, 0x0000 },
261 { 0x0145, 0x0002 },
262 { 0x0146, 0x0000 },
263 { 0x0147, 0x0000 },
264 { 0x0148, 0x0000 },
265 { 0x0160, 0x4ec0 },
266 { 0x0161, 0x0080 },
267 { 0x0162, 0x0200 },
268 { 0x0163, 0x0800 },
269 { 0x0164, 0x0000 },
270 { 0x0165, 0x0000 },
271 { 0x0166, 0x0000 },
272 { 0x0167, 0x000f },
273 { 0x0168, 0x000f },
274 { 0x0170, 0x4e80 },
275 { 0x0171, 0x0080 },
276 { 0x0172, 0x0200 },
277 { 0x0173, 0x0800 },
278 { 0x0174, 0x00ff },
279 { 0x0175, 0x0000 },
280 { 0x0190, 0x4131 },
281 { 0x0191, 0x4131 },
282 { 0x0192, 0x4131 },
283 { 0x0193, 0x4131 },
284 { 0x0194, 0x0000 },
285 { 0x0195, 0x0000 },
286 { 0x0196, 0x0000 },
287 { 0x0197, 0x0000 },
288 { 0x0198, 0x0000 },
289 { 0x0199, 0x0000 },
290 { 0x01a0, 0x1e64 },
291 { 0x01a1, 0x06a3 },
292 { 0x01a2, 0x0000 },
293 { 0x01a3, 0x0000 },
294 { 0x01a4, 0x0000 },
295 { 0x01a5, 0x0000 },
296 { 0x01a6, 0x0000 },
297 { 0x01a7, 0x0000 },
298 { 0x01a8, 0x0000 },
299 { 0x01a9, 0x0000 },
300 { 0x01aa, 0x0000 },
301 { 0x01ab, 0x0000 },
302 { 0x01b5, 0x0000 },
303 { 0x01b6, 0x01c3 },
304 { 0x01b7, 0x02a0 },
305 { 0x01b8, 0x03e9 },
306 { 0x01b9, 0x1389 },
307 { 0x01ba, 0xc351 },
308 { 0x01bb, 0x0009 },
309 { 0x01bc, 0x0018 },
310 { 0x01bd, 0x002a },
311 { 0x01be, 0x004c },
312 { 0x01bf, 0x0097 },
313 { 0x01c0, 0x433d },
314 { 0x01c1, 0x0000 },
315 { 0x01c2, 0x0000 },
316 { 0x01c3, 0x0000 },
317 { 0x01c4, 0x0000 },
318 { 0x01c5, 0x0000 },
319 { 0x01c6, 0x0000 },
320 { 0x01c7, 0x0000 },
321 { 0x01c8, 0x40af },
322 { 0x01c9, 0x0702 },
323 { 0x01ca, 0x0000 },
324 { 0x01cb, 0x0000 },
325 { 0x01cc, 0x5757 },
326 { 0x01cd, 0x5757 },
327 { 0x01ce, 0x5757 },
328 { 0x01cf, 0x5757 },
329 { 0x01d0, 0x5757 },
330 { 0x01d1, 0x5757 },
331 { 0x01d2, 0x5757 },
332 { 0x01d3, 0x5757 },
333 { 0x01d4, 0x5757 },
334 { 0x01d5, 0x5757 },
335 { 0x01d6, 0x003c },
336 { 0x01da, 0x0000 },
337 { 0x01db, 0x0000 },
338 { 0x01dc, 0x0000 },
339 { 0x01de, 0x7c00 },
340 { 0x01df, 0x0320 },
341 { 0x01e0, 0x06a1 },
342 { 0x01e1, 0x0000 },
343 { 0x01e2, 0x0000 },
344 { 0x01e3, 0x0000 },
345 { 0x01e4, 0x0000 },
346 { 0x01e5, 0x0000 },
347 { 0x01e6, 0x0001 },
348 { 0x01e7, 0x0000 },
349 { 0x01e8, 0x0000 },
350 { 0x01ea, 0x0000 },
351 { 0x01eb, 0x0000 },
352 { 0x01ec, 0x0000 },
353 { 0x01ed, 0x0000 },
354 { 0x01ee, 0x0000 },
355 { 0x01ef, 0x0000 },
356 { 0x01f0, 0x0000 },
357 { 0x01f1, 0x0000 },
358 { 0x01f2, 0x0000 },
359 { 0x01f3, 0x0000 },
360 { 0x01f4, 0x0000 },
361 { 0x0200, 0x0000 },
362 { 0x0201, 0x0000 },
363 { 0x0202, 0x0000 },
364 { 0x0203, 0x0000 },
365 { 0x0204, 0x0000 },
366 { 0x0205, 0x0000 },
367 { 0x0206, 0x0000 },
368 { 0x0207, 0x0000 },
369 { 0x0208, 0x0000 },
370 { 0x0210, 0x60b1 },
371 { 0x0211, 0xa000 },
372 { 0x0212, 0x024c },
373 { 0x0213, 0xf7ff },
374 { 0x0214, 0x024c },
375 { 0x0215, 0x0102 },
376 { 0x0216, 0x00a3 },
377 { 0x0217, 0x0048 },
378 { 0x0218, 0x92c0 },
379 { 0x0219, 0x0000 },
380 { 0x021a, 0x00c8 },
381 { 0x021b, 0x0020 },
382 { 0x02fa, 0x0000 },
383 { 0x02fb, 0x0000 },
384 { 0x02fc, 0x0000 },
385 { 0x02ff, 0x0110 },
386 { 0x0300, 0x001f },
387 { 0x0301, 0x032c },
388 { 0x0302, 0x5f21 },
389 { 0x0303, 0x4000 },
390 { 0x0304, 0x4000 },
391 { 0x0305, 0x06d5 },
392 { 0x0306, 0x8000 },
393 { 0x0307, 0x0700 },
394 { 0x0310, 0x4560 },
395 { 0x0311, 0xa4a8 },
396 { 0x0312, 0x7418 },
397 { 0x0313, 0x0000 },
398 { 0x0314, 0x0006 },
399 { 0x0315, 0xffff },
400 { 0x0316, 0xc400 },
401 { 0x0317, 0x0000 },
402 { 0x0330, 0x00a6 },
403 { 0x0331, 0x04c3 },
404 { 0x0332, 0x27c8 },
405 { 0x0333, 0xbf50 },
406 { 0x0334, 0x0045 },
407 { 0x0335, 0x0007 },
408 { 0x0336, 0x7418 },
409 { 0x0337, 0x0501 },
410 { 0x0338, 0x0000 },
411 { 0x0339, 0x0010 },
412 { 0x033a, 0x1010 },
413 { 0x03c0, 0x7e00 },
414 { 0x03c1, 0x8000 },
415 { 0x03c2, 0x8000 },
416 { 0x03c3, 0x8000 },
417 { 0x03c4, 0x8000 },
418 { 0x03c5, 0x8000 },
419 { 0x03c6, 0x8000 },
420 { 0x03c7, 0x8000 },
421 { 0x03c8, 0x8000 },
422 { 0x03c9, 0x8000 },
423 { 0x03ca, 0x8000 },
424 { 0x03cb, 0x8000 },
425 { 0x03cc, 0x8000 },
426 { 0x03d0, 0x0000 },
427 { 0x03d1, 0x0000 },
428 { 0x03d2, 0x0000 },
429 { 0x03d3, 0x0000 },
430 { 0x03d4, 0x2000 },
431 { 0x03d5, 0x2000 },
432 { 0x03d6, 0x0000 },
433 { 0x03d7, 0x0000 },
434 { 0x03d8, 0x2000 },
435 { 0x03d9, 0x2000 },
436 { 0x03da, 0x2000 },
437 { 0x03db, 0x2000 },
438 { 0x03dc, 0x0000 },
439 { 0x03dd, 0x0000 },
440 { 0x03de, 0x0000 },
441 { 0x03df, 0x2000 },
442 { 0x03e0, 0x0000 },
443 { 0x03e1, 0x0000 },
444 { 0x03e2, 0x0000 },
445 { 0x03e3, 0x0000 },
446 { 0x03e4, 0x0000 },
447 { 0x03e5, 0x0000 },
448 { 0x03e6, 0x0000 },
449 { 0x03e7, 0x0000 },
450 { 0x03e8, 0x0000 },
451 { 0x03e9, 0x0000 },
452 { 0x03ea, 0x0000 },
453 { 0x03eb, 0x0000 },
454 { 0x03ec, 0x0000 },
455 { 0x03ed, 0x0000 },
456 { 0x03ee, 0x0000 },
457 { 0x03ef, 0x0000 },
458 { 0x03f0, 0x0800 },
459 { 0x03f1, 0x0800 },
460 { 0x03f2, 0x0800 },
461 { 0x03f3, 0x0800 },
462 { 0x03fe, 0x0000 },
463 { 0x03ff, 0x0000 },
464 { 0x07f0, 0x0000 },
465 { 0x07fa, 0x0000 },
466};
467
468static const struct reg_default rt5663_reg[] = {
469 { 0x0000, 0x0000 },
470 { 0x0002, 0x0008 },
471 { 0x0005, 0x1000 },
472 { 0x0006, 0x1000 },
473 { 0x000a, 0x0000 },
474 { 0x0010, 0x000f },
475 { 0x0015, 0x42c1 },
476 { 0x0016, 0x0000 },
477 { 0x0018, 0x000b },
478 { 0x0019, 0xafaf },
479 { 0x001c, 0x2f2f },
480 { 0x001f, 0x0000 },
481 { 0x0022, 0x5757 },
482 { 0x0023, 0x0039 },
483 { 0x0026, 0xc0c0 },
484 { 0x0029, 0x8080 },
1d5c5b65 485 { 0x002a, 0x8020 },
df7c5216
BL		 486 { 0x002c, 0x000c },
487 { 0x002d, 0x0000 },
488 { 0x0040, 0x0808 },
489 { 0x0061, 0x0000 },
490 { 0x0062, 0x0000 },
491 { 0x0063, 0x003e },
492 { 0x0064, 0x0000 },
493 { 0x0065, 0x0000 },
494 { 0x0066, 0x0000 },
495 { 0x006b, 0x0000 },
496 { 0x006e, 0x0000 },
497 { 0x006f, 0x0000 },
498 { 0x0070, 0x8020 },
499 { 0x0073, 0x1000 },
500 { 0x0074, 0xe400 },
501 { 0x0075, 0x0002 },
502 { 0x0076, 0x0001 },
503 { 0x0077, 0x00f0 },
504 { 0x0078, 0x0000 },
505 { 0x0079, 0x0000 },
506 { 0x007a, 0x0123 },
507 { 0x007b, 0x8003 },
508 { 0x0080, 0x0000 },
509 { 0x0081, 0x0000 },
510 { 0x0082, 0x0000 },
511 { 0x0083, 0x0000 },
512 { 0x0084, 0x0000 },
d26ed933 513 { 0x0086, 0x0028 },
df7c5216
BL		 514 { 0x0087, 0x0000 },
515 { 0x008a, 0x0000 },
516 { 0x008b, 0x0000 },
517 { 0x008c, 0x0003 },
518 { 0x008e, 0x0004 },
519 { 0x008f, 0x1000 },
520 { 0x0090, 0x0646 },
521 { 0x0091, 0x0e3e },
522 { 0x0092, 0x1071 },
523 { 0x0093, 0x0000 },
524 { 0x0094, 0x0080 },
525 { 0x0097, 0x0000 },
526 { 0x0098, 0x0000 },
527 { 0x009a, 0x0000 },
528 { 0x009f, 0x0000 },
529 { 0x00ae, 0x2000 },
530 { 0x00af, 0x0000 },
531 { 0x00b6, 0x0000 },
532 { 0x00b7, 0x0000 },
533 { 0x00b8, 0x0000 },
534 { 0x00ba, 0x0000 },
535 { 0x00bb, 0x0000 },
536 { 0x00be, 0x0000 },
537 { 0x00bf, 0x0000 },
538 { 0x00c0, 0x0000 },
539 { 0x00c1, 0x0000 },
540 { 0x00c5, 0x0000 },
541 { 0x00cb, 0xa02f },
542 { 0x00cc, 0x0000 },
543 { 0x00cd, 0x0e02 },
544 { 0x00d9, 0x08f9 },
545 { 0x00db, 0x0008 },
546 { 0x00dc, 0x00c0 },
547 { 0x00dd, 0x6724 },
548 { 0x00de, 0x3131 },
549 { 0x00df, 0x0008 },
550 { 0x00e0, 0x4000 },
551 { 0x00e1, 0x3131 },
552 { 0x00e2, 0x0043 },
553 { 0x00e4, 0x400b },
554 { 0x00e5, 0x8031 },
555 { 0x00e6, 0x3080 },
556 { 0x00e7, 0x4100 },
557 { 0x00e8, 0x1400 },
558 { 0x00e9, 0xe00a },
559 { 0x00ea, 0x0404 },
560 { 0x00eb, 0x0404 },
561 { 0x00ec, 0xb320 },
562 { 0x00ed, 0x0000 },
563 { 0x00f4, 0x0000 },
564 { 0x00f6, 0x0000 },
565 { 0x00f8, 0x0000 },
566 { 0x00fa, 0x8000 },
567 { 0x00fd, 0x0001 },
568 { 0x00fe, 0x10ec },
569 { 0x00ff, 0x6406 },
570 { 0x0100, 0xa0a0 },
571 { 0x0108, 0x4444 },
572 { 0x0109, 0x4444 },
573 { 0x010a, 0xaaaa },
574 { 0x010b, 0x00a0 },
575 { 0x010c, 0x8aaa },
576 { 0x010d, 0xaaaa },
577 { 0x010e, 0x2aaa },
578 { 0x010f, 0x002a },
579 { 0x0110, 0xa0a4 },
580 { 0x0111, 0x4602 },
581 { 0x0112, 0x0101 },
582 { 0x0113, 0x2000 },
583 { 0x0114, 0x0000 },
584 { 0x0116, 0x0000 },
585 { 0x0117, 0x0f00 },
586 { 0x0118, 0x0006 },
587 { 0x0125, 0x2224 },
588 { 0x0126, 0x5550 },
589 { 0x0127, 0x0400 },
590 { 0x0128, 0x7711 },
591 { 0x0132, 0x0004 },
592 { 0x0137, 0x5441 },
593 { 0x0139, 0x79a1 },
594 { 0x013a, 0x30c0 },
595 { 0x013b, 0x2000 },
596 { 0x013c, 0x2005 },
597 { 0x013d, 0x30c0 },
598 { 0x013e, 0x0000 },
599 { 0x0140, 0x3700 },
600 { 0x0141, 0x1f00 },
601 { 0x0144, 0x0000 },
602 { 0x0145, 0x0002 },
603 { 0x0146, 0x0000 },
604 { 0x0160, 0x0e80 },
605 { 0x0161, 0x0020 },
606 { 0x0162, 0x0080 },
607 { 0x0163, 0x0800 },
608 { 0x0164, 0x0000 },
609 { 0x0165, 0x0000 },
610 { 0x0166, 0x0000 },
611 { 0x0167, 0x1417 },
612 { 0x0168, 0x0017 },
613 { 0x0169, 0x0017 },
614 { 0x0180, 0x2000 },
615 { 0x0181, 0x0000 },
616 { 0x0182, 0x0000 },
617 { 0x0183, 0x2000 },
618 { 0x0184, 0x0000 },
619 { 0x0185, 0x0000 },
620 { 0x01b0, 0x4b30 },
621 { 0x01b1, 0x0000 },
622 { 0x01b2, 0xd870 },
623 { 0x01b3, 0x0000 },
624 { 0x01b4, 0x0030 },
625 { 0x01b5, 0x5757 },
626 { 0x01b6, 0x5757 },
627 { 0x01b7, 0x5757 },
628 { 0x01b8, 0x5757 },
629 { 0x01c0, 0x433d },
630 { 0x01c1, 0x0540 },
631 { 0x01c2, 0x0000 },
632 { 0x01c3, 0x0000 },
633 { 0x01c4, 0x0000 },
634 { 0x01c5, 0x0009 },
635 { 0x01c6, 0x0018 },
636 { 0x01c7, 0x002a },
637 { 0x01c8, 0x004c },
638 { 0x01c9, 0x0097 },
639 { 0x01ca, 0x01c3 },
640 { 0x01cb, 0x03e9 },
641 { 0x01cc, 0x1389 },
642 { 0x01cd, 0xc351 },
643 { 0x01ce, 0x0000 },
644 { 0x01cf, 0x0000 },
645 { 0x01d0, 0x0000 },
646 { 0x01d1, 0x0000 },
647 { 0x01d2, 0x0000 },
648 { 0x01d3, 0x003c },
649 { 0x01d4, 0x5757 },
650 { 0x01d5, 0x5757 },
651 { 0x01d6, 0x5757 },
652 { 0x01d7, 0x5757 },
653 { 0x01d8, 0x5757 },
654 { 0x01d9, 0x5757 },
655 { 0x01da, 0x0000 },
656 { 0x01db, 0x0000 },
657 { 0x01dd, 0x0009 },
658 { 0x01de, 0x7f00 },
659 { 0x01df, 0x00c8 },
660 { 0x01e0, 0x0691 },
661 { 0x01e1, 0x0000 },
662 { 0x01e2, 0x0000 },
663 { 0x01e3, 0x0000 },
664 { 0x01e4, 0x0000 },
665 { 0x01e5, 0x0040 },
666 { 0x01e6, 0x0000 },
667 { 0x01e7, 0x0000 },
668 { 0x01e8, 0x0000 },
669 { 0x01ea, 0x0000 },
670 { 0x01eb, 0x0000 },
671 { 0x01ec, 0x0000 },
672 { 0x01ed, 0x0000 },
673 { 0x01ee, 0x0000 },
674 { 0x01ef, 0x0000 },
675 { 0x01f0, 0x0000 },
676 { 0x01f1, 0x0000 },
677 { 0x01f2, 0x0000 },
678 { 0x0200, 0x0000 },
679 { 0x0201, 0x2244 },
680 { 0x0202, 0xaaaa },
681 { 0x0250, 0x8010 },
682 { 0x0251, 0x0000 },
683 { 0x0252, 0x028a },
684 { 0x02fa, 0x0000 },
685 { 0x02fb, 0x0000 },
686 { 0x02fc, 0x0000 },
687 { 0x0300, 0x0000 },
688 { 0x03d0, 0x0000 },
689 { 0x03d1, 0x0000 },
690 { 0x03d2, 0x0000 },
691 { 0x03d3, 0x0000 },
692 { 0x03d4, 0x2000 },
693 { 0x03d5, 0x2000 },
694 { 0x03d6, 0x0000 },
695 { 0x03d7, 0x0000 },
696 { 0x03d8, 0x2000 },
697 { 0x03d9, 0x2000 },
698 { 0x03da, 0x2000 },
699 { 0x03db, 0x2000 },
700 { 0x03dc, 0x0000 },
701 { 0x03dd, 0x0000 },
702 { 0x03de, 0x0000 },
703 { 0x03df, 0x2000 },
704 { 0x03e0, 0x0000 },
705 { 0x03e1, 0x0000 },
706 { 0x03e2, 0x0000 },
707 { 0x03e3, 0x0000 },
708 { 0x03e4, 0x0000 },
709 { 0x03e5, 0x0000 },
710 { 0x03e6, 0x0000 },
711 { 0x03e7, 0x0000 },
712 { 0x03e8, 0x0000 },
713 { 0x03e9, 0x0000 },
714 { 0x03ea, 0x0000 },
715 { 0x03eb, 0x0000 },
716 { 0x03ec, 0x0000 },
717 { 0x03ed, 0x0000 },
718 { 0x03ee, 0x0000 },
719 { 0x03ef, 0x0000 },
720 { 0x03f0, 0x0800 },
721 { 0x03f1, 0x0800 },
722 { 0x03f2, 0x0800 },
723 { 0x03f3, 0x0800 },
724};
725
726static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
727{
728 switch (reg) {
729 case RT5663_RESET:
730 case RT5663_SIL_DET_CTL:
731 case RT5663_HP_IMP_GAIN_2:
732 case RT5663_AD_DA_MIXER:
733 case RT5663_FRAC_DIV_2:
734 case RT5663_MICBIAS_1:
735 case RT5663_ASRC_11_2:
736 case RT5663_ADC_EQ_1:
737 case RT5663_INT_ST_1:
738 case RT5663_INT_ST_2:
73444723 739 case RT5663_GPIO_STA1:
df7c5216
BL		 740 case RT5663_SIN_GEN_1:
741 case RT5663_IL_CMD_1:
742 case RT5663_IL_CMD_5:
743 case RT5663_IL_CMD_PWRSAV1:
744 case RT5663_EM_JACK_TYPE_1:
745 case RT5663_EM_JACK_TYPE_2:
746 case RT5663_EM_JACK_TYPE_3:
747 case RT5663_JD_CTRL2:
748 case RT5663_VENDOR_ID:
749 case RT5663_VENDOR_ID_1:
750 case RT5663_VENDOR_ID_2:
751 case RT5663_PLL_INT_REG:
752 case RT5663_SOFT_RAMP:
753 case RT5663_STO_DRE_1:
754 case RT5663_STO_DRE_5:
755 case RT5663_STO_DRE_6:
756 case RT5663_STO_DRE_7:
757 case RT5663_MIC_DECRO_1:
758 case RT5663_MIC_DECRO_4:
759 case RT5663_HP_IMP_SEN_1:
760 case RT5663_HP_IMP_SEN_3:
761 case RT5663_HP_IMP_SEN_4:
762 case RT5663_HP_IMP_SEN_5:
763 case RT5663_HP_CALIB_1_1:
764 case RT5663_HP_CALIB_9:
765 case RT5663_HP_CALIB_ST1:
766 case RT5663_HP_CALIB_ST2:
767 case RT5663_HP_CALIB_ST3:
768 case RT5663_HP_CALIB_ST4:
769 case RT5663_HP_CALIB_ST5:
770 case RT5663_HP_CALIB_ST6:
771 case RT5663_HP_CALIB_ST7:
772 case RT5663_HP_CALIB_ST8:
773 case RT5663_HP_CALIB_ST9:
774 case RT5663_ANA_JD:
775 return true;
776 default:
777 return false;
778 }
779}
780
781static bool rt5663_readable_register(struct device *dev, unsigned int reg)
782{
783 switch (reg) {
784 case RT5663_RESET:
785 case RT5663_HP_OUT_EN:
786 case RT5663_HP_LCH_DRE:
787 case RT5663_HP_RCH_DRE:
788 case RT5663_CALIB_BST:
789 case RT5663_RECMIX:
790 case RT5663_SIL_DET_CTL:
791 case RT5663_PWR_SAV_SILDET:
792 case RT5663_SIDETONE_CTL:
793 case RT5663_STO1_DAC_DIG_VOL:
794 case RT5663_STO1_ADC_DIG_VOL:
795 case RT5663_STO1_BOOST:
796 case RT5663_HP_IMP_GAIN_1:
797 case RT5663_HP_IMP_GAIN_2:
798 case RT5663_STO1_ADC_MIXER:
799 case RT5663_AD_DA_MIXER:
800 case RT5663_STO_DAC_MIXER:
801 case RT5663_DIG_SIDE_MIXER:
802 case RT5663_BYPASS_STO_DAC:
803 case RT5663_CALIB_REC_MIX:
804 case RT5663_PWR_DIG_1:
805 case RT5663_PWR_DIG_2:
806 case RT5663_PWR_ANLG_1:
807 case RT5663_PWR_ANLG_2:
808 case RT5663_PWR_ANLG_3:
809 case RT5663_PWR_MIXER:
810 case RT5663_SIG_CLK_DET:
811 case RT5663_PRE_DIV_GATING_1:
812 case RT5663_PRE_DIV_GATING_2:
813 case RT5663_I2S1_SDP:
814 case RT5663_ADDA_CLK_1:
815 case RT5663_ADDA_RST:
816 case RT5663_FRAC_DIV_1:
817 case RT5663_FRAC_DIV_2:
818 case RT5663_TDM_1:
819 case RT5663_TDM_2:
820 case RT5663_TDM_3:
821 case RT5663_TDM_4:
822 case RT5663_TDM_5:
823 case RT5663_GLB_CLK:
824 case RT5663_PLL_1:
825 case RT5663_PLL_2:
826 case RT5663_ASRC_1:
827 case RT5663_ASRC_2:
828 case RT5663_ASRC_4:
829 case RT5663_DUMMY_REG:
830 case RT5663_ASRC_8:
831 case RT5663_ASRC_9:
832 case RT5663_ASRC_11:
833 case RT5663_DEPOP_1:
834 case RT5663_DEPOP_2:
835 case RT5663_DEPOP_3:
836 case RT5663_HP_CHARGE_PUMP_1:
837 case RT5663_HP_CHARGE_PUMP_2:
838 case RT5663_MICBIAS_1:
839 case RT5663_RC_CLK:
840 case RT5663_ASRC_11_2:
841 case RT5663_DUMMY_REG_2:
842 case RT5663_REC_PATH_GAIN:
843 case RT5663_AUTO_1MRC_CLK:
844 case RT5663_ADC_EQ_1:
845 case RT5663_ADC_EQ_2:
846 case RT5663_IRQ_1:
847 case RT5663_IRQ_2:
848 case RT5663_IRQ_3:
849 case RT5663_IRQ_4:
850 case RT5663_IRQ_5:
851 case RT5663_INT_ST_1:
852 case RT5663_INT_ST_2:
853 case RT5663_GPIO_1:
854 case RT5663_GPIO_2:
73444723 855 case RT5663_GPIO_STA1:
df7c5216
BL		 856 case RT5663_SIN_GEN_1:
857 case RT5663_SIN_GEN_2:
858 case RT5663_SIN_GEN_3:
859 case RT5663_SOF_VOL_ZC1:
860 case RT5663_IL_CMD_1:
861 case RT5663_IL_CMD_2:
862 case RT5663_IL_CMD_3:
863 case RT5663_IL_CMD_4:
864 case RT5663_IL_CMD_5:
865 case RT5663_IL_CMD_6:
866 case RT5663_IL_CMD_7:
867 case RT5663_IL_CMD_8:
868 case RT5663_IL_CMD_PWRSAV1:
869 case RT5663_IL_CMD_PWRSAV2:
870 case RT5663_EM_JACK_TYPE_1:
871 case RT5663_EM_JACK_TYPE_2:
872 case RT5663_EM_JACK_TYPE_3:
873 case RT5663_EM_JACK_TYPE_4:
874 case RT5663_EM_JACK_TYPE_5:
875 case RT5663_EM_JACK_TYPE_6:
876 case RT5663_STO1_HPF_ADJ1:
877 case RT5663_STO1_HPF_ADJ2:
878 case RT5663_FAST_OFF_MICBIAS:
879 case RT5663_JD_CTRL1:
880 case RT5663_JD_CTRL2:
881 case RT5663_DIG_MISC:
882 case RT5663_VENDOR_ID:
883 case RT5663_VENDOR_ID_1:
884 case RT5663_VENDOR_ID_2:
885 case RT5663_DIG_VOL_ZCD:
886 case RT5663_ANA_BIAS_CUR_1:
887 case RT5663_ANA_BIAS_CUR_2:
888 case RT5663_ANA_BIAS_CUR_3:
889 case RT5663_ANA_BIAS_CUR_4:
890 case RT5663_ANA_BIAS_CUR_5:
891 case RT5663_ANA_BIAS_CUR_6:
892 case RT5663_BIAS_CUR_5:
893 case RT5663_BIAS_CUR_6:
894 case RT5663_BIAS_CUR_7:
895 case RT5663_BIAS_CUR_8:
896 case RT5663_DACREF_LDO:
897 case RT5663_DUMMY_REG_3:
898 case RT5663_BIAS_CUR_9:
899 case RT5663_DUMMY_REG_4:
900 case RT5663_VREFADJ_OP:
901 case RT5663_VREF_RECMIX:
902 case RT5663_CHARGE_PUMP_1:
903 case RT5663_CHARGE_PUMP_1_2:
904 case RT5663_CHARGE_PUMP_1_3:
905 case RT5663_CHARGE_PUMP_2:
906 case RT5663_DIG_IN_PIN1:
907 case RT5663_PAD_DRV_CTL:
908 case RT5663_PLL_INT_REG:
909 case RT5663_CHOP_DAC_L:
910 case RT5663_CHOP_ADC:
911 case RT5663_CALIB_ADC:
912 case RT5663_CHOP_DAC_R:
913 case RT5663_DUMMY_CTL_DACLR:
914 case RT5663_DUMMY_REG_5:
915 case RT5663_SOFT_RAMP:
916 case RT5663_TEST_MODE_1:
917 case RT5663_TEST_MODE_2:
918 case RT5663_TEST_MODE_3:
919 case RT5663_STO_DRE_1:
920 case RT5663_STO_DRE_2:
921 case RT5663_STO_DRE_3:
922 case RT5663_STO_DRE_4:
923 case RT5663_STO_DRE_5:
924 case RT5663_STO_DRE_6:
925 case RT5663_STO_DRE_7:
926 case RT5663_STO_DRE_8:
927 case RT5663_STO_DRE_9:
928 case RT5663_STO_DRE_10:
929 case RT5663_MIC_DECRO_1:
930 case RT5663_MIC_DECRO_2:
931 case RT5663_MIC_DECRO_3:
932 case RT5663_MIC_DECRO_4:
933 case RT5663_MIC_DECRO_5:
934 case RT5663_MIC_DECRO_6:
935 case RT5663_HP_DECRO_1:
936 case RT5663_HP_DECRO_2:
937 case RT5663_HP_DECRO_3:
938 case RT5663_HP_DECRO_4:
939 case RT5663_HP_DECOUP:
940 case RT5663_HP_IMP_SEN_MAP8:
941 case RT5663_HP_IMP_SEN_MAP9:
942 case RT5663_HP_IMP_SEN_MAP10:
943 case RT5663_HP_IMP_SEN_MAP11:
944 case RT5663_HP_IMP_SEN_1:
945 case RT5663_HP_IMP_SEN_2:
946 case RT5663_HP_IMP_SEN_3:
947 case RT5663_HP_IMP_SEN_4:
948 case RT5663_HP_IMP_SEN_5:
949 case RT5663_HP_IMP_SEN_6:
950 case RT5663_HP_IMP_SEN_7:
951 case RT5663_HP_IMP_SEN_8:
952 case RT5663_HP_IMP_SEN_9:
953 case RT5663_HP_IMP_SEN_10:
954 case RT5663_HP_IMP_SEN_11:
955 case RT5663_HP_IMP_SEN_12:
956 case RT5663_HP_IMP_SEN_13:
957 case RT5663_HP_IMP_SEN_14:
958 case RT5663_HP_IMP_SEN_15:
959 case RT5663_HP_IMP_SEN_16:
960 case RT5663_HP_IMP_SEN_17:
961 case RT5663_HP_IMP_SEN_18:
962 case RT5663_HP_IMP_SEN_19:
963 case RT5663_HP_IMPSEN_DIG5:
964 case RT5663_HP_IMPSEN_MAP1:
965 case RT5663_HP_IMPSEN_MAP2:
966 case RT5663_HP_IMPSEN_MAP3:
967 case RT5663_HP_IMPSEN_MAP4:
968 case RT5663_HP_IMPSEN_MAP5:
969 case RT5663_HP_IMPSEN_MAP7:
970 case RT5663_HP_LOGIC_1:
971 case RT5663_HP_LOGIC_2:
972 case RT5663_HP_CALIB_1:
973 case RT5663_HP_CALIB_1_1:
974 case RT5663_HP_CALIB_2:
975 case RT5663_HP_CALIB_3:
976 case RT5663_HP_CALIB_4:
977 case RT5663_HP_CALIB_5:
978 case RT5663_HP_CALIB_5_1:
979 case RT5663_HP_CALIB_6:
980 case RT5663_HP_CALIB_7:
981 case RT5663_HP_CALIB_9:
982 case RT5663_HP_CALIB_10:
983 case RT5663_HP_CALIB_11:
984 case RT5663_HP_CALIB_ST1:
985 case RT5663_HP_CALIB_ST2:
986 case RT5663_HP_CALIB_ST3:
987 case RT5663_HP_CALIB_ST4:
988 case RT5663_HP_CALIB_ST5:
989 case RT5663_HP_CALIB_ST6:
990 case RT5663_HP_CALIB_ST7:
991 case RT5663_HP_CALIB_ST8:
992 case RT5663_HP_CALIB_ST9:
993 case RT5663_HP_AMP_DET:
994 case RT5663_DUMMY_REG_6:
995 case RT5663_HP_BIAS:
996 case RT5663_CBJ_1:
997 case RT5663_CBJ_2:
998 case RT5663_CBJ_3:
999 case RT5663_DUMMY_1:
1000 case RT5663_DUMMY_2:
1001 case RT5663_DUMMY_3:
1002 case RT5663_ANA_JD:
1003 case RT5663_ADC_LCH_LPF1_A1:
1004 case RT5663_ADC_RCH_LPF1_A1:
1005 case RT5663_ADC_LCH_LPF1_H0:
1006 case RT5663_ADC_RCH_LPF1_H0:
1007 case RT5663_ADC_LCH_BPF1_A1:
1008 case RT5663_ADC_RCH_BPF1_A1:
1009 case RT5663_ADC_LCH_BPF1_A2:
1010 case RT5663_ADC_RCH_BPF1_A2:
1011 case RT5663_ADC_LCH_BPF1_H0:
1012 case RT5663_ADC_RCH_BPF1_H0:
1013 case RT5663_ADC_LCH_BPF2_A1:
1014 case RT5663_ADC_RCH_BPF2_A1:
1015 case RT5663_ADC_LCH_BPF2_A2:
1016 case RT5663_ADC_RCH_BPF2_A2:
1017 case RT5663_ADC_LCH_BPF2_H0:
1018 case RT5663_ADC_RCH_BPF2_H0:
1019 case RT5663_ADC_LCH_BPF3_A1:
1020 case RT5663_ADC_RCH_BPF3_A1:
1021 case RT5663_ADC_LCH_BPF3_A2:
1022 case RT5663_ADC_RCH_BPF3_A2:
1023 case RT5663_ADC_LCH_BPF3_H0:
1024 case RT5663_ADC_RCH_BPF3_H0:
1025 case RT5663_ADC_LCH_BPF4_A1:
1026 case RT5663_ADC_RCH_BPF4_A1:
1027 case RT5663_ADC_LCH_BPF4_A2:
1028 case RT5663_ADC_RCH_BPF4_A2:
1029 case RT5663_ADC_LCH_BPF4_H0:
1030 case RT5663_ADC_RCH_BPF4_H0:
1031 case RT5663_ADC_LCH_HPF1_A1:
1032 case RT5663_ADC_RCH_HPF1_A1:
1033 case RT5663_ADC_LCH_HPF1_H0:
1034 case RT5663_ADC_RCH_HPF1_H0:
1035 case RT5663_ADC_EQ_PRE_VOL_L:
1036 case RT5663_ADC_EQ_PRE_VOL_R:
1037 case RT5663_ADC_EQ_POST_VOL_L:
1038 case RT5663_ADC_EQ_POST_VOL_R:
1039 return true;
1040 default:
1041 return false;
1042 }
1043}
1044
73444723 1045static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
df7c5216
BL		 1046{
1047 switch (reg) {
1048 case RT5663_RESET:
73444723
BL		 1049 case RT5663_CBJ_TYPE_2:
1050 case RT5663_PDM_OUT_CTL:
1051 case RT5663_PDM_I2C_DATA_CTL1:
1052 case RT5663_PDM_I2C_DATA_CTL4:
1053 case RT5663_ALC_BK_GAIN:
df7c5216
BL		 1054 case RT5663_PLL_2:
1055 case RT5663_MICBIAS_1:
1056 case RT5663_ADC_EQ_1:
1057 case RT5663_INT_ST_1:
73444723 1058 case RT5663_GPIO_STA2:
df7c5216
BL		 1059 case RT5663_IL_CMD_1:
1060 case RT5663_IL_CMD_5:
73444723 1061 case RT5663_A_JD_CTRL:
df7c5216
BL		 1062 case RT5663_JD_CTRL2:
1063 case RT5663_VENDOR_ID:
1064 case RT5663_VENDOR_ID_1:
1065 case RT5663_VENDOR_ID_2:
1066 case RT5663_STO_DRE_1:
1067 case RT5663_STO_DRE_5:
1068 case RT5663_STO_DRE_6:
1069 case RT5663_STO_DRE_7:
73444723
BL		 1070 case RT5663_MONO_DYNA_6:
1071 case RT5663_STO1_SIL_DET:
1072 case RT5663_MONOL_SIL_DET:
1073 case RT5663_MONOR_SIL_DET:
1074 case RT5663_STO2_DAC_SIL:
1075 case RT5663_MONO_AMP_CAL_ST1:
1076 case RT5663_MONO_AMP_CAL_ST2:
1077 case RT5663_MONO_AMP_CAL_ST3:
1078 case RT5663_MONO_AMP_CAL_ST4:
df7c5216
BL		 1079 case RT5663_HP_IMP_SEN_2:
1080 case RT5663_HP_IMP_SEN_3:
1081 case RT5663_HP_IMP_SEN_4:
1082 case RT5663_HP_IMP_SEN_10:
1083 case RT5663_HP_CALIB_1:
1084 case RT5663_HP_CALIB_10:
1085 case RT5663_HP_CALIB_ST1:
1086 case RT5663_HP_CALIB_ST4:
1087 case RT5663_HP_CALIB_ST5:
1088 case RT5663_HP_CALIB_ST6:
1089 case RT5663_HP_CALIB_ST7:
1090 case RT5663_HP_CALIB_ST8:
1091 case RT5663_HP_CALIB_ST9:
73444723
BL		 1092 case RT5663_HP_CALIB_ST10:
1093 case RT5663_HP_CALIB_ST11:
df7c5216
BL		 1094 return true;
1095 default:
1096 return false;
1097 }
1098}
1099
73444723 1100static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
df7c5216
BL		 1101{
1102 switch (reg) {
73444723
BL		 1103 case RT5663_LOUT_CTRL:
1104 case RT5663_HP_AMP_2:
1105 case RT5663_MONO_OUT:
1106 case RT5663_MONO_GAIN:
1107 case RT5663_AEC_BST:
1108 case RT5663_IN1_IN2:
1109 case RT5663_IN3_IN4:
1110 case RT5663_INL1_INR1:
1111 case RT5663_CBJ_TYPE_2:
1112 case RT5663_CBJ_TYPE_3:
1113 case RT5663_CBJ_TYPE_4:
1114 case RT5663_CBJ_TYPE_5:
1115 case RT5663_CBJ_TYPE_8:
1116 case RT5663_DAC3_DIG_VOL:
1117 case RT5663_DAC3_CTRL:
1118 case RT5663_MONO_ADC_DIG_VOL:
1119 case RT5663_STO2_ADC_DIG_VOL:
1120 case RT5663_MONO_ADC_BST_GAIN:
1121 case RT5663_STO2_ADC_BST_GAIN:
1122 case RT5663_SIDETONE_CTRL:
1123 case RT5663_MONO1_ADC_MIXER:
1124 case RT5663_STO2_ADC_MIXER:
1125 case RT5663_MONO_DAC_MIXER:
1126 case RT5663_DAC2_SRC_CTRL:
1127 case RT5663_IF_3_4_DATA_CTL:
1128 case RT5663_IF_5_DATA_CTL:
1129 case RT5663_PDM_OUT_CTL:
1130 case RT5663_PDM_I2C_DATA_CTL1:
1131 case RT5663_PDM_I2C_DATA_CTL2:
1132 case RT5663_PDM_I2C_DATA_CTL3:
1133 case RT5663_PDM_I2C_DATA_CTL4:
1134 case RT5663_RECMIX1_NEW:
1135 case RT5663_RECMIX1L_0:
1136 case RT5663_RECMIX1L:
1137 case RT5663_RECMIX1R_0:
1138 case RT5663_RECMIX1R:
1139 case RT5663_RECMIX2_NEW:
1140 case RT5663_RECMIX2_L_2:
1141 case RT5663_RECMIX2_R:
1142 case RT5663_RECMIX2_R_2:
1143 case RT5663_CALIB_REC_LR:
1144 case RT5663_ALC_BK_GAIN:
1145 case RT5663_MONOMIX_GAIN:
1146 case RT5663_MONOMIX_IN_GAIN:
1147 case RT5663_OUT_MIXL_GAIN:
1148 case RT5663_OUT_LMIX_IN_GAIN:
1149 case RT5663_OUT_RMIX_IN_GAIN:
1150 case RT5663_OUT_RMIX_IN_GAIN1:
1151 case RT5663_LOUT_MIXER_CTRL:
1152 case RT5663_PWR_VOL:
1153 case RT5663_ADCDAC_RST:
1154 case RT5663_I2S34_SDP:
1155 case RT5663_I2S5_SDP:
1156 case RT5663_TDM_6:
1157 case RT5663_TDM_7:
1158 case RT5663_TDM_8:
1159 case RT5663_TDM_9:
1160 case RT5663_ASRC_3:
1161 case RT5663_ASRC_6:
1162 case RT5663_ASRC_7:
1163 case RT5663_PLL_TRK_13:
1164 case RT5663_I2S_M_CLK_CTL:
1165 case RT5663_FDIV_I2S34_M_CLK:
1166 case RT5663_FDIV_I2S34_M_CLK2:
1167 case RT5663_FDIV_I2S5_M_CLK:
1168 case RT5663_FDIV_I2S5_M_CLK2:
1169 case RT5663_V2_IRQ_4:
1170 case RT5663_GPIO_3:
1171 case RT5663_GPIO_4:
1172 case RT5663_GPIO_STA2:
1173 case RT5663_HP_AMP_DET1:
1174 case RT5663_HP_AMP_DET2:
1175 case RT5663_HP_AMP_DET3:
1176 case RT5663_MID_BD_HP_AMP:
1177 case RT5663_LOW_BD_HP_AMP:
1178 case RT5663_SOF_VOL_ZC2:
1179 case RT5663_ADC_STO2_ADJ1:
1180 case RT5663_ADC_STO2_ADJ2:
1181 case RT5663_A_JD_CTRL:
1182 case RT5663_JD1_TRES_CTRL:
1183 case RT5663_JD2_TRES_CTRL:
1184 case RT5663_V2_JD_CTRL2:
1185 case RT5663_DUM_REG_2:
1186 case RT5663_DUM_REG_3:
df7c5216
BL		 1187 case RT5663_VENDOR_ID:
1188 case RT5663_VENDOR_ID_1:
1189 case RT5663_VENDOR_ID_2:
73444723
BL		 1190 case RT5663_DACADC_DIG_VOL2:
1191 case RT5663_DIG_IN_PIN2:
1192 case RT5663_PAD_DRV_CTL1:
1193 case RT5663_SOF_RAM_DEPOP:
1194 case RT5663_VOL_TEST:
1195 case RT5663_TEST_MODE_4:
1196 case RT5663_TEST_MODE_5:
df7c5216 1197 case RT5663_STO_DRE_9:
73444723
BL		 1198 case RT5663_MONO_DYNA_1:
1199 case RT5663_MONO_DYNA_2:
1200 case RT5663_MONO_DYNA_3:
1201 case RT5663_MONO_DYNA_4:
1202 case RT5663_MONO_DYNA_5:
1203 case RT5663_MONO_DYNA_6:
1204 case RT5663_STO1_SIL_DET:
1205 case RT5663_MONOL_SIL_DET:
1206 case RT5663_MONOR_SIL_DET:
1207 case RT5663_STO2_DAC_SIL:
1208 case RT5663_PWR_SAV_CTL1:
1209 case RT5663_PWR_SAV_CTL2:
1210 case RT5663_PWR_SAV_CTL3:
1211 case RT5663_PWR_SAV_CTL4:
1212 case RT5663_PWR_SAV_CTL5:
1213 case RT5663_PWR_SAV_CTL6:
1214 case RT5663_MONO_AMP_CAL1:
1215 case RT5663_MONO_AMP_CAL2:
1216 case RT5663_MONO_AMP_CAL3:
1217 case RT5663_MONO_AMP_CAL4:
1218 case RT5663_MONO_AMP_CAL5:
1219 case RT5663_MONO_AMP_CAL6:
1220 case RT5663_MONO_AMP_CAL7:
1221 case RT5663_MONO_AMP_CAL_ST1:
1222 case RT5663_MONO_AMP_CAL_ST2:
1223 case RT5663_MONO_AMP_CAL_ST3:
1224 case RT5663_MONO_AMP_CAL_ST4:
1225 case RT5663_MONO_AMP_CAL_ST5:
1226 case RT5663_V2_HP_IMP_SEN_13:
1227 case RT5663_V2_HP_IMP_SEN_14:
1228 case RT5663_V2_HP_IMP_SEN_6:
1229 case RT5663_V2_HP_IMP_SEN_7:
1230 case RT5663_V2_HP_IMP_SEN_8:
1231 case RT5663_V2_HP_IMP_SEN_9:
1232 case RT5663_V2_HP_IMP_SEN_10:
1233 case RT5663_HP_LOGIC_3:
1234 case RT5663_HP_CALIB_ST10:
1235 case RT5663_HP_CALIB_ST11:
1236 case RT5663_PRO_REG_TBL_4:
1237 case RT5663_PRO_REG_TBL_5:
1238 case RT5663_PRO_REG_TBL_6:
1239 case RT5663_PRO_REG_TBL_7:
1240 case RT5663_PRO_REG_TBL_8:
1241 case RT5663_PRO_REG_TBL_9:
1242 case RT5663_SAR_ADC_INL_1:
1243 case RT5663_SAR_ADC_INL_2:
1244 case RT5663_SAR_ADC_INL_3:
1245 case RT5663_SAR_ADC_INL_4:
1246 case RT5663_SAR_ADC_INL_5:
1247 case RT5663_SAR_ADC_INL_6:
1248 case RT5663_SAR_ADC_INL_7:
1249 case RT5663_SAR_ADC_INL_8:
1250 case RT5663_SAR_ADC_INL_9:
1251 case RT5663_SAR_ADC_INL_10:
1252 case RT5663_SAR_ADC_INL_11:
1253 case RT5663_SAR_ADC_INL_12:
1254 case RT5663_DRC_CTRL_1:
1255 case RT5663_DRC1_CTRL_2:
1256 case RT5663_DRC1_CTRL_3:
1257 case RT5663_DRC1_CTRL_4:
1258 case RT5663_DRC1_CTRL_5:
1259 case RT5663_DRC1_CTRL_6:
1260 case RT5663_DRC1_HD_CTRL_1:
1261 case RT5663_DRC1_HD_CTRL_2:
1262 case RT5663_DRC1_PRI_REG_1:
1263 case RT5663_DRC1_PRI_REG_2:
1264 case RT5663_DRC1_PRI_REG_3:
1265 case RT5663_DRC1_PRI_REG_4:
1266 case RT5663_DRC1_PRI_REG_5:
1267 case RT5663_DRC1_PRI_REG_6:
1268 case RT5663_DRC1_PRI_REG_7:
1269 case RT5663_DRC1_PRI_REG_8:
1270 case RT5663_ALC_PGA_CTL_1:
1271 case RT5663_ALC_PGA_CTL_2:
1272 case RT5663_ALC_PGA_CTL_3:
1273 case RT5663_ALC_PGA_CTL_4:
1274 case RT5663_ALC_PGA_CTL_5:
1275 case RT5663_ALC_PGA_CTL_6:
1276 case RT5663_ALC_PGA_CTL_7:
1277 case RT5663_ALC_PGA_CTL_8:
1278 case RT5663_ALC_PGA_REG_1:
1279 case RT5663_ALC_PGA_REG_2:
1280 case RT5663_ALC_PGA_REG_3:
1281 case RT5663_ADC_EQ_RECOV_1:
1282 case RT5663_ADC_EQ_RECOV_2:
1283 case RT5663_ADC_EQ_RECOV_3:
1284 case RT5663_ADC_EQ_RECOV_4:
1285 case RT5663_ADC_EQ_RECOV_5:
1286 case RT5663_ADC_EQ_RECOV_6:
1287 case RT5663_ADC_EQ_RECOV_7:
1288 case RT5663_ADC_EQ_RECOV_8:
1289 case RT5663_ADC_EQ_RECOV_9:
1290 case RT5663_ADC_EQ_RECOV_10:
1291 case RT5663_ADC_EQ_RECOV_11:
1292 case RT5663_ADC_EQ_RECOV_12:
1293 case RT5663_ADC_EQ_RECOV_13:
1294 case RT5663_VID_HIDDEN:
1295 case RT5663_VID_CUSTOMER:
1296 case RT5663_SCAN_MODE:
1297 case RT5663_I2C_BYPA:
df7c5216
BL		 1298 return true;
1299 case RT5663_TDM_1:
1300 case RT5663_DEPOP_3:
1301 case RT5663_ASRC_11_2:
1302 case RT5663_INT_ST_2:
73444723 1303 case RT5663_GPIO_STA1:
df7c5216
BL		 1304 case RT5663_SIN_GEN_1:
1305 case RT5663_SIN_GEN_2:
1306 case RT5663_SIN_GEN_3:
1307 case RT5663_IL_CMD_PWRSAV1:
1308 case RT5663_IL_CMD_PWRSAV2:
1309 case RT5663_EM_JACK_TYPE_1:
1310 case RT5663_EM_JACK_TYPE_2:
1311 case RT5663_EM_JACK_TYPE_3:
1312 case RT5663_EM_JACK_TYPE_4:
1313 case RT5663_FAST_OFF_MICBIAS:
1314 case RT5663_ANA_BIAS_CUR_1:
1315 case RT5663_ANA_BIAS_CUR_2:
1316 case RT5663_BIAS_CUR_9:
1317 case RT5663_DUMMY_REG_4:
1318 case RT5663_VREF_RECMIX:
1319 case RT5663_CHARGE_PUMP_1_2:
1320 case RT5663_CHARGE_PUMP_1_3:
1321 case RT5663_CHARGE_PUMP_2:
1322 case RT5663_CHOP_DAC_R:
1323 case RT5663_DUMMY_CTL_DACLR:
1324 case RT5663_DUMMY_REG_5:
1325 case RT5663_SOFT_RAMP:
1326 case RT5663_TEST_MODE_1:
1327 case RT5663_STO_DRE_10:
1328 case RT5663_MIC_DECRO_1:
1329 case RT5663_MIC_DECRO_2:
1330 case RT5663_MIC_DECRO_3:
1331 case RT5663_MIC_DECRO_4:
1332 case RT5663_MIC_DECRO_5:
1333 case RT5663_MIC_DECRO_6:
1334 case RT5663_HP_DECRO_1:
1335 case RT5663_HP_DECRO_2:
1336 case RT5663_HP_DECRO_3:
1337 case RT5663_HP_DECRO_4:
1338 case RT5663_HP_DECOUP:
1339 case RT5663_HP_IMPSEN_MAP4:
1340 case RT5663_HP_IMPSEN_MAP5:
1341 case RT5663_HP_IMPSEN_MAP7:
1342 case RT5663_HP_CALIB_1:
1343 case RT5663_CBJ_1:
1344 case RT5663_CBJ_2:
1345 case RT5663_CBJ_3:
1346 return false;
1347 default:
1348 return rt5663_readable_register(dev, reg);
1349 }
1350}
1351
1352static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
73444723 1353static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
df7c5216
BL		 1354static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1355static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1356
1357/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1358static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1359 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1360 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1361 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1362 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1363 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1364 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1365 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1366);
1367
1368/* Interface data select */
1369static const char * const rt5663_if1_adc_data_select[] = {
1370 "L/R", "R/L", "L/L", "R/R"
1371};
1372
66d7c262 1373static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
df7c5216
BL		 1374 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1375
1376static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1377 bool enable)
1378{
1379 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1380
1381 if (enable) {
1382 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723 1383 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
df7c5216
BL		 1384 /* reset in-line command */
1385 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723
BL		 1386 RT5663_RESET_4BTN_INL_MASK,
1387 RT5663_RESET_4BTN_INL_RESET);
df7c5216 1388 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723
BL		 1389 RT5663_RESET_4BTN_INL_MASK,
1390 RT5663_RESET_4BTN_INL_NOR);
1391 switch (rt5663->codec_ver) {
1392 case CODEC_VER_1:
df7c5216 1393 snd_soc_update_bits(codec, RT5663_IRQ_3,
73444723
BL		 1394 RT5663_V2_EN_IRQ_INLINE_MASK,
1395 RT5663_V2_EN_IRQ_INLINE_NOR);
df7c5216 1396 break;
73444723 1397 case CODEC_VER_0:
df7c5216
BL		 1398 snd_soc_update_bits(codec, RT5663_IRQ_2,
1399 RT5663_EN_IRQ_INLINE_MASK,
1400 RT5663_EN_IRQ_INLINE_NOR);
1401 break;
1402 default:
73444723 1403 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1404 }
1405 } else {
73444723
BL		 1406 switch (rt5663->codec_ver) {
1407 case CODEC_VER_1:
df7c5216 1408 snd_soc_update_bits(codec, RT5663_IRQ_3,
73444723
BL		 1409 RT5663_V2_EN_IRQ_INLINE_MASK,
1410 RT5663_V2_EN_IRQ_INLINE_BYP);
df7c5216 1411 break;
73444723 1412 case CODEC_VER_0:
df7c5216
BL		 1413 snd_soc_update_bits(codec, RT5663_IRQ_2,
1414 RT5663_EN_IRQ_INLINE_MASK,
1415 RT5663_EN_IRQ_INLINE_BYP);
1416 break;
1417 default:
73444723 1418 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1419 }
1420 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723 1421 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
df7c5216
BL		 1422 /* reset in-line command */
1423 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723
BL		 1424 RT5663_RESET_4BTN_INL_MASK,
1425 RT5663_RESET_4BTN_INL_RESET);
df7c5216 1426 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723
BL		 1427 RT5663_RESET_4BTN_INL_MASK,
1428 RT5663_RESET_4BTN_INL_NOR);
df7c5216
BL		 1429 }
1430}
1431
1432/**
73444723 1433 * rt5663_v2_jack_detect - Detect headset.
df7c5216
BL		 1434 * @codec: SoC audio codec device.
1435 * @jack_insert: Jack insert or not.
1436 *
1437 * Detect whether is headset or not when jack inserted.
1438 *
1439 * Returns detect status.
1440 */
1441
73444723 1442static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
df7c5216
BL		 1443{
1444 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
73444723 1445 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
df7c5216
BL		 1446 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1447
1448 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1449 if (jack_insert) {
73444723
BL		 1450 snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
1451 snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
df7c5216
BL		 1452
1453 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1454 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1455 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1456 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1457 snd_soc_dapm_sync(dapm);
1458 snd_soc_update_bits(codec, RT5663_RC_CLK,
73444723 1459 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
df7c5216
BL		 1460 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
1461
1462 while (i < 5) {
1463 msleep(sleep_time[i]);
73444723 1464 val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
df7c5216
BL		 1465 if (val == 0x1 || val == 0x2 || val == 0x3)
1466 break;
1467 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
1468 __func__, val, sleep_time[i]);
1469 i++;
1470 }
1471 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1472 switch (val) {
1473 case 1:
1474 case 2:
73444723 1475 rt5663->jack_type = SND_JACK_HEADSET;
df7c5216
BL		 1476 rt5663_enable_push_button_irq(codec, true);
1477 break;
1478 default:
1479 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1480 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1481 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1482 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1483 snd_soc_dapm_sync(dapm);
73444723 1484 rt5663->jack_type = SND_JACK_HEADPHONE;
df7c5216
BL		 1485 break;
1486 }
1487 } else {
1488 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
1489
73444723 1490 if (rt5663->jack_type == SND_JACK_HEADSET) {
df7c5216
BL		 1491 rt5663_enable_push_button_irq(codec, false);
1492 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1493 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1494 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1495 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1496 snd_soc_dapm_sync(dapm);
1497 }
73444723 1498 rt5663->jack_type = 0;
df7c5216
BL		 1499 }
1500
73444723
BL		 1501 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1502 return rt5663->jack_type;
df7c5216
BL		 1503}
1504
1505/**
1506 * rt5663_jack_detect - Detect headset.
1507 * @codec: SoC audio codec device.
1508 * @jack_insert: Jack insert or not.
1509 *
1510 * Detect whether is headset or not when jack inserted.
1511 *
1512 * Returns detect status.
1513 */
1514static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1515{
1516 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
8f244127 1517 int val, i = 0;
df7c5216
BL		 1518
1519 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1520
1521 if (jack_insert) {
1522 snd_soc_update_bits(codec, RT5663_DIG_MISC,
73444723 1523 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
df7c5216 1524 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
73444723
BL		 1525 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1526 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1527 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
df7c5216
BL		 1528 snd_soc_update_bits(codec, RT5663_DUMMY_1,
1529 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1530 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1531 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1532 snd_soc_update_bits(codec, RT5663_CBJ_1,
1533 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1534 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1535 snd_soc_update_bits(codec, RT5663_IL_CMD_2,
1536 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1537 /* BST1 power on for JD */
1538 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
73444723 1539 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
df7c5216
BL		 1540 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
1541 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1542 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1543 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1544 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
73444723
BL		 1545 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1546 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1547 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
df7c5216 1548 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
73444723 1549 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
df7c5216
BL		 1550 snd_soc_update_bits(codec, RT5663_IRQ_1,
1551 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
8f244127 1552
1553 while (true) {
1554 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1555 if (!(val & 0x80))
1556 usleep_range(10000, 10005);
1557 else
1558 break;
1559
1560 if (i > 200)
df7c5216 1561 break;
8f244127 1562 i++;
df7c5216 1563 }
8f244127 1564
1565 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) & 0x0003;
df7c5216 1566 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
8f244127 1567
df7c5216
BL		 1568 switch (val) {
1569 case 1:
1570 case 2:
1571 rt5663->jack_type = SND_JACK_HEADSET;
1572 rt5663_enable_push_button_irq(codec, true);
1573 break;
1574 default:
1575 rt5663->jack_type = SND_JACK_HEADPHONE;
1576 break;
1577 }
1578 } else {
1579 if (rt5663->jack_type == SND_JACK_HEADSET)
1580 rt5663_enable_push_button_irq(codec, false);
1581 rt5663->jack_type = 0;
1582 }
1583
1584 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1585 return rt5663->jack_type;
1586}
1587
66d7c262 1588static int rt5663_button_detect(struct snd_soc_codec *codec)
df7c5216
BL		 1589{
1590 int btn_type, val;
1591
1592 val = snd_soc_read(codec, RT5663_IL_CMD_5);
1593 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val);
1594 btn_type = val & 0xfff0;
1595 snd_soc_write(codec, RT5663_IL_CMD_5, val);
1596
1597 return btn_type;
1598}
1599
1600static irqreturn_t rt5663_irq(int irq, void *data)
1601{
1602 struct rt5663_priv *rt5663 = data;
1603
1604 dev_dbg(rt5663->codec->dev, "%s IRQ queue work\n", __func__);
1605
1606 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1607 msecs_to_jiffies(250));
1608
1609 return IRQ_HANDLED;
1610}
1611
1612int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1613 struct snd_soc_jack *hs_jack)
1614{
1615 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1616
1617 rt5663->hs_jack = hs_jack;
1618
1619 rt5663_irq(0, rt5663);
1620
1621 return 0;
1622}
1623EXPORT_SYMBOL_GPL(rt5663_set_jack_detect);
1624
1625static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
1626{
1627 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1628 int val = snd_soc_read(codec, RT5663_INT_ST_1);
1629
1630 dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
1631
1632 /* JD1 */
73444723
BL		 1633 switch (rt5663->codec_ver) {
1634 case CODEC_VER_1:
df7c5216 1635 return !(val & 0x2000);
73444723 1636 case CODEC_VER_0:
df7c5216
BL		 1637 return !(val & 0x1000);
1638 default:
73444723 1639 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1640 }
1641
1642 return false;
1643}
1644
1645static void rt5663_jack_detect_work(struct work_struct *work)
1646{
1647 struct rt5663_priv *rt5663 =
1648 container_of(work, struct rt5663_priv, jack_detect_work.work);
1649 struct snd_soc_codec *codec = rt5663->codec;
1650 int btn_type, report = 0;
1651
1652 if (!codec)
1653 return;
1654
1655 if (rt5663_check_jd_status(codec)) {
1656 /* jack in */
1657 if (rt5663->jack_type == 0) {
1658 /* jack was out, report jack type */
73444723
BL		 1659 switch (rt5663->codec_ver) {
1660 case CODEC_VER_1:
1661 report = rt5663_v2_jack_detect(
1662 rt5663->codec, 1);
df7c5216 1663 break;
73444723 1664 case CODEC_VER_0:
df7c5216
BL		 1665 report = rt5663_jack_detect(rt5663->codec, 1);
1666 break;
1667 default:
73444723 1668 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1669 }
1670 } else {
1671 /* jack is already in, report button event */
1672 report = SND_JACK_HEADSET;
1673 btn_type = rt5663_button_detect(rt5663->codec);
1674 /**
1675 * rt5663 can report three kinds of button behavior,
1676 * one click, double click and hold. However,
1677 * currently we will report button pressed/released
1678 * event. So all the three button behaviors are
1679 * treated as button pressed.
1680 */
1681 switch (btn_type) {
1682 case 0x8000:
1683 case 0x4000:
1684 case 0x2000:
1685 report |= SND_JACK_BTN_0;
1686 break;
1687 case 0x1000:
1688 case 0x0800:
1689 case 0x0400:
1690 report |= SND_JACK_BTN_1;
1691 break;
1692 case 0x0200:
1693 case 0x0100:
1694 case 0x0080:
1695 report |= SND_JACK_BTN_2;
1696 break;
1697 case 0x0040:
1698 case 0x0020:
1699 case 0x0010:
1700 report |= SND_JACK_BTN_3;
1701 break;
1702 case 0x0000: /* unpressed */
1703 break;
1704 default:
1705 btn_type = 0;
1706 dev_err(rt5663->codec->dev,
1707 "Unexpected button code 0x%04x\n",
1708 btn_type);
1709 break;
1710 }
1711 /* button release or spurious interrput*/
1712 if (btn_type == 0)
1713 report = rt5663->jack_type;
1714 }
1715 } else {
1716 /* jack out */
73444723
BL		 1717 switch (rt5663->codec_ver) {
1718 case CODEC_VER_1:
1719 report = rt5663_v2_jack_detect(rt5663->codec, 0);
df7c5216 1720 break;
73444723 1721 case CODEC_VER_0:
df7c5216
BL		 1722 report = rt5663_jack_detect(rt5663->codec, 0);
1723 break;
1724 default:
73444723 1725 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1726 }
1727 }
1728 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
1729 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1730 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1731 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1732}
1733
1734static const struct snd_kcontrol_new rt5663_snd_controls[] = {
1735 /* DAC Digital Volume */
1736 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
73444723 1737 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
df7c5216
BL		 1738 87, 0, dac_vol_tlv),
1739 /* ADC Digital Volume Control */
1740 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
73444723 1741 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
df7c5216 1742 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
73444723 1743 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
df7c5216
BL		 1744 63, 0, adc_vol_tlv),
1745};
1746
73444723 1747static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
df7c5216
BL		 1748 /* Headphone Output Volume */
1749 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
73444723
BL		 1750 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
1751 rt5663_v2_hp_vol_tlv),
df7c5216 1752 /* Mic Boost Volume */
73444723
BL		 1753 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
1754 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
df7c5216
BL		 1755};
1756
1757static const struct snd_kcontrol_new rt5663_specific_controls[] = {
1758 /* Headphone Output Volume */
1759 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
1760 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
1761 rt5663_hp_vol_tlv),
1762 /* Mic Boost Volume*/
1763 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
1764 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
1765 /* Data Swap for Slot0/1 in ADCDAT1 */
1766 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
1767};
1768
1769static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1770 struct snd_soc_dapm_widget *sink)
1771{
1772 unsigned int val;
1773 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1774
1775 val = snd_soc_read(codec, RT5663_GLB_CLK);
1776 val &= RT5663_SCLK_SRC_MASK;
1777 if (val == RT5663_SCLK_SRC_PLL1)
1778 return 1;
1779 else
1780 return 0;
1781}
1782
1783static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
1784 struct snd_soc_dapm_widget *sink)
1785{
1786 unsigned int reg, shift, val;
1787 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1788 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1789
73444723 1790 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 1791 switch (w->shift) {
73444723
BL		 1792 case RT5663_ADC_STO1_ASRC_SHIFT:
1793 reg = RT5663_ASRC_3;
1794 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
df7c5216 1795 break;
73444723 1796 case RT5663_DAC_STO1_ASRC_SHIFT:
df7c5216 1797 reg = RT5663_ASRC_2;
73444723 1798 shift = RT5663_DA_STO1_TRACK_SHIFT;
df7c5216
BL		 1799 break;
1800 default:
1801 return 0;
1802 }
1803 } else {
1804 switch (w->shift) {
1805 case RT5663_ADC_STO1_ASRC_SHIFT:
1806 reg = RT5663_ASRC_2;
1807 shift = RT5663_AD_STO1_TRACK_SHIFT;
1808 break;
1809 case RT5663_DAC_STO1_ASRC_SHIFT:
1810 reg = RT5663_ASRC_2;
1811 shift = RT5663_DA_STO1_TRACK_SHIFT;
1812 break;
1813 default:
1814 return 0;
1815 }
1816 }
1817
1818 val = (snd_soc_read(codec, reg) >> shift) & 0x7;
1819
1820 if (val)
1821 return 1;
1822
1823 return 0;
1824}
1825
1826static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
1827 struct snd_soc_dapm_widget *sink)
1828{
1829 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1830 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1831 int da_asrc_en, ad_asrc_en;
1832
1833 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1834 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
73444723
BL		 1835 switch (rt5663->codec_ver) {
1836 case CODEC_VER_1:
1837 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
1838 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
df7c5216 1839 break;
73444723 1840 case CODEC_VER_0:
df7c5216
BL		 1841 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1842 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
1843 break;
1844 default:
73444723 1845 dev_err(codec->dev, "Unknown CODEC Version\n");
56efaed5 1846 return 1;
df7c5216
BL		 1847 }
1848
1849 if (da_asrc_en || ad_asrc_en)
1850 if (rt5663->sysclk > rt5663->lrck * 384)
1851 return 1;
1852
1853 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n");
1854
1855 return 0;
1856}
1857
1858/**
1859 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
1860 * @codec: SoC audio codec device.
1861 * @filter_mask: mask of filters.
1862 * @clk_src: clock source
1863 *
73444723 1864 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
df7c5216
BL		 1865 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1866 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1867 * ASRC function will track i2s clock and generate a corresponding system clock
1868 * for codec. This function provides an API to select the clock source for a
1869 * set of filters specified by the mask. And the codec driver will turn on ASRC
1870 * for these filters if ASRC is selected as their clock source.
1871 */
1872int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1873 unsigned int filter_mask, unsigned int clk_src)
1874{
73444723 1875 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
df7c5216
BL		 1876 unsigned int asrc2_mask = 0;
1877 unsigned int asrc2_value = 0;
1878 unsigned int asrc3_mask = 0;
1879 unsigned int asrc3_value = 0;
1880
1881 switch (clk_src) {
1882 case RT5663_CLK_SEL_SYS:
1883 case RT5663_CLK_SEL_I2S1_ASRC:
1884 break;
1885
1886 default:
1887 return -EINVAL;
1888 }
1889
1890 if (filter_mask & RT5663_DA_STEREO_FILTER) {
73444723
BL		 1891 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
1892 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
df7c5216
BL		 1893 }
1894
1895 if (filter_mask & RT5663_AD_STEREO_FILTER) {
73444723
BL		 1896 switch (rt5663->codec_ver) {
1897 case CODEC_VER_1:
1898 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
1899 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
df7c5216 1900 break;
73444723 1901 case CODEC_VER_0:
df7c5216
BL		 1902 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
1903 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
1904 break;
1905 default:
73444723 1906 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1907 }
1908 }
1909
1910 if (asrc2_mask)
1911 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask,
1912 asrc2_value);
1913
1914 if (asrc3_mask)
73444723 1915 snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
df7c5216
BL		 1916 asrc3_value);
1917
1918 return 0;
1919}
1920EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
1921
1922/* Analog Mixer */
73444723
BL		 1923static const struct snd_kcontrol_new rt5663_recmix1l[] = {
1924 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
1925 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
1926 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
1927 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
df7c5216
BL		 1928};
1929
73444723
BL		 1930static const struct snd_kcontrol_new rt5663_recmix1r[] = {
1931 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
1932 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
df7c5216
BL		 1933};
1934
1935/* Digital Mixer */
1936static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
1937 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
73444723 1938 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
df7c5216 1939 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
73444723 1940 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
df7c5216
BL		 1941};
1942
73444723 1943static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
df7c5216 1944 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
73444723 1945 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
df7c5216 1946 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
73444723 1947 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
df7c5216
BL		 1948};
1949
1950static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
1951 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
73444723 1952 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
df7c5216 1953 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
73444723 1954 RT5663_M_DAC1_L_SHIFT, 1, 1),
df7c5216
BL		 1955};
1956
1957static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
1958 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
73444723 1959 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
df7c5216 1960 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
73444723 1961 RT5663_M_DAC1_R_SHIFT, 1, 1),
df7c5216
BL		 1962};
1963
1964static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
1965 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
73444723 1966 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
df7c5216
BL		 1967};
1968
1969static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
1d5c5b65 1970 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
1971 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
df7c5216
BL		 1972};
1973
1974/* Out Switch */
73444723
BL		 1975static const struct snd_kcontrol_new rt5663_hpo_switch =
1976 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
1977 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
df7c5216
BL		 1978
1979/* Stereo ADC source */
73444723 1980static const char * const rt5663_sto1_adc_src[] = {
df7c5216
BL		 1981 "ADC L", "ADC R"
1982};
1983
73444723
BL		 1984static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
1985 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
df7c5216 1986
73444723
BL		 1987static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
1988 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
df7c5216 1989
73444723
BL		 1990static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
1991 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
df7c5216 1992
73444723
BL		 1993static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
1994 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
df7c5216
BL		 1995
1996/* RT5663: Analog DACL1 input source */
1997static const char * const rt5663_alg_dacl_src[] = {
1998 "DAC L", "STO DAC MIXL"
1999};
2000
2001static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2002 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2003
2004static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2005 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2006
2007/* RT5663: Analog DACR1 input source */
2008static const char * const rt5663_alg_dacr_src[] = {
2009 "DAC R", "STO DAC MIXR"
2010};
2011
2012static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2013 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2014
2015static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2016 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2017
2018static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2019 struct snd_kcontrol *kcontrol, int event)
2020{
2021 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2022 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2023
2024 switch (event) {
2025 case SND_SOC_DAPM_POST_PMU:
73444723 2026 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 2027 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
73444723 2028 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
df7c5216 2029 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
73444723
BL		 2030 RT5663_HP_SIG_SRC1_MASK,
2031 RT5663_HP_SIG_SRC1_SILENCE);
df7c5216
BL		 2032 } else {
2033 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
df7c5216 2034 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
73444723 2035 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
df7c5216
BL		 2036 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2037 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
2038 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
2039 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766);
2040 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
2041 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
2042 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000,
2043 0x3000);
2044 }
2045 break;
2046
2047 case SND_SOC_DAPM_PRE_PMD:
73444723 2048 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 2049 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
73444723
BL		 2050 RT5663_HP_SIG_SRC1_MASK,
2051 RT5663_HP_SIG_SRC1_REG);
df7c5216
BL		 2052 } else {
2053 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
2054 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
73444723 2055 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
df7c5216
BL		 2056 }
2057 break;
2058
2059 default:
2060 return 0;
2061 }
2062
2063 return 0;
2064}
2065
1325734c 2066static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2067 struct snd_kcontrol *kcontrol, int event)
2068{
2069 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2070 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2071
2072 switch (event) {
2073 case SND_SOC_DAPM_PRE_PMU:
2074 if (rt5663->codec_ver == CODEC_VER_0)
2075 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x003b,
2076 0x003b);
2077 break;
2078
2079 case SND_SOC_DAPM_POST_PMD:
2080 if (rt5663->codec_ver == CODEC_VER_0)
2081 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x003b, 0);
2082 break;
2083
2084 default:
2085 return 0;
2086 }
2087
2088 return 0;
2089}
2090
73444723 2091static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
df7c5216
BL		 2092 struct snd_kcontrol *kcontrol, int event)
2093{
2094 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2095
2096 switch (event) {
2097 case SND_SOC_DAPM_POST_PMU:
2098 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
73444723
BL		 2099 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2100 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
df7c5216
BL		 2101 break;
2102
2103 case SND_SOC_DAPM_PRE_PMD:
2104 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
73444723 2105 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
df7c5216
BL		 2106 break;
2107
2108 default:
2109 return 0;
2110 }
2111
2112 return 0;
2113}
2114
2115static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2116 struct snd_kcontrol *kcontrol, int event)
2117{
2118 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2119
2120 switch (event) {
2121 case SND_SOC_DAPM_POST_PMU:
2122 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
2123 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
2124 break;
2125
2126 case SND_SOC_DAPM_PRE_PMD:
2127 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000);
2128 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000);
2129 break;
2130
2131 default:
2132 return 0;
2133 }
2134
2135 return 0;
2136}
2137
2138static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
73444723 2139 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
df7c5216
BL		 2140 NULL, 0),
2141
2142 /* micbias */
2143 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
73444723 2144 RT5663_PWR_MB1_SHIFT, 0),
df7c5216 2145 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
73444723 2146 RT5663_PWR_MB2_SHIFT, 0),
df7c5216
BL		 2147
2148 /* Input Lines */
2149 SND_SOC_DAPM_INPUT("IN1P"),
2150 SND_SOC_DAPM_INPUT("IN1N"),
2151
2152 /* REC Mixer Power */
2153 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
73444723 2154 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
df7c5216
BL		 2155
2156 /* ADCs */
2157 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2158 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
73444723 2159 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
df7c5216 2160 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
73444723 2161 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
df7c5216
BL		 2162
2163 /* ADC Mixer */
2164 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2165 0, 0, rt5663_sto1_adc_l_mix,
2166 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2167
2168 /* ADC Filter Power */
2169 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
73444723 2170 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
df7c5216
BL		 2171
2172 /* Digital Interface */
73444723 2173 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
df7c5216
BL		 2174 NULL, 0),
2175 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2176 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2177 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2178 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2179 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2180
2181 /* Audio Interface */
2182 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2183 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2184
2185 /* DAC mixer before sound effect */
2186 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2187 ARRAY_SIZE(rt5663_adda_l_mix)),
2188 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2189 ARRAY_SIZE(rt5663_adda_r_mix)),
2190 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2191 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2192
2193 /* DAC Mixer */
2194 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
73444723 2195 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
df7c5216
BL		 2196 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2197 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2198 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2199 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2200
2201 /* DACs */
2202 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
73444723 2203 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
df7c5216 2204 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
73444723 2205 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
df7c5216
BL		 2206 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2207 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2208
2209 /* Headphone*/
1325734c 2210 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2211 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2212 SND_SOC_DAPM_POST_PMD),
df7c5216
BL		 2213 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2214 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2215
2216 /* Output Lines */
2217 SND_SOC_DAPM_OUTPUT("HPOL"),
2218 SND_SOC_DAPM_OUTPUT("HPOR"),
2219};
2220
73444723 2221static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
df7c5216 2222 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
73444723
BL		 2223 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2224 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2225 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
df7c5216 2226 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
73444723 2227 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
df7c5216
BL		 2228
2229 /* ASRC */
2230 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
73444723 2231 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
df7c5216 2232 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
73444723 2233 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
df7c5216 2234 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
73444723 2235 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
df7c5216
BL		 2236
2237 /* Input Lines */
2238 SND_SOC_DAPM_INPUT("IN2P"),
2239 SND_SOC_DAPM_INPUT("IN2N"),
2240
2241 /* Boost */
2242 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2243 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
73444723 2244 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
df7c5216
BL		 2245 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2246 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
73444723 2247 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
df7c5216
BL		 2248 SND_SOC_DAPM_POST_PMU),
2249
2250 /* REC Mixer */
73444723
BL		 2251 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2252 ARRAY_SIZE(rt5663_recmix1l)),
2253 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2254 ARRAY_SIZE(rt5663_recmix1r)),
df7c5216 2255 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
73444723 2256 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
df7c5216
BL		 2257
2258 /* ADC */
2259 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2260 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
73444723 2261 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
df7c5216
BL		 2262
2263 /* ADC Mux */
2264 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
73444723 2265 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
df7c5216 2266 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
73444723 2267 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
df7c5216 2268 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
73444723 2269 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
df7c5216 2270 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
73444723 2271 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
df7c5216
BL		 2272
2273 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
73444723 2274 &rt5663_sto1_adcl_mux),
df7c5216 2275 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
73444723 2276 &rt5663_sto1_adcr_mux),
df7c5216
BL		 2277
2278 /* ADC Mix */
2279 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
73444723 2280 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
df7c5216
BL		 2281
2282 /* Analog DAC Clock */
2283 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
73444723 2284 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
df7c5216
BL		 2285
2286 /* Headphone out */
2287 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
73444723 2288 &rt5663_hpo_switch),
df7c5216
BL		 2289};
2290
2291static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2292 /* System Clock Pre Divider Gating */
2293 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2294 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2295 SND_SOC_DAPM_PRE_PMD),
2296
2297 /* LDO */
2298 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
73444723 2299 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
df7c5216
BL		 2300
2301 /* ASRC */
2302 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2303 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2304 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2305 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2306 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2307 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2308
2309 /* Boost */
2310 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2311
2312 /* STO ADC */
2313 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2314 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2315
2316 /* Analog DAC source */
2317 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2318 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2319};
2320
2321static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2322 /* PLL */
2323 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2324
2325 /* ASRC */
2326 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2327 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2328 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2329
2330 { "ADC L", NULL, "ADC L Power" },
2331 { "ADC L", NULL, "ADC Clock" },
2332
2333 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2334
2335 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2336 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2337 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2338
2339 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2340 { "IF ADC", NULL, "IF1 ADC1" },
2341 { "AIFTX", NULL, "IF ADC" },
2342 { "AIFTX", NULL, "I2S" },
2343
2344 { "AIFRX", NULL, "I2S" },
2345 { "IF DAC", NULL, "AIFRX" },
2346 { "IF1 DAC1 L", NULL, "IF DAC" },
2347 { "IF1 DAC1 R", NULL, "IF DAC" },
2348
2349 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2350 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2351 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2352 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2353 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2354 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2355 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2356
2357 { "DAC L1", NULL, "ADDA MIXL" },
2358 { "DAC R1", NULL, "ADDA MIXR" },
2359
2360 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
df7c5216
BL		 2361 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2362 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2363 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
df7c5216
BL		 2364 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2365 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2366
1325734c 2367 { "HP Amp", NULL, "HP Charge Pump" },
df7c5216
BL		 2368 { "HP Amp", NULL, "DAC L" },
2369 { "HP Amp", NULL, "DAC R" },
2370};
2371
73444723 2372static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
df7c5216
BL		 2373 { "MICBIAS1", NULL, "LDO2" },
2374 { "MICBIAS2", NULL, "LDO2" },
2375
2376 { "BST1 CBJ", NULL, "IN1P" },
2377 { "BST1 CBJ", NULL, "IN1N" },
2378 { "BST1 CBJ", NULL, "CBJ Power" },
2379
2380 { "BST2", NULL, "IN2P" },
2381 { "BST2", NULL, "IN2N" },
2382 { "BST2", NULL, "BST2 Power" },
2383
2384 { "RECMIX1L", "BST2 Switch", "BST2" },
2385 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2386 { "RECMIX1L", NULL, "RECMIX1L Power" },
2387 { "RECMIX1R", "BST2 Switch", "BST2" },
2388 { "RECMIX1R", NULL, "RECMIX1R Power" },
2389
2390 { "ADC L", NULL, "RECMIX1L" },
2391 { "ADC R", NULL, "RECMIX1R" },
2392 { "ADC R", NULL, "ADC R Power" },
2393 { "ADC R", NULL, "ADC Clock" },
2394
2395 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2396 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2397 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2398
2399 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2400 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2401 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2402 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2403
2404 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2405 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2406 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2407
2408 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2409
2410 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2411
2412 { "DAC L", NULL, "STO1 DAC MIXL" },
2413 { "DAC L", NULL, "LDO DAC" },
2414 { "DAC L", NULL, "DAC Clock" },
2415 { "DAC R", NULL, "STO1 DAC MIXR" },
2416 { "DAC R", NULL, "LDO DAC" },
2417 { "DAC R", NULL, "DAC Clock" },
2418
2419 { "HPO Playback", "Switch", "HP Amp" },
2420 { "HPOL", NULL, "HPO Playback" },
2421 { "HPOR", NULL, "HPO Playback" },
2422};
2423
2424static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2425 { "I2S", NULL, "Pre Div Power" },
2426
2427 { "BST1", NULL, "IN1P" },
2428 { "BST1", NULL, "IN1N" },
2429 { "BST1", NULL, "RECMIX1L Power" },
2430
2431 { "ADC L", NULL, "BST1" },
2432
2433 { "STO1 ADC L1", NULL, "ADC L" },
2434
2435 { "DAC L Mux", "DAC L", "DAC L1" },
2436 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2437 { "DAC R Mux", "DAC R", "DAC R1"},
2438 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2439
2440 { "DAC L", NULL, "DAC L Mux" },
2441 { "DAC R", NULL, "DAC R Mux" },
2442
2443 { "HPOL", NULL, "HP Amp" },
2444 { "HPOR", NULL, "HP Amp" },
2445};
2446
2447static int rt5663_hw_params(struct snd_pcm_substream *substream,
2448 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2449{
2450 struct snd_soc_codec *codec = dai->codec;
2451 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2452 unsigned int val_len = 0;
2453 int pre_div;
2454
2455 rt5663->lrck = params_rate(params);
2456
2457 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2458 rt5663->lrck, rt5663->sysclk);
2459
2460 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2461 if (pre_div < 0) {
2462 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2463 rt5663->lrck, dai->id);
2464 return -EINVAL;
2465 }
2466
2467 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2468
2469 switch (params_width(params)) {
2470 case 8:
73444723 2471 val_len = RT5663_I2S_DL_8;
df7c5216
BL		 2472 break;
2473 case 16:
73444723 2474 val_len = RT5663_I2S_DL_16;
df7c5216
BL		 2475 break;
2476 case 20:
73444723 2477 val_len = RT5663_I2S_DL_20;
df7c5216
BL		 2478 break;
2479 case 24:
73444723 2480 val_len = RT5663_I2S_DL_24;
df7c5216
BL		 2481 break;
2482 default:
2483 return -EINVAL;
2484 }
2485
2486 snd_soc_update_bits(codec, RT5663_I2S1_SDP,
73444723 2487 RT5663_I2S_DL_MASK, val_len);
df7c5216
BL		 2488
2489 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
73444723 2490 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
df7c5216
BL		 2491
2492 return 0;
2493}
2494
2495static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2496{
2497 struct snd_soc_codec *codec = dai->codec;
2498 unsigned int reg_val = 0;
2499
2500 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2501 case SND_SOC_DAIFMT_CBM_CFM:
2502 break;
2503 case SND_SOC_DAIFMT_CBS_CFS:
73444723 2504 reg_val |= RT5663_I2S_MS_S;
df7c5216
BL		 2505 break;
2506 default:
2507 return -EINVAL;
2508 }
2509
2510 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2511 case SND_SOC_DAIFMT_NB_NF:
2512 break;
2513 case SND_SOC_DAIFMT_IB_NF:
73444723 2514 reg_val |= RT5663_I2S_BP_INV;
df7c5216
BL		 2515 break;
2516 default:
2517 return -EINVAL;
2518 }
2519
2520 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2521 case SND_SOC_DAIFMT_I2S:
2522 break;
2523 case SND_SOC_DAIFMT_LEFT_J:
73444723 2524 reg_val |= RT5663_I2S_DF_LEFT;
df7c5216
BL		 2525 break;
2526 case SND_SOC_DAIFMT_DSP_A:
73444723 2527 reg_val |= RT5663_I2S_DF_PCM_A;
df7c5216
BL		 2528 break;
2529 case SND_SOC_DAIFMT_DSP_B:
73444723 2530 reg_val |= RT5663_I2S_DF_PCM_B;
df7c5216
BL		 2531 break;
2532 default:
2533 return -EINVAL;
2534 }
2535
73444723
BL		 2536 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2537 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
df7c5216
BL		 2538
2539 return 0;
2540}
2541
2542static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2543 unsigned int freq, int dir)
2544{
2545 struct snd_soc_codec *codec = dai->codec;
2546 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2547 unsigned int reg_val = 0;
2548
2549 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2550 return 0;
2551
2552 switch (clk_id) {
2553 case RT5663_SCLK_S_MCLK:
2554 reg_val |= RT5663_SCLK_SRC_MCLK;
2555 break;
2556 case RT5663_SCLK_S_PLL1:
2557 reg_val |= RT5663_SCLK_SRC_PLL1;
2558 break;
2559 case RT5663_SCLK_S_RCCLK:
2560 reg_val |= RT5663_SCLK_SRC_RCCLK;
2561 break;
2562 default:
2563 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2564 return -EINVAL;
2565 }
73444723 2566 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
df7c5216
BL		 2567 reg_val);
2568 rt5663->sysclk = freq;
2569 rt5663->sysclk_src = clk_id;
2570
2571 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n",
2572 freq, clk_id);
2573
2574 return 0;
2575}
2576
2577static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2578 unsigned int freq_in, unsigned int freq_out)
2579{
2580 struct snd_soc_codec *codec = dai->codec;
2581 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2582 struct rl6231_pll_code pll_code;
2583 int ret;
2584 int mask, shift, val;
2585
2586 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2587 freq_out == rt5663->pll_out)
2588 return 0;
2589
2590 if (!freq_in || !freq_out) {
2591 dev_dbg(codec->dev, "PLL disabled\n");
2592
2593 rt5663->pll_in = 0;
2594 rt5663->pll_out = 0;
2595 snd_soc_update_bits(codec, RT5663_GLB_CLK,
2596 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2597 return 0;
2598 }
2599
73444723
BL		 2600 switch (rt5663->codec_ver) {
2601 case CODEC_VER_1:
2602 mask = RT5663_V2_PLL1_SRC_MASK;
2603 shift = RT5663_V2_PLL1_SRC_SHIFT;
df7c5216 2604 break;
73444723 2605 case CODEC_VER_0:
df7c5216
BL		 2606 mask = RT5663_PLL1_SRC_MASK;
2607 shift = RT5663_PLL1_SRC_SHIFT;
2608 break;
2609 default:
73444723 2610 dev_err(codec->dev, "Unknown CODEC Version\n");
56efaed5 2611 return -EINVAL;
df7c5216
BL		 2612 }
2613
2614 switch (source) {
2615 case RT5663_PLL1_S_MCLK:
2616 val = 0x0;
2617 break;
2618 case RT5663_PLL1_S_BCLK1:
2619 val = 0x1;
2620 break;
2621 default:
2622 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2623 return -EINVAL;
2624 }
2625 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift));
2626
2627 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2628 if (ret < 0) {
2629 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2630 return ret;
2631 }
2632
2633 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2634 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2635 pll_code.k_code);
2636
2637 snd_soc_write(codec, RT5663_PLL_1,
73444723 2638 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
df7c5216 2639 snd_soc_write(codec, RT5663_PLL_2,
73444723
BL		 2640 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2641 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
df7c5216
BL		 2642
2643 rt5663->pll_in = freq_in;
2644 rt5663->pll_out = freq_out;
2645 rt5663->pll_src = source;
2646
2647 return 0;
2648}
2649
2650static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2651 unsigned int rx_mask, int slots, int slot_width)
2652{
2653 struct snd_soc_codec *codec = dai->codec;
2654 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2655 unsigned int val = 0, reg;
2656
2657 if (rx_mask || tx_mask)
73444723 2658 val |= RT5663_TDM_MODE_TDM;
df7c5216
BL		 2659
2660 switch (slots) {
2661 case 4:
73444723
BL		 2662 val |= RT5663_TDM_IN_CH_4;
2663 val |= RT5663_TDM_OUT_CH_4;
df7c5216
BL		 2664 break;
2665 case 6:
73444723
BL		 2666 val |= RT5663_TDM_IN_CH_6;
2667 val |= RT5663_TDM_OUT_CH_6;
df7c5216
BL		 2668 break;
2669 case 8:
73444723
BL		 2670 val |= RT5663_TDM_IN_CH_8;
2671 val |= RT5663_TDM_OUT_CH_8;
df7c5216
BL		 2672 break;
2673 case 2:
2674 break;
2675 default:
2676 return -EINVAL;
2677 }
2678
2679 switch (slot_width) {
2680 case 20:
73444723
BL		 2681 val |= RT5663_TDM_IN_LEN_20;
2682 val |= RT5663_TDM_OUT_LEN_20;
df7c5216
BL		 2683 break;
2684 case 24:
73444723
BL		 2685 val |= RT5663_TDM_IN_LEN_24;
2686 val |= RT5663_TDM_OUT_LEN_24;
df7c5216
BL		 2687 break;
2688 case 32:
73444723
BL		 2689 val |= RT5663_TDM_IN_LEN_32;
2690 val |= RT5663_TDM_OUT_LEN_32;
df7c5216
BL		 2691 break;
2692 case 16:
2693 break;
2694 default:
2695 return -EINVAL;
2696 }
2697
73444723
BL		 2698 switch (rt5663->codec_ver) {
2699 case CODEC_VER_1:
df7c5216
BL		 2700 reg = RT5663_TDM_2;
2701 break;
73444723 2702 case CODEC_VER_0:
df7c5216
BL		 2703 reg = RT5663_TDM_1;
2704 break;
2705 default:
73444723 2706 dev_err(codec->dev, "Unknown CODEC Version\n");
56efaed5 2707 return -EINVAL;
df7c5216
BL		 2708 }
2709
73444723
BL		 2710 snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
2711 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
2712 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
df7c5216
BL		 2713
2714 return 0;
2715}
2716
2717static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2718{
2719 struct snd_soc_codec *codec = dai->codec;
2720 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2721 unsigned int reg;
2722
2723 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
2724
73444723
BL		 2725 if (rt5663->codec_ver == CODEC_VER_1)
2726 reg = RT5663_TDM_9;
df7c5216
BL		 2727 else
2728 reg = RT5663_TDM_5;
2729
2730 switch (ratio) {
2731 case 32:
2732 snd_soc_update_bits(codec, reg,
2733 RT5663_TDM_LENGTN_MASK,
2734 RT5663_TDM_LENGTN_16);
2735 break;
2736 case 40:
2737 snd_soc_update_bits(codec, reg,
2738 RT5663_TDM_LENGTN_MASK,
2739 RT5663_TDM_LENGTN_20);
2740 break;
2741 case 48:
2742 snd_soc_update_bits(codec, reg,
2743 RT5663_TDM_LENGTN_MASK,
2744 RT5663_TDM_LENGTN_24);
2745 break;
2746 case 64:
2747 snd_soc_update_bits(codec, reg,
2748 RT5663_TDM_LENGTN_MASK,
2749 RT5663_TDM_LENGTN_32);
2750 break;
2751 default:
2752 dev_err(codec->dev, "Invalid ratio!\n");
2753 return -EINVAL;
2754 }
2755
2756 return 0;
2757}
2758
2759static int rt5663_set_bias_level(struct snd_soc_codec *codec,
2760 enum snd_soc_bias_level level)
2761{
2762 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2763
2764 switch (level) {
2765 case SND_SOC_BIAS_ON:
2766 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
73444723
BL		 2767 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
2768 RT5663_PWR_FV1 | RT5663_PWR_FV2);
df7c5216
BL		 2769 break;
2770
2771 case SND_SOC_BIAS_PREPARE:
73444723 2772 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 2773 snd_soc_update_bits(codec, RT5663_DIG_MISC,
73444723
BL		 2774 RT5663_DIG_GATE_CTRL_MASK,
2775 RT5663_DIG_GATE_CTRL_EN);
df7c5216 2776 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
73444723
BL		 2777 RT5663_EN_ANA_CLK_DET_MASK |
2778 RT5663_PWR_CLK_DET_MASK,
2779 RT5663_EN_ANA_CLK_DET_AUTO |
2780 RT5663_PWR_CLK_DET_EN);
df7c5216
BL		 2781 }
2782 break;
2783
2784 case SND_SOC_BIAS_STANDBY:
73444723 2785 if (rt5663->codec_ver == CODEC_VER_1)
df7c5216 2786 snd_soc_update_bits(codec, RT5663_DIG_MISC,
73444723
BL		 2787 RT5663_DIG_GATE_CTRL_MASK,
2788 RT5663_DIG_GATE_CTRL_DIS);
df7c5216 2789 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
73444723
BL		 2790 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2791 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
2792 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
2793 RT5663_PWR_VREF2 | RT5663_PWR_MB);
df7c5216 2794 usleep_range(10000, 10005);
73444723 2795 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 2796 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
73444723
BL		 2797 RT5663_EN_ANA_CLK_DET_MASK |
2798 RT5663_PWR_CLK_DET_MASK,
2799 RT5663_EN_ANA_CLK_DET_DIS |
2800 RT5663_PWR_CLK_DET_DIS);
df7c5216
BL		 2801 }
2802 break;
2803
2804 case SND_SOC_BIAS_OFF:
2805 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
73444723
BL		 2806 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2807 RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
df7c5216
BL		 2808 break;
2809
2810 default:
2811 break;
2812 }
2813
2814 return 0;
2815}
2816
2817static int rt5663_probe(struct snd_soc_codec *codec)
2818{
2819 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2820 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2821
2822 rt5663->codec = codec;
2823
73444723
BL		 2824 switch (rt5663->codec_ver) {
2825 case CODEC_VER_1:
df7c5216 2826 snd_soc_dapm_new_controls(dapm,
73444723
BL		 2827 rt5663_v2_specific_dapm_widgets,
2828 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
df7c5216 2829 snd_soc_dapm_add_routes(dapm,
73444723
BL		 2830 rt5663_v2_specific_dapm_routes,
2831 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
2832 snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
2833 ARRAY_SIZE(rt5663_v2_specific_controls));
df7c5216 2834 break;
73444723 2835 case CODEC_VER_0:
df7c5216
BL		 2836 snd_soc_dapm_new_controls(dapm,
2837 rt5663_specific_dapm_widgets,
2838 ARRAY_SIZE(rt5663_specific_dapm_widgets));
2839 snd_soc_dapm_add_routes(dapm,
2840 rt5663_specific_dapm_routes,
2841 ARRAY_SIZE(rt5663_specific_dapm_routes));
2842 snd_soc_add_codec_controls(codec, rt5663_specific_controls,
2843 ARRAY_SIZE(rt5663_specific_controls));
2844 break;
2845 }
2846
2847 return 0;
2848}
2849
2850static int rt5663_remove(struct snd_soc_codec *codec)
2851{
2852 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2853
2854 regmap_write(rt5663->regmap, RT5663_RESET, 0);
2855
2856 return 0;
2857}
2858
2859#ifdef CONFIG_PM
2860static int rt5663_suspend(struct snd_soc_codec *codec)
2861{
2862 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2863
2864 regcache_cache_only(rt5663->regmap, true);
2865 regcache_mark_dirty(rt5663->regmap);
2866
2867 return 0;
2868}
2869
2870static int rt5663_resume(struct snd_soc_codec *codec)
2871{
2872 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2873
2874 regcache_cache_only(rt5663->regmap, false);
2875 regcache_sync(rt5663->regmap);
2876
17616ce6
OC		 2877 rt5663_irq(0, rt5663);
2878
df7c5216
BL		 2879 return 0;
2880}
2881#else
2882#define rt5663_suspend NULL
2883#define rt5663_resume NULL
2884#endif
2885
2886#define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2887#define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2888 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2889
6ccf3a6d 2890static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
df7c5216
BL		 2891 .hw_params = rt5663_hw_params,
2892 .set_fmt = rt5663_set_dai_fmt,
2893 .set_sysclk = rt5663_set_dai_sysclk,
2894 .set_pll = rt5663_set_dai_pll,
2895 .set_tdm_slot = rt5663_set_tdm_slot,
2896 .set_bclk_ratio = rt5663_set_bclk_ratio,
2897};
2898
66d7c262 2899static struct snd_soc_dai_driver rt5663_dai[] = {
df7c5216
BL		 2900 {
2901 .name = "rt5663-aif",
2902 .id = RT5663_AIF,
2903 .playback = {
2904 .stream_name = "AIF Playback",
2905 .channels_min = 1,
2906 .channels_max = 2,
2907 .rates = RT5663_STEREO_RATES,
2908 .formats = RT5663_FORMATS,
2909 },
2910 .capture = {
2911 .stream_name = "AIF Capture",
2912 .channels_min = 1,
2913 .channels_max = 2,
2914 .rates = RT5663_STEREO_RATES,
2915 .formats = RT5663_FORMATS,
2916 },
2917 .ops = &rt5663_aif_dai_ops,
2918 },
2919};
2920
2921static struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
2922 .probe = rt5663_probe,
2923 .remove = rt5663_remove,
2924 .suspend = rt5663_suspend,
2925 .resume = rt5663_resume,
2926 .set_bias_level = rt5663_set_bias_level,
2927 .idle_bias_off = true,
2928 .component_driver = {
2929 .controls = rt5663_snd_controls,
2930 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
2931 .dapm_widgets = rt5663_dapm_widgets,
2932 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
2933 .dapm_routes = rt5663_dapm_routes,
2934 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
2935 }
2936};
2937
73444723 2938static const struct regmap_config rt5663_v2_regmap = {
df7c5216
BL		 2939 .reg_bits = 16,
2940 .val_bits = 16,
2941 .use_single_rw = true,
2942 .max_register = 0x07fa,
73444723
BL		 2943 .volatile_reg = rt5663_v2_volatile_register,
2944 .readable_reg = rt5663_v2_readable_register,
df7c5216 2945 .cache_type = REGCACHE_RBTREE,
73444723
BL		 2946 .reg_defaults = rt5663_v2_reg,
2947 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
df7c5216
BL		 2948};
2949
2950static const struct regmap_config rt5663_regmap = {
2951 .reg_bits = 16,
2952 .val_bits = 16,
2953 .use_single_rw = true,
2954 .max_register = 0x03f3,
2955 .volatile_reg = rt5663_volatile_register,
2956 .readable_reg = rt5663_readable_register,
2957 .cache_type = REGCACHE_RBTREE,
2958 .reg_defaults = rt5663_reg,
2959 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
2960};
2961
2962static const struct regmap_config temp_regmap = {
2963 .name = "nocache",
2964 .reg_bits = 16,
2965 .val_bits = 16,
2966 .use_single_rw = true,
2967 .max_register = 0x03f3,
2968 .cache_type = REGCACHE_NONE,
2969};
2970
2971static const struct i2c_device_id rt5663_i2c_id[] = {
df7c5216
BL		 2972 { "rt5663", 0 },
2973 {}
2974};
2975MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
2976
2977#if defined(CONFIG_OF)
2978static const struct of_device_id rt5663_of_match[] = {
df7c5216
BL		 2979 { .compatible = "realtek,rt5663", },
2980 {},
2981};
2982MODULE_DEVICE_TABLE(of, rt5663_of_match);
2983#endif
2984
2985#ifdef CONFIG_ACPI
2986static struct acpi_device_id rt5663_acpi_match[] = {
df7c5216
BL		 2987 { "10EC5663", 0},
2988 {},
2989};
2990MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
2991#endif
2992
73444723 2993static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
df7c5216 2994{
73444723
BL		 2995 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
2996 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
2997 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
2998 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
2999 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3000 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3001 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3002 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3003 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3004 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
df7c5216 3005 msleep(40);
73444723
BL		 3006 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3007 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3008 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
df7c5216
BL		 3009 msleep(500);
3010}
3011
73444723 3012static void rt5663_calibrate(struct rt5663_priv *rt5663)
df7c5216
BL		 3013{
3014 int value, count;
3015
7d8e00c7 3016 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3017 msleep(20);
3018 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3019 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
73444723 3020 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
7d8e00c7 3021 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
73444723 3022 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
7d8e00c7 3023 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3024 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3025 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3026 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3027 msleep(30);
3028 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3029 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3030 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
73444723
BL		 3031 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3032 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
7d8e00c7 3033 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3034 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3035 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3036 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3037 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3038
3039 count = 0;
3040 while (true) {
3041 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3042 if (!(value & 0x80))
3043 usleep_range(10000, 10005);
3044 else
3045 break;
3046
09b8852c 3047 if (++count > 200)
7d8e00c7 3048 break;
3049 }
3050
3051 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
73444723 3052 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
7d8e00c7 3053 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
73444723 3054 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
7d8e00c7 3055 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3056 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3057 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3058 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
73444723 3059 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
73444723 3060 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
7d8e00c7 3061 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
73444723 3062 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
7d8e00c7 3063 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
73444723
BL		 3064 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3065 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3066 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3067 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3068 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
7d8e00c7 3069 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
73444723
BL		 3070 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3071 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3072 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3073 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3074 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
7d8e00c7 3075 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3076 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3077 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
73444723 3078 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
7d8e00c7 3079 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3080 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3081 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3082 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3083 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3084
df7c5216
BL		 3085 count = 0;
3086 while (true) {
73444723 3087 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
df7c5216
BL		 3088 if (value & 0x8000)
3089 usleep_range(10000, 10005);
3090 else
3091 break;
3092
3093 if (count > 200)
3094 return;
3095 count++;
3096 }
7d8e00c7 3097
3098 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3099 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3100 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3101
3102 count = 0;
3103 while (true) {
3104 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3105 if (value & 0x8000)
3106 usleep_range(10000, 10005);
3107 else
3108 break;
3109
3110 if (count > 200)
3111 return;
3112 count++;
3113 }
3114
3115 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3116 usleep_range(10000, 10005);
3117 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3118 usleep_range(10000, 10005);
3119 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3120 usleep_range(10000, 10005);
3121 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3122 usleep_range(10000, 10005);
3123 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3124 usleep_range(10000, 10005);
3125 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3126 usleep_range(10000, 10005);
df7c5216
BL		 3127}
3128
450f0f6a 3129static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3130{
3131 device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3132 &rt5663->pdata.dc_offset_l_manual);
3133 device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3134 &rt5663->pdata.dc_offset_r_manual);
3135
3136 return 0;
3137}
3138
df7c5216
BL		 3139static int rt5663_i2c_probe(struct i2c_client *i2c,
3140 const struct i2c_device_id *id)
3141{
450f0f6a 3142 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
df7c5216
BL		 3143 struct rt5663_priv *rt5663;
3144 int ret;
3145 unsigned int val;
3146 struct regmap *regmap;
3147
3148 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3149 GFP_KERNEL);
3150
3151 if (rt5663 == NULL)
3152 return -ENOMEM;
3153
3154 i2c_set_clientdata(i2c, rt5663);
3155
450f0f6a 3156 if (pdata)
3157 rt5663->pdata = *pdata;
3158 else
3159 rt5663_parse_dp(rt5663, &i2c->dev);
3160
df7c5216
BL		 3161 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3162 if (IS_ERR(regmap)) {
3163 ret = PTR_ERR(regmap);
3164 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3165 ret);
3166 return ret;
3167 }
3168 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3169 switch (val) {
73444723
BL		 3170 case RT5663_DEVICE_ID_2:
3171 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3172 rt5663->codec_ver = CODEC_VER_1;
df7c5216 3173 break;
73444723 3174 case RT5663_DEVICE_ID_1:
df7c5216 3175 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
73444723 3176 rt5663->codec_ver = CODEC_VER_0;
df7c5216
BL		 3177 break;
3178 default:
3179 dev_err(&i2c->dev,
73444723 3180 "Device with ID register %#x is not rt5663\n",
df7c5216
BL		 3181 val);
3182 return -ENODEV;
3183 }
3184
3185 if (IS_ERR(rt5663->regmap)) {
3186 ret = PTR_ERR(rt5663->regmap);
3187 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3188 ret);
3189 return ret;
3190 }
3191
3192 /* reset and calibrate */
3193 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3194 regcache_cache_bypass(rt5663->regmap, true);
73444723
BL		 3195 switch (rt5663->codec_ver) {
3196 case CODEC_VER_1:
3197 rt5663_v2_calibrate(rt5663);
df7c5216 3198 break;
73444723 3199 case CODEC_VER_0:
df7c5216
BL		 3200 rt5663_calibrate(rt5663);
3201 break;
3202 default:
3203 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3204 }
3205 regcache_cache_bypass(rt5663->regmap, false);
3206 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3207 dev_dbg(&i2c->dev, "calibrate done\n");
3208
450f0f6a 3209 switch (rt5663->codec_ver) {
3210 case CODEC_VER_1:
3211 break;
3212 case CODEC_VER_0:
3213 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3214 ARRAY_SIZE(rt5663_patch_list));
3215 if (ret != 0)
3216 dev_warn(&i2c->dev,
3217 "Failed to apply regmap patch: %d\n", ret);
3218 break;
3219 default:
3220 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3221 }
3222
3223 if (rt5663->pdata.dc_offset_l_manual) {
3224 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
3225 rt5663->pdata.dc_offset_l_manual >> 16);
3226 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
3227 rt5663->pdata.dc_offset_l_manual & 0xffff);
3228 }
3229
3230 if (rt5663->pdata.dc_offset_r_manual) {
3231 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
3232 rt5663->pdata.dc_offset_r_manual >> 16);
3233 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
3234 rt5663->pdata.dc_offset_r_manual & 0xffff);
3235 }
3236
df7c5216 3237 /* GPIO1 as IRQ */
73444723
BL		 3238 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3239 RT5663_GP1_PIN_IRQ);
df7c5216
BL		 3240 /* 4btn inline command debounce */
3241 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
73444723 3242 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
df7c5216 3243
73444723
BL		 3244 switch (rt5663->codec_ver) {
3245 case CODEC_VER_1:
df7c5216
BL		 3246 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3247 /* JD1 */
3248 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
73444723
BL		 3249 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3250 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
df7c5216 3251 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
73444723 3252 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
df7c5216 3253 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
73444723 3254 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
df7c5216
BL		 3255
3256 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
73444723 3257 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
df7c5216 3258 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
73444723
BL		 3259 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3260 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3261 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
df7c5216
BL		 3262 /* Set GPIO4 and GPIO8 as input for combo jack */
3263 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
73444723
BL		 3264 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3265 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3266 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
df7c5216 3267 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
73444723
BL		 3268 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3269 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
df7c5216 3270 break;
73444723 3271 case CODEC_VER_0:
7e7e76bd 3272 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
73444723 3273 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
7e7e76bd 3274 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
af2728e4 3275 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
7e7e76bd
JY		 3276 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3277 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3278 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3279 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
df7c5216
BL		 3280 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3281 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
3282 msleep(20);
3283 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
3284 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
7e7e76bd
JY		 3285 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3286 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
df7c5216
BL		 3287 /* DACREF LDO control */
3288 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
3289 0x3a0a);
3290 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3291 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3292 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3293 RT5663_DATA_SWAP_ADCDAT1_MASK,
3294 RT5663_DATA_SWAP_ADCDAT1_LL);
3295 break;
3296 default:
3297 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3298 }
3299
3300 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3301
3302 if (i2c->irq) {
3303 ret = request_irq(i2c->irq, rt5663_irq,
3304 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3305 | IRQF_ONESHOT, "rt5663", rt5663);
3306 if (ret)
3307 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3308 __func__, ret);
3309 }
3310
3311 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663,
3312 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3313
3314 if (ret) {
3315 if (i2c->irq)
3316 free_irq(i2c->irq, rt5663);
3317 }
3318
3319 return ret;
3320}
3321
3322static int rt5663_i2c_remove(struct i2c_client *i2c)
3323{
3324 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3325
3326 if (i2c->irq)
3327 free_irq(i2c->irq, rt5663);
3328
3329 snd_soc_unregister_codec(&i2c->dev);
3330
3331 return 0;
3332}
3333
66d7c262 3334static void rt5663_i2c_shutdown(struct i2c_client *client)
df7c5216
BL		 3335{
3336 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3337
3338 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3339}
3340
66d7c262 3341static struct i2c_driver rt5663_i2c_driver = {
df7c5216
BL		 3342 .driver = {
3343 .name = "rt5663",
df7c5216
BL		 3344 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3345 .of_match_table = of_match_ptr(rt5663_of_match),
3346 },
3347 .probe = rt5663_i2c_probe,
3348 .remove = rt5663_i2c_remove,
3349 .shutdown = rt5663_i2c_shutdown,
3350 .id_table = rt5663_i2c_id,
3351};
3352module_i2c_driver(rt5663_i2c_driver);
3353
3354MODULE_DESCRIPTION("ASoC RT5663 driver");
3355MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3356MODULE_LICENSE("GPL v2");
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