projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| df7c5216 BL |
1 | /* |
| 2 | * rt5663.h -- RT5663 ALSA SoC audio driver | |
| 3 | * | |
| 4 | * Copyright 2016 Realtek Microelectronics | |
| 5 | * Author: Jack Yu <jack.yu@realtek.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __RT5663_H__ | |
| 13 | #define __RT5663_H__ | |
| 14 | ||
| 450f0f6a | 15 | #include <sound/rt5663.h> |
| 16 | ||
| df7c5216 BL |
17 | /* Info */ |
| 18 | #define RT5663_RESET 0x0000 | |
| 19 | #define RT5663_VENDOR_ID 0x00fd | |
| 20 | #define RT5663_VENDOR_ID_1 0x00fe | |
| 21 | #define RT5663_VENDOR_ID_2 0x00ff | |
| 22 | ||
| 73444723 BL |
23 | #define RT5663_LOUT_CTRL 0x0001 |
| 24 | #define RT5663_HP_AMP_2 0x0003 | |
| 25 | #define RT5663_MONO_OUT 0x0004 | |
| 26 | #define RT5663_MONO_GAIN 0x0007 | |
| 27 | ||
| 28 | #define RT5663_AEC_BST 0x000b | |
| 29 | #define RT5663_IN1_IN2 0x000c | |
| 30 | #define RT5663_IN3_IN4 0x000d | |
| 31 | #define RT5663_INL1_INR1 0x000f | |
| 32 | #define RT5663_CBJ_TYPE_2 0x0011 | |
| 33 | #define RT5663_CBJ_TYPE_3 0x0012 | |
| 34 | #define RT5663_CBJ_TYPE_4 0x0013 | |
| 35 | #define RT5663_CBJ_TYPE_5 0x0014 | |
| 36 | #define RT5663_CBJ_TYPE_8 0x0017 | |
| df7c5216 BL |
37 | |
| 38 | /* I/O - ADC/DAC/DMIC */ | |
| 73444723 BL |
39 | #define RT5663_DAC3_DIG_VOL 0x001a |
| 40 | #define RT5663_DAC3_CTRL 0x001b | |
| 41 | #define RT5663_MONO_ADC_DIG_VOL 0x001d | |
| 42 | #define RT5663_STO2_ADC_DIG_VOL 0x001e | |
| 43 | #define RT5663_MONO_ADC_BST_GAIN 0x0020 | |
| 44 | #define RT5663_STO2_ADC_BST_GAIN 0x0021 | |
| 45 | #define RT5663_SIDETONE_CTRL 0x0024 | |
| df7c5216 | 46 | /* Mixer - D-D */ |
| 73444723 BL |
47 | #define RT5663_MONO1_ADC_MIXER 0x0027 |
| 48 | #define RT5663_STO2_ADC_MIXER 0x0028 | |
| 49 | #define RT5663_MONO_DAC_MIXER 0x002b | |
| 50 | #define RT5663_DAC2_SRC_CTRL 0x002e | |
| 51 | #define RT5663_IF_3_4_DATA_CTL 0x002f | |
| 52 | #define RT5663_IF_5_DATA_CTL 0x0030 | |
| 53 | #define RT5663_PDM_OUT_CTL 0x0031 | |
| 54 | #define RT5663_PDM_I2C_DATA_CTL1 0x0032 | |
| 55 | #define RT5663_PDM_I2C_DATA_CTL2 0x0033 | |
| 56 | #define RT5663_PDM_I2C_DATA_CTL3 0x0034 | |
| 57 | #define RT5663_PDM_I2C_DATA_CTL4 0x0035 | |
| df7c5216 BL |
58 | |
| 59 | /*Mixer - Analog*/ | |
| 73444723 BL |
60 | #define RT5663_RECMIX1_NEW 0x003a |
| 61 | #define RT5663_RECMIX1L_0 0x003b | |
| 62 | #define RT5663_RECMIX1L 0x003c | |
| 63 | #define RT5663_RECMIX1R_0 0x003d | |
| 64 | #define RT5663_RECMIX1R 0x003e | |
| 65 | #define RT5663_RECMIX2_NEW 0x003f | |
| 66 | #define RT5663_RECMIX2_L_2 0x0041 | |
| 67 | #define RT5663_RECMIX2_R 0x0042 | |
| 68 | #define RT5663_RECMIX2_R_2 0x0043 | |
| 69 | #define RT5663_CALIB_REC_LR 0x0044 | |
| 70 | #define RT5663_ALC_BK_GAIN 0x0049 | |
| 71 | #define RT5663_MONOMIX_GAIN 0x004a | |
| 72 | #define RT5663_MONOMIX_IN_GAIN 0x004b | |
| 73 | #define RT5663_OUT_MIXL_GAIN 0x004d | |
| 74 | #define RT5663_OUT_LMIX_IN_GAIN 0x004e | |
| 75 | #define RT5663_OUT_RMIX_IN_GAIN 0x004f | |
| 76 | #define RT5663_OUT_RMIX_IN_GAIN1 0x0050 | |
| 77 | #define RT5663_LOUT_MIXER_CTRL 0x0052 | |
| df7c5216 | 78 | /* Power */ |
| 73444723 | 79 | #define RT5663_PWR_VOL 0x0067 |
| df7c5216 | 80 | |
| 73444723 | 81 | #define RT5663_ADCDAC_RST 0x006d |
| df7c5216 | 82 | /* Format - ADC/DAC */ |
| 73444723 BL |
83 | #define RT5663_I2S34_SDP 0x0071 |
| 84 | #define RT5663_I2S5_SDP 0x0072 | |
| df7c5216 BL |
85 | |
| 86 | /* Function - Analog */ | |
| 73444723 BL |
87 | #define RT5663_ASRC_3 0x0085 |
| 88 | #define RT5663_ASRC_6 0x0088 | |
| 89 | #define RT5663_ASRC_7 0x0089 | |
| 90 | #define RT5663_PLL_TRK_13 0x0099 | |
| 91 | #define RT5663_I2S_M_CLK_CTL 0x00a0 | |
| 92 | #define RT5663_FDIV_I2S34_M_CLK 0x00a1 | |
| 93 | #define RT5663_FDIV_I2S34_M_CLK2 0x00a2 | |
| 94 | #define RT5663_FDIV_I2S5_M_CLK 0x00a3 | |
| 95 | #define RT5663_FDIV_I2S5_M_CLK2 0x00a4 | |
| df7c5216 BL |
96 | |
| 97 | /* Function - Digital */ | |
| 73444723 BL |
98 | #define RT5663_V2_IRQ_4 0x00b9 |
| 99 | #define RT5663_GPIO_3 0x00c2 | |
| 100 | #define RT5663_GPIO_4 0x00c3 | |
| 101 | #define RT5663_GPIO_STA2 0x00c4 | |
| 102 | #define RT5663_HP_AMP_DET1 0x00d0 | |
| 103 | #define RT5663_HP_AMP_DET2 0x00d1 | |
| 104 | #define RT5663_HP_AMP_DET3 0x00d2 | |
| 105 | #define RT5663_MID_BD_HP_AMP 0x00d3 | |
| 106 | #define RT5663_LOW_BD_HP_AMP 0x00d4 | |
| 107 | #define RT5663_SOF_VOL_ZC2 0x00da | |
| 108 | #define RT5663_ADC_STO2_ADJ1 0x00ee | |
| 109 | #define RT5663_ADC_STO2_ADJ2 0x00ef | |
| df7c5216 | 110 | /* General Control */ |
| 73444723 BL |
111 | #define RT5663_A_JD_CTRL 0x00f0 |
| 112 | #define RT5663_JD1_TRES_CTRL 0x00f1 | |
| 113 | #define RT5663_JD2_TRES_CTRL 0x00f2 | |
| 114 | #define RT5663_V2_JD_CTRL2 0x00f7 | |
| 115 | #define RT5663_DUM_REG_2 0x00fb | |
| 116 | #define RT5663_DUM_REG_3 0x00fc | |
| 117 | ||
| 118 | ||
| 119 | #define RT5663_DACADC_DIG_VOL2 0x0101 | |
| 120 | #define RT5663_DIG_IN_PIN2 0x0133 | |
| 121 | #define RT5663_PAD_DRV_CTL1 0x0136 | |
| 122 | #define RT5663_SOF_RAM_DEPOP 0x0138 | |
| 123 | #define RT5663_VOL_TEST 0x013f | |
| 124 | #define RT5663_MONO_DYNA_1 0x0170 | |
| 125 | #define RT5663_MONO_DYNA_2 0x0171 | |
| 126 | #define RT5663_MONO_DYNA_3 0x0172 | |
| 127 | #define RT5663_MONO_DYNA_4 0x0173 | |
| 128 | #define RT5663_MONO_DYNA_5 0x0174 | |
| 129 | #define RT5663_MONO_DYNA_6 0x0175 | |
| 130 | #define RT5663_STO1_SIL_DET 0x0190 | |
| 131 | #define RT5663_MONOL_SIL_DET 0x0191 | |
| 132 | #define RT5663_MONOR_SIL_DET 0x0192 | |
| 133 | #define RT5663_STO2_DAC_SIL 0x0193 | |
| 134 | #define RT5663_PWR_SAV_CTL1 0x0194 | |
| 135 | #define RT5663_PWR_SAV_CTL2 0x0195 | |
| 136 | #define RT5663_PWR_SAV_CTL3 0x0196 | |
| 137 | #define RT5663_PWR_SAV_CTL4 0x0197 | |
| 138 | #define RT5663_PWR_SAV_CTL5 0x0198 | |
| 139 | #define RT5663_PWR_SAV_CTL6 0x0199 | |
| 140 | #define RT5663_MONO_AMP_CAL1 0x01a0 | |
| 141 | #define RT5663_MONO_AMP_CAL2 0x01a1 | |
| 142 | #define RT5663_MONO_AMP_CAL3 0x01a2 | |
| 143 | #define RT5663_MONO_AMP_CAL4 0x01a3 | |
| 144 | #define RT5663_MONO_AMP_CAL5 0x01a4 | |
| 145 | #define RT5663_MONO_AMP_CAL6 0x01a5 | |
| 146 | #define RT5663_MONO_AMP_CAL7 0x01a6 | |
| 147 | #define RT5663_MONO_AMP_CAL_ST1 0x01a7 | |
| 148 | #define RT5663_MONO_AMP_CAL_ST2 0x01a8 | |
| 149 | #define RT5663_MONO_AMP_CAL_ST3 0x01a9 | |
| 150 | #define RT5663_MONO_AMP_CAL_ST4 0x01aa | |
| 151 | #define RT5663_MONO_AMP_CAL_ST5 0x01ab | |
| 152 | #define RT5663_V2_HP_IMP_SEN_13 0x01b9 | |
| 153 | #define RT5663_V2_HP_IMP_SEN_14 0x01ba | |
| 154 | #define RT5663_V2_HP_IMP_SEN_6 0x01bb | |
| 155 | #define RT5663_V2_HP_IMP_SEN_7 0x01bc | |
| 156 | #define RT5663_V2_HP_IMP_SEN_8 0x01bd | |
| 157 | #define RT5663_V2_HP_IMP_SEN_9 0x01be | |
| 158 | #define RT5663_V2_HP_IMP_SEN_10 0x01bf | |
| 159 | #define RT5663_HP_LOGIC_3 0x01dc | |
| 160 | #define RT5663_HP_CALIB_ST10 0x01f3 | |
| 161 | #define RT5663_HP_CALIB_ST11 0x01f4 | |
| 162 | #define RT5663_PRO_REG_TBL_4 0x0203 | |
| 163 | #define RT5663_PRO_REG_TBL_5 0x0204 | |
| 164 | #define RT5663_PRO_REG_TBL_6 0x0205 | |
| 165 | #define RT5663_PRO_REG_TBL_7 0x0206 | |
| 166 | #define RT5663_PRO_REG_TBL_8 0x0207 | |
| 167 | #define RT5663_PRO_REG_TBL_9 0x0208 | |
| 168 | #define RT5663_SAR_ADC_INL_1 0x0210 | |
| 169 | #define RT5663_SAR_ADC_INL_2 0x0211 | |
| 170 | #define RT5663_SAR_ADC_INL_3 0x0212 | |
| 171 | #define RT5663_SAR_ADC_INL_4 0x0213 | |
| 172 | #define RT5663_SAR_ADC_INL_5 0x0214 | |
| 173 | #define RT5663_SAR_ADC_INL_6 0x0215 | |
| 174 | #define RT5663_SAR_ADC_INL_7 0x0216 | |
| 175 | #define RT5663_SAR_ADC_INL_8 0x0217 | |
| 176 | #define RT5663_SAR_ADC_INL_9 0x0218 | |
| 177 | #define RT5663_SAR_ADC_INL_10 0x0219 | |
| 178 | #define RT5663_SAR_ADC_INL_11 0x021a | |
| 179 | #define RT5663_SAR_ADC_INL_12 0x021b | |
| 180 | #define RT5663_DRC_CTRL_1 0x02ff | |
| 181 | #define RT5663_DRC1_CTRL_2 0x0301 | |
| 182 | #define RT5663_DRC1_CTRL_3 0x0302 | |
| 183 | #define RT5663_DRC1_CTRL_4 0x0303 | |
| 184 | #define RT5663_DRC1_CTRL_5 0x0304 | |
| 185 | #define RT5663_DRC1_CTRL_6 0x0305 | |
| 186 | #define RT5663_DRC1_HD_CTRL_1 0x0306 | |
| 187 | #define RT5663_DRC1_HD_CTRL_2 0x0307 | |
| 188 | #define RT5663_DRC1_PRI_REG_1 0x0310 | |
| 189 | #define RT5663_DRC1_PRI_REG_2 0x0311 | |
| 190 | #define RT5663_DRC1_PRI_REG_3 0x0312 | |
| 191 | #define RT5663_DRC1_PRI_REG_4 0x0313 | |
| 192 | #define RT5663_DRC1_PRI_REG_5 0x0314 | |
| 193 | #define RT5663_DRC1_PRI_REG_6 0x0315 | |
| 194 | #define RT5663_DRC1_PRI_REG_7 0x0316 | |
| 195 | #define RT5663_DRC1_PRI_REG_8 0x0317 | |
| 196 | #define RT5663_ALC_PGA_CTL_1 0x0330 | |
| 197 | #define RT5663_ALC_PGA_CTL_2 0x0331 | |
| 198 | #define RT5663_ALC_PGA_CTL_3 0x0332 | |
| 199 | #define RT5663_ALC_PGA_CTL_4 0x0333 | |
| 200 | #define RT5663_ALC_PGA_CTL_5 0x0334 | |
| 201 | #define RT5663_ALC_PGA_CTL_6 0x0335 | |
| 202 | #define RT5663_ALC_PGA_CTL_7 0x0336 | |
| 203 | #define RT5663_ALC_PGA_CTL_8 0x0337 | |
| 204 | #define RT5663_ALC_PGA_REG_1 0x0338 | |
| 205 | #define RT5663_ALC_PGA_REG_2 0x0339 | |
| 206 | #define RT5663_ALC_PGA_REG_3 0x033a | |
| 207 | #define RT5663_ADC_EQ_RECOV_1 0x03c0 | |
| 208 | #define RT5663_ADC_EQ_RECOV_2 0x03c1 | |
| 209 | #define RT5663_ADC_EQ_RECOV_3 0x03c2 | |
| 210 | #define RT5663_ADC_EQ_RECOV_4 0x03c3 | |
| 211 | #define RT5663_ADC_EQ_RECOV_5 0x03c4 | |
| 212 | #define RT5663_ADC_EQ_RECOV_6 0x03c5 | |
| 213 | #define RT5663_ADC_EQ_RECOV_7 0x03c6 | |
| 214 | #define RT5663_ADC_EQ_RECOV_8 0x03c7 | |
| 215 | #define RT5663_ADC_EQ_RECOV_9 0x03c8 | |
| 216 | #define RT5663_ADC_EQ_RECOV_10 0x03c9 | |
| 217 | #define RT5663_ADC_EQ_RECOV_11 0x03ca | |
| 218 | #define RT5663_ADC_EQ_RECOV_12 0x03cb | |
| 219 | #define RT5663_ADC_EQ_RECOV_13 0x03cc | |
| 220 | #define RT5663_VID_HIDDEN 0x03fe | |
| 221 | #define RT5663_VID_CUSTOMER 0x03ff | |
| 222 | #define RT5663_SCAN_MODE 0x07f0 | |
| 223 | #define RT5663_I2C_BYPA 0x07fa | |
| df7c5216 BL |
224 | |
| 225 | /* Headphone Amp Control 2 (0x0003) */ | |
| 73444723 BL |
226 | #define RT5663_EN_DAC_HPO_MASK (0x1 << 14) |
| 227 | #define RT5663_EN_DAC_HPO_SHIFT 14 | |
| 228 | #define RT5663_EN_DAC_HPO_DIS (0x0 << 14) | |
| 229 | #define RT5663_EN_DAC_HPO_EN (0x1 << 14) | |
| df7c5216 BL |
230 | |
| 231 | /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ | |
| 73444723 BL |
232 | #define RT5663_GAIN_HP (0x1f << 8) |
| 233 | #define RT5663_GAIN_HP_SHIFT 8 | |
| df7c5216 BL |
234 | |
| 235 | /* AEC BST Control (0x000b) */ | |
| 73444723 BL |
236 | #define RT5663_GAIN_CBJ_MASK (0xf << 8) |
| 237 | #define RT5663_GAIN_CBJ_SHIFT 8 | |
| df7c5216 BL |
238 | |
| 239 | /* IN1 Control / MIC GND REF (0x000c) */ | |
| 73444723 BL |
240 | #define RT5663_IN1_DF_MASK (0x1 << 15) |
| 241 | #define RT5663_IN1_DF_SHIFT 15 | |
| df7c5216 BL |
242 | |
| 243 | /* Combo Jack and Type Detection Control 1 (0x0010) */ | |
| 73444723 BL |
244 | #define RT5663_CBJ_DET_MASK (0x1 << 15) |
| 245 | #define RT5663_CBJ_DET_SHIFT 15 | |
| 246 | #define RT5663_CBJ_DET_DIS (0x0 << 15) | |
| 247 | #define RT5663_CBJ_DET_EN (0x1 << 15) | |
| 248 | #define RT5663_DET_TYPE_MASK (0x1 << 12) | |
| 249 | #define RT5663_DET_TYPE_SHIFT 12 | |
| 250 | #define RT5663_DET_TYPE_WLCSP (0x0 << 12) | |
| 251 | #define RT5663_DET_TYPE_QFN (0x1 << 12) | |
| 252 | #define RT5663_VREF_BIAS_MASK (0x1 << 6) | |
| 253 | #define RT5663_VREF_BIAS_SHIFT 6 | |
| 254 | #define RT5663_VREF_BIAS_FSM (0x0 << 6) | |
| 255 | #define RT5663_VREF_BIAS_REG (0x1 << 6) | |
| df7c5216 BL |
256 | |
| 257 | /* REC Left Mixer Control 2 (0x003c) */ | |
| 73444723 BL |
258 | #define RT5663_RECMIX1L_BST1_CBJ (0x1 << 7) |
| 259 | #define RT5663_RECMIX1L_BST1_CBJ_SHIFT 7 | |
| 260 | #define RT5663_RECMIX1L_BST2 (0x1 << 4) | |
| 261 | #define RT5663_RECMIX1L_BST2_SHIFT 4 | |
| df7c5216 BL |
262 | |
| 263 | /* REC Right Mixer Control 2 (0x003e) */ | |
| 73444723 BL |
264 | #define RT5663_RECMIX1R_BST2 (0x1 << 4) |
| 265 | #define RT5663_RECMIX1R_BST2_SHIFT 4 | |
| df7c5216 BL |
266 | |
| 267 | /* DAC1 Digital Volume (0x0019) */ | |
| 73444723 BL |
268 | #define RT5663_DAC_L1_VOL_MASK (0xff << 8) |
| 269 | #define RT5663_DAC_L1_VOL_SHIFT 8 | |
| 270 | #define RT5663_DAC_R1_VOL_MASK (0xff) | |
| 271 | #define RT5663_DAC_R1_VOL_SHIFT 0 | |
| df7c5216 BL |
272 | |
| 273 | /* ADC Digital Volume Control (0x001c) */ | |
| 73444723 BL |
274 | #define RT5663_ADC_L_MUTE_MASK (0x1 << 15) |
| 275 | #define RT5663_ADC_L_MUTE_SHIFT 15 | |
| 276 | #define RT5663_ADC_L_VOL_MASK (0x7f << 8) | |
| 277 | #define RT5663_ADC_L_VOL_SHIFT 8 | |
| 278 | #define RT5663_ADC_R_MUTE_MASK (0x1 << 7) | |
| 279 | #define RT5663_ADC_R_MUTE_SHIFT 7 | |
| 280 | #define RT5663_ADC_R_VOL_MASK (0x7f) | |
| 281 | #define RT5663_ADC_R_VOL_SHIFT 0 | |
| df7c5216 BL |
282 | |
| 283 | /* Stereo ADC Mixer Control (0x0026) */ | |
| 73444723 BL |
284 | #define RT5663_M_STO1_ADC_L1 (0x1 << 15) |
| 285 | #define RT5663_M_STO1_ADC_L1_SHIFT 15 | |
| 286 | #define RT5663_M_STO1_ADC_L2 (0x1 << 14) | |
| 287 | #define RT5663_M_STO1_ADC_L2_SHIFT 14 | |
| 288 | #define RT5663_STO1_ADC_L1_SRC (0x1 << 13) | |
| 289 | #define RT5663_STO1_ADC_L1_SRC_SHIFT 13 | |
| 290 | #define RT5663_STO1_ADC_L2_SRC (0x1 << 12) | |
| 291 | #define RT5663_STO1_ADC_L2_SRC_SHIFT 12 | |
| 292 | #define RT5663_STO1_ADC_L_SRC (0x3 << 10) | |
| 293 | #define RT5663_STO1_ADC_L_SRC_SHIFT 10 | |
| 294 | #define RT5663_M_STO1_ADC_R1 (0x1 << 7) | |
| 295 | #define RT5663_M_STO1_ADC_R1_SHIFT 7 | |
| 296 | #define RT5663_M_STO1_ADC_R2 (0x1 << 6) | |
| 297 | #define RT5663_M_STO1_ADC_R2_SHIFT 6 | |
| 298 | #define RT5663_STO1_ADC_R1_SRC (0x1 << 5) | |
| 299 | #define RT5663_STO1_ADC_R1_SRC_SHIFT 5 | |
| 300 | #define RT5663_STO1_ADC_R2_SRC (0x1 << 4) | |
| 301 | #define RT5663_STO1_ADC_R2_SRC_SHIFT 4 | |
| 302 | #define RT5663_STO1_ADC_R_SRC (0x3 << 2) | |
| 303 | #define RT5663_STO1_ADC_R_SRC_SHIFT 2 | |
| df7c5216 BL |
304 | |
| 305 | /* ADC Mixer to DAC Mixer Control (0x0029) */ | |
| 73444723 BL |
306 | #define RT5663_M_ADCMIX_L (0x1 << 15) |
| 307 | #define RT5663_M_ADCMIX_L_SHIFT 15 | |
| 308 | #define RT5663_M_DAC1_L (0x1 << 14) | |
| 309 | #define RT5663_M_DAC1_L_SHIFT 14 | |
| 310 | #define RT5663_M_ADCMIX_R (0x1 << 7) | |
| 311 | #define RT5663_M_ADCMIX_R_SHIFT 7 | |
| 312 | #define RT5663_M_DAC1_R (0x1 << 6) | |
| 313 | #define RT5663_M_DAC1_R_SHIFT 6 | |
| df7c5216 BL |
314 | |
| 315 | /* Stereo DAC Mixer Control (0x002a) */ | |
| 73444723 BL |
316 | #define RT5663_M_DAC_L1_STO_L (0x1 << 15) |
| 317 | #define RT5663_M_DAC_L1_STO_L_SHIFT 15 | |
| 318 | #define RT5663_M_DAC_R1_STO_L (0x1 << 13) | |
| 319 | #define RT5663_M_DAC_R1_STO_L_SHIFT 13 | |
| 320 | #define RT5663_M_DAC_L1_STO_R (0x1 << 7) | |
| 321 | #define RT5663_M_DAC_L1_STO_R_SHIFT 7 | |
| 322 | #define RT5663_M_DAC_R1_STO_R (0x1 << 5) | |
| 323 | #define RT5663_M_DAC_R1_STO_R_SHIFT 5 | |
| df7c5216 BL |
324 | |
| 325 | /* Power Management for Digital 1 (0x0061) */ | |
| 73444723 BL |
326 | #define RT5663_PWR_I2S1 (0x1 << 15) |
| 327 | #define RT5663_PWR_I2S1_SHIFT 15 | |
| 328 | #define RT5663_PWR_DAC_L1 (0x1 << 11) | |
| 329 | #define RT5663_PWR_DAC_L1_SHIFT 11 | |
| 330 | #define RT5663_PWR_DAC_R1 (0x1 << 10) | |
| 331 | #define RT5663_PWR_DAC_R1_SHIFT 10 | |
| 332 | #define RT5663_PWR_LDO_DACREF_MASK (0x1 << 8) | |
| 333 | #define RT5663_PWR_LDO_DACREF_SHIFT 8 | |
| 334 | #define RT5663_PWR_LDO_DACREF_ON (0x1 << 8) | |
| 335 | #define RT5663_PWR_LDO_DACREF_DOWN (0x0 << 8) | |
| 336 | #define RT5663_PWR_LDO_SHIFT 8 | |
| 337 | #define RT5663_PWR_ADC_L1 (0x1 << 4) | |
| 338 | #define RT5663_PWR_ADC_L1_SHIFT 4 | |
| 339 | #define RT5663_PWR_ADC_R1 (0x1 << 3) | |
| 340 | #define RT5663_PWR_ADC_R1_SHIFT 3 | |
| df7c5216 BL |
341 | |
| 342 | /* Power Management for Digital 2 (0x0062) */ | |
| 73444723 BL |
343 | #define RT5663_PWR_ADC_S1F (0x1 << 15) |
| 344 | #define RT5663_PWR_ADC_S1F_SHIFT 15 | |
| 345 | #define RT5663_PWR_DAC_S1F (0x1 << 10) | |
| 346 | #define RT5663_PWR_DAC_S1F_SHIFT 10 | |
| df7c5216 BL |
347 | |
| 348 | /* Power Management for Analog 1 (0x0063) */ | |
| 73444723 BL |
349 | #define RT5663_PWR_VREF1 (0x1 << 15) |
| 350 | #define RT5663_PWR_VREF1_MASK (0x1 << 15) | |
| 351 | #define RT5663_PWR_VREF1_SHIFT 15 | |
| 352 | #define RT5663_PWR_FV1 (0x1 << 14) | |
| 353 | #define RT5663_PWR_FV1_MASK (0x1 << 14) | |
| 354 | #define RT5663_PWR_FV1_SHIFT 14 | |
| 355 | #define RT5663_PWR_VREF2 (0x1 << 13) | |
| 356 | #define RT5663_PWR_VREF2_MASK (0x1 << 13) | |
| 357 | #define RT5663_PWR_VREF2_SHIFT 13 | |
| 358 | #define RT5663_PWR_FV2 (0x1 << 12) | |
| 359 | #define RT5663_PWR_FV2_MASK (0x1 << 12) | |
| 360 | #define RT5663_PWR_FV2_SHIFT 12 | |
| 361 | #define RT5663_PWR_MB (0x1 << 9) | |
| 362 | #define RT5663_PWR_MB_MASK (0x1 << 9) | |
| 363 | #define RT5663_PWR_MB_SHIFT 9 | |
| 364 | #define RT5663_AMP_HP_MASK (0x3 << 2) | |
| 365 | #define RT5663_AMP_HP_SHIFT 2 | |
| 366 | #define RT5663_AMP_HP_1X (0x0 << 2) | |
| 367 | #define RT5663_AMP_HP_3X (0x1 << 2) | |
| 368 | #define RT5663_AMP_HP_5X (0x3 << 2) | |
| 369 | #define RT5663_LDO1_DVO_MASK (0x3) | |
| 370 | #define RT5663_LDO1_DVO_SHIFT 0 | |
| 371 | #define RT5663_LDO1_DVO_0_9V (0x0) | |
| 372 | #define RT5663_LDO1_DVO_1_0V (0x1) | |
| 373 | #define RT5663_LDO1_DVO_1_2V (0x2) | |
| 374 | #define RT5663_LDO1_DVO_1_4V (0x3) | |
| df7c5216 BL |
375 | |
| 376 | /* Power Management for Analog 2 (0x0064) */ | |
| 73444723 BL |
377 | #define RT5663_PWR_BST1 (0x1 << 15) |
| 378 | #define RT5663_PWR_BST1_MASK (0x1 << 15) | |
| 379 | #define RT5663_PWR_BST1_SHIFT 15 | |
| 380 | #define RT5663_PWR_BST1_OFF (0x0 << 15) | |
| 381 | #define RT5663_PWR_BST1_ON (0x1 << 15) | |
| 382 | #define RT5663_PWR_BST2 (0x1 << 14) | |
| 383 | #define RT5663_PWR_BST2_MASK (0x1 << 14) | |
| 384 | #define RT5663_PWR_BST2_SHIFT 14 | |
| 385 | #define RT5663_PWR_MB1 (0x1 << 11) | |
| 386 | #define RT5663_PWR_MB1_SHIFT 11 | |
| 387 | #define RT5663_PWR_MB2 (0x1 << 10) | |
| 388 | #define RT5663_PWR_MB2_SHIFT 10 | |
| 389 | #define RT5663_PWR_BST2_OP (0x1 << 6) | |
| 390 | #define RT5663_PWR_BST2_OP_MASK (0x1 << 6) | |
| 391 | #define RT5663_PWR_BST2_OP_SHIFT 6 | |
| 392 | #define RT5663_PWR_JD1 (0x1 << 3) | |
| 393 | #define RT5663_PWR_JD1_MASK (0x1 << 3) | |
| 394 | #define RT5663_PWR_JD1_SHIFT 3 | |
| 395 | #define RT5663_PWR_JD2 (0x1 << 2) | |
| 396 | #define RT5663_PWR_JD2_MASK (0x1 << 2) | |
| 397 | #define RT5663_PWR_JD2_SHIFT 2 | |
| 398 | #define RT5663_PWR_RECMIX1 (0x1 << 1) | |
| 399 | #define RT5663_PWR_RECMIX1_SHIFT 1 | |
| 400 | #define RT5663_PWR_RECMIX2 (0x1) | |
| 401 | #define RT5663_PWR_RECMIX2_SHIFT 0 | |
| df7c5216 BL |
402 | |
| 403 | /* Power Management for Analog 3 (0x0065) */ | |
| 73444723 BL |
404 | #define RT5663_PWR_CBJ_MASK (0x1 << 9) |
| 405 | #define RT5663_PWR_CBJ_SHIFT 9 | |
| 406 | #define RT5663_PWR_CBJ_OFF (0x0 << 9) | |
| 407 | #define RT5663_PWR_CBJ_ON (0x1 << 9) | |
| 408 | #define RT5663_PWR_PLL (0x1 << 6) | |
| 409 | #define RT5663_PWR_PLL_SHIFT 6 | |
| 410 | #define RT5663_PWR_LDO2 (0x1 << 2) | |
| 411 | #define RT5663_PWR_LDO2_SHIFT 2 | |
| df7c5216 BL |
412 | |
| 413 | /* Power Management for Volume (0x0067) */ | |
| 73444723 BL |
414 | #define RT5663_V2_PWR_MIC_DET (0x1 << 5) |
| 415 | #define RT5663_V2_PWR_MIC_DET_SHIFT 5 | |
| df7c5216 BL |
416 | |
| 417 | /* MCLK and System Clock Detection Control (0x006b) */ | |
| 73444723 BL |
418 | #define RT5663_EN_ANA_CLK_DET_MASK (0x1 << 15) |
| 419 | #define RT5663_EN_ANA_CLK_DET_SHIFT 15 | |
| 420 | #define RT5663_EN_ANA_CLK_DET_DIS (0x0 << 15) | |
| 421 | #define RT5663_EN_ANA_CLK_DET_AUTO (0x1 << 15) | |
| 422 | #define RT5663_PWR_CLK_DET_MASK (0x1) | |
| 423 | #define RT5663_PWR_CLK_DET_SHIFT 0 | |
| 424 | #define RT5663_PWR_CLK_DET_DIS (0x0) | |
| 425 | #define RT5663_PWR_CLK_DET_EN (0x1) | |
| df7c5216 BL |
426 | |
| 427 | /* I2S1 Audio Serial Data Port Control (0x0070) */ | |
| 73444723 BL |
428 | #define RT5663_I2S_MS_MASK (0x1 << 15) |
| 429 | #define RT5663_I2S_MS_SHIFT 15 | |
| 430 | #define RT5663_I2S_MS_M (0x0 << 15) | |
| 431 | #define RT5663_I2S_MS_S (0x1 << 15) | |
| 432 | #define RT5663_I2S_BP_MASK (0x1 << 8) | |
| 433 | #define RT5663_I2S_BP_SHIFT 8 | |
| 434 | #define RT5663_I2S_BP_NOR (0x0 << 8) | |
| 435 | #define RT5663_I2S_BP_INV (0x1 << 8) | |
| 436 | #define RT5663_I2S_DL_MASK (0x3 << 4) | |
| 437 | #define RT5663_I2S_DL_SHIFT 4 | |
| 438 | #define RT5663_I2S_DL_16 (0x0 << 4) | |
| 439 | #define RT5663_I2S_DL_20 (0x1 << 4) | |
| 440 | #define RT5663_I2S_DL_24 (0x2 << 4) | |
| 441 | #define RT5663_I2S_DL_8 (0x3 << 4) | |
| 442 | #define RT5663_I2S_DF_MASK (0x7) | |
| 443 | #define RT5663_I2S_DF_SHIFT 0 | |
| 444 | #define RT5663_I2S_DF_I2S (0x0) | |
| 445 | #define RT5663_I2S_DF_LEFT (0x1) | |
| 446 | #define RT5663_I2S_DF_PCM_A (0x2) | |
| 447 | #define RT5663_I2S_DF_PCM_B (0x3) | |
| 448 | #define RT5663_I2S_DF_PCM_A_N (0x6) | |
| 449 | #define RT5663_I2S_DF_PCM_B_N (0x7) | |
| df7c5216 BL |
450 | |
| 451 | /* ADC/DAC Clock Control 1 (0x0073) */ | |
| 73444723 BL |
452 | #define RT5663_I2S_PD1_MASK (0x7 << 12) |
| 453 | #define RT5663_I2S_PD1_SHIFT 12 | |
| 454 | #define RT5663_M_I2S_DIV_MASK (0x7 << 8) | |
| 455 | #define RT5663_M_I2S_DIV_SHIFT 8 | |
| 456 | #define RT5663_CLK_SRC_MASK (0x3 << 4) | |
| 457 | #define RT5663_CLK_SRC_MCLK (0x0 << 4) | |
| 458 | #define RT5663_CLK_SRC_PLL_OUT (0x1 << 4) | |
| 459 | #define RT5663_CLK_SRC_DIV (0x2 << 4) | |
| 460 | #define RT5663_CLK_SRC_RC (0x3 << 4) | |
| 461 | #define RT5663_DAC_OSR_MASK (0x3 << 2) | |
| 462 | #define RT5663_DAC_OSR_SHIFT 2 | |
| 463 | #define RT5663_DAC_OSR_128 (0x0 << 2) | |
| 464 | #define RT5663_DAC_OSR_64 (0x1 << 2) | |
| 465 | #define RT5663_DAC_OSR_32 (0x2 << 2) | |
| 466 | #define RT5663_ADC_OSR_MASK (0x3) | |
| 467 | #define RT5663_ADC_OSR_SHIFT 0 | |
| 468 | #define RT5663_ADC_OSR_128 (0x0) | |
| 469 | #define RT5663_ADC_OSR_64 (0x1) | |
| 470 | #define RT5663_ADC_OSR_32 (0x2) | |
| df7c5216 BL |
471 | |
| 472 | /* TDM1 control 1 (0x0078) */ | |
| 73444723 BL |
473 | #define RT5663_TDM_MODE_MASK (0x1 << 15) |
| 474 | #define RT5663_TDM_MODE_SHIFT 15 | |
| 475 | #define RT5663_TDM_MODE_I2S (0x0 << 15) | |
| 476 | #define RT5663_TDM_MODE_TDM (0x1 << 15) | |
| 477 | #define RT5663_TDM_IN_CH_MASK (0x3 << 10) | |
| 478 | #define RT5663_TDM_IN_CH_SHIFT 10 | |
| 479 | #define RT5663_TDM_IN_CH_2 (0x0 << 10) | |
| 480 | #define RT5663_TDM_IN_CH_4 (0x1 << 10) | |
| 481 | #define RT5663_TDM_IN_CH_6 (0x2 << 10) | |
| 482 | #define RT5663_TDM_IN_CH_8 (0x3 << 10) | |
| 483 | #define RT5663_TDM_OUT_CH_MASK (0x3 << 8) | |
| 484 | #define RT5663_TDM_OUT_CH_SHIFT 8 | |
| 485 | #define RT5663_TDM_OUT_CH_2 (0x0 << 8) | |
| 486 | #define RT5663_TDM_OUT_CH_4 (0x1 << 8) | |
| 487 | #define RT5663_TDM_OUT_CH_6 (0x2 << 8) | |
| 488 | #define RT5663_TDM_OUT_CH_8 (0x3 << 8) | |
| 489 | #define RT5663_TDM_IN_LEN_MASK (0x3 << 6) | |
| 490 | #define RT5663_TDM_IN_LEN_SHIFT 6 | |
| 491 | #define RT5663_TDM_IN_LEN_16 (0x0 << 6) | |
| 492 | #define RT5663_TDM_IN_LEN_20 (0x1 << 6) | |
| 493 | #define RT5663_TDM_IN_LEN_24 (0x2 << 6) | |
| 494 | #define RT5663_TDM_IN_LEN_32 (0x3 << 6) | |
| 495 | #define RT5663_TDM_OUT_LEN_MASK (0x3 << 4) | |
| 496 | #define RT5663_TDM_OUT_LEN_SHIFT 4 | |
| 497 | #define RT5663_TDM_OUT_LEN_16 (0x0 << 4) | |
| 498 | #define RT5663_TDM_OUT_LEN_20 (0x1 << 4) | |
| 499 | #define RT5663_TDM_OUT_LEN_24 (0x2 << 4) | |
| 500 | #define RT5663_TDM_OUT_LEN_32 (0x3 << 4) | |
| df7c5216 BL |
501 | |
| 502 | /* Global Clock Control (0x0080) */ | |
| 73444723 BL |
503 | #define RT5663_SCLK_SRC_MASK (0x3 << 14) |
| 504 | #define RT5663_SCLK_SRC_SHIFT 14 | |
| 505 | #define RT5663_SCLK_SRC_MCLK (0x0 << 14) | |
| 506 | #define RT5663_SCLK_SRC_PLL1 (0x1 << 14) | |
| 507 | #define RT5663_SCLK_SRC_RCCLK (0x2 << 14) | |
| 508 | #define RT5663_PLL1_SRC_MASK (0x7 << 11) | |
| 509 | #define RT5663_PLL1_SRC_SHIFT 11 | |
| 510 | #define RT5663_PLL1_SRC_MCLK (0x0 << 11) | |
| 511 | #define RT5663_PLL1_SRC_BCLK1 (0x1 << 11) | |
| 512 | #define RT5663_V2_PLL1_SRC_MASK (0x7 << 8) | |
| 513 | #define RT5663_V2_PLL1_SRC_SHIFT 8 | |
| 514 | #define RT5663_V2_PLL1_SRC_MCLK (0x0 << 8) | |
| 515 | #define RT5663_V2_PLL1_SRC_BCLK1 (0x1 << 8) | |
| 516 | #define RT5663_PLL1_PD_MASK (0x1 << 4) | |
| 517 | #define RT5663_PLL1_PD_SHIFT 4 | |
| 518 | ||
| 519 | #define RT5663_PLL_INP_MAX 40000000 | |
| 520 | #define RT5663_PLL_INP_MIN 256000 | |
| df7c5216 | 521 | /* PLL M/N/K Code Control 1 (0x0081) */ |
| 73444723 BL |
522 | #define RT5663_PLL_N_MAX 0x001ff |
| 523 | #define RT5663_PLL_N_MASK (RT5663_PLL_N_MAX << 7) | |
| 524 | #define RT5663_PLL_N_SHIFT 7 | |
| 525 | #define RT5663_PLL_K_MAX 0x001f | |
| 526 | #define RT5663_PLL_K_MASK (RT5663_PLL_K_MAX) | |
| 527 | #define RT5663_PLL_K_SHIFT 0 | |
| df7c5216 BL |
528 | |
| 529 | /* PLL M/N/K Code Control 2 (0x0082) */ | |
| 73444723 BL |
530 | #define RT5663_PLL_M_MAX 0x00f |
| 531 | #define RT5663_PLL_M_MASK (RT5663_PLL_M_MAX << 12) | |
| 532 | #define RT5663_PLL_M_SHIFT 12 | |
| 533 | #define RT5663_PLL_M_BP (0x1 << 11) | |
| 534 | #define RT5663_PLL_M_BP_SHIFT 11 | |
| df7c5216 BL |
535 | |
| 536 | /* PLL tracking mode 1 (0x0083) */ | |
| 73444723 BL |
537 | #define RT5663_V2_I2S1_ASRC_MASK (0x1 << 13) |
| 538 | #define RT5663_V2_I2S1_ASRC_SHIFT 13 | |
| 539 | #define RT5663_V2_DAC_STO1_ASRC_MASK (0x1 << 12) | |
| 540 | #define RT5663_V2_DAC_STO1_ASRC_SHIFT 12 | |
| 541 | #define RT5663_V2_ADC_STO1_ASRC_MASK (0x1 << 4) | |
| 542 | #define RT5663_V2_ADC_STO1_ASRC_SHIFT 4 | |
| df7c5216 BL |
543 | |
| 544 | /* PLL tracking mode 2 (0x0084)*/ | |
| 73444723 BL |
545 | #define RT5663_DA_STO1_TRACK_MASK (0x7 << 12) |
| 546 | #define RT5663_DA_STO1_TRACK_SHIFT 12 | |
| 547 | #define RT5663_DA_STO1_TRACK_SYSCLK (0x0 << 12) | |
| 548 | #define RT5663_DA_STO1_TRACK_I2S1 (0x1 << 12) | |
| df7c5216 BL |
549 | |
| 550 | /* PLL tracking mode 3 (0x0085)*/ | |
| 73444723 BL |
551 | #define RT5663_V2_AD_STO1_TRACK_MASK (0x7 << 12) |
| 552 | #define RT5663_V2_AD_STO1_TRACK_SHIFT 12 | |
| 553 | #define RT5663_V2_AD_STO1_TRACK_SYSCLK (0x0 << 12) | |
| 554 | #define RT5663_V2_AD_STO1_TRACK_I2S1 (0x1 << 12) | |
| df7c5216 BL |
555 | |
| 556 | /* HPOUT Charge pump control 1 (0x0091) */ | |
| 73444723 BL |
557 | #define RT5663_OSW_HP_L_MASK (0x1 << 11) |
| 558 | #define RT5663_OSW_HP_L_SHIFT 11 | |
| 559 | #define RT5663_OSW_HP_L_EN (0x1 << 11) | |
| 560 | #define RT5663_OSW_HP_L_DIS (0x0 << 11) | |
| 561 | #define RT5663_OSW_HP_R_MASK (0x1 << 10) | |
| 562 | #define RT5663_OSW_HP_R_SHIFT 10 | |
| 563 | #define RT5663_OSW_HP_R_EN (0x1 << 10) | |
| 564 | #define RT5663_OSW_HP_R_DIS (0x0 << 10) | |
| 565 | #define RT5663_SEL_PM_HP_MASK (0x3 << 8) | |
| 566 | #define RT5663_SEL_PM_HP_SHIFT 8 | |
| 567 | #define RT5663_SEL_PM_HP_0_6 (0x0 << 8) | |
| 568 | #define RT5663_SEL_PM_HP_0_9 (0x1 << 8) | |
| 569 | #define RT5663_SEL_PM_HP_1_8 (0x2 << 8) | |
| 570 | #define RT5663_SEL_PM_HP_HIGH (0x3 << 8) | |
| 571 | #define RT5663_OVCD_HP_MASK (0x1 << 2) | |
| 572 | #define RT5663_OVCD_HP_SHIFT 2 | |
| 573 | #define RT5663_OVCD_HP_EN (0x1 << 2) | |
| 574 | #define RT5663_OVCD_HP_DIS (0x0 << 2) | |
| df7c5216 BL |
575 | |
| 576 | /* RC Clock Control (0x0094) */ | |
| 73444723 BL |
577 | #define RT5663_DIG_25M_CLK_MASK (0x1 << 9) |
| 578 | #define RT5663_DIG_25M_CLK_SHIFT 9 | |
| 579 | #define RT5663_DIG_25M_CLK_DIS (0x0 << 9) | |
| 580 | #define RT5663_DIG_25M_CLK_EN (0x1 << 9) | |
| 581 | #define RT5663_DIG_1M_CLK_MASK (0x1 << 8) | |
| 582 | #define RT5663_DIG_1M_CLK_SHIFT 8 | |
| 583 | #define RT5663_DIG_1M_CLK_DIS (0x0 << 8) | |
| 584 | #define RT5663_DIG_1M_CLK_EN (0x1 << 8) | |
| df7c5216 BL |
585 | |
| 586 | /* Auto Turn On 1M RC CLK (0x009f) */ | |
| 73444723 BL |
587 | #define RT5663_IRQ_POW_SAV_MASK (0x1 << 15) |
| 588 | #define RT5663_IRQ_POW_SAV_SHIFT 15 | |
| 589 | #define RT5663_IRQ_POW_SAV_DIS (0x0 << 15) | |
| 590 | #define RT5663_IRQ_POW_SAV_EN (0x1 << 15) | |
| 591 | #define RT5663_IRQ_POW_SAV_JD1_MASK (0x1 << 14) | |
| 592 | #define RT5663_IRQ_POW_SAV_JD1_SHIFT 14 | |
| 593 | #define RT5663_IRQ_POW_SAV_JD1_DIS (0x0 << 14) | |
| 594 | #define RT5663_IRQ_POW_SAV_JD1_EN (0x1 << 14) | |
| af2728e4 OC |
595 | #define RT5663_IRQ_MANUAL_MASK (0x1 << 8) |
| 596 | #define RT5663_IRQ_MANUAL_SHIFT 8 | |
| 597 | #define RT5663_IRQ_MANUAL_DIS (0x0 << 8) | |
| 598 | #define RT5663_IRQ_MANUAL_EN (0x1 << 8) | |
| df7c5216 BL |
599 | |
| 600 | /* IRQ Control 1 (0x00b6) */ | |
| 73444723 BL |
601 | #define RT5663_EN_CB_JD_MASK (0x1 << 3) |
| 602 | #define RT5663_EN_CB_JD_SHIFT 3 | |
| 603 | #define RT5663_EN_CB_JD_EN (0x1 << 3) | |
| 604 | #define RT5663_EN_CB_JD_DIS (0x0 << 3) | |
| df7c5216 BL |
605 | |
| 606 | /* IRQ Control 3 (0x00b8) */ | |
| 73444723 BL |
607 | #define RT5663_V2_EN_IRQ_INLINE_MASK (0x1 << 6) |
| 608 | #define RT5663_V2_EN_IRQ_INLINE_SHIFT 6 | |
| 609 | #define RT5663_V2_EN_IRQ_INLINE_BYP (0x0 << 6) | |
| 610 | #define RT5663_V2_EN_IRQ_INLINE_NOR (0x1 << 6) | |
| df7c5216 BL |
611 | |
| 612 | /* GPIO Control 1 (0x00c0) */ | |
| 73444723 BL |
613 | #define RT5663_GP1_PIN_MASK (0x1 << 15) |
| 614 | #define RT5663_GP1_PIN_SHIFT 15 | |
| 615 | #define RT5663_GP1_PIN_GPIO1 (0x0 << 15) | |
| 616 | #define RT5663_GP1_PIN_IRQ (0x1 << 15) | |
| df7c5216 BL |
617 | |
| 618 | /* GPIO Control 2 (0x00c1) */ | |
| 73444723 BL |
619 | #define RT5663_GP4_PIN_CONF_MASK (0x1 << 5) |
| 620 | #define RT5663_GP4_PIN_CONF_SHIFT 5 | |
| 621 | #define RT5663_GP4_PIN_CONF_INPUT (0x0 << 5) | |
| 622 | #define RT5663_GP4_PIN_CONF_OUTPUT (0x1 << 5) | |
| df7c5216 BL |
623 | |
| 624 | /* GPIO Control 2 (0x00c2) */ | |
| 73444723 BL |
625 | #define RT5663_GP8_PIN_CONF_MASK (0x1 << 13) |
| 626 | #define RT5663_GP8_PIN_CONF_SHIFT 13 | |
| 627 | #define RT5663_GP8_PIN_CONF_INPUT (0x0 << 13) | |
| 628 | #define RT5663_GP8_PIN_CONF_OUTPUT (0x1 << 13) | |
| df7c5216 BL |
629 | |
| 630 | /* 4 Buttons Inline Command Function 1 (0x00df) */ | |
| 73444723 BL |
631 | #define RT5663_4BTN_CLK_DEB_MASK (0x3 << 2) |
| 632 | #define RT5663_4BTN_CLK_DEB_SHIFT 2 | |
| 633 | #define RT5663_4BTN_CLK_DEB_8MS (0x0 << 2) | |
| 634 | #define RT5663_4BTN_CLK_DEB_16MS (0x1 << 2) | |
| 635 | #define RT5663_4BTN_CLK_DEB_32MS (0x2 << 2) | |
| 636 | #define RT5663_4BTN_CLK_DEB_65MS (0x3 << 2) | |
| df7c5216 BL |
637 | |
| 638 | /* Inline Command Function 6 (0x00e0) */ | |
| 73444723 BL |
639 | #define RT5663_EN_4BTN_INL_MASK (0x1 << 15) |
| 640 | #define RT5663_EN_4BTN_INL_SHIFT 15 | |
| 641 | #define RT5663_EN_4BTN_INL_DIS (0x0 << 15) | |
| 642 | #define RT5663_EN_4BTN_INL_EN (0x1 << 15) | |
| 643 | #define RT5663_RESET_4BTN_INL_MASK (0x1 << 14) | |
| 644 | #define RT5663_RESET_4BTN_INL_SHIFT 14 | |
| 645 | #define RT5663_RESET_4BTN_INL_RESET (0x0 << 14) | |
| 646 | #define RT5663_RESET_4BTN_INL_NOR (0x1 << 14) | |
| df7c5216 BL |
647 | |
| 648 | /* Digital Misc Control (0x00fa) */ | |
| 73444723 BL |
649 | #define RT5663_DIG_GATE_CTRL_MASK 0x1 |
| 650 | #define RT5663_DIG_GATE_CTRL_SHIFT (0) | |
| 651 | #define RT5663_DIG_GATE_CTRL_DIS 0x0 | |
| 652 | #define RT5663_DIG_GATE_CTRL_EN 0x1 | |
| df7c5216 BL |
653 | |
| 654 | /* Chopper and Clock control for DAC L (0x013a)*/ | |
| 73444723 BL |
655 | #define RT5663_CKXEN_DAC1_MASK (0x1 << 13) |
| 656 | #define RT5663_CKXEN_DAC1_SHIFT 13 | |
| 657 | #define RT5663_CKGEN_DAC1_MASK (0x1 << 12) | |
| 658 | #define RT5663_CKGEN_DAC1_SHIFT 12 | |
| df7c5216 BL |
659 | |
| 660 | /* Chopper and Clock control for ADC (0x013b)*/ | |
| 73444723 BL |
661 | #define RT5663_CKXEN_ADCC_MASK (0x1 << 13) |
| 662 | #define RT5663_CKXEN_ADCC_SHIFT 13 | |
| 663 | #define RT5663_CKGEN_ADCC_MASK (0x1 << 12) | |
| 664 | #define RT5663_CKGEN_ADCC_SHIFT 12 | |
| df7c5216 BL |
665 | |
| 666 | /* HP Behavior Logic Control 2 (0x01db) */ | |
| 73444723 BL |
667 | #define RT5663_HP_SIG_SRC1_MASK (0x3) |
| 668 | #define RT5663_HP_SIG_SRC1_SHIFT 0 | |
| 669 | #define RT5663_HP_SIG_SRC1_HP_DC (0x0) | |
| 670 | #define RT5663_HP_SIG_SRC1_HP_CALIB (0x1) | |
| 671 | #define RT5663_HP_SIG_SRC1_REG (0x2) | |
| 672 | #define RT5663_HP_SIG_SRC1_SILENCE (0x3) | |
| df7c5216 BL |
673 | |
| 674 | /* RT5663 specific register */ | |
| 675 | #define RT5663_HP_OUT_EN 0x0002 | |
| 676 | #define RT5663_HP_LCH_DRE 0x0005 | |
| 677 | #define RT5663_HP_RCH_DRE 0x0006 | |
| 678 | #define RT5663_CALIB_BST 0x000a | |
| 679 | #define RT5663_RECMIX 0x0010 | |
| 680 | #define RT5663_SIL_DET_CTL 0x0015 | |
| 681 | #define RT5663_PWR_SAV_SILDET 0x0016 | |
| 682 | #define RT5663_SIDETONE_CTL 0x0018 | |
| 683 | #define RT5663_STO1_DAC_DIG_VOL 0x0019 | |
| 684 | #define RT5663_STO1_ADC_DIG_VOL 0x001c | |
| 685 | #define RT5663_STO1_BOOST 0x001f | |
| 686 | #define RT5663_HP_IMP_GAIN_1 0x0022 | |
| 687 | #define RT5663_HP_IMP_GAIN_2 0x0023 | |
| 688 | #define RT5663_STO1_ADC_MIXER 0x0026 | |
| 689 | #define RT5663_AD_DA_MIXER 0x0029 | |
| 690 | #define RT5663_STO_DAC_MIXER 0x002a | |
| 691 | #define RT5663_DIG_SIDE_MIXER 0x002c | |
| 692 | #define RT5663_BYPASS_STO_DAC 0x002d | |
| 693 | #define RT5663_CALIB_REC_MIX 0x0040 | |
| 694 | #define RT5663_PWR_DIG_1 0x0061 | |
| 695 | #define RT5663_PWR_DIG_2 0x0062 | |
| 696 | #define RT5663_PWR_ANLG_1 0x0063 | |
| 697 | #define RT5663_PWR_ANLG_2 0x0064 | |
| 698 | #define RT5663_PWR_ANLG_3 0x0065 | |
| 699 | #define RT5663_PWR_MIXER 0x0066 | |
| 700 | #define RT5663_SIG_CLK_DET 0x006b | |
| 701 | #define RT5663_PRE_DIV_GATING_1 0x006e | |
| 702 | #define RT5663_PRE_DIV_GATING_2 0x006f | |
| 703 | #define RT5663_I2S1_SDP 0x0070 | |
| 704 | #define RT5663_ADDA_CLK_1 0x0073 | |
| 705 | #define RT5663_ADDA_RST 0x0074 | |
| 706 | #define RT5663_FRAC_DIV_1 0x0075 | |
| 707 | #define RT5663_FRAC_DIV_2 0x0076 | |
| 708 | #define RT5663_TDM_1 0x0077 | |
| 709 | #define RT5663_TDM_2 0x0078 | |
| 710 | #define RT5663_TDM_3 0x0079 | |
| 711 | #define RT5663_TDM_4 0x007a | |
| 712 | #define RT5663_TDM_5 0x007b | |
| 73444723 BL |
713 | #define RT5663_TDM_6 0x007c |
| 714 | #define RT5663_TDM_7 0x007d | |
| 715 | #define RT5663_TDM_8 0x007e | |
| 716 | #define RT5663_TDM_9 0x007f | |
| df7c5216 BL |
717 | #define RT5663_GLB_CLK 0x0080 |
| 718 | #define RT5663_PLL_1 0x0081 | |
| 719 | #define RT5663_PLL_2 0x0082 | |
| 720 | #define RT5663_ASRC_1 0x0083 | |
| 721 | #define RT5663_ASRC_2 0x0084 | |
| 722 | #define RT5663_ASRC_4 0x0086 | |
| 723 | #define RT5663_DUMMY_REG 0x0087 | |
| 724 | #define RT5663_ASRC_8 0x008a | |
| 725 | #define RT5663_ASRC_9 0x008b | |
| 726 | #define RT5663_ASRC_11 0x008c | |
| 727 | #define RT5663_DEPOP_1 0x008e | |
| 728 | #define RT5663_DEPOP_2 0x008f | |
| 729 | #define RT5663_DEPOP_3 0x0090 | |
| 730 | #define RT5663_HP_CHARGE_PUMP_1 0x0091 | |
| 731 | #define RT5663_HP_CHARGE_PUMP_2 0x0092 | |
| 732 | #define RT5663_MICBIAS_1 0x0093 | |
| 733 | #define RT5663_RC_CLK 0x0094 | |
| 734 | #define RT5663_ASRC_11_2 0x0097 | |
| 735 | #define RT5663_DUMMY_REG_2 0x0098 | |
| 736 | #define RT5663_REC_PATH_GAIN 0x009a | |
| 737 | #define RT5663_AUTO_1MRC_CLK 0x009f | |
| 738 | #define RT5663_ADC_EQ_1 0x00ae | |
| 739 | #define RT5663_ADC_EQ_2 0x00af | |
| 740 | #define RT5663_IRQ_1 0x00b6 | |
| 741 | #define RT5663_IRQ_2 0x00b7 | |
| 742 | #define RT5663_IRQ_3 0x00b8 | |
| 743 | #define RT5663_IRQ_4 0x00ba | |
| 744 | #define RT5663_IRQ_5 0x00bb | |
| 745 | #define RT5663_INT_ST_1 0x00be | |
| 746 | #define RT5663_INT_ST_2 0x00bf | |
| 747 | #define RT5663_GPIO_1 0x00c0 | |
| 748 | #define RT5663_GPIO_2 0x00c1 | |
| 73444723 | 749 | #define RT5663_GPIO_STA1 0x00c5 |
| df7c5216 BL |
750 | #define RT5663_SIN_GEN_1 0x00cb |
| 751 | #define RT5663_SIN_GEN_2 0x00cc | |
| 752 | #define RT5663_SIN_GEN_3 0x00cd | |
| 753 | #define RT5663_SOF_VOL_ZC1 0x00d9 | |
| 754 | #define RT5663_IL_CMD_1 0x00db | |
| 755 | #define RT5663_IL_CMD_2 0x00dc | |
| 756 | #define RT5663_IL_CMD_3 0x00dd | |
| 757 | #define RT5663_IL_CMD_4 0x00de | |
| 758 | #define RT5663_IL_CMD_5 0x00df | |
| 759 | #define RT5663_IL_CMD_6 0x00e0 | |
| 760 | #define RT5663_IL_CMD_7 0x00e1 | |
| 761 | #define RT5663_IL_CMD_8 0x00e2 | |
| 762 | #define RT5663_IL_CMD_PWRSAV1 0x00e4 | |
| 763 | #define RT5663_IL_CMD_PWRSAV2 0x00e5 | |
| 764 | #define RT5663_EM_JACK_TYPE_1 0x00e6 | |
| 765 | #define RT5663_EM_JACK_TYPE_2 0x00e7 | |
| 766 | #define RT5663_EM_JACK_TYPE_3 0x00e8 | |
| 767 | #define RT5663_EM_JACK_TYPE_4 0x00e9 | |
| 768 | #define RT5663_EM_JACK_TYPE_5 0x00ea | |
| 769 | #define RT5663_EM_JACK_TYPE_6 0x00eb | |
| 770 | #define RT5663_STO1_HPF_ADJ1 0x00ec | |
| 771 | #define RT5663_STO1_HPF_ADJ2 0x00ed | |
| 772 | #define RT5663_FAST_OFF_MICBIAS 0x00f4 | |
| 773 | #define RT5663_JD_CTRL1 0x00f6 | |
| 774 | #define RT5663_JD_CTRL2 0x00f8 | |
| 775 | #define RT5663_DIG_MISC 0x00fa | |
| 776 | #define RT5663_DIG_VOL_ZCD 0x0100 | |
| 777 | #define RT5663_ANA_BIAS_CUR_1 0x0108 | |
| 778 | #define RT5663_ANA_BIAS_CUR_2 0x0109 | |
| 779 | #define RT5663_ANA_BIAS_CUR_3 0x010a | |
| 780 | #define RT5663_ANA_BIAS_CUR_4 0x010b | |
| 781 | #define RT5663_ANA_BIAS_CUR_5 0x010c | |
| 782 | #define RT5663_ANA_BIAS_CUR_6 0x010d | |
| 783 | #define RT5663_BIAS_CUR_5 0x010e | |
| 784 | #define RT5663_BIAS_CUR_6 0x010f | |
| 785 | #define RT5663_BIAS_CUR_7 0x0110 | |
| 786 | #define RT5663_BIAS_CUR_8 0x0111 | |
| 787 | #define RT5663_DACREF_LDO 0x0112 | |
| 788 | #define RT5663_DUMMY_REG_3 0x0113 | |
| 789 | #define RT5663_BIAS_CUR_9 0x0114 | |
| 790 | #define RT5663_DUMMY_REG_4 0x0116 | |
| 791 | #define RT5663_VREFADJ_OP 0x0117 | |
| 792 | #define RT5663_VREF_RECMIX 0x0118 | |
| 793 | #define RT5663_CHARGE_PUMP_1 0x0125 | |
| 794 | #define RT5663_CHARGE_PUMP_1_2 0x0126 | |
| 795 | #define RT5663_CHARGE_PUMP_1_3 0x0127 | |
| 796 | #define RT5663_CHARGE_PUMP_2 0x0128 | |
| 797 | #define RT5663_DIG_IN_PIN1 0x0132 | |
| 798 | #define RT5663_PAD_DRV_CTL 0x0137 | |
| 799 | #define RT5663_PLL_INT_REG 0x0139 | |
| 800 | #define RT5663_CHOP_DAC_L 0x013a | |
| 801 | #define RT5663_CHOP_ADC 0x013b | |
| 802 | #define RT5663_CALIB_ADC 0x013c | |
| 803 | #define RT5663_CHOP_DAC_R 0x013d | |
| 804 | #define RT5663_DUMMY_CTL_DACLR 0x013e | |
| 805 | #define RT5663_DUMMY_REG_5 0x0140 | |
| 806 | #define RT5663_SOFT_RAMP 0x0141 | |
| 807 | #define RT5663_TEST_MODE_1 0x0144 | |
| 808 | #define RT5663_TEST_MODE_2 0x0145 | |
| 809 | #define RT5663_TEST_MODE_3 0x0146 | |
| 73444723 BL |
810 | #define RT5663_TEST_MODE_4 0x0147 |
| 811 | #define RT5663_TEST_MODE_5 0x0148 | |
| df7c5216 BL |
812 | #define RT5663_STO_DRE_1 0x0160 |
| 813 | #define RT5663_STO_DRE_2 0x0161 | |
| 814 | #define RT5663_STO_DRE_3 0x0162 | |
| 815 | #define RT5663_STO_DRE_4 0x0163 | |
| 816 | #define RT5663_STO_DRE_5 0x0164 | |
| 817 | #define RT5663_STO_DRE_6 0x0165 | |
| 818 | #define RT5663_STO_DRE_7 0x0166 | |
| 819 | #define RT5663_STO_DRE_8 0x0167 | |
| 820 | #define RT5663_STO_DRE_9 0x0168 | |
| 821 | #define RT5663_STO_DRE_10 0x0169 | |
| 822 | #define RT5663_MIC_DECRO_1 0x0180 | |
| 823 | #define RT5663_MIC_DECRO_2 0x0181 | |
| 824 | #define RT5663_MIC_DECRO_3 0x0182 | |
| 825 | #define RT5663_MIC_DECRO_4 0x0183 | |
| 826 | #define RT5663_MIC_DECRO_5 0x0184 | |
| 827 | #define RT5663_MIC_DECRO_6 0x0185 | |
| 828 | #define RT5663_HP_DECRO_1 0x01b0 | |
| 829 | #define RT5663_HP_DECRO_2 0x01b1 | |
| 830 | #define RT5663_HP_DECRO_3 0x01b2 | |
| 831 | #define RT5663_HP_DECRO_4 0x01b3 | |
| 832 | #define RT5663_HP_DECOUP 0x01b4 | |
| 833 | #define RT5663_HP_IMP_SEN_MAP8 0x01b5 | |
| 834 | #define RT5663_HP_IMP_SEN_MAP9 0x01b6 | |
| 835 | #define RT5663_HP_IMP_SEN_MAP10 0x01b7 | |
| 836 | #define RT5663_HP_IMP_SEN_MAP11 0x01b8 | |
| 837 | #define RT5663_HP_IMP_SEN_1 0x01c0 | |
| 838 | #define RT5663_HP_IMP_SEN_2 0x01c1 | |
| 839 | #define RT5663_HP_IMP_SEN_3 0x01c2 | |
| 840 | #define RT5663_HP_IMP_SEN_4 0x01c3 | |
| 841 | #define RT5663_HP_IMP_SEN_5 0x01c4 | |
| 842 | #define RT5663_HP_IMP_SEN_6 0x01c5 | |
| 843 | #define RT5663_HP_IMP_SEN_7 0x01c6 | |
| 844 | #define RT5663_HP_IMP_SEN_8 0x01c7 | |
| 845 | #define RT5663_HP_IMP_SEN_9 0x01c8 | |
| 846 | #define RT5663_HP_IMP_SEN_10 0x01c9 | |
| 847 | #define RT5663_HP_IMP_SEN_11 0x01ca | |
| 848 | #define RT5663_HP_IMP_SEN_12 0x01cb | |
| 849 | #define RT5663_HP_IMP_SEN_13 0x01cc | |
| 850 | #define RT5663_HP_IMP_SEN_14 0x01cd | |
| 851 | #define RT5663_HP_IMP_SEN_15 0x01ce | |
| 852 | #define RT5663_HP_IMP_SEN_16 0x01cf | |
| 853 | #define RT5663_HP_IMP_SEN_17 0x01d0 | |
| 854 | #define RT5663_HP_IMP_SEN_18 0x01d1 | |
| 855 | #define RT5663_HP_IMP_SEN_19 0x01d2 | |
| 856 | #define RT5663_HP_IMPSEN_DIG5 0x01d3 | |
| 857 | #define RT5663_HP_IMPSEN_MAP1 0x01d4 | |
| 858 | #define RT5663_HP_IMPSEN_MAP2 0x01d5 | |
| 859 | #define RT5663_HP_IMPSEN_MAP3 0x01d6 | |
| 860 | #define RT5663_HP_IMPSEN_MAP4 0x01d7 | |
| 861 | #define RT5663_HP_IMPSEN_MAP5 0x01d8 | |
| 862 | #define RT5663_HP_IMPSEN_MAP7 0x01d9 | |
| 863 | #define RT5663_HP_LOGIC_1 0x01da | |
| 864 | #define RT5663_HP_LOGIC_2 0x01db | |
| 865 | #define RT5663_HP_CALIB_1 0x01dd | |
| 866 | #define RT5663_HP_CALIB_1_1 0x01de | |
| 867 | #define RT5663_HP_CALIB_2 0x01df | |
| 868 | #define RT5663_HP_CALIB_3 0x01e0 | |
| 869 | #define RT5663_HP_CALIB_4 0x01e1 | |
| 870 | #define RT5663_HP_CALIB_5 0x01e2 | |
| 871 | #define RT5663_HP_CALIB_5_1 0x01e3 | |
| 872 | #define RT5663_HP_CALIB_6 0x01e4 | |
| 873 | #define RT5663_HP_CALIB_7 0x01e5 | |
| 874 | #define RT5663_HP_CALIB_9 0x01e6 | |
| 875 | #define RT5663_HP_CALIB_10 0x01e7 | |
| 876 | #define RT5663_HP_CALIB_11 0x01e8 | |
| 877 | #define RT5663_HP_CALIB_ST1 0x01ea | |
| 878 | #define RT5663_HP_CALIB_ST2 0x01eb | |
| 879 | #define RT5663_HP_CALIB_ST3 0x01ec | |
| 880 | #define RT5663_HP_CALIB_ST4 0x01ed | |
| 881 | #define RT5663_HP_CALIB_ST5 0x01ee | |
| 882 | #define RT5663_HP_CALIB_ST6 0x01ef | |
| 883 | #define RT5663_HP_CALIB_ST7 0x01f0 | |
| 884 | #define RT5663_HP_CALIB_ST8 0x01f1 | |
| 885 | #define RT5663_HP_CALIB_ST9 0x01f2 | |
| 886 | #define RT5663_HP_AMP_DET 0x0200 | |
| 887 | #define RT5663_DUMMY_REG_6 0x0201 | |
| 888 | #define RT5663_HP_BIAS 0x0202 | |
| 889 | #define RT5663_CBJ_1 0x0250 | |
| 890 | #define RT5663_CBJ_2 0x0251 | |
| 891 | #define RT5663_CBJ_3 0x0252 | |
| 892 | #define RT5663_DUMMY_1 0x02fa | |
| 893 | #define RT5663_DUMMY_2 0x02fb | |
| 894 | #define RT5663_DUMMY_3 0x02fc | |
| 895 | #define RT5663_ANA_JD 0x0300 | |
| 896 | #define RT5663_ADC_LCH_LPF1_A1 0x03d0 | |
| 897 | #define RT5663_ADC_RCH_LPF1_A1 0x03d1 | |
| 898 | #define RT5663_ADC_LCH_LPF1_H0 0x03d2 | |
| 899 | #define RT5663_ADC_RCH_LPF1_H0 0x03d3 | |
| 900 | #define RT5663_ADC_LCH_BPF1_A1 0x03d4 | |
| 901 | #define RT5663_ADC_RCH_BPF1_A1 0x03d5 | |
| 902 | #define RT5663_ADC_LCH_BPF1_A2 0x03d6 | |
| 903 | #define RT5663_ADC_RCH_BPF1_A2 0x03d7 | |
| 904 | #define RT5663_ADC_LCH_BPF1_H0 0x03d8 | |
| 905 | #define RT5663_ADC_RCH_BPF1_H0 0x03d9 | |
| 906 | #define RT5663_ADC_LCH_BPF2_A1 0x03da | |
| 907 | #define RT5663_ADC_RCH_BPF2_A1 0x03db | |
| 908 | #define RT5663_ADC_LCH_BPF2_A2 0x03dc | |
| 909 | #define RT5663_ADC_RCH_BPF2_A2 0x03dd | |
| 910 | #define RT5663_ADC_LCH_BPF2_H0 0x03de | |
| 911 | #define RT5663_ADC_RCH_BPF2_H0 0x03df | |
| 912 | #define RT5663_ADC_LCH_BPF3_A1 0x03e0 | |
| 913 | #define RT5663_ADC_RCH_BPF3_A1 0x03e1 | |
| 914 | #define RT5663_ADC_LCH_BPF3_A2 0x03e2 | |
| 915 | #define RT5663_ADC_RCH_BPF3_A2 0x03e3 | |
| 916 | #define RT5663_ADC_LCH_BPF3_H0 0x03e4 | |
| 917 | #define RT5663_ADC_RCH_BPF3_H0 0x03e5 | |
| 918 | #define RT5663_ADC_LCH_BPF4_A1 0x03e6 | |
| 919 | #define RT5663_ADC_RCH_BPF4_A1 0x03e7 | |
| 920 | #define RT5663_ADC_LCH_BPF4_A2 0x03e8 | |
| 921 | #define RT5663_ADC_RCH_BPF4_A2 0x03e9 | |
| 922 | #define RT5663_ADC_LCH_BPF4_H0 0x03ea | |
| 923 | #define RT5663_ADC_RCH_BPF4_H0 0x03eb | |
| 924 | #define RT5663_ADC_LCH_HPF1_A1 0x03ec | |
| 925 | #define RT5663_ADC_RCH_HPF1_A1 0x03ed | |
| 926 | #define RT5663_ADC_LCH_HPF1_H0 0x03ee | |
| 927 | #define RT5663_ADC_RCH_HPF1_H0 0x03ef | |
| 928 | #define RT5663_ADC_EQ_PRE_VOL_L 0x03f0 | |
| 929 | #define RT5663_ADC_EQ_PRE_VOL_R 0x03f1 | |
| 930 | #define RT5663_ADC_EQ_POST_VOL_L 0x03f2 | |
| 931 | #define RT5663_ADC_EQ_POST_VOL_R 0x03f3 | |
| 932 | ||
| 73444723 | 933 | /* RECMIX Control (0x0010) */ |
| df7c5216 BL |
934 | #define RT5663_RECMIX1_BST1_MASK (0x1) |
| 935 | #define RT5663_RECMIX1_BST1_SHIFT 0 | |
| 936 | #define RT5663_RECMIX1_BST1_ON (0x0) | |
| 937 | #define RT5663_RECMIX1_BST1_OFF (0x1) | |
| 938 | ||
| 73444723 | 939 | /* Bypass Stereo1 DAC Mixer Control (0x002d) */ |
| df7c5216 BL |
940 | #define RT5663_DACL1_SRC_MASK (0x1 << 3) |
| 941 | #define RT5663_DACL1_SRC_SHIFT 3 | |
| 942 | #define RT5663_DACR1_SRC_MASK (0x1 << 2) | |
| 943 | #define RT5663_DACR1_SRC_SHIFT 2 | |
| 944 | ||
| 73444723 | 945 | /* TDM control 2 (0x0078) */ |
| df7c5216 BL |
946 | #define RT5663_DATA_SWAP_ADCDAT1_MASK (0x3 << 14) |
| 947 | #define RT5663_DATA_SWAP_ADCDAT1_SHIFT 14 | |
| 948 | #define RT5663_DATA_SWAP_ADCDAT1_LR (0x0 << 14) | |
| 949 | #define RT5663_DATA_SWAP_ADCDAT1_RL (0x1 << 14) | |
| 950 | #define RT5663_DATA_SWAP_ADCDAT1_LL (0x2 << 14) | |
| 951 | #define RT5663_DATA_SWAP_ADCDAT1_RR (0x3 << 14) | |
| 952 | ||
| 73444723 | 953 | /* TDM control 5 (0x007b) */ |
| df7c5216 BL |
954 | #define RT5663_TDM_LENGTN_MASK (0x3) |
| 955 | #define RT5663_TDM_LENGTN_SHIFT 0 | |
| 956 | #define RT5663_TDM_LENGTN_16 (0x0) | |
| 957 | #define RT5663_TDM_LENGTN_20 (0x1) | |
| 958 | #define RT5663_TDM_LENGTN_24 (0x2) | |
| 959 | #define RT5663_TDM_LENGTN_32 (0x3) | |
| 960 | ||
| df7c5216 BL |
961 | /* PLL tracking mode 1 (0x0083) */ |
| 962 | #define RT5663_I2S1_ASRC_MASK (0x1 << 11) | |
| 963 | #define RT5663_I2S1_ASRC_SHIFT 11 | |
| 964 | #define RT5663_DAC_STO1_ASRC_MASK (0x1 << 10) | |
| 965 | #define RT5663_DAC_STO1_ASRC_SHIFT 10 | |
| 966 | #define RT5663_ADC_STO1_ASRC_MASK (0x1 << 3) | |
| 967 | #define RT5663_ADC_STO1_ASRC_SHIFT 3 | |
| 968 | ||
| 969 | /* PLL tracking mode 2 (0x0084)*/ | |
| 970 | #define RT5663_DA_STO1_TRACK_MASK (0x7 << 12) | |
| 971 | #define RT5663_DA_STO1_TRACK_SHIFT 12 | |
| 972 | #define RT5663_DA_STO1_TRACK_SYSCLK (0x0 << 12) | |
| 973 | #define RT5663_DA_STO1_TRACK_I2S1 (0x1 << 12) | |
| 974 | #define RT5663_AD_STO1_TRACK_MASK (0x7) | |
| 975 | #define RT5663_AD_STO1_TRACK_SHIFT 0 | |
| 976 | #define RT5663_AD_STO1_TRACK_SYSCLK (0x0) | |
| 977 | #define RT5663_AD_STO1_TRACK_I2S1 (0x1) | |
| 978 | ||
| 73444723 | 979 | /* HPOUT Charge pump control 1 (0x0091) */ |
| df7c5216 BL |
980 | #define RT5663_SI_HP_MASK (0x1 << 12) |
| 981 | #define RT5663_SI_HP_SHIFT 12 | |
| 982 | #define RT5663_SI_HP_EN (0x1 << 12) | |
| 983 | #define RT5663_SI_HP_DIS (0x0 << 12) | |
| 984 | ||
| 73444723 | 985 | /* GPIO Control 2 (0x00b6) */ |
| df7c5216 BL |
986 | #define RT5663_GP1_PIN_CONF_MASK (0x1 << 2) |
| 987 | #define RT5663_GP1_PIN_CONF_SHIFT 2 | |
| 988 | #define RT5663_GP1_PIN_CONF_OUTPUT (0x1 << 2) | |
| 989 | #define RT5663_GP1_PIN_CONF_INPUT (0x0 << 2) | |
| 990 | ||
| 73444723 | 991 | /* GPIO Control 2 (0x00b7) */ |
| df7c5216 BL |
992 | #define RT5663_EN_IRQ_INLINE_MASK (0x1 << 3) |
| 993 | #define RT5663_EN_IRQ_INLINE_SHIFT 3 | |
| 994 | #define RT5663_EN_IRQ_INLINE_NOR (0x1 << 3) | |
| 995 | #define RT5663_EN_IRQ_INLINE_BYP (0x0 << 3) | |
| 996 | ||
| 73444723 | 997 | /* GPIO Control 1 (0x00c0) */ |
| 7e7e76bd JY |
998 | #define RT5663_GPIO1_TYPE_MASK (0x1 << 15) |
| 999 | #define RT5663_GPIO1_TYPE_SHIFT 15 | |
| 1000 | #define RT5663_GPIO1_TYPE_EN (0x1 << 15) | |
| 1001 | #define RT5663_GPIO1_TYPE_DIS (0x0 << 15) | |
| 1002 | ||
| 73444723 | 1003 | /* IRQ Control 1 (0x00c1) */ |
| df7c5216 BL |
1004 | #define RT5663_EN_IRQ_JD1_MASK (0x1 << 6) |
| 1005 | #define RT5663_EN_IRQ_JD1_SHIFT 6 | |
| 1006 | #define RT5663_EN_IRQ_JD1_EN (0x1 << 6) | |
| 1007 | #define RT5663_EN_IRQ_JD1_DIS (0x0 << 6) | |
| 7e7e76bd JY |
1008 | #define RT5663_SEL_GPIO1_MASK (0x1 << 2) |
| 1009 | #define RT5663_SEL_GPIO1_SHIFT 6 | |
| 1010 | #define RT5663_SEL_GPIO1_EN (0x1 << 2) | |
| 1011 | #define RT5663_SEL_GPIO1_DIS (0x0 << 2) | |
| df7c5216 | 1012 | |
| 73444723 | 1013 | /* Inline Command Function 2 (0x00dc) */ |
| df7c5216 BL |
1014 | #define RT5663_PWR_MIC_DET_MASK (0x1) |
| 1015 | #define RT5663_PWR_MIC_DET_SHIFT 0 | |
| 1016 | #define RT5663_PWR_MIC_DET_ON (0x1) | |
| 1017 | #define RT5663_PWR_MIC_DET_OFF (0x0) | |
| 1018 | ||
| 73444723 | 1019 | /* Embeeded Jack and Type Detection Control 1 (0x00e6)*/ |
| df7c5216 BL |
1020 | #define RT5663_CBJ_DET_MASK (0x1 << 15) |
| 1021 | #define RT5663_CBJ_DET_SHIFT 15 | |
| 1022 | #define RT5663_CBJ_DET_DIS (0x0 << 15) | |
| 1023 | #define RT5663_CBJ_DET_EN (0x1 << 15) | |
| 1024 | #define RT5663_EXT_JD_MASK (0x1 << 11) | |
| 1025 | #define RT5663_EXT_JD_SHIFT 11 | |
| 1026 | #define RT5663_EXT_JD_EN (0x1 << 11) | |
| 1027 | #define RT5663_EXT_JD_DIS (0x0 << 11) | |
| 1028 | #define RT5663_POL_EXT_JD_MASK (0x1 << 10) | |
| 1029 | #define RT5663_POL_EXT_JD_SHIFT 10 | |
| 1030 | #define RT5663_POL_EXT_JD_EN (0x1 << 10) | |
| 1031 | #define RT5663_POL_EXT_JD_DIS (0x0 << 10) | |
| 958d022e | 1032 | #define RT5663_EM_JD_MASK (0x1 << 7) |
| 1033 | #define RT5663_EM_JD_SHIFT 7 | |
| 1034 | #define RT5663_EM_JD_NOR (0x1 << 7) | |
| 1035 | #define RT5663_EM_JD_RST (0x0 << 7) | |
| df7c5216 | 1036 | |
| 73444723 | 1037 | /* DACREF LDO Control (0x0112)*/ |
| df7c5216 BL |
1038 | #define RT5663_PWR_LDO_DACREFL_MASK (0x1 << 9) |
| 1039 | #define RT5663_PWR_LDO_DACREFL_SHIFT 9 | |
| 1040 | #define RT5663_PWR_LDO_DACREFR_MASK (0x1 << 1) | |
| 1041 | #define RT5663_PWR_LDO_DACREFR_SHIFT 1 | |
| 1042 | ||
| 73444723 | 1043 | /* Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/ |
| df7c5216 BL |
1044 | #define RT5663_DRE_GAIN_HP_MASK (0x1f) |
| 1045 | #define RT5663_DRE_GAIN_HP_SHIFT 0 | |
| 1046 | ||
| 73444723 | 1047 | /* Combo Jack Control (0x0250) */ |
| df7c5216 BL |
1048 | #define RT5663_INBUF_CBJ_BST1_MASK (0x1 << 11) |
| 1049 | #define RT5663_INBUF_CBJ_BST1_SHIFT 11 | |
| 1050 | #define RT5663_INBUF_CBJ_BST1_ON (0x1 << 11) | |
| 1051 | #define RT5663_INBUF_CBJ_BST1_OFF (0x0 << 11) | |
| 1052 | #define RT5663_CBJ_SENSE_BST1_MASK (0x1 << 10) | |
| 1053 | #define RT5663_CBJ_SENSE_BST1_SHIFT 10 | |
| 1054 | #define RT5663_CBJ_SENSE_BST1_L (0x1 << 10) | |
| 1055 | #define RT5663_CBJ_SENSE_BST1_R (0x0 << 10) | |
| 1056 | ||
| 73444723 | 1057 | /* Combo Jack Control (0x0251) */ |
| df7c5216 BL |
1058 | #define RT5663_GAIN_BST1_MASK (0xf) |
| 1059 | #define RT5663_GAIN_BST1_SHIFT 0 | |
| 1060 | ||
| 73444723 | 1061 | /* Dummy register 1 (0x02fa) */ |
| df7c5216 BL |
1062 | #define RT5663_EMB_CLK_MASK (0x1 << 9) |
| 1063 | #define RT5663_EMB_CLK_SHIFT 9 | |
| 1064 | #define RT5663_EMB_CLK_EN (0x1 << 9) | |
| 1065 | #define RT5663_EMB_CLK_DIS (0x0 << 9) | |
| 1066 | #define RT5663_HPA_CPL_BIAS_MASK (0x7 << 6) | |
| 1067 | #define RT5663_HPA_CPL_BIAS_SHIFT 6 | |
| 1068 | #define RT5663_HPA_CPL_BIAS_0_5 (0x0 << 6) | |
| 1069 | #define RT5663_HPA_CPL_BIAS_1 (0x1 << 6) | |
| 1070 | #define RT5663_HPA_CPL_BIAS_2 (0x2 << 6) | |
| 1071 | #define RT5663_HPA_CPL_BIAS_3 (0x3 << 6) | |
| 1072 | #define RT5663_HPA_CPL_BIAS_4_1 (0x4 << 6) | |
| 1073 | #define RT5663_HPA_CPL_BIAS_4_2 (0x5 << 6) | |
| 1074 | #define RT5663_HPA_CPL_BIAS_6 (0x6 << 6) | |
| 1075 | #define RT5663_HPA_CPL_BIAS_8 (0x7 << 6) | |
| 1076 | #define RT5663_HPA_CPR_BIAS_MASK (0x7 << 3) | |
| 1077 | #define RT5663_HPA_CPR_BIAS_SHIFT 3 | |
| 1078 | #define RT5663_HPA_CPR_BIAS_0_5 (0x0 << 3) | |
| 1079 | #define RT5663_HPA_CPR_BIAS_1 (0x1 << 3) | |
| 1080 | #define RT5663_HPA_CPR_BIAS_2 (0x2 << 3) | |
| 1081 | #define RT5663_HPA_CPR_BIAS_3 (0x3 << 3) | |
| 1082 | #define RT5663_HPA_CPR_BIAS_4_1 (0x4 << 3) | |
| 1083 | #define RT5663_HPA_CPR_BIAS_4_2 (0x5 << 3) | |
| 1084 | #define RT5663_HPA_CPR_BIAS_6 (0x6 << 3) | |
| 1085 | #define RT5663_HPA_CPR_BIAS_8 (0x7 << 3) | |
| 1086 | #define RT5663_DUMMY_BIAS_MASK (0x7) | |
| 1087 | #define RT5663_DUMMY_BIAS_SHIFT 0 | |
| 1088 | #define RT5663_DUMMY_BIAS_0_5 (0x0) | |
| 1089 | #define RT5663_DUMMY_BIAS_1 (0x1) | |
| 1090 | #define RT5663_DUMMY_BIAS_2 (0x2) | |
| 1091 | #define RT5663_DUMMY_BIAS_3 (0x3) | |
| 1092 | #define RT5663_DUMMY_BIAS_4_1 (0x4) | |
| 1093 | #define RT5663_DUMMY_BIAS_4_2 (0x5) | |
| 1094 | #define RT5663_DUMMY_BIAS_6 (0x6) | |
| 1095 | #define RT5663_DUMMY_BIAS_8 (0x7) | |
| 1096 | ||
| 1097 | ||
| 1098 | /* System Clock Source */ | |
| 1099 | enum { | |
| 1100 | RT5663_SCLK_S_MCLK, | |
| 1101 | RT5663_SCLK_S_PLL1, | |
| 1102 | RT5663_SCLK_S_RCCLK, | |
| 1103 | }; | |
| 1104 | ||
| 1105 | /* PLL1 Source */ | |
| 1106 | enum { | |
| 1107 | RT5663_PLL1_S_MCLK, | |
| 1108 | RT5663_PLL1_S_BCLK1, | |
| 1109 | }; | |
| 1110 | ||
| 1111 | enum { | |
| 1112 | RT5663_AIF, | |
| 1113 | RT5663_AIFS, | |
| 1114 | }; | |
| 1115 | ||
| 1116 | /* asrc clock source */ | |
| 1117 | enum { | |
| 1118 | RT5663_CLK_SEL_SYS = 0x0, | |
| 1119 | RT5663_CLK_SEL_I2S1_ASRC = 0x1, | |
| 1120 | }; | |
| 1121 | ||
| 1122 | /* filter mask */ | |
| 1123 | enum { | |
| 1124 | RT5663_DA_STEREO_FILTER = 0x1, | |
| 1125 | RT5663_AD_STEREO_FILTER = 0x2, | |
| 1126 | }; | |
| 1127 | ||
| 1128 | int rt5663_set_jack_detect(struct snd_soc_codec *codec, | |
| 1129 | struct snd_soc_jack *hs_jack); | |
| 1130 | int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec, | |
| 1131 | unsigned int filter_mask, unsigned int clk_src); | |
| 1132 | ||
| 1133 | #endif /* __RT5663_H__ */ |