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[mirror_ubuntu-jammy-kernel.git] / sound / soc / codecs / rt5670.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
5e8351de
BL		 2/*
3 * rt5670.c -- RT5670 ALSA SoC audio codec driver
4 *
5 * Copyright 2014 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
5e8351de
BL		 7 */
8
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/pm.h>
64e89e5f 14#include <linux/pm_runtime.h>
5e8351de
BL		 15#include <linux/i2c.h>
16#include <linux/platform_device.h>
0605815e 17#include <linux/acpi.h>
5e8351de 18#include <linux/spi/spi.h>
223c055a 19#include <linux/dmi.h>
5e8351de
BL		 20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/jack.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <sound/rt5670.h>
29
30#include "rl6231.h"
31#include "rt5670.h"
32#include "rt5670-dsp.h"
33
8e1b1785
PLB		 34#define RT5670_DEV_GPIO BIT(0)
35#define RT5670_IN2_DIFF BIT(1)
36#define RT5670_DMIC_EN BIT(2)
37#define RT5670_DMIC1_IN2P BIT(3)
38#define RT5670_DMIC1_GPIO6 BIT(4)
39#define RT5670_DMIC1_GPIO7 BIT(5)
40#define RT5670_DMIC2_INR BIT(6)
41#define RT5670_DMIC2_GPIO8 BIT(7)
42#define RT5670_DMIC3_GPIO5 BIT(8)
43#define RT5670_JD_MODE1 BIT(9)
44#define RT5670_JD_MODE2 BIT(10)
45#define RT5670_JD_MODE3 BIT(11)
46
47static unsigned long rt5670_quirk;
48static unsigned int quirk_override;
49module_param_named(quirk, quirk_override, uint, 0444);
50MODULE_PARM_DESC(quirk, "Board-specific quirk override");
51
5e8351de
BL		 52#define RT5670_DEVICE_ID 0x6271
53
54#define RT5670_PR_RANGE_BASE (0xff + 1)
55#define RT5670_PR_SPACING 0x100
56
57#define RT5670_PR_BASE (RT5670_PR_RANGE_BASE + (0 * RT5670_PR_SPACING))
58
59static const struct regmap_range_cfg rt5670_ranges[] = {
60 { .name = "PR", .range_min = RT5670_PR_BASE,
61 .range_max = RT5670_PR_BASE + 0xf8,
62 .selector_reg = RT5670_PRIV_INDEX,
63 .selector_mask = 0xff,
64 .selector_shift = 0x0,
65 .window_start = RT5670_PRIV_DATA,
66 .window_len = 0x1, },
67};
68
8019ff6c 69static const struct reg_sequence init_list[] = {
5e8351de 70 { RT5670_PR_BASE + 0x14, 0x9a8a },
81dd1c5d 71 { RT5670_PR_BASE + 0x38, 0x1fe1 },
5e8351de 72 { RT5670_PR_BASE + 0x3d, 0x3640 },
874352a7 73 { 0x8a, 0x0123 },
5e8351de 74};
5e8351de
BL		 75
76static const struct reg_default rt5670_reg[] = {
77 { 0x00, 0x0000 },
78 { 0x02, 0x8888 },
79 { 0x03, 0x8888 },
80 { 0x0a, 0x0001 },
81 { 0x0b, 0x0827 },
82 { 0x0c, 0x0000 },
83 { 0x0d, 0x0008 },
84 { 0x0e, 0x0000 },
85 { 0x0f, 0x0808 },
86 { 0x19, 0xafaf },
87 { 0x1a, 0xafaf },
88 { 0x1b, 0x0011 },
89 { 0x1c, 0x2f2f },
90 { 0x1d, 0x2f2f },
91 { 0x1e, 0x0000 },
92 { 0x1f, 0x2f2f },
93 { 0x20, 0x0000 },
94 { 0x26, 0x7860 },
95 { 0x27, 0x7860 },
96 { 0x28, 0x7871 },
97 { 0x29, 0x8080 },
98 { 0x2a, 0x5656 },
99 { 0x2b, 0x5454 },
100 { 0x2c, 0xaaa0 },
101 { 0x2d, 0x0000 },
102 { 0x2e, 0x2f2f },
103 { 0x2f, 0x1002 },
104 { 0x30, 0x0000 },
105 { 0x31, 0x5f00 },
106 { 0x32, 0x0000 },
107 { 0x33, 0x0000 },
108 { 0x34, 0x0000 },
109 { 0x35, 0x0000 },
110 { 0x36, 0x0000 },
111 { 0x37, 0x0000 },
112 { 0x38, 0x0000 },
113 { 0x3b, 0x0000 },
114 { 0x3c, 0x007f },
115 { 0x3d, 0x0000 },
116 { 0x3e, 0x007f },
117 { 0x45, 0xe00f },
118 { 0x4c, 0x5380 },
119 { 0x4f, 0x0073 },
120 { 0x52, 0x00d3 },
ac87f221 121 { 0x53, 0xf000 },
5e8351de
BL		 122 { 0x61, 0x0000 },
123 { 0x62, 0x0001 },
124 { 0x63, 0x00c3 },
125 { 0x64, 0x0000 },
ac87f221 126 { 0x65, 0x0001 },
5e8351de
BL		 127 { 0x66, 0x0000 },
128 { 0x6f, 0x8000 },
129 { 0x70, 0x8000 },
130 { 0x71, 0x8000 },
131 { 0x72, 0x8000 },
ac87f221 132 { 0x73, 0x7770 },
5e8351de
BL		 133 { 0x74, 0x0e00 },
134 { 0x75, 0x1505 },
135 { 0x76, 0x0015 },
136 { 0x77, 0x0c00 },
137 { 0x78, 0x4000 },
138 { 0x79, 0x0123 },
139 { 0x7f, 0x1100 },
140 { 0x80, 0x0000 },
141 { 0x81, 0x0000 },
142 { 0x82, 0x0000 },
143 { 0x83, 0x0000 },
144 { 0x84, 0x0000 },
145 { 0x85, 0x0000 },
ac87f221 146 { 0x86, 0x0004 },
5e8351de
BL		 147 { 0x87, 0x0000 },
148 { 0x88, 0x0000 },
149 { 0x89, 0x0000 },
874352a7 150 { 0x8a, 0x0123 },
5e8351de 151 { 0x8b, 0x0000 },
ac87f221 152 { 0x8c, 0x0003 },
5e8351de
BL		 153 { 0x8d, 0x0000 },
154 { 0x8e, 0x0004 },
155 { 0x8f, 0x1100 },
156 { 0x90, 0x0646 },
157 { 0x91, 0x0c06 },
158 { 0x93, 0x0000 },
ac87f221
BL		 159 { 0x94, 0x1270 },
160 { 0x95, 0x1000 },
5e8351de
BL		 161 { 0x97, 0x0000 },
162 { 0x98, 0x0000 },
163 { 0x99, 0x0000 },
164 { 0x9a, 0x2184 },
165 { 0x9b, 0x010a },
166 { 0x9c, 0x0aea },
167 { 0x9d, 0x000c },
168 { 0x9e, 0x0400 },
169 { 0xae, 0x7000 },
170 { 0xaf, 0x0000 },
ac87f221 171 { 0xb0, 0x7000 },
5e8351de
BL		 172 { 0xb1, 0x0000 },
173 { 0xb2, 0x0000 },
174 { 0xb3, 0x001f },
ac87f221 175 { 0xb4, 0x220c },
5e8351de
BL		 176 { 0xb5, 0x1f00 },
177 { 0xb6, 0x0000 },
178 { 0xb7, 0x0000 },
179 { 0xbb, 0x0000 },
180 { 0xbc, 0x0000 },
181 { 0xbd, 0x0000 },
182 { 0xbe, 0x0000 },
183 { 0xbf, 0x0000 },
184 { 0xc0, 0x0000 },
185 { 0xc1, 0x0000 },
186 { 0xc2, 0x0000 },
187 { 0xcd, 0x0000 },
188 { 0xce, 0x0000 },
189 { 0xcf, 0x1813 },
190 { 0xd0, 0x0690 },
191 { 0xd1, 0x1c17 },
ac87f221 192 { 0xd3, 0xa220 },
5e8351de
BL		 193 { 0xd4, 0x0000 },
194 { 0xd6, 0x0400 },
195 { 0xd9, 0x0809 },
196 { 0xda, 0x0000 },
197 { 0xdb, 0x0001 },
198 { 0xdc, 0x0049 },
ac87f221 199 { 0xdd, 0x0024 },
5e8351de
BL		 200 { 0xe6, 0x8000 },
201 { 0xe7, 0x0000 },
ac87f221 202 { 0xec, 0xa200 },
5e8351de 203 { 0xed, 0x0000 },
ac87f221 204 { 0xee, 0xa200 },
5e8351de
BL		 205 { 0xef, 0x0000 },
206 { 0xf8, 0x0000 },
207 { 0xf9, 0x0000 },
208 { 0xfa, 0x8010 },
209 { 0xfb, 0x0033 },
ac87f221 210 { 0xfc, 0x0100 },
5e8351de
BL		 211};
212
213static bool rt5670_volatile_register(struct device *dev, unsigned int reg)
214{
215 int i;
216
217 for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
218 if ((reg >= rt5670_ranges[i].window_start &&
219 reg <= rt5670_ranges[i].window_start +
220 rt5670_ranges[i].window_len) ||
221 (reg >= rt5670_ranges[i].range_min &&
222 reg <= rt5670_ranges[i].range_max)) {
223 return true;
224 }
225 }
226
227 switch (reg) {
228 case RT5670_RESET:
229 case RT5670_PDM_DATA_CTRL1:
230 case RT5670_PDM1_DATA_CTRL4:
231 case RT5670_PDM2_DATA_CTRL4:
232 case RT5670_PRIV_DATA:
233 case RT5670_ASRC_5:
234 case RT5670_CJ_CTRL1:
235 case RT5670_CJ_CTRL2:
236 case RT5670_CJ_CTRL3:
237 case RT5670_A_JD_CTRL1:
238 case RT5670_A_JD_CTRL2:
239 case RT5670_VAD_CTRL5:
240 case RT5670_ADC_EQ_CTRL1:
241 case RT5670_EQ_CTRL1:
242 case RT5670_ALC_CTRL_1:
5e8351de
BL		 243 case RT5670_IRQ_CTRL2:
244 case RT5670_INT_IRQ_ST:
245 case RT5670_IL_CMD:
246 case RT5670_DSP_CTRL1:
247 case RT5670_DSP_CTRL2:
248 case RT5670_DSP_CTRL3:
249 case RT5670_DSP_CTRL4:
250 case RT5670_DSP_CTRL5:
251 case RT5670_VENDOR_ID:
252 case RT5670_VENDOR_ID1:
253 case RT5670_VENDOR_ID2:
254 return true;
255 default:
256 return false;
257 }
258}
259
260static bool rt5670_readable_register(struct device *dev, unsigned int reg)
261{
262 int i;
263
264 for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
265 if ((reg >= rt5670_ranges[i].window_start &&
266 reg <= rt5670_ranges[i].window_start +
267 rt5670_ranges[i].window_len) ||
268 (reg >= rt5670_ranges[i].range_min &&
269 reg <= rt5670_ranges[i].range_max)) {
270 return true;
271 }
272 }
273
274 switch (reg) {
275 case RT5670_RESET:
276 case RT5670_HP_VOL:
277 case RT5670_LOUT1:
278 case RT5670_CJ_CTRL1:
279 case RT5670_CJ_CTRL2:
280 case RT5670_CJ_CTRL3:
281 case RT5670_IN2:
282 case RT5670_INL1_INR1_VOL:
283 case RT5670_DAC1_DIG_VOL:
284 case RT5670_DAC2_DIG_VOL:
285 case RT5670_DAC_CTRL:
286 case RT5670_STO1_ADC_DIG_VOL:
287 case RT5670_MONO_ADC_DIG_VOL:
288 case RT5670_STO2_ADC_DIG_VOL:
289 case RT5670_ADC_BST_VOL1:
290 case RT5670_ADC_BST_VOL2:
291 case RT5670_STO2_ADC_MIXER:
292 case RT5670_STO1_ADC_MIXER:
293 case RT5670_MONO_ADC_MIXER:
294 case RT5670_AD_DA_MIXER:
295 case RT5670_STO_DAC_MIXER:
296 case RT5670_DD_MIXER:
297 case RT5670_DIG_MIXER:
298 case RT5670_DSP_PATH1:
299 case RT5670_DSP_PATH2:
300 case RT5670_DIG_INF1_DATA:
301 case RT5670_DIG_INF2_DATA:
302 case RT5670_PDM_OUT_CTRL:
303 case RT5670_PDM_DATA_CTRL1:
304 case RT5670_PDM1_DATA_CTRL2:
305 case RT5670_PDM1_DATA_CTRL3:
306 case RT5670_PDM1_DATA_CTRL4:
307 case RT5670_PDM2_DATA_CTRL2:
308 case RT5670_PDM2_DATA_CTRL3:
309 case RT5670_PDM2_DATA_CTRL4:
310 case RT5670_REC_L1_MIXER:
311 case RT5670_REC_L2_MIXER:
312 case RT5670_REC_R1_MIXER:
313 case RT5670_REC_R2_MIXER:
314 case RT5670_HPO_MIXER:
315 case RT5670_MONO_MIXER:
316 case RT5670_OUT_L1_MIXER:
317 case RT5670_OUT_R1_MIXER:
318 case RT5670_LOUT_MIXER:
319 case RT5670_PWR_DIG1:
320 case RT5670_PWR_DIG2:
321 case RT5670_PWR_ANLG1:
322 case RT5670_PWR_ANLG2:
323 case RT5670_PWR_MIXER:
324 case RT5670_PWR_VOL:
325 case RT5670_PRIV_INDEX:
326 case RT5670_PRIV_DATA:
327 case RT5670_I2S4_SDP:
328 case RT5670_I2S1_SDP:
329 case RT5670_I2S2_SDP:
330 case RT5670_I2S3_SDP:
331 case RT5670_ADDA_CLK1:
332 case RT5670_ADDA_CLK2:
333 case RT5670_DMIC_CTRL1:
334 case RT5670_DMIC_CTRL2:
335 case RT5670_TDM_CTRL_1:
336 case RT5670_TDM_CTRL_2:
337 case RT5670_TDM_CTRL_3:
338 case RT5670_DSP_CLK:
339 case RT5670_GLB_CLK:
340 case RT5670_PLL_CTRL1:
341 case RT5670_PLL_CTRL2:
342 case RT5670_ASRC_1:
343 case RT5670_ASRC_2:
344 case RT5670_ASRC_3:
345 case RT5670_ASRC_4:
346 case RT5670_ASRC_5:
347 case RT5670_ASRC_7:
348 case RT5670_ASRC_8:
349 case RT5670_ASRC_9:
350 case RT5670_ASRC_10:
351 case RT5670_ASRC_11:
352 case RT5670_ASRC_12:
353 case RT5670_ASRC_13:
354 case RT5670_ASRC_14:
355 case RT5670_DEPOP_M1:
356 case RT5670_DEPOP_M2:
357 case RT5670_DEPOP_M3:
358 case RT5670_CHARGE_PUMP:
359 case RT5670_MICBIAS:
360 case RT5670_A_JD_CTRL1:
361 case RT5670_A_JD_CTRL2:
362 case RT5670_VAD_CTRL1:
363 case RT5670_VAD_CTRL2:
364 case RT5670_VAD_CTRL3:
365 case RT5670_VAD_CTRL4:
366 case RT5670_VAD_CTRL5:
367 case RT5670_ADC_EQ_CTRL1:
368 case RT5670_ADC_EQ_CTRL2:
369 case RT5670_EQ_CTRL1:
370 case RT5670_EQ_CTRL2:
371 case RT5670_ALC_DRC_CTRL1:
372 case RT5670_ALC_DRC_CTRL2:
373 case RT5670_ALC_CTRL_1:
374 case RT5670_ALC_CTRL_2:
375 case RT5670_ALC_CTRL_3:
376 case RT5670_JD_CTRL:
377 case RT5670_IRQ_CTRL1:
378 case RT5670_IRQ_CTRL2:
379 case RT5670_INT_IRQ_ST:
380 case RT5670_GPIO_CTRL1:
381 case RT5670_GPIO_CTRL2:
382 case RT5670_GPIO_CTRL3:
383 case RT5670_SCRABBLE_FUN:
384 case RT5670_SCRABBLE_CTRL:
385 case RT5670_BASE_BACK:
386 case RT5670_MP3_PLUS1:
387 case RT5670_MP3_PLUS2:
388 case RT5670_ADJ_HPF1:
389 case RT5670_ADJ_HPF2:
390 case RT5670_HP_CALIB_AMP_DET:
391 case RT5670_SV_ZCD1:
392 case RT5670_SV_ZCD2:
393 case RT5670_IL_CMD:
394 case RT5670_IL_CMD2:
395 case RT5670_IL_CMD3:
396 case RT5670_DRC_HL_CTRL1:
397 case RT5670_DRC_HL_CTRL2:
398 case RT5670_ADC_MONO_HP_CTRL1:
399 case RT5670_ADC_MONO_HP_CTRL2:
400 case RT5670_ADC_STO2_HP_CTRL1:
401 case RT5670_ADC_STO2_HP_CTRL2:
402 case RT5670_JD_CTRL3:
403 case RT5670_JD_CTRL4:
404 case RT5670_DIG_MISC:
405 case RT5670_DSP_CTRL1:
406 case RT5670_DSP_CTRL2:
407 case RT5670_DSP_CTRL3:
408 case RT5670_DSP_CTRL4:
409 case RT5670_DSP_CTRL5:
410 case RT5670_GEN_CTRL2:
411 case RT5670_GEN_CTRL3:
412 case RT5670_VENDOR_ID:
413 case RT5670_VENDOR_ID1:
414 case RT5670_VENDOR_ID2:
415 return true;
416 default:
417 return false;
418 }
419}
420
d3ef7054
BL		 421/**
422 * rt5670_headset_detect - Detect headset.
5ba04c66 423 * @component: SoC audio component device.
d3ef7054
BL		 424 * @jack_insert: Jack insert or not.
425 *
426 * Detect whether is headset or not when jack inserted.
427 *
428 * Returns detect status.
429 */
430
5ba04c66 431static int rt5670_headset_detect(struct snd_soc_component *component, int jack_insert)
d3ef7054
BL		 432{
433 int val;
5ba04c66
KM		 434 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
435 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
d3ef7054
BL		 436
437 if (jack_insert) {
6d8135ff
LPC		 438 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
439 snd_soc_dapm_sync(dapm);
5ba04c66
KM		 440 snd_soc_component_update_bits(component, RT5670_GEN_CTRL3, 0x4, 0x0);
441 snd_soc_component_update_bits(component, RT5670_CJ_CTRL2,
d3ef7054
BL		 442 RT5670_CBJ_DET_MODE | RT5670_CBJ_MN_JD,
443 RT5670_CBJ_MN_JD);
5ba04c66
KM		 444 snd_soc_component_write(component, RT5670_GPIO_CTRL2, 0x0004);
445 snd_soc_component_update_bits(component, RT5670_GPIO_CTRL1,
d3ef7054 446 RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_IRQ);
5ba04c66 447 snd_soc_component_update_bits(component, RT5670_CJ_CTRL1,
d3ef7054 448 RT5670_CBJ_BST1_EN, RT5670_CBJ_BST1_EN);
5ba04c66
KM		 449 snd_soc_component_write(component, RT5670_JD_CTRL3, 0x00f0);
450 snd_soc_component_update_bits(component, RT5670_CJ_CTRL2,
d3ef7054 451 RT5670_CBJ_MN_JD, RT5670_CBJ_MN_JD);
5ba04c66 452 snd_soc_component_update_bits(component, RT5670_CJ_CTRL2,
d3ef7054
BL		 453 RT5670_CBJ_MN_JD, 0);
454 msleep(300);
5ba04c66 455 val = snd_soc_component_read32(component, RT5670_CJ_CTRL3) & 0x7;
d3ef7054
BL		 456 if (val == 0x1 || val == 0x2) {
457 rt5670->jack_type = SND_JACK_HEADSET;
458 /* for push button */
5ba04c66
KM		 459 snd_soc_component_update_bits(component, RT5670_INT_IRQ_ST, 0x8, 0x8);
460 snd_soc_component_update_bits(component, RT5670_IL_CMD, 0x40, 0x40);
461 snd_soc_component_read32(component, RT5670_IL_CMD);
d3ef7054 462 } else {
5ba04c66 463 snd_soc_component_update_bits(component, RT5670_GEN_CTRL3, 0x4, 0x4);
d3ef7054 464 rt5670->jack_type = SND_JACK_HEADPHONE;
6d8135ff
LPC		 465 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
466 snd_soc_dapm_sync(dapm);
d3ef7054
BL		 467 }
468 } else {
5ba04c66
KM		 469 snd_soc_component_update_bits(component, RT5670_INT_IRQ_ST, 0x8, 0x0);
470 snd_soc_component_update_bits(component, RT5670_GEN_CTRL3, 0x4, 0x4);
d3ef7054 471 rt5670->jack_type = 0;
6d8135ff
LPC		 472 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
473 snd_soc_dapm_sync(dapm);
d3ef7054
BL		 474 }
475
476 return rt5670->jack_type;
477}
478
5ba04c66 479void rt5670_jack_suspend(struct snd_soc_component *component)
cc3c340d 480{
5ba04c66 481 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
cc3c340d
BL		 482
483 rt5670->jack_type_saved = rt5670->jack_type;
5ba04c66 484 rt5670_headset_detect(component, 0);
cc3c340d
BL		 485}
486EXPORT_SYMBOL_GPL(rt5670_jack_suspend);
487
5ba04c66 488void rt5670_jack_resume(struct snd_soc_component *component)
cc3c340d 489{
5ba04c66 490 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
cc3c340d
BL		 491
492 if (rt5670->jack_type_saved)
5ba04c66 493 rt5670_headset_detect(component, 1);
cc3c340d
BL		 494}
495EXPORT_SYMBOL_GPL(rt5670_jack_resume);
496
5ba04c66 497static int rt5670_button_detect(struct snd_soc_component *component)
d3ef7054
BL		 498{
499 int btn_type, val;
500
5ba04c66 501 val = snd_soc_component_read32(component, RT5670_IL_CMD);
d3ef7054 502 btn_type = val & 0xff80;
5ba04c66 503 snd_soc_component_write(component, RT5670_IL_CMD, val);
d3ef7054
BL		 504 if (btn_type != 0) {
505 msleep(20);
5ba04c66
KM		 506 val = snd_soc_component_read32(component, RT5670_IL_CMD);
507 snd_soc_component_write(component, RT5670_IL_CMD, val);
d3ef7054
BL		 508 }
509
510 return btn_type;
511}
512
513static int rt5670_irq_detection(void *data)
514{
515 struct rt5670_priv *rt5670 = (struct rt5670_priv *)data;
516 struct snd_soc_jack_gpio *gpio = &rt5670->hp_gpio;
517 struct snd_soc_jack *jack = rt5670->jack;
518 int val, btn_type, report = jack->status;
519
520 if (rt5670->pdata.jd_mode == 1) /* 2 port */
5ba04c66 521 val = snd_soc_component_read32(rt5670->component, RT5670_A_JD_CTRL1) & 0x0070;
d3ef7054 522 else
5ba04c66 523 val = snd_soc_component_read32(rt5670->component, RT5670_A_JD_CTRL1) & 0x0020;
d3ef7054
BL		 524
525 switch (val) {
526 /* jack in */
527 case 0x30: /* 2 port */
528 case 0x0: /* 1 port or 2 port */
529 if (rt5670->jack_type == 0) {
5ba04c66 530 report = rt5670_headset_detect(rt5670->component, 1);
d3ef7054
BL		 531 /* for push button and jack out */
532 gpio->debounce_time = 25;
533 break;
534 }
535 btn_type = 0;
5ba04c66 536 if (snd_soc_component_read32(rt5670->component, RT5670_INT_IRQ_ST) & 0x4) {
d3ef7054
BL		 537 /* button pressed */
538 report = SND_JACK_HEADSET;
5ba04c66 539 btn_type = rt5670_button_detect(rt5670->component);
d3ef7054
BL		 540 switch (btn_type) {
541 case 0x2000: /* up */
542 report |= SND_JACK_BTN_1;
543 break;
544 case 0x0400: /* center */
545 report |= SND_JACK_BTN_0;
546 break;
547 case 0x0080: /* down */
548 report |= SND_JACK_BTN_2;
549 break;
550 default:
5ba04c66 551 dev_err(rt5670->component->dev,
d3ef7054
BL		 552 "Unexpected button code 0x%04x\n",
553 btn_type);
554 break;
555 }
556 }
557 if (btn_type == 0)/* button release */
558 report = rt5670->jack_type;
559
560 break;
561 /* jack out */
562 case 0x70: /* 2 port */
563 case 0x10: /* 2 port */
564 case 0x20: /* 1 port */
565 report = 0;
5ba04c66
KM		 566 snd_soc_component_update_bits(rt5670->component, RT5670_INT_IRQ_ST, 0x1, 0x0);
567 rt5670_headset_detect(rt5670->component, 0);
d3ef7054
BL		 568 gpio->debounce_time = 150; /* for jack in */
569 break;
570 default:
571 break;
572 }
573
574 return report;
575}
576
5ba04c66 577int rt5670_set_jack_detect(struct snd_soc_component *component,
d3ef7054
BL		 578 struct snd_soc_jack *jack)
579{
5ba04c66 580 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
d3ef7054
BL		 581 int ret;
582
583 rt5670->jack = jack;
5ba04c66 584 rt5670->hp_gpio.gpiod_dev = component->dev;
804e73ad 585 rt5670->hp_gpio.name = "headset";
d3ef7054
BL		 586 rt5670->hp_gpio.report = SND_JACK_HEADSET |
587 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2;
588 rt5670->hp_gpio.debounce_time = 150;
589 rt5670->hp_gpio.wake = true;
590 rt5670->hp_gpio.data = (struct rt5670_priv *)rt5670;
591 rt5670->hp_gpio.jack_status_check = rt5670_irq_detection;
592
593 ret = snd_soc_jack_add_gpios(rt5670->jack, 1,
594 &rt5670->hp_gpio);
595 if (ret) {
5ba04c66 596 dev_err(component->dev, "Adding jack GPIO failed\n");
d3ef7054
BL		 597 return ret;
598 }
599
600 return 0;
601}
602EXPORT_SYMBOL_GPL(rt5670_set_jack_detect);
603
5e8351de
BL		 604static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
605static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
606static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
607static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
608static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
609
610/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
dea6d32e 611static const DECLARE_TLV_DB_RANGE(bst_tlv,
5e8351de
BL		 612 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
613 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
614 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
615 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
616 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
617 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
dea6d32e
LPC		 618 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
619);
5e8351de
BL		 620
621/* Interface data select */
622static const char * const rt5670_data_select[] = {
623 "Normal", "Swap", "left copy to right", "right copy to left"
624};
625
01957572 626static SOC_ENUM_SINGLE_DECL(rt5670_if2_dac_enum, RT5670_DIG_INF1_DATA,
5e8351de
BL		 627 RT5670_IF2_DAC_SEL_SFT, rt5670_data_select);
628
01957572 629static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_enum, RT5670_DIG_INF1_DATA,
5e8351de
BL		 630 RT5670_IF2_ADC_SEL_SFT, rt5670_data_select);
631
632static const struct snd_kcontrol_new rt5670_snd_controls[] = {
633 /* Headphone Output Volume */
634 SOC_DOUBLE("HP Playback Switch", RT5670_HP_VOL,
635 RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
636 SOC_DOUBLE_TLV("HP Playback Volume", RT5670_HP_VOL,
637 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
e1f42a2f 638 39, 1, out_vol_tlv),
5e8351de
BL		 639 /* OUTPUT Control */
640 SOC_DOUBLE("OUT Channel Switch", RT5670_LOUT1,
641 RT5670_VOL_L_SFT, RT5670_VOL_R_SFT, 1, 1),
642 SOC_DOUBLE_TLV("OUT Playback Volume", RT5670_LOUT1,
643 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT, 39, 1, out_vol_tlv),
644 /* DAC Digital Volume */
645 SOC_DOUBLE("DAC2 Playback Switch", RT5670_DAC_CTRL,
646 RT5670_M_DAC_L2_VOL_SFT, RT5670_M_DAC_R2_VOL_SFT, 1, 1),
647 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5670_DAC1_DIG_VOL,
648 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
649 175, 0, dac_vol_tlv),
650 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5670_DAC2_DIG_VOL,
651 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
652 175, 0, dac_vol_tlv),
653 /* IN1/IN2 Control */
654 SOC_SINGLE_TLV("IN1 Boost Volume", RT5670_CJ_CTRL1,
655 RT5670_BST_SFT1, 8, 0, bst_tlv),
656 SOC_SINGLE_TLV("IN2 Boost Volume", RT5670_IN2,
657 RT5670_BST_SFT1, 8, 0, bst_tlv),
658 /* INL/INR Volume Control */
659 SOC_DOUBLE_TLV("IN Capture Volume", RT5670_INL1_INR1_VOL,
660 RT5670_INL_VOL_SFT, RT5670_INR_VOL_SFT,
661 31, 1, in_vol_tlv),
662 /* ADC Digital Volume Control */
663 SOC_DOUBLE("ADC Capture Switch", RT5670_STO1_ADC_DIG_VOL,
664 RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
665 SOC_DOUBLE_TLV("ADC Capture Volume", RT5670_STO1_ADC_DIG_VOL,
666 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
667 127, 0, adc_vol_tlv),
668
669 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5670_MONO_ADC_DIG_VOL,
670 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
671 127, 0, adc_vol_tlv),
672
673 /* ADC Boost Volume Control */
674 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
675 RT5670_STO1_ADC_L_BST_SFT, RT5670_STO1_ADC_R_BST_SFT,
676 3, 0, adc_bst_tlv),
677
678 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
679 RT5670_STO2_ADC_L_BST_SFT, RT5670_STO2_ADC_R_BST_SFT,
680 3, 0, adc_bst_tlv),
681
682 SOC_ENUM("ADC IF2 Data Switch", rt5670_if2_adc_enum),
683 SOC_ENUM("DAC IF2 Data Switch", rt5670_if2_dac_enum),
684};
685
686/**
687 * set_dmic_clk - Set parameter of dmic.
688 *
689 * @w: DAPM widget.
690 * @kcontrol: The kcontrol of this widget.
691 * @event: Event id.
692 *
693 * Choose dmic clock between 1MHz and 3MHz.
694 * It is better for clock to approximate 3MHz.
695 */
696static int set_dmic_clk(struct snd_soc_dapm_widget *w,
697 struct snd_kcontrol *kcontrol, int event)
698{
5ba04c66
KM		 699 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
700 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
00a6d6e5 701 int idx, rate;
5e8351de 702
00a6d6e5
OC		 703 rate = rt5670->sysclk / rl6231_get_pre_div(rt5670->regmap,
704 RT5670_ADDA_CLK1, RT5670_I2S_PD1_SFT);
705 idx = rl6231_calc_dmic_clk(rate);
5e8351de 706 if (idx < 0)
5ba04c66 707 dev_err(component->dev, "Failed to set DMIC clock\n");
5e8351de 708 else
5ba04c66 709 snd_soc_component_update_bits(component, RT5670_DMIC_CTRL1,
5e8351de
BL		 710 RT5670_DMIC_CLK_MASK, idx << RT5670_DMIC_CLK_SFT);
711 return idx;
712}
713
714static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
715 struct snd_soc_dapm_widget *sink)
716{
5ba04c66
KM		 717 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
718 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de 719
485372dc 720 if (rt5670->sysclk_src == RT5670_SCLK_S_PLL1)
5e8351de
BL		 721 return 1;
722 else
723 return 0;
724}
725
726static int is_using_asrc(struct snd_soc_dapm_widget *source,
727 struct snd_soc_dapm_widget *sink)
728{
5ba04c66 729 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
5e8351de
BL		 730 unsigned int reg, shift, val;
731
732 switch (source->shift) {
733 case 0:
734 reg = RT5670_ASRC_3;
735 shift = 0;
736 break;
737 case 1:
738 reg = RT5670_ASRC_3;
739 shift = 4;
740 break;
741 case 2:
742 reg = RT5670_ASRC_5;
743 shift = 12;
744 break;
745 case 3:
746 reg = RT5670_ASRC_2;
747 shift = 0;
748 break;
749 case 8:
750 reg = RT5670_ASRC_2;
751 shift = 4;
752 break;
753 case 9:
754 reg = RT5670_ASRC_2;
755 shift = 8;
756 break;
757 case 10:
758 reg = RT5670_ASRC_2;
759 shift = 12;
760 break;
761 default:
762 return 0;
763 }
764
5ba04c66 765 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
5e8351de
BL		 766 switch (val) {
767 case 1:
768 case 2:
769 case 3:
770 case 4:
771 return 1;
772 default:
773 return 0;
774 }
775
776}
777
e50334d4
BL		 778static int can_use_asrc(struct snd_soc_dapm_widget *source,
779 struct snd_soc_dapm_widget *sink)
780{
5ba04c66
KM		 781 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
782 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
e50334d4
BL		 783
784 if (rt5670->sysclk > rt5670->lrck[RT5670_AIF1] * 384)
785 return 1;
786
787 return 0;
788}
789
ea232b3f
ML		 790
791/**
792 * rt5670_sel_asrc_clk_src - select ASRC clock source for a set of filters
5ba04c66 793 * @component: SoC audio component device.
ea232b3f
ML		 794 * @filter_mask: mask of filters.
795 * @clk_src: clock source
796 *
797 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5670 can
798 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
799 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
800 * ASRC function will track i2s clock and generate a corresponding system clock
801 * for codec. This function provides an API to select the clock source for a
802 * set of filters specified by the mask. And the codec driver will turn on ASRC
803 * for these filters if ASRC is selected as their clock source.
804 */
5ba04c66 805int rt5670_sel_asrc_clk_src(struct snd_soc_component *component,
ea232b3f
ML		 806 unsigned int filter_mask, unsigned int clk_src)
807{
808 unsigned int asrc2_mask = 0, asrc2_value = 0;
809 unsigned int asrc3_mask = 0, asrc3_value = 0;
810
811 if (clk_src > RT5670_CLK_SEL_SYS3)
812 return -EINVAL;
813
814 if (filter_mask & RT5670_DA_STEREO_FILTER) {
815 asrc2_mask |= RT5670_DA_STO_CLK_SEL_MASK;
816 asrc2_value = (asrc2_value & ~RT5670_DA_STO_CLK_SEL_MASK)
817 | (clk_src << RT5670_DA_STO_CLK_SEL_SFT);
818 }
819
820 if (filter_mask & RT5670_DA_MONO_L_FILTER) {
821 asrc2_mask |= RT5670_DA_MONOL_CLK_SEL_MASK;
822 asrc2_value = (asrc2_value & ~RT5670_DA_MONOL_CLK_SEL_MASK)
823 | (clk_src << RT5670_DA_MONOL_CLK_SEL_SFT);
824 }
825
826 if (filter_mask & RT5670_DA_MONO_R_FILTER) {
827 asrc2_mask |= RT5670_DA_MONOR_CLK_SEL_MASK;
828 asrc2_value = (asrc2_value & ~RT5670_DA_MONOR_CLK_SEL_MASK)
829 | (clk_src << RT5670_DA_MONOR_CLK_SEL_SFT);
830 }
831
832 if (filter_mask & RT5670_AD_STEREO_FILTER) {
833 asrc2_mask |= RT5670_AD_STO1_CLK_SEL_MASK;
834 asrc2_value = (asrc2_value & ~RT5670_AD_STO1_CLK_SEL_MASK)
835 | (clk_src << RT5670_AD_STO1_CLK_SEL_SFT);
836 }
837
838 if (filter_mask & RT5670_AD_MONO_L_FILTER) {
839 asrc3_mask |= RT5670_AD_MONOL_CLK_SEL_MASK;
840 asrc3_value = (asrc3_value & ~RT5670_AD_MONOL_CLK_SEL_MASK)
841 | (clk_src << RT5670_AD_MONOL_CLK_SEL_SFT);
842 }
843
844 if (filter_mask & RT5670_AD_MONO_R_FILTER) {
845 asrc3_mask |= RT5670_AD_MONOR_CLK_SEL_MASK;
846 asrc3_value = (asrc3_value & ~RT5670_AD_MONOR_CLK_SEL_MASK)
847 | (clk_src << RT5670_AD_MONOR_CLK_SEL_SFT);
848 }
849
850 if (filter_mask & RT5670_UP_RATE_FILTER) {
851 asrc3_mask |= RT5670_UP_CLK_SEL_MASK;
852 asrc3_value = (asrc3_value & ~RT5670_UP_CLK_SEL_MASK)
853 | (clk_src << RT5670_UP_CLK_SEL_SFT);
854 }
855
856 if (filter_mask & RT5670_DOWN_RATE_FILTER) {
857 asrc3_mask |= RT5670_DOWN_CLK_SEL_MASK;
858 asrc3_value = (asrc3_value & ~RT5670_DOWN_CLK_SEL_MASK)
859 | (clk_src << RT5670_DOWN_CLK_SEL_SFT);
860 }
861
862 if (asrc2_mask)
5ba04c66 863 snd_soc_component_update_bits(component, RT5670_ASRC_2,
ea232b3f
ML		 864 asrc2_mask, asrc2_value);
865
866 if (asrc3_mask)
5ba04c66 867 snd_soc_component_update_bits(component, RT5670_ASRC_3,
ea232b3f
ML		 868 asrc3_mask, asrc3_value);
869 return 0;
870}
871EXPORT_SYMBOL_GPL(rt5670_sel_asrc_clk_src);
872
5e8351de
BL		 873/* Digital Mixer */
874static const struct snd_kcontrol_new rt5670_sto1_adc_l_mix[] = {
875 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
876 RT5670_M_ADC_L1_SFT, 1, 1),
877 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
878 RT5670_M_ADC_L2_SFT, 1, 1),
879};
880
881static const struct snd_kcontrol_new rt5670_sto1_adc_r_mix[] = {
882 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
883 RT5670_M_ADC_R1_SFT, 1, 1),
884 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
885 RT5670_M_ADC_R2_SFT, 1, 1),
886};
887
888static const struct snd_kcontrol_new rt5670_sto2_adc_l_mix[] = {
889 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
890 RT5670_M_ADC_L1_SFT, 1, 1),
891 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
892 RT5670_M_ADC_L2_SFT, 1, 1),
893};
894
895static const struct snd_kcontrol_new rt5670_sto2_adc_r_mix[] = {
896 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
897 RT5670_M_ADC_R1_SFT, 1, 1),
898 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
899 RT5670_M_ADC_R2_SFT, 1, 1),
900};
901
902static const struct snd_kcontrol_new rt5670_mono_adc_l_mix[] = {
903 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
904 RT5670_M_MONO_ADC_L1_SFT, 1, 1),
905 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
906 RT5670_M_MONO_ADC_L2_SFT, 1, 1),
907};
908
909static const struct snd_kcontrol_new rt5670_mono_adc_r_mix[] = {
910 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
911 RT5670_M_MONO_ADC_R1_SFT, 1, 1),
912 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
913 RT5670_M_MONO_ADC_R2_SFT, 1, 1),
914};
915
916static const struct snd_kcontrol_new rt5670_dac_l_mix[] = {
917 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
918 RT5670_M_ADCMIX_L_SFT, 1, 1),
919 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
920 RT5670_M_DAC1_L_SFT, 1, 1),
921};
922
923static const struct snd_kcontrol_new rt5670_dac_r_mix[] = {
924 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
925 RT5670_M_ADCMIX_R_SFT, 1, 1),
926 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
927 RT5670_M_DAC1_R_SFT, 1, 1),
928};
929
930static const struct snd_kcontrol_new rt5670_sto_dac_l_mix[] = {
931 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
932 RT5670_M_DAC_L1_SFT, 1, 1),
933 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_STO_DAC_MIXER,
934 RT5670_M_DAC_L2_SFT, 1, 1),
935 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
936 RT5670_M_DAC_R1_STO_L_SFT, 1, 1),
937};
938
939static const struct snd_kcontrol_new rt5670_sto_dac_r_mix[] = {
940 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
941 RT5670_M_DAC_R1_SFT, 1, 1),
942 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_STO_DAC_MIXER,
943 RT5670_M_DAC_R2_SFT, 1, 1),
944 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
945 RT5670_M_DAC_L1_STO_R_SFT, 1, 1),
946};
947
948static const struct snd_kcontrol_new rt5670_mono_dac_l_mix[] = {
949 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_DD_MIXER,
950 RT5670_M_DAC_L1_MONO_L_SFT, 1, 1),
951 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
952 RT5670_M_DAC_L2_MONO_L_SFT, 1, 1),
953 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
954 RT5670_M_DAC_R2_MONO_L_SFT, 1, 1),
955};
956
957static const struct snd_kcontrol_new rt5670_mono_dac_r_mix[] = {
958 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_DD_MIXER,
959 RT5670_M_DAC_R1_MONO_R_SFT, 1, 1),
960 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
961 RT5670_M_DAC_R2_MONO_R_SFT, 1, 1),
962 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
963 RT5670_M_DAC_L2_MONO_R_SFT, 1, 1),
964};
965
966static const struct snd_kcontrol_new rt5670_dig_l_mix[] = {
967 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5670_DIG_MIXER,
968 RT5670_M_STO_L_DAC_L_SFT, 1, 1),
969 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
970 RT5670_M_DAC_L2_DAC_L_SFT, 1, 1),
971 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
972 RT5670_M_DAC_R2_DAC_L_SFT, 1, 1),
973};
974
975static const struct snd_kcontrol_new rt5670_dig_r_mix[] = {
976 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5670_DIG_MIXER,
977 RT5670_M_STO_R_DAC_R_SFT, 1, 1),
978 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
979 RT5670_M_DAC_R2_DAC_R_SFT, 1, 1),
980 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
981 RT5670_M_DAC_L2_DAC_R_SFT, 1, 1),
982};
983
984/* Analog Input Mixer */
985static const struct snd_kcontrol_new rt5670_rec_l_mix[] = {
986 SOC_DAPM_SINGLE("INL Switch", RT5670_REC_L2_MIXER,
987 RT5670_M_IN_L_RM_L_SFT, 1, 1),
988 SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_L2_MIXER,
989 RT5670_M_BST2_RM_L_SFT, 1, 1),
990 SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_L2_MIXER,
991 RT5670_M_BST1_RM_L_SFT, 1, 1),
992};
993
994static const struct snd_kcontrol_new rt5670_rec_r_mix[] = {
995 SOC_DAPM_SINGLE("INR Switch", RT5670_REC_R2_MIXER,
996 RT5670_M_IN_R_RM_R_SFT, 1, 1),
997 SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_R2_MIXER,
998 RT5670_M_BST2_RM_R_SFT, 1, 1),
999 SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_R2_MIXER,
1000 RT5670_M_BST1_RM_R_SFT, 1, 1),
1001};
1002
1003static const struct snd_kcontrol_new rt5670_out_l_mix[] = {
1004 SOC_DAPM_SINGLE("BST1 Switch", RT5670_OUT_L1_MIXER,
1005 RT5670_M_BST1_OM_L_SFT, 1, 1),
1006 SOC_DAPM_SINGLE("INL Switch", RT5670_OUT_L1_MIXER,
1007 RT5670_M_IN_L_OM_L_SFT, 1, 1),
1008 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_OUT_L1_MIXER,
1009 RT5670_M_DAC_L2_OM_L_SFT, 1, 1),
1010 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_OUT_L1_MIXER,
1011 RT5670_M_DAC_L1_OM_L_SFT, 1, 1),
1012};
1013
1014static const struct snd_kcontrol_new rt5670_out_r_mix[] = {
1015 SOC_DAPM_SINGLE("BST2 Switch", RT5670_OUT_R1_MIXER,
1016 RT5670_M_BST2_OM_R_SFT, 1, 1),
1017 SOC_DAPM_SINGLE("INR Switch", RT5670_OUT_R1_MIXER,
1018 RT5670_M_IN_R_OM_R_SFT, 1, 1),
1019 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_OUT_R1_MIXER,
1020 RT5670_M_DAC_R2_OM_R_SFT, 1, 1),
1021 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_OUT_R1_MIXER,
1022 RT5670_M_DAC_R1_OM_R_SFT, 1, 1),
1023};
1024
1025static const struct snd_kcontrol_new rt5670_hpo_mix[] = {
1026 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
1027 RT5670_M_DAC1_HM_SFT, 1, 1),
1028 SOC_DAPM_SINGLE("HPVOL Switch", RT5670_HPO_MIXER,
1029 RT5670_M_HPVOL_HM_SFT, 1, 1),
1030};
1031
1032static const struct snd_kcontrol_new rt5670_hpvoll_mix[] = {
1033 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
1034 RT5670_M_DACL1_HML_SFT, 1, 1),
1035 SOC_DAPM_SINGLE("INL Switch", RT5670_HPO_MIXER,
1036 RT5670_M_INL1_HML_SFT, 1, 1),
1037};
1038
1039static const struct snd_kcontrol_new rt5670_hpvolr_mix[] = {
1040 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
1041 RT5670_M_DACR1_HMR_SFT, 1, 1),
1042 SOC_DAPM_SINGLE("INR Switch", RT5670_HPO_MIXER,
1043 RT5670_M_INR1_HMR_SFT, 1, 1),
1044};
1045
1046static const struct snd_kcontrol_new rt5670_lout_mix[] = {
1047 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_LOUT_MIXER,
1048 RT5670_M_DAC_L1_LM_SFT, 1, 1),
1049 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_LOUT_MIXER,
1050 RT5670_M_DAC_R1_LM_SFT, 1, 1),
1051 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5670_LOUT_MIXER,
1052 RT5670_M_OV_L_LM_SFT, 1, 1),
1053 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5670_LOUT_MIXER,
1054 RT5670_M_OV_R_LM_SFT, 1, 1),
1055};
1056
5e8351de
BL		 1057static const struct snd_kcontrol_new lout_l_enable_control =
1058 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
1059 RT5670_L_MUTE_SFT, 1, 1);
1060
1061static const struct snd_kcontrol_new lout_r_enable_control =
1062 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
1063 RT5670_R_MUTE_SFT, 1, 1);
1064
1065/* DAC1 L/R source */ /* MX-29 [9:8] [11:10] */
1066static const char * const rt5670_dac1_src[] = {
1067 "IF1 DAC", "IF2 DAC"
1068};
1069
01957572 1070static SOC_ENUM_SINGLE_DECL(rt5670_dac1l_enum, RT5670_AD_DA_MIXER,
5e8351de
BL		 1071 RT5670_DAC1_L_SEL_SFT, rt5670_dac1_src);
1072
1073static const struct snd_kcontrol_new rt5670_dac1l_mux =
1074 SOC_DAPM_ENUM("DAC1 L source", rt5670_dac1l_enum);
1075
01957572 1076static SOC_ENUM_SINGLE_DECL(rt5670_dac1r_enum, RT5670_AD_DA_MIXER,
5e8351de
BL		 1077 RT5670_DAC1_R_SEL_SFT, rt5670_dac1_src);
1078
1079static const struct snd_kcontrol_new rt5670_dac1r_mux =
1080 SOC_DAPM_ENUM("DAC1 R source", rt5670_dac1r_enum);
1081
1082/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1083/* TODO Use SOC_VALUE_ENUM_SINGLE_DECL */
1084static const char * const rt5670_dac12_src[] = {
1085 "IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC",
1086 "Bass", "VAD_ADC", "IF4 DAC"
1087};
1088
01957572 1089static SOC_ENUM_SINGLE_DECL(rt5670_dac2l_enum, RT5670_DAC_CTRL,
5e8351de
BL		 1090 RT5670_DAC2_L_SEL_SFT, rt5670_dac12_src);
1091
1092static const struct snd_kcontrol_new rt5670_dac_l2_mux =
1093 SOC_DAPM_ENUM("DAC2 L source", rt5670_dac2l_enum);
1094
1095static const char * const rt5670_dacr2_src[] = {
1096 "IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC", "TxDP ADC", "IF4 DAC"
1097};
1098
01957572 1099static SOC_ENUM_SINGLE_DECL(rt5670_dac2r_enum, RT5670_DAC_CTRL,
5e8351de
BL		 1100 RT5670_DAC2_R_SEL_SFT, rt5670_dacr2_src);
1101
1102static const struct snd_kcontrol_new rt5670_dac_r2_mux =
1103 SOC_DAPM_ENUM("DAC2 R source", rt5670_dac2r_enum);
1104
1105/*RxDP source*/ /* MX-2D [15:13] */
1106static const char * const rt5670_rxdp_src[] = {
1107 "IF2 DAC", "IF1 DAC", "STO1 ADC Mixer", "STO2 ADC Mixer",
1108 "Mono ADC Mixer L", "Mono ADC Mixer R", "DAC1"
1109};
1110
01957572 1111static SOC_ENUM_SINGLE_DECL(rt5670_rxdp_enum, RT5670_DSP_PATH1,
5e8351de
BL		 1112 RT5670_RXDP_SEL_SFT, rt5670_rxdp_src);
1113
1114static const struct snd_kcontrol_new rt5670_rxdp_mux =
1115 SOC_DAPM_ENUM("DAC2 L source", rt5670_rxdp_enum);
1116
1117/* MX-2D [1] [0] */
1118static const char * const rt5670_dsp_bypass_src[] = {
1119 "DSP", "Bypass"
1120};
1121
01957572 1122static SOC_ENUM_SINGLE_DECL(rt5670_dsp_ul_enum, RT5670_DSP_PATH1,
5e8351de
BL		 1123 RT5670_DSP_UL_SFT, rt5670_dsp_bypass_src);
1124
1125static const struct snd_kcontrol_new rt5670_dsp_ul_mux =
1126 SOC_DAPM_ENUM("DSP UL source", rt5670_dsp_ul_enum);
1127
01957572 1128static SOC_ENUM_SINGLE_DECL(rt5670_dsp_dl_enum, RT5670_DSP_PATH1,
5e8351de
BL		 1129 RT5670_DSP_DL_SFT, rt5670_dsp_bypass_src);
1130
1131static const struct snd_kcontrol_new rt5670_dsp_dl_mux =
1132 SOC_DAPM_ENUM("DSP DL source", rt5670_dsp_dl_enum);
1133
1134/* Stereo2 ADC source */
1135/* MX-26 [15] */
1136static const char * const rt5670_stereo2_adc_lr_src[] = {
1137 "L", "LR"
1138};
1139
01957572 1140static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc_lr_enum, RT5670_STO2_ADC_MIXER,
5e8351de
BL		 1141 RT5670_STO2_ADC_SRC_SFT, rt5670_stereo2_adc_lr_src);
1142
1143static const struct snd_kcontrol_new rt5670_sto2_adc_lr_mux =
1144 SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5670_stereo2_adc_lr_enum);
1145
1146/* Stereo1 ADC source */
1147/* MX-27 MX-26 [12] */
1148static const char * const rt5670_stereo_adc1_src[] = {
1149 "DAC MIX", "ADC"
1150};
1151
01957572 1152static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc1_enum, RT5670_STO1_ADC_MIXER,
5e8351de
BL		 1153 RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
1154
ea746a29
BL		 1155static const struct snd_kcontrol_new rt5670_sto_adc_1_mux =
1156 SOC_DAPM_ENUM("Stereo1 ADC 1 Mux", rt5670_stereo1_adc1_enum);
5e8351de 1157
01957572 1158static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc1_enum, RT5670_STO2_ADC_MIXER,
5e8351de
BL		 1159 RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
1160
ea746a29
BL		 1161static const struct snd_kcontrol_new rt5670_sto2_adc_1_mux =
1162 SOC_DAPM_ENUM("Stereo2 ADC 1 Mux", rt5670_stereo2_adc1_enum);
5e8351de 1163
5e8351de
BL		 1164
1165/* MX-27 MX-26 [11] */
1166static const char * const rt5670_stereo_adc2_src[] = {
1167 "DAC MIX", "DMIC"
1168};
1169
01957572 1170static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc2_enum, RT5670_STO1_ADC_MIXER,
5e8351de
BL		 1171 RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
1172
ea746a29
BL		 1173static const struct snd_kcontrol_new rt5670_sto_adc_2_mux =
1174 SOC_DAPM_ENUM("Stereo1 ADC 2 Mux", rt5670_stereo1_adc2_enum);
5e8351de 1175
01957572 1176static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc2_enum, RT5670_STO2_ADC_MIXER,
5e8351de
BL		 1177 RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
1178
ea746a29
BL		 1179static const struct snd_kcontrol_new rt5670_sto2_adc_2_mux =
1180 SOC_DAPM_ENUM("Stereo2 ADC 2 Mux", rt5670_stereo2_adc2_enum);
5e8351de 1181
5e8351de
BL		 1182/* MX-27 MX-26 [9:8] */
1183static const char * const rt5670_stereo_dmic_src[] = {
1184 "DMIC1", "DMIC2", "DMIC3"
1185};
1186
01957572 1187static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_dmic_enum, RT5670_STO1_ADC_MIXER,
5e8351de
BL		 1188 RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
1189
1190static const struct snd_kcontrol_new rt5670_sto1_dmic_mux =
1191 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5670_stereo1_dmic_enum);
1192
01957572 1193static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_dmic_enum, RT5670_STO2_ADC_MIXER,
5e8351de
BL		 1194 RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
1195
1196static const struct snd_kcontrol_new rt5670_sto2_dmic_mux =
1197 SOC_DAPM_ENUM("Stereo2 DMIC source", rt5670_stereo2_dmic_enum);
1198
5e8351de
BL		 1199/* Mono ADC source */
1200/* MX-28 [12] */
1201static const char * const rt5670_mono_adc_l1_src[] = {
1202 "Mono DAC MIXL", "ADC1"
1203};
1204
01957572 1205static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l1_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1206 RT5670_MONO_ADC_L1_SRC_SFT, rt5670_mono_adc_l1_src);
1207
1208static const struct snd_kcontrol_new rt5670_mono_adc_l1_mux =
1209 SOC_DAPM_ENUM("Mono ADC1 left source", rt5670_mono_adc_l1_enum);
1210/* MX-28 [11] */
1211static const char * const rt5670_mono_adc_l2_src[] = {
1212 "Mono DAC MIXL", "DMIC"
1213};
1214
01957572 1215static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l2_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1216 RT5670_MONO_ADC_L2_SRC_SFT, rt5670_mono_adc_l2_src);
1217
1218static const struct snd_kcontrol_new rt5670_mono_adc_l2_mux =
1219 SOC_DAPM_ENUM("Mono ADC2 left source", rt5670_mono_adc_l2_enum);
1220
1221/* MX-28 [9:8] */
1222static const char * const rt5670_mono_dmic_src[] = {
1223 "DMIC1", "DMIC2", "DMIC3"
1224};
1225
01957572 1226static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_l_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1227 RT5670_MONO_DMIC_L_SRC_SFT, rt5670_mono_dmic_src);
1228
1229static const struct snd_kcontrol_new rt5670_mono_dmic_l_mux =
1230 SOC_DAPM_ENUM("Mono DMIC left source", rt5670_mono_dmic_l_enum);
1231/* MX-28 [1:0] */
01957572 1232static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_r_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1233 RT5670_MONO_DMIC_R_SRC_SFT, rt5670_mono_dmic_src);
1234
1235static const struct snd_kcontrol_new rt5670_mono_dmic_r_mux =
1236 SOC_DAPM_ENUM("Mono DMIC Right source", rt5670_mono_dmic_r_enum);
1237/* MX-28 [4] */
1238static const char * const rt5670_mono_adc_r1_src[] = {
1239 "Mono DAC MIXR", "ADC2"
1240};
1241
01957572 1242static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r1_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1243 RT5670_MONO_ADC_R1_SRC_SFT, rt5670_mono_adc_r1_src);
1244
1245static const struct snd_kcontrol_new rt5670_mono_adc_r1_mux =
1246 SOC_DAPM_ENUM("Mono ADC1 right source", rt5670_mono_adc_r1_enum);
1247/* MX-28 [3] */
1248static const char * const rt5670_mono_adc_r2_src[] = {
1249 "Mono DAC MIXR", "DMIC"
1250};
1251
01957572 1252static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r2_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1253 RT5670_MONO_ADC_R2_SRC_SFT, rt5670_mono_adc_r2_src);
1254
1255static const struct snd_kcontrol_new rt5670_mono_adc_r2_mux =
1256 SOC_DAPM_ENUM("Mono ADC2 right source", rt5670_mono_adc_r2_enum);
1257
1258/* MX-2D [3:2] */
1259static const char * const rt5670_txdp_slot_src[] = {
1260 "Slot 0-1", "Slot 2-3", "Slot 4-5", "Slot 6-7"
1261};
1262
01957572 1263static SOC_ENUM_SINGLE_DECL(rt5670_txdp_slot_enum, RT5670_DSP_PATH1,
5e8351de
BL		 1264 RT5670_TXDP_SLOT_SEL_SFT, rt5670_txdp_slot_src);
1265
1266static const struct snd_kcontrol_new rt5670_txdp_slot_mux =
1267 SOC_DAPM_ENUM("TxDP Slot source", rt5670_txdp_slot_enum);
1268
1269/* MX-2F [15] */
1270static const char * const rt5670_if1_adc2_in_src[] = {
1271 "IF_ADC2", "VAD_ADC"
1272};
1273
01957572 1274static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in_enum, RT5670_DIG_INF1_DATA,
5e8351de
BL		 1275 RT5670_IF1_ADC2_IN_SFT, rt5670_if1_adc2_in_src);
1276
1277static const struct snd_kcontrol_new rt5670_if1_adc2_in_mux =
1278 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5670_if1_adc2_in_enum);
1279
1280/* MX-2F [14:12] */
1281static const char * const rt5670_if2_adc_in_src[] = {
1282 "IF_ADC1", "IF_ADC2", "IF_ADC3", "TxDC_DAC", "TxDP_ADC", "VAD_ADC"
1283};
1284
01957572 1285static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_in_enum, RT5670_DIG_INF1_DATA,
5e8351de
BL		 1286 RT5670_IF2_ADC_IN_SFT, rt5670_if2_adc_in_src);
1287
1288static const struct snd_kcontrol_new rt5670_if2_adc_in_mux =
1289 SOC_DAPM_ENUM("IF2 ADC IN source", rt5670_if2_adc_in_enum);
1290
5e8351de
BL		 1291/* MX-31 [15] [13] [11] [9] */
1292static const char * const rt5670_pdm_src[] = {
1293 "Mono DAC", "Stereo DAC"
1294};
1295
01957572 1296static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_l_enum, RT5670_PDM_OUT_CTRL,
5e8351de
BL		 1297 RT5670_PDM1_L_SFT, rt5670_pdm_src);
1298
1299static const struct snd_kcontrol_new rt5670_pdm1_l_mux =
1300 SOC_DAPM_ENUM("PDM1 L source", rt5670_pdm1_l_enum);
1301
01957572 1302static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_r_enum, RT5670_PDM_OUT_CTRL,
5e8351de
BL		 1303 RT5670_PDM1_R_SFT, rt5670_pdm_src);
1304
1305static const struct snd_kcontrol_new rt5670_pdm1_r_mux =
1306 SOC_DAPM_ENUM("PDM1 R source", rt5670_pdm1_r_enum);
1307
01957572 1308static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_l_enum, RT5670_PDM_OUT_CTRL,
5e8351de
BL		 1309 RT5670_PDM2_L_SFT, rt5670_pdm_src);
1310
1311static const struct snd_kcontrol_new rt5670_pdm2_l_mux =
1312 SOC_DAPM_ENUM("PDM2 L source", rt5670_pdm2_l_enum);
1313
01957572 1314static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_r_enum, RT5670_PDM_OUT_CTRL,
5e8351de
BL		 1315 RT5670_PDM2_R_SFT, rt5670_pdm_src);
1316
1317static const struct snd_kcontrol_new rt5670_pdm2_r_mux =
1318 SOC_DAPM_ENUM("PDM2 R source", rt5670_pdm2_r_enum);
1319
1320/* MX-FA [12] */
1321static const char * const rt5670_if1_adc1_in1_src[] = {
1322 "IF_ADC1", "IF1_ADC3"
1323};
1324
01957572 1325static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in1_enum, RT5670_DIG_MISC,
5e8351de
BL		 1326 RT5670_IF1_ADC1_IN1_SFT, rt5670_if1_adc1_in1_src);
1327
1328static const struct snd_kcontrol_new rt5670_if1_adc1_in1_mux =
1329 SOC_DAPM_ENUM("IF1 ADC1 IN1 source", rt5670_if1_adc1_in1_enum);
1330
1331/* MX-FA [11] */
1332static const char * const rt5670_if1_adc1_in2_src[] = {
1333 "IF1_ADC1_IN1", "IF1_ADC4"
1334};
1335
01957572 1336static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in2_enum, RT5670_DIG_MISC,
5e8351de
BL		 1337 RT5670_IF1_ADC1_IN2_SFT, rt5670_if1_adc1_in2_src);
1338
1339static const struct snd_kcontrol_new rt5670_if1_adc1_in2_mux =
1340 SOC_DAPM_ENUM("IF1 ADC1 IN2 source", rt5670_if1_adc1_in2_enum);
1341
1342/* MX-FA [10] */
1343static const char * const rt5670_if1_adc2_in1_src[] = {
1344 "IF1_ADC2_IN", "IF1_ADC4"
1345};
1346
01957572 1347static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in1_enum, RT5670_DIG_MISC,
5e8351de
BL		 1348 RT5670_IF1_ADC2_IN1_SFT, rt5670_if1_adc2_in1_src);
1349
1350static const struct snd_kcontrol_new rt5670_if1_adc2_in1_mux =
1351 SOC_DAPM_ENUM("IF1 ADC2 IN1 source", rt5670_if1_adc2_in1_enum);
1352
1353/* MX-9D [9:8] */
1354static const char * const rt5670_vad_adc_src[] = {
1355 "Sto1 ADC L", "Mono ADC L", "Mono ADC R", "Sto2 ADC L"
1356};
1357
01957572 1358static SOC_ENUM_SINGLE_DECL(rt5670_vad_adc_enum, RT5670_VAD_CTRL4,
5e8351de
BL		 1359 RT5670_VAD_SEL_SFT, rt5670_vad_adc_src);
1360
1361static const struct snd_kcontrol_new rt5670_vad_adc_mux =
1362 SOC_DAPM_ENUM("VAD ADC source", rt5670_vad_adc_enum);
1363
1364static int rt5670_hp_power_event(struct snd_soc_dapm_widget *w,
1365 struct snd_kcontrol *kcontrol, int event)
1366{
5ba04c66
KM		 1367 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1368 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de
BL		 1369
1370 switch (event) {
1371 case SND_SOC_DAPM_POST_PMU:
1372 regmap_update_bits(rt5670->regmap, RT5670_CHARGE_PUMP,
1373 RT5670_PM_HP_MASK, RT5670_PM_HP_HV);
1374 regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
1375 0x0400, 0x0400);
1376 /* headphone amp power on */
1377 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
1378 RT5670_PWR_HA | RT5670_PWR_FV1 |
1379 RT5670_PWR_FV2, RT5670_PWR_HA |
1380 RT5670_PWR_FV1 | RT5670_PWR_FV2);
1381 /* depop parameters */
1382 regmap_write(rt5670->regmap, RT5670_DEPOP_M2, 0x3100);
1383 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8009);
1384 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1385 RT5670_HP_DCC_INT1, 0x9f00);
1386 mdelay(20);
1387 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1388 break;
1389 case SND_SOC_DAPM_PRE_PMD:
1390 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x0004);
1391 msleep(30);
1392 break;
1393 default:
1394 return 0;
1395 }
1396
1397 return 0;
1398}
1399
1400static int rt5670_hp_event(struct snd_soc_dapm_widget *w,
1401 struct snd_kcontrol *kcontrol, int event)
1402{
5ba04c66
KM		 1403 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1404 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de
BL		 1405
1406 switch (event) {
1407 case SND_SOC_DAPM_POST_PMU:
1408 /* headphone unmute sequence */
1409 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1410 RT5670_MAMP_INT_REG2, 0xb400);
1411 regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
1412 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x805d);
1413 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
1414 regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
1415 0x0300, 0x0300);
1416 regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
1417 RT5670_L_MUTE | RT5670_R_MUTE, 0);
1418 msleep(80);
1419 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1420 break;
1421
1422 case SND_SOC_DAPM_PRE_PMD:
1423 /* headphone mute sequence */
1424 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1425 RT5670_MAMP_INT_REG2, 0xb400);
1426 regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
1427 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x803d);
1428 mdelay(10);
1429 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
1430 mdelay(10);
1431 regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
1432 RT5670_L_MUTE | RT5670_R_MUTE,
1433 RT5670_L_MUTE | RT5670_R_MUTE);
1434 msleep(20);
1435 regmap_update_bits(rt5670->regmap,
1436 RT5670_GEN_CTRL2, 0x0300, 0x0);
1437 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1438 regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0707);
1439 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1440 RT5670_MAMP_INT_REG2, 0xfc00);
1441 break;
1442
1443 default:
1444 return 0;
1445 }
1446
1447 return 0;
1448}
1449
1450static int rt5670_bst1_event(struct snd_soc_dapm_widget *w,
1451 struct snd_kcontrol *kcontrol, int event)
1452{
5ba04c66 1453 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
5e8351de
BL		 1454
1455 switch (event) {
1456 case SND_SOC_DAPM_POST_PMU:
5ba04c66 1457 snd_soc_component_update_bits(component, RT5670_PWR_ANLG2,
5e8351de
BL		 1458 RT5670_PWR_BST1_P, RT5670_PWR_BST1_P);
1459 break;
1460
1461 case SND_SOC_DAPM_PRE_PMD:
5ba04c66 1462 snd_soc_component_update_bits(component, RT5670_PWR_ANLG2,
5e8351de
BL		 1463 RT5670_PWR_BST1_P, 0);
1464 break;
1465
1466 default:
1467 return 0;
1468 }
1469
1470 return 0;
1471}
1472
1473static int rt5670_bst2_event(struct snd_soc_dapm_widget *w,
1474 struct snd_kcontrol *kcontrol, int event)
1475{
5ba04c66 1476 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
5e8351de
BL		 1477
1478 switch (event) {
1479 case SND_SOC_DAPM_POST_PMU:
5ba04c66 1480 snd_soc_component_update_bits(component, RT5670_PWR_ANLG2,
5e8351de
BL		 1481 RT5670_PWR_BST2_P, RT5670_PWR_BST2_P);
1482 break;
1483
1484 case SND_SOC_DAPM_PRE_PMD:
5ba04c66 1485 snd_soc_component_update_bits(component, RT5670_PWR_ANLG2,
5e8351de
BL		 1486 RT5670_PWR_BST2_P, 0);
1487 break;
1488
1489 default:
1490 return 0;
1491 }
1492
1493 return 0;
1494}
1495
1496static const struct snd_soc_dapm_widget rt5670_dapm_widgets[] = {
1497 SND_SOC_DAPM_SUPPLY("PLL1", RT5670_PWR_ANLG2,
1498 RT5670_PWR_PLL_BIT, 0, NULL, 0),
1499 SND_SOC_DAPM_SUPPLY("I2S DSP", RT5670_PWR_DIG2,
1500 RT5670_PWR_I2S_DSP_BIT, 0, NULL, 0),
1501 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5670_PWR_VOL,
1502 RT5670_PWR_MIC_DET_BIT, 0, NULL, 0),
1503
1504 /* ASRC */
1505 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5670_ASRC_1,
1506 11, 0, NULL, 0),
1507 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5670_ASRC_1,
1508 12, 0, NULL, 0),
1509 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5670_ASRC_1,
1510 10, 0, NULL, 0),
1511 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5670_ASRC_1,
1512 9, 0, NULL, 0),
1513 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5670_ASRC_1,
1514 8, 0, NULL, 0),
ff4541c3
BL		 1515 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5670_ASRC_1,
1516 7, 0, NULL, 0),
1517 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5670_ASRC_1,
1518 6, 0, NULL, 0),
1519 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5670_ASRC_1,
1520 5, 0, NULL, 0),
1521 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5670_ASRC_1,
1522 4, 0, NULL, 0),
5e8351de
BL		 1523 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5670_ASRC_1,
1524 3, 0, NULL, 0),
1525 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5670_ASRC_1,
1526 2, 0, NULL, 0),
1527 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5670_ASRC_1,
1528 1, 0, NULL, 0),
1529 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5670_ASRC_1,
1530 0, 0, NULL, 0),
1531
1532 /* Input Side */
1533 /* micbias */
1534 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5670_PWR_ANLG2,
1535 RT5670_PWR_MB1_BIT, 0, NULL, 0),
1536
1537 /* Input Lines */
1538 SND_SOC_DAPM_INPUT("DMIC L1"),
1539 SND_SOC_DAPM_INPUT("DMIC R1"),
1540 SND_SOC_DAPM_INPUT("DMIC L2"),
1541 SND_SOC_DAPM_INPUT("DMIC R2"),
1542 SND_SOC_DAPM_INPUT("DMIC L3"),
1543 SND_SOC_DAPM_INPUT("DMIC R3"),
1544
1545 SND_SOC_DAPM_INPUT("IN1P"),
1546 SND_SOC_DAPM_INPUT("IN1N"),
1547 SND_SOC_DAPM_INPUT("IN2P"),
1548 SND_SOC_DAPM_INPUT("IN2N"),
1549
1550 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1551 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1552 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1553
1554 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1555 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1556 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5670_DMIC_CTRL1,
1557 RT5670_DMIC_1_EN_SFT, 0, NULL, 0),
1558 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5670_DMIC_CTRL1,
1559 RT5670_DMIC_2_EN_SFT, 0, NULL, 0),
1560 SND_SOC_DAPM_SUPPLY("DMIC3 Power", RT5670_DMIC_CTRL1,
1561 RT5670_DMIC_3_EN_SFT, 0, NULL, 0),
1562 /* Boost */
1563 SND_SOC_DAPM_PGA_E("BST1", RT5670_PWR_ANLG2, RT5670_PWR_BST1_BIT,
1564 0, NULL, 0, rt5670_bst1_event,
1565 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1566 SND_SOC_DAPM_PGA_E("BST2", RT5670_PWR_ANLG2, RT5670_PWR_BST2_BIT,
1567 0, NULL, 0, rt5670_bst2_event,
1568 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1569 /* Input Volume */
1570 SND_SOC_DAPM_PGA("INL VOL", RT5670_PWR_VOL,
1571 RT5670_PWR_IN_L_BIT, 0, NULL, 0),
1572 SND_SOC_DAPM_PGA("INR VOL", RT5670_PWR_VOL,
1573 RT5670_PWR_IN_R_BIT, 0, NULL, 0),
1574
1575 /* REC Mixer */
1576 SND_SOC_DAPM_MIXER("RECMIXL", RT5670_PWR_MIXER, RT5670_PWR_RM_L_BIT, 0,
1577 rt5670_rec_l_mix, ARRAY_SIZE(rt5670_rec_l_mix)),
1578 SND_SOC_DAPM_MIXER("RECMIXR", RT5670_PWR_MIXER, RT5670_PWR_RM_R_BIT, 0,
1579 rt5670_rec_r_mix, ARRAY_SIZE(rt5670_rec_r_mix)),
1580 /* ADCs */
1581 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
1582 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 0, 0),
1583
1584 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1585
1586 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5670_PWR_DIG1,
1587 RT5670_PWR_ADC_L_BIT, 0, NULL, 0),
1588 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5670_PWR_DIG1,
1589 RT5670_PWR_ADC_R_BIT, 0, NULL, 0),
1590 SND_SOC_DAPM_SUPPLY("ADC clock", RT5670_PR_BASE +
1591 RT5670_CHOP_DAC_ADC, 12, 0, NULL, 0),
1592 /* ADC Mux */
1593 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1594 &rt5670_sto1_dmic_mux),
1595 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1596 &rt5670_sto_adc_2_mux),
5e8351de 1597 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1598 &rt5670_sto_adc_2_mux),
5e8351de 1599 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1600 &rt5670_sto_adc_1_mux),
5e8351de 1601 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1602 &rt5670_sto_adc_1_mux),
5e8351de
BL		 1603 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1604 &rt5670_sto2_dmic_mux),
1605 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1606 &rt5670_sto2_adc_2_mux),
5e8351de 1607 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1608 &rt5670_sto2_adc_2_mux),
5e8351de 1609 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1610 &rt5670_sto2_adc_1_mux),
5e8351de 1611 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1612 &rt5670_sto2_adc_1_mux),
5e8351de
BL		 1613 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1614 &rt5670_sto2_adc_lr_mux),
1615 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1616 &rt5670_mono_dmic_l_mux),
1617 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1618 &rt5670_mono_dmic_r_mux),
1619 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1620 &rt5670_mono_adc_l2_mux),
1621 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1622 &rt5670_mono_adc_l1_mux),
1623 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1624 &rt5670_mono_adc_r1_mux),
1625 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1626 &rt5670_mono_adc_r2_mux),
1627 /* ADC Mixer */
1628 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5670_PWR_DIG2,
1629 RT5670_PWR_ADC_S1F_BIT, 0, NULL, 0),
1630 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5670_PWR_DIG2,
1631 RT5670_PWR_ADC_S2F_BIT, 0, NULL, 0),
1632 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", RT5670_STO1_ADC_DIG_VOL,
1633 RT5670_L_MUTE_SFT, 1, rt5670_sto1_adc_l_mix,
1634 ARRAY_SIZE(rt5670_sto1_adc_l_mix)),
1635 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", RT5670_STO1_ADC_DIG_VOL,
1636 RT5670_R_MUTE_SFT, 1, rt5670_sto1_adc_r_mix,
1637 ARRAY_SIZE(rt5670_sto1_adc_r_mix)),
1638 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1639 rt5670_sto2_adc_l_mix,
1640 ARRAY_SIZE(rt5670_sto2_adc_l_mix)),
1641 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1642 rt5670_sto2_adc_r_mix,
1643 ARRAY_SIZE(rt5670_sto2_adc_r_mix)),
1644 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5670_PWR_DIG2,
1645 RT5670_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1646 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5670_MONO_ADC_DIG_VOL,
1647 RT5670_L_MUTE_SFT, 1, rt5670_mono_adc_l_mix,
1648 ARRAY_SIZE(rt5670_mono_adc_l_mix)),
1649 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5670_PWR_DIG2,
1650 RT5670_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1651 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5670_MONO_ADC_DIG_VOL,
1652 RT5670_R_MUTE_SFT, 1, rt5670_mono_adc_r_mix,
1653 ARRAY_SIZE(rt5670_mono_adc_r_mix)),
1654
1655 /* ADC PGA */
1656 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1657 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1658 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1659 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1660 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1661 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1662 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1663 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1664 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1665 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1666 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1667 SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1668 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1669 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1670 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
5e8351de
BL		 1671
1672 /* DSP */
1673 SND_SOC_DAPM_PGA("TxDP_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1674 SND_SOC_DAPM_PGA("TxDP_ADC_L", SND_SOC_NOPM, 0, 0, NULL, 0),
1675 SND_SOC_DAPM_PGA("TxDP_ADC_R", SND_SOC_NOPM, 0, 0, NULL, 0),
1676 SND_SOC_DAPM_PGA("TxDC_DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1677
1678 SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
1679 &rt5670_txdp_slot_mux),
1680
1681 SND_SOC_DAPM_MUX("DSP UL Mux", SND_SOC_NOPM, 0, 0,
1682 &rt5670_dsp_ul_mux),
1683 SND_SOC_DAPM_MUX("DSP DL Mux", SND_SOC_NOPM, 0, 0,
1684 &rt5670_dsp_dl_mux),
1685
1686 SND_SOC_DAPM_MUX("RxDP Mux", SND_SOC_NOPM, 0, 0,
1687 &rt5670_rxdp_mux),
1688
1689 /* IF2 Mux */
1690 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
1691 &rt5670_if2_adc_in_mux),
1692
1693 /* Digital Interface */
1694 SND_SOC_DAPM_SUPPLY("I2S1", RT5670_PWR_DIG1,
1695 RT5670_PWR_I2S1_BIT, 0, NULL, 0),
1696 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1697 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1698 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1699 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1700 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1701 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1702 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1703 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1704 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1705 SND_SOC_DAPM_SUPPLY("I2S2", RT5670_PWR_DIG1,
1706 RT5670_PWR_I2S2_BIT, 0, NULL, 0),
1707 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1708 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1709 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1710 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1711 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1712 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1713
1714 /* Digital Interface Select */
1715 SND_SOC_DAPM_MUX("IF1 ADC1 IN1 Mux", SND_SOC_NOPM, 0, 0,
1716 &rt5670_if1_adc1_in1_mux),
1717 SND_SOC_DAPM_MUX("IF1 ADC1 IN2 Mux", SND_SOC_NOPM, 0, 0,
1718 &rt5670_if1_adc1_in2_mux),
1719 SND_SOC_DAPM_MUX("IF1 ADC2 IN Mux", SND_SOC_NOPM, 0, 0,
1720 &rt5670_if1_adc2_in_mux),
1721 SND_SOC_DAPM_MUX("IF1 ADC2 IN1 Mux", SND_SOC_NOPM, 0, 0,
1722 &rt5670_if1_adc2_in1_mux),
1723 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
1724 &rt5670_vad_adc_mux),
1725
1726 /* Audio Interface */
1727 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1728 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1729 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1730 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1731 RT5670_GPIO_CTRL1, RT5670_I2S2_PIN_SFT, 1),
1732
1733 /* Audio DSP */
1734 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1735
1736 /* Output Side */
1737 /* DAC mixer before sound effect */
1738 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1739 rt5670_dac_l_mix, ARRAY_SIZE(rt5670_dac_l_mix)),
1740 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1741 rt5670_dac_r_mix, ARRAY_SIZE(rt5670_dac_r_mix)),
1742 SND_SOC_DAPM_PGA("DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1743
1744 /* DAC2 channel Mux */
1745 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
1746 &rt5670_dac_l2_mux),
1747 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
1748 &rt5670_dac_r2_mux),
1749 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5670_PWR_DIG1,
1750 RT5670_PWR_DAC_L2_BIT, 0, NULL, 0),
1751 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5670_PWR_DIG1,
1752 RT5670_PWR_DAC_R2_BIT, 0, NULL, 0),
1753
1754 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1l_mux),
1755 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1r_mux),
1756
1757 /* DAC Mixer */
1758 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5670_PWR_DIG2,
1759 RT5670_PWR_DAC_S1F_BIT, 0, NULL, 0),
1760 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5670_PWR_DIG2,
1761 RT5670_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1762 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5670_PWR_DIG2,
1763 RT5670_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1764 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1765 rt5670_sto_dac_l_mix,
1766 ARRAY_SIZE(rt5670_sto_dac_l_mix)),
1767 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1768 rt5670_sto_dac_r_mix,
1769 ARRAY_SIZE(rt5670_sto_dac_r_mix)),
1770 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1771 rt5670_mono_dac_l_mix,
1772 ARRAY_SIZE(rt5670_mono_dac_l_mix)),
1773 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1774 rt5670_mono_dac_r_mix,
1775 ARRAY_SIZE(rt5670_mono_dac_r_mix)),
1776 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1777 rt5670_dig_l_mix,
1778 ARRAY_SIZE(rt5670_dig_l_mix)),
1779 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1780 rt5670_dig_r_mix,
1781 ARRAY_SIZE(rt5670_dig_r_mix)),
1782
1783 /* DACs */
1784 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5670_PWR_DIG1,
1785 RT5670_PWR_DAC_L1_BIT, 0, NULL, 0),
1786 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5670_PWR_DIG1,
1787 RT5670_PWR_DAC_R1_BIT, 0, NULL, 0),
1788 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1789 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1790 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5670_PWR_DIG1,
1791 RT5670_PWR_DAC_L2_BIT, 0),
1792
1793 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5670_PWR_DIG1,
1794 RT5670_PWR_DAC_R2_BIT, 0),
1795 /* OUT Mixer */
1796
1797 SND_SOC_DAPM_MIXER("OUT MIXL", RT5670_PWR_MIXER, RT5670_PWR_OM_L_BIT,
1798 0, rt5670_out_l_mix, ARRAY_SIZE(rt5670_out_l_mix)),
1799 SND_SOC_DAPM_MIXER("OUT MIXR", RT5670_PWR_MIXER, RT5670_PWR_OM_R_BIT,
1800 0, rt5670_out_r_mix, ARRAY_SIZE(rt5670_out_r_mix)),
1801 /* Ouput Volume */
1802 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5670_PWR_VOL,
1803 RT5670_PWR_HV_L_BIT, 0,
1804 rt5670_hpvoll_mix, ARRAY_SIZE(rt5670_hpvoll_mix)),
1805 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5670_PWR_VOL,
1806 RT5670_PWR_HV_R_BIT, 0,
1807 rt5670_hpvolr_mix, ARRAY_SIZE(rt5670_hpvolr_mix)),
1808 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1809 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1810 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1811
1812 /* HPO/LOUT/Mono Mixer */
1813 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
1814 rt5670_hpo_mix, ARRAY_SIZE(rt5670_hpo_mix)),
1815 SND_SOC_DAPM_MIXER("LOUT MIX", RT5670_PWR_ANLG1, RT5670_PWR_LM_BIT,
1816 0, rt5670_lout_mix, ARRAY_SIZE(rt5670_lout_mix)),
1817 SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM, 0, 0,
1818 rt5670_hp_power_event, SND_SOC_DAPM_POST_PMU |
1819 SND_SOC_DAPM_PRE_PMD),
1820 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5670_PWR_ANLG1,
1821 RT5670_PWR_HP_L_BIT, 0, NULL, 0),
1822 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5670_PWR_ANLG1,
1823 RT5670_PWR_HP_R_BIT, 0, NULL, 0),
1824 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
1825 rt5670_hp_event, SND_SOC_DAPM_PRE_PMD |
1826 SND_SOC_DAPM_POST_PMU),
1827 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1828 &lout_l_enable_control),
1829 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1830 &lout_r_enable_control),
1831 SND_SOC_DAPM_PGA("LOUT Amp", SND_SOC_NOPM, 0, 0, NULL, 0),
1832
1833 /* PDM */
1834 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5670_PWR_DIG2,
1835 RT5670_PWR_PDM1_BIT, 0, NULL, 0),
5e8351de
BL		 1836
1837 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5670_PDM_OUT_CTRL,
1838 RT5670_M_PDM1_L_SFT, 1, &rt5670_pdm1_l_mux),
1839 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5670_PDM_OUT_CTRL,
1840 RT5670_M_PDM1_R_SFT, 1, &rt5670_pdm1_r_mux),
5e8351de
BL		 1841
1842 /* Output Lines */
1843 SND_SOC_DAPM_OUTPUT("HPOL"),
1844 SND_SOC_DAPM_OUTPUT("HPOR"),
1845 SND_SOC_DAPM_OUTPUT("LOUTL"),
1846 SND_SOC_DAPM_OUTPUT("LOUTR"),
0cf18632
BL		 1847};
1848
1849static const struct snd_soc_dapm_widget rt5670_specific_dapm_widgets[] = {
1850 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5670_PWR_DIG2,
1851 RT5670_PWR_PDM2_BIT, 0, NULL, 0),
1852 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5670_PDM_OUT_CTRL,
1853 RT5670_M_PDM2_L_SFT, 1, &rt5670_pdm2_l_mux),
1854 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5670_PDM_OUT_CTRL,
1855 RT5670_M_PDM2_R_SFT, 1, &rt5670_pdm2_r_mux),
5e8351de
BL		 1856 SND_SOC_DAPM_OUTPUT("PDM1L"),
1857 SND_SOC_DAPM_OUTPUT("PDM1R"),
1858 SND_SOC_DAPM_OUTPUT("PDM2L"),
1859 SND_SOC_DAPM_OUTPUT("PDM2R"),
1860};
1861
0cf18632
BL		 1862static const struct snd_soc_dapm_widget rt5672_specific_dapm_widgets[] = {
1863 SND_SOC_DAPM_PGA("SPO Amp", SND_SOC_NOPM, 0, 0, NULL, 0),
1864 SND_SOC_DAPM_OUTPUT("SPOLP"),
1865 SND_SOC_DAPM_OUTPUT("SPOLN"),
1866 SND_SOC_DAPM_OUTPUT("SPORP"),
1867 SND_SOC_DAPM_OUTPUT("SPORN"),
1868};
1869
5e8351de
BL		 1870static const struct snd_soc_dapm_route rt5670_dapm_routes[] = {
1871 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
1872 { "ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc },
1873 { "ADC Mono Left Filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1874 { "ADC Mono Right Filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1875 { "DAC Mono Left Filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1876 { "DAC Mono Right Filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1877 { "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
ff4541c3
BL		 1878 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
1879 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
1880 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
1881 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
5e8351de 1882
e50334d4
BL		 1883 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
1884 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
5e8351de
BL		 1885
1886 { "DMIC1", NULL, "DMIC L1" },
1887 { "DMIC1", NULL, "DMIC R1" },
1888 { "DMIC2", NULL, "DMIC L2" },
1889 { "DMIC2", NULL, "DMIC R2" },
1890 { "DMIC3", NULL, "DMIC L3" },
1891 { "DMIC3", NULL, "DMIC R3" },
1892
1893 { "BST1", NULL, "IN1P" },
1894 { "BST1", NULL, "IN1N" },
1895 { "BST1", NULL, "Mic Det Power" },
1896 { "BST2", NULL, "IN2P" },
1897 { "BST2", NULL, "IN2N" },
1898
1899 { "INL VOL", NULL, "IN2P" },
1900 { "INR VOL", NULL, "IN2N" },
1901
1902 { "RECMIXL", "INL Switch", "INL VOL" },
1903 { "RECMIXL", "BST2 Switch", "BST2" },
1904 { "RECMIXL", "BST1 Switch", "BST1" },
1905
1906 { "RECMIXR", "INR Switch", "INR VOL" },
1907 { "RECMIXR", "BST2 Switch", "BST2" },
1908 { "RECMIXR", "BST1 Switch", "BST1" },
1909
1910 { "ADC 1", NULL, "RECMIXL" },
1911 { "ADC 1", NULL, "ADC 1 power" },
1912 { "ADC 1", NULL, "ADC clock" },
1913 { "ADC 2", NULL, "RECMIXR" },
1914 { "ADC 2", NULL, "ADC 2 power" },
1915 { "ADC 2", NULL, "ADC clock" },
1916
1917 { "DMIC L1", NULL, "DMIC CLK" },
1918 { "DMIC L1", NULL, "DMIC1 Power" },
1919 { "DMIC R1", NULL, "DMIC CLK" },
1920 { "DMIC R1", NULL, "DMIC1 Power" },
1921 { "DMIC L2", NULL, "DMIC CLK" },
1922 { "DMIC L2", NULL, "DMIC2 Power" },
1923 { "DMIC R2", NULL, "DMIC CLK" },
1924 { "DMIC R2", NULL, "DMIC2 Power" },
1925 { "DMIC L3", NULL, "DMIC CLK" },
1926 { "DMIC L3", NULL, "DMIC3 Power" },
1927 { "DMIC R3", NULL, "DMIC CLK" },
1928 { "DMIC R3", NULL, "DMIC3 Power" },
1929
1930 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1931 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
1932 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
1933
1934 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
1935 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
1936 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
1937
1938 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1939 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
1940 { "Mono DMIC L Mux", "DMIC3", "DMIC L3" },
1941
1942 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1943 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
1944 { "Mono DMIC R Mux", "DMIC3", "DMIC R3" },
1945
1946 { "ADC 1_2", NULL, "ADC 1" },
1947 { "ADC 1_2", NULL, "ADC 2" },
1948
1949 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1950 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1951 { "Stereo1 ADC L1 Mux", "ADC", "ADC 1_2" },
1952 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1953
1954 { "Stereo1 ADC R1 Mux", "ADC", "ADC 1_2" },
1955 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1956 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1957 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1958
1959 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1960 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1961 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1962 { "Mono ADC L1 Mux", "ADC1", "ADC 1" },
1963
1964 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1965 { "Mono ADC R1 Mux", "ADC2", "ADC 2" },
1966 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1967 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1968
1969 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1970 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1971 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1972 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1973
1974 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1975 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
5e8351de
BL		 1976
1977 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1978 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
1979 { "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
1980
1981 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1982 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1983 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
1984 { "ADC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
1985
1986 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1987 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1988 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
1989 { "ADC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
1990
1991 { "Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC Mux" },
1992 { "Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1993 { "Stereo2 ADC L1 Mux", "ADC", "ADC 1_2" },
1994 { "Stereo2 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1995
1996 { "Stereo2 ADC R1 Mux", "ADC", "ADC 1_2" },
1997 { "Stereo2 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1998 { "Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC Mux" },
1999 { "Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2000
2001 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux" },
2002 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux" },
2003 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux" },
2004 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux" },
2005
2006 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2007 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2008
2009 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2010 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2011
2012 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2013 { "Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter" },
5e8351de
BL		 2014
2015 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2016 { "Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter" },
2017 { "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2018
2019 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2020 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2021 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2022 { "VAD ADC Mux", "Sto2 ADC L", "Sto2 ADC MIXL" },
2023
2024 { "VAD_ADC", NULL, "VAD ADC Mux" },
2025
2026 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2027 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2028 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2029 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2030 { "IF_ADC3", NULL, "Stereo2 ADC MIXL" },
2031 { "IF_ADC3", NULL, "Stereo2 ADC MIXR" },
2032
2033 { "IF1 ADC1 IN1 Mux", "IF_ADC1", "IF_ADC1" },
2034 { "IF1 ADC1 IN1 Mux", "IF1_ADC3", "IF1_ADC3" },
2035
2036 { "IF1 ADC1 IN2 Mux", "IF1_ADC1_IN1", "IF1 ADC1 IN1 Mux" },
8e2d163b 2037 { "IF1 ADC1 IN2 Mux", "IF1_ADC4", "TxDP_ADC" },
5e8351de
BL		 2038
2039 { "IF1 ADC2 IN Mux", "IF_ADC2", "IF_ADC2" },
2040 { "IF1 ADC2 IN Mux", "VAD_ADC", "VAD_ADC" },
2041
2042 { "IF1 ADC2 IN1 Mux", "IF1_ADC2_IN", "IF1 ADC2 IN Mux" },
8e2d163b 2043 { "IF1 ADC2 IN1 Mux", "IF1_ADC4", "TxDP_ADC" },
5e8351de
BL		 2044
2045 { "IF1_ADC1" , NULL, "IF1 ADC1 IN2 Mux" },
2046 { "IF1_ADC2" , NULL, "IF1 ADC2 IN1 Mux" },
2047
2048 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2049 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2050 { "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXL" },
2051 { "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXR" },
2052 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2053 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2054
2055 { "RxDP Mux", "IF2 DAC", "IF2 DAC" },
2056 { "RxDP Mux", "IF1 DAC", "IF1 DAC2" },
2057 { "RxDP Mux", "STO1 ADC Mixer", "Stereo1 ADC MIX" },
2058 { "RxDP Mux", "STO2 ADC Mixer", "Stereo2 ADC MIX" },
2059 { "RxDP Mux", "Mono ADC Mixer L", "Mono ADC MIXL" },
2060 { "RxDP Mux", "Mono ADC Mixer R", "Mono ADC MIXR" },
2061 { "RxDP Mux", "DAC1", "DAC MIX" },
2062
2063 { "TDM Data Mux", "Slot 0-1", "Stereo1 ADC MIX" },
2064 { "TDM Data Mux", "Slot 2-3", "Mono ADC MIX" },
2065 { "TDM Data Mux", "Slot 4-5", "Stereo2 ADC MIX" },
2066 { "TDM Data Mux", "Slot 6-7", "IF2 DAC" },
2067
2068 { "DSP UL Mux", "Bypass", "TDM Data Mux" },
2069 { "DSP UL Mux", NULL, "I2S DSP" },
2070 { "DSP DL Mux", "Bypass", "RxDP Mux" },
2071 { "DSP DL Mux", NULL, "I2S DSP" },
2072
2073 { "TxDP_ADC_L", NULL, "DSP UL Mux" },
2074 { "TxDP_ADC_R", NULL, "DSP UL Mux" },
2075 { "TxDC_DAC", NULL, "DSP DL Mux" },
2076
2077 { "TxDP_ADC", NULL, "TxDP_ADC_L" },
2078 { "TxDP_ADC", NULL, "TxDP_ADC_R" },
2079
2080 { "IF1 ADC", NULL, "I2S1" },
2081 { "IF1 ADC", NULL, "IF1_ADC1" },
2082 { "IF1 ADC", NULL, "IF1_ADC2" },
2083 { "IF1 ADC", NULL, "IF_ADC3" },
2084 { "IF1 ADC", NULL, "TxDP_ADC" },
2085
2086 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2087 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2088 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
2089 { "IF2 ADC Mux", "TxDC_DAC", "TxDC_DAC" },
2090 { "IF2 ADC Mux", "TxDP_ADC", "TxDP_ADC" },
2091 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2092
2093 { "IF2 ADC L", NULL, "IF2 ADC Mux" },
2094 { "IF2 ADC R", NULL, "IF2 ADC Mux" },
2095
2096 { "IF2 ADC", NULL, "I2S2" },
2097 { "IF2 ADC", NULL, "IF2 ADC L" },
2098 { "IF2 ADC", NULL, "IF2 ADC R" },
2099
2100 { "AIF1TX", NULL, "IF1 ADC" },
2101 { "AIF2TX", NULL, "IF2 ADC" },
2102
2103 { "IF1 DAC1", NULL, "AIF1RX" },
2104 { "IF1 DAC2", NULL, "AIF1RX" },
2105 { "IF2 DAC", NULL, "AIF2RX" },
2106
2107 { "IF1 DAC1", NULL, "I2S1" },
2108 { "IF1 DAC2", NULL, "I2S1" },
2109 { "IF2 DAC", NULL, "I2S2" },
2110
2111 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
2112 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
2113 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
2114 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
2115 { "IF2 DAC L", NULL, "IF2 DAC" },
2116 { "IF2 DAC R", NULL, "IF2 DAC" },
2117
2118 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
2119 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2120
2121 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
2122 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2123
2124 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2125 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2126 { "DAC1 MIXL", NULL, "DAC Stereo1 Filter" },
2127 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2128 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2129 { "DAC1 MIXR", NULL, "DAC Stereo1 Filter" },
2130
96927ac9
BL		 2131 { "DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2132 { "DAC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
2133 { "DAC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
2134
5e8351de
BL		 2135 { "DAC MIX", NULL, "DAC1 MIXL" },
2136 { "DAC MIX", NULL, "DAC1 MIXR" },
2137
2138 { "Audio DSP", NULL, "DAC1 MIXL" },
2139 { "Audio DSP", NULL, "DAC1 MIXR" },
2140
2141 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
2142 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2143 { "DAC L2 Mux", "TxDC DAC", "TxDC_DAC" },
2144 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2145 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2146 { "DAC L2 Volume", NULL, "DAC Mono Left Filter" },
2147
2148 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
2149 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2150 { "DAC R2 Mux", "TxDC DAC", "TxDC_DAC" },
2151 { "DAC R2 Mux", "TxDP ADC", "TxDP_ADC" },
2152 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2153 { "DAC R2 Volume", NULL, "DAC Mono Right Filter" },
2154
2155 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2156 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2157 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2158 { "Stereo DAC MIXL", NULL, "DAC Stereo1 Filter" },
2159 { "Stereo DAC MIXL", NULL, "DAC L1 Power" },
2160 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2161 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2162 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2163 { "Stereo DAC MIXR", NULL, "DAC Stereo1 Filter" },
2164 { "Stereo DAC MIXR", NULL, "DAC R1 Power" },
2165
2166 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2167 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2168 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2169 { "Mono DAC MIXL", NULL, "DAC Mono Left Filter" },
2170 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2171 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2172 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2173 { "Mono DAC MIXR", NULL, "DAC Mono Right Filter" },
2174
2175 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2176 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2177 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2178 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2179 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2180 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2181
2182 { "DAC L1", NULL, "DAC L1 Power" },
2183 { "DAC L1", NULL, "Stereo DAC MIXL" },
5e8351de
BL		 2184 { "DAC R1", NULL, "DAC R1 Power" },
2185 { "DAC R1", NULL, "Stereo DAC MIXR" },
5e8351de 2186 { "DAC L2", NULL, "Mono DAC MIXL" },
5e8351de 2187 { "DAC R2", NULL, "Mono DAC MIXR" },
5e8351de
BL		 2188
2189 { "OUT MIXL", "BST1 Switch", "BST1" },
2190 { "OUT MIXL", "INL Switch", "INL VOL" },
2191 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2192 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2193
2194 { "OUT MIXR", "BST2 Switch", "BST2" },
2195 { "OUT MIXR", "INR Switch", "INR VOL" },
2196 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2197 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2198
2199 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2200 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2201 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2202 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2203
2204 { "DAC 2", NULL, "DAC L2" },
2205 { "DAC 2", NULL, "DAC R2" },
2206 { "DAC 1", NULL, "DAC L1" },
2207 { "DAC 1", NULL, "DAC R1" },
2208 { "HPOVOL", NULL, "HPOVOL MIXL" },
2209 { "HPOVOL", NULL, "HPOVOL MIXR" },
2210 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2211 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2212
2213 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2214 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2215 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2216 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2217
2218 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2219 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2220 { "PDM1 L Mux", NULL, "PDM1 Power" },
2221 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2222 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2223 { "PDM1 R Mux", NULL, "PDM1 Power" },
5e8351de
BL		 2224
2225 { "HP Amp", NULL, "HPO MIX" },
2226 { "HP Amp", NULL, "Mic Det Power" },
2227 { "HPOL", NULL, "HP Amp" },
2228 { "HPOL", NULL, "HP L Amp" },
2229 { "HPOL", NULL, "Improve HP Amp Drv" },
2230 { "HPOR", NULL, "HP Amp" },
2231 { "HPOR", NULL, "HP R Amp" },
2232 { "HPOR", NULL, "Improve HP Amp Drv" },
2233
2234 { "LOUT Amp", NULL, "LOUT MIX" },
2235 { "LOUT L Playback", "Switch", "LOUT Amp" },
2236 { "LOUT R Playback", "Switch", "LOUT Amp" },
2237 { "LOUTL", NULL, "LOUT L Playback" },
2238 { "LOUTR", NULL, "LOUT R Playback" },
2239 { "LOUTL", NULL, "Improve HP Amp Drv" },
2240 { "LOUTR", NULL, "Improve HP Amp Drv" },
0cf18632 2241};
5e8351de 2242
0cf18632
BL		 2243static const struct snd_soc_dapm_route rt5670_specific_dapm_routes[] = {
2244 { "PDM2 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2245 { "PDM2 L Mux", "Mono DAC", "Mono DAC MIXL" },
2246 { "PDM2 L Mux", NULL, "PDM2 Power" },
2247 { "PDM2 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2248 { "PDM2 R Mux", "Mono DAC", "Mono DAC MIXR" },
2249 { "PDM2 R Mux", NULL, "PDM2 Power" },
5e8351de
BL		 2250 { "PDM1L", NULL, "PDM1 L Mux" },
2251 { "PDM1R", NULL, "PDM1 R Mux" },
2252 { "PDM2L", NULL, "PDM2 L Mux" },
2253 { "PDM2R", NULL, "PDM2 R Mux" },
2254};
2255
0cf18632
BL		 2256static const struct snd_soc_dapm_route rt5672_specific_dapm_routes[] = {
2257 { "SPO Amp", NULL, "PDM1 L Mux" },
2258 { "SPO Amp", NULL, "PDM1 R Mux" },
2259 { "SPOLP", NULL, "SPO Amp" },
2260 { "SPOLN", NULL, "SPO Amp" },
2261 { "SPORP", NULL, "SPO Amp" },
2262 { "SPORN", NULL, "SPO Amp" },
2263};
2264
5e8351de
BL		 2265static int rt5670_hw_params(struct snd_pcm_substream *substream,
2266 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2267{
5ba04c66
KM		 2268 struct snd_soc_component *component = dai->component;
2269 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de
BL		 2270 unsigned int val_len = 0, val_clk, mask_clk;
2271 int pre_div, bclk_ms, frame_size;
2272
2273 rt5670->lrck[dai->id] = params_rate(params);
2274 pre_div = rl6231_get_clk_info(rt5670->sysclk, rt5670->lrck[dai->id]);
2275 if (pre_div < 0) {
5ba04c66 2276 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
5e8351de
BL		 2277 rt5670->lrck[dai->id], dai->id);
2278 return -EINVAL;
2279 }
2280 frame_size = snd_soc_params_to_frame_size(params);
2281 if (frame_size < 0) {
5ba04c66 2282 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
5e8351de
BL		 2283 return -EINVAL;
2284 }
2285 bclk_ms = frame_size > 32;
2286 rt5670->bclk[dai->id] = rt5670->lrck[dai->id] * (32 << bclk_ms);
2287
2288 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2289 rt5670->bclk[dai->id], rt5670->lrck[dai->id]);
2290 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2291 bclk_ms, pre_div, dai->id);
2292
2293 switch (params_width(params)) {
2294 case 16:
2295 break;
2296 case 20:
2297 val_len |= RT5670_I2S_DL_20;
2298 break;
2299 case 24:
2300 val_len |= RT5670_I2S_DL_24;
2301 break;
2302 case 8:
2303 val_len |= RT5670_I2S_DL_8;
2304 break;
2305 default:
2306 return -EINVAL;
2307 }
2308
2309 switch (dai->id) {
2310 case RT5670_AIF1:
2311 mask_clk = RT5670_I2S_BCLK_MS1_MASK | RT5670_I2S_PD1_MASK;
2312 val_clk = bclk_ms << RT5670_I2S_BCLK_MS1_SFT |
2313 pre_div << RT5670_I2S_PD1_SFT;
5ba04c66 2314 snd_soc_component_update_bits(component, RT5670_I2S1_SDP,
5e8351de 2315 RT5670_I2S_DL_MASK, val_len);
5ba04c66 2316 snd_soc_component_update_bits(component, RT5670_ADDA_CLK1, mask_clk, val_clk);
5e8351de
BL		 2317 break;
2318 case RT5670_AIF2:
2319 mask_clk = RT5670_I2S_BCLK_MS2_MASK | RT5670_I2S_PD2_MASK;
2320 val_clk = bclk_ms << RT5670_I2S_BCLK_MS2_SFT |
2321 pre_div << RT5670_I2S_PD2_SFT;
5ba04c66 2322 snd_soc_component_update_bits(component, RT5670_I2S2_SDP,
5e8351de 2323 RT5670_I2S_DL_MASK, val_len);
5ba04c66 2324 snd_soc_component_update_bits(component, RT5670_ADDA_CLK1, mask_clk, val_clk);
5e8351de
BL		 2325 break;
2326 default:
5ba04c66 2327 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
5e8351de
BL		 2328 return -EINVAL;
2329 }
2330
2331 return 0;
2332}
2333
2334static int rt5670_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2335{
5ba04c66
KM		 2336 struct snd_soc_component *component = dai->component;
2337 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de
BL		 2338 unsigned int reg_val = 0;
2339
2340 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2341 case SND_SOC_DAIFMT_CBM_CFM:
2342 rt5670->master[dai->id] = 1;
2343 break;
2344 case SND_SOC_DAIFMT_CBS_CFS:
2345 reg_val |= RT5670_I2S_MS_S;
2346 rt5670->master[dai->id] = 0;
2347 break;
2348 default:
2349 return -EINVAL;
2350 }
2351
2352 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2353 case SND_SOC_DAIFMT_NB_NF:
2354 break;
2355 case SND_SOC_DAIFMT_IB_NF:
2356 reg_val |= RT5670_I2S_BP_INV;
2357 break;
2358 default:
2359 return -EINVAL;
2360 }
2361
2362 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2363 case SND_SOC_DAIFMT_I2S:
2364 break;
2365 case SND_SOC_DAIFMT_LEFT_J:
2366 reg_val |= RT5670_I2S_DF_LEFT;
2367 break;
2368 case SND_SOC_DAIFMT_DSP_A:
2369 reg_val |= RT5670_I2S_DF_PCM_A;
2370 break;
2371 case SND_SOC_DAIFMT_DSP_B:
2372 reg_val |= RT5670_I2S_DF_PCM_B;
2373 break;
2374 default:
2375 return -EINVAL;
2376 }
2377
2378 switch (dai->id) {
2379 case RT5670_AIF1:
5ba04c66 2380 snd_soc_component_update_bits(component, RT5670_I2S1_SDP,
5e8351de
BL		 2381 RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
2382 RT5670_I2S_DF_MASK, reg_val);
2383 break;
2384 case RT5670_AIF2:
5ba04c66 2385 snd_soc_component_update_bits(component, RT5670_I2S2_SDP,
5e8351de
BL		 2386 RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
2387 RT5670_I2S_DF_MASK, reg_val);
2388 break;
2389 default:
5ba04c66 2390 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
5e8351de
BL		 2391 return -EINVAL;
2392 }
2393 return 0;
2394}
2395
5ba04c66 2396static int rt5670_set_codec_sysclk(struct snd_soc_component *component, int clk_id,
6c28ce3c 2397 int source, unsigned int freq, int dir)
5e8351de 2398{
5ba04c66 2399 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de
BL		 2400 unsigned int reg_val = 0;
2401
5e8351de
BL		 2402 switch (clk_id) {
2403 case RT5670_SCLK_S_MCLK:
2404 reg_val |= RT5670_SCLK_SRC_MCLK;
2405 break;
2406 case RT5670_SCLK_S_PLL1:
2407 reg_val |= RT5670_SCLK_SRC_PLL1;
2408 break;
2409 case RT5670_SCLK_S_RCCLK:
2410 reg_val |= RT5670_SCLK_SRC_RCCLK;
2411 break;
2412 default:
5ba04c66 2413 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
5e8351de
BL		 2414 return -EINVAL;
2415 }
5ba04c66 2416 snd_soc_component_update_bits(component, RT5670_GLB_CLK,
5e8351de
BL		 2417 RT5670_SCLK_SRC_MASK, reg_val);
2418 rt5670->sysclk = freq;
485372dc
BL		 2419 if (clk_id != RT5670_SCLK_S_RCCLK)
2420 rt5670->sysclk_src = clk_id;
5e8351de 2421
5ba04c66 2422 dev_dbg(component->dev, "Sysclk : %dHz clock id : %d\n", freq, clk_id);
5e8351de
BL		 2423
2424 return 0;
2425}
2426
2427static int rt5670_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2428 unsigned int freq_in, unsigned int freq_out)
2429{
5ba04c66
KM		 2430 struct snd_soc_component *component = dai->component;
2431 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de
BL		 2432 struct rl6231_pll_code pll_code;
2433 int ret;
2434
2435 if (source == rt5670->pll_src && freq_in == rt5670->pll_in &&
2436 freq_out == rt5670->pll_out)
2437 return 0;
2438
2439 if (!freq_in || !freq_out) {
5ba04c66 2440 dev_dbg(component->dev, "PLL disabled\n");
5e8351de
BL		 2441
2442 rt5670->pll_in = 0;
2443 rt5670->pll_out = 0;
5ba04c66 2444 snd_soc_component_update_bits(component, RT5670_GLB_CLK,
5e8351de
BL		 2445 RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_MCLK);
2446 return 0;
2447 }
2448
2449 switch (source) {
2450 case RT5670_PLL1_S_MCLK:
5ba04c66 2451 snd_soc_component_update_bits(component, RT5670_GLB_CLK,
5e8351de
BL		 2452 RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_MCLK);
2453 break;
2454 case RT5670_PLL1_S_BCLK1:
2455 case RT5670_PLL1_S_BCLK2:
2456 case RT5670_PLL1_S_BCLK3:
2457 case RT5670_PLL1_S_BCLK4:
2458 switch (dai->id) {
2459 case RT5670_AIF1:
5ba04c66 2460 snd_soc_component_update_bits(component, RT5670_GLB_CLK,
5e8351de
BL		 2461 RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK1);
2462 break;
2463 case RT5670_AIF2:
5ba04c66 2464 snd_soc_component_update_bits(component, RT5670_GLB_CLK,
5e8351de
BL		 2465 RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK2);
2466 break;
2467 default:
5ba04c66 2468 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
5e8351de
BL		 2469 return -EINVAL;
2470 }
2471 break;
2472 default:
5ba04c66 2473 dev_err(component->dev, "Unknown PLL source %d\n", source);
5e8351de
BL		 2474 return -EINVAL;
2475 }
2476
2477 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2478 if (ret < 0) {
5ba04c66 2479 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
5e8351de
BL		 2480 return ret;
2481 }
2482
5ba04c66 2483 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
5e8351de
BL		 2484 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2485 pll_code.n_code, pll_code.k_code);
2486
5ba04c66 2487 snd_soc_component_write(component, RT5670_PLL_CTRL1,
5e8351de 2488 pll_code.n_code << RT5670_PLL_N_SFT | pll_code.k_code);
5ba04c66 2489 snd_soc_component_write(component, RT5670_PLL_CTRL2,
5e8351de
BL		 2490 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5670_PLL_M_SFT |
2491 pll_code.m_bp << RT5670_PLL_M_BP_SFT);
2492
2493 rt5670->pll_in = freq_in;
2494 rt5670->pll_out = freq_out;
2495 rt5670->pll_src = source;
2496
2497 return 0;
2498}
2499
2500static int rt5670_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2501 unsigned int rx_mask, int slots, int slot_width)
2502{
5ba04c66 2503 struct snd_soc_component *component = dai->component;
5e8351de
BL		 2504 unsigned int val = 0;
2505
2506 if (rx_mask || tx_mask)
2507 val |= (1 << 14);
2508
2509 switch (slots) {
2510 case 4:
2511 val |= (1 << 12);
2512 break;
2513 case 6:
2514 val |= (2 << 12);
2515 break;
2516 case 8:
2517 val |= (3 << 12);
2518 break;
2519 case 2:
2520 break;
2521 default:
2522 return -EINVAL;
2523 }
2524
2525 switch (slot_width) {
2526 case 20:
2527 val |= (1 << 10);
2528 break;
2529 case 24:
2530 val |= (2 << 10);
2531 break;
2532 case 32:
2533 val |= (3 << 10);
2534 break;
2535 case 16:
2536 break;
2537 default:
2538 return -EINVAL;
2539 }
2540
5ba04c66 2541 snd_soc_component_update_bits(component, RT5670_TDM_CTRL_1, 0x7c00, val);
5e8351de
BL		 2542
2543 return 0;
2544}
2545
d0817657
BL		 2546static int rt5670_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2547{
5ba04c66 2548 struct snd_soc_component *component = dai->component;
d0817657 2549
5ba04c66 2550 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
d0817657
BL		 2551 if (dai->id != RT5670_AIF1)
2552 return 0;
2553
2554 if ((ratio % 50) == 0)
5ba04c66 2555 snd_soc_component_update_bits(component, RT5670_GEN_CTRL3,
d0817657
BL		 2556 RT5670_TDM_DATA_MODE_SEL, RT5670_TDM_DATA_MODE_50FS);
2557 else
5ba04c66 2558 snd_soc_component_update_bits(component, RT5670_GEN_CTRL3,
d0817657
BL		 2559 RT5670_TDM_DATA_MODE_SEL, RT5670_TDM_DATA_MODE_NOR);
2560
2561 return 0;
2562}
2563
5ba04c66 2564static int rt5670_set_bias_level(struct snd_soc_component *component,
5e8351de
BL		 2565 enum snd_soc_bias_level level)
2566{
5ba04c66 2567 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
044b724a 2568
5e8351de
BL		 2569 switch (level) {
2570 case SND_SOC_BIAS_PREPARE:
5ba04c66
KM		 2571 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
2572 snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
5e8351de
BL		 2573 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2574 RT5670_PWR_BG | RT5670_PWR_VREF2,
2575 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2576 RT5670_PWR_BG | RT5670_PWR_VREF2);
2577 mdelay(10);
5ba04c66 2578 snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
5e8351de
BL		 2579 RT5670_PWR_FV1 | RT5670_PWR_FV2,
2580 RT5670_PWR_FV1 | RT5670_PWR_FV2);
5ba04c66 2581 snd_soc_component_update_bits(component, RT5670_CHARGE_PUMP,
5e8351de
BL		 2582 RT5670_OSW_L_MASK | RT5670_OSW_R_MASK,
2583 RT5670_OSW_L_DIS | RT5670_OSW_R_DIS);
5ba04c66
KM		 2584 snd_soc_component_update_bits(component, RT5670_DIG_MISC, 0x1, 0x1);
2585 snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
c8c6f0d8 2586 RT5670_LDO_SEL_MASK, 0x5);
5e8351de
BL		 2587 }
2588 break;
2589 case SND_SOC_BIAS_STANDBY:
5ba04c66 2590 snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
044b724a
BL		 2591 RT5670_PWR_VREF1 | RT5670_PWR_VREF2 |
2592 RT5670_PWR_FV1 | RT5670_PWR_FV2, 0);
5ba04c66 2593 snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
c8c6f0d8 2594 RT5670_LDO_SEL_MASK, 0x3);
5e8351de 2595 break;
044b724a
BL		 2596 case SND_SOC_BIAS_OFF:
2597 if (rt5670->pdata.jd_mode)
5ba04c66 2598 snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
044b724a
BL		 2599 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2600 RT5670_PWR_BG | RT5670_PWR_VREF2 |
2601 RT5670_PWR_FV1 | RT5670_PWR_FV2,
2602 RT5670_PWR_MB | RT5670_PWR_BG);
2603 else
5ba04c66 2604 snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
044b724a
BL		 2605 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2606 RT5670_PWR_BG | RT5670_PWR_VREF2 |
2607 RT5670_PWR_FV1 | RT5670_PWR_FV2, 0);
2608
5ba04c66 2609 snd_soc_component_update_bits(component, RT5670_DIG_MISC, 0x1, 0x0);
044b724a 2610 break;
5e8351de
BL		 2611
2612 default:
2613 break;
2614 }
5e8351de
BL		 2615
2616 return 0;
2617}
2618
5ba04c66 2619static int rt5670_probe(struct snd_soc_component *component)
5e8351de 2620{
5ba04c66
KM		 2621 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2622 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de 2623
5ba04c66 2624 switch (snd_soc_component_read32(component, RT5670_RESET) & RT5670_ID_MASK) {
0cf18632
BL		 2625 case RT5670_ID_5670:
2626 case RT5670_ID_5671:
6d8135ff 2627 snd_soc_dapm_new_controls(dapm,
0cf18632
BL		 2628 rt5670_specific_dapm_widgets,
2629 ARRAY_SIZE(rt5670_specific_dapm_widgets));
6d8135ff 2630 snd_soc_dapm_add_routes(dapm,
0cf18632
BL		 2631 rt5670_specific_dapm_routes,
2632 ARRAY_SIZE(rt5670_specific_dapm_routes));
2633 break;
2634 case RT5670_ID_5672:
6d8135ff 2635 snd_soc_dapm_new_controls(dapm,
0cf18632
BL		 2636 rt5672_specific_dapm_widgets,
2637 ARRAY_SIZE(rt5672_specific_dapm_widgets));
6d8135ff 2638 snd_soc_dapm_add_routes(dapm,
0cf18632
BL		 2639 rt5672_specific_dapm_routes,
2640 ARRAY_SIZE(rt5672_specific_dapm_routes));
2641 break;
2642 default:
5ba04c66 2643 dev_err(component->dev,
0cf18632
BL		 2644 "The driver is for RT5670 RT5671 or RT5672 only\n");
2645 return -ENODEV;
2646 }
5ba04c66 2647 rt5670->component = component;
5e8351de
BL		 2648
2649 return 0;
2650}
2651
5ba04c66 2652static void rt5670_remove(struct snd_soc_component *component)
5e8351de 2653{
5ba04c66 2654 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de
BL		 2655
2656 regmap_write(rt5670->regmap, RT5670_RESET, 0);
d3ef7054 2657 snd_soc_jack_free_gpios(rt5670->jack, 1, &rt5670->hp_gpio);
5e8351de
BL		 2658}
2659
2660#ifdef CONFIG_PM
5ba04c66 2661static int rt5670_suspend(struct snd_soc_component *component)
5e8351de 2662{
5ba04c66 2663 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de
BL		 2664
2665 regcache_cache_only(rt5670->regmap, true);
2666 regcache_mark_dirty(rt5670->regmap);
2667 return 0;
2668}
2669
5ba04c66 2670static int rt5670_resume(struct snd_soc_component *component)
5e8351de 2671{
5ba04c66 2672 struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
5e8351de
BL		 2673
2674 regcache_cache_only(rt5670->regmap, false);
2675 regcache_sync(rt5670->regmap);
2676
2677 return 0;
2678}
2679#else
2680#define rt5670_suspend NULL
2681#define rt5670_resume NULL
2682#endif
2683
2684#define RT5670_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2685#define RT5670_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2686 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2687
64793047 2688static const struct snd_soc_dai_ops rt5670_aif_dai_ops = {
5e8351de
BL		 2689 .hw_params = rt5670_hw_params,
2690 .set_fmt = rt5670_set_dai_fmt,
5e8351de
BL		 2691 .set_tdm_slot = rt5670_set_tdm_slot,
2692 .set_pll = rt5670_set_dai_pll,
d0817657 2693 .set_bclk_ratio = rt5670_set_bclk_ratio,
5e8351de
BL		 2694};
2695
ff62b958 2696static struct snd_soc_dai_driver rt5670_dai[] = {
5e8351de
BL		 2697 {
2698 .name = "rt5670-aif1",
2699 .id = RT5670_AIF1,
2700 .playback = {
2701 .stream_name = "AIF1 Playback",
2702 .channels_min = 1,
2703 .channels_max = 2,
2704 .rates = RT5670_STEREO_RATES,
2705 .formats = RT5670_FORMATS,
2706 },
2707 .capture = {
2708 .stream_name = "AIF1 Capture",
2709 .channels_min = 1,
2710 .channels_max = 2,
2711 .rates = RT5670_STEREO_RATES,
2712 .formats = RT5670_FORMATS,
2713 },
2714 .ops = &rt5670_aif_dai_ops,
8215313c 2715 .symmetric_rates = 1,
5e8351de
BL		 2716 },
2717 {
2718 .name = "rt5670-aif2",
2719 .id = RT5670_AIF2,
2720 .playback = {
2721 .stream_name = "AIF2 Playback",
2722 .channels_min = 1,
2723 .channels_max = 2,
2724 .rates = RT5670_STEREO_RATES,
2725 .formats = RT5670_FORMATS,
2726 },
2727 .capture = {
2728 .stream_name = "AIF2 Capture",
2729 .channels_min = 1,
2730 .channels_max = 2,
2731 .rates = RT5670_STEREO_RATES,
2732 .formats = RT5670_FORMATS,
2733 },
2734 .ops = &rt5670_aif_dai_ops,
8215313c 2735 .symmetric_rates = 1,
5e8351de
BL		 2736 },
2737};
2738
5ba04c66
KM		 2739static const struct snd_soc_component_driver soc_component_dev_rt5670 = {
2740 .probe = rt5670_probe,
2741 .remove = rt5670_remove,
2742 .suspend = rt5670_suspend,
2743 .resume = rt5670_resume,
2744 .set_bias_level = rt5670_set_bias_level,
2745 .set_sysclk = rt5670_set_codec_sysclk,
2746 .controls = rt5670_snd_controls,
2747 .num_controls = ARRAY_SIZE(rt5670_snd_controls),
2748 .dapm_widgets = rt5670_dapm_widgets,
2749 .num_dapm_widgets = ARRAY_SIZE(rt5670_dapm_widgets),
2750 .dapm_routes = rt5670_dapm_routes,
2751 .num_dapm_routes = ARRAY_SIZE(rt5670_dapm_routes),
2752 .use_pmdown_time = 1,
2753 .endianness = 1,
2754 .non_legacy_dai_naming = 1,
5e8351de
BL		 2755};
2756
2757static const struct regmap_config rt5670_regmap = {
2758 .reg_bits = 8,
2759 .val_bits = 16,
1c96a2f6
DF		 2760 .use_single_read = true,
2761 .use_single_write = true,
5e8351de
BL		 2762 .max_register = RT5670_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5670_ranges) *
2763 RT5670_PR_SPACING),
2764 .volatile_reg = rt5670_volatile_register,
2765 .readable_reg = rt5670_readable_register,
2766 .cache_type = REGCACHE_RBTREE,
2767 .reg_defaults = rt5670_reg,
2768 .num_reg_defaults = ARRAY_SIZE(rt5670_reg),
2769 .ranges = rt5670_ranges,
2770 .num_ranges = ARRAY_SIZE(rt5670_ranges),
2771};
2772
2773static const struct i2c_device_id rt5670_i2c_id[] = {
2774 { "rt5670", 0 },
0cf18632
BL		 2775 { "rt5671", 0 },
2776 { "rt5672", 0 },
5e8351de
BL		 2777 { }
2778};
2779MODULE_DEVICE_TABLE(i2c, rt5670_i2c_id);
2780
0605815e 2781#ifdef CONFIG_ACPI
4e0ce6a4 2782static const struct acpi_device_id rt5670_acpi_match[] = {
0605815e 2783 { "10EC5670", 0},
d2528006 2784 { "10EC5672", 0},
93ffeaa8 2785 { "10EC5640", 0}, /* quirk */
0605815e
ML		 2786 { },
2787};
2788MODULE_DEVICE_TABLE(acpi, rt5670_acpi_match);
2789#endif
2790
8e1b1785
PLB		 2791static int rt5670_quirk_cb(const struct dmi_system_id *id)
2792{
2793 rt5670_quirk = (unsigned long)id->driver_data;
2794 return 1;
2795}
2796
2797static const struct dmi_system_id dmi_platform_intel_quirks[] = {
223c055a 2798 {
8e1b1785 2799 .callback = rt5670_quirk_cb,
223c055a
BL		 2800 .ident = "Intel Braswell",
2801 .matches = {
2802 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
2803 DMI_MATCH(DMI_BOARD_NAME, "Braswell CRB"),
2804 },
8e1b1785
PLB		 2805 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2806 RT5670_DMIC1_IN2P |
2807 RT5670_DEV_GPIO |
2808 RT5670_JD_MODE1),
223c055a 2809 },
b4ff47d2 2810 {
8e1b1785 2811 .callback = rt5670_quirk_cb,
b4ff47d2
TI		 2812 .ident = "Dell Wyse 3040",
2813 .matches = {
2814 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
2815 DMI_MATCH(DMI_PRODUCT_NAME, "Wyse 3040"),
2816 },
8e1b1785
PLB		 2817 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2818 RT5670_DMIC1_IN2P |
2819 RT5670_DEV_GPIO |
2820 RT5670_JD_MODE1),
b4ff47d2 2821 },
818838e6
HG		 2822 {
2823 .callback = rt5670_quirk_cb,
2824 .ident = "Lenovo Thinkpad Tablet 8",
2825 .matches = {
2826 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2827 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad 8"),
2828 },
2829 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2830 RT5670_DMIC2_INR |
2831 RT5670_DEV_GPIO |
2832 RT5670_JD_MODE1),
2833 },
67e03ff3 2834 {
8e1b1785 2835 .callback = rt5670_quirk_cb,
67e03ff3
NF		 2836 .ident = "Lenovo Thinkpad Tablet 10",
2837 .matches = {
2838 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2839 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad 10"),
2840 },
8e1b1785
PLB		 2841 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2842 RT5670_DMIC1_IN2P |
2843 RT5670_DEV_GPIO |
2844 RT5670_JD_MODE1),
67e03ff3
NF		 2845 },
2846 {
8e1b1785 2847 .callback = rt5670_quirk_cb,
67e03ff3
NF		 2848 .ident = "Lenovo Thinkpad Tablet 10",
2849 .matches = {
2850 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2851 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Tablet B"),
2852 },
8e1b1785
PLB		 2853 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2854 RT5670_DMIC1_IN2P |
2855 RT5670_DEV_GPIO |
2856 RT5670_JD_MODE1),
67e03ff3
NF		 2857 },
2858 {
8e1b1785 2859 .callback = rt5670_quirk_cb,
67e03ff3
NF		 2860 .ident = "Lenovo Thinkpad Tablet 10",
2861 .matches = {
2862 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2863 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo Miix 2 10"),
2864 },
8e1b1785
PLB		 2865 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2866 RT5670_DMIC1_IN2P |
2867 RT5670_DEV_GPIO |
2868 RT5670_JD_MODE2),
67e03ff3 2869 },
c26d8389 2870 {
8e1b1785 2871 .callback = rt5670_quirk_cb,
c26d8389
PLB		 2872 .ident = "Dell Venue 8 Pro 5855",
2873 .matches = {
2874 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
2875 DMI_MATCH(DMI_PRODUCT_NAME, "Venue 8 Pro 5855"),
2876 },
8e1b1785
PLB		 2877 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2878 RT5670_DMIC2_INR |
2879 RT5670_DEV_GPIO |
2880 RT5670_JD_MODE3),
c26d8389 2881 },
3e951e79
KT		 2882 {
2883 .callback = rt5670_quirk_cb,
2884 .ident = "Aegex 10 tablet (RU2)",
2885 .matches = {
2886 DMI_MATCH(DMI_SYS_VENDOR, "AEGEX"),
2887 DMI_MATCH(DMI_PRODUCT_VERSION, "RU2"),
2888 },
2889 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2890 RT5670_DMIC2_INR |
2891 RT5670_DEV_GPIO |
2892 RT5670_JD_MODE3),
2893 },
c26d8389
PLB		 2894 {}
2895};
2896
5e8351de
BL		 2897static int rt5670_i2c_probe(struct i2c_client *i2c,
2898 const struct i2c_device_id *id)
2899{
2900 struct rt5670_platform_data *pdata = dev_get_platdata(&i2c->dev);
2901 struct rt5670_priv *rt5670;
2902 int ret;
2903 unsigned int val;
2904
2905 rt5670 = devm_kzalloc(&i2c->dev,
2906 sizeof(struct rt5670_priv),
2907 GFP_KERNEL);
2908 if (NULL == rt5670)
2909 return -ENOMEM;
2910
2911 i2c_set_clientdata(i2c, rt5670);
2912
2913 if (pdata)
2914 rt5670->pdata = *pdata;
2915
8e1b1785
PLB		 2916 dmi_check_system(dmi_platform_intel_quirks);
2917 if (quirk_override) {
2918 dev_info(&i2c->dev, "Overriding quirk 0x%x => 0x%x\n",
2919 (unsigned int)rt5670_quirk, quirk_override);
2920 rt5670_quirk = quirk_override;
2921 }
2922
2923 if (rt5670_quirk & RT5670_DEV_GPIO) {
d3ef7054 2924 rt5670->pdata.dev_gpio = true;
8e1b1785
PLB		 2925 dev_info(&i2c->dev, "quirk dev_gpio\n");
2926 }
2927 if (rt5670_quirk & RT5670_IN2_DIFF) {
2928 rt5670->pdata.in2_diff = true;
2929 dev_info(&i2c->dev, "quirk IN2_DIFF\n");
2930 }
2931 if (rt5670_quirk & RT5670_DMIC_EN) {
8cffb503 2932 rt5670->pdata.dmic_en = true;
8e1b1785
PLB		 2933 dev_info(&i2c->dev, "quirk DMIC enabled\n");
2934 }
2935 if (rt5670_quirk & RT5670_DMIC1_IN2P) {
8cffb503 2936 rt5670->pdata.dmic1_data_pin = RT5670_DMIC_DATA_IN2P;
8e1b1785
PLB		 2937 dev_info(&i2c->dev, "quirk DMIC1 on IN2P pin\n");
2938 }
2939 if (rt5670_quirk & RT5670_DMIC1_GPIO6) {
2940 rt5670->pdata.dmic1_data_pin = RT5670_DMIC_DATA_GPIO6;
2941 dev_info(&i2c->dev, "quirk DMIC1 on GPIO6 pin\n");
2942 }
2943 if (rt5670_quirk & RT5670_DMIC1_GPIO7) {
2944 rt5670->pdata.dmic1_data_pin = RT5670_DMIC_DATA_GPIO7;
2945 dev_info(&i2c->dev, "quirk DMIC1 on GPIO7 pin\n");
2946 }
2947 if (rt5670_quirk & RT5670_DMIC2_INR) {
2948 rt5670->pdata.dmic2_data_pin = RT5670_DMIC_DATA_IN3N;
2949 dev_info(&i2c->dev, "quirk DMIC2 on INR pin\n");
2950 }
2951 if (rt5670_quirk & RT5670_DMIC2_GPIO8) {
2952 rt5670->pdata.dmic2_data_pin = RT5670_DMIC_DATA_GPIO8;
2953 dev_info(&i2c->dev, "quirk DMIC2 on GPIO8 pin\n");
2954 }
2955 if (rt5670_quirk & RT5670_DMIC3_GPIO5) {
2956 rt5670->pdata.dmic3_data_pin = RT5670_DMIC_DATA_GPIO5;
2957 dev_info(&i2c->dev, "quirk DMIC3 on GPIO5 pin\n");
2958 }
2959
2960 if (rt5670_quirk & RT5670_JD_MODE1) {
2961 rt5670->pdata.jd_mode = 1;
2962 dev_info(&i2c->dev, "quirk JD mode 1\n");
2963 }
2964 if (rt5670_quirk & RT5670_JD_MODE2) {
8cffb503 2965 rt5670->pdata.jd_mode = 2;
8e1b1785
PLB		 2966 dev_info(&i2c->dev, "quirk JD mode 2\n");
2967 }
2968 if (rt5670_quirk & RT5670_JD_MODE3) {
c26d8389 2969 rt5670->pdata.jd_mode = 3;
8e1b1785 2970 dev_info(&i2c->dev, "quirk JD mode 3\n");
223c055a
BL		 2971 }
2972
5e8351de
BL		 2973 rt5670->regmap = devm_regmap_init_i2c(i2c, &rt5670_regmap);
2974 if (IS_ERR(rt5670->regmap)) {
2975 ret = PTR_ERR(rt5670->regmap);
2976 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2977 ret);
2978 return ret;
2979 }
2980
2981 regmap_read(rt5670->regmap, RT5670_VENDOR_ID2, &val);
2982 if (val != RT5670_DEVICE_ID) {
2983 dev_err(&i2c->dev,
387ad57f 2984 "Device with ID register %#x is not rt5670/72\n", val);
5e8351de
BL		 2985 return -ENODEV;
2986 }
2987
2988 regmap_write(rt5670->regmap, RT5670_RESET, 0);
2989 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
2990 RT5670_PWR_HP_L | RT5670_PWR_HP_R |
2991 RT5670_PWR_VREF2, RT5670_PWR_VREF2);
2992 msleep(100);
2993
2994 regmap_write(rt5670->regmap, RT5670_RESET, 0);
2995
2bf9eba1
BL		 2996 regmap_read(rt5670->regmap, RT5670_VENDOR_ID, &val);
2997 if (val >= 4)
2998 regmap_write(rt5670->regmap, RT5670_GPIO_CTRL3, 0x0980);
2999 else
3000 regmap_write(rt5670->regmap, RT5670_GPIO_CTRL3, 0x0d00);
3001
5e8351de
BL		 3002 ret = regmap_register_patch(rt5670->regmap, init_list,
3003 ARRAY_SIZE(init_list));
3004 if (ret != 0)
3005 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3006
a5d93da1
BL		 3007 regmap_update_bits(rt5670->regmap, RT5670_DIG_MISC,
3008 RT5670_MCLK_DET, RT5670_MCLK_DET);
3009
5e8351de
BL		 3010 if (rt5670->pdata.in2_diff)
3011 regmap_update_bits(rt5670->regmap, RT5670_IN2,
3012 RT5670_IN_DF2, RT5670_IN_DF2);
3013
d3ef7054
BL		 3014 if (rt5670->pdata.dev_gpio) {
3015 /* for push button */
3016 regmap_write(rt5670->regmap, RT5670_IL_CMD, 0x0000);
3017 regmap_write(rt5670->regmap, RT5670_IL_CMD2, 0x0010);
3018 regmap_write(rt5670->regmap, RT5670_IL_CMD3, 0x0014);
3019 /* for irq */
5e8351de
BL		 3020 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3021 RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_IRQ);
3022 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL2,
3023 RT5670_GP1_PF_MASK, RT5670_GP1_PF_OUT);
5e8351de
BL		 3024 }
3025
3026 if (rt5670->pdata.jd_mode) {
026e7368
BL		 3027 regmap_update_bits(rt5670->regmap, RT5670_GLB_CLK,
3028 RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_RCCLK);
3029 rt5670->sysclk = 0;
3030 rt5670->sysclk_src = RT5670_SCLK_S_RCCLK;
5e8351de
BL		 3031 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
3032 RT5670_PWR_MB, RT5670_PWR_MB);
3033 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG2,
3034 RT5670_PWR_JD1, RT5670_PWR_JD1);
3035 regmap_update_bits(rt5670->regmap, RT5670_IRQ_CTRL1,
3036 RT5670_JD1_1_EN_MASK, RT5670_JD1_1_EN);
3037 regmap_update_bits(rt5670->regmap, RT5670_JD_CTRL3,
3038 RT5670_JD_TRI_CBJ_SEL_MASK |
3039 RT5670_JD_TRI_HPO_SEL_MASK,
3040 RT5670_JD_CBJ_JD1_1 | RT5670_JD_HPO_JD1_1);
3041 switch (rt5670->pdata.jd_mode) {
3042 case 1:
3043 regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
3044 RT5670_JD1_MODE_MASK,
3045 RT5670_JD1_MODE_0);
3046 break;
3047 case 2:
3048 regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
3049 RT5670_JD1_MODE_MASK,
3050 RT5670_JD1_MODE_1);
3051 break;
3052 case 3:
3053 regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
3054 RT5670_JD1_MODE_MASK,
3055 RT5670_JD1_MODE_2);
3056 break;
3057 default:
3058 break;
3059 }
3060 }
3061
3062 if (rt5670->pdata.dmic_en) {
3063 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3064 RT5670_GP2_PIN_MASK,
3065 RT5670_GP2_PIN_DMIC1_SCL);
3066
3067 switch (rt5670->pdata.dmic1_data_pin) {
3068 case RT5670_DMIC_DATA_IN2P:
3069 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3070 RT5670_DMIC_1_DP_MASK,
3071 RT5670_DMIC_1_DP_IN2P);
3072 break;
3073
3074 case RT5670_DMIC_DATA_GPIO6:
3075 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3076 RT5670_DMIC_1_DP_MASK,
3077 RT5670_DMIC_1_DP_GPIO6);
3078 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3079 RT5670_GP6_PIN_MASK,
3080 RT5670_GP6_PIN_DMIC1_SDA);
3081 break;
3082
3083 case RT5670_DMIC_DATA_GPIO7:
3084 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3085 RT5670_DMIC_1_DP_MASK,
3086 RT5670_DMIC_1_DP_GPIO7);
3087 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3088 RT5670_GP7_PIN_MASK,
3089 RT5670_GP7_PIN_DMIC1_SDA);
3090 break;
3091
3092 default:
3093 break;
3094 }
3095
3096 switch (rt5670->pdata.dmic2_data_pin) {
3097 case RT5670_DMIC_DATA_IN3N:
3098 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3099 RT5670_DMIC_2_DP_MASK,
3100 RT5670_DMIC_2_DP_IN3N);
3101 break;
3102
3103 case RT5670_DMIC_DATA_GPIO8:
3104 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3105 RT5670_DMIC_2_DP_MASK,
3106 RT5670_DMIC_2_DP_GPIO8);
3107 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3108 RT5670_GP8_PIN_MASK,
3109 RT5670_GP8_PIN_DMIC2_SDA);
3110 break;
3111
3112 default:
3113 break;
3114 }
3115
3116 switch (rt5670->pdata.dmic3_data_pin) {
3117 case RT5670_DMIC_DATA_GPIO5:
3118 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL2,
3119 RT5670_DMIC_3_DP_MASK,
3120 RT5670_DMIC_3_DP_GPIO5);
3121 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3122 RT5670_GP5_PIN_MASK,
3123 RT5670_GP5_PIN_DMIC3_SDA);
3124 break;
3125
3126 case RT5670_DMIC_DATA_GPIO9:
3127 case RT5670_DMIC_DATA_GPIO10:
3128 dev_err(&i2c->dev,
3129 "Always use GPIO5 as DMIC3 data pin\n");
3130 break;
3131
3132 default:
3133 break;
3134 }
3135
3136 }
3137
64e89e5f
BL		 3138 pm_runtime_enable(&i2c->dev);
3139 pm_request_idle(&i2c->dev);
3140
5ba04c66
KM		 3141 ret = devm_snd_soc_register_component(&i2c->dev,
3142 &soc_component_dev_rt5670,
5e8351de
BL		 3143 rt5670_dai, ARRAY_SIZE(rt5670_dai));
3144 if (ret < 0)
3145 goto err;
3146
64e89e5f
BL		 3147 pm_runtime_put(&i2c->dev);
3148
5e8351de
BL		 3149 return 0;
3150err:
64e89e5f
BL		 3151 pm_runtime_disable(&i2c->dev);
3152
5e8351de
BL		 3153 return ret;
3154}
3155
3156static int rt5670_i2c_remove(struct i2c_client *i2c)
3157{
64e89e5f 3158 pm_runtime_disable(&i2c->dev);
5e8351de
BL		 3159
3160 return 0;
3161}
3162
ff62b958 3163static struct i2c_driver rt5670_i2c_driver = {
5e8351de
BL		 3164 .driver = {
3165 .name = "rt5670",
0605815e 3166 .acpi_match_table = ACPI_PTR(rt5670_acpi_match),
5e8351de
BL		 3167 },
3168 .probe = rt5670_i2c_probe,
3169 .remove = rt5670_i2c_remove,
3170 .id_table = rt5670_i2c_id,
3171};
3172
3173module_i2c_driver(rt5670_i2c_driver);
3174
3175MODULE_DESCRIPTION("ASoC RT5670 driver");
3176MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3177MODULE_LICENSE("GPL v2");
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