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ASoC: rt5677: add i2s asrc clk src selection
[mirror_ubuntu-eoan-kernel.git] / sound / soc / codecs / rt5677.c
CommitLineData
0e826e86
OC		 1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
f9f6a592 18#include <linux/of_gpio.h>
0e826e86
OC		 19#include <linux/regmap.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
af48f1d0 23#include <linux/firmware.h>
44caf764 24#include <linux/gpio.h>
0e826e86
OC		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
30f14b43 33#include "rl6231.h"
0e826e86 34#include "rt5677.h"
af48f1d0 35#include "rt5677-spi.h"
0e826e86
OC		 36
37#define RT5677_DEVICE_ID 0x6327
38
39#define RT5677_PR_RANGE_BASE (0xff + 1)
40#define RT5677_PR_SPACING 0x100
41
42#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44static const struct regmap_range_cfg rt5677_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
53 .window_len = 0x1,
54 },
55};
56
57static const struct reg_default init_list[] = {
2dfe2b08
OC		 58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
0e826e86
OC		 65};
66#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
67
68static const struct reg_default rt5677_reg[] = {
69 {RT5677_RESET , 0x0000},
70 {RT5677_LOUT1 , 0xa800},
71 {RT5677_IN1 , 0x0000},
72 {RT5677_MICBIAS , 0x0000},
73 {RT5677_SLIMBUS_PARAM , 0x0000},
74 {RT5677_SLIMBUS_RX , 0x0000},
75 {RT5677_SLIMBUS_CTRL , 0x0000},
76 {RT5677_SIDETONE_CTRL , 0x000b},
77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
79 {RT5677_DAC4_DIG_VOL , 0xafaf},
80 {RT5677_DAC3_DIG_VOL , 0xafaf},
81 {RT5677_DAC1_DIG_VOL , 0xafaf},
82 {RT5677_DAC2_DIG_VOL , 0xafaf},
83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO1_2_ADC_BST , 0x0000},
87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_ADC_BST_CTRL2 , 0x0000},
89 {RT5677_STO3_4_ADC_BST , 0x0000},
90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
92 {RT5677_STO4_ADC_MIXER , 0xd4c0},
93 {RT5677_STO3_ADC_MIXER , 0xd4c0},
94 {RT5677_STO2_ADC_MIXER , 0xd4c0},
95 {RT5677_STO1_ADC_MIXER , 0xd4c0},
96 {RT5677_MONO_ADC_MIXER , 0xd4d1},
97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
98 {RT5677_STO1_DAC_MIXER , 0xaaaa},
99 {RT5677_MONO_DAC_MIXER , 0xaaaa},
100 {RT5677_DD1_MIXER , 0xaaaa},
101 {RT5677_DD2_MIXER , 0xaaaa},
102 {RT5677_IF3_DATA , 0x0000},
103 {RT5677_IF4_DATA , 0x0000},
104 {RT5677_PDM_OUT_CTRL , 0x8888},
105 {RT5677_PDM_DATA_CTRL1 , 0x0000},
106 {RT5677_PDM_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
113 {RT5677_TDM1_CTRL1 , 0x0300},
114 {RT5677_TDM1_CTRL2 , 0x0000},
115 {RT5677_TDM1_CTRL3 , 0x4000},
116 {RT5677_TDM1_CTRL4 , 0x0123},
117 {RT5677_TDM1_CTRL5 , 0x4567},
118 {RT5677_TDM2_CTRL1 , 0x0300},
119 {RT5677_TDM2_CTRL2 , 0x0000},
120 {RT5677_TDM2_CTRL3 , 0x4000},
121 {RT5677_TDM2_CTRL4 , 0x0123},
122 {RT5677_TDM2_CTRL5 , 0x4567},
123 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
124 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
131 {RT5677_DMIC_CTRL1 , 0x1505},
132 {RT5677_DMIC_CTRL2 , 0x0055},
133 {RT5677_HAP_GENE_CTRL1 , 0x0111},
134 {RT5677_HAP_GENE_CTRL2 , 0x0064},
135 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL9 , 0xf000},
142 {RT5677_HAP_GENE_CTRL10 , 0x0000},
143 {RT5677_PWR_DIG1 , 0x0000},
144 {RT5677_PWR_DIG2 , 0x0000},
145 {RT5677_PWR_ANLG1 , 0x0055},
146 {RT5677_PWR_ANLG2 , 0x0000},
147 {RT5677_PWR_DSP1 , 0x0001},
148 {RT5677_PWR_DSP_ST , 0x0000},
149 {RT5677_PWR_DSP2 , 0x0000},
150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
151 {RT5677_PRIV_INDEX , 0x0000},
152 {RT5677_PRIV_DATA , 0x0000},
153 {RT5677_I2S4_SDP , 0x8000},
154 {RT5677_I2S1_SDP , 0x8000},
155 {RT5677_I2S2_SDP , 0x8000},
156 {RT5677_I2S3_SDP , 0x8000},
157 {RT5677_CLK_TREE_CTRL1 , 0x1111},
158 {RT5677_CLK_TREE_CTRL2 , 0x1111},
159 {RT5677_CLK_TREE_CTRL3 , 0x0000},
160 {RT5677_PLL1_CTRL1 , 0x0000},
161 {RT5677_PLL1_CTRL2 , 0x0000},
162 {RT5677_PLL2_CTRL1 , 0x0c60},
163 {RT5677_PLL2_CTRL2 , 0x2000},
164 {RT5677_GLB_CLK1 , 0x0000},
165 {RT5677_GLB_CLK2 , 0x0000},
166 {RT5677_ASRC_1 , 0x0000},
167 {RT5677_ASRC_2 , 0x0000},
168 {RT5677_ASRC_3 , 0x0000},
169 {RT5677_ASRC_4 , 0x0000},
170 {RT5677_ASRC_5 , 0x0000},
171 {RT5677_ASRC_6 , 0x0000},
172 {RT5677_ASRC_7 , 0x0000},
173 {RT5677_ASRC_8 , 0x0000},
174 {RT5677_ASRC_9 , 0x0000},
175 {RT5677_ASRC_10 , 0x0000},
176 {RT5677_ASRC_11 , 0x0000},
86ae04b1 177 {RT5677_ASRC_12 , 0x0018},
0e826e86
OC		 178 {RT5677_ASRC_13 , 0x0000},
179 {RT5677_ASRC_14 , 0x0000},
180 {RT5677_ASRC_15 , 0x0000},
181 {RT5677_ASRC_16 , 0x0000},
182 {RT5677_ASRC_17 , 0x0000},
183 {RT5677_ASRC_18 , 0x0000},
184 {RT5677_ASRC_19 , 0x0000},
185 {RT5677_ASRC_20 , 0x0000},
186 {RT5677_ASRC_21 , 0x000c},
187 {RT5677_ASRC_22 , 0x0000},
188 {RT5677_ASRC_23 , 0x0000},
189 {RT5677_VAD_CTRL1 , 0x2184},
190 {RT5677_VAD_CTRL2 , 0x010a},
191 {RT5677_VAD_CTRL3 , 0x0aea},
192 {RT5677_VAD_CTRL4 , 0x000c},
193 {RT5677_VAD_CTRL5 , 0x0000},
194 {RT5677_DSP_INB_CTRL1 , 0x0000},
195 {RT5677_DSP_INB_CTRL2 , 0x0000},
196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
201 {RT5677_ADC_EQ_CTRL1 , 0x6000},
202 {RT5677_ADC_EQ_CTRL2 , 0x0000},
203 {RT5677_EQ_CTRL1 , 0xc000},
204 {RT5677_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL3 , 0x0000},
206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
207 {RT5677_JD_CTRL1 , 0x0000},
208 {RT5677_JD_CTRL2 , 0x0000},
209 {RT5677_JD_CTRL3 , 0x0000},
210 {RT5677_IRQ_CTRL1 , 0x0000},
211 {RT5677_IRQ_CTRL2 , 0x0000},
212 {RT5677_GPIO_ST , 0x0000},
213 {RT5677_GPIO_CTRL1 , 0x0000},
214 {RT5677_GPIO_CTRL2 , 0x0000},
215 {RT5677_GPIO_CTRL3 , 0x0000},
216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_MB_DRC_CTRL1 , 0x0f20},
227 {RT5677_DRC1_CTRL1 , 0x001f},
228 {RT5677_DRC1_CTRL2 , 0x020c},
229 {RT5677_DRC1_CTRL3 , 0x1f00},
230 {RT5677_DRC1_CTRL4 , 0x0000},
231 {RT5677_DRC1_CTRL5 , 0x0000},
232 {RT5677_DRC1_CTRL6 , 0x0029},
233 {RT5677_DRC2_CTRL1 , 0x001f},
234 {RT5677_DRC2_CTRL2 , 0x020c},
235 {RT5677_DRC2_CTRL3 , 0x1f00},
236 {RT5677_DRC2_CTRL4 , 0x0000},
237 {RT5677_DRC2_CTRL5 , 0x0000},
238 {RT5677_DRC2_CTRL6 , 0x0029},
239 {RT5677_DRC1_HL_CTRL1 , 0x8000},
240 {RT5677_DRC1_HL_CTRL2 , 0x0200},
241 {RT5677_DRC2_HL_CTRL1 , 0x8000},
242 {RT5677_DRC2_HL_CTRL2 , 0x0200},
243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
266 {RT5677_DIG_MISC , 0x0000},
267 {RT5677_GEN_CTRL1 , 0x0000},
268 {RT5677_GEN_CTRL2 , 0x0000},
269 {RT5677_VENDOR_ID , 0x0000},
270 {RT5677_VENDOR_ID1 , 0x10ec},
271 {RT5677_VENDOR_ID2 , 0x6327},
272};
273
274static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
275{
276 int i;
277
278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
279 if (reg >= rt5677_ranges[i].range_min &&
280 reg <= rt5677_ranges[i].range_max) {
281 return true;
282 }
283 }
284
285 switch (reg) {
286 case RT5677_RESET:
287 case RT5677_SLIMBUS_PARAM:
288 case RT5677_PDM_DATA_CTRL1:
289 case RT5677_PDM_DATA_CTRL2:
290 case RT5677_PDM1_DATA_CTRL4:
291 case RT5677_PDM2_DATA_CTRL4:
292 case RT5677_I2C_MASTER_CTRL1:
293 case RT5677_I2C_MASTER_CTRL7:
294 case RT5677_I2C_MASTER_CTRL8:
295 case RT5677_HAP_GENE_CTRL2:
296 case RT5677_PWR_DSP_ST:
297 case RT5677_PRIV_DATA:
298 case RT5677_PLL1_CTRL2:
299 case RT5677_PLL2_CTRL2:
300 case RT5677_ASRC_22:
301 case RT5677_ASRC_23:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
307 case RT5677_GPIO_ST:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
316 return true;
317 default:
318 return false;
319 }
320}
321
322static bool rt5677_readable_register(struct device *dev, unsigned int reg)
323{
324 int i;
325
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
329 return true;
330 }
331 }
332
333 switch (reg) {
334 case RT5677_RESET:
335 case RT5677_LOUT1:
336 case RT5677_IN1:
337 case RT5677_MICBIAS:
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
431 case RT5677_ASRC_1:
432 case RT5677_ASRC_2:
433 case RT5677_ASRC_3:
434 case RT5677_ASRC_4:
435 case RT5677_ASRC_5:
436 case RT5677_ASRC_6:
437 case RT5677_ASRC_7:
438 case RT5677_ASRC_8:
439 case RT5677_ASRC_9:
440 case RT5677_ASRC_10:
441 case RT5677_ASRC_11:
442 case RT5677_ASRC_12:
443 case RT5677_ASRC_13:
444 case RT5677_ASRC_14:
445 case RT5677_ASRC_15:
446 case RT5677_ASRC_16:
447 case RT5677_ASRC_17:
448 case RT5677_ASRC_18:
449 case RT5677_ASRC_19:
450 case RT5677_ASRC_20:
451 case RT5677_ASRC_21:
452 case RT5677_ASRC_22:
453 case RT5677_ASRC_23:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
477 case RT5677_GPIO_ST:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
537 return true;
538 default:
539 return false;
540 }
541}
542
af48f1d0
OC		 543/**
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
19ba484d 545 * @rt5677: Private Data.
af48f1d0
OC		 546 * @addr: Address index.
547 * @value: Address data.
548 *
549 *
550 * Returns 0 for success or negative error code.
551 */
19ba484d 552static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
af48f1d0
OC		 553 unsigned int addr, unsigned int value, unsigned int opcode)
554{
19ba484d 555 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 556 int ret;
557
558 mutex_lock(&rt5677->dsp_cmd_lock);
559
19ba484d
OC		 560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
561 addr >> 16);
af48f1d0
OC		 562 if (ret < 0) {
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
564 goto err;
565 }
566
19ba484d 567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 568 addr & 0xffff);
569 if (ret < 0) {
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
571 goto err;
572 }
573
19ba484d 574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
af48f1d0
OC		 575 value >> 16);
576 if (ret < 0) {
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
578 goto err;
579 }
580
19ba484d 581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
af48f1d0
OC		 582 value & 0xffff);
583 if (ret < 0) {
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
585 goto err;
586 }
587
19ba484d
OC		 588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
589 opcode);
af48f1d0
OC		 590 if (ret < 0) {
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
592 goto err;
593 }
594
595err:
596 mutex_unlock(&rt5677->dsp_cmd_lock);
597
598 return ret;
599}
600
601/**
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
19ba484d 603 * rt5677: Private Data.
af48f1d0
OC		 604 * @addr: Address index.
605 * @value: Address data.
606 *
19ba484d 607 *
af48f1d0
OC		 608 * Returns 0 for success or negative error code.
609 */
610static int rt5677_dsp_mode_i2c_read_addr(
19ba484d 611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
af48f1d0 612{
19ba484d 613 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 614 int ret;
615 unsigned int msb, lsb;
616
617 mutex_lock(&rt5677->dsp_cmd_lock);
618
19ba484d
OC		 619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
620 addr >> 16);
af48f1d0
OC		 621 if (ret < 0) {
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
623 goto err;
624 }
625
19ba484d 626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 627 addr & 0xffff);
628 if (ret < 0) {
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
630 goto err;
631 }
632
19ba484d
OC		 633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
634 0x0002);
af48f1d0
OC		 635 if (ret < 0) {
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
637 goto err;
638 }
639
19ba484d
OC		 640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
af48f1d0
OC		 642 *value = (msb << 16) | lsb;
643
644err:
645 mutex_unlock(&rt5677->dsp_cmd_lock);
646
647 return ret;
648}
649
650/**
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
19ba484d 652 * rt5677: Private Data.
af48f1d0
OC		 653 * @reg: Register index.
654 * @value: Register data.
655 *
656 *
657 * Returns 0 for success or negative error code.
658 */
19ba484d 659static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
af48f1d0
OC		 660 unsigned int reg, unsigned int value)
661{
19ba484d 662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
af48f1d0
OC		 663 value, 0x0001);
664}
665
666/**
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
19ba484d 670 * @value: Register data.
af48f1d0
OC		 671 *
672 *
19ba484d 673 * Returns 0 for success or negative error code.
af48f1d0 674 */
19ba484d
OC		 675static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
af48f1d0 677{
19ba484d
OC		 678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
679 value);
af48f1d0 680
19ba484d 681 *value &= 0xffff;
af48f1d0 682
19ba484d 683 return ret;
af48f1d0
OC		 684}
685
19ba484d 686static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
af48f1d0 687{
19ba484d 688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
af48f1d0 689
19ba484d
OC		 690 if (on) {
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
693 } else {
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
af48f1d0 696 }
af48f1d0
OC		 697}
698
699static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
700{
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
703 int ret;
704
4c121129
AB		 705 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
706 return -ENXIO;
707
af48f1d0
OC		 708 if (on && !activity) {
709 activity = true;
710
711 regcache_cache_only(rt5677->regmap, false);
712 regcache_cache_bypass(rt5677->regmap, true);
713
714 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
715 regmap_update_bits(rt5677->regmap,
716 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
717 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
718 RT5677_LDO1_SEL_MASK, 0x0);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
720 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
ab1f7095
OC		 721 switch (rt5677->type) {
722 case RT5677:
723 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
724 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
725 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
726 RT5677_PLL2_PR_SRC_MASK |
727 RT5677_DSP_CLK_SRC_MASK,
728 RT5677_PLL2_PR_SRC_MCLK2 |
729 RT5677_DSP_CLK_SRC_BYPASS);
730 break;
731 case RT5676:
732 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
733 RT5677_DSP_CLK_SRC_MASK,
734 RT5677_DSP_CLK_SRC_BYPASS);
735 break;
736 default:
737 break;
738 }
af48f1d0 739 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
19ba484d
OC		 740 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
741 rt5677_set_dsp_mode(codec, true);
af48f1d0
OC		 742
743 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
744 codec->dev);
745 if (ret == 0) {
746 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
747 release_firmware(rt5677->fw1);
748 }
749
750 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
751 codec->dev);
752 if (ret == 0) {
753 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
754 release_firmware(rt5677->fw2);
755 }
756
19ba484d 757 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
af48f1d0
OC		 758
759 regcache_cache_bypass(rt5677->regmap, false);
760 regcache_cache_only(rt5677->regmap, true);
761 } else if (!on && activity) {
762 activity = false;
763
764 regcache_cache_only(rt5677->regmap, false);
765 regcache_cache_bypass(rt5677->regmap, true);
766
19ba484d
OC		 767 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
768 rt5677_set_dsp_mode(codec, false);
769 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
af48f1d0
OC		 770
771 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
772
773 regcache_cache_bypass(rt5677->regmap, false);
774 regcache_mark_dirty(rt5677->regmap);
775 regcache_sync(rt5677->regmap);
776 }
777
778 return 0;
779}
780
0e826e86 781static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
40e3262e 782static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
0e826e86 783static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
40e3262e 784static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
0e826e86 785static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
90bdbb46 786static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
0e826e86
OC		 787
788/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
789static unsigned int bst_tlv[] = {
790 TLV_DB_RANGE_HEAD(7),
791 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
792 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
793 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
794 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
795 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
796 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
797 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
798};
799
af48f1d0
OC		 800static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
801 struct snd_ctl_elem_value *ucontrol)
802{
6087fcab
FY		 803 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
804 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
af48f1d0
OC		 805
806 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
807
808 return 0;
809}
810
811static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
812 struct snd_ctl_elem_value *ucontrol)
813{
6087fcab
FY		 814 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
815 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
816 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
af48f1d0
OC		 817
818 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
819
820 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
821 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
822
823 return 0;
824}
825
0e826e86
OC		 826static const struct snd_kcontrol_new rt5677_snd_controls[] = {
827 /* OUTPUT Control */
828 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
829 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
830 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
831 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
832 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
833 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
834
835 /* DAC Digital Volume */
836 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
40e3262e 837 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 838 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
40e3262e 839 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 840 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
40e3262e 841 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 842 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
40e3262e 843 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86
OC		 844
845 /* IN1/IN2 Control */
846 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
847 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
848
849 /* ADC Digital Volume Control */
850 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
851 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
852 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
853 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
854 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
855 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
856 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
857 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
858 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
859 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
860
861 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
40e3262e 862 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 863 adc_vol_tlv),
864 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
40e3262e 865 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 866 adc_vol_tlv),
867 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
40e3262e 868 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 869 adc_vol_tlv),
870 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
40e3262e 871 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 872 adc_vol_tlv),
873 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
40e3262e 874 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 875 adc_vol_tlv),
876
90bdbb46
OC		 877 /* Sidetone Control */
878 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
879 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
880
0e826e86 881 /* ADC Boost Volume Control */
80220f29 882 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 883 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
884 adc_bst_tlv),
80220f29 885 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 886 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
887 adc_bst_tlv),
80220f29 888 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 889 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
890 adc_bst_tlv),
80220f29 891 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 892 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
893 adc_bst_tlv),
80220f29 894 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
0e826e86
OC		 895 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
896 adc_bst_tlv),
af48f1d0
OC		 897
898 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
899 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
0e826e86
OC		 900};
901
902/**
903 * set_dmic_clk - Set parameter of dmic.
904 *
905 * @w: DAPM widget.
906 * @kcontrol: The kcontrol of this widget.
907 * @event: Event id.
908 *
909 * Choose dmic clock between 1MHz and 3MHz.
910 * It is better for clock to approximate 3MHz.
911 */
912static int set_dmic_clk(struct snd_soc_dapm_widget *w,
913 struct snd_kcontrol *kcontrol, int event)
914{
46f20872 915 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86 916 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
9a53581e 917 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
0e826e86
OC		 918
919 if (idx < 0)
920 dev_err(codec->dev, "Failed to set DMIC clock\n");
921 else
922 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
923 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
924 return idx;
925}
926
927static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
928 struct snd_soc_dapm_widget *sink)
929{
46f20872
LPC		 930 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
931 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
0e826e86
OC		 932 unsigned int val;
933
934 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
935 val &= RT5677_SCLK_SRC_MASK;
936 if (val == RT5677_SCLK_SRC_PLL1)
937 return 1;
938 else
939 return 0;
940}
941
5a8c7c26
OC		 942static int is_using_asrc(struct snd_soc_dapm_widget *source,
943 struct snd_soc_dapm_widget *sink)
944{
46f20872 945 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
e4b7e6a8 946 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
5a8c7c26
OC		 947 unsigned int reg, shift, val;
948
949 if (source->reg == RT5677_ASRC_1) {
950 switch (source->shift) {
951 case 12:
952 reg = RT5677_ASRC_4;
953 shift = 0;
954 break;
955 case 13:
956 reg = RT5677_ASRC_4;
957 shift = 4;
958 break;
959 case 14:
960 reg = RT5677_ASRC_4;
961 shift = 8;
962 break;
963 case 15:
964 reg = RT5677_ASRC_4;
965 shift = 12;
966 break;
967 default:
968 return 0;
969 }
970 } else {
971 switch (source->shift) {
972 case 0:
973 reg = RT5677_ASRC_6;
974 shift = 8;
975 break;
976 case 1:
977 reg = RT5677_ASRC_6;
978 shift = 12;
979 break;
980 case 2:
981 reg = RT5677_ASRC_5;
982 shift = 0;
983 break;
984 case 3:
985 reg = RT5677_ASRC_5;
986 shift = 4;
987 break;
988 case 4:
989 reg = RT5677_ASRC_5;
990 shift = 8;
991 break;
992 case 5:
993 reg = RT5677_ASRC_5;
994 shift = 12;
995 break;
996 case 12:
997 reg = RT5677_ASRC_3;
998 shift = 0;
999 break;
1000 case 13:
1001 reg = RT5677_ASRC_3;
1002 shift = 4;
1003 break;
1004 case 14:
1005 reg = RT5677_ASRC_3;
1006 shift = 12;
1007 break;
1008 default:
1009 return 0;
1010 }
1011 }
1012
e4b7e6a8
OC		 1013 regmap_read(rt5677->regmap, reg, &val);
1014 val = (val >> shift) & 0xf;
1015
5a8c7c26
OC		 1016 switch (val) {
1017 case 1 ... 6:
1018 return 1;
1019 default:
1020 return 0;
1021 }
1022
1023}
1024
1025static int can_use_asrc(struct snd_soc_dapm_widget *source,
1026 struct snd_soc_dapm_widget *sink)
1027{
1028 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1029 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1030
1031 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1032 return 1;
1033
1034 return 0;
1035}
1036
c36aa0a1
OC		 1037/**
1038 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1039 * @codec: SoC audio codec device.
1040 * @filter_mask: mask of filters.
1041 * @clk_src: clock source
1042 *
1043 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1044 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1045 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1046 * ASRC function will track i2s clock and generate a corresponding system clock
1047 * for codec. This function provides an API to select the clock source for a
1048 * set of filters specified by the mask. And the codec driver will turn on ASRC
1049 * for these filters if ASRC is selected as their clock source.
1050 */
1051int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1052 unsigned int filter_mask, unsigned int clk_src)
1053{
1054 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1055 unsigned int asrc3_mask = 0, asrc3_value = 0;
1056 unsigned int asrc4_mask = 0, asrc4_value = 0;
1057 unsigned int asrc5_mask = 0, asrc5_value = 0;
1058 unsigned int asrc6_mask = 0, asrc6_value = 0;
1059 unsigned int asrc7_mask = 0, asrc7_value = 0;
16ab6e18 1060 unsigned int asrc8_mask = 0, asrc8_value = 0;
c36aa0a1
OC		 1061
1062 switch (clk_src) {
1063 case RT5677_CLK_SEL_SYS:
1064 case RT5677_CLK_SEL_I2S1_ASRC:
1065 case RT5677_CLK_SEL_I2S2_ASRC:
1066 case RT5677_CLK_SEL_I2S3_ASRC:
1067 case RT5677_CLK_SEL_I2S4_ASRC:
1068 case RT5677_CLK_SEL_I2S5_ASRC:
1069 case RT5677_CLK_SEL_I2S6_ASRC:
1070 case RT5677_CLK_SEL_SYS2:
1071 case RT5677_CLK_SEL_SYS3:
1072 case RT5677_CLK_SEL_SYS4:
1073 case RT5677_CLK_SEL_SYS5:
1074 case RT5677_CLK_SEL_SYS6:
1075 case RT5677_CLK_SEL_SYS7:
1076 break;
1077
1078 default:
1079 return -EINVAL;
1080 }
1081
1082 /* ASRC 3 */
1083 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1084 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1085 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1086 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1087 }
1088
1089 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1090 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1091 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1092 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1093 }
1094
1095 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1096 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1097 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1098 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1099 }
1100
1101 if (asrc3_mask)
1102 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1103 asrc3_value);
1104
1105 /* ASRC 4 */
1106 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1107 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1108 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1109 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1110 }
1111
1112 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1113 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1114 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1115 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1116 }
1117
1118 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1119 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1120 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1121 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1122 }
1123
1124 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1125 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1126 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1127 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1128 }
1129
1130 if (asrc4_mask)
1131 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1132 asrc4_value);
1133
1134 /* ASRC 5 */
1135 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1136 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1137 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1138 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1139 }
1140
1141 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1142 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1143 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1144 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1145 }
1146
1147 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1148 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1149 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1150 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1151 }
1152
1153 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1154 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1155 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1156 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1157 }
1158
1159 if (asrc5_mask)
1160 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1161 asrc5_value);
1162
1163 /* ASRC 6 */
1164 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1165 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1166 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1167 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1168 }
1169
1170 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1171 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1172 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1173 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1174 }
1175
1176 if (asrc6_mask)
1177 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1178 asrc6_value);
1179
1180 /* ASRC 7 */
1181 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1182 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1183 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1184 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1185 }
1186
1187 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1188 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1189 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1190 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1191 }
1192
1193 if (asrc7_mask)
1194 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1195 asrc7_value);
1196
16ab6e18
BL		 1197 /* ASRC 8 */
1198 if (filter_mask & RT5677_I2S1_SOURCE) {
1199 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1200 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1201 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1202 }
1203
1204 if (filter_mask & RT5677_I2S2_SOURCE) {
1205 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1206 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1207 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1208 }
1209
1210 if (filter_mask & RT5677_I2S3_SOURCE) {
1211 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1212 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1213 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1214 }
1215
1216 if (filter_mask & RT5677_I2S4_SOURCE) {
1217 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1218 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1219 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1220 }
1221
1222 if (asrc8_mask)
1223 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1224 asrc8_value);
1225
c36aa0a1
OC		 1226 return 0;
1227}
1228EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1229
0e826e86
OC		 1230/* Digital Mixer */
1231static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1232 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1233 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1234 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1235 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1236};
1237
1238static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1239 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1240 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1241 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1242 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1243};
1244
1245static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1246 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1247 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1248 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1249 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1250};
1251
1252static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1253 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1254 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1255 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1256 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1257};
1258
1259static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1260 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1261 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1262 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1263 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1264};
1265
1266static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1267 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1268 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1269 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1270 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1271};
1272
1273static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1274 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1275 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1276 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1277 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1278};
1279
1280static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1281 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1282 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1283 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1284 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1285};
1286
1287static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1288 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1289 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1290 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1291 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1292};
1293
1294static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1295 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1296 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1297 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1298 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1299};
1300
1301static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1302 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1303 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1304 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1305 RT5677_M_DAC1_L_SFT, 1, 1),
1306};
1307
1308static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1309 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1310 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1311 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1312 RT5677_M_DAC1_R_SFT, 1, 1),
1313};
1314
1315static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1316 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1317 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1318 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1319 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1320 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1321 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1322 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1323 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1324};
1325
1326static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1327 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1328 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1329 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1330 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1331 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1332 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1333 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1334 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1335};
1336
1337static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1338 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1339 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1340 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1341 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1342 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1343 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1344 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1345 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1346};
1347
1348static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1349 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1350 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1351 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1352 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1353 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1354 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1355 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1356 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1357};
1358
1359static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1360 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1361 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1362 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1363 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1364 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1365 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1366 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1367 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1368};
1369
1370static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1371 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1372 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1373 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1374 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1375 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1376 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1377 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1378 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1379};
1380
1381static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1382 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1383 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1384 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1385 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1386 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1387 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1388 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1389 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1390};
1391
1392static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1393 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1394 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1395 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1396 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1397 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1398 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1399 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1400 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1401};
1402
1403static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1404 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1405 RT5677_DSP_IB_01_H_SFT, 1, 1),
1406 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1407 RT5677_DSP_IB_23_H_SFT, 1, 1),
1408 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1409 RT5677_DSP_IB_45_H_SFT, 1, 1),
1410 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1411 RT5677_DSP_IB_6_H_SFT, 1, 1),
1412 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1413 RT5677_DSP_IB_7_H_SFT, 1, 1),
1414 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1415 RT5677_DSP_IB_8_H_SFT, 1, 1),
1416 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1417 RT5677_DSP_IB_9_H_SFT, 1, 1),
1418};
1419
1420static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1421 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1422 RT5677_DSP_IB_01_L_SFT, 1, 1),
1423 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1424 RT5677_DSP_IB_23_L_SFT, 1, 1),
1425 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1426 RT5677_DSP_IB_45_L_SFT, 1, 1),
1427 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1428 RT5677_DSP_IB_6_L_SFT, 1, 1),
1429 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1430 RT5677_DSP_IB_7_L_SFT, 1, 1),
1431 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1432 RT5677_DSP_IB_8_L_SFT, 1, 1),
1433 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1434 RT5677_DSP_IB_9_L_SFT, 1, 1),
1435};
1436
1437static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1438 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1439 RT5677_DSP_IB_01_H_SFT, 1, 1),
1440 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1441 RT5677_DSP_IB_23_H_SFT, 1, 1),
1442 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1443 RT5677_DSP_IB_45_H_SFT, 1, 1),
1444 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1445 RT5677_DSP_IB_6_H_SFT, 1, 1),
1446 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1447 RT5677_DSP_IB_7_H_SFT, 1, 1),
1448 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1449 RT5677_DSP_IB_8_H_SFT, 1, 1),
1450 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1451 RT5677_DSP_IB_9_H_SFT, 1, 1),
1452};
1453
1454static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1455 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1456 RT5677_DSP_IB_01_L_SFT, 1, 1),
1457 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1458 RT5677_DSP_IB_23_L_SFT, 1, 1),
1459 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1460 RT5677_DSP_IB_45_L_SFT, 1, 1),
1461 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1462 RT5677_DSP_IB_6_L_SFT, 1, 1),
1463 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1464 RT5677_DSP_IB_7_L_SFT, 1, 1),
1465 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1466 RT5677_DSP_IB_8_L_SFT, 1, 1),
1467 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1468 RT5677_DSP_IB_9_L_SFT, 1, 1),
1469};
1470
1471static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1472 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1473 RT5677_DSP_IB_01_H_SFT, 1, 1),
1474 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1475 RT5677_DSP_IB_23_H_SFT, 1, 1),
1476 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1477 RT5677_DSP_IB_45_H_SFT, 1, 1),
1478 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1479 RT5677_DSP_IB_6_H_SFT, 1, 1),
1480 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1481 RT5677_DSP_IB_7_H_SFT, 1, 1),
1482 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1483 RT5677_DSP_IB_8_H_SFT, 1, 1),
1484 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1485 RT5677_DSP_IB_9_H_SFT, 1, 1),
1486};
1487
1488static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1489 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1490 RT5677_DSP_IB_01_L_SFT, 1, 1),
1491 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1492 RT5677_DSP_IB_23_L_SFT, 1, 1),
1493 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1494 RT5677_DSP_IB_45_L_SFT, 1, 1),
1495 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1496 RT5677_DSP_IB_6_L_SFT, 1, 1),
1497 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1498 RT5677_DSP_IB_7_L_SFT, 1, 1),
1499 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1500 RT5677_DSP_IB_8_L_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1502 RT5677_DSP_IB_9_L_SFT, 1, 1),
1503};
1504
1505
1506/* Mux */
1b7fd76a 1507/* DAC1 L/R Source */ /* MX-29 [10:8] */
0e826e86
OC		 1508static const char * const rt5677_dac1_src[] = {
1509 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1510 "OB 01"
1511};
1512
1513static SOC_ENUM_SINGLE_DECL(
1514 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1515 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1516
1517static const struct snd_kcontrol_new rt5677_dac1_mux =
1b7fd76a 1518 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
0e826e86 1519
1b7fd76a 1520/* ADDA1 L/R Source */ /* MX-29 [1:0] */
0e826e86
OC		 1521static const char * const rt5677_adda1_src[] = {
1522 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1523};
1524
1525static SOC_ENUM_SINGLE_DECL(
1526 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1527 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1528
1529static const struct snd_kcontrol_new rt5677_adda1_mux =
1b7fd76a 1530 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
0e826e86
OC		 1531
1532
1b7fd76a 1533/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
0e826e86
OC		 1534static const char * const rt5677_dac2l_src[] = {
1535 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1536 "OB 2",
1537};
1538
1539static SOC_ENUM_SINGLE_DECL(
1540 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1541 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1542
1543static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1b7fd76a 1544 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
0e826e86
OC		 1545
1546static const char * const rt5677_dac2r_src[] = {
1547 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1548 "OB 3", "Haptic Generator", "VAD ADC"
1549};
1550
1551static SOC_ENUM_SINGLE_DECL(
1552 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1553 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1554
1555static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1b7fd76a 1556 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
0e826e86 1557
1b7fd76a 1558/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
0e826e86
OC		 1559static const char * const rt5677_dac3l_src[] = {
1560 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1561 "SLB DAC 4", "OB 4"
1562};
1563
1564static SOC_ENUM_SINGLE_DECL(
1565 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1566 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1567
1568static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1b7fd76a 1569 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
0e826e86
OC		 1570
1571static const char * const rt5677_dac3r_src[] = {
1572 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1573 "SLB DAC 5", "OB 5"
1574};
1575
1576static SOC_ENUM_SINGLE_DECL(
1577 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1578 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1579
1580static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1b7fd76a 1581 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
0e826e86 1582
1b7fd76a 1583/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
0e826e86
OC		 1584static const char * const rt5677_dac4l_src[] = {
1585 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1586 "SLB DAC 6", "OB 6"
1587};
1588
1589static SOC_ENUM_SINGLE_DECL(
1590 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1591 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1592
1593static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1b7fd76a 1594 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
0e826e86
OC		 1595
1596static const char * const rt5677_dac4r_src[] = {
1597 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1598 "SLB DAC 7", "OB 7"
1599};
1600
1601static SOC_ENUM_SINGLE_DECL(
1602 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1603 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1604
1605static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1b7fd76a 1606 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
0e826e86
OC		 1607
1608/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1609static const char * const rt5677_iob_bypass_src[] = {
1610 "Bypass", "Pass SRC"
1611};
1612
1613static SOC_ENUM_SINGLE_DECL(
1614 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1615 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1616
1617static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1b7fd76a 1618 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
0e826e86
OC		 1619
1620static SOC_ENUM_SINGLE_DECL(
1621 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1622 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1623
1624static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1b7fd76a 1625 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
0e826e86
OC		 1626
1627static SOC_ENUM_SINGLE_DECL(
1628 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1629 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1630
1631static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1b7fd76a 1632 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
0e826e86
OC		 1633
1634static SOC_ENUM_SINGLE_DECL(
1635 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1636 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1637
1638static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1b7fd76a 1639 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
0e826e86
OC		 1640
1641static SOC_ENUM_SINGLE_DECL(
1642 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1643 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1644
1645static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1b7fd76a 1646 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
0e826e86 1647
d65fd3a4 1648/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
0e826e86
OC		 1649static const char * const rt5677_stereo_adc2_src[] = {
1650 "DD MIX1", "DMIC", "Stereo DAC MIX"
1651};
1652
1653static SOC_ENUM_SINGLE_DECL(
1654 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1655 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1656
1657static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1b7fd76a 1658 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
0e826e86
OC		 1659
1660static SOC_ENUM_SINGLE_DECL(
1661 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1662 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1663
1664static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1b7fd76a 1665 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
0e826e86
OC		 1666
1667static SOC_ENUM_SINGLE_DECL(
1668 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1669 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1670
1671static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1b7fd76a 1672 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
0e826e86
OC		 1673
1674/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1675static const char * const rt5677_dmic_src[] = {
1676 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1677};
1678
1679static SOC_ENUM_SINGLE_DECL(
1680 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1681 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1682
1683static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1b7fd76a 1684 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
0e826e86
OC		 1685
1686static SOC_ENUM_SINGLE_DECL(
1687 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1688 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1689
1690static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1b7fd76a 1691 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
0e826e86
OC		 1692
1693static SOC_ENUM_SINGLE_DECL(
1694 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1695 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1696
1697static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1b7fd76a 1698 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
0e826e86
OC		 1699
1700static SOC_ENUM_SINGLE_DECL(
1701 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1702 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1703
1704static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1b7fd76a 1705 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
0e826e86
OC		 1706
1707static SOC_ENUM_SINGLE_DECL(
1708 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1709 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1710
1711static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1b7fd76a 1712 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
0e826e86
OC		 1713
1714static SOC_ENUM_SINGLE_DECL(
1715 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1716 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1717
1718static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1b7fd76a 1719 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
0e826e86 1720
1b7fd76a 1721/* Stereo2 ADC Source */ /* MX-26 [0] */
0e826e86
OC		 1722static const char * const rt5677_stereo2_adc_lr_src[] = {
1723 "L", "LR"
1724};
1725
1726static SOC_ENUM_SINGLE_DECL(
1727 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1728 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1729
1730static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1b7fd76a 1731 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
0e826e86 1732
d65fd3a4 1733/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
0e826e86
OC		 1734static const char * const rt5677_stereo_adc1_src[] = {
1735 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1736};
1737
1738static SOC_ENUM_SINGLE_DECL(
1739 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1740 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1741
1742static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1b7fd76a 1743 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
0e826e86
OC		 1744
1745static SOC_ENUM_SINGLE_DECL(
1746 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1747 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1748
1749static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1b7fd76a 1750 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
0e826e86
OC		 1751
1752static SOC_ENUM_SINGLE_DECL(
1753 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1754 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1755
1756static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1b7fd76a 1757 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
0e826e86 1758
1b7fd76a 1759/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
0e826e86
OC		 1760static const char * const rt5677_mono_adc2_l_src[] = {
1761 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1762};
1763
1764static SOC_ENUM_SINGLE_DECL(
1765 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1766 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1767
1768static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1b7fd76a 1769 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
0e826e86 1770
1b7fd76a 1771/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
0e826e86
OC		 1772static const char * const rt5677_mono_adc1_l_src[] = {
1773 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1774};
1775
1776static SOC_ENUM_SINGLE_DECL(
1777 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1778 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1779
1780static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1b7fd76a 1781 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
0e826e86 1782
1b7fd76a 1783/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
0e826e86
OC		 1784static const char * const rt5677_mono_adc2_r_src[] = {
1785 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1786};
1787
1788static SOC_ENUM_SINGLE_DECL(
1789 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1790 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1791
1792static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1b7fd76a 1793 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
0e826e86 1794
1b7fd76a 1795/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
0e826e86
OC		 1796static const char * const rt5677_mono_adc1_r_src[] = {
1797 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1798};
1799
1800static SOC_ENUM_SINGLE_DECL(
1801 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1802 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1803
1804static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1b7fd76a 1805 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
0e826e86
OC		 1806
1807/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1808static const char * const rt5677_stereo4_adc2_src[] = {
1809 "DD MIX1", "DMIC", "DD MIX2"
1810};
1811
1812static SOC_ENUM_SINGLE_DECL(
1813 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1814 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1815
1816static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1b7fd76a 1817 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
0e826e86
OC		 1818
1819
1820/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1821static const char * const rt5677_stereo4_adc1_src[] = {
1822 "DD MIX1", "ADC1/2", "DD MIX2"
1823};
1824
1825static SOC_ENUM_SINGLE_DECL(
1826 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1827 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1828
1829static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1b7fd76a 1830 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
0e826e86
OC		 1831
1832/* InBound0/1 Source */ /* MX-A3 [14:12] */
1833static const char * const rt5677_inbound01_src[] = {
1834 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1835 "VAD ADC/DAC1 FS"
1836};
1837
1838static SOC_ENUM_SINGLE_DECL(
1839 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1840 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1841
1842static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1843 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1844
1845/* InBound2/3 Source */ /* MX-A3 [10:8] */
1846static const char * const rt5677_inbound23_src[] = {
1847 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1848 "DAC1 FS", "IF4 DAC"
1849};
1850
1851static SOC_ENUM_SINGLE_DECL(
1852 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1853 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1854
1855static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1856 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1857
1858/* InBound4/5 Source */ /* MX-A3 [6:4] */
1859static const char * const rt5677_inbound45_src[] = {
1860 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1861 "IF3 DAC"
1862};
1863
1864static SOC_ENUM_SINGLE_DECL(
1865 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1866 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1867
1868static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1869 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1870
1871/* InBound6 Source */ /* MX-A3 [2:0] */
1872static const char * const rt5677_inbound6_src[] = {
1873 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1874 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1875};
1876
1877static SOC_ENUM_SINGLE_DECL(
1878 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1879 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1880
1881static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1882 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1883
1884/* InBound7 Source */ /* MX-A4 [14:12] */
1885static const char * const rt5677_inbound7_src[] = {
1886 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1887 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1888};
1889
1890static SOC_ENUM_SINGLE_DECL(
1891 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1892 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1893
1894static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1895 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1896
1897/* InBound8 Source */ /* MX-A4 [10:8] */
1898static const char * const rt5677_inbound8_src[] = {
1899 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1900 "MONO ADC MIX L", "DACL1 FS"
1901};
1902
1903static SOC_ENUM_SINGLE_DECL(
1904 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1905 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1906
1907static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1908 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1909
1910/* InBound9 Source */ /* MX-A4 [6:4] */
1911static const char * const rt5677_inbound9_src[] = {
1912 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1913 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1914};
1915
1916static SOC_ENUM_SINGLE_DECL(
1917 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1918 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1919
1920static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1921 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1922
1923/* VAD Source */ /* MX-9F [6:4] */
1924static const char * const rt5677_vad_src[] = {
1925 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1926 "STO3 ADC MIX L"
1927};
1928
1929static SOC_ENUM_SINGLE_DECL(
1930 rt5677_vad_enum, RT5677_VAD_CTRL4,
1931 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1932
1933static const struct snd_kcontrol_new rt5677_vad_src_mux =
1934 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1935
1936/* Sidetone Source */ /* MX-13 [11:9] */
1937static const char * const rt5677_sidetone_src[] = {
1938 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1939};
1940
1941static SOC_ENUM_SINGLE_DECL(
1942 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1943 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1944
1945static const struct snd_kcontrol_new rt5677_sidetone_mux =
1946 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1947
1948/* DAC1/2 Source */ /* MX-15 [1:0] */
1949static const char * const rt5677_dac12_src[] = {
1950 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1951};
1952
1953static SOC_ENUM_SINGLE_DECL(
1954 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1955 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1956
1957static const struct snd_kcontrol_new rt5677_dac12_mux =
1958 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1959
1960/* DAC3 Source */ /* MX-15 [5:4] */
1961static const char * const rt5677_dac3_src[] = {
1962 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1963};
1964
1965static SOC_ENUM_SINGLE_DECL(
1966 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1967 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1968
1969static const struct snd_kcontrol_new rt5677_dac3_mux =
1970 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1971
1b7fd76a 1972/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
0e826e86
OC		 1973static const char * const rt5677_pdm_src[] = {
1974 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1975};
1976
1977static SOC_ENUM_SINGLE_DECL(
1978 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1979 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1980
1981static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1b7fd76a 1982 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
0e826e86
OC		 1983
1984static SOC_ENUM_SINGLE_DECL(
1985 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1986 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1987
1988static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1b7fd76a 1989 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
0e826e86
OC		 1990
1991static SOC_ENUM_SINGLE_DECL(
1992 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1993 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1994
1995static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1b7fd76a 1996 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
0e826e86
OC		 1997
1998static SOC_ENUM_SINGLE_DECL(
1999 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2000 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2001
2002static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1b7fd76a 2003 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
0e826e86 2004
d65fd3a4 2005/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
0e826e86
OC		 2006static const char * const rt5677_if12_adc1_src[] = {
2007 "STO1 ADC MIX", "OB01", "VAD ADC"
2008};
2009
2010static SOC_ENUM_SINGLE_DECL(
2011 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2012 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2013
2014static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1b7fd76a 2015 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
0e826e86
OC		 2016
2017static SOC_ENUM_SINGLE_DECL(
2018 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2019 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2020
2021static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1b7fd76a 2022 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
0e826e86
OC		 2023
2024static SOC_ENUM_SINGLE_DECL(
2025 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2026 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2027
2028static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1b7fd76a 2029 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
0e826e86
OC		 2030
2031/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2032static const char * const rt5677_if12_adc2_src[] = {
2033 "STO2 ADC MIX", "OB23"
2034};
2035
2036static SOC_ENUM_SINGLE_DECL(
2037 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2038 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2039
2040static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1b7fd76a 2041 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
0e826e86
OC		 2042
2043static SOC_ENUM_SINGLE_DECL(
2044 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2045 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2046
2047static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1b7fd76a 2048 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
0e826e86
OC		 2049
2050static SOC_ENUM_SINGLE_DECL(
2051 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2052 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2053
2054static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1b7fd76a 2055 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
0e826e86
OC		 2056
2057/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2058static const char * const rt5677_if12_adc3_src[] = {
2059 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2060};
2061
2062static SOC_ENUM_SINGLE_DECL(
2063 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2064 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2065
2066static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1b7fd76a 2067 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
0e826e86
OC		 2068
2069static SOC_ENUM_SINGLE_DECL(
2070 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2071 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2072
2073static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1b7fd76a 2074 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
0e826e86
OC		 2075
2076static SOC_ENUM_SINGLE_DECL(
2077 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2078 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2079
2080static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1b7fd76a 2081 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
0e826e86 2082
d65fd3a4 2083/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
0e826e86
OC		 2084static const char * const rt5677_if12_adc4_src[] = {
2085 "STO4 ADC MIX", "OB67", "OB01"
2086};
2087
2088static SOC_ENUM_SINGLE_DECL(
2089 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2090 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2091
2092static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1b7fd76a 2093 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
0e826e86
OC		 2094
2095static SOC_ENUM_SINGLE_DECL(
2096 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2097 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2098
2099static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1b7fd76a 2100 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
0e826e86
OC		 2101
2102static SOC_ENUM_SINGLE_DECL(
2103 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2104 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2105
2106static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1b7fd76a 2107 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
0e826e86 2108
d65fd3a4 2109/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
0e826e86
OC		 2110static const char * const rt5677_if34_adc_src[] = {
2111 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2112 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2113};
2114
2115static SOC_ENUM_SINGLE_DECL(
2116 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2117 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2118
2119static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1b7fd76a 2120 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
0e826e86
OC		 2121
2122static SOC_ENUM_SINGLE_DECL(
2123 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2124 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2125
2126static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1b7fd76a 2127 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
0e826e86 2128
e6f6ebc1
OC		 2129/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2130static const char * const rt5677_if12_adc_swap_src[] = {
2131 "L/R", "R/L", "L/L", "R/R"
2132};
2133
2134static SOC_ENUM_SINGLE_DECL(
2135 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2136 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2137
2138static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2139 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2140
2141static SOC_ENUM_SINGLE_DECL(
2142 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2143 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2144
2145static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2146 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2147
2148static SOC_ENUM_SINGLE_DECL(
2149 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2150 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2151
2152static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2153 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2154
2155static SOC_ENUM_SINGLE_DECL(
2156 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2157 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2158
2159static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2160 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2161
2162static SOC_ENUM_SINGLE_DECL(
2163 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2164 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2165
2166static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2167 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2168
2169static SOC_ENUM_SINGLE_DECL(
2170 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2171 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2172
2173static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2174 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2175
2176static SOC_ENUM_SINGLE_DECL(
2177 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2178 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2179
2180static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2181 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2182
2183static SOC_ENUM_SINGLE_DECL(
2184 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2185 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2186
2187static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2188 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2189
d65fd3a4 2190/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
e6f6ebc1
OC		 2191static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2192 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2193 "3/1/2/4", "3/4/1/2"
2194};
2195
2196static SOC_ENUM_SINGLE_DECL(
2197 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2198 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2199
2200static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2201 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2202
2203/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2204static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2205 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2206 "2/3/1/4", "3/4/1/2"
2207};
2208
2209static SOC_ENUM_SINGLE_DECL(
2210 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2211 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2212
2213static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2214 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2215
91159eca
OC		 2216/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2217 MX-3F[14:12][10:8][6:4][2:0]
2218 MX-43[14:12][10:8][6:4][2:0]
2219 MX-44[14:12][10:8][6:4][2:0] */
2220static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2221 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2222};
2223
2224static SOC_ENUM_SINGLE_DECL(
2225 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2226 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2227
2228static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2229 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2230
2231static SOC_ENUM_SINGLE_DECL(
2232 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2233 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2234
2235static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2236 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2237
2238static SOC_ENUM_SINGLE_DECL(
2239 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2240 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2241
2242static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2243 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2244
2245static SOC_ENUM_SINGLE_DECL(
2246 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2247 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2248
2249static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2250 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2251
2252static SOC_ENUM_SINGLE_DECL(
2253 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2254 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2255
2256static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2257 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2258
2259static SOC_ENUM_SINGLE_DECL(
2260 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2261 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2262
2263static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2264 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2265
2266static SOC_ENUM_SINGLE_DECL(
2267 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2268 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2269
2270static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2271 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2272
2273static SOC_ENUM_SINGLE_DECL(
2274 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2275 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2276
2277static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2278 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2279
2280static SOC_ENUM_SINGLE_DECL(
2281 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2282 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2283
2284static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2285 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2286
2287static SOC_ENUM_SINGLE_DECL(
2288 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2289 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2290
2291static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2292 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2293
2294static SOC_ENUM_SINGLE_DECL(
2295 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2296 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2297
2298static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2299 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2300
2301static SOC_ENUM_SINGLE_DECL(
2302 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2303 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2304
2305static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2306 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2307
2308static SOC_ENUM_SINGLE_DECL(
2309 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2310 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2311
2312static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2313 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2314
2315static SOC_ENUM_SINGLE_DECL(
2316 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2317 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2318
2319static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2320 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2321
2322static SOC_ENUM_SINGLE_DECL(
2323 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2324 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2325
2326static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2327 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2328
2329static SOC_ENUM_SINGLE_DECL(
2330 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2331 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2332
2333static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2334 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2335
0e826e86
OC		 2336static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2337 struct snd_kcontrol *kcontrol, int event)
2338{
46f20872 2339 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2340 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2341
2342 switch (event) {
2343 case SND_SOC_DAPM_POST_PMU:
2344 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2345 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2346 break;
2347
2348 case SND_SOC_DAPM_PRE_PMD:
2349 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2350 RT5677_PWR_BST1_P, 0);
2351 break;
2352
2353 default:
2354 return 0;
2355 }
2356
2357 return 0;
2358}
2359
2360static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2361 struct snd_kcontrol *kcontrol, int event)
2362{
46f20872 2363 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2364 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2365
2366 switch (event) {
2367 case SND_SOC_DAPM_POST_PMU:
2368 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2369 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2370 break;
2371
2372 case SND_SOC_DAPM_PRE_PMD:
2373 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2374 RT5677_PWR_BST2_P, 0);
2375 break;
2376
2377 default:
2378 return 0;
2379 }
2380
2381 return 0;
2382}
2383
2384static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2385 struct snd_kcontrol *kcontrol, int event)
2386{
46f20872 2387 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2388 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2389
2390 switch (event) {
bdfbf255 2391 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2392 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2393 break;
2394
2395 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2396 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2397 break;
bdfbf255 2398
0e826e86
OC		 2399 default:
2400 return 0;
2401 }
2402
2403 return 0;
2404}
2405
2406static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2407 struct snd_kcontrol *kcontrol, int event)
2408{
46f20872 2409 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2410 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2411
2412 switch (event) {
bdfbf255 2413 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2414 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2415 break;
2416
2417 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2418 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2419 break;
bdfbf255 2420
0e826e86
OC		 2421 default:
2422 return 0;
2423 }
2424
2425 return 0;
2426}
2427
2428static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2429 struct snd_kcontrol *kcontrol, int event)
2430{
46f20872 2431 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2432 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2433
2434 switch (event) {
2435 case SND_SOC_DAPM_POST_PMU:
2436 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2437 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2438 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2439 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2440 break;
f58c3b91
OC		 2441
2442 case SND_SOC_DAPM_PRE_PMD:
2443 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2444 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2445 RT5677_PWR_CLK_MB, 0);
2446 break;
2447
0e826e86
OC		 2448 default:
2449 return 0;
2450 }
2451
2452 return 0;
2453}
2454
e6f6ebc1
OC		 2455static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2456 struct snd_kcontrol *kcontrol, int event)
2457{
46f20872 2458 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e6f6ebc1
OC		 2459 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2460 unsigned int value;
2461
2462 switch (event) {
2463 case SND_SOC_DAPM_PRE_PMU:
2464 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2465 if (value & RT5677_IF1_ADC_CTRL_MASK)
2466 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2467 RT5677_IF1_ADC_MODE_MASK,
2468 RT5677_IF1_ADC_MODE_TDM);
2469 break;
2470
2471 default:
2472 return 0;
2473 }
2474
2475 return 0;
2476}
2477
2478static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2479 struct snd_kcontrol *kcontrol, int event)
2480{
46f20872 2481 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e6f6ebc1
OC		 2482 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2483 unsigned int value;
2484
2485 switch (event) {
2486 case SND_SOC_DAPM_PRE_PMU:
2487 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2488 if (value & RT5677_IF2_ADC_CTRL_MASK)
2489 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2490 RT5677_IF2_ADC_MODE_MASK,
2491 RT5677_IF2_ADC_MODE_TDM);
2492 break;
2493
2494 default:
2495 return 0;
2496 }
2497
2498 return 0;
2499}
2500
683996cb
OC		 2501static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2502 struct snd_kcontrol *kcontrol, int event)
2503{
46f20872 2504 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
683996cb
OC		 2505 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2506
2507 switch (event) {
2508 case SND_SOC_DAPM_POST_PMU:
2509 if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2510 !rt5677->is_vref_slow) {
2511 mdelay(20);
2512 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2513 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2514 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2515 rt5677->is_vref_slow = true;
2516 }
2517 break;
2518
2519 default:
2520 return 0;
2521 }
2522
2523 return 0;
2524}
2525
0e826e86
OC		 2526static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2527 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
bdfbf255
OC		 2528 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2529 SND_SOC_DAPM_POST_PMU),
0e826e86 2530 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
bdfbf255
OC		 2531 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2532 SND_SOC_DAPM_POST_PMU),
0e826e86 2533
5a8c7c26
OC		 2534 /* ASRC */
2535 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2536 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2537 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2538 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2539 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2540 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2541 0),
2542 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2543 0),
2544 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2545 0),
2546 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2547 0),
2548 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2549 0),
2550 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2551 0),
2552 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2553 0),
2554 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2555 0),
2556 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2557 0),
2558 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2559 0),
2560 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2561 0),
2562 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2563 0),
2564 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2565 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2566 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2567 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2568 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2569 0),
2570 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2571 0),
2572
0e826e86
OC		 2573 /* Input Side */
2574 /* micbias */
3d0c03d9 2575 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
f58c3b91
OC		 2576 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2577 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 2578
2579 /* Input Lines */
2580 SND_SOC_DAPM_INPUT("DMIC L1"),
2581 SND_SOC_DAPM_INPUT("DMIC R1"),
2582 SND_SOC_DAPM_INPUT("DMIC L2"),
2583 SND_SOC_DAPM_INPUT("DMIC R2"),
2584 SND_SOC_DAPM_INPUT("DMIC L3"),
2585 SND_SOC_DAPM_INPUT("DMIC R3"),
2586 SND_SOC_DAPM_INPUT("DMIC L4"),
2587 SND_SOC_DAPM_INPUT("DMIC R4"),
2588
2589 SND_SOC_DAPM_INPUT("IN1P"),
2590 SND_SOC_DAPM_INPUT("IN1N"),
2591 SND_SOC_DAPM_INPUT("IN2P"),
2592 SND_SOC_DAPM_INPUT("IN2N"),
2593
2594 SND_SOC_DAPM_INPUT("Haptic Generator"),
2595
2d15d974
BL		 2596 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2597 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2598 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2599 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2600
2601 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2602 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2603 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2604 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2605 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2606 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2607 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2608 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
0e826e86
OC		 2609
2610 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2611 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2612
2613 /* Boost */
2614 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2615 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2616 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2617 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2618 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2619 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2620
2621 /* ADCs */
2622 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2623 0, 0),
2624 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2625 0, 0),
2626 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2627
2628 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2629 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2630 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2631 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2632 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2633 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2634 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2635 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2636
2637 /* ADC Mux */
2638 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2639 &rt5677_sto1_dmic_mux),
2640 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2641 &rt5677_sto1_adc1_mux),
2642 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2643 &rt5677_sto1_adc2_mux),
2644 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2645 &rt5677_sto2_dmic_mux),
2646 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2647 &rt5677_sto2_adc1_mux),
2648 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2649 &rt5677_sto2_adc2_mux),
2650 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2651 &rt5677_sto2_adc_lr_mux),
2652 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2653 &rt5677_sto3_dmic_mux),
2654 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2655 &rt5677_sto3_adc1_mux),
2656 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2657 &rt5677_sto3_adc2_mux),
2658 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2659 &rt5677_sto4_dmic_mux),
2660 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2661 &rt5677_sto4_adc1_mux),
2662 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2663 &rt5677_sto4_adc2_mux),
2664 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2665 &rt5677_mono_dmic_l_mux),
2666 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2667 &rt5677_mono_dmic_r_mux),
2668 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2669 &rt5677_mono_adc2_l_mux),
2670 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2671 &rt5677_mono_adc1_l_mux),
2672 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2673 &rt5677_mono_adc1_r_mux),
2674 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2675 &rt5677_mono_adc2_r_mux),
2676
2677 /* ADC Mixer */
2678 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2679 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2680 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2681 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2682 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2683 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2684 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2685 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2686 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2687 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2688 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2689 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2690 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2691 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2692 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2693 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2694 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2695 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2696 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2697 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2698 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2699 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2700 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2701 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2702 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2703 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2704 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2705 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2706 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2707 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2708 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2709 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2710
2711 /* ADC PGA */
2712 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2713 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2714 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2715 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2716 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2717 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2718 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2719 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2720 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2721 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2722 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2723 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2724 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2725 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
e6f6ebc1
OC		 2726 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2727 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
0e826e86
OC		 2728
2729 /* DSP */
2730 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2731 &rt5677_ib9_src_mux),
2732 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2733 &rt5677_ib8_src_mux),
2734 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2735 &rt5677_ib7_src_mux),
2736 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2737 &rt5677_ib6_src_mux),
2738 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2739 &rt5677_ib45_src_mux),
2740 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2741 &rt5677_ib23_src_mux),
2742 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2743 &rt5677_ib01_src_mux),
2744 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2745 &rt5677_ib45_bypass_src_mux),
2746 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2747 &rt5677_ib23_bypass_src_mux),
2748 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2749 &rt5677_ib01_bypass_src_mux),
2750 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2751 &rt5677_ob23_bypass_src_mux),
2752 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2753 &rt5677_ob01_bypass_src_mux),
2754
2755 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2756 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2757
2758 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2759 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2760 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2761 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2762 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2763 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2764
2765 /* Digital Interface */
2766 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2767 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2768 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2769 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2770 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2771 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2772 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2773 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2774 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2775 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2776 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2777 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2778 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2779 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2780 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2781 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2782 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2783 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2784
2785 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2786 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2787 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2788 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2791 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2792 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2793 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2797 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2800 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2801 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2802 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2803
2804 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2805 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2806 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2807 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2808 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2809 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2810 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2811 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2812
2813 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2814 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2815 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2816 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2817 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2818 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2819 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2820 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2821
2822 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2823 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2824 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2825 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2826 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2827 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2828 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2829 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2830 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2831 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2832 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2833 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2834 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2835 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2836 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2837 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2838 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2839 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2840
2841 /* Digital Interface Select */
2842 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2843 &rt5677_if1_adc1_mux),
2844 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2845 &rt5677_if1_adc2_mux),
2846 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2847 &rt5677_if1_adc3_mux),
2848 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2849 &rt5677_if1_adc4_mux),
e6f6ebc1
OC		 2850 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2851 &rt5677_if1_adc1_swap_mux),
2852 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2853 &rt5677_if1_adc2_swap_mux),
2854 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2855 &rt5677_if1_adc3_swap_mux),
2856 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2857 &rt5677_if1_adc4_swap_mux),
2858 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2859 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2860 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2861 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2862 &rt5677_if2_adc1_mux),
2863 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2864 &rt5677_if2_adc2_mux),
2865 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2866 &rt5677_if2_adc3_mux),
2867 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2868 &rt5677_if2_adc4_mux),
e6f6ebc1
OC		 2869 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2870 &rt5677_if2_adc1_swap_mux),
2871 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2872 &rt5677_if2_adc2_swap_mux),
2873 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2874 &rt5677_if2_adc3_swap_mux),
2875 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2876 &rt5677_if2_adc4_swap_mux),
2877 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2878 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2879 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2880 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2881 &rt5677_if3_adc_mux),
2882 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2883 &rt5677_if4_adc_mux),
2884 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2885 &rt5677_slb_adc1_mux),
2886 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2887 &rt5677_slb_adc2_mux),
2888 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2889 &rt5677_slb_adc3_mux),
2890 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2891 &rt5677_slb_adc4_mux),
2892
91159eca
OC		 2893 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2894 &rt5677_if1_dac0_tdm_sel_mux),
2895 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2896 &rt5677_if1_dac1_tdm_sel_mux),
2897 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2898 &rt5677_if1_dac2_tdm_sel_mux),
2899 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2900 &rt5677_if1_dac3_tdm_sel_mux),
2901 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2902 &rt5677_if1_dac4_tdm_sel_mux),
2903 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2904 &rt5677_if1_dac5_tdm_sel_mux),
2905 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2906 &rt5677_if1_dac6_tdm_sel_mux),
2907 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2908 &rt5677_if1_dac7_tdm_sel_mux),
2909
2910 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2911 &rt5677_if2_dac0_tdm_sel_mux),
2912 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2913 &rt5677_if2_dac1_tdm_sel_mux),
2914 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2915 &rt5677_if2_dac2_tdm_sel_mux),
2916 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5677_if2_dac3_tdm_sel_mux),
2918 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5677_if2_dac4_tdm_sel_mux),
2920 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5677_if2_dac5_tdm_sel_mux),
2922 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5677_if2_dac6_tdm_sel_mux),
2924 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5677_if2_dac7_tdm_sel_mux),
2926
0e826e86
OC		 2927 /* Audio Interface */
2928 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2929 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2930 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2931 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2932 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2933 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2934 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2935 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2936 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2937 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2938
2939 /* Sidetone Mux */
2940 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5677_sidetone_mux),
90bdbb46
OC		 2942 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2943 RT5677_ST_EN_SFT, 0, NULL, 0),
2944
0e826e86
OC		 2945 /* VAD Mux*/
2946 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5677_vad_src_mux),
2948
2949 /* Tensilica DSP */
2950 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2951 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2952 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2953 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2954 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2955 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2956 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2957 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2958 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2959 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2960 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2961 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2962 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2963
2964 /* Output Side */
d65fd3a4 2965 /* DAC mixer before sound effect */
0e826e86
OC		 2966 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2967 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2968 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2969 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2970 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2971
2972 /* DAC Mux */
2973 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5677_dac1_mux),
2975 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5677_adda1_mux),
2977 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2978 &rt5677_dac12_mux),
2979 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5677_dac3_mux),
2981
2982 /* DAC2 channel Mux */
2983 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5677_dac2_l_mux),
2985 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5677_dac2_r_mux),
2987
2988 /* DAC3 channel Mux */
2989 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5677_dac3_l_mux),
2991 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5677_dac3_r_mux),
2993
2994 /* DAC4 channel Mux */
2995 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5677_dac4_l_mux),
2997 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2998 &rt5677_dac4_r_mux),
2999
3000 /* DAC Mixer */
3001 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3002 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
6800b5ba 3003 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
0e826e86 3004 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
6800b5ba 3005 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
0e826e86 3006 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
6800b5ba
OC		 3007 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3008 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
3009 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3010 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
3011 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3012 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
3013 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3014 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
0e826e86
OC		 3015
3016 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3017 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3018 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3019 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3020 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3021 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3022 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3023 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3024 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3025 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3026 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3027 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3028 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3029 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3030 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3031 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3032 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3033 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3034 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3035 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3036
3037 /* DACs */
3038 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3039 RT5677_PWR_DAC1_BIT, 0),
3040 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3041 RT5677_PWR_DAC2_BIT, 0),
3042 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3043 RT5677_PWR_DAC3_BIT, 0),
3044
3045 /* PDM */
3046 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3047 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3048 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3049 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3050
3051 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3052 1, &rt5677_pdm1_l_mux),
3053 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3054 1, &rt5677_pdm1_r_mux),
3055 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3056 1, &rt5677_pdm2_l_mux),
3057 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3058 1, &rt5677_pdm2_r_mux),
3059
683996cb 3060 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
0e826e86 3061 0, NULL, 0),
683996cb 3062 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
0e826e86 3063 0, NULL, 0),
683996cb 3064 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
0e826e86
OC		 3065 0, NULL, 0),
3066
683996cb
OC		 3067 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3068 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3069 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3070 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3071 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3072 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3073
0e826e86
OC		 3074 /* Output Lines */
3075 SND_SOC_DAPM_OUTPUT("LOUT1"),
3076 SND_SOC_DAPM_OUTPUT("LOUT2"),
3077 SND_SOC_DAPM_OUTPUT("LOUT3"),
3078 SND_SOC_DAPM_OUTPUT("PDM1L"),
3079 SND_SOC_DAPM_OUTPUT("PDM1R"),
3080 SND_SOC_DAPM_OUTPUT("PDM2L"),
3081 SND_SOC_DAPM_OUTPUT("PDM2R"),
683996cb
OC		 3082
3083 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
0e826e86
OC		 3084};
3085
3086static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
5a8c7c26
OC		 3087 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
3088 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
3089 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", can_use_asrc },
3090 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", can_use_asrc },
3091 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
3092 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
3093 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3094 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3095 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3096 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3097
3098 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3099 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3100 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3101 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3102 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3103 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3104 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3105 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3106 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3107 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3108 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3109 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3110 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3111
0e826e86
OC		 3112 { "DMIC1", NULL, "DMIC L1" },
3113 { "DMIC1", NULL, "DMIC R1" },
3114 { "DMIC2", NULL, "DMIC L2" },
3115 { "DMIC2", NULL, "DMIC R2" },
3116 { "DMIC3", NULL, "DMIC L3" },
3117 { "DMIC3", NULL, "DMIC R3" },
3118 { "DMIC4", NULL, "DMIC L4" },
3119 { "DMIC4", NULL, "DMIC R4" },
3120
3121 { "DMIC L1", NULL, "DMIC CLK" },
3122 { "DMIC R1", NULL, "DMIC CLK" },
3123 { "DMIC L2", NULL, "DMIC CLK" },
3124 { "DMIC R2", NULL, "DMIC CLK" },
3125 { "DMIC L3", NULL, "DMIC CLK" },
3126 { "DMIC R3", NULL, "DMIC CLK" },
3127 { "DMIC L4", NULL, "DMIC CLK" },
3128 { "DMIC R4", NULL, "DMIC CLK" },
3129
2d15d974
BL		 3130 { "DMIC L1", NULL, "DMIC1 power" },
3131 { "DMIC R1", NULL, "DMIC1 power" },
3132 { "DMIC L3", NULL, "DMIC3 power" },
3133 { "DMIC R3", NULL, "DMIC3 power" },
3134 { "DMIC L4", NULL, "DMIC4 power" },
3135 { "DMIC R4", NULL, "DMIC4 power" },
3136
0e826e86
OC		 3137 { "BST1", NULL, "IN1P" },
3138 { "BST1", NULL, "IN1N" },
3139 { "BST2", NULL, "IN2P" },
3140 { "BST2", NULL, "IN2N" },
3141
22e51345
BL		 3142 { "IN1P", NULL, "MICBIAS1" },
3143 { "IN1N", NULL, "MICBIAS1" },
3144 { "IN2P", NULL, "MICBIAS1" },
3145 { "IN2N", NULL, "MICBIAS1" },
0e826e86
OC		 3146
3147 { "ADC 1", NULL, "BST1" },
3148 { "ADC 1", NULL, "ADC 1 power" },
3149 { "ADC 1", NULL, "ADC1 clock" },
3150 { "ADC 2", NULL, "BST2" },
3151 { "ADC 2", NULL, "ADC 2 power" },
3152 { "ADC 2", NULL, "ADC2 clock" },
3153
3154 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3155 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3156 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3157 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3158
3159 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3160 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3161 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3162 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3163
3164 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3165 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3166 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3167 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3168
3169 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3170 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3171 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3172 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3173
3174 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3175 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3176 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3177 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3178
3179 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3180 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3181 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3182 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3183
3184 { "ADC 1_2", NULL, "ADC 1" },
3185 { "ADC 1_2", NULL, "ADC 2" },
3186
3187 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3188 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3189 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3190
3191 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3192 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3193 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3194
3195 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3196 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3197 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3198
3199 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3200 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3201 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3202
3203 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3204 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3205 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3206
3207 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3208 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3209 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3210
3211 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3212 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3213 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3214
3215 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3216 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3217 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3218
3219 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3220 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3221 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3222
3223 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3224 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3225 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3226
3227 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3228 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3229 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3230
3231 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3232 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3233 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3234
3235 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3236 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3237 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3238 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3239
3240 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3241 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
0e826e86
OC		 3242 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3243 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3244 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3245
3246 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3247 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3248
3249 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3250 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3251 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3252 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3253
3254 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3255 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3256
3257 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3258 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3259
3260 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3261 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
0e826e86
OC		 3262 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3263 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3264 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3265
3266 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3267 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3268
3269 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3270 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3271 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3272 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3273
3274 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3275 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
0e826e86
OC		 3276 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3277 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3278 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3279
3280 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3281 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3282
3283 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3284 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3285 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3286 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3287
3288 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3289 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
0e826e86
OC		 3290 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3291 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3292 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3293
3294 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3295 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3296
3297 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3298 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3299 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3300 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3301
3302 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3303 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3304 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3305 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3306
3307 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3308 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3309
3310 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3311 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3312 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3313 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3314 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3315
3316 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3317 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3318 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3319
3320 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3321 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3322
3323 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3324 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3325 { "IF1 ADC3 Mux", "OB45", "OB45" },
3326
3327 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3328 { "IF1 ADC4 Mux", "OB67", "OB67" },
3329 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3330
e6f6ebc1
OC		 3331 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3332 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3333 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3334 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3335
3336 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3337 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3338 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3339 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3340
3341 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3342 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3343 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3344 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3345
3346 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3347 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3348 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3349 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3350
3351 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3352 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3353 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3354 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3355
3356 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3357 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3358 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3359 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3360 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3361 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3362 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3363 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3364
0e826e86 3365 { "AIF1TX", NULL, "I2S1" },
e6f6ebc1 3366 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
0e826e86
OC		 3367
3368 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3369 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3370 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3371
3372 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3373 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3374
3375 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3376 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3377 { "IF2 ADC3 Mux", "OB45", "OB45" },
3378
3379 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3380 { "IF2 ADC4 Mux", "OB67", "OB67" },
3381 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3382
e6f6ebc1
OC		 3383 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3384 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3385 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3386 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3387
3388 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3389 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3390 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3391 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3392
3393 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3394 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3395 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3396 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3397
3398 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3399 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3400 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3401 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3402
3403 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3404 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3405 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3406 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3407
3408 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3409 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3410 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3411 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3412 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3413 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3414 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3415 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3416
0e826e86 3417 { "AIF2TX", NULL, "I2S2" },
e6f6ebc1 3418 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
0e826e86
OC		 3419
3420 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3421 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3422 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3423 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3424 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3425 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3426 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3427 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3428
3429 { "AIF3TX", NULL, "I2S3" },
3430 { "AIF3TX", NULL, "IF3 ADC Mux" },
3431
3432 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3433 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3434 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3435 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3436 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3437 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3438 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3439 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3440
3441 { "AIF4TX", NULL, "I2S4" },
3442 { "AIF4TX", NULL, "IF4 ADC Mux" },
3443
3444 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3445 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3446 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3447
3448 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3449 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3450
3451 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3452 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3453 { "SLB ADC3 Mux", "OB45", "OB45" },
3454
3455 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3456 { "SLB ADC4 Mux", "OB67", "OB67" },
3457 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3458
3459 { "SLBTX", NULL, "SLB" },
3460 { "SLBTX", NULL, "SLB ADC1 Mux" },
3461 { "SLBTX", NULL, "SLB ADC2 Mux" },
3462 { "SLBTX", NULL, "SLB ADC3 Mux" },
3463 { "SLBTX", NULL, "SLB ADC4 Mux" },
3464
3465 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3466 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3467 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3468 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3469 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3470
3471 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3472 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3473
3474 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3475 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3476 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3477 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3478 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3479 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3480
3481 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3482 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3483
3484 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3485 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3486 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3487 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3488 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3489
3490 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3491 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3492
70068776
OC		 3493 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3494 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
0e826e86
OC		 3495 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3496 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3497 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3498 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3499 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3500 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3501
70068776
OC		 3502 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3503 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
0e826e86
OC		 3504 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3505 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3506 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3507 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3508 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3509 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3510
3511 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3512 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3513 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3514 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3515 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3516 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3517
3518 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3519 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3520 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3521 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3522 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3523 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3524 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3525
3526 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3527 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3528 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3529 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3530 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3531 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3532 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3533
3534 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3535 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3536 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3537 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3538 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3539 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3540 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3541
3542 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3543 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3544 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3545 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3546 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3547 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3548 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3549
3550 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3551 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3552 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3553 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3554 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3555 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3556 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3557
3558 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3559 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3560 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3561 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3562 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3563 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3564 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3565
3566 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3567 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3568 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3569 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3570 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3571 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3572 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3573
3574 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3575 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3576 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3577 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3578
3579 { "OutBound2", NULL, "OB23 Bypass Mux" },
3580 { "OutBound3", NULL, "OB23 Bypass Mux" },
3581 { "OutBound4", NULL, "OB4 MIX" },
3582 { "OutBound5", NULL, "OB5 MIX" },
3583 { "OutBound6", NULL, "OB6 MIX" },
3584 { "OutBound7", NULL, "OB7 MIX" },
3585
3586 { "OB45", NULL, "OutBound4" },
3587 { "OB45", NULL, "OutBound5" },
3588 { "OB67", NULL, "OutBound6" },
3589 { "OB67", NULL, "OutBound7" },
3590
3591 { "IF1 DAC0", NULL, "AIF1RX" },
3592 { "IF1 DAC1", NULL, "AIF1RX" },
3593 { "IF1 DAC2", NULL, "AIF1RX" },
3594 { "IF1 DAC3", NULL, "AIF1RX" },
3595 { "IF1 DAC4", NULL, "AIF1RX" },
3596 { "IF1 DAC5", NULL, "AIF1RX" },
3597 { "IF1 DAC6", NULL, "AIF1RX" },
3598 { "IF1 DAC7", NULL, "AIF1RX" },
3599 { "IF1 DAC0", NULL, "I2S1" },
3600 { "IF1 DAC1", NULL, "I2S1" },
3601 { "IF1 DAC2", NULL, "I2S1" },
3602 { "IF1 DAC3", NULL, "I2S1" },
3603 { "IF1 DAC4", NULL, "I2S1" },
3604 { "IF1 DAC5", NULL, "I2S1" },
3605 { "IF1 DAC6", NULL, "I2S1" },
3606 { "IF1 DAC7", NULL, "I2S1" },
3607
91159eca
OC		 3608 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3609 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3610 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3611 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3612 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3613 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3614 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3615 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3616
3617 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3618 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3619 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3620 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3621 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3622 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3623 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3624 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3625
3626 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3627 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3628 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3629 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3630 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3631 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3632 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3633 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3634
3635 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3636 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3637 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3638 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3639 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3640 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3641 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3642 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3643
3644 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3645 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3646 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3647 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3648 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3649 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3650 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3651 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3652
3653 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3654 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3655 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3656 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3657 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3658 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3659 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3660 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3661
3662 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3663 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3664 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3665 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3666 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3667 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3668 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3669 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3670
3671 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3672 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3673 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3674 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3675 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3676 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3677 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3678 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3679
3680 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3681 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3682 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3683 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3684 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3685 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3686 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3687 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
0e826e86
OC		 3688
3689 { "IF2 DAC0", NULL, "AIF2RX" },
3690 { "IF2 DAC1", NULL, "AIF2RX" },
3691 { "IF2 DAC2", NULL, "AIF2RX" },
3692 { "IF2 DAC3", NULL, "AIF2RX" },
3693 { "IF2 DAC4", NULL, "AIF2RX" },
3694 { "IF2 DAC5", NULL, "AIF2RX" },
3695 { "IF2 DAC6", NULL, "AIF2RX" },
3696 { "IF2 DAC7", NULL, "AIF2RX" },
3697 { "IF2 DAC0", NULL, "I2S2" },
3698 { "IF2 DAC1", NULL, "I2S2" },
3699 { "IF2 DAC2", NULL, "I2S2" },
3700 { "IF2 DAC3", NULL, "I2S2" },
3701 { "IF2 DAC4", NULL, "I2S2" },
3702 { "IF2 DAC5", NULL, "I2S2" },
3703 { "IF2 DAC6", NULL, "I2S2" },
3704 { "IF2 DAC7", NULL, "I2S2" },
3705
91159eca
OC		 3706 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3707 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3708 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3709 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3710 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3711 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3712 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3713 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3714
3715 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3716 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3717 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3718 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3719 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3720 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3721 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3722 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3723
3724 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3725 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3726 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3727 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3728 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3729 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3730 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3731 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3732
3733 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3734 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3735 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3736 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3737 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3738 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3739 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3740 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3741
3742 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3743 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3744 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3745 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3746 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3747 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3748 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3749 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3750
3751 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3752 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3753 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3754 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3755 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3756 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3757 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3758 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3759
3760 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3761 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3762 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3763 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3764 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3765 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3766 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3767 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3768
3769 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3770 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3771 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3772 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3773 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3774 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3775 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3776 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3777
3778 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3779 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3780 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3781 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3782 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3783 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3784 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3785 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
0e826e86
OC		 3786
3787 { "IF3 DAC", NULL, "AIF3RX" },
3788 { "IF3 DAC", NULL, "I2S3" },
3789
3790 { "IF4 DAC", NULL, "AIF4RX" },
3791 { "IF4 DAC", NULL, "I2S4" },
3792
3793 { "IF3 DAC L", NULL, "IF3 DAC" },
3794 { "IF3 DAC R", NULL, "IF3 DAC" },
3795
3796 { "IF4 DAC L", NULL, "IF4 DAC" },
3797 { "IF4 DAC R", NULL, "IF4 DAC" },
3798
3799 { "SLB DAC0", NULL, "SLBRX" },
3800 { "SLB DAC1", NULL, "SLBRX" },
3801 { "SLB DAC2", NULL, "SLBRX" },
3802 { "SLB DAC3", NULL, "SLBRX" },
3803 { "SLB DAC4", NULL, "SLBRX" },
3804 { "SLB DAC5", NULL, "SLBRX" },
3805 { "SLB DAC6", NULL, "SLBRX" },
3806 { "SLB DAC7", NULL, "SLBRX" },
3807 { "SLB DAC0", NULL, "SLB" },
3808 { "SLB DAC1", NULL, "SLB" },
3809 { "SLB DAC2", NULL, "SLB" },
3810 { "SLB DAC3", NULL, "SLB" },
3811 { "SLB DAC4", NULL, "SLB" },
3812 { "SLB DAC5", NULL, "SLB" },
3813 { "SLB DAC6", NULL, "SLB" },
3814 { "SLB DAC7", NULL, "SLB" },
3815
3816 { "SLB DAC01", NULL, "SLB DAC0" },
3817 { "SLB DAC01", NULL, "SLB DAC1" },
3818 { "SLB DAC23", NULL, "SLB DAC2" },
3819 { "SLB DAC23", NULL, "SLB DAC3" },
3820 { "SLB DAC45", NULL, "SLB DAC4" },
3821 { "SLB DAC45", NULL, "SLB DAC5" },
3822 { "SLB DAC67", NULL, "SLB DAC6" },
3823 { "SLB DAC67", NULL, "SLB DAC7" },
3824
3825 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3826 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3827 { "ADDA1 Mux", "OB 67", "OB67" },
3828
3829 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3830 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3831 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3832 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3833 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3834 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3835
3836 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3837 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3838 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3839 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3840
3841 { "DAC1 FS", NULL, "DAC1 MIXL" },
3842 { "DAC1 FS", NULL, "DAC1 MIXR" },
3843
70068776
OC		 3844 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3845 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
0e826e86
OC		 3846 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3847 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3848 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3849 { "DAC2 L Mux", "OB 2", "OutBound2" },
3850
70068776
OC		 3851 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3852 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
0e826e86
OC		 3853 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3854 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3855 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3856 { "DAC2 R Mux", "OB 3", "OutBound3" },
3857 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3858 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3859
70068776
OC		 3860 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3861 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
0e826e86
OC		 3862 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3863 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3864 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3865 { "DAC3 L Mux", "OB 4", "OutBound4" },
3866
70068776
OC		 3867 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3868 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
0e826e86
OC		 3869 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3870 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3871 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3872 { "DAC3 R Mux", "OB 5", "OutBound5" },
3873
70068776
OC		 3874 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3875 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
0e826e86
OC		 3876 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3877 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3878 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3879 { "DAC4 L Mux", "OB 6", "OutBound6" },
3880
70068776
OC		 3881 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3882 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
0e826e86
OC		 3883 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3884 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3885 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3886 { "DAC4 R Mux", "OB 7", "OutBound7" },
3887
3888 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3889 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3890 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3891 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3892 { "Sidetone Mux", "ADC1", "ADC 1" },
3893 { "Sidetone Mux", "ADC2", "ADC 2" },
90bdbb46 3894 { "Sidetone Mux", NULL, "Sidetone Power" },
0e826e86
OC		 3895
3896 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3897 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3898 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3899 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3900 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3901 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3902 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3903 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3904 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3905 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
38d595e2 3906 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3907
3908 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3909 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3910 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3911 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
6800b5ba 3912 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
38d595e2 3913 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3914 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3915 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3916 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3917 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
6800b5ba 3918 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
38d595e2 3919 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3920
3921 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3922 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3923 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3924 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 3925 { "DD1 MIXL", NULL, "dac mono3 left filter" },
38d595e2 3926 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3927 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3928 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3929 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3930 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 3931 { "DD1 MIXR", NULL, "dac mono3 right filter" },
38d595e2 3932 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3933
3934 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3935 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3936 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3937 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 3938 { "DD2 MIXL", NULL, "dac mono4 left filter" },
38d595e2 3939 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3940 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3941 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3942 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3943 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 3944 { "DD2 MIXR", NULL, "dac mono4 right filter" },
38d595e2 3945 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3946
3947 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3948 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3949 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3950 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3951 { "DD1 MIX", NULL, "DD1 MIXL" },
3952 { "DD1 MIX", NULL, "DD1 MIXR" },
3953 { "DD2 MIX", NULL, "DD2 MIXL" },
3954 { "DD2 MIX", NULL, "DD2 MIXR" },
3955
3956 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3957 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3958 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3959 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3960
3961 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3962 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3963 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3964 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3965
3966 { "DAC 1", NULL, "DAC12 SRC Mux" },
0e826e86 3967 { "DAC 2", NULL, "DAC12 SRC Mux" },
0e826e86 3968 { "DAC 3", NULL, "DAC3 SRC Mux" },
0e826e86
OC		 3969
3970 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3971 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3972 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3973 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3974 { "PDM1 L Mux", NULL, "PDM1 Power" },
3975 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3976 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3977 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3978 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3979 { "PDM1 R Mux", NULL, "PDM1 Power" },
3980 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3981 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3982 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3983 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3984 { "PDM2 L Mux", NULL, "PDM2 Power" },
3985 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3986 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3987 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3988 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3989 { "PDM2 R Mux", NULL, "PDM2 Power" },
3990
3991 { "LOUT1 amp", NULL, "DAC 1" },
3992 { "LOUT2 amp", NULL, "DAC 2" },
3993 { "LOUT3 amp", NULL, "DAC 3" },
3994
683996cb
OC		 3995 { "LOUT1 vref", NULL, "LOUT1 amp" },
3996 { "LOUT2 vref", NULL, "LOUT2 amp" },
3997 { "LOUT3 vref", NULL, "LOUT3 amp" },
3998
3999 { "LOUT1", NULL, "LOUT1 vref" },
4000 { "LOUT2", NULL, "LOUT2 vref" },
4001 { "LOUT3", NULL, "LOUT3 vref" },
0e826e86
OC		 4002
4003 { "PDM1L", NULL, "PDM1 L Mux" },
4004 { "PDM1R", NULL, "PDM1 R Mux" },
4005 { "PDM2L", NULL, "PDM2 L Mux" },
4006 { "PDM2R", NULL, "PDM2 R Mux" },
4007};
4008
2d15d974
BL		 4009static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4010 { "DMIC L2", NULL, "DMIC1 power" },
4011 { "DMIC R2", NULL, "DMIC1 power" },
4012};
4013
4014static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4015 { "DMIC L2", NULL, "DMIC2 power" },
4016 { "DMIC R2", NULL, "DMIC2 power" },
4017};
4018
0e826e86
OC		 4019static int rt5677_hw_params(struct snd_pcm_substream *substream,
4020 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4021{
4022 struct snd_soc_codec *codec = dai->codec;
4023 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4024 unsigned int val_len = 0, val_clk, mask_clk;
4025 int pre_div, bclk_ms, frame_size;
4026
4027 rt5677->lrck[dai->id] = params_rate(params);
30f14b43 4028 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86 4029 if (pre_div < 0) {
8a4bd60a
AP		 4030 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4031 rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86
OC		 4032 return -EINVAL;
4033 }
4034 frame_size = snd_soc_params_to_frame_size(params);
4035 if (frame_size < 0) {
4036 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4037 return -EINVAL;
4038 }
4039 bclk_ms = frame_size > 32;
4040 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4041
4042 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4043 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4044 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4045 bclk_ms, pre_div, dai->id);
4046
4047 switch (params_width(params)) {
4048 case 16:
4049 break;
4050 case 20:
4051 val_len |= RT5677_I2S_DL_20;
4052 break;
4053 case 24:
4054 val_len |= RT5677_I2S_DL_24;
4055 break;
4056 case 8:
4057 val_len |= RT5677_I2S_DL_8;
4058 break;
4059 default:
4060 return -EINVAL;
4061 }
4062
4063 switch (dai->id) {
4064 case RT5677_AIF1:
4065 mask_clk = RT5677_I2S_PD1_MASK;
4066 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4067 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4068 RT5677_I2S_DL_MASK, val_len);
4069 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4070 mask_clk, val_clk);
4071 break;
4072 case RT5677_AIF2:
4073 mask_clk = RT5677_I2S_PD2_MASK;
4074 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4075 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4076 RT5677_I2S_DL_MASK, val_len);
4077 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4078 mask_clk, val_clk);
4079 break;
4080 case RT5677_AIF3:
4081 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4082 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4083 pre_div << RT5677_I2S_PD3_SFT;
4084 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4085 RT5677_I2S_DL_MASK, val_len);
4086 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4087 mask_clk, val_clk);
4088 break;
4089 case RT5677_AIF4:
4090 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4091 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4092 pre_div << RT5677_I2S_PD4_SFT;
4093 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4094 RT5677_I2S_DL_MASK, val_len);
4095 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4096 mask_clk, val_clk);
4097 break;
4098 default:
4099 break;
4100 }
4101
4102 return 0;
4103}
4104
4105static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4106{
4107 struct snd_soc_codec *codec = dai->codec;
4108 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4109 unsigned int reg_val = 0;
4110
4111 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4112 case SND_SOC_DAIFMT_CBM_CFM:
4113 rt5677->master[dai->id] = 1;
4114 break;
4115 case SND_SOC_DAIFMT_CBS_CFS:
4116 reg_val |= RT5677_I2S_MS_S;
4117 rt5677->master[dai->id] = 0;
4118 break;
4119 default:
4120 return -EINVAL;
4121 }
4122
4123 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4124 case SND_SOC_DAIFMT_NB_NF:
4125 break;
4126 case SND_SOC_DAIFMT_IB_NF:
4127 reg_val |= RT5677_I2S_BP_INV;
4128 break;
4129 default:
4130 return -EINVAL;
4131 }
4132
4133 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4134 case SND_SOC_DAIFMT_I2S:
4135 break;
4136 case SND_SOC_DAIFMT_LEFT_J:
4137 reg_val |= RT5677_I2S_DF_LEFT;
4138 break;
4139 case SND_SOC_DAIFMT_DSP_A:
4140 reg_val |= RT5677_I2S_DF_PCM_A;
4141 break;
4142 case SND_SOC_DAIFMT_DSP_B:
4143 reg_val |= RT5677_I2S_DF_PCM_B;
4144 break;
4145 default:
4146 return -EINVAL;
4147 }
4148
4149 switch (dai->id) {
4150 case RT5677_AIF1:
4151 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4152 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4153 RT5677_I2S_DF_MASK, reg_val);
4154 break;
4155 case RT5677_AIF2:
4156 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4157 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4158 RT5677_I2S_DF_MASK, reg_val);
4159 break;
4160 case RT5677_AIF3:
4161 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4162 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4163 RT5677_I2S_DF_MASK, reg_val);
4164 break;
4165 case RT5677_AIF4:
4166 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4167 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4168 RT5677_I2S_DF_MASK, reg_val);
4169 break;
4170 default:
4171 break;
4172 }
4173
4174
4175 return 0;
4176}
4177
4178static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4179 int clk_id, unsigned int freq, int dir)
4180{
4181 struct snd_soc_codec *codec = dai->codec;
4182 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4183 unsigned int reg_val = 0;
4184
4185 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4186 return 0;
4187
4188 switch (clk_id) {
4189 case RT5677_SCLK_S_MCLK:
4190 reg_val |= RT5677_SCLK_SRC_MCLK;
4191 break;
4192 case RT5677_SCLK_S_PLL1:
4193 reg_val |= RT5677_SCLK_SRC_PLL1;
4194 break;
4195 case RT5677_SCLK_S_RCCLK:
4196 reg_val |= RT5677_SCLK_SRC_RCCLK;
4197 break;
4198 default:
4199 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4200 return -EINVAL;
4201 }
4202 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4203 RT5677_SCLK_SRC_MASK, reg_val);
4204 rt5677->sysclk = freq;
4205 rt5677->sysclk_src = clk_id;
4206
4207 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4208
4209 return 0;
4210}
4211
4212/**
4213 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4214 * @freq_in: external clock provided to codec.
4215 * @freq_out: target clock which codec works on.
4216 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4217 *
4218 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4219 *
4220 * Returns 0 for success or negative error code.
4221 */
4222static int rt5677_pll_calc(const unsigned int freq_in,
099d334e 4223 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
0e826e86 4224{
099d334e 4225 if (RT5677_PLL_INP_MIN > freq_in)
0e826e86
OC		 4226 return -EINVAL;
4227
099d334e 4228 return rl6231_pll_calc(freq_in, freq_out, pll_code);
0e826e86
OC		 4229}
4230
4231static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4232 unsigned int freq_in, unsigned int freq_out)
4233{
4234 struct snd_soc_codec *codec = dai->codec;
4235 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
099d334e 4236 struct rl6231_pll_code pll_code;
0e826e86
OC		 4237 int ret;
4238
4239 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4240 freq_out == rt5677->pll_out)
4241 return 0;
4242
4243 if (!freq_in || !freq_out) {
4244 dev_dbg(codec->dev, "PLL disabled\n");
4245
4246 rt5677->pll_in = 0;
4247 rt5677->pll_out = 0;
4248 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4249 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4250 return 0;
4251 }
4252
4253 switch (source) {
4254 case RT5677_PLL1_S_MCLK:
4255 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4256 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4257 break;
4258 case RT5677_PLL1_S_BCLK1:
4259 case RT5677_PLL1_S_BCLK2:
4260 case RT5677_PLL1_S_BCLK3:
4261 case RT5677_PLL1_S_BCLK4:
4262 switch (dai->id) {
4263 case RT5677_AIF1:
4264 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4265 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4266 break;
4267 case RT5677_AIF2:
4268 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4269 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4270 break;
4271 case RT5677_AIF3:
4272 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4273 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4274 break;
4275 case RT5677_AIF4:
4276 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4277 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4278 break;
4279 default:
4280 break;
4281 }
4282 break;
4283 default:
4284 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4285 return -EINVAL;
4286 }
4287
4288 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4289 if (ret < 0) {
4290 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4291 return ret;
4292 }
4293
099d334e
AL		 4294 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4295 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4296 pll_code.n_code, pll_code.k_code);
0e826e86
OC		 4297
4298 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
099d334e 4299 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
0e826e86
OC		 4300 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4301 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4302 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4303
4304 rt5677->pll_in = freq_in;
4305 rt5677->pll_out = freq_out;
4306 rt5677->pll_src = source;
4307
4308 return 0;
4309}
4310
48561afe
OC		 4311static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4312 unsigned int rx_mask, int slots, int slot_width)
4313{
4314 struct snd_soc_codec *codec = dai->codec;
e4b7e6a8 4315 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
9913b9f5 4316 unsigned int val = 0, slot_width_25 = 0;
48561afe
OC		 4317
4318 if (rx_mask || tx_mask)
4319 val |= (1 << 12);
4320
4321 switch (slots) {
4322 case 4:
4323 val |= (1 << 10);
4324 break;
4325 case 6:
4326 val |= (2 << 10);
4327 break;
4328 case 8:
4329 val |= (3 << 10);
4330 break;
4331 case 2:
4332 default:
4333 break;
4334 }
4335
4336 switch (slot_width) {
4337 case 20:
4338 val |= (1 << 8);
4339 break;
9913b9f5
OC		 4340 case 25:
4341 slot_width_25 = 0x8080;
48561afe
OC		 4342 case 24:
4343 val |= (2 << 8);
4344 break;
4345 case 32:
4346 val |= (3 << 8);
4347 break;
4348 case 16:
4349 default:
4350 break;
4351 }
4352
4353 switch (dai->id) {
4354 case RT5677_AIF1:
e4b7e6a8
OC		 4355 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4356 val);
9913b9f5
OC		 4357 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4358 slot_width_25);
48561afe
OC		 4359 break;
4360 case RT5677_AIF2:
e4b7e6a8
OC		 4361 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4362 val);
9913b9f5
OC		 4363 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4364 slot_width_25);
48561afe
OC		 4365 break;
4366 default:
4367 break;
4368 }
4369
4370 return 0;
4371}
4372
0e826e86
OC		 4373static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4374 enum snd_soc_bias_level level)
4375{
4376 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4377
4378 switch (level) {
4379 case SND_SOC_BIAS_ON:
4380 break;
4381
4382 case SND_SOC_BIAS_PREPARE:
4383 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
af48f1d0
OC		 4384 rt5677_set_dsp_vad(codec, false);
4385
0e826e86
OC		 4386 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4387 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4388 0x0055);
4389 regmap_update_bits(rt5677->regmap,
4390 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4391 0x0f00, 0x0f00);
4392 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
683996cb 4393 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
0e826e86
OC		 4394 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4395 RT5677_PWR_BG | RT5677_PWR_VREF2,
4396 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4397 RT5677_PWR_BG | RT5677_PWR_VREF2);
683996cb 4398 rt5677->is_vref_slow = false;
0e826e86
OC		 4399 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4400 RT5677_PWR_CORE, RT5677_PWR_CORE);
4401 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4402 0x1, 0x1);
4403 }
4404 break;
4405
4406 case SND_SOC_BIAS_STANDBY:
4407 break;
4408
4409 case SND_SOC_BIAS_OFF:
4410 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4411 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4412 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
f18803a3 4413 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
0e826e86
OC		 4414 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4415 regmap_update_bits(rt5677->regmap,
4416 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
af48f1d0
OC		 4417
4418 if (rt5677->dsp_vad_en)
4419 rt5677_set_dsp_vad(codec, true);
0e826e86
OC		 4420 break;
4421
4422 default:
4423 break;
4424 }
4425 codec->dapm.bias_level = level;
4426
4427 return 0;
4428}
4429
44caf764
OC		 4430#ifdef CONFIG_GPIOLIB
4431static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4432{
4433 return container_of(chip, struct rt5677_priv, gpio_chip);
4434}
4435
4436static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4437{
4438 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4439
4440 switch (offset) {
4441 case RT5677_GPIO1 ... RT5677_GPIO5:
4442 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4443 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4444 break;
4445
4446 case RT5677_GPIO6:
4447 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4448 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4449 break;
4450
4451 default:
4452 break;
4453 }
4454}
4455
4456static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4457 unsigned offset, int value)
4458{
4459 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4460
4461 switch (offset) {
4462 case RT5677_GPIO1 ... RT5677_GPIO5:
4463 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4464 0x3 << (offset * 3 + 1),
4465 (0x2 | !!value) << (offset * 3 + 1));
4466 break;
4467
4468 case RT5677_GPIO6:
4469 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4470 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4471 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4472 break;
4473
4474 default:
4475 break;
4476 }
4477
4478 return 0;
4479}
4480
4481static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4482{
4483 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4484 int value, ret;
4485
4486 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4487 if (ret < 0)
4488 return ret;
4489
4490 return (value & (0x1 << offset)) >> offset;
4491}
4492
4493static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4494{
4495 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4496
4497 switch (offset) {
4498 case RT5677_GPIO1 ... RT5677_GPIO5:
4499 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4500 0x1 << (offset * 3 + 2), 0x0);
4501 break;
4502
4503 case RT5677_GPIO6:
4504 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4505 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4506 break;
4507
4508 default:
4509 break;
4510 }
4511
4512 return 0;
4513}
4514
40eb90a1
AP		 4515/** Configures the gpio as
4516 * 0 - floating
4517 * 1 - pull down
4518 * 2 - pull up
4519 */
4520static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4521 int value)
4522{
4523 int shift;
4524
4525 switch (offset) {
4526 case RT5677_GPIO1 ... RT5677_GPIO2:
4527 shift = 2 * (1 - offset);
4528 regmap_update_bits(rt5677->regmap,
4529 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4530 0x3 << shift,
4531 (value & 0x3) << shift);
4532 break;
4533
4534 case RT5677_GPIO3 ... RT5677_GPIO6:
4535 shift = 2 * (9 - offset);
4536 regmap_update_bits(rt5677->regmap,
4537 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4538 0x3 << shift,
4539 (value & 0x3) << shift);
4540 break;
4541
4542 default:
4543 break;
4544 }
4545}
4546
5e3363ad
OC		 4547static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4548{
4549 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4550 struct regmap_irq_chip_data *data = rt5677->irq_data;
4551 int irq;
4552
4553 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4554 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4555 (rt5677->pdata.jd1_gpio == 2 &&
4556 offset == RT5677_GPIO2) ||
4557 (rt5677->pdata.jd1_gpio == 3 &&
4558 offset == RT5677_GPIO3)) {
4559 irq = RT5677_IRQ_JD1;
4560 } else {
4561 return -ENXIO;
4562 }
4563 }
4564
4565 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4566 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4567 (rt5677->pdata.jd2_gpio == 2 &&
4568 offset == RT5677_GPIO5) ||
4569 (rt5677->pdata.jd2_gpio == 3 &&
4570 offset == RT5677_GPIO6)) {
4571 irq = RT5677_IRQ_JD2;
4572 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4573 offset == RT5677_GPIO4) ||
4574 (rt5677->pdata.jd3_gpio == 2 &&
4575 offset == RT5677_GPIO5) ||
4576 (rt5677->pdata.jd3_gpio == 3 &&
4577 offset == RT5677_GPIO6)) {
4578 irq = RT5677_IRQ_JD3;
4579 } else {
4580 return -ENXIO;
4581 }
4582 }
4583
4584 return regmap_irq_get_virq(data, irq);
4585}
4586
44caf764
OC		 4587static struct gpio_chip rt5677_template_chip = {
4588 .label = "rt5677",
4589 .owner = THIS_MODULE,
4590 .direction_output = rt5677_gpio_direction_out,
4591 .set = rt5677_gpio_set,
4592 .direction_input = rt5677_gpio_direction_in,
4593 .get = rt5677_gpio_get,
5e3363ad 4594 .to_irq = rt5677_to_irq,
44caf764
OC		 4595 .can_sleep = 1,
4596};
4597
4598static void rt5677_init_gpio(struct i2c_client *i2c)
4599{
4600 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4601 int ret;
4602
4603 rt5677->gpio_chip = rt5677_template_chip;
4604 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4605 rt5677->gpio_chip.dev = &i2c->dev;
4606 rt5677->gpio_chip.base = -1;
4607
4608 ret = gpiochip_add(&rt5677->gpio_chip);
4609 if (ret != 0)
4610 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4611}
4612
4613static void rt5677_free_gpio(struct i2c_client *i2c)
4614{
4615 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
44caf764 4616
5d5e63af 4617 gpiochip_remove(&rt5677->gpio_chip);
44caf764
OC		 4618}
4619#else
45b6e1d3
AP		 4620static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4621 int value)
4622{
4623}
4624
44caf764
OC		 4625static void rt5677_init_gpio(struct i2c_client *i2c)
4626{
4627}
4628
4629static void rt5677_free_gpio(struct i2c_client *i2c)
4630{
4631}
4632#endif
4633
0e826e86
OC		 4634static int rt5677_probe(struct snd_soc_codec *codec)
4635{
4636 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
40eb90a1 4637 int i;
0e826e86
OC		 4638
4639 rt5677->codec = codec;
4640
2d15d974
BL		 4641 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4642 snd_soc_dapm_add_routes(&codec->dapm,
4643 rt5677_dmic2_clk_2,
4644 ARRAY_SIZE(rt5677_dmic2_clk_2));
4645 } else { /*use dmic1 clock by default*/
4646 snd_soc_dapm_add_routes(&codec->dapm,
4647 rt5677_dmic2_clk_1,
4648 ARRAY_SIZE(rt5677_dmic2_clk_1));
4649 }
4650
0e826e86
OC		 4651 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
4652
4653 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4654 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4655
40eb90a1
AP		 4656 for (i = 0; i < RT5677_GPIO_NUM; i++)
4657 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4658
5e3363ad
OC		 4659 if (rt5677->irq_data) {
4660 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4661 0x8000);
4662 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4663 0x0008);
4664
4665 if (rt5677->pdata.jd1_gpio)
4666 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4667 RT5677_SEL_GPIO_JD1_MASK,
4668 rt5677->pdata.jd1_gpio <<
4669 RT5677_SEL_GPIO_JD1_SFT);
4670
4671 if (rt5677->pdata.jd2_gpio)
4672 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4673 RT5677_SEL_GPIO_JD2_MASK,
4674 rt5677->pdata.jd2_gpio <<
4675 RT5677_SEL_GPIO_JD2_SFT);
4676
4677 if (rt5677->pdata.jd3_gpio)
4678 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4679 RT5677_SEL_GPIO_JD3_MASK,
4680 rt5677->pdata.jd3_gpio <<
4681 RT5677_SEL_GPIO_JD3_SFT);
4682 }
4683
af48f1d0 4684 mutex_init(&rt5677->dsp_cmd_lock);
6fe17da0 4685 mutex_init(&rt5677->dsp_pri_lock);
af48f1d0 4686
0e826e86
OC		 4687 return 0;
4688}
4689
4690static int rt5677_remove(struct snd_soc_codec *codec)
4691{
4692 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4693
4694 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
f9f6a592
AP		 4695 if (gpio_is_valid(rt5677->pow_ldo2))
4696 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
0e826e86
OC		 4697
4698 return 0;
4699}
4700
4701#ifdef CONFIG_PM
4702static int rt5677_suspend(struct snd_soc_codec *codec)
4703{
4704 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4705
af48f1d0
OC		 4706 if (!rt5677->dsp_vad_en) {
4707 regcache_cache_only(rt5677->regmap, true);
4708 regcache_mark_dirty(rt5677->regmap);
af48f1d0 4709
cbca4076
OC		 4710 if (gpio_is_valid(rt5677->pow_ldo2))
4711 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4712 }
0e826e86
OC		 4713
4714 return 0;
4715}
4716
4717static int rt5677_resume(struct snd_soc_codec *codec)
4718{
4719 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4720
af48f1d0 4721 if (!rt5677->dsp_vad_en) {
cbca4076
OC		 4722 if (gpio_is_valid(rt5677->pow_ldo2)) {
4723 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4724 msleep(10);
4725 }
4726
af48f1d0
OC		 4727 regcache_cache_only(rt5677->regmap, false);
4728 regcache_sync(rt5677->regmap);
4729 }
0e826e86
OC		 4730
4731 return 0;
4732}
4733#else
4734#define rt5677_suspend NULL
4735#define rt5677_resume NULL
4736#endif
4737
19ba484d
OC		 4738static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4739{
4740 struct i2c_client *client = context;
4741 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4742
6fe17da0
OC		 4743 if (rt5677->is_dsp_mode) {
4744 if (reg > 0xff) {
4745 mutex_lock(&rt5677->dsp_pri_lock);
4746 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4747 reg & 0xff);
4748 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4749 mutex_unlock(&rt5677->dsp_pri_lock);
4750 } else {
4751 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4752 }
4753 } else {
19ba484d 4754 regmap_read(rt5677->regmap_physical, reg, val);
6fe17da0 4755 }
19ba484d
OC		 4756
4757 return 0;
4758}
4759
4760static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4761{
4762 struct i2c_client *client = context;
4763 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4764
6fe17da0
OC		 4765 if (rt5677->is_dsp_mode) {
4766 if (reg > 0xff) {
4767 mutex_lock(&rt5677->dsp_pri_lock);
4768 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4769 reg & 0xff);
4770 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4771 val);
4772 mutex_unlock(&rt5677->dsp_pri_lock);
4773 } else {
4774 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4775 }
4776 } else {
19ba484d 4777 regmap_write(rt5677->regmap_physical, reg, val);
6fe17da0 4778 }
19ba484d
OC		 4779
4780 return 0;
4781}
4782
0e826e86
OC		 4783#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4784#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4785 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4786
4787static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4788 .hw_params = rt5677_hw_params,
4789 .set_fmt = rt5677_set_dai_fmt,
4790 .set_sysclk = rt5677_set_dai_sysclk,
4791 .set_pll = rt5677_set_dai_pll,
48561afe 4792 .set_tdm_slot = rt5677_set_tdm_slot,
0e826e86
OC		 4793};
4794
4795static struct snd_soc_dai_driver rt5677_dai[] = {
4796 {
4797 .name = "rt5677-aif1",
4798 .id = RT5677_AIF1,
4799 .playback = {
4800 .stream_name = "AIF1 Playback",
4801 .channels_min = 1,
4802 .channels_max = 2,
4803 .rates = RT5677_STEREO_RATES,
4804 .formats = RT5677_FORMATS,
4805 },
4806 .capture = {
4807 .stream_name = "AIF1 Capture",
4808 .channels_min = 1,
4809 .channels_max = 2,
4810 .rates = RT5677_STEREO_RATES,
4811 .formats = RT5677_FORMATS,
4812 },
4813 .ops = &rt5677_aif_dai_ops,
4814 },
4815 {
4816 .name = "rt5677-aif2",
4817 .id = RT5677_AIF2,
4818 .playback = {
4819 .stream_name = "AIF2 Playback",
4820 .channels_min = 1,
4821 .channels_max = 2,
4822 .rates = RT5677_STEREO_RATES,
4823 .formats = RT5677_FORMATS,
4824 },
4825 .capture = {
4826 .stream_name = "AIF2 Capture",
4827 .channels_min = 1,
4828 .channels_max = 2,
4829 .rates = RT5677_STEREO_RATES,
4830 .formats = RT5677_FORMATS,
4831 },
4832 .ops = &rt5677_aif_dai_ops,
4833 },
4834 {
4835 .name = "rt5677-aif3",
4836 .id = RT5677_AIF3,
4837 .playback = {
4838 .stream_name = "AIF3 Playback",
4839 .channels_min = 1,
4840 .channels_max = 2,
4841 .rates = RT5677_STEREO_RATES,
4842 .formats = RT5677_FORMATS,
4843 },
4844 .capture = {
4845 .stream_name = "AIF3 Capture",
4846 .channels_min = 1,
4847 .channels_max = 2,
4848 .rates = RT5677_STEREO_RATES,
4849 .formats = RT5677_FORMATS,
4850 },
4851 .ops = &rt5677_aif_dai_ops,
4852 },
4853 {
4854 .name = "rt5677-aif4",
4855 .id = RT5677_AIF4,
4856 .playback = {
4857 .stream_name = "AIF4 Playback",
4858 .channels_min = 1,
4859 .channels_max = 2,
4860 .rates = RT5677_STEREO_RATES,
4861 .formats = RT5677_FORMATS,
4862 },
4863 .capture = {
4864 .stream_name = "AIF4 Capture",
4865 .channels_min = 1,
4866 .channels_max = 2,
4867 .rates = RT5677_STEREO_RATES,
4868 .formats = RT5677_FORMATS,
4869 },
4870 .ops = &rt5677_aif_dai_ops,
4871 },
4872 {
4873 .name = "rt5677-slimbus",
4874 .id = RT5677_AIF5,
4875 .playback = {
4876 .stream_name = "SLIMBus Playback",
4877 .channels_min = 1,
4878 .channels_max = 2,
4879 .rates = RT5677_STEREO_RATES,
4880 .formats = RT5677_FORMATS,
4881 },
4882 .capture = {
4883 .stream_name = "SLIMBus Capture",
4884 .channels_min = 1,
4885 .channels_max = 2,
4886 .rates = RT5677_STEREO_RATES,
4887 .formats = RT5677_FORMATS,
4888 },
4889 .ops = &rt5677_aif_dai_ops,
4890 },
4891};
4892
4893static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4894 .probe = rt5677_probe,
4895 .remove = rt5677_remove,
4896 .suspend = rt5677_suspend,
4897 .resume = rt5677_resume,
4898 .set_bias_level = rt5677_set_bias_level,
4899 .idle_bias_off = true,
4900 .controls = rt5677_snd_controls,
4901 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4902 .dapm_widgets = rt5677_dapm_widgets,
4903 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4904 .dapm_routes = rt5677_dapm_routes,
4905 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4906};
4907
19ba484d
OC		 4908static const struct regmap_config rt5677_regmap_physical = {
4909 .name = "physical",
4910 .reg_bits = 8,
4911 .val_bits = 16,
4912
6fe17da0
OC		 4913 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4914 RT5677_PR_SPACING),
19ba484d
OC		 4915 .readable_reg = rt5677_readable_register,
4916
4917 .cache_type = REGCACHE_NONE,
6fe17da0
OC		 4918 .ranges = rt5677_ranges,
4919 .num_ranges = ARRAY_SIZE(rt5677_ranges),
19ba484d
OC		 4920};
4921
0e826e86
OC		 4922static const struct regmap_config rt5677_regmap = {
4923 .reg_bits = 8,
4924 .val_bits = 16,
4925
4926 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4927 RT5677_PR_SPACING),
4928
4929 .volatile_reg = rt5677_volatile_register,
4930 .readable_reg = rt5677_readable_register,
19ba484d
OC		 4931 .reg_read = rt5677_read,
4932 .reg_write = rt5677_write,
0e826e86
OC		 4933
4934 .cache_type = REGCACHE_RBTREE,
4935 .reg_defaults = rt5677_reg,
4936 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4937 .ranges = rt5677_ranges,
4938 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4939};
4940
4941static const struct i2c_device_id rt5677_i2c_id[] = {
ab1f7095
OC		 4942 { "rt5677", RT5677 },
4943 { "rt5676", RT5676 },
0e826e86
OC		 4944 { }
4945};
4946MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4947
f9f6a592
AP		 4948static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4949{
6f67c380
AP		 4950 rt5677->pdata.in1_diff = of_property_read_bool(np,
4951 "realtek,in1-differential");
4952 rt5677->pdata.in2_diff = of_property_read_bool(np,
4953 "realtek,in2-differential");
4954 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4955 "realtek,lout1-differential");
4956 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4957 "realtek,lout2-differential");
4958 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4959 "realtek,lout3-differential");
4960
f9f6a592
AP		 4961 rt5677->pow_ldo2 = of_get_named_gpio(np,
4962 "realtek,pow-ldo2-gpio", 0);
4963
4964 /*
4965 * POW_LDO2 is optional (it may be statically tied on the board).
4966 * -ENOENT means that the property doesn't exist, i.e. there is no
4967 * GPIO, so is not an error. Any other error code means the property
4968 * exists, but could not be parsed.
4969 */
4970 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4971 (rt5677->pow_ldo2 != -ENOENT))
4972 return rt5677->pow_ldo2;
4973
40eb90a1
AP		 4974 of_property_read_u8_array(np, "realtek,gpio-config",
4975 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4976
5e3363ad
OC		 4977 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4978 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4979 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4980
f9f6a592
AP		 4981 return 0;
4982}
4983
5e3363ad
OC		 4984static struct regmap_irq rt5677_irqs[] = {
4985 [RT5677_IRQ_JD1] = {
4986 .reg_offset = 0,
4987 .mask = RT5677_EN_IRQ_GPIO_JD1,
4988 },
4989 [RT5677_IRQ_JD2] = {
4990 .reg_offset = 0,
4991 .mask = RT5677_EN_IRQ_GPIO_JD2,
4992 },
4993 [RT5677_IRQ_JD3] = {
4994 .reg_offset = 0,
4995 .mask = RT5677_EN_IRQ_GPIO_JD3,
4996 },
4997};
4998
4999static struct regmap_irq_chip rt5677_irq_chip = {
5000 .name = "rt5677",
5001 .irqs = rt5677_irqs,
5002 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5003
5004 .num_regs = 1,
5005 .status_base = RT5677_IRQ_CTRL1,
5006 .mask_base = RT5677_IRQ_CTRL1,
5007 .mask_invert = 1,
5008};
5009
35d40d10 5010static int rt5677_init_irq(struct i2c_client *i2c)
5e3363ad
OC		 5011{
5012 int ret;
5013 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5014
5015 if (!rt5677->pdata.jd1_gpio &&
5016 !rt5677->pdata.jd2_gpio &&
5017 !rt5677->pdata.jd3_gpio)
5018 return 0;
5019
5020 if (!i2c->irq) {
5021 dev_err(&i2c->dev, "No interrupt specified\n");
5022 return -EINVAL;
5023 }
5024
5025 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5026 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5027 &rt5677_irq_chip, &rt5677->irq_data);
5028
5029 if (ret != 0) {
5030 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5031 return ret;
5032 }
5033
5034 return 0;
5035}
5036
35d40d10 5037static void rt5677_free_irq(struct i2c_client *i2c)
5e3363ad
OC		 5038{
5039 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5040
5041 if (rt5677->irq_data)
5042 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5043}
5044
0e826e86
OC		 5045static int rt5677_i2c_probe(struct i2c_client *i2c,
5046 const struct i2c_device_id *id)
5047{
5048 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5049 struct rt5677_priv *rt5677;
5050 int ret;
5051 unsigned int val;
5052
5053 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5054 GFP_KERNEL);
5055 if (rt5677 == NULL)
5056 return -ENOMEM;
5057
5058 i2c_set_clientdata(i2c, rt5677);
5059
ab1f7095
OC		 5060 rt5677->type = id->driver_data;
5061
0e826e86
OC		 5062 if (pdata)
5063 rt5677->pdata = *pdata;
5064
f9f6a592
AP		 5065 if (i2c->dev.of_node) {
5066 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
5067 if (ret) {
5068 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
5069 ret);
5070 return ret;
5071 }
5072 } else {
5073 rt5677->pow_ldo2 = -EINVAL;
5074 }
5075
5076 if (gpio_is_valid(rt5677->pow_ldo2)) {
5077 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
5078 GPIOF_OUT_INIT_HIGH,
5079 "RT5677 POW_LDO2");
5080 if (ret < 0) {
5081 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
5082 rt5677->pow_ldo2, ret);
5083 return ret;
5084 }
5085 /* Wait a while until I2C bus becomes available. The datasheet
5086 * does not specify the exact we should wait but startup
5087 * sequence mentiones at least a few milliseconds.
5088 */
5089 msleep(10);
5090 }
5091
19ba484d
OC		 5092 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5093 &rt5677_regmap_physical);
5094 if (IS_ERR(rt5677->regmap_physical)) {
5095 ret = PTR_ERR(rt5677->regmap_physical);
5096 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5097 ret);
5098 return ret;
5099 }
5100
5101 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
0e826e86
OC		 5102 if (IS_ERR(rt5677->regmap)) {
5103 ret = PTR_ERR(rt5677->regmap);
5104 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5105 ret);
5106 return ret;
5107 }
5108
5109 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5110 if (val != RT5677_DEVICE_ID) {
5111 dev_err(&i2c->dev,
5112 "Device with ID register %x is not rt5677\n", val);
5113 return -ENODEV;
5114 }
5115
5116 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5117
5118 ret = regmap_register_patch(rt5677->regmap, init_list,
5119 ARRAY_SIZE(init_list));
5120 if (ret != 0)
5121 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5122
5123 if (rt5677->pdata.in1_diff)
5124 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5125 RT5677_IN_DF1, RT5677_IN_DF1);
5126
5127 if (rt5677->pdata.in2_diff)
5128 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5129 RT5677_IN_DF2, RT5677_IN_DF2);
5130
6f67c380
AP		 5131 if (rt5677->pdata.lout1_diff)
5132 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5133 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5134
5135 if (rt5677->pdata.lout2_diff)
5136 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5137 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5138
5139 if (rt5677->pdata.lout3_diff)
5140 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5141 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5142
2d15d974
BL		 5143 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5144 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5145 RT5677_GPIO5_FUNC_MASK,
5146 RT5677_GPIO5_FUNC_DMIC);
5147 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5148 RT5677_GPIO5_DIR_MASK,
5149 RT5677_GPIO5_DIR_OUT);
5150 }
5151
277880a3
OC		 5152 if (rt5677->pdata.micbias1_vdd_3v3)
5153 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5154 RT5677_MICBIAS1_CTRL_VDD_MASK,
5155 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5156
44caf764 5157 rt5677_init_gpio(i2c);
35d40d10 5158 rt5677_init_irq(i2c);
44caf764 5159
d0bdcb91
AL		 5160 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5161 rt5677_dai, ARRAY_SIZE(rt5677_dai));
0e826e86
OC		 5162}
5163
5164static int rt5677_i2c_remove(struct i2c_client *i2c)
5165{
5166 snd_soc_unregister_codec(&i2c->dev);
35d40d10 5167 rt5677_free_irq(i2c);
44caf764 5168 rt5677_free_gpio(i2c);
0e826e86
OC		 5169
5170 return 0;
5171}
5172
5173static struct i2c_driver rt5677_i2c_driver = {
5174 .driver = {
5175 .name = "rt5677",
5176 .owner = THIS_MODULE,
5177 },
5178 .probe = rt5677_i2c_probe,
5179 .remove = rt5677_i2c_remove,
5180 .id_table = rt5677_i2c_id,
5181};
c8cfbec8 5182module_i2c_driver(rt5677_i2c_driver);
0e826e86
OC		 5183
5184MODULE_DESCRIPTION("ASoC RT5677 driver");
5185MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5186MODULE_LICENSE("GPL v2");
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