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0e826e86 OC |
1 | /* |
2 | * rt5677.c -- RT5677 ALSA SoC audio codec driver | |
3 | * | |
4 | * Copyright 2013 Realtek Semiconductor Corp. | |
5 | * Author: Oder Chiou <oder_chiou@realtek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/fs.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/pm.h> | |
f9f6a592 | 18 | #include <linux/of_gpio.h> |
0e826e86 OC |
19 | #include <linux/regmap.h> |
20 | #include <linux/i2c.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/spi/spi.h> | |
af48f1d0 | 23 | #include <linux/firmware.h> |
44caf764 | 24 | #include <linux/gpio.h> |
0e826e86 OC |
25 | #include <sound/core.h> |
26 | #include <sound/pcm.h> | |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/soc.h> | |
29 | #include <sound/soc-dapm.h> | |
30 | #include <sound/initval.h> | |
31 | #include <sound/tlv.h> | |
32 | ||
30f14b43 | 33 | #include "rl6231.h" |
0e826e86 | 34 | #include "rt5677.h" |
af48f1d0 | 35 | #include "rt5677-spi.h" |
0e826e86 OC |
36 | |
37 | #define RT5677_DEVICE_ID 0x6327 | |
38 | ||
39 | #define RT5677_PR_RANGE_BASE (0xff + 1) | |
40 | #define RT5677_PR_SPACING 0x100 | |
41 | ||
42 | #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) | |
43 | ||
44 | static const struct regmap_range_cfg rt5677_ranges[] = { | |
45 | { | |
46 | .name = "PR", | |
47 | .range_min = RT5677_PR_BASE, | |
48 | .range_max = RT5677_PR_BASE + 0xfd, | |
49 | .selector_reg = RT5677_PRIV_INDEX, | |
50 | .selector_mask = 0xff, | |
51 | .selector_shift = 0x0, | |
52 | .window_start = RT5677_PRIV_DATA, | |
53 | .window_len = 0x1, | |
54 | }, | |
55 | }; | |
56 | ||
57 | static const struct reg_default init_list[] = { | |
2dfe2b08 OC |
58 | {RT5677_ASRC_12, 0x0018}, |
59 | {RT5677_PR_BASE + 0x3d, 0x364d}, | |
60 | {RT5677_PR_BASE + 0x17, 0x4fc0}, | |
61 | {RT5677_PR_BASE + 0x13, 0x0312}, | |
62 | {RT5677_PR_BASE + 0x1e, 0x0000}, | |
63 | {RT5677_PR_BASE + 0x12, 0x0eaa}, | |
64 | {RT5677_PR_BASE + 0x14, 0x018a}, | |
0e826e86 OC |
65 | }; |
66 | #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) | |
67 | ||
68 | static const struct reg_default rt5677_reg[] = { | |
69 | {RT5677_RESET , 0x0000}, | |
70 | {RT5677_LOUT1 , 0xa800}, | |
71 | {RT5677_IN1 , 0x0000}, | |
72 | {RT5677_MICBIAS , 0x0000}, | |
73 | {RT5677_SLIMBUS_PARAM , 0x0000}, | |
74 | {RT5677_SLIMBUS_RX , 0x0000}, | |
75 | {RT5677_SLIMBUS_CTRL , 0x0000}, | |
76 | {RT5677_SIDETONE_CTRL , 0x000b}, | |
77 | {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, | |
78 | {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, | |
79 | {RT5677_DAC4_DIG_VOL , 0xafaf}, | |
80 | {RT5677_DAC3_DIG_VOL , 0xafaf}, | |
81 | {RT5677_DAC1_DIG_VOL , 0xafaf}, | |
82 | {RT5677_DAC2_DIG_VOL , 0xafaf}, | |
83 | {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, | |
84 | {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, | |
85 | {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, | |
86 | {RT5677_STO1_2_ADC_BST , 0x0000}, | |
87 | {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, | |
88 | {RT5677_ADC_BST_CTRL2 , 0x0000}, | |
89 | {RT5677_STO3_4_ADC_BST , 0x0000}, | |
90 | {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, | |
91 | {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, | |
92 | {RT5677_STO4_ADC_MIXER , 0xd4c0}, | |
93 | {RT5677_STO3_ADC_MIXER , 0xd4c0}, | |
94 | {RT5677_STO2_ADC_MIXER , 0xd4c0}, | |
95 | {RT5677_STO1_ADC_MIXER , 0xd4c0}, | |
96 | {RT5677_MONO_ADC_MIXER , 0xd4d1}, | |
97 | {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, | |
98 | {RT5677_STO1_DAC_MIXER , 0xaaaa}, | |
99 | {RT5677_MONO_DAC_MIXER , 0xaaaa}, | |
100 | {RT5677_DD1_MIXER , 0xaaaa}, | |
101 | {RT5677_DD2_MIXER , 0xaaaa}, | |
102 | {RT5677_IF3_DATA , 0x0000}, | |
103 | {RT5677_IF4_DATA , 0x0000}, | |
104 | {RT5677_PDM_OUT_CTRL , 0x8888}, | |
105 | {RT5677_PDM_DATA_CTRL1 , 0x0000}, | |
106 | {RT5677_PDM_DATA_CTRL2 , 0x0000}, | |
107 | {RT5677_PDM1_DATA_CTRL2 , 0x0000}, | |
108 | {RT5677_PDM1_DATA_CTRL3 , 0x0000}, | |
109 | {RT5677_PDM1_DATA_CTRL4 , 0x0000}, | |
110 | {RT5677_PDM2_DATA_CTRL2 , 0x0000}, | |
111 | {RT5677_PDM2_DATA_CTRL3 , 0x0000}, | |
112 | {RT5677_PDM2_DATA_CTRL4 , 0x0000}, | |
113 | {RT5677_TDM1_CTRL1 , 0x0300}, | |
114 | {RT5677_TDM1_CTRL2 , 0x0000}, | |
115 | {RT5677_TDM1_CTRL3 , 0x4000}, | |
116 | {RT5677_TDM1_CTRL4 , 0x0123}, | |
117 | {RT5677_TDM1_CTRL5 , 0x4567}, | |
118 | {RT5677_TDM2_CTRL1 , 0x0300}, | |
119 | {RT5677_TDM2_CTRL2 , 0x0000}, | |
120 | {RT5677_TDM2_CTRL3 , 0x4000}, | |
121 | {RT5677_TDM2_CTRL4 , 0x0123}, | |
122 | {RT5677_TDM2_CTRL5 , 0x4567}, | |
123 | {RT5677_I2C_MASTER_CTRL1 , 0x0001}, | |
124 | {RT5677_I2C_MASTER_CTRL2 , 0x0000}, | |
125 | {RT5677_I2C_MASTER_CTRL3 , 0x0000}, | |
126 | {RT5677_I2C_MASTER_CTRL4 , 0x0000}, | |
127 | {RT5677_I2C_MASTER_CTRL5 , 0x0000}, | |
128 | {RT5677_I2C_MASTER_CTRL6 , 0x0000}, | |
129 | {RT5677_I2C_MASTER_CTRL7 , 0x0000}, | |
130 | {RT5677_I2C_MASTER_CTRL8 , 0x0000}, | |
131 | {RT5677_DMIC_CTRL1 , 0x1505}, | |
132 | {RT5677_DMIC_CTRL2 , 0x0055}, | |
133 | {RT5677_HAP_GENE_CTRL1 , 0x0111}, | |
134 | {RT5677_HAP_GENE_CTRL2 , 0x0064}, | |
135 | {RT5677_HAP_GENE_CTRL3 , 0xef0e}, | |
136 | {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, | |
137 | {RT5677_HAP_GENE_CTRL5 , 0xef0e}, | |
138 | {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, | |
139 | {RT5677_HAP_GENE_CTRL7 , 0xef0e}, | |
140 | {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, | |
141 | {RT5677_HAP_GENE_CTRL9 , 0xf000}, | |
142 | {RT5677_HAP_GENE_CTRL10 , 0x0000}, | |
143 | {RT5677_PWR_DIG1 , 0x0000}, | |
144 | {RT5677_PWR_DIG2 , 0x0000}, | |
145 | {RT5677_PWR_ANLG1 , 0x0055}, | |
146 | {RT5677_PWR_ANLG2 , 0x0000}, | |
147 | {RT5677_PWR_DSP1 , 0x0001}, | |
148 | {RT5677_PWR_DSP_ST , 0x0000}, | |
149 | {RT5677_PWR_DSP2 , 0x0000}, | |
150 | {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, | |
151 | {RT5677_PRIV_INDEX , 0x0000}, | |
152 | {RT5677_PRIV_DATA , 0x0000}, | |
153 | {RT5677_I2S4_SDP , 0x8000}, | |
154 | {RT5677_I2S1_SDP , 0x8000}, | |
155 | {RT5677_I2S2_SDP , 0x8000}, | |
156 | {RT5677_I2S3_SDP , 0x8000}, | |
157 | {RT5677_CLK_TREE_CTRL1 , 0x1111}, | |
158 | {RT5677_CLK_TREE_CTRL2 , 0x1111}, | |
159 | {RT5677_CLK_TREE_CTRL3 , 0x0000}, | |
160 | {RT5677_PLL1_CTRL1 , 0x0000}, | |
161 | {RT5677_PLL1_CTRL2 , 0x0000}, | |
162 | {RT5677_PLL2_CTRL1 , 0x0c60}, | |
163 | {RT5677_PLL2_CTRL2 , 0x2000}, | |
164 | {RT5677_GLB_CLK1 , 0x0000}, | |
165 | {RT5677_GLB_CLK2 , 0x0000}, | |
166 | {RT5677_ASRC_1 , 0x0000}, | |
167 | {RT5677_ASRC_2 , 0x0000}, | |
168 | {RT5677_ASRC_3 , 0x0000}, | |
169 | {RT5677_ASRC_4 , 0x0000}, | |
170 | {RT5677_ASRC_5 , 0x0000}, | |
171 | {RT5677_ASRC_6 , 0x0000}, | |
172 | {RT5677_ASRC_7 , 0x0000}, | |
173 | {RT5677_ASRC_8 , 0x0000}, | |
174 | {RT5677_ASRC_9 , 0x0000}, | |
175 | {RT5677_ASRC_10 , 0x0000}, | |
176 | {RT5677_ASRC_11 , 0x0000}, | |
86ae04b1 | 177 | {RT5677_ASRC_12 , 0x0018}, |
0e826e86 OC |
178 | {RT5677_ASRC_13 , 0x0000}, |
179 | {RT5677_ASRC_14 , 0x0000}, | |
180 | {RT5677_ASRC_15 , 0x0000}, | |
181 | {RT5677_ASRC_16 , 0x0000}, | |
182 | {RT5677_ASRC_17 , 0x0000}, | |
183 | {RT5677_ASRC_18 , 0x0000}, | |
184 | {RT5677_ASRC_19 , 0x0000}, | |
185 | {RT5677_ASRC_20 , 0x0000}, | |
186 | {RT5677_ASRC_21 , 0x000c}, | |
187 | {RT5677_ASRC_22 , 0x0000}, | |
188 | {RT5677_ASRC_23 , 0x0000}, | |
189 | {RT5677_VAD_CTRL1 , 0x2184}, | |
190 | {RT5677_VAD_CTRL2 , 0x010a}, | |
191 | {RT5677_VAD_CTRL3 , 0x0aea}, | |
192 | {RT5677_VAD_CTRL4 , 0x000c}, | |
193 | {RT5677_VAD_CTRL5 , 0x0000}, | |
194 | {RT5677_DSP_INB_CTRL1 , 0x0000}, | |
195 | {RT5677_DSP_INB_CTRL2 , 0x0000}, | |
196 | {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, | |
197 | {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, | |
198 | {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, | |
199 | {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, | |
200 | {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, | |
201 | {RT5677_ADC_EQ_CTRL1 , 0x6000}, | |
202 | {RT5677_ADC_EQ_CTRL2 , 0x0000}, | |
203 | {RT5677_EQ_CTRL1 , 0xc000}, | |
204 | {RT5677_EQ_CTRL2 , 0x0000}, | |
205 | {RT5677_EQ_CTRL3 , 0x0000}, | |
206 | {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, | |
207 | {RT5677_JD_CTRL1 , 0x0000}, | |
208 | {RT5677_JD_CTRL2 , 0x0000}, | |
209 | {RT5677_JD_CTRL3 , 0x0000}, | |
210 | {RT5677_IRQ_CTRL1 , 0x0000}, | |
211 | {RT5677_IRQ_CTRL2 , 0x0000}, | |
212 | {RT5677_GPIO_ST , 0x0000}, | |
213 | {RT5677_GPIO_CTRL1 , 0x0000}, | |
214 | {RT5677_GPIO_CTRL2 , 0x0000}, | |
215 | {RT5677_GPIO_CTRL3 , 0x0000}, | |
216 | {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, | |
217 | {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, | |
218 | {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, | |
219 | {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, | |
220 | {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, | |
221 | {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, | |
222 | {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, | |
223 | {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, | |
224 | {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, | |
225 | {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, | |
226 | {RT5677_MB_DRC_CTRL1 , 0x0f20}, | |
227 | {RT5677_DRC1_CTRL1 , 0x001f}, | |
228 | {RT5677_DRC1_CTRL2 , 0x020c}, | |
229 | {RT5677_DRC1_CTRL3 , 0x1f00}, | |
230 | {RT5677_DRC1_CTRL4 , 0x0000}, | |
231 | {RT5677_DRC1_CTRL5 , 0x0000}, | |
232 | {RT5677_DRC1_CTRL6 , 0x0029}, | |
233 | {RT5677_DRC2_CTRL1 , 0x001f}, | |
234 | {RT5677_DRC2_CTRL2 , 0x020c}, | |
235 | {RT5677_DRC2_CTRL3 , 0x1f00}, | |
236 | {RT5677_DRC2_CTRL4 , 0x0000}, | |
237 | {RT5677_DRC2_CTRL5 , 0x0000}, | |
238 | {RT5677_DRC2_CTRL6 , 0x0029}, | |
239 | {RT5677_DRC1_HL_CTRL1 , 0x8000}, | |
240 | {RT5677_DRC1_HL_CTRL2 , 0x0200}, | |
241 | {RT5677_DRC2_HL_CTRL1 , 0x8000}, | |
242 | {RT5677_DRC2_HL_CTRL2 , 0x0200}, | |
243 | {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, | |
244 | {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, | |
245 | {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, | |
246 | {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, | |
247 | {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, | |
248 | {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, | |
249 | {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, | |
250 | {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, | |
251 | {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, | |
252 | {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, | |
253 | {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, | |
254 | {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, | |
255 | {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, | |
256 | {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, | |
257 | {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, | |
258 | {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, | |
259 | {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, | |
260 | {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, | |
261 | {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, | |
262 | {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, | |
263 | {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, | |
264 | {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, | |
265 | {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, | |
266 | {RT5677_DIG_MISC , 0x0000}, | |
267 | {RT5677_GEN_CTRL1 , 0x0000}, | |
268 | {RT5677_GEN_CTRL2 , 0x0000}, | |
269 | {RT5677_VENDOR_ID , 0x0000}, | |
270 | {RT5677_VENDOR_ID1 , 0x10ec}, | |
271 | {RT5677_VENDOR_ID2 , 0x6327}, | |
272 | }; | |
273 | ||
274 | static bool rt5677_volatile_register(struct device *dev, unsigned int reg) | |
275 | { | |
276 | int i; | |
277 | ||
278 | for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { | |
279 | if (reg >= rt5677_ranges[i].range_min && | |
280 | reg <= rt5677_ranges[i].range_max) { | |
281 | return true; | |
282 | } | |
283 | } | |
284 | ||
285 | switch (reg) { | |
286 | case RT5677_RESET: | |
287 | case RT5677_SLIMBUS_PARAM: | |
288 | case RT5677_PDM_DATA_CTRL1: | |
289 | case RT5677_PDM_DATA_CTRL2: | |
290 | case RT5677_PDM1_DATA_CTRL4: | |
291 | case RT5677_PDM2_DATA_CTRL4: | |
292 | case RT5677_I2C_MASTER_CTRL1: | |
293 | case RT5677_I2C_MASTER_CTRL7: | |
294 | case RT5677_I2C_MASTER_CTRL8: | |
295 | case RT5677_HAP_GENE_CTRL2: | |
296 | case RT5677_PWR_DSP_ST: | |
297 | case RT5677_PRIV_DATA: | |
298 | case RT5677_PLL1_CTRL2: | |
299 | case RT5677_PLL2_CTRL2: | |
300 | case RT5677_ASRC_22: | |
301 | case RT5677_ASRC_23: | |
302 | case RT5677_VAD_CTRL5: | |
303 | case RT5677_ADC_EQ_CTRL1: | |
304 | case RT5677_EQ_CTRL1: | |
305 | case RT5677_IRQ_CTRL1: | |
306 | case RT5677_IRQ_CTRL2: | |
307 | case RT5677_GPIO_ST: | |
308 | case RT5677_DSP_INB1_SRC_CTRL4: | |
309 | case RT5677_DSP_INB2_SRC_CTRL4: | |
310 | case RT5677_DSP_INB3_SRC_CTRL4: | |
311 | case RT5677_DSP_OUTB1_SRC_CTRL4: | |
312 | case RT5677_DSP_OUTB2_SRC_CTRL4: | |
313 | case RT5677_VENDOR_ID: | |
314 | case RT5677_VENDOR_ID1: | |
315 | case RT5677_VENDOR_ID2: | |
316 | return true; | |
317 | default: | |
318 | return false; | |
319 | } | |
320 | } | |
321 | ||
322 | static bool rt5677_readable_register(struct device *dev, unsigned int reg) | |
323 | { | |
324 | int i; | |
325 | ||
326 | for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { | |
327 | if (reg >= rt5677_ranges[i].range_min && | |
328 | reg <= rt5677_ranges[i].range_max) { | |
329 | return true; | |
330 | } | |
331 | } | |
332 | ||
333 | switch (reg) { | |
334 | case RT5677_RESET: | |
335 | case RT5677_LOUT1: | |
336 | case RT5677_IN1: | |
337 | case RT5677_MICBIAS: | |
338 | case RT5677_SLIMBUS_PARAM: | |
339 | case RT5677_SLIMBUS_RX: | |
340 | case RT5677_SLIMBUS_CTRL: | |
341 | case RT5677_SIDETONE_CTRL: | |
342 | case RT5677_ANA_DAC1_2_3_SRC: | |
343 | case RT5677_IF_DSP_DAC3_4_MIXER: | |
344 | case RT5677_DAC4_DIG_VOL: | |
345 | case RT5677_DAC3_DIG_VOL: | |
346 | case RT5677_DAC1_DIG_VOL: | |
347 | case RT5677_DAC2_DIG_VOL: | |
348 | case RT5677_IF_DSP_DAC2_MIXER: | |
349 | case RT5677_STO1_ADC_DIG_VOL: | |
350 | case RT5677_MONO_ADC_DIG_VOL: | |
351 | case RT5677_STO1_2_ADC_BST: | |
352 | case RT5677_STO2_ADC_DIG_VOL: | |
353 | case RT5677_ADC_BST_CTRL2: | |
354 | case RT5677_STO3_4_ADC_BST: | |
355 | case RT5677_STO3_ADC_DIG_VOL: | |
356 | case RT5677_STO4_ADC_DIG_VOL: | |
357 | case RT5677_STO4_ADC_MIXER: | |
358 | case RT5677_STO3_ADC_MIXER: | |
359 | case RT5677_STO2_ADC_MIXER: | |
360 | case RT5677_STO1_ADC_MIXER: | |
361 | case RT5677_MONO_ADC_MIXER: | |
362 | case RT5677_ADC_IF_DSP_DAC1_MIXER: | |
363 | case RT5677_STO1_DAC_MIXER: | |
364 | case RT5677_MONO_DAC_MIXER: | |
365 | case RT5677_DD1_MIXER: | |
366 | case RT5677_DD2_MIXER: | |
367 | case RT5677_IF3_DATA: | |
368 | case RT5677_IF4_DATA: | |
369 | case RT5677_PDM_OUT_CTRL: | |
370 | case RT5677_PDM_DATA_CTRL1: | |
371 | case RT5677_PDM_DATA_CTRL2: | |
372 | case RT5677_PDM1_DATA_CTRL2: | |
373 | case RT5677_PDM1_DATA_CTRL3: | |
374 | case RT5677_PDM1_DATA_CTRL4: | |
375 | case RT5677_PDM2_DATA_CTRL2: | |
376 | case RT5677_PDM2_DATA_CTRL3: | |
377 | case RT5677_PDM2_DATA_CTRL4: | |
378 | case RT5677_TDM1_CTRL1: | |
379 | case RT5677_TDM1_CTRL2: | |
380 | case RT5677_TDM1_CTRL3: | |
381 | case RT5677_TDM1_CTRL4: | |
382 | case RT5677_TDM1_CTRL5: | |
383 | case RT5677_TDM2_CTRL1: | |
384 | case RT5677_TDM2_CTRL2: | |
385 | case RT5677_TDM2_CTRL3: | |
386 | case RT5677_TDM2_CTRL4: | |
387 | case RT5677_TDM2_CTRL5: | |
388 | case RT5677_I2C_MASTER_CTRL1: | |
389 | case RT5677_I2C_MASTER_CTRL2: | |
390 | case RT5677_I2C_MASTER_CTRL3: | |
391 | case RT5677_I2C_MASTER_CTRL4: | |
392 | case RT5677_I2C_MASTER_CTRL5: | |
393 | case RT5677_I2C_MASTER_CTRL6: | |
394 | case RT5677_I2C_MASTER_CTRL7: | |
395 | case RT5677_I2C_MASTER_CTRL8: | |
396 | case RT5677_DMIC_CTRL1: | |
397 | case RT5677_DMIC_CTRL2: | |
398 | case RT5677_HAP_GENE_CTRL1: | |
399 | case RT5677_HAP_GENE_CTRL2: | |
400 | case RT5677_HAP_GENE_CTRL3: | |
401 | case RT5677_HAP_GENE_CTRL4: | |
402 | case RT5677_HAP_GENE_CTRL5: | |
403 | case RT5677_HAP_GENE_CTRL6: | |
404 | case RT5677_HAP_GENE_CTRL7: | |
405 | case RT5677_HAP_GENE_CTRL8: | |
406 | case RT5677_HAP_GENE_CTRL9: | |
407 | case RT5677_HAP_GENE_CTRL10: | |
408 | case RT5677_PWR_DIG1: | |
409 | case RT5677_PWR_DIG2: | |
410 | case RT5677_PWR_ANLG1: | |
411 | case RT5677_PWR_ANLG2: | |
412 | case RT5677_PWR_DSP1: | |
413 | case RT5677_PWR_DSP_ST: | |
414 | case RT5677_PWR_DSP2: | |
415 | case RT5677_ADC_DAC_HPF_CTRL1: | |
416 | case RT5677_PRIV_INDEX: | |
417 | case RT5677_PRIV_DATA: | |
418 | case RT5677_I2S4_SDP: | |
419 | case RT5677_I2S1_SDP: | |
420 | case RT5677_I2S2_SDP: | |
421 | case RT5677_I2S3_SDP: | |
422 | case RT5677_CLK_TREE_CTRL1: | |
423 | case RT5677_CLK_TREE_CTRL2: | |
424 | case RT5677_CLK_TREE_CTRL3: | |
425 | case RT5677_PLL1_CTRL1: | |
426 | case RT5677_PLL1_CTRL2: | |
427 | case RT5677_PLL2_CTRL1: | |
428 | case RT5677_PLL2_CTRL2: | |
429 | case RT5677_GLB_CLK1: | |
430 | case RT5677_GLB_CLK2: | |
431 | case RT5677_ASRC_1: | |
432 | case RT5677_ASRC_2: | |
433 | case RT5677_ASRC_3: | |
434 | case RT5677_ASRC_4: | |
435 | case RT5677_ASRC_5: | |
436 | case RT5677_ASRC_6: | |
437 | case RT5677_ASRC_7: | |
438 | case RT5677_ASRC_8: | |
439 | case RT5677_ASRC_9: | |
440 | case RT5677_ASRC_10: | |
441 | case RT5677_ASRC_11: | |
442 | case RT5677_ASRC_12: | |
443 | case RT5677_ASRC_13: | |
444 | case RT5677_ASRC_14: | |
445 | case RT5677_ASRC_15: | |
446 | case RT5677_ASRC_16: | |
447 | case RT5677_ASRC_17: | |
448 | case RT5677_ASRC_18: | |
449 | case RT5677_ASRC_19: | |
450 | case RT5677_ASRC_20: | |
451 | case RT5677_ASRC_21: | |
452 | case RT5677_ASRC_22: | |
453 | case RT5677_ASRC_23: | |
454 | case RT5677_VAD_CTRL1: | |
455 | case RT5677_VAD_CTRL2: | |
456 | case RT5677_VAD_CTRL3: | |
457 | case RT5677_VAD_CTRL4: | |
458 | case RT5677_VAD_CTRL5: | |
459 | case RT5677_DSP_INB_CTRL1: | |
460 | case RT5677_DSP_INB_CTRL2: | |
461 | case RT5677_DSP_IN_OUTB_CTRL: | |
462 | case RT5677_DSP_OUTB0_1_DIG_VOL: | |
463 | case RT5677_DSP_OUTB2_3_DIG_VOL: | |
464 | case RT5677_DSP_OUTB4_5_DIG_VOL: | |
465 | case RT5677_DSP_OUTB6_7_DIG_VOL: | |
466 | case RT5677_ADC_EQ_CTRL1: | |
467 | case RT5677_ADC_EQ_CTRL2: | |
468 | case RT5677_EQ_CTRL1: | |
469 | case RT5677_EQ_CTRL2: | |
470 | case RT5677_EQ_CTRL3: | |
471 | case RT5677_SOFT_VOL_ZERO_CROSS1: | |
472 | case RT5677_JD_CTRL1: | |
473 | case RT5677_JD_CTRL2: | |
474 | case RT5677_JD_CTRL3: | |
475 | case RT5677_IRQ_CTRL1: | |
476 | case RT5677_IRQ_CTRL2: | |
477 | case RT5677_GPIO_ST: | |
478 | case RT5677_GPIO_CTRL1: | |
479 | case RT5677_GPIO_CTRL2: | |
480 | case RT5677_GPIO_CTRL3: | |
481 | case RT5677_STO1_ADC_HI_FILTER1: | |
482 | case RT5677_STO1_ADC_HI_FILTER2: | |
483 | case RT5677_MONO_ADC_HI_FILTER1: | |
484 | case RT5677_MONO_ADC_HI_FILTER2: | |
485 | case RT5677_STO2_ADC_HI_FILTER1: | |
486 | case RT5677_STO2_ADC_HI_FILTER2: | |
487 | case RT5677_STO3_ADC_HI_FILTER1: | |
488 | case RT5677_STO3_ADC_HI_FILTER2: | |
489 | case RT5677_STO4_ADC_HI_FILTER1: | |
490 | case RT5677_STO4_ADC_HI_FILTER2: | |
491 | case RT5677_MB_DRC_CTRL1: | |
492 | case RT5677_DRC1_CTRL1: | |
493 | case RT5677_DRC1_CTRL2: | |
494 | case RT5677_DRC1_CTRL3: | |
495 | case RT5677_DRC1_CTRL4: | |
496 | case RT5677_DRC1_CTRL5: | |
497 | case RT5677_DRC1_CTRL6: | |
498 | case RT5677_DRC2_CTRL1: | |
499 | case RT5677_DRC2_CTRL2: | |
500 | case RT5677_DRC2_CTRL3: | |
501 | case RT5677_DRC2_CTRL4: | |
502 | case RT5677_DRC2_CTRL5: | |
503 | case RT5677_DRC2_CTRL6: | |
504 | case RT5677_DRC1_HL_CTRL1: | |
505 | case RT5677_DRC1_HL_CTRL2: | |
506 | case RT5677_DRC2_HL_CTRL1: | |
507 | case RT5677_DRC2_HL_CTRL2: | |
508 | case RT5677_DSP_INB1_SRC_CTRL1: | |
509 | case RT5677_DSP_INB1_SRC_CTRL2: | |
510 | case RT5677_DSP_INB1_SRC_CTRL3: | |
511 | case RT5677_DSP_INB1_SRC_CTRL4: | |
512 | case RT5677_DSP_INB2_SRC_CTRL1: | |
513 | case RT5677_DSP_INB2_SRC_CTRL2: | |
514 | case RT5677_DSP_INB2_SRC_CTRL3: | |
515 | case RT5677_DSP_INB2_SRC_CTRL4: | |
516 | case RT5677_DSP_INB3_SRC_CTRL1: | |
517 | case RT5677_DSP_INB3_SRC_CTRL2: | |
518 | case RT5677_DSP_INB3_SRC_CTRL3: | |
519 | case RT5677_DSP_INB3_SRC_CTRL4: | |
520 | case RT5677_DSP_OUTB1_SRC_CTRL1: | |
521 | case RT5677_DSP_OUTB1_SRC_CTRL2: | |
522 | case RT5677_DSP_OUTB1_SRC_CTRL3: | |
523 | case RT5677_DSP_OUTB1_SRC_CTRL4: | |
524 | case RT5677_DSP_OUTB2_SRC_CTRL1: | |
525 | case RT5677_DSP_OUTB2_SRC_CTRL2: | |
526 | case RT5677_DSP_OUTB2_SRC_CTRL3: | |
527 | case RT5677_DSP_OUTB2_SRC_CTRL4: | |
528 | case RT5677_DSP_OUTB_0123_MIXER_CTRL: | |
529 | case RT5677_DSP_OUTB_45_MIXER_CTRL: | |
530 | case RT5677_DSP_OUTB_67_MIXER_CTRL: | |
531 | case RT5677_DIG_MISC: | |
532 | case RT5677_GEN_CTRL1: | |
533 | case RT5677_GEN_CTRL2: | |
534 | case RT5677_VENDOR_ID: | |
535 | case RT5677_VENDOR_ID1: | |
536 | case RT5677_VENDOR_ID2: | |
537 | return true; | |
538 | default: | |
539 | return false; | |
540 | } | |
541 | } | |
542 | ||
af48f1d0 OC |
543 | /** |
544 | * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. | |
19ba484d | 545 | * @rt5677: Private Data. |
af48f1d0 OC |
546 | * @addr: Address index. |
547 | * @value: Address data. | |
548 | * | |
549 | * | |
550 | * Returns 0 for success or negative error code. | |
551 | */ | |
19ba484d | 552 | static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, |
af48f1d0 OC |
553 | unsigned int addr, unsigned int value, unsigned int opcode) |
554 | { | |
19ba484d | 555 | struct snd_soc_codec *codec = rt5677->codec; |
af48f1d0 OC |
556 | int ret; |
557 | ||
558 | mutex_lock(&rt5677->dsp_cmd_lock); | |
559 | ||
19ba484d OC |
560 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, |
561 | addr >> 16); | |
af48f1d0 OC |
562 | if (ret < 0) { |
563 | dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); | |
564 | goto err; | |
565 | } | |
566 | ||
19ba484d | 567 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, |
af48f1d0 OC |
568 | addr & 0xffff); |
569 | if (ret < 0) { | |
570 | dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); | |
571 | goto err; | |
572 | } | |
573 | ||
19ba484d | 574 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, |
af48f1d0 OC |
575 | value >> 16); |
576 | if (ret < 0) { | |
577 | dev_err(codec->dev, "Failed to set data msb value: %d\n", ret); | |
578 | goto err; | |
579 | } | |
580 | ||
19ba484d | 581 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, |
af48f1d0 OC |
582 | value & 0xffff); |
583 | if (ret < 0) { | |
584 | dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret); | |
585 | goto err; | |
586 | } | |
587 | ||
19ba484d OC |
588 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, |
589 | opcode); | |
af48f1d0 OC |
590 | if (ret < 0) { |
591 | dev_err(codec->dev, "Failed to set op code value: %d\n", ret); | |
592 | goto err; | |
593 | } | |
594 | ||
595 | err: | |
596 | mutex_unlock(&rt5677->dsp_cmd_lock); | |
597 | ||
598 | return ret; | |
599 | } | |
600 | ||
601 | /** | |
602 | * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. | |
19ba484d | 603 | * rt5677: Private Data. |
af48f1d0 OC |
604 | * @addr: Address index. |
605 | * @value: Address data. | |
606 | * | |
19ba484d | 607 | * |
af48f1d0 OC |
608 | * Returns 0 for success or negative error code. |
609 | */ | |
610 | static int rt5677_dsp_mode_i2c_read_addr( | |
19ba484d | 611 | struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) |
af48f1d0 | 612 | { |
19ba484d | 613 | struct snd_soc_codec *codec = rt5677->codec; |
af48f1d0 OC |
614 | int ret; |
615 | unsigned int msb, lsb; | |
616 | ||
617 | mutex_lock(&rt5677->dsp_cmd_lock); | |
618 | ||
19ba484d OC |
619 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, |
620 | addr >> 16); | |
af48f1d0 OC |
621 | if (ret < 0) { |
622 | dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); | |
623 | goto err; | |
624 | } | |
625 | ||
19ba484d | 626 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, |
af48f1d0 OC |
627 | addr & 0xffff); |
628 | if (ret < 0) { | |
629 | dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); | |
630 | goto err; | |
631 | } | |
632 | ||
19ba484d OC |
633 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, |
634 | 0x0002); | |
af48f1d0 OC |
635 | if (ret < 0) { |
636 | dev_err(codec->dev, "Failed to set op code value: %d\n", ret); | |
637 | goto err; | |
638 | } | |
639 | ||
19ba484d OC |
640 | regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); |
641 | regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); | |
af48f1d0 OC |
642 | *value = (msb << 16) | lsb; |
643 | ||
644 | err: | |
645 | mutex_unlock(&rt5677->dsp_cmd_lock); | |
646 | ||
647 | return ret; | |
648 | } | |
649 | ||
650 | /** | |
651 | * rt5677_dsp_mode_i2c_write - Write register on DSP mode. | |
19ba484d | 652 | * rt5677: Private Data. |
af48f1d0 OC |
653 | * @reg: Register index. |
654 | * @value: Register data. | |
655 | * | |
656 | * | |
657 | * Returns 0 for success or negative error code. | |
658 | */ | |
19ba484d | 659 | static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, |
af48f1d0 OC |
660 | unsigned int reg, unsigned int value) |
661 | { | |
19ba484d | 662 | return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, |
af48f1d0 OC |
663 | value, 0x0001); |
664 | } | |
665 | ||
666 | /** | |
667 | * rt5677_dsp_mode_i2c_read - Read register on DSP mode. | |
668 | * @codec: SoC audio codec device. | |
669 | * @reg: Register index. | |
19ba484d | 670 | * @value: Register data. |
af48f1d0 OC |
671 | * |
672 | * | |
19ba484d | 673 | * Returns 0 for success or negative error code. |
af48f1d0 | 674 | */ |
19ba484d OC |
675 | static int rt5677_dsp_mode_i2c_read( |
676 | struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) | |
af48f1d0 | 677 | { |
19ba484d OC |
678 | int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, |
679 | value); | |
af48f1d0 | 680 | |
19ba484d | 681 | *value &= 0xffff; |
af48f1d0 | 682 | |
19ba484d | 683 | return ret; |
af48f1d0 OC |
684 | } |
685 | ||
19ba484d | 686 | static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on) |
af48f1d0 | 687 | { |
19ba484d | 688 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
af48f1d0 | 689 | |
19ba484d OC |
690 | if (on) { |
691 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2); | |
692 | rt5677->is_dsp_mode = true; | |
693 | } else { | |
694 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0); | |
695 | rt5677->is_dsp_mode = false; | |
af48f1d0 | 696 | } |
af48f1d0 OC |
697 | } |
698 | ||
699 | static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on) | |
700 | { | |
701 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
702 | static bool activity; | |
703 | int ret; | |
704 | ||
705 | if (on && !activity) { | |
706 | activity = true; | |
707 | ||
708 | regcache_cache_only(rt5677->regmap, false); | |
709 | regcache_cache_bypass(rt5677->regmap, true); | |
710 | ||
711 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1); | |
712 | regmap_update_bits(rt5677->regmap, | |
713 | RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00); | |
714 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, | |
715 | RT5677_LDO1_SEL_MASK, 0x0); | |
716 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, | |
717 | RT5677_PWR_LDO1, RT5677_PWR_LDO1); | |
19ba484d OC |
718 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
719 | RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC); | |
720 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, | |
721 | RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK, | |
722 | RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS); | |
af48f1d0 | 723 | regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff); |
19ba484d OC |
724 | regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd); |
725 | rt5677_set_dsp_mode(codec, true); | |
af48f1d0 OC |
726 | |
727 | ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1, | |
728 | codec->dev); | |
729 | if (ret == 0) { | |
730 | rt5677_spi_burst_write(0x50000000, rt5677->fw1); | |
731 | release_firmware(rt5677->fw1); | |
732 | } | |
733 | ||
734 | ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2, | |
735 | codec->dev); | |
736 | if (ret == 0) { | |
737 | rt5677_spi_burst_write(0x60000000, rt5677->fw2); | |
738 | release_firmware(rt5677->fw2); | |
739 | } | |
740 | ||
19ba484d | 741 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0); |
af48f1d0 OC |
742 | |
743 | regcache_cache_bypass(rt5677->regmap, false); | |
744 | regcache_cache_only(rt5677->regmap, true); | |
745 | } else if (!on && activity) { | |
746 | activity = false; | |
747 | ||
748 | regcache_cache_only(rt5677->regmap, false); | |
749 | regcache_cache_bypass(rt5677->regmap, true); | |
750 | ||
19ba484d OC |
751 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1); |
752 | rt5677_set_dsp_mode(codec, false); | |
753 | regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001); | |
af48f1d0 OC |
754 | |
755 | regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); | |
756 | ||
757 | regcache_cache_bypass(rt5677->regmap, false); | |
758 | regcache_mark_dirty(rt5677->regmap); | |
759 | regcache_sync(rt5677->regmap); | |
760 | } | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
0e826e86 OC |
765 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); |
766 | static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); | |
767 | static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); | |
768 | static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); | |
769 | static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); | |
90bdbb46 | 770 | static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); |
0e826e86 OC |
771 | |
772 | /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ | |
773 | static unsigned int bst_tlv[] = { | |
774 | TLV_DB_RANGE_HEAD(7), | |
775 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), | |
776 | 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), | |
777 | 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), | |
778 | 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), | |
779 | 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), | |
780 | 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), | |
781 | 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0), | |
782 | }; | |
783 | ||
af48f1d0 OC |
784 | static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, |
785 | struct snd_ctl_elem_value *ucontrol) | |
786 | { | |
787 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
788 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
789 | ||
790 | ucontrol->value.integer.value[0] = rt5677->dsp_vad_en; | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
795 | static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, | |
796 | struct snd_ctl_elem_value *ucontrol) | |
797 | { | |
798 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
799 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
800 | ||
801 | rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0]; | |
802 | ||
803 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) | |
804 | rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
0e826e86 OC |
809 | static const struct snd_kcontrol_new rt5677_snd_controls[] = { |
810 | /* OUTPUT Control */ | |
811 | SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, | |
812 | RT5677_LOUT1_L_MUTE_SFT, 1, 1), | |
813 | SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, | |
814 | RT5677_LOUT2_L_MUTE_SFT, 1, 1), | |
815 | SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, | |
816 | RT5677_LOUT3_L_MUTE_SFT, 1, 1), | |
817 | ||
818 | /* DAC Digital Volume */ | |
819 | SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, | |
820 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), | |
821 | SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, | |
822 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), | |
823 | SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, | |
824 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), | |
825 | SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, | |
826 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), | |
827 | ||
828 | /* IN1/IN2 Control */ | |
829 | SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), | |
830 | SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), | |
831 | ||
832 | /* ADC Digital Volume Control */ | |
833 | SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, | |
834 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), | |
835 | SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, | |
836 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), | |
837 | SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, | |
838 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), | |
839 | SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, | |
840 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), | |
841 | SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, | |
842 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), | |
843 | ||
844 | SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, | |
845 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, | |
846 | adc_vol_tlv), | |
847 | SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, | |
848 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, | |
849 | adc_vol_tlv), | |
850 | SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, | |
851 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, | |
852 | adc_vol_tlv), | |
853 | SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, | |
854 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, | |
855 | adc_vol_tlv), | |
856 | SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, | |
857 | RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0, | |
858 | adc_vol_tlv), | |
859 | ||
90bdbb46 OC |
860 | /* Sidetone Control */ |
861 | SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, | |
862 | RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), | |
863 | ||
0e826e86 | 864 | /* ADC Boost Volume Control */ |
80220f29 | 865 | SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, |
0e826e86 OC |
866 | RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, |
867 | adc_bst_tlv), | |
80220f29 | 868 | SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, |
0e826e86 OC |
869 | RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, |
870 | adc_bst_tlv), | |
80220f29 | 871 | SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, |
0e826e86 OC |
872 | RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, |
873 | adc_bst_tlv), | |
80220f29 | 874 | SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, |
0e826e86 OC |
875 | RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, |
876 | adc_bst_tlv), | |
80220f29 | 877 | SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, |
0e826e86 OC |
878 | RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, |
879 | adc_bst_tlv), | |
af48f1d0 OC |
880 | |
881 | SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, | |
882 | rt5677_dsp_vad_get, rt5677_dsp_vad_put), | |
0e826e86 OC |
883 | }; |
884 | ||
885 | /** | |
886 | * set_dmic_clk - Set parameter of dmic. | |
887 | * | |
888 | * @w: DAPM widget. | |
889 | * @kcontrol: The kcontrol of this widget. | |
890 | * @event: Event id. | |
891 | * | |
892 | * Choose dmic clock between 1MHz and 3MHz. | |
893 | * It is better for clock to approximate 3MHz. | |
894 | */ | |
895 | static int set_dmic_clk(struct snd_soc_dapm_widget *w, | |
896 | struct snd_kcontrol *kcontrol, int event) | |
897 | { | |
898 | struct snd_soc_codec *codec = w->codec; | |
899 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
9a53581e | 900 | int idx = rl6231_calc_dmic_clk(rt5677->sysclk); |
0e826e86 OC |
901 | |
902 | if (idx < 0) | |
903 | dev_err(codec->dev, "Failed to set DMIC clock\n"); | |
904 | else | |
905 | regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, | |
906 | RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); | |
907 | return idx; | |
908 | } | |
909 | ||
910 | static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, | |
911 | struct snd_soc_dapm_widget *sink) | |
912 | { | |
913 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec); | |
914 | unsigned int val; | |
915 | ||
916 | regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); | |
917 | val &= RT5677_SCLK_SRC_MASK; | |
918 | if (val == RT5677_SCLK_SRC_PLL1) | |
919 | return 1; | |
920 | else | |
921 | return 0; | |
922 | } | |
923 | ||
924 | /* Digital Mixer */ | |
925 | static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { | |
926 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, | |
927 | RT5677_M_STO1_ADC_L1_SFT, 1, 1), | |
928 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, | |
929 | RT5677_M_STO1_ADC_L2_SFT, 1, 1), | |
930 | }; | |
931 | ||
932 | static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { | |
933 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, | |
934 | RT5677_M_STO1_ADC_R1_SFT, 1, 1), | |
935 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, | |
936 | RT5677_M_STO1_ADC_R2_SFT, 1, 1), | |
937 | }; | |
938 | ||
939 | static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { | |
940 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, | |
941 | RT5677_M_STO2_ADC_L1_SFT, 1, 1), | |
942 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, | |
943 | RT5677_M_STO2_ADC_L2_SFT, 1, 1), | |
944 | }; | |
945 | ||
946 | static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { | |
947 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, | |
948 | RT5677_M_STO2_ADC_R1_SFT, 1, 1), | |
949 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, | |
950 | RT5677_M_STO2_ADC_R2_SFT, 1, 1), | |
951 | }; | |
952 | ||
953 | static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { | |
954 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, | |
955 | RT5677_M_STO3_ADC_L1_SFT, 1, 1), | |
956 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, | |
957 | RT5677_M_STO3_ADC_L2_SFT, 1, 1), | |
958 | }; | |
959 | ||
960 | static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { | |
961 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, | |
962 | RT5677_M_STO3_ADC_R1_SFT, 1, 1), | |
963 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, | |
964 | RT5677_M_STO3_ADC_R2_SFT, 1, 1), | |
965 | }; | |
966 | ||
967 | static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { | |
968 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, | |
969 | RT5677_M_STO4_ADC_L1_SFT, 1, 1), | |
970 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, | |
971 | RT5677_M_STO4_ADC_L2_SFT, 1, 1), | |
972 | }; | |
973 | ||
974 | static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { | |
975 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, | |
976 | RT5677_M_STO4_ADC_R1_SFT, 1, 1), | |
977 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, | |
978 | RT5677_M_STO4_ADC_R2_SFT, 1, 1), | |
979 | }; | |
980 | ||
981 | static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { | |
982 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, | |
983 | RT5677_M_MONO_ADC_L1_SFT, 1, 1), | |
984 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, | |
985 | RT5677_M_MONO_ADC_L2_SFT, 1, 1), | |
986 | }; | |
987 | ||
988 | static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { | |
989 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, | |
990 | RT5677_M_MONO_ADC_R1_SFT, 1, 1), | |
991 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, | |
992 | RT5677_M_MONO_ADC_R2_SFT, 1, 1), | |
993 | }; | |
994 | ||
995 | static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { | |
996 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, | |
997 | RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), | |
998 | SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, | |
999 | RT5677_M_DAC1_L_SFT, 1, 1), | |
1000 | }; | |
1001 | ||
1002 | static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { | |
1003 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, | |
1004 | RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), | |
1005 | SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, | |
1006 | RT5677_M_DAC1_R_SFT, 1, 1), | |
1007 | }; | |
1008 | ||
1009 | static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { | |
1010 | SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER, | |
1011 | RT5677_M_ST_DAC1_L_SFT, 1, 1), | |
1012 | SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, | |
1013 | RT5677_M_DAC1_L_STO_L_SFT, 1, 1), | |
1014 | SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, | |
1015 | RT5677_M_DAC2_L_STO_L_SFT, 1, 1), | |
1016 | SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, | |
1017 | RT5677_M_DAC1_R_STO_L_SFT, 1, 1), | |
1018 | }; | |
1019 | ||
1020 | static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { | |
1021 | SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER, | |
1022 | RT5677_M_ST_DAC1_R_SFT, 1, 1), | |
1023 | SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, | |
1024 | RT5677_M_DAC1_R_STO_R_SFT, 1, 1), | |
1025 | SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, | |
1026 | RT5677_M_DAC2_R_STO_R_SFT, 1, 1), | |
1027 | SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, | |
1028 | RT5677_M_DAC1_L_STO_R_SFT, 1, 1), | |
1029 | }; | |
1030 | ||
1031 | static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { | |
1032 | SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER, | |
1033 | RT5677_M_ST_DAC2_L_SFT, 1, 1), | |
1034 | SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, | |
1035 | RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), | |
1036 | SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, | |
1037 | RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), | |
1038 | SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, | |
1039 | RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), | |
1040 | }; | |
1041 | ||
1042 | static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { | |
1043 | SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER, | |
1044 | RT5677_M_ST_DAC2_R_SFT, 1, 1), | |
1045 | SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, | |
1046 | RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), | |
1047 | SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, | |
1048 | RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), | |
1049 | SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, | |
1050 | RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), | |
1051 | }; | |
1052 | ||
1053 | static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { | |
1054 | SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, | |
1055 | RT5677_M_STO_L_DD1_L_SFT, 1, 1), | |
1056 | SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, | |
1057 | RT5677_M_MONO_L_DD1_L_SFT, 1, 1), | |
1058 | SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, | |
1059 | RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), | |
1060 | SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, | |
1061 | RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), | |
1062 | }; | |
1063 | ||
1064 | static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { | |
1065 | SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, | |
1066 | RT5677_M_STO_R_DD1_R_SFT, 1, 1), | |
1067 | SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, | |
1068 | RT5677_M_MONO_R_DD1_R_SFT, 1, 1), | |
1069 | SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, | |
1070 | RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), | |
1071 | SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, | |
1072 | RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), | |
1073 | }; | |
1074 | ||
1075 | static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { | |
1076 | SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, | |
1077 | RT5677_M_STO_L_DD2_L_SFT, 1, 1), | |
1078 | SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, | |
1079 | RT5677_M_MONO_L_DD2_L_SFT, 1, 1), | |
1080 | SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, | |
1081 | RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), | |
1082 | SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, | |
1083 | RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), | |
1084 | }; | |
1085 | ||
1086 | static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { | |
1087 | SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, | |
1088 | RT5677_M_STO_R_DD2_R_SFT, 1, 1), | |
1089 | SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, | |
1090 | RT5677_M_MONO_R_DD2_R_SFT, 1, 1), | |
1091 | SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, | |
1092 | RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), | |
1093 | SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, | |
1094 | RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), | |
1095 | }; | |
1096 | ||
1097 | static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { | |
1098 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1099 | RT5677_DSP_IB_01_H_SFT, 1, 1), | |
1100 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1101 | RT5677_DSP_IB_23_H_SFT, 1, 1), | |
1102 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1103 | RT5677_DSP_IB_45_H_SFT, 1, 1), | |
1104 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1105 | RT5677_DSP_IB_6_H_SFT, 1, 1), | |
1106 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1107 | RT5677_DSP_IB_7_H_SFT, 1, 1), | |
1108 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1109 | RT5677_DSP_IB_8_H_SFT, 1, 1), | |
1110 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1111 | RT5677_DSP_IB_9_H_SFT, 1, 1), | |
1112 | }; | |
1113 | ||
1114 | static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { | |
1115 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1116 | RT5677_DSP_IB_01_L_SFT, 1, 1), | |
1117 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1118 | RT5677_DSP_IB_23_L_SFT, 1, 1), | |
1119 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1120 | RT5677_DSP_IB_45_L_SFT, 1, 1), | |
1121 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1122 | RT5677_DSP_IB_6_L_SFT, 1, 1), | |
1123 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1124 | RT5677_DSP_IB_7_L_SFT, 1, 1), | |
1125 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1126 | RT5677_DSP_IB_8_L_SFT, 1, 1), | |
1127 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, | |
1128 | RT5677_DSP_IB_9_L_SFT, 1, 1), | |
1129 | }; | |
1130 | ||
1131 | static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { | |
1132 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1133 | RT5677_DSP_IB_01_H_SFT, 1, 1), | |
1134 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1135 | RT5677_DSP_IB_23_H_SFT, 1, 1), | |
1136 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1137 | RT5677_DSP_IB_45_H_SFT, 1, 1), | |
1138 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1139 | RT5677_DSP_IB_6_H_SFT, 1, 1), | |
1140 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1141 | RT5677_DSP_IB_7_H_SFT, 1, 1), | |
1142 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1143 | RT5677_DSP_IB_8_H_SFT, 1, 1), | |
1144 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1145 | RT5677_DSP_IB_9_H_SFT, 1, 1), | |
1146 | }; | |
1147 | ||
1148 | static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { | |
1149 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1150 | RT5677_DSP_IB_01_L_SFT, 1, 1), | |
1151 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1152 | RT5677_DSP_IB_23_L_SFT, 1, 1), | |
1153 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1154 | RT5677_DSP_IB_45_L_SFT, 1, 1), | |
1155 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1156 | RT5677_DSP_IB_6_L_SFT, 1, 1), | |
1157 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1158 | RT5677_DSP_IB_7_L_SFT, 1, 1), | |
1159 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1160 | RT5677_DSP_IB_8_L_SFT, 1, 1), | |
1161 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, | |
1162 | RT5677_DSP_IB_9_L_SFT, 1, 1), | |
1163 | }; | |
1164 | ||
1165 | static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { | |
1166 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1167 | RT5677_DSP_IB_01_H_SFT, 1, 1), | |
1168 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1169 | RT5677_DSP_IB_23_H_SFT, 1, 1), | |
1170 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1171 | RT5677_DSP_IB_45_H_SFT, 1, 1), | |
1172 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1173 | RT5677_DSP_IB_6_H_SFT, 1, 1), | |
1174 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1175 | RT5677_DSP_IB_7_H_SFT, 1, 1), | |
1176 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1177 | RT5677_DSP_IB_8_H_SFT, 1, 1), | |
1178 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1179 | RT5677_DSP_IB_9_H_SFT, 1, 1), | |
1180 | }; | |
1181 | ||
1182 | static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { | |
1183 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1184 | RT5677_DSP_IB_01_L_SFT, 1, 1), | |
1185 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1186 | RT5677_DSP_IB_23_L_SFT, 1, 1), | |
1187 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1188 | RT5677_DSP_IB_45_L_SFT, 1, 1), | |
1189 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1190 | RT5677_DSP_IB_6_L_SFT, 1, 1), | |
1191 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1192 | RT5677_DSP_IB_7_L_SFT, 1, 1), | |
1193 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1194 | RT5677_DSP_IB_8_L_SFT, 1, 1), | |
1195 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, | |
1196 | RT5677_DSP_IB_9_L_SFT, 1, 1), | |
1197 | }; | |
1198 | ||
1199 | ||
1200 | /* Mux */ | |
1b7fd76a | 1201 | /* DAC1 L/R Source */ /* MX-29 [10:8] */ |
0e826e86 OC |
1202 | static const char * const rt5677_dac1_src[] = { |
1203 | "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", | |
1204 | "OB 01" | |
1205 | }; | |
1206 | ||
1207 | static SOC_ENUM_SINGLE_DECL( | |
1208 | rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, | |
1209 | RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); | |
1210 | ||
1211 | static const struct snd_kcontrol_new rt5677_dac1_mux = | |
1b7fd76a | 1212 | SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); |
0e826e86 | 1213 | |
1b7fd76a | 1214 | /* ADDA1 L/R Source */ /* MX-29 [1:0] */ |
0e826e86 OC |
1215 | static const char * const rt5677_adda1_src[] = { |
1216 | "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", | |
1217 | }; | |
1218 | ||
1219 | static SOC_ENUM_SINGLE_DECL( | |
1220 | rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, | |
1221 | RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); | |
1222 | ||
1223 | static const struct snd_kcontrol_new rt5677_adda1_mux = | |
1b7fd76a | 1224 | SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); |
0e826e86 OC |
1225 | |
1226 | ||
1b7fd76a | 1227 | /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ |
0e826e86 OC |
1228 | static const char * const rt5677_dac2l_src[] = { |
1229 | "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", | |
1230 | "OB 2", | |
1231 | }; | |
1232 | ||
1233 | static SOC_ENUM_SINGLE_DECL( | |
1234 | rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, | |
1235 | RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); | |
1236 | ||
1237 | static const struct snd_kcontrol_new rt5677_dac2_l_mux = | |
1b7fd76a | 1238 | SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); |
0e826e86 OC |
1239 | |
1240 | static const char * const rt5677_dac2r_src[] = { | |
1241 | "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", | |
1242 | "OB 3", "Haptic Generator", "VAD ADC" | |
1243 | }; | |
1244 | ||
1245 | static SOC_ENUM_SINGLE_DECL( | |
1246 | rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, | |
1247 | RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); | |
1248 | ||
1249 | static const struct snd_kcontrol_new rt5677_dac2_r_mux = | |
1b7fd76a | 1250 | SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); |
0e826e86 | 1251 | |
1b7fd76a | 1252 | /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ |
0e826e86 OC |
1253 | static const char * const rt5677_dac3l_src[] = { |
1254 | "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", | |
1255 | "SLB DAC 4", "OB 4" | |
1256 | }; | |
1257 | ||
1258 | static SOC_ENUM_SINGLE_DECL( | |
1259 | rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, | |
1260 | RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); | |
1261 | ||
1262 | static const struct snd_kcontrol_new rt5677_dac3_l_mux = | |
1b7fd76a | 1263 | SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); |
0e826e86 OC |
1264 | |
1265 | static const char * const rt5677_dac3r_src[] = { | |
1266 | "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", | |
1267 | "SLB DAC 5", "OB 5" | |
1268 | }; | |
1269 | ||
1270 | static SOC_ENUM_SINGLE_DECL( | |
1271 | rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, | |
1272 | RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); | |
1273 | ||
1274 | static const struct snd_kcontrol_new rt5677_dac3_r_mux = | |
1b7fd76a | 1275 | SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); |
0e826e86 | 1276 | |
1b7fd76a | 1277 | /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ |
0e826e86 OC |
1278 | static const char * const rt5677_dac4l_src[] = { |
1279 | "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", | |
1280 | "SLB DAC 6", "OB 6" | |
1281 | }; | |
1282 | ||
1283 | static SOC_ENUM_SINGLE_DECL( | |
1284 | rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, | |
1285 | RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); | |
1286 | ||
1287 | static const struct snd_kcontrol_new rt5677_dac4_l_mux = | |
1b7fd76a | 1288 | SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); |
0e826e86 OC |
1289 | |
1290 | static const char * const rt5677_dac4r_src[] = { | |
1291 | "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", | |
1292 | "SLB DAC 7", "OB 7" | |
1293 | }; | |
1294 | ||
1295 | static SOC_ENUM_SINGLE_DECL( | |
1296 | rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, | |
1297 | RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); | |
1298 | ||
1299 | static const struct snd_kcontrol_new rt5677_dac4_r_mux = | |
1b7fd76a | 1300 | SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); |
0e826e86 OC |
1301 | |
1302 | /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ | |
1303 | static const char * const rt5677_iob_bypass_src[] = { | |
1304 | "Bypass", "Pass SRC" | |
1305 | }; | |
1306 | ||
1307 | static SOC_ENUM_SINGLE_DECL( | |
1308 | rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, | |
1309 | RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); | |
1310 | ||
1311 | static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = | |
1b7fd76a | 1312 | SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); |
0e826e86 OC |
1313 | |
1314 | static SOC_ENUM_SINGLE_DECL( | |
1315 | rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, | |
1316 | RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); | |
1317 | ||
1318 | static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = | |
1b7fd76a | 1319 | SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); |
0e826e86 OC |
1320 | |
1321 | static SOC_ENUM_SINGLE_DECL( | |
1322 | rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, | |
1323 | RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); | |
1324 | ||
1325 | static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = | |
1b7fd76a | 1326 | SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); |
0e826e86 OC |
1327 | |
1328 | static SOC_ENUM_SINGLE_DECL( | |
1329 | rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, | |
1330 | RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); | |
1331 | ||
1332 | static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = | |
1b7fd76a | 1333 | SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); |
0e826e86 OC |
1334 | |
1335 | static SOC_ENUM_SINGLE_DECL( | |
1336 | rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, | |
1337 | RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); | |
1338 | ||
1339 | static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = | |
1b7fd76a | 1340 | SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); |
0e826e86 | 1341 | |
d65fd3a4 | 1342 | /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ |
0e826e86 OC |
1343 | static const char * const rt5677_stereo_adc2_src[] = { |
1344 | "DD MIX1", "DMIC", "Stereo DAC MIX" | |
1345 | }; | |
1346 | ||
1347 | static SOC_ENUM_SINGLE_DECL( | |
1348 | rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, | |
1349 | RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); | |
1350 | ||
1351 | static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = | |
1b7fd76a | 1352 | SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); |
0e826e86 OC |
1353 | |
1354 | static SOC_ENUM_SINGLE_DECL( | |
1355 | rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, | |
1356 | RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); | |
1357 | ||
1358 | static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = | |
1b7fd76a | 1359 | SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); |
0e826e86 OC |
1360 | |
1361 | static SOC_ENUM_SINGLE_DECL( | |
1362 | rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, | |
1363 | RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); | |
1364 | ||
1365 | static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = | |
1b7fd76a | 1366 | SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); |
0e826e86 OC |
1367 | |
1368 | /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ | |
1369 | static const char * const rt5677_dmic_src[] = { | |
1370 | "DMIC1", "DMIC2", "DMIC3", "DMIC4" | |
1371 | }; | |
1372 | ||
1373 | static SOC_ENUM_SINGLE_DECL( | |
1374 | rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, | |
1375 | RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); | |
1376 | ||
1377 | static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = | |
1b7fd76a | 1378 | SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); |
0e826e86 OC |
1379 | |
1380 | static SOC_ENUM_SINGLE_DECL( | |
1381 | rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, | |
1382 | RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); | |
1383 | ||
1384 | static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = | |
1b7fd76a | 1385 | SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); |
0e826e86 OC |
1386 | |
1387 | static SOC_ENUM_SINGLE_DECL( | |
1388 | rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, | |
1389 | RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); | |
1390 | ||
1391 | static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = | |
1b7fd76a | 1392 | SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); |
0e826e86 OC |
1393 | |
1394 | static SOC_ENUM_SINGLE_DECL( | |
1395 | rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, | |
1396 | RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); | |
1397 | ||
1398 | static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = | |
1b7fd76a | 1399 | SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); |
0e826e86 OC |
1400 | |
1401 | static SOC_ENUM_SINGLE_DECL( | |
1402 | rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, | |
1403 | RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); | |
1404 | ||
1405 | static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = | |
1b7fd76a | 1406 | SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); |
0e826e86 OC |
1407 | |
1408 | static SOC_ENUM_SINGLE_DECL( | |
1409 | rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, | |
1410 | RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); | |
1411 | ||
1412 | static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = | |
1b7fd76a | 1413 | SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); |
0e826e86 | 1414 | |
1b7fd76a | 1415 | /* Stereo2 ADC Source */ /* MX-26 [0] */ |
0e826e86 OC |
1416 | static const char * const rt5677_stereo2_adc_lr_src[] = { |
1417 | "L", "LR" | |
1418 | }; | |
1419 | ||
1420 | static SOC_ENUM_SINGLE_DECL( | |
1421 | rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, | |
1422 | RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); | |
1423 | ||
1424 | static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = | |
1b7fd76a | 1425 | SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); |
0e826e86 | 1426 | |
d65fd3a4 | 1427 | /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ |
0e826e86 OC |
1428 | static const char * const rt5677_stereo_adc1_src[] = { |
1429 | "DD MIX1", "ADC1/2", "Stereo DAC MIX" | |
1430 | }; | |
1431 | ||
1432 | static SOC_ENUM_SINGLE_DECL( | |
1433 | rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, | |
1434 | RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); | |
1435 | ||
1436 | static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = | |
1b7fd76a | 1437 | SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); |
0e826e86 OC |
1438 | |
1439 | static SOC_ENUM_SINGLE_DECL( | |
1440 | rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, | |
1441 | RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); | |
1442 | ||
1443 | static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = | |
1b7fd76a | 1444 | SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); |
0e826e86 OC |
1445 | |
1446 | static SOC_ENUM_SINGLE_DECL( | |
1447 | rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, | |
1448 | RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); | |
1449 | ||
1450 | static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = | |
1b7fd76a | 1451 | SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); |
0e826e86 | 1452 | |
1b7fd76a | 1453 | /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ |
0e826e86 OC |
1454 | static const char * const rt5677_mono_adc2_l_src[] = { |
1455 | "DD MIX1L", "DMIC", "MONO DAC MIXL" | |
1456 | }; | |
1457 | ||
1458 | static SOC_ENUM_SINGLE_DECL( | |
1459 | rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, | |
1460 | RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); | |
1461 | ||
1462 | static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = | |
1b7fd76a | 1463 | SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); |
0e826e86 | 1464 | |
1b7fd76a | 1465 | /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ |
0e826e86 OC |
1466 | static const char * const rt5677_mono_adc1_l_src[] = { |
1467 | "DD MIX1L", "ADC1", "MONO DAC MIXL" | |
1468 | }; | |
1469 | ||
1470 | static SOC_ENUM_SINGLE_DECL( | |
1471 | rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, | |
1472 | RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); | |
1473 | ||
1474 | static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = | |
1b7fd76a | 1475 | SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); |
0e826e86 | 1476 | |
1b7fd76a | 1477 | /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ |
0e826e86 OC |
1478 | static const char * const rt5677_mono_adc2_r_src[] = { |
1479 | "DD MIX1R", "DMIC", "MONO DAC MIXR" | |
1480 | }; | |
1481 | ||
1482 | static SOC_ENUM_SINGLE_DECL( | |
1483 | rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, | |
1484 | RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); | |
1485 | ||
1486 | static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = | |
1b7fd76a | 1487 | SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); |
0e826e86 | 1488 | |
1b7fd76a | 1489 | /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ |
0e826e86 OC |
1490 | static const char * const rt5677_mono_adc1_r_src[] = { |
1491 | "DD MIX1R", "ADC2", "MONO DAC MIXR" | |
1492 | }; | |
1493 | ||
1494 | static SOC_ENUM_SINGLE_DECL( | |
1495 | rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, | |
1496 | RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); | |
1497 | ||
1498 | static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = | |
1b7fd76a | 1499 | SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); |
0e826e86 OC |
1500 | |
1501 | /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ | |
1502 | static const char * const rt5677_stereo4_adc2_src[] = { | |
1503 | "DD MIX1", "DMIC", "DD MIX2" | |
1504 | }; | |
1505 | ||
1506 | static SOC_ENUM_SINGLE_DECL( | |
1507 | rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, | |
1508 | RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); | |
1509 | ||
1510 | static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = | |
1b7fd76a | 1511 | SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); |
0e826e86 OC |
1512 | |
1513 | ||
1514 | /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ | |
1515 | static const char * const rt5677_stereo4_adc1_src[] = { | |
1516 | "DD MIX1", "ADC1/2", "DD MIX2" | |
1517 | }; | |
1518 | ||
1519 | static SOC_ENUM_SINGLE_DECL( | |
1520 | rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, | |
1521 | RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); | |
1522 | ||
1523 | static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = | |
1b7fd76a | 1524 | SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); |
0e826e86 OC |
1525 | |
1526 | /* InBound0/1 Source */ /* MX-A3 [14:12] */ | |
1527 | static const char * const rt5677_inbound01_src[] = { | |
1528 | "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", | |
1529 | "VAD ADC/DAC1 FS" | |
1530 | }; | |
1531 | ||
1532 | static SOC_ENUM_SINGLE_DECL( | |
1533 | rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, | |
1534 | RT5677_IB01_SRC_SFT, rt5677_inbound01_src); | |
1535 | ||
1536 | static const struct snd_kcontrol_new rt5677_ib01_src_mux = | |
1537 | SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); | |
1538 | ||
1539 | /* InBound2/3 Source */ /* MX-A3 [10:8] */ | |
1540 | static const char * const rt5677_inbound23_src[] = { | |
1541 | "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", | |
1542 | "DAC1 FS", "IF4 DAC" | |
1543 | }; | |
1544 | ||
1545 | static SOC_ENUM_SINGLE_DECL( | |
1546 | rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, | |
1547 | RT5677_IB23_SRC_SFT, rt5677_inbound23_src); | |
1548 | ||
1549 | static const struct snd_kcontrol_new rt5677_ib23_src_mux = | |
1550 | SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); | |
1551 | ||
1552 | /* InBound4/5 Source */ /* MX-A3 [6:4] */ | |
1553 | static const char * const rt5677_inbound45_src[] = { | |
1554 | "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", | |
1555 | "IF3 DAC" | |
1556 | }; | |
1557 | ||
1558 | static SOC_ENUM_SINGLE_DECL( | |
1559 | rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, | |
1560 | RT5677_IB45_SRC_SFT, rt5677_inbound45_src); | |
1561 | ||
1562 | static const struct snd_kcontrol_new rt5677_ib45_src_mux = | |
1563 | SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); | |
1564 | ||
1565 | /* InBound6 Source */ /* MX-A3 [2:0] */ | |
1566 | static const char * const rt5677_inbound6_src[] = { | |
1567 | "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", | |
1568 | "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" | |
1569 | }; | |
1570 | ||
1571 | static SOC_ENUM_SINGLE_DECL( | |
1572 | rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, | |
1573 | RT5677_IB6_SRC_SFT, rt5677_inbound6_src); | |
1574 | ||
1575 | static const struct snd_kcontrol_new rt5677_ib6_src_mux = | |
1576 | SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); | |
1577 | ||
1578 | /* InBound7 Source */ /* MX-A4 [14:12] */ | |
1579 | static const char * const rt5677_inbound7_src[] = { | |
1580 | "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", | |
1581 | "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" | |
1582 | }; | |
1583 | ||
1584 | static SOC_ENUM_SINGLE_DECL( | |
1585 | rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, | |
1586 | RT5677_IB7_SRC_SFT, rt5677_inbound7_src); | |
1587 | ||
1588 | static const struct snd_kcontrol_new rt5677_ib7_src_mux = | |
1589 | SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); | |
1590 | ||
1591 | /* InBound8 Source */ /* MX-A4 [10:8] */ | |
1592 | static const char * const rt5677_inbound8_src[] = { | |
1593 | "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", | |
1594 | "MONO ADC MIX L", "DACL1 FS" | |
1595 | }; | |
1596 | ||
1597 | static SOC_ENUM_SINGLE_DECL( | |
1598 | rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, | |
1599 | RT5677_IB8_SRC_SFT, rt5677_inbound8_src); | |
1600 | ||
1601 | static const struct snd_kcontrol_new rt5677_ib8_src_mux = | |
1602 | SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); | |
1603 | ||
1604 | /* InBound9 Source */ /* MX-A4 [6:4] */ | |
1605 | static const char * const rt5677_inbound9_src[] = { | |
1606 | "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", | |
1607 | "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" | |
1608 | }; | |
1609 | ||
1610 | static SOC_ENUM_SINGLE_DECL( | |
1611 | rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, | |
1612 | RT5677_IB9_SRC_SFT, rt5677_inbound9_src); | |
1613 | ||
1614 | static const struct snd_kcontrol_new rt5677_ib9_src_mux = | |
1615 | SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); | |
1616 | ||
1617 | /* VAD Source */ /* MX-9F [6:4] */ | |
1618 | static const char * const rt5677_vad_src[] = { | |
1619 | "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", | |
1620 | "STO3 ADC MIX L" | |
1621 | }; | |
1622 | ||
1623 | static SOC_ENUM_SINGLE_DECL( | |
1624 | rt5677_vad_enum, RT5677_VAD_CTRL4, | |
1625 | RT5677_VAD_SRC_SFT, rt5677_vad_src); | |
1626 | ||
1627 | static const struct snd_kcontrol_new rt5677_vad_src_mux = | |
1628 | SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); | |
1629 | ||
1630 | /* Sidetone Source */ /* MX-13 [11:9] */ | |
1631 | static const char * const rt5677_sidetone_src[] = { | |
1632 | "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" | |
1633 | }; | |
1634 | ||
1635 | static SOC_ENUM_SINGLE_DECL( | |
1636 | rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, | |
1637 | RT5677_ST_SEL_SFT, rt5677_sidetone_src); | |
1638 | ||
1639 | static const struct snd_kcontrol_new rt5677_sidetone_mux = | |
1640 | SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); | |
1641 | ||
1642 | /* DAC1/2 Source */ /* MX-15 [1:0] */ | |
1643 | static const char * const rt5677_dac12_src[] = { | |
1644 | "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" | |
1645 | }; | |
1646 | ||
1647 | static SOC_ENUM_SINGLE_DECL( | |
1648 | rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, | |
1649 | RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); | |
1650 | ||
1651 | static const struct snd_kcontrol_new rt5677_dac12_mux = | |
1652 | SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); | |
1653 | ||
1654 | /* DAC3 Source */ /* MX-15 [5:4] */ | |
1655 | static const char * const rt5677_dac3_src[] = { | |
1656 | "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" | |
1657 | }; | |
1658 | ||
1659 | static SOC_ENUM_SINGLE_DECL( | |
1660 | rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, | |
1661 | RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); | |
1662 | ||
1663 | static const struct snd_kcontrol_new rt5677_dac3_mux = | |
1664 | SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); | |
1665 | ||
1b7fd76a | 1666 | /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ |
0e826e86 OC |
1667 | static const char * const rt5677_pdm_src[] = { |
1668 | "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" | |
1669 | }; | |
1670 | ||
1671 | static SOC_ENUM_SINGLE_DECL( | |
1672 | rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, | |
1673 | RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); | |
1674 | ||
1675 | static const struct snd_kcontrol_new rt5677_pdm1_l_mux = | |
1b7fd76a | 1676 | SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); |
0e826e86 OC |
1677 | |
1678 | static SOC_ENUM_SINGLE_DECL( | |
1679 | rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, | |
1680 | RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); | |
1681 | ||
1682 | static const struct snd_kcontrol_new rt5677_pdm2_l_mux = | |
1b7fd76a | 1683 | SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); |
0e826e86 OC |
1684 | |
1685 | static SOC_ENUM_SINGLE_DECL( | |
1686 | rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, | |
1687 | RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); | |
1688 | ||
1689 | static const struct snd_kcontrol_new rt5677_pdm1_r_mux = | |
1b7fd76a | 1690 | SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); |
0e826e86 OC |
1691 | |
1692 | static SOC_ENUM_SINGLE_DECL( | |
1693 | rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, | |
1694 | RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); | |
1695 | ||
1696 | static const struct snd_kcontrol_new rt5677_pdm2_r_mux = | |
1b7fd76a | 1697 | SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); |
0e826e86 | 1698 | |
d65fd3a4 | 1699 | /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ |
0e826e86 OC |
1700 | static const char * const rt5677_if12_adc1_src[] = { |
1701 | "STO1 ADC MIX", "OB01", "VAD ADC" | |
1702 | }; | |
1703 | ||
1704 | static SOC_ENUM_SINGLE_DECL( | |
1705 | rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, | |
1706 | RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); | |
1707 | ||
1708 | static const struct snd_kcontrol_new rt5677_if1_adc1_mux = | |
1b7fd76a | 1709 | SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); |
0e826e86 OC |
1710 | |
1711 | static SOC_ENUM_SINGLE_DECL( | |
1712 | rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, | |
1713 | RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); | |
1714 | ||
1715 | static const struct snd_kcontrol_new rt5677_if2_adc1_mux = | |
1b7fd76a | 1716 | SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); |
0e826e86 OC |
1717 | |
1718 | static SOC_ENUM_SINGLE_DECL( | |
1719 | rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, | |
1720 | RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); | |
1721 | ||
1722 | static const struct snd_kcontrol_new rt5677_slb_adc1_mux = | |
1b7fd76a | 1723 | SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); |
0e826e86 OC |
1724 | |
1725 | /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ | |
1726 | static const char * const rt5677_if12_adc2_src[] = { | |
1727 | "STO2 ADC MIX", "OB23" | |
1728 | }; | |
1729 | ||
1730 | static SOC_ENUM_SINGLE_DECL( | |
1731 | rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, | |
1732 | RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); | |
1733 | ||
1734 | static const struct snd_kcontrol_new rt5677_if1_adc2_mux = | |
1b7fd76a | 1735 | SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); |
0e826e86 OC |
1736 | |
1737 | static SOC_ENUM_SINGLE_DECL( | |
1738 | rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, | |
1739 | RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); | |
1740 | ||
1741 | static const struct snd_kcontrol_new rt5677_if2_adc2_mux = | |
1b7fd76a | 1742 | SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); |
0e826e86 OC |
1743 | |
1744 | static SOC_ENUM_SINGLE_DECL( | |
1745 | rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, | |
1746 | RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); | |
1747 | ||
1748 | static const struct snd_kcontrol_new rt5677_slb_adc2_mux = | |
1b7fd76a | 1749 | SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); |
0e826e86 OC |
1750 | |
1751 | /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ | |
1752 | static const char * const rt5677_if12_adc3_src[] = { | |
1753 | "STO3 ADC MIX", "MONO ADC MIX", "OB45" | |
1754 | }; | |
1755 | ||
1756 | static SOC_ENUM_SINGLE_DECL( | |
1757 | rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, | |
1758 | RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); | |
1759 | ||
1760 | static const struct snd_kcontrol_new rt5677_if1_adc3_mux = | |
1b7fd76a | 1761 | SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); |
0e826e86 OC |
1762 | |
1763 | static SOC_ENUM_SINGLE_DECL( | |
1764 | rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, | |
1765 | RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); | |
1766 | ||
1767 | static const struct snd_kcontrol_new rt5677_if2_adc3_mux = | |
1b7fd76a | 1768 | SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); |
0e826e86 OC |
1769 | |
1770 | static SOC_ENUM_SINGLE_DECL( | |
1771 | rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, | |
1772 | RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); | |
1773 | ||
1774 | static const struct snd_kcontrol_new rt5677_slb_adc3_mux = | |
1b7fd76a | 1775 | SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); |
0e826e86 | 1776 | |
d65fd3a4 | 1777 | /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ |
0e826e86 OC |
1778 | static const char * const rt5677_if12_adc4_src[] = { |
1779 | "STO4 ADC MIX", "OB67", "OB01" | |
1780 | }; | |
1781 | ||
1782 | static SOC_ENUM_SINGLE_DECL( | |
1783 | rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, | |
1784 | RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); | |
1785 | ||
1786 | static const struct snd_kcontrol_new rt5677_if1_adc4_mux = | |
1b7fd76a | 1787 | SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); |
0e826e86 OC |
1788 | |
1789 | static SOC_ENUM_SINGLE_DECL( | |
1790 | rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, | |
1791 | RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); | |
1792 | ||
1793 | static const struct snd_kcontrol_new rt5677_if2_adc4_mux = | |
1b7fd76a | 1794 | SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); |
0e826e86 OC |
1795 | |
1796 | static SOC_ENUM_SINGLE_DECL( | |
1797 | rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, | |
1798 | RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); | |
1799 | ||
1800 | static const struct snd_kcontrol_new rt5677_slb_adc4_mux = | |
1b7fd76a | 1801 | SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); |
0e826e86 | 1802 | |
d65fd3a4 | 1803 | /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ |
0e826e86 OC |
1804 | static const char * const rt5677_if34_adc_src[] = { |
1805 | "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", | |
1806 | "MONO ADC MIX", "OB01", "OB23", "VAD ADC" | |
1807 | }; | |
1808 | ||
1809 | static SOC_ENUM_SINGLE_DECL( | |
1810 | rt5677_if3_adc_enum, RT5677_IF3_DATA, | |
1811 | RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); | |
1812 | ||
1813 | static const struct snd_kcontrol_new rt5677_if3_adc_mux = | |
1b7fd76a | 1814 | SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); |
0e826e86 OC |
1815 | |
1816 | static SOC_ENUM_SINGLE_DECL( | |
1817 | rt5677_if4_adc_enum, RT5677_IF4_DATA, | |
1818 | RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); | |
1819 | ||
1820 | static const struct snd_kcontrol_new rt5677_if4_adc_mux = | |
1b7fd76a | 1821 | SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); |
0e826e86 | 1822 | |
e6f6ebc1 OC |
1823 | /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ |
1824 | static const char * const rt5677_if12_adc_swap_src[] = { | |
1825 | "L/R", "R/L", "L/L", "R/R" | |
1826 | }; | |
1827 | ||
1828 | static SOC_ENUM_SINGLE_DECL( | |
1829 | rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, | |
1830 | RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); | |
1831 | ||
1832 | static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = | |
1833 | SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); | |
1834 | ||
1835 | static SOC_ENUM_SINGLE_DECL( | |
1836 | rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, | |
1837 | RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); | |
1838 | ||
1839 | static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = | |
1840 | SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); | |
1841 | ||
1842 | static SOC_ENUM_SINGLE_DECL( | |
1843 | rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, | |
1844 | RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); | |
1845 | ||
1846 | static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = | |
1847 | SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); | |
1848 | ||
1849 | static SOC_ENUM_SINGLE_DECL( | |
1850 | rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, | |
1851 | RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); | |
1852 | ||
1853 | static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = | |
1854 | SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); | |
1855 | ||
1856 | static SOC_ENUM_SINGLE_DECL( | |
1857 | rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, | |
1858 | RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); | |
1859 | ||
1860 | static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = | |
1861 | SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); | |
1862 | ||
1863 | static SOC_ENUM_SINGLE_DECL( | |
1864 | rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, | |
1865 | RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); | |
1866 | ||
1867 | static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = | |
1868 | SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); | |
1869 | ||
1870 | static SOC_ENUM_SINGLE_DECL( | |
1871 | rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, | |
1872 | RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); | |
1873 | ||
1874 | static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = | |
1875 | SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); | |
1876 | ||
1877 | static SOC_ENUM_SINGLE_DECL( | |
1878 | rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, | |
1879 | RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); | |
1880 | ||
1881 | static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = | |
1882 | SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); | |
1883 | ||
d65fd3a4 | 1884 | /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ |
e6f6ebc1 OC |
1885 | static const char * const rt5677_if1_adc_tdm_swap_src[] = { |
1886 | "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", | |
1887 | "3/1/2/4", "3/4/1/2" | |
1888 | }; | |
1889 | ||
1890 | static SOC_ENUM_SINGLE_DECL( | |
1891 | rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, | |
1892 | RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); | |
1893 | ||
1894 | static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = | |
1895 | SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); | |
1896 | ||
1897 | /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ | |
1898 | static const char * const rt5677_if2_adc_tdm_swap_src[] = { | |
1899 | "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", | |
1900 | "2/3/1/4", "3/4/1/2" | |
1901 | }; | |
1902 | ||
1903 | static SOC_ENUM_SINGLE_DECL( | |
1904 | rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, | |
1905 | RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); | |
1906 | ||
1907 | static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = | |
1908 | SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); | |
1909 | ||
91159eca OC |
1910 | /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] |
1911 | MX-3F[14:12][10:8][6:4][2:0] | |
1912 | MX-43[14:12][10:8][6:4][2:0] | |
1913 | MX-44[14:12][10:8][6:4][2:0] */ | |
1914 | static const char * const rt5677_if12_dac_tdm_sel_src[] = { | |
1915 | "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" | |
1916 | }; | |
1917 | ||
1918 | static SOC_ENUM_SINGLE_DECL( | |
1919 | rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, | |
1920 | RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); | |
1921 | ||
1922 | static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = | |
1923 | SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); | |
1924 | ||
1925 | static SOC_ENUM_SINGLE_DECL( | |
1926 | rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, | |
1927 | RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); | |
1928 | ||
1929 | static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = | |
1930 | SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); | |
1931 | ||
1932 | static SOC_ENUM_SINGLE_DECL( | |
1933 | rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, | |
1934 | RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); | |
1935 | ||
1936 | static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = | |
1937 | SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); | |
1938 | ||
1939 | static SOC_ENUM_SINGLE_DECL( | |
1940 | rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, | |
1941 | RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); | |
1942 | ||
1943 | static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = | |
1944 | SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); | |
1945 | ||
1946 | static SOC_ENUM_SINGLE_DECL( | |
1947 | rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, | |
1948 | RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); | |
1949 | ||
1950 | static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = | |
1951 | SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); | |
1952 | ||
1953 | static SOC_ENUM_SINGLE_DECL( | |
1954 | rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, | |
1955 | RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); | |
1956 | ||
1957 | static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = | |
1958 | SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); | |
1959 | ||
1960 | static SOC_ENUM_SINGLE_DECL( | |
1961 | rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, | |
1962 | RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); | |
1963 | ||
1964 | static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = | |
1965 | SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); | |
1966 | ||
1967 | static SOC_ENUM_SINGLE_DECL( | |
1968 | rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, | |
1969 | RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); | |
1970 | ||
1971 | static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = | |
1972 | SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); | |
1973 | ||
1974 | static SOC_ENUM_SINGLE_DECL( | |
1975 | rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, | |
1976 | RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); | |
1977 | ||
1978 | static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = | |
1979 | SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); | |
1980 | ||
1981 | static SOC_ENUM_SINGLE_DECL( | |
1982 | rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, | |
1983 | RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); | |
1984 | ||
1985 | static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = | |
1986 | SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); | |
1987 | ||
1988 | static SOC_ENUM_SINGLE_DECL( | |
1989 | rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, | |
1990 | RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); | |
1991 | ||
1992 | static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = | |
1993 | SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); | |
1994 | ||
1995 | static SOC_ENUM_SINGLE_DECL( | |
1996 | rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, | |
1997 | RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); | |
1998 | ||
1999 | static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = | |
2000 | SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); | |
2001 | ||
2002 | static SOC_ENUM_SINGLE_DECL( | |
2003 | rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, | |
2004 | RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); | |
2005 | ||
2006 | static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = | |
2007 | SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); | |
2008 | ||
2009 | static SOC_ENUM_SINGLE_DECL( | |
2010 | rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, | |
2011 | RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); | |
2012 | ||
2013 | static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = | |
2014 | SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); | |
2015 | ||
2016 | static SOC_ENUM_SINGLE_DECL( | |
2017 | rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, | |
2018 | RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); | |
2019 | ||
2020 | static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = | |
2021 | SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); | |
2022 | ||
2023 | static SOC_ENUM_SINGLE_DECL( | |
2024 | rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, | |
2025 | RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); | |
2026 | ||
2027 | static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = | |
2028 | SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); | |
2029 | ||
0e826e86 OC |
2030 | static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, |
2031 | struct snd_kcontrol *kcontrol, int event) | |
2032 | { | |
2033 | struct snd_soc_codec *codec = w->codec; | |
2034 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
2035 | ||
2036 | switch (event) { | |
2037 | case SND_SOC_DAPM_POST_PMU: | |
2038 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, | |
2039 | RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); | |
2040 | break; | |
2041 | ||
2042 | case SND_SOC_DAPM_PRE_PMD: | |
2043 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, | |
2044 | RT5677_PWR_BST1_P, 0); | |
2045 | break; | |
2046 | ||
2047 | default: | |
2048 | return 0; | |
2049 | } | |
2050 | ||
2051 | return 0; | |
2052 | } | |
2053 | ||
2054 | static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, | |
2055 | struct snd_kcontrol *kcontrol, int event) | |
2056 | { | |
2057 | struct snd_soc_codec *codec = w->codec; | |
2058 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
2059 | ||
2060 | switch (event) { | |
2061 | case SND_SOC_DAPM_POST_PMU: | |
2062 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, | |
2063 | RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); | |
2064 | break; | |
2065 | ||
2066 | case SND_SOC_DAPM_PRE_PMD: | |
2067 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, | |
2068 | RT5677_PWR_BST2_P, 0); | |
2069 | break; | |
2070 | ||
2071 | default: | |
2072 | return 0; | |
2073 | } | |
2074 | ||
2075 | return 0; | |
2076 | } | |
2077 | ||
2078 | static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, | |
2079 | struct snd_kcontrol *kcontrol, int event) | |
2080 | { | |
2081 | struct snd_soc_codec *codec = w->codec; | |
2082 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
2083 | ||
2084 | switch (event) { | |
2085 | case SND_SOC_DAPM_POST_PMU: | |
2086 | regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); | |
2087 | regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); | |
2088 | break; | |
2089 | default: | |
2090 | return 0; | |
2091 | } | |
2092 | ||
2093 | return 0; | |
2094 | } | |
2095 | ||
2096 | static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, | |
2097 | struct snd_kcontrol *kcontrol, int event) | |
2098 | { | |
2099 | struct snd_soc_codec *codec = w->codec; | |
2100 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
2101 | ||
2102 | switch (event) { | |
2103 | case SND_SOC_DAPM_POST_PMU: | |
2104 | regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); | |
2105 | regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); | |
2106 | break; | |
2107 | default: | |
2108 | return 0; | |
2109 | } | |
2110 | ||
2111 | return 0; | |
2112 | } | |
2113 | ||
2114 | static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, | |
2115 | struct snd_kcontrol *kcontrol, int event) | |
2116 | { | |
2117 | struct snd_soc_codec *codec = w->codec; | |
2118 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
2119 | ||
2120 | switch (event) { | |
2121 | case SND_SOC_DAPM_POST_PMU: | |
2122 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, | |
2123 | RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | | |
2124 | RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | | |
2125 | RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); | |
2126 | break; | |
f58c3b91 OC |
2127 | |
2128 | case SND_SOC_DAPM_PRE_PMD: | |
2129 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, | |
2130 | RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | | |
2131 | RT5677_PWR_CLK_MB, 0); | |
2132 | break; | |
2133 | ||
0e826e86 OC |
2134 | default: |
2135 | return 0; | |
2136 | } | |
2137 | ||
2138 | return 0; | |
2139 | } | |
2140 | ||
e6f6ebc1 OC |
2141 | static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, |
2142 | struct snd_kcontrol *kcontrol, int event) | |
2143 | { | |
2144 | struct snd_soc_codec *codec = w->codec; | |
2145 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
2146 | unsigned int value; | |
2147 | ||
2148 | switch (event) { | |
2149 | case SND_SOC_DAPM_PRE_PMU: | |
2150 | regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); | |
2151 | if (value & RT5677_IF1_ADC_CTRL_MASK) | |
2152 | regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, | |
2153 | RT5677_IF1_ADC_MODE_MASK, | |
2154 | RT5677_IF1_ADC_MODE_TDM); | |
2155 | break; | |
2156 | ||
2157 | default: | |
2158 | return 0; | |
2159 | } | |
2160 | ||
2161 | return 0; | |
2162 | } | |
2163 | ||
2164 | static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, | |
2165 | struct snd_kcontrol *kcontrol, int event) | |
2166 | { | |
2167 | struct snd_soc_codec *codec = w->codec; | |
2168 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
2169 | unsigned int value; | |
2170 | ||
2171 | switch (event) { | |
2172 | case SND_SOC_DAPM_PRE_PMU: | |
2173 | regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); | |
2174 | if (value & RT5677_IF2_ADC_CTRL_MASK) | |
2175 | regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, | |
2176 | RT5677_IF2_ADC_MODE_MASK, | |
2177 | RT5677_IF2_ADC_MODE_TDM); | |
2178 | break; | |
2179 | ||
2180 | default: | |
2181 | return 0; | |
2182 | } | |
2183 | ||
2184 | return 0; | |
2185 | } | |
2186 | ||
0e826e86 OC |
2187 | static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { |
2188 | SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, | |
2189 | 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU), | |
2190 | SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, | |
2191 | 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU), | |
2192 | ||
2193 | /* Input Side */ | |
2194 | /* micbias */ | |
3d0c03d9 | 2195 | SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, |
f58c3b91 OC |
2196 | 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | |
2197 | SND_SOC_DAPM_POST_PMU), | |
0e826e86 OC |
2198 | |
2199 | /* Input Lines */ | |
2200 | SND_SOC_DAPM_INPUT("DMIC L1"), | |
2201 | SND_SOC_DAPM_INPUT("DMIC R1"), | |
2202 | SND_SOC_DAPM_INPUT("DMIC L2"), | |
2203 | SND_SOC_DAPM_INPUT("DMIC R2"), | |
2204 | SND_SOC_DAPM_INPUT("DMIC L3"), | |
2205 | SND_SOC_DAPM_INPUT("DMIC R3"), | |
2206 | SND_SOC_DAPM_INPUT("DMIC L4"), | |
2207 | SND_SOC_DAPM_INPUT("DMIC R4"), | |
2208 | ||
2209 | SND_SOC_DAPM_INPUT("IN1P"), | |
2210 | SND_SOC_DAPM_INPUT("IN1N"), | |
2211 | SND_SOC_DAPM_INPUT("IN2P"), | |
2212 | SND_SOC_DAPM_INPUT("IN2N"), | |
2213 | ||
2214 | SND_SOC_DAPM_INPUT("Haptic Generator"), | |
2215 | ||
2d15d974 BL |
2216 | SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
2217 | SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2218 | SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2219 | SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2220 | ||
2221 | SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, | |
2222 | RT5677_DMIC_1_EN_SFT, 0, NULL, 0), | |
2223 | SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, | |
2224 | RT5677_DMIC_2_EN_SFT, 0, NULL, 0), | |
2225 | SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, | |
2226 | RT5677_DMIC_3_EN_SFT, 0, NULL, 0), | |
2227 | SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, | |
2228 | RT5677_DMIC_4_EN_SFT, 0, NULL, 0), | |
0e826e86 OC |
2229 | |
2230 | SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, | |
2231 | set_dmic_clk, SND_SOC_DAPM_PRE_PMU), | |
2232 | ||
2233 | /* Boost */ | |
2234 | SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, | |
2235 | RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, | |
2236 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
2237 | SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, | |
2238 | RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, | |
2239 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
2240 | ||
2241 | /* ADCs */ | |
2242 | SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, | |
2243 | 0, 0), | |
2244 | SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, | |
2245 | 0, 0), | |
2246 | SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2247 | ||
2248 | SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, | |
2249 | RT5677_PWR_ADC_L_BIT, 0, NULL, 0), | |
2250 | SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, | |
2251 | RT5677_PWR_ADC_R_BIT, 0, NULL, 0), | |
2252 | SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, | |
2253 | RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), | |
2254 | SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, | |
2255 | RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), | |
2256 | ||
2257 | /* ADC Mux */ | |
2258 | SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, | |
2259 | &rt5677_sto1_dmic_mux), | |
2260 | SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, | |
2261 | &rt5677_sto1_adc1_mux), | |
2262 | SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, | |
2263 | &rt5677_sto1_adc2_mux), | |
2264 | SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, | |
2265 | &rt5677_sto2_dmic_mux), | |
2266 | SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, | |
2267 | &rt5677_sto2_adc1_mux), | |
2268 | SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, | |
2269 | &rt5677_sto2_adc2_mux), | |
2270 | SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, | |
2271 | &rt5677_sto2_adc_lr_mux), | |
2272 | SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, | |
2273 | &rt5677_sto3_dmic_mux), | |
2274 | SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, | |
2275 | &rt5677_sto3_adc1_mux), | |
2276 | SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, | |
2277 | &rt5677_sto3_adc2_mux), | |
2278 | SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, | |
2279 | &rt5677_sto4_dmic_mux), | |
2280 | SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, | |
2281 | &rt5677_sto4_adc1_mux), | |
2282 | SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, | |
2283 | &rt5677_sto4_adc2_mux), | |
2284 | SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, | |
2285 | &rt5677_mono_dmic_l_mux), | |
2286 | SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, | |
2287 | &rt5677_mono_dmic_r_mux), | |
2288 | SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, | |
2289 | &rt5677_mono_adc2_l_mux), | |
2290 | SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, | |
2291 | &rt5677_mono_adc1_l_mux), | |
2292 | SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, | |
2293 | &rt5677_mono_adc1_r_mux), | |
2294 | SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, | |
2295 | &rt5677_mono_adc2_r_mux), | |
2296 | ||
2297 | /* ADC Mixer */ | |
2298 | SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, | |
2299 | RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), | |
2300 | SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, | |
2301 | RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), | |
2302 | SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, | |
2303 | RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), | |
2304 | SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, | |
2305 | RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), | |
2306 | SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, | |
2307 | rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), | |
2308 | SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, | |
2309 | rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), | |
2310 | SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, | |
2311 | rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), | |
2312 | SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, | |
2313 | rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), | |
2314 | SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, | |
2315 | rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), | |
2316 | SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, | |
2317 | rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), | |
2318 | SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, | |
2319 | rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), | |
2320 | SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, | |
2321 | rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), | |
2322 | SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, | |
2323 | RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), | |
2324 | SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, | |
2325 | rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), | |
2326 | SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, | |
2327 | RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), | |
2328 | SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, | |
2329 | rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), | |
2330 | ||
2331 | /* ADC PGA */ | |
2332 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2333 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2334 | SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2335 | SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2336 | SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2337 | SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2338 | SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2339 | SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2340 | SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2341 | SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2342 | SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2343 | SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2344 | SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2345 | SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
e6f6ebc1 OC |
2346 | SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
2347 | SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
0e826e86 OC |
2348 | |
2349 | /* DSP */ | |
2350 | SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, | |
2351 | &rt5677_ib9_src_mux), | |
2352 | SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, | |
2353 | &rt5677_ib8_src_mux), | |
2354 | SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, | |
2355 | &rt5677_ib7_src_mux), | |
2356 | SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, | |
2357 | &rt5677_ib6_src_mux), | |
2358 | SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, | |
2359 | &rt5677_ib45_src_mux), | |
2360 | SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, | |
2361 | &rt5677_ib23_src_mux), | |
2362 | SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, | |
2363 | &rt5677_ib01_src_mux), | |
2364 | SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, | |
2365 | &rt5677_ib45_bypass_src_mux), | |
2366 | SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, | |
2367 | &rt5677_ib23_bypass_src_mux), | |
2368 | SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, | |
2369 | &rt5677_ib01_bypass_src_mux), | |
2370 | SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, | |
2371 | &rt5677_ob23_bypass_src_mux), | |
2372 | SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, | |
2373 | &rt5677_ob01_bypass_src_mux), | |
2374 | ||
2375 | SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2376 | SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2377 | ||
2378 | SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2379 | SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2380 | SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2381 | SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2382 | SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2383 | SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2384 | ||
2385 | /* Digital Interface */ | |
2386 | SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, | |
2387 | RT5677_PWR_I2S1_BIT, 0, NULL, 0), | |
2388 | SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2389 | SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2390 | SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2391 | SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2392 | SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2393 | SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2394 | SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2395 | SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2396 | SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2397 | SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2398 | SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2399 | SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2400 | SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2401 | SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2402 | SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2403 | SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2404 | ||
2405 | SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, | |
2406 | RT5677_PWR_I2S2_BIT, 0, NULL, 0), | |
2407 | SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2408 | SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2409 | SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2410 | SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2411 | SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2412 | SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2413 | SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2414 | SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2415 | SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2416 | SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2417 | SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2418 | SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2419 | SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2420 | SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2421 | SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2422 | SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2423 | ||
2424 | SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, | |
2425 | RT5677_PWR_I2S3_BIT, 0, NULL, 0), | |
2426 | SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2427 | SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2428 | SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2429 | SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2430 | SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2431 | SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2432 | ||
2433 | SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, | |
2434 | RT5677_PWR_I2S4_BIT, 0, NULL, 0), | |
2435 | SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2436 | SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2437 | SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2438 | SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2439 | SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2440 | SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2441 | ||
2442 | SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, | |
2443 | RT5677_PWR_SLB_BIT, 0, NULL, 0), | |
2444 | SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2445 | SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2446 | SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2447 | SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2448 | SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2449 | SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2450 | SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2451 | SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2452 | SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2453 | SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2454 | SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2455 | SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2456 | SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2457 | SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2458 | SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2459 | SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2460 | ||
2461 | /* Digital Interface Select */ | |
2462 | SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, | |
2463 | &rt5677_if1_adc1_mux), | |
2464 | SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, | |
2465 | &rt5677_if1_adc2_mux), | |
2466 | SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, | |
2467 | &rt5677_if1_adc3_mux), | |
2468 | SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, | |
2469 | &rt5677_if1_adc4_mux), | |
e6f6ebc1 OC |
2470 | SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, |
2471 | &rt5677_if1_adc1_swap_mux), | |
2472 | SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, | |
2473 | &rt5677_if1_adc2_swap_mux), | |
2474 | SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, | |
2475 | &rt5677_if1_adc3_swap_mux), | |
2476 | SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, | |
2477 | &rt5677_if1_adc4_swap_mux), | |
2478 | SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, | |
2479 | &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, | |
2480 | SND_SOC_DAPM_PRE_PMU), | |
0e826e86 OC |
2481 | SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
2482 | &rt5677_if2_adc1_mux), | |
2483 | SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, | |
2484 | &rt5677_if2_adc2_mux), | |
2485 | SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, | |
2486 | &rt5677_if2_adc3_mux), | |
2487 | SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, | |
2488 | &rt5677_if2_adc4_mux), | |
e6f6ebc1 OC |
2489 | SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, |
2490 | &rt5677_if2_adc1_swap_mux), | |
2491 | SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, | |
2492 | &rt5677_if2_adc2_swap_mux), | |
2493 | SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, | |
2494 | &rt5677_if2_adc3_swap_mux), | |
2495 | SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, | |
2496 | &rt5677_if2_adc4_swap_mux), | |
2497 | SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, | |
2498 | &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, | |
2499 | SND_SOC_DAPM_PRE_PMU), | |
0e826e86 OC |
2500 | SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, |
2501 | &rt5677_if3_adc_mux), | |
2502 | SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, | |
2503 | &rt5677_if4_adc_mux), | |
2504 | SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, | |
2505 | &rt5677_slb_adc1_mux), | |
2506 | SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, | |
2507 | &rt5677_slb_adc2_mux), | |
2508 | SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, | |
2509 | &rt5677_slb_adc3_mux), | |
2510 | SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, | |
2511 | &rt5677_slb_adc4_mux), | |
2512 | ||
91159eca OC |
2513 | SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, |
2514 | &rt5677_if1_dac0_tdm_sel_mux), | |
2515 | SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, | |
2516 | &rt5677_if1_dac1_tdm_sel_mux), | |
2517 | SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, | |
2518 | &rt5677_if1_dac2_tdm_sel_mux), | |
2519 | SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, | |
2520 | &rt5677_if1_dac3_tdm_sel_mux), | |
2521 | SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, | |
2522 | &rt5677_if1_dac4_tdm_sel_mux), | |
2523 | SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, | |
2524 | &rt5677_if1_dac5_tdm_sel_mux), | |
2525 | SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, | |
2526 | &rt5677_if1_dac6_tdm_sel_mux), | |
2527 | SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, | |
2528 | &rt5677_if1_dac7_tdm_sel_mux), | |
2529 | ||
2530 | SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, | |
2531 | &rt5677_if2_dac0_tdm_sel_mux), | |
2532 | SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, | |
2533 | &rt5677_if2_dac1_tdm_sel_mux), | |
2534 | SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, | |
2535 | &rt5677_if2_dac2_tdm_sel_mux), | |
2536 | SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, | |
2537 | &rt5677_if2_dac3_tdm_sel_mux), | |
2538 | SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, | |
2539 | &rt5677_if2_dac4_tdm_sel_mux), | |
2540 | SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, | |
2541 | &rt5677_if2_dac5_tdm_sel_mux), | |
2542 | SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, | |
2543 | &rt5677_if2_dac6_tdm_sel_mux), | |
2544 | SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, | |
2545 | &rt5677_if2_dac7_tdm_sel_mux), | |
2546 | ||
0e826e86 OC |
2547 | /* Audio Interface */ |
2548 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
2549 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
2550 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
2551 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
2552 | SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), | |
2553 | SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), | |
2554 | SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), | |
2555 | SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), | |
2556 | SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), | |
2557 | SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), | |
2558 | ||
2559 | /* Sidetone Mux */ | |
2560 | SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, | |
2561 | &rt5677_sidetone_mux), | |
90bdbb46 OC |
2562 | SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, |
2563 | RT5677_ST_EN_SFT, 0, NULL, 0), | |
2564 | ||
0e826e86 OC |
2565 | /* VAD Mux*/ |
2566 | SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, | |
2567 | &rt5677_vad_src_mux), | |
2568 | ||
2569 | /* Tensilica DSP */ | |
2570 | SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2571 | SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, | |
2572 | rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), | |
2573 | SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, | |
2574 | rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), | |
2575 | SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, | |
2576 | rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), | |
2577 | SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, | |
2578 | rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), | |
2579 | SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, | |
2580 | rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), | |
2581 | SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, | |
2582 | rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), | |
2583 | ||
2584 | /* Output Side */ | |
d65fd3a4 | 2585 | /* DAC mixer before sound effect */ |
0e826e86 OC |
2586 | SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, |
2587 | rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), | |
2588 | SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, | |
2589 | rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), | |
2590 | SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2591 | ||
2592 | /* DAC Mux */ | |
2593 | SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, | |
2594 | &rt5677_dac1_mux), | |
2595 | SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, | |
2596 | &rt5677_adda1_mux), | |
2597 | SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, | |
2598 | &rt5677_dac12_mux), | |
2599 | SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, | |
2600 | &rt5677_dac3_mux), | |
2601 | ||
2602 | /* DAC2 channel Mux */ | |
2603 | SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, | |
2604 | &rt5677_dac2_l_mux), | |
2605 | SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, | |
2606 | &rt5677_dac2_r_mux), | |
2607 | ||
2608 | /* DAC3 channel Mux */ | |
2609 | SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, | |
2610 | &rt5677_dac3_l_mux), | |
2611 | SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, | |
2612 | &rt5677_dac3_r_mux), | |
2613 | ||
2614 | /* DAC4 channel Mux */ | |
2615 | SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, | |
2616 | &rt5677_dac4_l_mux), | |
2617 | SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, | |
2618 | &rt5677_dac4_r_mux), | |
2619 | ||
2620 | /* DAC Mixer */ | |
2621 | SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, | |
2622 | RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0), | |
2623 | SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2, | |
2624 | RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0), | |
2625 | SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2, | |
2626 | RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0), | |
2627 | ||
2628 | SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, | |
2629 | rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), | |
2630 | SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, | |
2631 | rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), | |
2632 | SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, | |
2633 | rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), | |
2634 | SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, | |
2635 | rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), | |
2636 | SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, | |
2637 | rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), | |
2638 | SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, | |
2639 | rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), | |
2640 | SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, | |
2641 | rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), | |
2642 | SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, | |
2643 | rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), | |
2644 | SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2645 | SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2646 | SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2647 | SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2648 | ||
2649 | /* DACs */ | |
2650 | SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, | |
2651 | RT5677_PWR_DAC1_BIT, 0), | |
2652 | SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, | |
2653 | RT5677_PWR_DAC2_BIT, 0), | |
2654 | SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, | |
2655 | RT5677_PWR_DAC3_BIT, 0), | |
2656 | ||
2657 | /* PDM */ | |
2658 | SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, | |
2659 | RT5677_PWR_PDM1_BIT, 0, NULL, 0), | |
2660 | SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, | |
2661 | RT5677_PWR_PDM2_BIT, 0, NULL, 0), | |
2662 | ||
2663 | SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, | |
2664 | 1, &rt5677_pdm1_l_mux), | |
2665 | SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, | |
2666 | 1, &rt5677_pdm1_r_mux), | |
2667 | SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, | |
2668 | 1, &rt5677_pdm2_l_mux), | |
2669 | SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, | |
2670 | 1, &rt5677_pdm2_r_mux), | |
2671 | ||
2672 | SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, | |
2673 | 0, NULL, 0), | |
2674 | SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, | |
2675 | 0, NULL, 0), | |
2676 | SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, | |
2677 | 0, NULL, 0), | |
2678 | ||
2679 | /* Output Lines */ | |
2680 | SND_SOC_DAPM_OUTPUT("LOUT1"), | |
2681 | SND_SOC_DAPM_OUTPUT("LOUT2"), | |
2682 | SND_SOC_DAPM_OUTPUT("LOUT3"), | |
2683 | SND_SOC_DAPM_OUTPUT("PDM1L"), | |
2684 | SND_SOC_DAPM_OUTPUT("PDM1R"), | |
2685 | SND_SOC_DAPM_OUTPUT("PDM2L"), | |
2686 | SND_SOC_DAPM_OUTPUT("PDM2R"), | |
2687 | }; | |
2688 | ||
2689 | static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { | |
2690 | { "DMIC1", NULL, "DMIC L1" }, | |
2691 | { "DMIC1", NULL, "DMIC R1" }, | |
2692 | { "DMIC2", NULL, "DMIC L2" }, | |
2693 | { "DMIC2", NULL, "DMIC R2" }, | |
2694 | { "DMIC3", NULL, "DMIC L3" }, | |
2695 | { "DMIC3", NULL, "DMIC R3" }, | |
2696 | { "DMIC4", NULL, "DMIC L4" }, | |
2697 | { "DMIC4", NULL, "DMIC R4" }, | |
2698 | ||
2699 | { "DMIC L1", NULL, "DMIC CLK" }, | |
2700 | { "DMIC R1", NULL, "DMIC CLK" }, | |
2701 | { "DMIC L2", NULL, "DMIC CLK" }, | |
2702 | { "DMIC R2", NULL, "DMIC CLK" }, | |
2703 | { "DMIC L3", NULL, "DMIC CLK" }, | |
2704 | { "DMIC R3", NULL, "DMIC CLK" }, | |
2705 | { "DMIC L4", NULL, "DMIC CLK" }, | |
2706 | { "DMIC R4", NULL, "DMIC CLK" }, | |
2707 | ||
2d15d974 BL |
2708 | { "DMIC L1", NULL, "DMIC1 power" }, |
2709 | { "DMIC R1", NULL, "DMIC1 power" }, | |
2710 | { "DMIC L3", NULL, "DMIC3 power" }, | |
2711 | { "DMIC R3", NULL, "DMIC3 power" }, | |
2712 | { "DMIC L4", NULL, "DMIC4 power" }, | |
2713 | { "DMIC R4", NULL, "DMIC4 power" }, | |
2714 | ||
0e826e86 OC |
2715 | { "BST1", NULL, "IN1P" }, |
2716 | { "BST1", NULL, "IN1N" }, | |
2717 | { "BST2", NULL, "IN2P" }, | |
2718 | { "BST2", NULL, "IN2N" }, | |
2719 | ||
22e51345 BL |
2720 | { "IN1P", NULL, "MICBIAS1" }, |
2721 | { "IN1N", NULL, "MICBIAS1" }, | |
2722 | { "IN2P", NULL, "MICBIAS1" }, | |
2723 | { "IN2N", NULL, "MICBIAS1" }, | |
0e826e86 OC |
2724 | |
2725 | { "ADC 1", NULL, "BST1" }, | |
2726 | { "ADC 1", NULL, "ADC 1 power" }, | |
2727 | { "ADC 1", NULL, "ADC1 clock" }, | |
2728 | { "ADC 2", NULL, "BST2" }, | |
2729 | { "ADC 2", NULL, "ADC 2 power" }, | |
2730 | { "ADC 2", NULL, "ADC2 clock" }, | |
2731 | ||
2732 | { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, | |
2733 | { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, | |
2734 | { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, | |
2735 | { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, | |
2736 | ||
2737 | { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, | |
2738 | { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, | |
2739 | { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, | |
2740 | { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, | |
2741 | ||
2742 | { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, | |
2743 | { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, | |
2744 | { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, | |
2745 | { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, | |
2746 | ||
2747 | { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, | |
2748 | { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, | |
2749 | { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, | |
2750 | { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, | |
2751 | ||
2752 | { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, | |
2753 | { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, | |
2754 | { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, | |
2755 | { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, | |
2756 | ||
2757 | { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, | |
2758 | { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, | |
2759 | { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, | |
2760 | { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, | |
2761 | ||
2762 | { "ADC 1_2", NULL, "ADC 1" }, | |
2763 | { "ADC 1_2", NULL, "ADC 2" }, | |
2764 | ||
2765 | { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, | |
2766 | { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, | |
2767 | { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, | |
2768 | ||
2769 | { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, | |
2770 | { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, | |
2771 | { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, | |
2772 | ||
2773 | { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, | |
2774 | { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, | |
2775 | { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, | |
2776 | ||
2777 | { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, | |
2778 | { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, | |
2779 | { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, | |
2780 | ||
2781 | { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, | |
2782 | { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, | |
2783 | { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, | |
2784 | ||
2785 | { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, | |
2786 | { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, | |
2787 | { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, | |
2788 | ||
2789 | { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, | |
2790 | { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, | |
2791 | { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, | |
2792 | ||
2793 | { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, | |
2794 | { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, | |
2795 | { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, | |
2796 | ||
2797 | { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, | |
2798 | { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, | |
2799 | { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, | |
2800 | ||
2801 | { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, | |
2802 | { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, | |
2803 | { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, | |
2804 | ||
2805 | { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, | |
2806 | { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, | |
2807 | { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, | |
2808 | ||
2809 | { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, | |
2810 | { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, | |
2811 | { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, | |
2812 | ||
2813 | { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, | |
2814 | { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, | |
2815 | { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, | |
2816 | { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, | |
2817 | ||
2818 | { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, | |
2819 | { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, | |
2820 | { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2821 | ||
2822 | { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, | |
2823 | { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, | |
2824 | { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2825 | ||
2826 | { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, | |
2827 | { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, | |
2828 | ||
2829 | { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, | |
2830 | { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, | |
2831 | { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, | |
2832 | { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, | |
2833 | ||
2834 | { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, | |
2835 | { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, | |
2836 | ||
2837 | { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, | |
2838 | { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, | |
2839 | ||
2840 | { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, | |
2841 | { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, | |
2842 | { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2843 | ||
2844 | { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, | |
2845 | { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, | |
2846 | { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2847 | ||
2848 | { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, | |
2849 | { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, | |
2850 | ||
2851 | { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, | |
2852 | { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, | |
2853 | { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, | |
2854 | { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, | |
2855 | ||
2856 | { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, | |
2857 | { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, | |
2858 | { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2859 | ||
2860 | { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, | |
2861 | { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, | |
2862 | { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2863 | ||
2864 | { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, | |
2865 | { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, | |
2866 | ||
2867 | { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, | |
2868 | { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, | |
2869 | { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, | |
2870 | { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, | |
2871 | ||
2872 | { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, | |
2873 | { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, | |
2874 | { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2875 | ||
2876 | { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, | |
2877 | { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, | |
2878 | { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2879 | ||
2880 | { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, | |
2881 | { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, | |
2882 | ||
2883 | { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, | |
2884 | { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, | |
2885 | { "Mono ADC MIXL", NULL, "adc mono left filter" }, | |
2886 | { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2887 | ||
2888 | { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, | |
2889 | { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, | |
2890 | { "Mono ADC MIXR", NULL, "adc mono right filter" }, | |
2891 | { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2892 | ||
2893 | { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, | |
2894 | { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, | |
2895 | ||
2896 | { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, | |
2897 | { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, | |
2898 | { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, | |
2899 | { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, | |
2900 | { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, | |
2901 | ||
2902 | { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, | |
2903 | { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, | |
2904 | { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, | |
2905 | ||
2906 | { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, | |
2907 | { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, | |
2908 | ||
2909 | { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, | |
2910 | { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, | |
2911 | { "IF1 ADC3 Mux", "OB45", "OB45" }, | |
2912 | ||
2913 | { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, | |
2914 | { "IF1 ADC4 Mux", "OB67", "OB67" }, | |
2915 | { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, | |
2916 | ||
e6f6ebc1 OC |
2917 | { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, |
2918 | { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, | |
2919 | { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, | |
2920 | { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, | |
2921 | ||
2922 | { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, | |
2923 | { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, | |
2924 | { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, | |
2925 | { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, | |
2926 | ||
2927 | { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, | |
2928 | { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, | |
2929 | { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, | |
2930 | { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, | |
2931 | ||
2932 | { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, | |
2933 | { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, | |
2934 | { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, | |
2935 | { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, | |
2936 | ||
2937 | { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, | |
2938 | { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, | |
2939 | { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, | |
2940 | { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, | |
2941 | ||
2942 | { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, | |
2943 | { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, | |
2944 | { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, | |
2945 | { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, | |
2946 | { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, | |
2947 | { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, | |
2948 | { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, | |
2949 | { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, | |
2950 | ||
0e826e86 | 2951 | { "AIF1TX", NULL, "I2S1" }, |
e6f6ebc1 | 2952 | { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, |
0e826e86 OC |
2953 | |
2954 | { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, | |
2955 | { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, | |
2956 | { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, | |
2957 | ||
2958 | { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, | |
2959 | { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, | |
2960 | ||
2961 | { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, | |
2962 | { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, | |
2963 | { "IF2 ADC3 Mux", "OB45", "OB45" }, | |
2964 | ||
2965 | { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, | |
2966 | { "IF2 ADC4 Mux", "OB67", "OB67" }, | |
2967 | { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, | |
2968 | ||
e6f6ebc1 OC |
2969 | { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, |
2970 | { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, | |
2971 | { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, | |
2972 | { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, | |
2973 | ||
2974 | { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, | |
2975 | { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, | |
2976 | { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, | |
2977 | { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, | |
2978 | ||
2979 | { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, | |
2980 | { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, | |
2981 | { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, | |
2982 | { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, | |
2983 | ||
2984 | { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, | |
2985 | { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, | |
2986 | { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, | |
2987 | { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, | |
2988 | ||
2989 | { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, | |
2990 | { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, | |
2991 | { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, | |
2992 | { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, | |
2993 | ||
2994 | { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, | |
2995 | { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, | |
2996 | { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, | |
2997 | { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, | |
2998 | { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, | |
2999 | { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, | |
3000 | { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, | |
3001 | { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, | |
3002 | ||
0e826e86 | 3003 | { "AIF2TX", NULL, "I2S2" }, |
e6f6ebc1 | 3004 | { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, |
0e826e86 OC |
3005 | |
3006 | { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, | |
3007 | { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, | |
3008 | { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, | |
3009 | { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, | |
3010 | { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, | |
3011 | { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, | |
3012 | { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, | |
3013 | { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, | |
3014 | ||
3015 | { "AIF3TX", NULL, "I2S3" }, | |
3016 | { "AIF3TX", NULL, "IF3 ADC Mux" }, | |
3017 | ||
3018 | { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, | |
3019 | { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, | |
3020 | { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, | |
3021 | { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, | |
3022 | { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, | |
3023 | { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, | |
3024 | { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, | |
3025 | { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, | |
3026 | ||
3027 | { "AIF4TX", NULL, "I2S4" }, | |
3028 | { "AIF4TX", NULL, "IF4 ADC Mux" }, | |
3029 | ||
3030 | { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, | |
3031 | { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, | |
3032 | { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, | |
3033 | ||
3034 | { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, | |
3035 | { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, | |
3036 | ||
3037 | { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, | |
3038 | { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, | |
3039 | { "SLB ADC3 Mux", "OB45", "OB45" }, | |
3040 | ||
3041 | { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, | |
3042 | { "SLB ADC4 Mux", "OB67", "OB67" }, | |
3043 | { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, | |
3044 | ||
3045 | { "SLBTX", NULL, "SLB" }, | |
3046 | { "SLBTX", NULL, "SLB ADC1 Mux" }, | |
3047 | { "SLBTX", NULL, "SLB ADC2 Mux" }, | |
3048 | { "SLBTX", NULL, "SLB ADC3 Mux" }, | |
3049 | { "SLBTX", NULL, "SLB ADC4 Mux" }, | |
3050 | ||
3051 | { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, | |
3052 | { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, | |
3053 | { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, | |
3054 | { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, | |
3055 | { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" }, | |
3056 | ||
3057 | { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, | |
3058 | { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, | |
3059 | ||
3060 | { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, | |
3061 | { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, | |
3062 | { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, | |
3063 | { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, | |
3064 | { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, | |
3065 | { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, | |
3066 | ||
3067 | { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, | |
3068 | { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, | |
3069 | ||
3070 | { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, | |
3071 | { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, | |
3072 | { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, | |
3073 | { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, | |
3074 | { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, | |
3075 | ||
3076 | { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, | |
3077 | { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, | |
3078 | ||
3079 | { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" }, | |
3080 | { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" }, | |
3081 | { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, | |
3082 | { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, | |
3083 | { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, | |
3084 | { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, | |
3085 | { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, | |
3086 | { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, | |
3087 | ||
3088 | { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" }, | |
3089 | { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" }, | |
3090 | { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, | |
3091 | { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, | |
3092 | { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, | |
3093 | { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, | |
3094 | { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, | |
3095 | { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, | |
3096 | ||
3097 | { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, | |
3098 | { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, | |
3099 | { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, | |
3100 | { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, | |
3101 | { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, | |
3102 | { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, | |
3103 | ||
3104 | { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, | |
3105 | { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, | |
3106 | { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, | |
3107 | { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, | |
3108 | { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, | |
3109 | { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, | |
3110 | { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, | |
3111 | ||
3112 | { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, | |
3113 | { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, | |
3114 | { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, | |
3115 | { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, | |
3116 | { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, | |
3117 | { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, | |
3118 | { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, | |
3119 | ||
3120 | { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, | |
3121 | { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, | |
3122 | { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, | |
3123 | { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, | |
3124 | { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, | |
3125 | { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, | |
3126 | { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, | |
3127 | ||
3128 | { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, | |
3129 | { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, | |
3130 | { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, | |
3131 | { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, | |
3132 | { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, | |
3133 | { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, | |
3134 | { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, | |
3135 | ||
3136 | { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, | |
3137 | { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, | |
3138 | { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, | |
3139 | { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, | |
3140 | { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, | |
3141 | { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, | |
3142 | { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, | |
3143 | ||
3144 | { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, | |
3145 | { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, | |
3146 | { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, | |
3147 | { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, | |
3148 | { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, | |
3149 | { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, | |
3150 | { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, | |
3151 | ||
3152 | { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, | |
3153 | { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, | |
3154 | { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, | |
3155 | { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, | |
3156 | { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, | |
3157 | { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, | |
3158 | { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, | |
3159 | ||
3160 | { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, | |
3161 | { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, | |
3162 | { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, | |
3163 | { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, | |
3164 | ||
3165 | { "OutBound2", NULL, "OB23 Bypass Mux" }, | |
3166 | { "OutBound3", NULL, "OB23 Bypass Mux" }, | |
3167 | { "OutBound4", NULL, "OB4 MIX" }, | |
3168 | { "OutBound5", NULL, "OB5 MIX" }, | |
3169 | { "OutBound6", NULL, "OB6 MIX" }, | |
3170 | { "OutBound7", NULL, "OB7 MIX" }, | |
3171 | ||
3172 | { "OB45", NULL, "OutBound4" }, | |
3173 | { "OB45", NULL, "OutBound5" }, | |
3174 | { "OB67", NULL, "OutBound6" }, | |
3175 | { "OB67", NULL, "OutBound7" }, | |
3176 | ||
3177 | { "IF1 DAC0", NULL, "AIF1RX" }, | |
3178 | { "IF1 DAC1", NULL, "AIF1RX" }, | |
3179 | { "IF1 DAC2", NULL, "AIF1RX" }, | |
3180 | { "IF1 DAC3", NULL, "AIF1RX" }, | |
3181 | { "IF1 DAC4", NULL, "AIF1RX" }, | |
3182 | { "IF1 DAC5", NULL, "AIF1RX" }, | |
3183 | { "IF1 DAC6", NULL, "AIF1RX" }, | |
3184 | { "IF1 DAC7", NULL, "AIF1RX" }, | |
3185 | { "IF1 DAC0", NULL, "I2S1" }, | |
3186 | { "IF1 DAC1", NULL, "I2S1" }, | |
3187 | { "IF1 DAC2", NULL, "I2S1" }, | |
3188 | { "IF1 DAC3", NULL, "I2S1" }, | |
3189 | { "IF1 DAC4", NULL, "I2S1" }, | |
3190 | { "IF1 DAC5", NULL, "I2S1" }, | |
3191 | { "IF1 DAC6", NULL, "I2S1" }, | |
3192 | { "IF1 DAC7", NULL, "I2S1" }, | |
3193 | ||
91159eca OC |
3194 | { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, |
3195 | { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, | |
3196 | { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, | |
3197 | { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, | |
3198 | { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, | |
3199 | { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, | |
3200 | { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, | |
3201 | { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, | |
3202 | ||
3203 | { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, | |
3204 | { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, | |
3205 | { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, | |
3206 | { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, | |
3207 | { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, | |
3208 | { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, | |
3209 | { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, | |
3210 | { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, | |
3211 | ||
3212 | { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, | |
3213 | { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, | |
3214 | { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, | |
3215 | { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, | |
3216 | { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, | |
3217 | { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, | |
3218 | { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, | |
3219 | { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, | |
3220 | ||
3221 | { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, | |
3222 | { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, | |
3223 | { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, | |
3224 | { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, | |
3225 | { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, | |
3226 | { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, | |
3227 | { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, | |
3228 | { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, | |
3229 | ||
3230 | { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, | |
3231 | { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, | |
3232 | { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, | |
3233 | { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, | |
3234 | { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, | |
3235 | { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, | |
3236 | { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, | |
3237 | { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, | |
3238 | ||
3239 | { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, | |
3240 | { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, | |
3241 | { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, | |
3242 | { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, | |
3243 | { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, | |
3244 | { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, | |
3245 | { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, | |
3246 | { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, | |
3247 | ||
3248 | { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, | |
3249 | { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, | |
3250 | { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, | |
3251 | { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, | |
3252 | { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, | |
3253 | { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, | |
3254 | { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, | |
3255 | { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, | |
3256 | ||
3257 | { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, | |
3258 | { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, | |
3259 | { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, | |
3260 | { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, | |
3261 | { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, | |
3262 | { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, | |
3263 | { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, | |
3264 | { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, | |
3265 | ||
3266 | { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, | |
3267 | { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, | |
3268 | { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, | |
3269 | { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, | |
3270 | { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, | |
3271 | { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, | |
3272 | { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, | |
3273 | { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, | |
0e826e86 OC |
3274 | |
3275 | { "IF2 DAC0", NULL, "AIF2RX" }, | |
3276 | { "IF2 DAC1", NULL, "AIF2RX" }, | |
3277 | { "IF2 DAC2", NULL, "AIF2RX" }, | |
3278 | { "IF2 DAC3", NULL, "AIF2RX" }, | |
3279 | { "IF2 DAC4", NULL, "AIF2RX" }, | |
3280 | { "IF2 DAC5", NULL, "AIF2RX" }, | |
3281 | { "IF2 DAC6", NULL, "AIF2RX" }, | |
3282 | { "IF2 DAC7", NULL, "AIF2RX" }, | |
3283 | { "IF2 DAC0", NULL, "I2S2" }, | |
3284 | { "IF2 DAC1", NULL, "I2S2" }, | |
3285 | { "IF2 DAC2", NULL, "I2S2" }, | |
3286 | { "IF2 DAC3", NULL, "I2S2" }, | |
3287 | { "IF2 DAC4", NULL, "I2S2" }, | |
3288 | { "IF2 DAC5", NULL, "I2S2" }, | |
3289 | { "IF2 DAC6", NULL, "I2S2" }, | |
3290 | { "IF2 DAC7", NULL, "I2S2" }, | |
3291 | ||
91159eca OC |
3292 | { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, |
3293 | { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, | |
3294 | { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, | |
3295 | { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, | |
3296 | { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, | |
3297 | { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, | |
3298 | { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, | |
3299 | { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, | |
3300 | ||
3301 | { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, | |
3302 | { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, | |
3303 | { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, | |
3304 | { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, | |
3305 | { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, | |
3306 | { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, | |
3307 | { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, | |
3308 | { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, | |
3309 | ||
3310 | { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, | |
3311 | { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, | |
3312 | { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, | |
3313 | { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, | |
3314 | { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, | |
3315 | { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, | |
3316 | { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, | |
3317 | { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, | |
3318 | ||
3319 | { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, | |
3320 | { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, | |
3321 | { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, | |
3322 | { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, | |
3323 | { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, | |
3324 | { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, | |
3325 | { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, | |
3326 | { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, | |
3327 | ||
3328 | { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, | |
3329 | { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, | |
3330 | { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, | |
3331 | { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, | |
3332 | { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, | |
3333 | { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, | |
3334 | { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, | |
3335 | { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, | |
3336 | ||
3337 | { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, | |
3338 | { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, | |
3339 | { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, | |
3340 | { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, | |
3341 | { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, | |
3342 | { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, | |
3343 | { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, | |
3344 | { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, | |
3345 | ||
3346 | { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, | |
3347 | { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, | |
3348 | { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, | |
3349 | { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, | |
3350 | { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, | |
3351 | { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, | |
3352 | { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, | |
3353 | { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, | |
3354 | ||
3355 | { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, | |
3356 | { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, | |
3357 | { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, | |
3358 | { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, | |
3359 | { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, | |
3360 | { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, | |
3361 | { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, | |
3362 | { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, | |
3363 | ||
3364 | { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, | |
3365 | { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, | |
3366 | { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, | |
3367 | { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, | |
3368 | { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, | |
3369 | { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, | |
3370 | { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, | |
3371 | { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, | |
0e826e86 OC |
3372 | |
3373 | { "IF3 DAC", NULL, "AIF3RX" }, | |
3374 | { "IF3 DAC", NULL, "I2S3" }, | |
3375 | ||
3376 | { "IF4 DAC", NULL, "AIF4RX" }, | |
3377 | { "IF4 DAC", NULL, "I2S4" }, | |
3378 | ||
3379 | { "IF3 DAC L", NULL, "IF3 DAC" }, | |
3380 | { "IF3 DAC R", NULL, "IF3 DAC" }, | |
3381 | ||
3382 | { "IF4 DAC L", NULL, "IF4 DAC" }, | |
3383 | { "IF4 DAC R", NULL, "IF4 DAC" }, | |
3384 | ||
3385 | { "SLB DAC0", NULL, "SLBRX" }, | |
3386 | { "SLB DAC1", NULL, "SLBRX" }, | |
3387 | { "SLB DAC2", NULL, "SLBRX" }, | |
3388 | { "SLB DAC3", NULL, "SLBRX" }, | |
3389 | { "SLB DAC4", NULL, "SLBRX" }, | |
3390 | { "SLB DAC5", NULL, "SLBRX" }, | |
3391 | { "SLB DAC6", NULL, "SLBRX" }, | |
3392 | { "SLB DAC7", NULL, "SLBRX" }, | |
3393 | { "SLB DAC0", NULL, "SLB" }, | |
3394 | { "SLB DAC1", NULL, "SLB" }, | |
3395 | { "SLB DAC2", NULL, "SLB" }, | |
3396 | { "SLB DAC3", NULL, "SLB" }, | |
3397 | { "SLB DAC4", NULL, "SLB" }, | |
3398 | { "SLB DAC5", NULL, "SLB" }, | |
3399 | { "SLB DAC6", NULL, "SLB" }, | |
3400 | { "SLB DAC7", NULL, "SLB" }, | |
3401 | ||
3402 | { "SLB DAC01", NULL, "SLB DAC0" }, | |
3403 | { "SLB DAC01", NULL, "SLB DAC1" }, | |
3404 | { "SLB DAC23", NULL, "SLB DAC2" }, | |
3405 | { "SLB DAC23", NULL, "SLB DAC3" }, | |
3406 | { "SLB DAC45", NULL, "SLB DAC4" }, | |
3407 | { "SLB DAC45", NULL, "SLB DAC5" }, | |
3408 | { "SLB DAC67", NULL, "SLB DAC6" }, | |
3409 | { "SLB DAC67", NULL, "SLB DAC7" }, | |
3410 | ||
3411 | { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, | |
3412 | { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, | |
3413 | { "ADDA1 Mux", "OB 67", "OB67" }, | |
3414 | ||
3415 | { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, | |
3416 | { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, | |
3417 | { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, | |
3418 | { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, | |
3419 | { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, | |
3420 | { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, | |
3421 | ||
3422 | { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, | |
3423 | { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, | |
3424 | { "DAC1 MIXL", NULL, "dac stereo1 filter" }, | |
3425 | { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, | |
3426 | { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, | |
3427 | { "DAC1 MIXR", NULL, "dac stereo1 filter" }, | |
3428 | ||
3429 | { "DAC1 FS", NULL, "DAC1 MIXL" }, | |
3430 | { "DAC1 FS", NULL, "DAC1 MIXR" }, | |
3431 | ||
3432 | { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" }, | |
3433 | { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" }, | |
3434 | { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, | |
3435 | { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, | |
3436 | { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, | |
3437 | { "DAC2 L Mux", "OB 2", "OutBound2" }, | |
3438 | ||
3439 | { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" }, | |
3440 | { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" }, | |
3441 | { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, | |
3442 | { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, | |
3443 | { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, | |
3444 | { "DAC2 R Mux", "OB 3", "OutBound3" }, | |
3445 | { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, | |
3446 | { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, | |
3447 | ||
3448 | { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" }, | |
3449 | { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" }, | |
3450 | { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, | |
3451 | { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, | |
3452 | { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, | |
3453 | { "DAC3 L Mux", "OB 4", "OutBound4" }, | |
3454 | ||
3455 | { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" }, | |
3456 | { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" }, | |
3457 | { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, | |
3458 | { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, | |
3459 | { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, | |
3460 | { "DAC3 R Mux", "OB 5", "OutBound5" }, | |
3461 | ||
3462 | { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" }, | |
3463 | { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" }, | |
3464 | { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, | |
3465 | { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, | |
3466 | { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, | |
3467 | { "DAC4 L Mux", "OB 6", "OutBound6" }, | |
3468 | ||
3469 | { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" }, | |
3470 | { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" }, | |
3471 | { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, | |
3472 | { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, | |
3473 | { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, | |
3474 | { "DAC4 R Mux", "OB 7", "OutBound7" }, | |
3475 | ||
3476 | { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, | |
3477 | { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, | |
3478 | { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, | |
3479 | { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, | |
3480 | { "Sidetone Mux", "ADC1", "ADC 1" }, | |
3481 | { "Sidetone Mux", "ADC2", "ADC 2" }, | |
90bdbb46 | 3482 | { "Sidetone Mux", NULL, "Sidetone Power" }, |
0e826e86 OC |
3483 | |
3484 | { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, | |
3485 | { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, | |
3486 | { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, | |
3487 | { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, | |
3488 | { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, | |
3489 | { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, | |
3490 | { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, | |
3491 | { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, | |
3492 | { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, | |
3493 | { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, | |
3494 | ||
3495 | { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, | |
3496 | { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, | |
3497 | { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, | |
3498 | { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, | |
3499 | { "Mono DAC MIXL", NULL, "dac mono left filter" }, | |
3500 | { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, | |
3501 | { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, | |
3502 | { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, | |
3503 | { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, | |
3504 | { "Mono DAC MIXR", NULL, "dac mono right filter" }, | |
3505 | ||
3506 | { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, | |
3507 | { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, | |
3508 | { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, | |
3509 | { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, | |
3510 | { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, | |
3511 | { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, | |
3512 | { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, | |
3513 | { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, | |
3514 | ||
3515 | { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, | |
3516 | { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, | |
3517 | { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, | |
3518 | { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, | |
3519 | { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, | |
3520 | { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, | |
3521 | { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, | |
3522 | { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, | |
3523 | ||
3524 | { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, | |
3525 | { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, | |
3526 | { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, | |
3527 | { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, | |
3528 | { "DD1 MIX", NULL, "DD1 MIXL" }, | |
3529 | { "DD1 MIX", NULL, "DD1 MIXR" }, | |
3530 | { "DD2 MIX", NULL, "DD2 MIXL" }, | |
3531 | { "DD2 MIX", NULL, "DD2 MIXR" }, | |
3532 | ||
3533 | { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, | |
3534 | { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, | |
3535 | { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, | |
3536 | { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, | |
3537 | ||
3538 | { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, | |
3539 | { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, | |
3540 | { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, | |
3541 | { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, | |
3542 | ||
3543 | { "DAC 1", NULL, "DAC12 SRC Mux" }, | |
3544 | { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll }, | |
3545 | { "DAC 2", NULL, "DAC12 SRC Mux" }, | |
3546 | { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll }, | |
3547 | { "DAC 3", NULL, "DAC3 SRC Mux" }, | |
3548 | { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll }, | |
3549 | ||
3550 | { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, | |
3551 | { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, | |
3552 | { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, | |
3553 | { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, | |
3554 | { "PDM1 L Mux", NULL, "PDM1 Power" }, | |
3555 | { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, | |
3556 | { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, | |
3557 | { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, | |
3558 | { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, | |
3559 | { "PDM1 R Mux", NULL, "PDM1 Power" }, | |
3560 | { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, | |
3561 | { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, | |
3562 | { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, | |
3563 | { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, | |
3564 | { "PDM2 L Mux", NULL, "PDM2 Power" }, | |
3565 | { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, | |
3566 | { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, | |
3567 | { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, | |
3568 | { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, | |
3569 | { "PDM2 R Mux", NULL, "PDM2 Power" }, | |
3570 | ||
3571 | { "LOUT1 amp", NULL, "DAC 1" }, | |
3572 | { "LOUT2 amp", NULL, "DAC 2" }, | |
3573 | { "LOUT3 amp", NULL, "DAC 3" }, | |
3574 | ||
3575 | { "LOUT1", NULL, "LOUT1 amp" }, | |
3576 | { "LOUT2", NULL, "LOUT2 amp" }, | |
3577 | { "LOUT3", NULL, "LOUT3 amp" }, | |
3578 | ||
3579 | { "PDM1L", NULL, "PDM1 L Mux" }, | |
3580 | { "PDM1R", NULL, "PDM1 R Mux" }, | |
3581 | { "PDM2L", NULL, "PDM2 L Mux" }, | |
3582 | { "PDM2R", NULL, "PDM2 R Mux" }, | |
3583 | }; | |
3584 | ||
2d15d974 BL |
3585 | static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { |
3586 | { "DMIC L2", NULL, "DMIC1 power" }, | |
3587 | { "DMIC R2", NULL, "DMIC1 power" }, | |
3588 | }; | |
3589 | ||
3590 | static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { | |
3591 | { "DMIC L2", NULL, "DMIC2 power" }, | |
3592 | { "DMIC R2", NULL, "DMIC2 power" }, | |
3593 | }; | |
3594 | ||
0e826e86 OC |
3595 | static int rt5677_hw_params(struct snd_pcm_substream *substream, |
3596 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
3597 | { | |
3598 | struct snd_soc_codec *codec = dai->codec; | |
3599 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
3600 | unsigned int val_len = 0, val_clk, mask_clk; | |
3601 | int pre_div, bclk_ms, frame_size; | |
3602 | ||
3603 | rt5677->lrck[dai->id] = params_rate(params); | |
30f14b43 | 3604 | pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); |
0e826e86 | 3605 | if (pre_div < 0) { |
8a4bd60a AP |
3606 | dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", |
3607 | rt5677->sysclk, rt5677->lrck[dai->id]); | |
0e826e86 OC |
3608 | return -EINVAL; |
3609 | } | |
3610 | frame_size = snd_soc_params_to_frame_size(params); | |
3611 | if (frame_size < 0) { | |
3612 | dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); | |
3613 | return -EINVAL; | |
3614 | } | |
3615 | bclk_ms = frame_size > 32; | |
3616 | rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); | |
3617 | ||
3618 | dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", | |
3619 | rt5677->bclk[dai->id], rt5677->lrck[dai->id]); | |
3620 | dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", | |
3621 | bclk_ms, pre_div, dai->id); | |
3622 | ||
3623 | switch (params_width(params)) { | |
3624 | case 16: | |
3625 | break; | |
3626 | case 20: | |
3627 | val_len |= RT5677_I2S_DL_20; | |
3628 | break; | |
3629 | case 24: | |
3630 | val_len |= RT5677_I2S_DL_24; | |
3631 | break; | |
3632 | case 8: | |
3633 | val_len |= RT5677_I2S_DL_8; | |
3634 | break; | |
3635 | default: | |
3636 | return -EINVAL; | |
3637 | } | |
3638 | ||
3639 | switch (dai->id) { | |
3640 | case RT5677_AIF1: | |
3641 | mask_clk = RT5677_I2S_PD1_MASK; | |
3642 | val_clk = pre_div << RT5677_I2S_PD1_SFT; | |
3643 | regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, | |
3644 | RT5677_I2S_DL_MASK, val_len); | |
3645 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, | |
3646 | mask_clk, val_clk); | |
3647 | break; | |
3648 | case RT5677_AIF2: | |
3649 | mask_clk = RT5677_I2S_PD2_MASK; | |
3650 | val_clk = pre_div << RT5677_I2S_PD2_SFT; | |
3651 | regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, | |
3652 | RT5677_I2S_DL_MASK, val_len); | |
3653 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, | |
3654 | mask_clk, val_clk); | |
3655 | break; | |
3656 | case RT5677_AIF3: | |
3657 | mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; | |
3658 | val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | | |
3659 | pre_div << RT5677_I2S_PD3_SFT; | |
3660 | regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, | |
3661 | RT5677_I2S_DL_MASK, val_len); | |
3662 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, | |
3663 | mask_clk, val_clk); | |
3664 | break; | |
3665 | case RT5677_AIF4: | |
3666 | mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; | |
3667 | val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | | |
3668 | pre_div << RT5677_I2S_PD4_SFT; | |
3669 | regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, | |
3670 | RT5677_I2S_DL_MASK, val_len); | |
3671 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, | |
3672 | mask_clk, val_clk); | |
3673 | break; | |
3674 | default: | |
3675 | break; | |
3676 | } | |
3677 | ||
3678 | return 0; | |
3679 | } | |
3680 | ||
3681 | static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
3682 | { | |
3683 | struct snd_soc_codec *codec = dai->codec; | |
3684 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
3685 | unsigned int reg_val = 0; | |
3686 | ||
3687 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
3688 | case SND_SOC_DAIFMT_CBM_CFM: | |
3689 | rt5677->master[dai->id] = 1; | |
3690 | break; | |
3691 | case SND_SOC_DAIFMT_CBS_CFS: | |
3692 | reg_val |= RT5677_I2S_MS_S; | |
3693 | rt5677->master[dai->id] = 0; | |
3694 | break; | |
3695 | default: | |
3696 | return -EINVAL; | |
3697 | } | |
3698 | ||
3699 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
3700 | case SND_SOC_DAIFMT_NB_NF: | |
3701 | break; | |
3702 | case SND_SOC_DAIFMT_IB_NF: | |
3703 | reg_val |= RT5677_I2S_BP_INV; | |
3704 | break; | |
3705 | default: | |
3706 | return -EINVAL; | |
3707 | } | |
3708 | ||
3709 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
3710 | case SND_SOC_DAIFMT_I2S: | |
3711 | break; | |
3712 | case SND_SOC_DAIFMT_LEFT_J: | |
3713 | reg_val |= RT5677_I2S_DF_LEFT; | |
3714 | break; | |
3715 | case SND_SOC_DAIFMT_DSP_A: | |
3716 | reg_val |= RT5677_I2S_DF_PCM_A; | |
3717 | break; | |
3718 | case SND_SOC_DAIFMT_DSP_B: | |
3719 | reg_val |= RT5677_I2S_DF_PCM_B; | |
3720 | break; | |
3721 | default: | |
3722 | return -EINVAL; | |
3723 | } | |
3724 | ||
3725 | switch (dai->id) { | |
3726 | case RT5677_AIF1: | |
3727 | regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, | |
3728 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | | |
3729 | RT5677_I2S_DF_MASK, reg_val); | |
3730 | break; | |
3731 | case RT5677_AIF2: | |
3732 | regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, | |
3733 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | | |
3734 | RT5677_I2S_DF_MASK, reg_val); | |
3735 | break; | |
3736 | case RT5677_AIF3: | |
3737 | regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, | |
3738 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | | |
3739 | RT5677_I2S_DF_MASK, reg_val); | |
3740 | break; | |
3741 | case RT5677_AIF4: | |
3742 | regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, | |
3743 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | | |
3744 | RT5677_I2S_DF_MASK, reg_val); | |
3745 | break; | |
3746 | default: | |
3747 | break; | |
3748 | } | |
3749 | ||
3750 | ||
3751 | return 0; | |
3752 | } | |
3753 | ||
3754 | static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, | |
3755 | int clk_id, unsigned int freq, int dir) | |
3756 | { | |
3757 | struct snd_soc_codec *codec = dai->codec; | |
3758 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
3759 | unsigned int reg_val = 0; | |
3760 | ||
3761 | if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) | |
3762 | return 0; | |
3763 | ||
3764 | switch (clk_id) { | |
3765 | case RT5677_SCLK_S_MCLK: | |
3766 | reg_val |= RT5677_SCLK_SRC_MCLK; | |
3767 | break; | |
3768 | case RT5677_SCLK_S_PLL1: | |
3769 | reg_val |= RT5677_SCLK_SRC_PLL1; | |
3770 | break; | |
3771 | case RT5677_SCLK_S_RCCLK: | |
3772 | reg_val |= RT5677_SCLK_SRC_RCCLK; | |
3773 | break; | |
3774 | default: | |
3775 | dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); | |
3776 | return -EINVAL; | |
3777 | } | |
3778 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, | |
3779 | RT5677_SCLK_SRC_MASK, reg_val); | |
3780 | rt5677->sysclk = freq; | |
3781 | rt5677->sysclk_src = clk_id; | |
3782 | ||
3783 | dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); | |
3784 | ||
3785 | return 0; | |
3786 | } | |
3787 | ||
3788 | /** | |
3789 | * rt5677_pll_calc - Calcualte PLL M/N/K code. | |
3790 | * @freq_in: external clock provided to codec. | |
3791 | * @freq_out: target clock which codec works on. | |
3792 | * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. | |
3793 | * | |
3794 | * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. | |
3795 | * | |
3796 | * Returns 0 for success or negative error code. | |
3797 | */ | |
3798 | static int rt5677_pll_calc(const unsigned int freq_in, | |
099d334e | 3799 | const unsigned int freq_out, struct rl6231_pll_code *pll_code) |
0e826e86 | 3800 | { |
099d334e | 3801 | if (RT5677_PLL_INP_MIN > freq_in) |
0e826e86 OC |
3802 | return -EINVAL; |
3803 | ||
099d334e | 3804 | return rl6231_pll_calc(freq_in, freq_out, pll_code); |
0e826e86 OC |
3805 | } |
3806 | ||
3807 | static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, | |
3808 | unsigned int freq_in, unsigned int freq_out) | |
3809 | { | |
3810 | struct snd_soc_codec *codec = dai->codec; | |
3811 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
099d334e | 3812 | struct rl6231_pll_code pll_code; |
0e826e86 OC |
3813 | int ret; |
3814 | ||
3815 | if (source == rt5677->pll_src && freq_in == rt5677->pll_in && | |
3816 | freq_out == rt5677->pll_out) | |
3817 | return 0; | |
3818 | ||
3819 | if (!freq_in || !freq_out) { | |
3820 | dev_dbg(codec->dev, "PLL disabled\n"); | |
3821 | ||
3822 | rt5677->pll_in = 0; | |
3823 | rt5677->pll_out = 0; | |
3824 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, | |
3825 | RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); | |
3826 | return 0; | |
3827 | } | |
3828 | ||
3829 | switch (source) { | |
3830 | case RT5677_PLL1_S_MCLK: | |
3831 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, | |
3832 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); | |
3833 | break; | |
3834 | case RT5677_PLL1_S_BCLK1: | |
3835 | case RT5677_PLL1_S_BCLK2: | |
3836 | case RT5677_PLL1_S_BCLK3: | |
3837 | case RT5677_PLL1_S_BCLK4: | |
3838 | switch (dai->id) { | |
3839 | case RT5677_AIF1: | |
3840 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, | |
3841 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); | |
3842 | break; | |
3843 | case RT5677_AIF2: | |
3844 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, | |
3845 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); | |
3846 | break; | |
3847 | case RT5677_AIF3: | |
3848 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, | |
3849 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); | |
3850 | break; | |
3851 | case RT5677_AIF4: | |
3852 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, | |
3853 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); | |
3854 | break; | |
3855 | default: | |
3856 | break; | |
3857 | } | |
3858 | break; | |
3859 | default: | |
3860 | dev_err(codec->dev, "Unknown PLL source %d\n", source); | |
3861 | return -EINVAL; | |
3862 | } | |
3863 | ||
3864 | ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); | |
3865 | if (ret < 0) { | |
3866 | dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); | |
3867 | return ret; | |
3868 | } | |
3869 | ||
099d334e AL |
3870 | dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n", |
3871 | pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), | |
3872 | pll_code.n_code, pll_code.k_code); | |
0e826e86 OC |
3873 | |
3874 | regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, | |
099d334e | 3875 | pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); |
0e826e86 OC |
3876 | regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, |
3877 | (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT | | |
3878 | pll_code.m_bp << RT5677_PLL_M_BP_SFT); | |
3879 | ||
3880 | rt5677->pll_in = freq_in; | |
3881 | rt5677->pll_out = freq_out; | |
3882 | rt5677->pll_src = source; | |
3883 | ||
3884 | return 0; | |
3885 | } | |
3886 | ||
48561afe OC |
3887 | static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, |
3888 | unsigned int rx_mask, int slots, int slot_width) | |
3889 | { | |
3890 | struct snd_soc_codec *codec = dai->codec; | |
3891 | unsigned int val = 0; | |
3892 | ||
3893 | if (rx_mask || tx_mask) | |
3894 | val |= (1 << 12); | |
3895 | ||
3896 | switch (slots) { | |
3897 | case 4: | |
3898 | val |= (1 << 10); | |
3899 | break; | |
3900 | case 6: | |
3901 | val |= (2 << 10); | |
3902 | break; | |
3903 | case 8: | |
3904 | val |= (3 << 10); | |
3905 | break; | |
3906 | case 2: | |
3907 | default: | |
3908 | break; | |
3909 | } | |
3910 | ||
3911 | switch (slot_width) { | |
3912 | case 20: | |
3913 | val |= (1 << 8); | |
3914 | break; | |
3915 | case 24: | |
3916 | val |= (2 << 8); | |
3917 | break; | |
3918 | case 32: | |
3919 | val |= (3 << 8); | |
3920 | break; | |
3921 | case 16: | |
3922 | default: | |
3923 | break; | |
3924 | } | |
3925 | ||
3926 | switch (dai->id) { | |
3927 | case RT5677_AIF1: | |
3928 | snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val); | |
3929 | break; | |
3930 | case RT5677_AIF2: | |
3931 | snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val); | |
3932 | break; | |
3933 | default: | |
3934 | break; | |
3935 | } | |
3936 | ||
3937 | return 0; | |
3938 | } | |
3939 | ||
0e826e86 OC |
3940 | static int rt5677_set_bias_level(struct snd_soc_codec *codec, |
3941 | enum snd_soc_bias_level level) | |
3942 | { | |
3943 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
3944 | ||
3945 | switch (level) { | |
3946 | case SND_SOC_BIAS_ON: | |
3947 | break; | |
3948 | ||
3949 | case SND_SOC_BIAS_PREPARE: | |
3950 | if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { | |
af48f1d0 OC |
3951 | rt5677_set_dsp_vad(codec, false); |
3952 | ||
0e826e86 OC |
3953 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, |
3954 | RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, | |
3955 | 0x0055); | |
3956 | regmap_update_bits(rt5677->regmap, | |
3957 | RT5677_PR_BASE + RT5677_BIAS_CUR4, | |
3958 | 0x0f00, 0x0f00); | |
3959 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, | |
3960 | RT5677_PWR_VREF1 | RT5677_PWR_MB | | |
3961 | RT5677_PWR_BG | RT5677_PWR_VREF2, | |
3962 | RT5677_PWR_VREF1 | RT5677_PWR_MB | | |
3963 | RT5677_PWR_BG | RT5677_PWR_VREF2); | |
3964 | mdelay(20); | |
3965 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, | |
3966 | RT5677_PWR_FV1 | RT5677_PWR_FV2, | |
3967 | RT5677_PWR_FV1 | RT5677_PWR_FV2); | |
3968 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, | |
3969 | RT5677_PWR_CORE, RT5677_PWR_CORE); | |
3970 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, | |
3971 | 0x1, 0x1); | |
3972 | } | |
3973 | break; | |
3974 | ||
3975 | case SND_SOC_BIAS_STANDBY: | |
3976 | break; | |
3977 | ||
3978 | case SND_SOC_BIAS_OFF: | |
3979 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); | |
3980 | regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); | |
3981 | regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000); | |
f18803a3 | 3982 | regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022); |
0e826e86 OC |
3983 | regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); |
3984 | regmap_update_bits(rt5677->regmap, | |
3985 | RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); | |
af48f1d0 OC |
3986 | |
3987 | if (rt5677->dsp_vad_en) | |
3988 | rt5677_set_dsp_vad(codec, true); | |
0e826e86 OC |
3989 | break; |
3990 | ||
3991 | default: | |
3992 | break; | |
3993 | } | |
3994 | codec->dapm.bias_level = level; | |
3995 | ||
3996 | return 0; | |
3997 | } | |
3998 | ||
44caf764 OC |
3999 | #ifdef CONFIG_GPIOLIB |
4000 | static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip) | |
4001 | { | |
4002 | return container_of(chip, struct rt5677_priv, gpio_chip); | |
4003 | } | |
4004 | ||
4005 | static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
4006 | { | |
4007 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); | |
4008 | ||
4009 | switch (offset) { | |
4010 | case RT5677_GPIO1 ... RT5677_GPIO5: | |
4011 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, | |
4012 | 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1)); | |
4013 | break; | |
4014 | ||
4015 | case RT5677_GPIO6: | |
4016 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, | |
4017 | RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT); | |
4018 | break; | |
4019 | ||
4020 | default: | |
4021 | break; | |
4022 | } | |
4023 | } | |
4024 | ||
4025 | static int rt5677_gpio_direction_out(struct gpio_chip *chip, | |
4026 | unsigned offset, int value) | |
4027 | { | |
4028 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); | |
4029 | ||
4030 | switch (offset) { | |
4031 | case RT5677_GPIO1 ... RT5677_GPIO5: | |
4032 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, | |
4033 | 0x3 << (offset * 3 + 1), | |
4034 | (0x2 | !!value) << (offset * 3 + 1)); | |
4035 | break; | |
4036 | ||
4037 | case RT5677_GPIO6: | |
4038 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, | |
4039 | RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK, | |
4040 | RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT); | |
4041 | break; | |
4042 | ||
4043 | default: | |
4044 | break; | |
4045 | } | |
4046 | ||
4047 | return 0; | |
4048 | } | |
4049 | ||
4050 | static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) | |
4051 | { | |
4052 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); | |
4053 | int value, ret; | |
4054 | ||
4055 | ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); | |
4056 | if (ret < 0) | |
4057 | return ret; | |
4058 | ||
4059 | return (value & (0x1 << offset)) >> offset; | |
4060 | } | |
4061 | ||
4062 | static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) | |
4063 | { | |
4064 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); | |
4065 | ||
4066 | switch (offset) { | |
4067 | case RT5677_GPIO1 ... RT5677_GPIO5: | |
4068 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, | |
4069 | 0x1 << (offset * 3 + 2), 0x0); | |
4070 | break; | |
4071 | ||
4072 | case RT5677_GPIO6: | |
4073 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, | |
4074 | RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN); | |
4075 | break; | |
4076 | ||
4077 | default: | |
4078 | break; | |
4079 | } | |
4080 | ||
4081 | return 0; | |
4082 | } | |
4083 | ||
40eb90a1 AP |
4084 | /** Configures the gpio as |
4085 | * 0 - floating | |
4086 | * 1 - pull down | |
4087 | * 2 - pull up | |
4088 | */ | |
4089 | static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, | |
4090 | int value) | |
4091 | { | |
4092 | int shift; | |
4093 | ||
4094 | switch (offset) { | |
4095 | case RT5677_GPIO1 ... RT5677_GPIO2: | |
4096 | shift = 2 * (1 - offset); | |
4097 | regmap_update_bits(rt5677->regmap, | |
4098 | RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, | |
4099 | 0x3 << shift, | |
4100 | (value & 0x3) << shift); | |
4101 | break; | |
4102 | ||
4103 | case RT5677_GPIO3 ... RT5677_GPIO6: | |
4104 | shift = 2 * (9 - offset); | |
4105 | regmap_update_bits(rt5677->regmap, | |
4106 | RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, | |
4107 | 0x3 << shift, | |
4108 | (value & 0x3) << shift); | |
4109 | break; | |
4110 | ||
4111 | default: | |
4112 | break; | |
4113 | } | |
4114 | } | |
4115 | ||
5e3363ad OC |
4116 | static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) |
4117 | { | |
4118 | struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); | |
4119 | struct regmap_irq_chip_data *data = rt5677->irq_data; | |
4120 | int irq; | |
4121 | ||
4122 | if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) { | |
4123 | if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || | |
4124 | (rt5677->pdata.jd1_gpio == 2 && | |
4125 | offset == RT5677_GPIO2) || | |
4126 | (rt5677->pdata.jd1_gpio == 3 && | |
4127 | offset == RT5677_GPIO3)) { | |
4128 | irq = RT5677_IRQ_JD1; | |
4129 | } else { | |
4130 | return -ENXIO; | |
4131 | } | |
4132 | } | |
4133 | ||
4134 | if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) { | |
4135 | if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || | |
4136 | (rt5677->pdata.jd2_gpio == 2 && | |
4137 | offset == RT5677_GPIO5) || | |
4138 | (rt5677->pdata.jd2_gpio == 3 && | |
4139 | offset == RT5677_GPIO6)) { | |
4140 | irq = RT5677_IRQ_JD2; | |
4141 | } else if ((rt5677->pdata.jd3_gpio == 1 && | |
4142 | offset == RT5677_GPIO4) || | |
4143 | (rt5677->pdata.jd3_gpio == 2 && | |
4144 | offset == RT5677_GPIO5) || | |
4145 | (rt5677->pdata.jd3_gpio == 3 && | |
4146 | offset == RT5677_GPIO6)) { | |
4147 | irq = RT5677_IRQ_JD3; | |
4148 | } else { | |
4149 | return -ENXIO; | |
4150 | } | |
4151 | } | |
4152 | ||
4153 | return regmap_irq_get_virq(data, irq); | |
4154 | } | |
4155 | ||
44caf764 OC |
4156 | static struct gpio_chip rt5677_template_chip = { |
4157 | .label = "rt5677", | |
4158 | .owner = THIS_MODULE, | |
4159 | .direction_output = rt5677_gpio_direction_out, | |
4160 | .set = rt5677_gpio_set, | |
4161 | .direction_input = rt5677_gpio_direction_in, | |
4162 | .get = rt5677_gpio_get, | |
5e3363ad | 4163 | .to_irq = rt5677_to_irq, |
44caf764 OC |
4164 | .can_sleep = 1, |
4165 | }; | |
4166 | ||
4167 | static void rt5677_init_gpio(struct i2c_client *i2c) | |
4168 | { | |
4169 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); | |
4170 | int ret; | |
4171 | ||
4172 | rt5677->gpio_chip = rt5677_template_chip; | |
4173 | rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; | |
4174 | rt5677->gpio_chip.dev = &i2c->dev; | |
4175 | rt5677->gpio_chip.base = -1; | |
4176 | ||
4177 | ret = gpiochip_add(&rt5677->gpio_chip); | |
4178 | if (ret != 0) | |
4179 | dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); | |
4180 | } | |
4181 | ||
4182 | static void rt5677_free_gpio(struct i2c_client *i2c) | |
4183 | { | |
4184 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); | |
44caf764 | 4185 | |
5d5e63af | 4186 | gpiochip_remove(&rt5677->gpio_chip); |
44caf764 OC |
4187 | } |
4188 | #else | |
45b6e1d3 AP |
4189 | static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, |
4190 | int value) | |
4191 | { | |
4192 | } | |
4193 | ||
44caf764 OC |
4194 | static void rt5677_init_gpio(struct i2c_client *i2c) |
4195 | { | |
4196 | } | |
4197 | ||
4198 | static void rt5677_free_gpio(struct i2c_client *i2c) | |
4199 | { | |
4200 | } | |
4201 | #endif | |
4202 | ||
0e826e86 OC |
4203 | static int rt5677_probe(struct snd_soc_codec *codec) |
4204 | { | |
4205 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
40eb90a1 | 4206 | int i; |
0e826e86 OC |
4207 | |
4208 | rt5677->codec = codec; | |
4209 | ||
2d15d974 BL |
4210 | if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { |
4211 | snd_soc_dapm_add_routes(&codec->dapm, | |
4212 | rt5677_dmic2_clk_2, | |
4213 | ARRAY_SIZE(rt5677_dmic2_clk_2)); | |
4214 | } else { /*use dmic1 clock by default*/ | |
4215 | snd_soc_dapm_add_routes(&codec->dapm, | |
4216 | rt5677_dmic2_clk_1, | |
4217 | ARRAY_SIZE(rt5677_dmic2_clk_1)); | |
4218 | } | |
4219 | ||
0e826e86 OC |
4220 | rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF); |
4221 | ||
4222 | regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020); | |
4223 | regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00); | |
4224 | ||
40eb90a1 AP |
4225 | for (i = 0; i < RT5677_GPIO_NUM; i++) |
4226 | rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); | |
4227 | ||
5e3363ad OC |
4228 | if (rt5677->irq_data) { |
4229 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000, | |
4230 | 0x8000); | |
4231 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018, | |
4232 | 0x0008); | |
4233 | ||
4234 | if (rt5677->pdata.jd1_gpio) | |
4235 | regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, | |
4236 | RT5677_SEL_GPIO_JD1_MASK, | |
4237 | rt5677->pdata.jd1_gpio << | |
4238 | RT5677_SEL_GPIO_JD1_SFT); | |
4239 | ||
4240 | if (rt5677->pdata.jd2_gpio) | |
4241 | regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, | |
4242 | RT5677_SEL_GPIO_JD2_MASK, | |
4243 | rt5677->pdata.jd2_gpio << | |
4244 | RT5677_SEL_GPIO_JD2_SFT); | |
4245 | ||
4246 | if (rt5677->pdata.jd3_gpio) | |
4247 | regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, | |
4248 | RT5677_SEL_GPIO_JD3_MASK, | |
4249 | rt5677->pdata.jd3_gpio << | |
4250 | RT5677_SEL_GPIO_JD3_SFT); | |
4251 | } | |
4252 | ||
af48f1d0 OC |
4253 | mutex_init(&rt5677->dsp_cmd_lock); |
4254 | ||
0e826e86 OC |
4255 | return 0; |
4256 | } | |
4257 | ||
4258 | static int rt5677_remove(struct snd_soc_codec *codec) | |
4259 | { | |
4260 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
4261 | ||
4262 | regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); | |
f9f6a592 AP |
4263 | if (gpio_is_valid(rt5677->pow_ldo2)) |
4264 | gpio_set_value_cansleep(rt5677->pow_ldo2, 0); | |
0e826e86 OC |
4265 | |
4266 | return 0; | |
4267 | } | |
4268 | ||
4269 | #ifdef CONFIG_PM | |
4270 | static int rt5677_suspend(struct snd_soc_codec *codec) | |
4271 | { | |
4272 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
4273 | ||
af48f1d0 OC |
4274 | if (!rt5677->dsp_vad_en) { |
4275 | regcache_cache_only(rt5677->regmap, true); | |
4276 | regcache_mark_dirty(rt5677->regmap); | |
4277 | } | |
4278 | ||
f9f6a592 AP |
4279 | if (gpio_is_valid(rt5677->pow_ldo2)) |
4280 | gpio_set_value_cansleep(rt5677->pow_ldo2, 0); | |
0e826e86 OC |
4281 | |
4282 | return 0; | |
4283 | } | |
4284 | ||
4285 | static int rt5677_resume(struct snd_soc_codec *codec) | |
4286 | { | |
4287 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); | |
4288 | ||
f9f6a592 AP |
4289 | if (gpio_is_valid(rt5677->pow_ldo2)) { |
4290 | gpio_set_value_cansleep(rt5677->pow_ldo2, 1); | |
4291 | msleep(10); | |
4292 | } | |
af48f1d0 OC |
4293 | |
4294 | if (!rt5677->dsp_vad_en) { | |
4295 | regcache_cache_only(rt5677->regmap, false); | |
4296 | regcache_sync(rt5677->regmap); | |
4297 | } | |
0e826e86 OC |
4298 | |
4299 | return 0; | |
4300 | } | |
4301 | #else | |
4302 | #define rt5677_suspend NULL | |
4303 | #define rt5677_resume NULL | |
4304 | #endif | |
4305 | ||
19ba484d OC |
4306 | static int rt5677_read(void *context, unsigned int reg, unsigned int *val) |
4307 | { | |
4308 | struct i2c_client *client = context; | |
4309 | struct rt5677_priv *rt5677 = i2c_get_clientdata(client); | |
4310 | ||
4311 | if (rt5677->is_dsp_mode) | |
4312 | rt5677_dsp_mode_i2c_read(rt5677, reg, val); | |
4313 | else | |
4314 | regmap_read(rt5677->regmap_physical, reg, val); | |
4315 | ||
4316 | return 0; | |
4317 | } | |
4318 | ||
4319 | static int rt5677_write(void *context, unsigned int reg, unsigned int val) | |
4320 | { | |
4321 | struct i2c_client *client = context; | |
4322 | struct rt5677_priv *rt5677 = i2c_get_clientdata(client); | |
4323 | ||
4324 | if (rt5677->is_dsp_mode) | |
4325 | rt5677_dsp_mode_i2c_write(rt5677, reg, val); | |
4326 | else | |
4327 | regmap_write(rt5677->regmap_physical, reg, val); | |
4328 | ||
4329 | return 0; | |
4330 | } | |
4331 | ||
0e826e86 OC |
4332 | #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 |
4333 | #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
4334 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | |
4335 | ||
4336 | static struct snd_soc_dai_ops rt5677_aif_dai_ops = { | |
4337 | .hw_params = rt5677_hw_params, | |
4338 | .set_fmt = rt5677_set_dai_fmt, | |
4339 | .set_sysclk = rt5677_set_dai_sysclk, | |
4340 | .set_pll = rt5677_set_dai_pll, | |
48561afe | 4341 | .set_tdm_slot = rt5677_set_tdm_slot, |
0e826e86 OC |
4342 | }; |
4343 | ||
4344 | static struct snd_soc_dai_driver rt5677_dai[] = { | |
4345 | { | |
4346 | .name = "rt5677-aif1", | |
4347 | .id = RT5677_AIF1, | |
4348 | .playback = { | |
4349 | .stream_name = "AIF1 Playback", | |
4350 | .channels_min = 1, | |
4351 | .channels_max = 2, | |
4352 | .rates = RT5677_STEREO_RATES, | |
4353 | .formats = RT5677_FORMATS, | |
4354 | }, | |
4355 | .capture = { | |
4356 | .stream_name = "AIF1 Capture", | |
4357 | .channels_min = 1, | |
4358 | .channels_max = 2, | |
4359 | .rates = RT5677_STEREO_RATES, | |
4360 | .formats = RT5677_FORMATS, | |
4361 | }, | |
4362 | .ops = &rt5677_aif_dai_ops, | |
4363 | }, | |
4364 | { | |
4365 | .name = "rt5677-aif2", | |
4366 | .id = RT5677_AIF2, | |
4367 | .playback = { | |
4368 | .stream_name = "AIF2 Playback", | |
4369 | .channels_min = 1, | |
4370 | .channels_max = 2, | |
4371 | .rates = RT5677_STEREO_RATES, | |
4372 | .formats = RT5677_FORMATS, | |
4373 | }, | |
4374 | .capture = { | |
4375 | .stream_name = "AIF2 Capture", | |
4376 | .channels_min = 1, | |
4377 | .channels_max = 2, | |
4378 | .rates = RT5677_STEREO_RATES, | |
4379 | .formats = RT5677_FORMATS, | |
4380 | }, | |
4381 | .ops = &rt5677_aif_dai_ops, | |
4382 | }, | |
4383 | { | |
4384 | .name = "rt5677-aif3", | |
4385 | .id = RT5677_AIF3, | |
4386 | .playback = { | |
4387 | .stream_name = "AIF3 Playback", | |
4388 | .channels_min = 1, | |
4389 | .channels_max = 2, | |
4390 | .rates = RT5677_STEREO_RATES, | |
4391 | .formats = RT5677_FORMATS, | |
4392 | }, | |
4393 | .capture = { | |
4394 | .stream_name = "AIF3 Capture", | |
4395 | .channels_min = 1, | |
4396 | .channels_max = 2, | |
4397 | .rates = RT5677_STEREO_RATES, | |
4398 | .formats = RT5677_FORMATS, | |
4399 | }, | |
4400 | .ops = &rt5677_aif_dai_ops, | |
4401 | }, | |
4402 | { | |
4403 | .name = "rt5677-aif4", | |
4404 | .id = RT5677_AIF4, | |
4405 | .playback = { | |
4406 | .stream_name = "AIF4 Playback", | |
4407 | .channels_min = 1, | |
4408 | .channels_max = 2, | |
4409 | .rates = RT5677_STEREO_RATES, | |
4410 | .formats = RT5677_FORMATS, | |
4411 | }, | |
4412 | .capture = { | |
4413 | .stream_name = "AIF4 Capture", | |
4414 | .channels_min = 1, | |
4415 | .channels_max = 2, | |
4416 | .rates = RT5677_STEREO_RATES, | |
4417 | .formats = RT5677_FORMATS, | |
4418 | }, | |
4419 | .ops = &rt5677_aif_dai_ops, | |
4420 | }, | |
4421 | { | |
4422 | .name = "rt5677-slimbus", | |
4423 | .id = RT5677_AIF5, | |
4424 | .playback = { | |
4425 | .stream_name = "SLIMBus Playback", | |
4426 | .channels_min = 1, | |
4427 | .channels_max = 2, | |
4428 | .rates = RT5677_STEREO_RATES, | |
4429 | .formats = RT5677_FORMATS, | |
4430 | }, | |
4431 | .capture = { | |
4432 | .stream_name = "SLIMBus Capture", | |
4433 | .channels_min = 1, | |
4434 | .channels_max = 2, | |
4435 | .rates = RT5677_STEREO_RATES, | |
4436 | .formats = RT5677_FORMATS, | |
4437 | }, | |
4438 | .ops = &rt5677_aif_dai_ops, | |
4439 | }, | |
4440 | }; | |
4441 | ||
4442 | static struct snd_soc_codec_driver soc_codec_dev_rt5677 = { | |
4443 | .probe = rt5677_probe, | |
4444 | .remove = rt5677_remove, | |
4445 | .suspend = rt5677_suspend, | |
4446 | .resume = rt5677_resume, | |
4447 | .set_bias_level = rt5677_set_bias_level, | |
4448 | .idle_bias_off = true, | |
4449 | .controls = rt5677_snd_controls, | |
4450 | .num_controls = ARRAY_SIZE(rt5677_snd_controls), | |
4451 | .dapm_widgets = rt5677_dapm_widgets, | |
4452 | .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), | |
4453 | .dapm_routes = rt5677_dapm_routes, | |
4454 | .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), | |
4455 | }; | |
4456 | ||
19ba484d OC |
4457 | static const struct regmap_config rt5677_regmap_physical = { |
4458 | .name = "physical", | |
4459 | .reg_bits = 8, | |
4460 | .val_bits = 16, | |
4461 | ||
4462 | .max_register = RT5677_VENDOR_ID2 + 1, | |
4463 | .readable_reg = rt5677_readable_register, | |
4464 | ||
4465 | .cache_type = REGCACHE_NONE, | |
4466 | }; | |
4467 | ||
0e826e86 OC |
4468 | static const struct regmap_config rt5677_regmap = { |
4469 | .reg_bits = 8, | |
4470 | .val_bits = 16, | |
4471 | ||
4472 | .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * | |
4473 | RT5677_PR_SPACING), | |
4474 | ||
4475 | .volatile_reg = rt5677_volatile_register, | |
4476 | .readable_reg = rt5677_readable_register, | |
19ba484d OC |
4477 | .reg_read = rt5677_read, |
4478 | .reg_write = rt5677_write, | |
0e826e86 OC |
4479 | |
4480 | .cache_type = REGCACHE_RBTREE, | |
4481 | .reg_defaults = rt5677_reg, | |
4482 | .num_reg_defaults = ARRAY_SIZE(rt5677_reg), | |
4483 | .ranges = rt5677_ranges, | |
4484 | .num_ranges = ARRAY_SIZE(rt5677_ranges), | |
4485 | }; | |
4486 | ||
4487 | static const struct i2c_device_id rt5677_i2c_id[] = { | |
4488 | { "rt5677", 0 }, | |
4489 | { } | |
4490 | }; | |
4491 | MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id); | |
4492 | ||
f9f6a592 AP |
4493 | static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np) |
4494 | { | |
6f67c380 AP |
4495 | rt5677->pdata.in1_diff = of_property_read_bool(np, |
4496 | "realtek,in1-differential"); | |
4497 | rt5677->pdata.in2_diff = of_property_read_bool(np, | |
4498 | "realtek,in2-differential"); | |
4499 | rt5677->pdata.lout1_diff = of_property_read_bool(np, | |
4500 | "realtek,lout1-differential"); | |
4501 | rt5677->pdata.lout2_diff = of_property_read_bool(np, | |
4502 | "realtek,lout2-differential"); | |
4503 | rt5677->pdata.lout3_diff = of_property_read_bool(np, | |
4504 | "realtek,lout3-differential"); | |
4505 | ||
f9f6a592 AP |
4506 | rt5677->pow_ldo2 = of_get_named_gpio(np, |
4507 | "realtek,pow-ldo2-gpio", 0); | |
4508 | ||
4509 | /* | |
4510 | * POW_LDO2 is optional (it may be statically tied on the board). | |
4511 | * -ENOENT means that the property doesn't exist, i.e. there is no | |
4512 | * GPIO, so is not an error. Any other error code means the property | |
4513 | * exists, but could not be parsed. | |
4514 | */ | |
4515 | if (!gpio_is_valid(rt5677->pow_ldo2) && | |
4516 | (rt5677->pow_ldo2 != -ENOENT)) | |
4517 | return rt5677->pow_ldo2; | |
4518 | ||
40eb90a1 AP |
4519 | of_property_read_u8_array(np, "realtek,gpio-config", |
4520 | rt5677->pdata.gpio_config, RT5677_GPIO_NUM); | |
4521 | ||
5e3363ad OC |
4522 | of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio); |
4523 | of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio); | |
4524 | of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio); | |
4525 | ||
f9f6a592 AP |
4526 | return 0; |
4527 | } | |
4528 | ||
5e3363ad OC |
4529 | static struct regmap_irq rt5677_irqs[] = { |
4530 | [RT5677_IRQ_JD1] = { | |
4531 | .reg_offset = 0, | |
4532 | .mask = RT5677_EN_IRQ_GPIO_JD1, | |
4533 | }, | |
4534 | [RT5677_IRQ_JD2] = { | |
4535 | .reg_offset = 0, | |
4536 | .mask = RT5677_EN_IRQ_GPIO_JD2, | |
4537 | }, | |
4538 | [RT5677_IRQ_JD3] = { | |
4539 | .reg_offset = 0, | |
4540 | .mask = RT5677_EN_IRQ_GPIO_JD3, | |
4541 | }, | |
4542 | }; | |
4543 | ||
4544 | static struct regmap_irq_chip rt5677_irq_chip = { | |
4545 | .name = "rt5677", | |
4546 | .irqs = rt5677_irqs, | |
4547 | .num_irqs = ARRAY_SIZE(rt5677_irqs), | |
4548 | ||
4549 | .num_regs = 1, | |
4550 | .status_base = RT5677_IRQ_CTRL1, | |
4551 | .mask_base = RT5677_IRQ_CTRL1, | |
4552 | .mask_invert = 1, | |
4553 | }; | |
4554 | ||
35d40d10 | 4555 | static int rt5677_init_irq(struct i2c_client *i2c) |
5e3363ad OC |
4556 | { |
4557 | int ret; | |
4558 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); | |
4559 | ||
4560 | if (!rt5677->pdata.jd1_gpio && | |
4561 | !rt5677->pdata.jd2_gpio && | |
4562 | !rt5677->pdata.jd3_gpio) | |
4563 | return 0; | |
4564 | ||
4565 | if (!i2c->irq) { | |
4566 | dev_err(&i2c->dev, "No interrupt specified\n"); | |
4567 | return -EINVAL; | |
4568 | } | |
4569 | ||
4570 | ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq, | |
4571 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0, | |
4572 | &rt5677_irq_chip, &rt5677->irq_data); | |
4573 | ||
4574 | if (ret != 0) { | |
4575 | dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret); | |
4576 | return ret; | |
4577 | } | |
4578 | ||
4579 | return 0; | |
4580 | } | |
4581 | ||
35d40d10 | 4582 | static void rt5677_free_irq(struct i2c_client *i2c) |
5e3363ad OC |
4583 | { |
4584 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); | |
4585 | ||
4586 | if (rt5677->irq_data) | |
4587 | regmap_del_irq_chip(i2c->irq, rt5677->irq_data); | |
4588 | } | |
4589 | ||
0e826e86 OC |
4590 | static int rt5677_i2c_probe(struct i2c_client *i2c, |
4591 | const struct i2c_device_id *id) | |
4592 | { | |
4593 | struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev); | |
4594 | struct rt5677_priv *rt5677; | |
4595 | int ret; | |
4596 | unsigned int val; | |
4597 | ||
4598 | rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), | |
4599 | GFP_KERNEL); | |
4600 | if (rt5677 == NULL) | |
4601 | return -ENOMEM; | |
4602 | ||
4603 | i2c_set_clientdata(i2c, rt5677); | |
4604 | ||
4605 | if (pdata) | |
4606 | rt5677->pdata = *pdata; | |
4607 | ||
f9f6a592 AP |
4608 | if (i2c->dev.of_node) { |
4609 | ret = rt5677_parse_dt(rt5677, i2c->dev.of_node); | |
4610 | if (ret) { | |
4611 | dev_err(&i2c->dev, "Failed to parse device tree: %d\n", | |
4612 | ret); | |
4613 | return ret; | |
4614 | } | |
4615 | } else { | |
4616 | rt5677->pow_ldo2 = -EINVAL; | |
4617 | } | |
4618 | ||
4619 | if (gpio_is_valid(rt5677->pow_ldo2)) { | |
4620 | ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2, | |
4621 | GPIOF_OUT_INIT_HIGH, | |
4622 | "RT5677 POW_LDO2"); | |
4623 | if (ret < 0) { | |
4624 | dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n", | |
4625 | rt5677->pow_ldo2, ret); | |
4626 | return ret; | |
4627 | } | |
4628 | /* Wait a while until I2C bus becomes available. The datasheet | |
4629 | * does not specify the exact we should wait but startup | |
4630 | * sequence mentiones at least a few milliseconds. | |
4631 | */ | |
4632 | msleep(10); | |
4633 | } | |
4634 | ||
19ba484d OC |
4635 | rt5677->regmap_physical = devm_regmap_init_i2c(i2c, |
4636 | &rt5677_regmap_physical); | |
4637 | if (IS_ERR(rt5677->regmap_physical)) { | |
4638 | ret = PTR_ERR(rt5677->regmap_physical); | |
4639 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
4640 | ret); | |
4641 | return ret; | |
4642 | } | |
4643 | ||
4644 | rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); | |
0e826e86 OC |
4645 | if (IS_ERR(rt5677->regmap)) { |
4646 | ret = PTR_ERR(rt5677->regmap); | |
4647 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
4648 | ret); | |
4649 | return ret; | |
4650 | } | |
4651 | ||
4652 | regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); | |
4653 | if (val != RT5677_DEVICE_ID) { | |
4654 | dev_err(&i2c->dev, | |
4655 | "Device with ID register %x is not rt5677\n", val); | |
4656 | return -ENODEV; | |
4657 | } | |
4658 | ||
4659 | regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); | |
4660 | ||
4661 | ret = regmap_register_patch(rt5677->regmap, init_list, | |
4662 | ARRAY_SIZE(init_list)); | |
4663 | if (ret != 0) | |
4664 | dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); | |
4665 | ||
4666 | if (rt5677->pdata.in1_diff) | |
4667 | regmap_update_bits(rt5677->regmap, RT5677_IN1, | |
4668 | RT5677_IN_DF1, RT5677_IN_DF1); | |
4669 | ||
4670 | if (rt5677->pdata.in2_diff) | |
4671 | regmap_update_bits(rt5677->regmap, RT5677_IN1, | |
4672 | RT5677_IN_DF2, RT5677_IN_DF2); | |
4673 | ||
6f67c380 AP |
4674 | if (rt5677->pdata.lout1_diff) |
4675 | regmap_update_bits(rt5677->regmap, RT5677_LOUT1, | |
4676 | RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); | |
4677 | ||
4678 | if (rt5677->pdata.lout2_diff) | |
4679 | regmap_update_bits(rt5677->regmap, RT5677_LOUT1, | |
4680 | RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); | |
4681 | ||
4682 | if (rt5677->pdata.lout3_diff) | |
4683 | regmap_update_bits(rt5677->regmap, RT5677_LOUT1, | |
4684 | RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); | |
4685 | ||
2d15d974 BL |
4686 | if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { |
4687 | regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, | |
4688 | RT5677_GPIO5_FUNC_MASK, | |
4689 | RT5677_GPIO5_FUNC_DMIC); | |
4690 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, | |
4691 | RT5677_GPIO5_DIR_MASK, | |
4692 | RT5677_GPIO5_DIR_OUT); | |
4693 | } | |
4694 | ||
44caf764 | 4695 | rt5677_init_gpio(i2c); |
35d40d10 | 4696 | rt5677_init_irq(i2c); |
44caf764 | 4697 | |
d0bdcb91 AL |
4698 | return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677, |
4699 | rt5677_dai, ARRAY_SIZE(rt5677_dai)); | |
0e826e86 OC |
4700 | } |
4701 | ||
4702 | static int rt5677_i2c_remove(struct i2c_client *i2c) | |
4703 | { | |
4704 | snd_soc_unregister_codec(&i2c->dev); | |
35d40d10 | 4705 | rt5677_free_irq(i2c); |
44caf764 | 4706 | rt5677_free_gpio(i2c); |
0e826e86 OC |
4707 | |
4708 | return 0; | |
4709 | } | |
4710 | ||
4711 | static struct i2c_driver rt5677_i2c_driver = { | |
4712 | .driver = { | |
4713 | .name = "rt5677", | |
4714 | .owner = THIS_MODULE, | |
4715 | }, | |
4716 | .probe = rt5677_i2c_probe, | |
4717 | .remove = rt5677_i2c_remove, | |
4718 | .id_table = rt5677_i2c_id, | |
4719 | }; | |
c8cfbec8 | 4720 | module_i2c_driver(rt5677_i2c_driver); |
0e826e86 OC |
4721 | |
4722 | MODULE_DESCRIPTION("ASoC RT5677 driver"); | |
4723 | MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); | |
4724 | MODULE_LICENSE("GPL v2"); |