]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - sound/soc/codecs/rt5677.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: rt5677: Add the chip type to distinguish the setting of the clock source
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / rt5677.c
CommitLineData
0e826e86
OC		 1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
f9f6a592 18#include <linux/of_gpio.h>
0e826e86
OC		 19#include <linux/regmap.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
af48f1d0 23#include <linux/firmware.h>
44caf764 24#include <linux/gpio.h>
0e826e86
OC		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
30f14b43 33#include "rl6231.h"
0e826e86 34#include "rt5677.h"
af48f1d0 35#include "rt5677-spi.h"
0e826e86
OC		 36
37#define RT5677_DEVICE_ID 0x6327
38
39#define RT5677_PR_RANGE_BASE (0xff + 1)
40#define RT5677_PR_SPACING 0x100
41
42#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44static const struct regmap_range_cfg rt5677_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
53 .window_len = 0x1,
54 },
55};
56
57static const struct reg_default init_list[] = {
2dfe2b08
OC		 58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
0e826e86
OC		 65};
66#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
67
68static const struct reg_default rt5677_reg[] = {
69 {RT5677_RESET , 0x0000},
70 {RT5677_LOUT1 , 0xa800},
71 {RT5677_IN1 , 0x0000},
72 {RT5677_MICBIAS , 0x0000},
73 {RT5677_SLIMBUS_PARAM , 0x0000},
74 {RT5677_SLIMBUS_RX , 0x0000},
75 {RT5677_SLIMBUS_CTRL , 0x0000},
76 {RT5677_SIDETONE_CTRL , 0x000b},
77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
79 {RT5677_DAC4_DIG_VOL , 0xafaf},
80 {RT5677_DAC3_DIG_VOL , 0xafaf},
81 {RT5677_DAC1_DIG_VOL , 0xafaf},
82 {RT5677_DAC2_DIG_VOL , 0xafaf},
83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO1_2_ADC_BST , 0x0000},
87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_ADC_BST_CTRL2 , 0x0000},
89 {RT5677_STO3_4_ADC_BST , 0x0000},
90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
92 {RT5677_STO4_ADC_MIXER , 0xd4c0},
93 {RT5677_STO3_ADC_MIXER , 0xd4c0},
94 {RT5677_STO2_ADC_MIXER , 0xd4c0},
95 {RT5677_STO1_ADC_MIXER , 0xd4c0},
96 {RT5677_MONO_ADC_MIXER , 0xd4d1},
97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
98 {RT5677_STO1_DAC_MIXER , 0xaaaa},
99 {RT5677_MONO_DAC_MIXER , 0xaaaa},
100 {RT5677_DD1_MIXER , 0xaaaa},
101 {RT5677_DD2_MIXER , 0xaaaa},
102 {RT5677_IF3_DATA , 0x0000},
103 {RT5677_IF4_DATA , 0x0000},
104 {RT5677_PDM_OUT_CTRL , 0x8888},
105 {RT5677_PDM_DATA_CTRL1 , 0x0000},
106 {RT5677_PDM_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
113 {RT5677_TDM1_CTRL1 , 0x0300},
114 {RT5677_TDM1_CTRL2 , 0x0000},
115 {RT5677_TDM1_CTRL3 , 0x4000},
116 {RT5677_TDM1_CTRL4 , 0x0123},
117 {RT5677_TDM1_CTRL5 , 0x4567},
118 {RT5677_TDM2_CTRL1 , 0x0300},
119 {RT5677_TDM2_CTRL2 , 0x0000},
120 {RT5677_TDM2_CTRL3 , 0x4000},
121 {RT5677_TDM2_CTRL4 , 0x0123},
122 {RT5677_TDM2_CTRL5 , 0x4567},
123 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
124 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
131 {RT5677_DMIC_CTRL1 , 0x1505},
132 {RT5677_DMIC_CTRL2 , 0x0055},
133 {RT5677_HAP_GENE_CTRL1 , 0x0111},
134 {RT5677_HAP_GENE_CTRL2 , 0x0064},
135 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL9 , 0xf000},
142 {RT5677_HAP_GENE_CTRL10 , 0x0000},
143 {RT5677_PWR_DIG1 , 0x0000},
144 {RT5677_PWR_DIG2 , 0x0000},
145 {RT5677_PWR_ANLG1 , 0x0055},
146 {RT5677_PWR_ANLG2 , 0x0000},
147 {RT5677_PWR_DSP1 , 0x0001},
148 {RT5677_PWR_DSP_ST , 0x0000},
149 {RT5677_PWR_DSP2 , 0x0000},
150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
151 {RT5677_PRIV_INDEX , 0x0000},
152 {RT5677_PRIV_DATA , 0x0000},
153 {RT5677_I2S4_SDP , 0x8000},
154 {RT5677_I2S1_SDP , 0x8000},
155 {RT5677_I2S2_SDP , 0x8000},
156 {RT5677_I2S3_SDP , 0x8000},
157 {RT5677_CLK_TREE_CTRL1 , 0x1111},
158 {RT5677_CLK_TREE_CTRL2 , 0x1111},
159 {RT5677_CLK_TREE_CTRL3 , 0x0000},
160 {RT5677_PLL1_CTRL1 , 0x0000},
161 {RT5677_PLL1_CTRL2 , 0x0000},
162 {RT5677_PLL2_CTRL1 , 0x0c60},
163 {RT5677_PLL2_CTRL2 , 0x2000},
164 {RT5677_GLB_CLK1 , 0x0000},
165 {RT5677_GLB_CLK2 , 0x0000},
166 {RT5677_ASRC_1 , 0x0000},
167 {RT5677_ASRC_2 , 0x0000},
168 {RT5677_ASRC_3 , 0x0000},
169 {RT5677_ASRC_4 , 0x0000},
170 {RT5677_ASRC_5 , 0x0000},
171 {RT5677_ASRC_6 , 0x0000},
172 {RT5677_ASRC_7 , 0x0000},
173 {RT5677_ASRC_8 , 0x0000},
174 {RT5677_ASRC_9 , 0x0000},
175 {RT5677_ASRC_10 , 0x0000},
176 {RT5677_ASRC_11 , 0x0000},
86ae04b1 177 {RT5677_ASRC_12 , 0x0018},
0e826e86
OC		 178 {RT5677_ASRC_13 , 0x0000},
179 {RT5677_ASRC_14 , 0x0000},
180 {RT5677_ASRC_15 , 0x0000},
181 {RT5677_ASRC_16 , 0x0000},
182 {RT5677_ASRC_17 , 0x0000},
183 {RT5677_ASRC_18 , 0x0000},
184 {RT5677_ASRC_19 , 0x0000},
185 {RT5677_ASRC_20 , 0x0000},
186 {RT5677_ASRC_21 , 0x000c},
187 {RT5677_ASRC_22 , 0x0000},
188 {RT5677_ASRC_23 , 0x0000},
189 {RT5677_VAD_CTRL1 , 0x2184},
190 {RT5677_VAD_CTRL2 , 0x010a},
191 {RT5677_VAD_CTRL3 , 0x0aea},
192 {RT5677_VAD_CTRL4 , 0x000c},
193 {RT5677_VAD_CTRL5 , 0x0000},
194 {RT5677_DSP_INB_CTRL1 , 0x0000},
195 {RT5677_DSP_INB_CTRL2 , 0x0000},
196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
201 {RT5677_ADC_EQ_CTRL1 , 0x6000},
202 {RT5677_ADC_EQ_CTRL2 , 0x0000},
203 {RT5677_EQ_CTRL1 , 0xc000},
204 {RT5677_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL3 , 0x0000},
206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
207 {RT5677_JD_CTRL1 , 0x0000},
208 {RT5677_JD_CTRL2 , 0x0000},
209 {RT5677_JD_CTRL3 , 0x0000},
210 {RT5677_IRQ_CTRL1 , 0x0000},
211 {RT5677_IRQ_CTRL2 , 0x0000},
212 {RT5677_GPIO_ST , 0x0000},
213 {RT5677_GPIO_CTRL1 , 0x0000},
214 {RT5677_GPIO_CTRL2 , 0x0000},
215 {RT5677_GPIO_CTRL3 , 0x0000},
216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_MB_DRC_CTRL1 , 0x0f20},
227 {RT5677_DRC1_CTRL1 , 0x001f},
228 {RT5677_DRC1_CTRL2 , 0x020c},
229 {RT5677_DRC1_CTRL3 , 0x1f00},
230 {RT5677_DRC1_CTRL4 , 0x0000},
231 {RT5677_DRC1_CTRL5 , 0x0000},
232 {RT5677_DRC1_CTRL6 , 0x0029},
233 {RT5677_DRC2_CTRL1 , 0x001f},
234 {RT5677_DRC2_CTRL2 , 0x020c},
235 {RT5677_DRC2_CTRL3 , 0x1f00},
236 {RT5677_DRC2_CTRL4 , 0x0000},
237 {RT5677_DRC2_CTRL5 , 0x0000},
238 {RT5677_DRC2_CTRL6 , 0x0029},
239 {RT5677_DRC1_HL_CTRL1 , 0x8000},
240 {RT5677_DRC1_HL_CTRL2 , 0x0200},
241 {RT5677_DRC2_HL_CTRL1 , 0x8000},
242 {RT5677_DRC2_HL_CTRL2 , 0x0200},
243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
266 {RT5677_DIG_MISC , 0x0000},
267 {RT5677_GEN_CTRL1 , 0x0000},
268 {RT5677_GEN_CTRL2 , 0x0000},
269 {RT5677_VENDOR_ID , 0x0000},
270 {RT5677_VENDOR_ID1 , 0x10ec},
271 {RT5677_VENDOR_ID2 , 0x6327},
272};
273
274static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
275{
276 int i;
277
278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
279 if (reg >= rt5677_ranges[i].range_min &&
280 reg <= rt5677_ranges[i].range_max) {
281 return true;
282 }
283 }
284
285 switch (reg) {
286 case RT5677_RESET:
287 case RT5677_SLIMBUS_PARAM:
288 case RT5677_PDM_DATA_CTRL1:
289 case RT5677_PDM_DATA_CTRL2:
290 case RT5677_PDM1_DATA_CTRL4:
291 case RT5677_PDM2_DATA_CTRL4:
292 case RT5677_I2C_MASTER_CTRL1:
293 case RT5677_I2C_MASTER_CTRL7:
294 case RT5677_I2C_MASTER_CTRL8:
295 case RT5677_HAP_GENE_CTRL2:
296 case RT5677_PWR_DSP_ST:
297 case RT5677_PRIV_DATA:
298 case RT5677_PLL1_CTRL2:
299 case RT5677_PLL2_CTRL2:
300 case RT5677_ASRC_22:
301 case RT5677_ASRC_23:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
307 case RT5677_GPIO_ST:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
316 return true;
317 default:
318 return false;
319 }
320}
321
322static bool rt5677_readable_register(struct device *dev, unsigned int reg)
323{
324 int i;
325
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
329 return true;
330 }
331 }
332
333 switch (reg) {
334 case RT5677_RESET:
335 case RT5677_LOUT1:
336 case RT5677_IN1:
337 case RT5677_MICBIAS:
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
431 case RT5677_ASRC_1:
432 case RT5677_ASRC_2:
433 case RT5677_ASRC_3:
434 case RT5677_ASRC_4:
435 case RT5677_ASRC_5:
436 case RT5677_ASRC_6:
437 case RT5677_ASRC_7:
438 case RT5677_ASRC_8:
439 case RT5677_ASRC_9:
440 case RT5677_ASRC_10:
441 case RT5677_ASRC_11:
442 case RT5677_ASRC_12:
443 case RT5677_ASRC_13:
444 case RT5677_ASRC_14:
445 case RT5677_ASRC_15:
446 case RT5677_ASRC_16:
447 case RT5677_ASRC_17:
448 case RT5677_ASRC_18:
449 case RT5677_ASRC_19:
450 case RT5677_ASRC_20:
451 case RT5677_ASRC_21:
452 case RT5677_ASRC_22:
453 case RT5677_ASRC_23:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
477 case RT5677_GPIO_ST:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
537 return true;
538 default:
539 return false;
540 }
541}
542
af48f1d0
OC		 543/**
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
19ba484d 545 * @rt5677: Private Data.
af48f1d0
OC		 546 * @addr: Address index.
547 * @value: Address data.
548 *
549 *
550 * Returns 0 for success or negative error code.
551 */
19ba484d 552static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
af48f1d0
OC		 553 unsigned int addr, unsigned int value, unsigned int opcode)
554{
19ba484d 555 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 556 int ret;
557
558 mutex_lock(&rt5677->dsp_cmd_lock);
559
19ba484d
OC		 560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
561 addr >> 16);
af48f1d0
OC		 562 if (ret < 0) {
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
564 goto err;
565 }
566
19ba484d 567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 568 addr & 0xffff);
569 if (ret < 0) {
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
571 goto err;
572 }
573
19ba484d 574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
af48f1d0
OC		 575 value >> 16);
576 if (ret < 0) {
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
578 goto err;
579 }
580
19ba484d 581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
af48f1d0
OC		 582 value & 0xffff);
583 if (ret < 0) {
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
585 goto err;
586 }
587
19ba484d
OC		 588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
589 opcode);
af48f1d0
OC		 590 if (ret < 0) {
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
592 goto err;
593 }
594
595err:
596 mutex_unlock(&rt5677->dsp_cmd_lock);
597
598 return ret;
599}
600
601/**
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
19ba484d 603 * rt5677: Private Data.
af48f1d0
OC		 604 * @addr: Address index.
605 * @value: Address data.
606 *
19ba484d 607 *
af48f1d0
OC		 608 * Returns 0 for success or negative error code.
609 */
610static int rt5677_dsp_mode_i2c_read_addr(
19ba484d 611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
af48f1d0 612{
19ba484d 613 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 614 int ret;
615 unsigned int msb, lsb;
616
617 mutex_lock(&rt5677->dsp_cmd_lock);
618
19ba484d
OC		 619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
620 addr >> 16);
af48f1d0
OC		 621 if (ret < 0) {
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
623 goto err;
624 }
625
19ba484d 626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 627 addr & 0xffff);
628 if (ret < 0) {
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
630 goto err;
631 }
632
19ba484d
OC		 633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
634 0x0002);
af48f1d0
OC		 635 if (ret < 0) {
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
637 goto err;
638 }
639
19ba484d
OC		 640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
af48f1d0
OC		 642 *value = (msb << 16) | lsb;
643
644err:
645 mutex_unlock(&rt5677->dsp_cmd_lock);
646
647 return ret;
648}
649
650/**
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
19ba484d 652 * rt5677: Private Data.
af48f1d0
OC		 653 * @reg: Register index.
654 * @value: Register data.
655 *
656 *
657 * Returns 0 for success or negative error code.
658 */
19ba484d 659static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
af48f1d0
OC		 660 unsigned int reg, unsigned int value)
661{
19ba484d 662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
af48f1d0
OC		 663 value, 0x0001);
664}
665
666/**
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
19ba484d 670 * @value: Register data.
af48f1d0
OC		 671 *
672 *
19ba484d 673 * Returns 0 for success or negative error code.
af48f1d0 674 */
19ba484d
OC		 675static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
af48f1d0 677{
19ba484d
OC		 678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
679 value);
af48f1d0 680
19ba484d 681 *value &= 0xffff;
af48f1d0 682
19ba484d 683 return ret;
af48f1d0
OC		 684}
685
19ba484d 686static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
af48f1d0 687{
19ba484d 688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
af48f1d0 689
19ba484d
OC		 690 if (on) {
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
693 } else {
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
af48f1d0 696 }
af48f1d0
OC		 697}
698
699static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
700{
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
703 int ret;
704
4c121129
AB		 705 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
706 return -ENXIO;
707
af48f1d0
OC		 708 if (on && !activity) {
709 activity = true;
710
711 regcache_cache_only(rt5677->regmap, false);
712 regcache_cache_bypass(rt5677->regmap, true);
713
714 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
715 regmap_update_bits(rt5677->regmap,
716 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
717 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
718 RT5677_LDO1_SEL_MASK, 0x0);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
720 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
ab1f7095
OC		 721 switch (rt5677->type) {
722 case RT5677:
723 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
724 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
725 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
726 RT5677_PLL2_PR_SRC_MASK |
727 RT5677_DSP_CLK_SRC_MASK,
728 RT5677_PLL2_PR_SRC_MCLK2 |
729 RT5677_DSP_CLK_SRC_BYPASS);
730 break;
731 case RT5676:
732 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
733 RT5677_DSP_CLK_SRC_MASK,
734 RT5677_DSP_CLK_SRC_BYPASS);
735 break;
736 default:
737 break;
738 }
af48f1d0 739 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
19ba484d
OC		 740 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
741 rt5677_set_dsp_mode(codec, true);
af48f1d0
OC		 742
743 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
744 codec->dev);
745 if (ret == 0) {
746 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
747 release_firmware(rt5677->fw1);
748 }
749
750 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
751 codec->dev);
752 if (ret == 0) {
753 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
754 release_firmware(rt5677->fw2);
755 }
756
19ba484d 757 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
af48f1d0
OC		 758
759 regcache_cache_bypass(rt5677->regmap, false);
760 regcache_cache_only(rt5677->regmap, true);
761 } else if (!on && activity) {
762 activity = false;
763
764 regcache_cache_only(rt5677->regmap, false);
765 regcache_cache_bypass(rt5677->regmap, true);
766
19ba484d
OC		 767 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
768 rt5677_set_dsp_mode(codec, false);
769 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
af48f1d0
OC		 770
771 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
772
773 regcache_cache_bypass(rt5677->regmap, false);
774 regcache_mark_dirty(rt5677->regmap);
775 regcache_sync(rt5677->regmap);
776 }
777
778 return 0;
779}
780
0e826e86 781static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
40e3262e 782static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
0e826e86 783static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
40e3262e 784static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
0e826e86 785static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
90bdbb46 786static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
0e826e86
OC		 787
788/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
789static unsigned int bst_tlv[] = {
790 TLV_DB_RANGE_HEAD(7),
791 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
792 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
793 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
794 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
795 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
796 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
797 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
798};
799
af48f1d0
OC		 800static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
801 struct snd_ctl_elem_value *ucontrol)
802{
6087fcab
FY		 803 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
804 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
af48f1d0
OC		 805
806 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
807
808 return 0;
809}
810
811static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
812 struct snd_ctl_elem_value *ucontrol)
813{
6087fcab
FY		 814 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
815 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
816 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
af48f1d0
OC		 817
818 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
819
820 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
821 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
822
823 return 0;
824}
825
0e826e86
OC		 826static const struct snd_kcontrol_new rt5677_snd_controls[] = {
827 /* OUTPUT Control */
828 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
829 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
830 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
831 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
832 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
833 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
834
835 /* DAC Digital Volume */
836 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
40e3262e 837 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 838 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
40e3262e 839 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 840 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
40e3262e 841 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 842 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
40e3262e 843 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86
OC		 844
845 /* IN1/IN2 Control */
846 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
847 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
848
849 /* ADC Digital Volume Control */
850 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
851 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
852 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
853 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
854 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
855 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
856 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
857 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
858 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
859 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
860
861 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
40e3262e 862 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 863 adc_vol_tlv),
864 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
40e3262e 865 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 866 adc_vol_tlv),
867 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
40e3262e 868 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 869 adc_vol_tlv),
870 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
40e3262e 871 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 872 adc_vol_tlv),
873 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
40e3262e 874 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 875 adc_vol_tlv),
876
90bdbb46
OC		 877 /* Sidetone Control */
878 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
879 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
880
0e826e86 881 /* ADC Boost Volume Control */
80220f29 882 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 883 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
884 adc_bst_tlv),
80220f29 885 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 886 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
887 adc_bst_tlv),
80220f29 888 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 889 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
890 adc_bst_tlv),
80220f29 891 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 892 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
893 adc_bst_tlv),
80220f29 894 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
0e826e86
OC		 895 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
896 adc_bst_tlv),
af48f1d0
OC		 897
898 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
899 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
0e826e86
OC		 900};
901
902/**
903 * set_dmic_clk - Set parameter of dmic.
904 *
905 * @w: DAPM widget.
906 * @kcontrol: The kcontrol of this widget.
907 * @event: Event id.
908 *
909 * Choose dmic clock between 1MHz and 3MHz.
910 * It is better for clock to approximate 3MHz.
911 */
912static int set_dmic_clk(struct snd_soc_dapm_widget *w,
913 struct snd_kcontrol *kcontrol, int event)
914{
46f20872 915 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86 916 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
9a53581e 917 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
0e826e86
OC		 918
919 if (idx < 0)
920 dev_err(codec->dev, "Failed to set DMIC clock\n");
921 else
922 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
923 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
924 return idx;
925}
926
927static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
928 struct snd_soc_dapm_widget *sink)
929{
46f20872
LPC		 930 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
931 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
0e826e86
OC		 932 unsigned int val;
933
934 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
935 val &= RT5677_SCLK_SRC_MASK;
936 if (val == RT5677_SCLK_SRC_PLL1)
937 return 1;
938 else
939 return 0;
940}
941
5a8c7c26
OC		 942static int is_using_asrc(struct snd_soc_dapm_widget *source,
943 struct snd_soc_dapm_widget *sink)
944{
46f20872 945 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
e4b7e6a8 946 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
5a8c7c26
OC		 947 unsigned int reg, shift, val;
948
949 if (source->reg == RT5677_ASRC_1) {
950 switch (source->shift) {
951 case 12:
952 reg = RT5677_ASRC_4;
953 shift = 0;
954 break;
955 case 13:
956 reg = RT5677_ASRC_4;
957 shift = 4;
958 break;
959 case 14:
960 reg = RT5677_ASRC_4;
961 shift = 8;
962 break;
963 case 15:
964 reg = RT5677_ASRC_4;
965 shift = 12;
966 break;
967 default:
968 return 0;
969 }
970 } else {
971 switch (source->shift) {
972 case 0:
973 reg = RT5677_ASRC_6;
974 shift = 8;
975 break;
976 case 1:
977 reg = RT5677_ASRC_6;
978 shift = 12;
979 break;
980 case 2:
981 reg = RT5677_ASRC_5;
982 shift = 0;
983 break;
984 case 3:
985 reg = RT5677_ASRC_5;
986 shift = 4;
987 break;
988 case 4:
989 reg = RT5677_ASRC_5;
990 shift = 8;
991 break;
992 case 5:
993 reg = RT5677_ASRC_5;
994 shift = 12;
995 break;
996 case 12:
997 reg = RT5677_ASRC_3;
998 shift = 0;
999 break;
1000 case 13:
1001 reg = RT5677_ASRC_3;
1002 shift = 4;
1003 break;
1004 case 14:
1005 reg = RT5677_ASRC_3;
1006 shift = 12;
1007 break;
1008 default:
1009 return 0;
1010 }
1011 }
1012
e4b7e6a8
OC		 1013 regmap_read(rt5677->regmap, reg, &val);
1014 val = (val >> shift) & 0xf;
1015
5a8c7c26
OC		 1016 switch (val) {
1017 case 1 ... 6:
1018 return 1;
1019 default:
1020 return 0;
1021 }
1022
1023}
1024
1025static int can_use_asrc(struct snd_soc_dapm_widget *source,
1026 struct snd_soc_dapm_widget *sink)
1027{
1028 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1029 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1030
1031 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1032 return 1;
1033
1034 return 0;
1035}
1036
0e826e86
OC		 1037/* Digital Mixer */
1038static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1039 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1040 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1041 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1042 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1043};
1044
1045static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1046 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1047 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1048 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1049 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1050};
1051
1052static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1053 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1054 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1055 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1056 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1057};
1058
1059static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1060 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1061 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1062 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1063 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1064};
1065
1066static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1067 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1068 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1069 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1070 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1071};
1072
1073static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1074 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1075 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1076 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1077 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1078};
1079
1080static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1081 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1082 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1083 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1084 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1085};
1086
1087static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1088 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1089 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1090 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1091 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1092};
1093
1094static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1095 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1096 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1097 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1098 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1099};
1100
1101static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1102 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1103 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1104 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1105 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1106};
1107
1108static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1109 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1110 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1111 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1112 RT5677_M_DAC1_L_SFT, 1, 1),
1113};
1114
1115static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1116 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1117 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1118 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1119 RT5677_M_DAC1_R_SFT, 1, 1),
1120};
1121
1122static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1123 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1124 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1125 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1126 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1127 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1128 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1129 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1130 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1131};
1132
1133static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1134 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1135 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1136 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1137 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1138 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1139 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1140 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1141 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1142};
1143
1144static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1145 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1146 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1147 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1148 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1149 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1150 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1151 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1152 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1153};
1154
1155static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1156 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1157 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1158 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1159 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1160 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1161 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1162 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1163 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1164};
1165
1166static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1167 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1168 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1169 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1170 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1171 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1172 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1173 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1174 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1175};
1176
1177static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1178 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1179 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1180 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1181 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1182 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1183 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1184 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1185 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1186};
1187
1188static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1189 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1190 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1191 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1192 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1193 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1194 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1195 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1196 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1197};
1198
1199static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1200 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1201 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1202 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1203 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1204 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1205 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1206 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1207 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1208};
1209
1210static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1211 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1212 RT5677_DSP_IB_01_H_SFT, 1, 1),
1213 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1214 RT5677_DSP_IB_23_H_SFT, 1, 1),
1215 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1216 RT5677_DSP_IB_45_H_SFT, 1, 1),
1217 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1218 RT5677_DSP_IB_6_H_SFT, 1, 1),
1219 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1220 RT5677_DSP_IB_7_H_SFT, 1, 1),
1221 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1222 RT5677_DSP_IB_8_H_SFT, 1, 1),
1223 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1224 RT5677_DSP_IB_9_H_SFT, 1, 1),
1225};
1226
1227static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1228 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1229 RT5677_DSP_IB_01_L_SFT, 1, 1),
1230 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1231 RT5677_DSP_IB_23_L_SFT, 1, 1),
1232 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1233 RT5677_DSP_IB_45_L_SFT, 1, 1),
1234 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1235 RT5677_DSP_IB_6_L_SFT, 1, 1),
1236 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1237 RT5677_DSP_IB_7_L_SFT, 1, 1),
1238 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1239 RT5677_DSP_IB_8_L_SFT, 1, 1),
1240 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1241 RT5677_DSP_IB_9_L_SFT, 1, 1),
1242};
1243
1244static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1245 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1246 RT5677_DSP_IB_01_H_SFT, 1, 1),
1247 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1248 RT5677_DSP_IB_23_H_SFT, 1, 1),
1249 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1250 RT5677_DSP_IB_45_H_SFT, 1, 1),
1251 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1252 RT5677_DSP_IB_6_H_SFT, 1, 1),
1253 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1254 RT5677_DSP_IB_7_H_SFT, 1, 1),
1255 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1256 RT5677_DSP_IB_8_H_SFT, 1, 1),
1257 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1258 RT5677_DSP_IB_9_H_SFT, 1, 1),
1259};
1260
1261static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1262 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1263 RT5677_DSP_IB_01_L_SFT, 1, 1),
1264 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1265 RT5677_DSP_IB_23_L_SFT, 1, 1),
1266 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1267 RT5677_DSP_IB_45_L_SFT, 1, 1),
1268 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1269 RT5677_DSP_IB_6_L_SFT, 1, 1),
1270 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1271 RT5677_DSP_IB_7_L_SFT, 1, 1),
1272 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1273 RT5677_DSP_IB_8_L_SFT, 1, 1),
1274 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1275 RT5677_DSP_IB_9_L_SFT, 1, 1),
1276};
1277
1278static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1279 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1280 RT5677_DSP_IB_01_H_SFT, 1, 1),
1281 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1282 RT5677_DSP_IB_23_H_SFT, 1, 1),
1283 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1284 RT5677_DSP_IB_45_H_SFT, 1, 1),
1285 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1286 RT5677_DSP_IB_6_H_SFT, 1, 1),
1287 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1288 RT5677_DSP_IB_7_H_SFT, 1, 1),
1289 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1290 RT5677_DSP_IB_8_H_SFT, 1, 1),
1291 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1292 RT5677_DSP_IB_9_H_SFT, 1, 1),
1293};
1294
1295static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1296 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1297 RT5677_DSP_IB_01_L_SFT, 1, 1),
1298 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1299 RT5677_DSP_IB_23_L_SFT, 1, 1),
1300 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1301 RT5677_DSP_IB_45_L_SFT, 1, 1),
1302 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1303 RT5677_DSP_IB_6_L_SFT, 1, 1),
1304 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1305 RT5677_DSP_IB_7_L_SFT, 1, 1),
1306 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1307 RT5677_DSP_IB_8_L_SFT, 1, 1),
1308 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1309 RT5677_DSP_IB_9_L_SFT, 1, 1),
1310};
1311
1312
1313/* Mux */
1b7fd76a 1314/* DAC1 L/R Source */ /* MX-29 [10:8] */
0e826e86
OC		 1315static const char * const rt5677_dac1_src[] = {
1316 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1317 "OB 01"
1318};
1319
1320static SOC_ENUM_SINGLE_DECL(
1321 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1322 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1323
1324static const struct snd_kcontrol_new rt5677_dac1_mux =
1b7fd76a 1325 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
0e826e86 1326
1b7fd76a 1327/* ADDA1 L/R Source */ /* MX-29 [1:0] */
0e826e86
OC		 1328static const char * const rt5677_adda1_src[] = {
1329 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1330};
1331
1332static SOC_ENUM_SINGLE_DECL(
1333 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1334 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1335
1336static const struct snd_kcontrol_new rt5677_adda1_mux =
1b7fd76a 1337 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
0e826e86
OC		 1338
1339
1b7fd76a 1340/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
0e826e86
OC		 1341static const char * const rt5677_dac2l_src[] = {
1342 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1343 "OB 2",
1344};
1345
1346static SOC_ENUM_SINGLE_DECL(
1347 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1348 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1349
1350static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1b7fd76a 1351 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
0e826e86
OC		 1352
1353static const char * const rt5677_dac2r_src[] = {
1354 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1355 "OB 3", "Haptic Generator", "VAD ADC"
1356};
1357
1358static SOC_ENUM_SINGLE_DECL(
1359 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1360 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1361
1362static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1b7fd76a 1363 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
0e826e86 1364
1b7fd76a 1365/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
0e826e86
OC		 1366static const char * const rt5677_dac3l_src[] = {
1367 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1368 "SLB DAC 4", "OB 4"
1369};
1370
1371static SOC_ENUM_SINGLE_DECL(
1372 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1373 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1374
1375static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1b7fd76a 1376 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
0e826e86
OC		 1377
1378static const char * const rt5677_dac3r_src[] = {
1379 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1380 "SLB DAC 5", "OB 5"
1381};
1382
1383static SOC_ENUM_SINGLE_DECL(
1384 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1385 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1386
1387static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1b7fd76a 1388 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
0e826e86 1389
1b7fd76a 1390/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
0e826e86
OC		 1391static const char * const rt5677_dac4l_src[] = {
1392 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1393 "SLB DAC 6", "OB 6"
1394};
1395
1396static SOC_ENUM_SINGLE_DECL(
1397 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1398 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1399
1400static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1b7fd76a 1401 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
0e826e86
OC		 1402
1403static const char * const rt5677_dac4r_src[] = {
1404 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1405 "SLB DAC 7", "OB 7"
1406};
1407
1408static SOC_ENUM_SINGLE_DECL(
1409 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1410 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1411
1412static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1b7fd76a 1413 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
0e826e86
OC		 1414
1415/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1416static const char * const rt5677_iob_bypass_src[] = {
1417 "Bypass", "Pass SRC"
1418};
1419
1420static SOC_ENUM_SINGLE_DECL(
1421 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1422 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1423
1424static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1b7fd76a 1425 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
0e826e86
OC		 1426
1427static SOC_ENUM_SINGLE_DECL(
1428 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1429 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1430
1431static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1b7fd76a 1432 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
0e826e86
OC		 1433
1434static SOC_ENUM_SINGLE_DECL(
1435 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1436 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1437
1438static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1b7fd76a 1439 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
0e826e86
OC		 1440
1441static SOC_ENUM_SINGLE_DECL(
1442 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1443 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1444
1445static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1b7fd76a 1446 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
0e826e86
OC		 1447
1448static SOC_ENUM_SINGLE_DECL(
1449 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1450 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1451
1452static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1b7fd76a 1453 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
0e826e86 1454
d65fd3a4 1455/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
0e826e86
OC		 1456static const char * const rt5677_stereo_adc2_src[] = {
1457 "DD MIX1", "DMIC", "Stereo DAC MIX"
1458};
1459
1460static SOC_ENUM_SINGLE_DECL(
1461 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1462 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1463
1464static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1b7fd76a 1465 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
0e826e86
OC		 1466
1467static SOC_ENUM_SINGLE_DECL(
1468 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1469 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1470
1471static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1b7fd76a 1472 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
0e826e86
OC		 1473
1474static SOC_ENUM_SINGLE_DECL(
1475 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1476 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1477
1478static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1b7fd76a 1479 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
0e826e86
OC		 1480
1481/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1482static const char * const rt5677_dmic_src[] = {
1483 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1484};
1485
1486static SOC_ENUM_SINGLE_DECL(
1487 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1488 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1489
1490static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1b7fd76a 1491 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
0e826e86
OC		 1492
1493static SOC_ENUM_SINGLE_DECL(
1494 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1495 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1496
1497static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1b7fd76a 1498 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
0e826e86
OC		 1499
1500static SOC_ENUM_SINGLE_DECL(
1501 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1502 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1503
1504static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1b7fd76a 1505 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
0e826e86
OC		 1506
1507static SOC_ENUM_SINGLE_DECL(
1508 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1509 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1510
1511static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1b7fd76a 1512 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
0e826e86
OC		 1513
1514static SOC_ENUM_SINGLE_DECL(
1515 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1516 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1517
1518static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1b7fd76a 1519 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
0e826e86
OC		 1520
1521static SOC_ENUM_SINGLE_DECL(
1522 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1523 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1524
1525static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1b7fd76a 1526 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
0e826e86 1527
1b7fd76a 1528/* Stereo2 ADC Source */ /* MX-26 [0] */
0e826e86
OC		 1529static const char * const rt5677_stereo2_adc_lr_src[] = {
1530 "L", "LR"
1531};
1532
1533static SOC_ENUM_SINGLE_DECL(
1534 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1535 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1536
1537static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1b7fd76a 1538 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
0e826e86 1539
d65fd3a4 1540/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
0e826e86
OC		 1541static const char * const rt5677_stereo_adc1_src[] = {
1542 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1543};
1544
1545static SOC_ENUM_SINGLE_DECL(
1546 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1547 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1548
1549static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1b7fd76a 1550 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
0e826e86
OC		 1551
1552static SOC_ENUM_SINGLE_DECL(
1553 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1554 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1555
1556static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1b7fd76a 1557 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
0e826e86
OC		 1558
1559static SOC_ENUM_SINGLE_DECL(
1560 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1561 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1562
1563static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1b7fd76a 1564 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
0e826e86 1565
1b7fd76a 1566/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
0e826e86
OC		 1567static const char * const rt5677_mono_adc2_l_src[] = {
1568 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1569};
1570
1571static SOC_ENUM_SINGLE_DECL(
1572 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1573 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1574
1575static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1b7fd76a 1576 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
0e826e86 1577
1b7fd76a 1578/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
0e826e86
OC		 1579static const char * const rt5677_mono_adc1_l_src[] = {
1580 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1581};
1582
1583static SOC_ENUM_SINGLE_DECL(
1584 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1585 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1586
1587static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1b7fd76a 1588 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
0e826e86 1589
1b7fd76a 1590/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
0e826e86
OC		 1591static const char * const rt5677_mono_adc2_r_src[] = {
1592 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1593};
1594
1595static SOC_ENUM_SINGLE_DECL(
1596 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1597 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1598
1599static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1b7fd76a 1600 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
0e826e86 1601
1b7fd76a 1602/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
0e826e86
OC		 1603static const char * const rt5677_mono_adc1_r_src[] = {
1604 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1605};
1606
1607static SOC_ENUM_SINGLE_DECL(
1608 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1609 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1610
1611static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1b7fd76a 1612 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
0e826e86
OC		 1613
1614/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1615static const char * const rt5677_stereo4_adc2_src[] = {
1616 "DD MIX1", "DMIC", "DD MIX2"
1617};
1618
1619static SOC_ENUM_SINGLE_DECL(
1620 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1621 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1622
1623static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1b7fd76a 1624 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
0e826e86
OC		 1625
1626
1627/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1628static const char * const rt5677_stereo4_adc1_src[] = {
1629 "DD MIX1", "ADC1/2", "DD MIX2"
1630};
1631
1632static SOC_ENUM_SINGLE_DECL(
1633 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1634 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1635
1636static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1b7fd76a 1637 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
0e826e86
OC		 1638
1639/* InBound0/1 Source */ /* MX-A3 [14:12] */
1640static const char * const rt5677_inbound01_src[] = {
1641 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1642 "VAD ADC/DAC1 FS"
1643};
1644
1645static SOC_ENUM_SINGLE_DECL(
1646 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1647 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1648
1649static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1650 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1651
1652/* InBound2/3 Source */ /* MX-A3 [10:8] */
1653static const char * const rt5677_inbound23_src[] = {
1654 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1655 "DAC1 FS", "IF4 DAC"
1656};
1657
1658static SOC_ENUM_SINGLE_DECL(
1659 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1660 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1661
1662static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1663 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1664
1665/* InBound4/5 Source */ /* MX-A3 [6:4] */
1666static const char * const rt5677_inbound45_src[] = {
1667 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1668 "IF3 DAC"
1669};
1670
1671static SOC_ENUM_SINGLE_DECL(
1672 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1673 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1674
1675static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1676 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1677
1678/* InBound6 Source */ /* MX-A3 [2:0] */
1679static const char * const rt5677_inbound6_src[] = {
1680 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1681 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1682};
1683
1684static SOC_ENUM_SINGLE_DECL(
1685 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1686 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1687
1688static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1689 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1690
1691/* InBound7 Source */ /* MX-A4 [14:12] */
1692static const char * const rt5677_inbound7_src[] = {
1693 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1694 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1695};
1696
1697static SOC_ENUM_SINGLE_DECL(
1698 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1699 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1700
1701static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1702 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1703
1704/* InBound8 Source */ /* MX-A4 [10:8] */
1705static const char * const rt5677_inbound8_src[] = {
1706 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1707 "MONO ADC MIX L", "DACL1 FS"
1708};
1709
1710static SOC_ENUM_SINGLE_DECL(
1711 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1712 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1713
1714static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1715 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1716
1717/* InBound9 Source */ /* MX-A4 [6:4] */
1718static const char * const rt5677_inbound9_src[] = {
1719 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1720 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1721};
1722
1723static SOC_ENUM_SINGLE_DECL(
1724 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1725 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1726
1727static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1728 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1729
1730/* VAD Source */ /* MX-9F [6:4] */
1731static const char * const rt5677_vad_src[] = {
1732 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1733 "STO3 ADC MIX L"
1734};
1735
1736static SOC_ENUM_SINGLE_DECL(
1737 rt5677_vad_enum, RT5677_VAD_CTRL4,
1738 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1739
1740static const struct snd_kcontrol_new rt5677_vad_src_mux =
1741 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1742
1743/* Sidetone Source */ /* MX-13 [11:9] */
1744static const char * const rt5677_sidetone_src[] = {
1745 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1746};
1747
1748static SOC_ENUM_SINGLE_DECL(
1749 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1750 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1751
1752static const struct snd_kcontrol_new rt5677_sidetone_mux =
1753 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1754
1755/* DAC1/2 Source */ /* MX-15 [1:0] */
1756static const char * const rt5677_dac12_src[] = {
1757 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1758};
1759
1760static SOC_ENUM_SINGLE_DECL(
1761 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1762 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1763
1764static const struct snd_kcontrol_new rt5677_dac12_mux =
1765 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1766
1767/* DAC3 Source */ /* MX-15 [5:4] */
1768static const char * const rt5677_dac3_src[] = {
1769 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1770};
1771
1772static SOC_ENUM_SINGLE_DECL(
1773 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1774 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1775
1776static const struct snd_kcontrol_new rt5677_dac3_mux =
1777 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1778
1b7fd76a 1779/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
0e826e86
OC		 1780static const char * const rt5677_pdm_src[] = {
1781 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1782};
1783
1784static SOC_ENUM_SINGLE_DECL(
1785 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1786 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1787
1788static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1b7fd76a 1789 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
0e826e86
OC		 1790
1791static SOC_ENUM_SINGLE_DECL(
1792 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1793 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1794
1795static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1b7fd76a 1796 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
0e826e86
OC		 1797
1798static SOC_ENUM_SINGLE_DECL(
1799 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1800 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1801
1802static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1b7fd76a 1803 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
0e826e86
OC		 1804
1805static SOC_ENUM_SINGLE_DECL(
1806 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1807 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1808
1809static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1b7fd76a 1810 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
0e826e86 1811
d65fd3a4 1812/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
0e826e86
OC		 1813static const char * const rt5677_if12_adc1_src[] = {
1814 "STO1 ADC MIX", "OB01", "VAD ADC"
1815};
1816
1817static SOC_ENUM_SINGLE_DECL(
1818 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1819 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1820
1821static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1b7fd76a 1822 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
0e826e86
OC		 1823
1824static SOC_ENUM_SINGLE_DECL(
1825 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1826 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1827
1828static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1b7fd76a 1829 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
0e826e86
OC		 1830
1831static SOC_ENUM_SINGLE_DECL(
1832 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1833 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1834
1835static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1b7fd76a 1836 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
0e826e86
OC		 1837
1838/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1839static const char * const rt5677_if12_adc2_src[] = {
1840 "STO2 ADC MIX", "OB23"
1841};
1842
1843static SOC_ENUM_SINGLE_DECL(
1844 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1845 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1846
1847static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1b7fd76a 1848 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
0e826e86
OC		 1849
1850static SOC_ENUM_SINGLE_DECL(
1851 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1852 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1853
1854static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1b7fd76a 1855 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
0e826e86
OC		 1856
1857static SOC_ENUM_SINGLE_DECL(
1858 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1859 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1860
1861static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1b7fd76a 1862 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
0e826e86
OC		 1863
1864/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1865static const char * const rt5677_if12_adc3_src[] = {
1866 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1867};
1868
1869static SOC_ENUM_SINGLE_DECL(
1870 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1871 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1872
1873static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1b7fd76a 1874 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
0e826e86
OC		 1875
1876static SOC_ENUM_SINGLE_DECL(
1877 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1878 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1879
1880static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1b7fd76a 1881 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
0e826e86
OC		 1882
1883static SOC_ENUM_SINGLE_DECL(
1884 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1885 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1886
1887static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1b7fd76a 1888 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
0e826e86 1889
d65fd3a4 1890/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
0e826e86
OC		 1891static const char * const rt5677_if12_adc4_src[] = {
1892 "STO4 ADC MIX", "OB67", "OB01"
1893};
1894
1895static SOC_ENUM_SINGLE_DECL(
1896 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1897 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1898
1899static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1b7fd76a 1900 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
0e826e86
OC		 1901
1902static SOC_ENUM_SINGLE_DECL(
1903 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1904 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1905
1906static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1b7fd76a 1907 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
0e826e86
OC		 1908
1909static SOC_ENUM_SINGLE_DECL(
1910 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1911 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1912
1913static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1b7fd76a 1914 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
0e826e86 1915
d65fd3a4 1916/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
0e826e86
OC		 1917static const char * const rt5677_if34_adc_src[] = {
1918 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1919 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1920};
1921
1922static SOC_ENUM_SINGLE_DECL(
1923 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1924 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1925
1926static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1b7fd76a 1927 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
0e826e86
OC		 1928
1929static SOC_ENUM_SINGLE_DECL(
1930 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1931 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1932
1933static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1b7fd76a 1934 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
0e826e86 1935
e6f6ebc1
OC		 1936/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
1937static const char * const rt5677_if12_adc_swap_src[] = {
1938 "L/R", "R/L", "L/L", "R/R"
1939};
1940
1941static SOC_ENUM_SINGLE_DECL(
1942 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
1943 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
1944
1945static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
1946 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
1947
1948static SOC_ENUM_SINGLE_DECL(
1949 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
1950 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1951
1952static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
1953 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
1954
1955static SOC_ENUM_SINGLE_DECL(
1956 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
1957 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1958
1959static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
1960 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
1961
1962static SOC_ENUM_SINGLE_DECL(
1963 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
1964 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1965
1966static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
1967 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
1968
1969static SOC_ENUM_SINGLE_DECL(
1970 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
1971 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1972
1973static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
1974 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
1975
1976static SOC_ENUM_SINGLE_DECL(
1977 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
1978 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1979
1980static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
1981 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
1982
1983static SOC_ENUM_SINGLE_DECL(
1984 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
1985 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1986
1987static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
1988 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
1989
1990static SOC_ENUM_SINGLE_DECL(
1991 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
1992 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1993
1994static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
1995 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
1996
d65fd3a4 1997/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
e6f6ebc1
OC		 1998static const char * const rt5677_if1_adc_tdm_swap_src[] = {
1999 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2000 "3/1/2/4", "3/4/1/2"
2001};
2002
2003static SOC_ENUM_SINGLE_DECL(
2004 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2005 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2006
2007static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2008 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2009
2010/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2011static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2012 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2013 "2/3/1/4", "3/4/1/2"
2014};
2015
2016static SOC_ENUM_SINGLE_DECL(
2017 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2018 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2019
2020static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2021 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2022
91159eca
OC		 2023/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2024 MX-3F[14:12][10:8][6:4][2:0]
2025 MX-43[14:12][10:8][6:4][2:0]
2026 MX-44[14:12][10:8][6:4][2:0] */
2027static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2028 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2029};
2030
2031static SOC_ENUM_SINGLE_DECL(
2032 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2033 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2034
2035static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2036 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2037
2038static SOC_ENUM_SINGLE_DECL(
2039 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2040 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2041
2042static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2043 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2044
2045static SOC_ENUM_SINGLE_DECL(
2046 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2047 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2048
2049static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2050 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2051
2052static SOC_ENUM_SINGLE_DECL(
2053 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2054 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2055
2056static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2057 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2058
2059static SOC_ENUM_SINGLE_DECL(
2060 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2061 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2062
2063static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2064 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2065
2066static SOC_ENUM_SINGLE_DECL(
2067 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2068 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2069
2070static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2071 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2072
2073static SOC_ENUM_SINGLE_DECL(
2074 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2075 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2076
2077static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2078 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2079
2080static SOC_ENUM_SINGLE_DECL(
2081 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2082 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2083
2084static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2085 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2086
2087static SOC_ENUM_SINGLE_DECL(
2088 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2089 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2090
2091static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2092 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2093
2094static SOC_ENUM_SINGLE_DECL(
2095 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2096 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2097
2098static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2099 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2100
2101static SOC_ENUM_SINGLE_DECL(
2102 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2103 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2104
2105static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2106 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2107
2108static SOC_ENUM_SINGLE_DECL(
2109 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2110 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2111
2112static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2113 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2114
2115static SOC_ENUM_SINGLE_DECL(
2116 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2117 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2118
2119static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2120 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2121
2122static SOC_ENUM_SINGLE_DECL(
2123 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2124 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2125
2126static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2127 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2128
2129static SOC_ENUM_SINGLE_DECL(
2130 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2131 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2132
2133static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2134 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2135
2136static SOC_ENUM_SINGLE_DECL(
2137 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2138 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2139
2140static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2141 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2142
0e826e86
OC		 2143static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2144 struct snd_kcontrol *kcontrol, int event)
2145{
46f20872 2146 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2147 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2148
2149 switch (event) {
2150 case SND_SOC_DAPM_POST_PMU:
2151 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2152 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2153 break;
2154
2155 case SND_SOC_DAPM_PRE_PMD:
2156 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2157 RT5677_PWR_BST1_P, 0);
2158 break;
2159
2160 default:
2161 return 0;
2162 }
2163
2164 return 0;
2165}
2166
2167static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2168 struct snd_kcontrol *kcontrol, int event)
2169{
46f20872 2170 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2171 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2172
2173 switch (event) {
2174 case SND_SOC_DAPM_POST_PMU:
2175 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2176 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2177 break;
2178
2179 case SND_SOC_DAPM_PRE_PMD:
2180 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2181 RT5677_PWR_BST2_P, 0);
2182 break;
2183
2184 default:
2185 return 0;
2186 }
2187
2188 return 0;
2189}
2190
2191static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2192 struct snd_kcontrol *kcontrol, int event)
2193{
46f20872 2194 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2195 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2196
2197 switch (event) {
bdfbf255 2198 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2199 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2200 break;
2201
2202 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2203 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2204 break;
bdfbf255 2205
0e826e86
OC		 2206 default:
2207 return 0;
2208 }
2209
2210 return 0;
2211}
2212
2213static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2214 struct snd_kcontrol *kcontrol, int event)
2215{
46f20872 2216 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2217 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2218
2219 switch (event) {
bdfbf255 2220 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2221 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2222 break;
2223
2224 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2225 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2226 break;
bdfbf255 2227
0e826e86
OC		 2228 default:
2229 return 0;
2230 }
2231
2232 return 0;
2233}
2234
2235static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2236 struct snd_kcontrol *kcontrol, int event)
2237{
46f20872 2238 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2239 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2240
2241 switch (event) {
2242 case SND_SOC_DAPM_POST_PMU:
2243 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2244 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2245 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2246 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2247 break;
f58c3b91
OC		 2248
2249 case SND_SOC_DAPM_PRE_PMD:
2250 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2251 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2252 RT5677_PWR_CLK_MB, 0);
2253 break;
2254
0e826e86
OC		 2255 default:
2256 return 0;
2257 }
2258
2259 return 0;
2260}
2261
e6f6ebc1
OC		 2262static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2263 struct snd_kcontrol *kcontrol, int event)
2264{
46f20872 2265 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e6f6ebc1
OC		 2266 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2267 unsigned int value;
2268
2269 switch (event) {
2270 case SND_SOC_DAPM_PRE_PMU:
2271 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2272 if (value & RT5677_IF1_ADC_CTRL_MASK)
2273 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2274 RT5677_IF1_ADC_MODE_MASK,
2275 RT5677_IF1_ADC_MODE_TDM);
2276 break;
2277
2278 default:
2279 return 0;
2280 }
2281
2282 return 0;
2283}
2284
2285static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2286 struct snd_kcontrol *kcontrol, int event)
2287{
46f20872 2288 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e6f6ebc1
OC		 2289 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2290 unsigned int value;
2291
2292 switch (event) {
2293 case SND_SOC_DAPM_PRE_PMU:
2294 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2295 if (value & RT5677_IF2_ADC_CTRL_MASK)
2296 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2297 RT5677_IF2_ADC_MODE_MASK,
2298 RT5677_IF2_ADC_MODE_TDM);
2299 break;
2300
2301 default:
2302 return 0;
2303 }
2304
2305 return 0;
2306}
2307
683996cb
OC		 2308static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2309 struct snd_kcontrol *kcontrol, int event)
2310{
46f20872 2311 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
683996cb
OC		 2312 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2313
2314 switch (event) {
2315 case SND_SOC_DAPM_POST_PMU:
2316 if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2317 !rt5677->is_vref_slow) {
2318 mdelay(20);
2319 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2320 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2321 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2322 rt5677->is_vref_slow = true;
2323 }
2324 break;
2325
2326 default:
2327 return 0;
2328 }
2329
2330 return 0;
2331}
2332
0e826e86
OC		 2333static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2334 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
bdfbf255
OC		 2335 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2336 SND_SOC_DAPM_POST_PMU),
0e826e86 2337 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
bdfbf255
OC		 2338 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2339 SND_SOC_DAPM_POST_PMU),
0e826e86 2340
5a8c7c26
OC		 2341 /* ASRC */
2342 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2343 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2344 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2345 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2346 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2347 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2348 0),
2349 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2350 0),
2351 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2352 0),
2353 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2354 0),
2355 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2356 0),
2357 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2358 0),
2359 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2360 0),
2361 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2362 0),
2363 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2364 0),
2365 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2366 0),
2367 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2368 0),
2369 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2370 0),
2371 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2372 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2373 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2374 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2375 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2376 0),
2377 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2378 0),
2379
0e826e86
OC		 2380 /* Input Side */
2381 /* micbias */
3d0c03d9 2382 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
f58c3b91
OC		 2383 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2384 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 2385
2386 /* Input Lines */
2387 SND_SOC_DAPM_INPUT("DMIC L1"),
2388 SND_SOC_DAPM_INPUT("DMIC R1"),
2389 SND_SOC_DAPM_INPUT("DMIC L2"),
2390 SND_SOC_DAPM_INPUT("DMIC R2"),
2391 SND_SOC_DAPM_INPUT("DMIC L3"),
2392 SND_SOC_DAPM_INPUT("DMIC R3"),
2393 SND_SOC_DAPM_INPUT("DMIC L4"),
2394 SND_SOC_DAPM_INPUT("DMIC R4"),
2395
2396 SND_SOC_DAPM_INPUT("IN1P"),
2397 SND_SOC_DAPM_INPUT("IN1N"),
2398 SND_SOC_DAPM_INPUT("IN2P"),
2399 SND_SOC_DAPM_INPUT("IN2N"),
2400
2401 SND_SOC_DAPM_INPUT("Haptic Generator"),
2402
2d15d974
BL		 2403 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2404 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2405 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2406 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2407
2408 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2409 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2410 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2411 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2412 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2413 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2414 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2415 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
0e826e86
OC		 2416
2417 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2418 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2419
2420 /* Boost */
2421 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2422 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2423 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2424 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2425 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2426 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2427
2428 /* ADCs */
2429 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2430 0, 0),
2431 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2432 0, 0),
2433 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2434
2435 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2436 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2437 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2438 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2439 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2440 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2441 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2442 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2443
2444 /* ADC Mux */
2445 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2446 &rt5677_sto1_dmic_mux),
2447 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2448 &rt5677_sto1_adc1_mux),
2449 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2450 &rt5677_sto1_adc2_mux),
2451 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2452 &rt5677_sto2_dmic_mux),
2453 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2454 &rt5677_sto2_adc1_mux),
2455 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2456 &rt5677_sto2_adc2_mux),
2457 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2458 &rt5677_sto2_adc_lr_mux),
2459 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2460 &rt5677_sto3_dmic_mux),
2461 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2462 &rt5677_sto3_adc1_mux),
2463 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2464 &rt5677_sto3_adc2_mux),
2465 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2466 &rt5677_sto4_dmic_mux),
2467 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2468 &rt5677_sto4_adc1_mux),
2469 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2470 &rt5677_sto4_adc2_mux),
2471 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2472 &rt5677_mono_dmic_l_mux),
2473 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2474 &rt5677_mono_dmic_r_mux),
2475 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2476 &rt5677_mono_adc2_l_mux),
2477 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2478 &rt5677_mono_adc1_l_mux),
2479 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2480 &rt5677_mono_adc1_r_mux),
2481 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2482 &rt5677_mono_adc2_r_mux),
2483
2484 /* ADC Mixer */
2485 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2486 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2487 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2488 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2489 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2490 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2491 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2492 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2493 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2494 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2495 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2496 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2497 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2498 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2499 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2500 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2501 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2502 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2503 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2504 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2505 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2506 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2507 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2508 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2509 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2510 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2511 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2512 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2513 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2514 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2515 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2516 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2517
2518 /* ADC PGA */
2519 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2520 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2521 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2522 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2523 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2524 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2525 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2526 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2527 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2528 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2529 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2530 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2531 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2532 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
e6f6ebc1
OC		 2533 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2534 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
0e826e86
OC		 2535
2536 /* DSP */
2537 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2538 &rt5677_ib9_src_mux),
2539 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2540 &rt5677_ib8_src_mux),
2541 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2542 &rt5677_ib7_src_mux),
2543 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2544 &rt5677_ib6_src_mux),
2545 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2546 &rt5677_ib45_src_mux),
2547 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2548 &rt5677_ib23_src_mux),
2549 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2550 &rt5677_ib01_src_mux),
2551 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2552 &rt5677_ib45_bypass_src_mux),
2553 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2554 &rt5677_ib23_bypass_src_mux),
2555 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2556 &rt5677_ib01_bypass_src_mux),
2557 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2558 &rt5677_ob23_bypass_src_mux),
2559 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2560 &rt5677_ob01_bypass_src_mux),
2561
2562 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2563 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2564
2565 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2566 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2567 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2568 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2569 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2570 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2571
2572 /* Digital Interface */
2573 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2574 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2575 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2576 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2577 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2578 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2579 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2580 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2581 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2582 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2583 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2584 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2585 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2586 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2587 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2588 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2589 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2590 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2591
2592 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2593 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2594 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2595 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2596 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2597 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2598 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2599 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2600 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2601 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2602 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2603 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2604 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2605 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2606 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2607 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2608 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2609 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2610
2611 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2612 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2613 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2614 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2615 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2616 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2617 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2618 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2619
2620 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2621 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2622 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2623 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2624 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2625 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2626 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2627 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2628
2629 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2630 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2631 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2632 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2633 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2634 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2635 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2636 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2637 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2638 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2639 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2640 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2641 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2642 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2643 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2644 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2645 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2646 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2647
2648 /* Digital Interface Select */
2649 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2650 &rt5677_if1_adc1_mux),
2651 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2652 &rt5677_if1_adc2_mux),
2653 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2654 &rt5677_if1_adc3_mux),
2655 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2656 &rt5677_if1_adc4_mux),
e6f6ebc1
OC		 2657 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2658 &rt5677_if1_adc1_swap_mux),
2659 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2660 &rt5677_if1_adc2_swap_mux),
2661 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2662 &rt5677_if1_adc3_swap_mux),
2663 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2664 &rt5677_if1_adc4_swap_mux),
2665 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2666 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2667 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2668 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2669 &rt5677_if2_adc1_mux),
2670 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2671 &rt5677_if2_adc2_mux),
2672 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2673 &rt5677_if2_adc3_mux),
2674 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2675 &rt5677_if2_adc4_mux),
e6f6ebc1
OC		 2676 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2677 &rt5677_if2_adc1_swap_mux),
2678 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2679 &rt5677_if2_adc2_swap_mux),
2680 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2681 &rt5677_if2_adc3_swap_mux),
2682 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2683 &rt5677_if2_adc4_swap_mux),
2684 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2685 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2686 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2687 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2688 &rt5677_if3_adc_mux),
2689 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2690 &rt5677_if4_adc_mux),
2691 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2692 &rt5677_slb_adc1_mux),
2693 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2694 &rt5677_slb_adc2_mux),
2695 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2696 &rt5677_slb_adc3_mux),
2697 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2698 &rt5677_slb_adc4_mux),
2699
91159eca
OC		 2700 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2701 &rt5677_if1_dac0_tdm_sel_mux),
2702 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2703 &rt5677_if1_dac1_tdm_sel_mux),
2704 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2705 &rt5677_if1_dac2_tdm_sel_mux),
2706 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2707 &rt5677_if1_dac3_tdm_sel_mux),
2708 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2709 &rt5677_if1_dac4_tdm_sel_mux),
2710 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2711 &rt5677_if1_dac5_tdm_sel_mux),
2712 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2713 &rt5677_if1_dac6_tdm_sel_mux),
2714 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2715 &rt5677_if1_dac7_tdm_sel_mux),
2716
2717 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2718 &rt5677_if2_dac0_tdm_sel_mux),
2719 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2720 &rt5677_if2_dac1_tdm_sel_mux),
2721 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2722 &rt5677_if2_dac2_tdm_sel_mux),
2723 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2724 &rt5677_if2_dac3_tdm_sel_mux),
2725 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2726 &rt5677_if2_dac4_tdm_sel_mux),
2727 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2728 &rt5677_if2_dac5_tdm_sel_mux),
2729 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2730 &rt5677_if2_dac6_tdm_sel_mux),
2731 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2732 &rt5677_if2_dac7_tdm_sel_mux),
2733
0e826e86
OC		 2734 /* Audio Interface */
2735 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2736 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2737 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2738 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2739 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2740 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2741 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2742 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2743 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2744 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2745
2746 /* Sidetone Mux */
2747 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2748 &rt5677_sidetone_mux),
90bdbb46
OC		 2749 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2750 RT5677_ST_EN_SFT, 0, NULL, 0),
2751
0e826e86
OC		 2752 /* VAD Mux*/
2753 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2754 &rt5677_vad_src_mux),
2755
2756 /* Tensilica DSP */
2757 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2758 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2759 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2760 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2761 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2762 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2763 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2764 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2765 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2766 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2767 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2768 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2769 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2770
2771 /* Output Side */
d65fd3a4 2772 /* DAC mixer before sound effect */
0e826e86
OC		 2773 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2774 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2775 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2776 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2777 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2778
2779 /* DAC Mux */
2780 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2781 &rt5677_dac1_mux),
2782 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2783 &rt5677_adda1_mux),
2784 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2785 &rt5677_dac12_mux),
2786 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2787 &rt5677_dac3_mux),
2788
2789 /* DAC2 channel Mux */
2790 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2791 &rt5677_dac2_l_mux),
2792 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2793 &rt5677_dac2_r_mux),
2794
2795 /* DAC3 channel Mux */
2796 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2797 &rt5677_dac3_l_mux),
2798 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2799 &rt5677_dac3_r_mux),
2800
2801 /* DAC4 channel Mux */
2802 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2803 &rt5677_dac4_l_mux),
2804 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2805 &rt5677_dac4_r_mux),
2806
2807 /* DAC Mixer */
2808 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2809 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
6800b5ba 2810 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
0e826e86 2811 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
6800b5ba 2812 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
0e826e86 2813 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
6800b5ba
OC		 2814 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
2815 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
2816 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
2817 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
2818 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
2819 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
2820 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
2821 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
0e826e86
OC		 2822
2823 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2824 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2825 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2826 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2827 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2828 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2829 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2830 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2831 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2832 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2833 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2834 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2835 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2836 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2837 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2838 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2839 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2840 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2841 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2842 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2843
2844 /* DACs */
2845 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2846 RT5677_PWR_DAC1_BIT, 0),
2847 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2848 RT5677_PWR_DAC2_BIT, 0),
2849 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2850 RT5677_PWR_DAC3_BIT, 0),
2851
2852 /* PDM */
2853 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2854 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2855 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2856 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2857
2858 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2859 1, &rt5677_pdm1_l_mux),
2860 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2861 1, &rt5677_pdm1_r_mux),
2862 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2863 1, &rt5677_pdm2_l_mux),
2864 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2865 1, &rt5677_pdm2_r_mux),
2866
683996cb 2867 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
0e826e86 2868 0, NULL, 0),
683996cb 2869 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
0e826e86 2870 0, NULL, 0),
683996cb 2871 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
0e826e86
OC		 2872 0, NULL, 0),
2873
683996cb
OC		 2874 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
2875 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2876 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
2877 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2878 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
2879 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2880
0e826e86
OC		 2881 /* Output Lines */
2882 SND_SOC_DAPM_OUTPUT("LOUT1"),
2883 SND_SOC_DAPM_OUTPUT("LOUT2"),
2884 SND_SOC_DAPM_OUTPUT("LOUT3"),
2885 SND_SOC_DAPM_OUTPUT("PDM1L"),
2886 SND_SOC_DAPM_OUTPUT("PDM1R"),
2887 SND_SOC_DAPM_OUTPUT("PDM2L"),
2888 SND_SOC_DAPM_OUTPUT("PDM2R"),
683996cb
OC		 2889
2890 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
0e826e86
OC		 2891};
2892
2893static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
5a8c7c26
OC		 2894 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
2895 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
2896 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", can_use_asrc },
2897 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", can_use_asrc },
2898 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
2899 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
2900 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
2901 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
2902 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
2903 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
2904
2905 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2906 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
2907 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
2908 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
2909 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
2910 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
2911 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
2912 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2913 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
2914 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
2915 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
2916 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2917 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2918
0e826e86
OC		 2919 { "DMIC1", NULL, "DMIC L1" },
2920 { "DMIC1", NULL, "DMIC R1" },
2921 { "DMIC2", NULL, "DMIC L2" },
2922 { "DMIC2", NULL, "DMIC R2" },
2923 { "DMIC3", NULL, "DMIC L3" },
2924 { "DMIC3", NULL, "DMIC R3" },
2925 { "DMIC4", NULL, "DMIC L4" },
2926 { "DMIC4", NULL, "DMIC R4" },
2927
2928 { "DMIC L1", NULL, "DMIC CLK" },
2929 { "DMIC R1", NULL, "DMIC CLK" },
2930 { "DMIC L2", NULL, "DMIC CLK" },
2931 { "DMIC R2", NULL, "DMIC CLK" },
2932 { "DMIC L3", NULL, "DMIC CLK" },
2933 { "DMIC R3", NULL, "DMIC CLK" },
2934 { "DMIC L4", NULL, "DMIC CLK" },
2935 { "DMIC R4", NULL, "DMIC CLK" },
2936
2d15d974
BL		 2937 { "DMIC L1", NULL, "DMIC1 power" },
2938 { "DMIC R1", NULL, "DMIC1 power" },
2939 { "DMIC L3", NULL, "DMIC3 power" },
2940 { "DMIC R3", NULL, "DMIC3 power" },
2941 { "DMIC L4", NULL, "DMIC4 power" },
2942 { "DMIC R4", NULL, "DMIC4 power" },
2943
0e826e86
OC		 2944 { "BST1", NULL, "IN1P" },
2945 { "BST1", NULL, "IN1N" },
2946 { "BST2", NULL, "IN2P" },
2947 { "BST2", NULL, "IN2N" },
2948
22e51345
BL		 2949 { "IN1P", NULL, "MICBIAS1" },
2950 { "IN1N", NULL, "MICBIAS1" },
2951 { "IN2P", NULL, "MICBIAS1" },
2952 { "IN2N", NULL, "MICBIAS1" },
0e826e86
OC		 2953
2954 { "ADC 1", NULL, "BST1" },
2955 { "ADC 1", NULL, "ADC 1 power" },
2956 { "ADC 1", NULL, "ADC1 clock" },
2957 { "ADC 2", NULL, "BST2" },
2958 { "ADC 2", NULL, "ADC 2 power" },
2959 { "ADC 2", NULL, "ADC2 clock" },
2960
2961 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2962 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2963 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2964 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2965
2966 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2967 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2968 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2969 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2970
2971 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2972 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2973 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2974 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2975
2976 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2977 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2978 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2979 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2980
2981 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2982 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2983 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2984 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2985
2986 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2987 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2988 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2989 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2990
2991 { "ADC 1_2", NULL, "ADC 1" },
2992 { "ADC 1_2", NULL, "ADC 2" },
2993
2994 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2995 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2996 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2997
2998 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2999 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3000 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3001
3002 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3003 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3004 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3005
3006 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3007 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3008 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3009
3010 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3011 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3012 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3013
3014 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3015 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3016 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3017
3018 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3019 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3020 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3021
3022 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3023 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3024 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3025
3026 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3027 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3028 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3029
3030 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3031 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3032 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3033
3034 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3035 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3036 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3037
3038 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3039 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3040 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3041
3042 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3043 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3044 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3045 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3046
3047 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3048 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
0e826e86
OC		 3049 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3050 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3051 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3052
3053 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3054 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3055
3056 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3057 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3058 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3059 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3060
3061 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3062 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3063
3064 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3065 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3066
3067 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3068 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
0e826e86
OC		 3069 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3070 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3071 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3072
3073 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3074 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3075
3076 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3077 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3078 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3079 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3080
3081 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3082 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
0e826e86
OC		 3083 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3084 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3085 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3086
3087 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3088 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3089
3090 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3091 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3092 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3093 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3094
3095 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3096 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
0e826e86
OC		 3097 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3098 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3099 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3100
3101 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3102 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3103
3104 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3105 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3106 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3107 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3108
3109 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3110 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3111 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3112 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3113
3114 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3115 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3116
3117 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3118 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3119 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3120 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3121 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3122
3123 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3124 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3125 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3126
3127 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3128 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3129
3130 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3131 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3132 { "IF1 ADC3 Mux", "OB45", "OB45" },
3133
3134 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3135 { "IF1 ADC4 Mux", "OB67", "OB67" },
3136 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3137
e6f6ebc1
OC		 3138 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3139 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3140 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3141 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3142
3143 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3144 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3145 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3146 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3147
3148 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3149 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3150 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3151 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3152
3153 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3154 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3155 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3156 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3157
3158 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3159 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3160 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3161 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3162
3163 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3164 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3165 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3166 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3167 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3168 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3169 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3170 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3171
0e826e86 3172 { "AIF1TX", NULL, "I2S1" },
e6f6ebc1 3173 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
0e826e86
OC		 3174
3175 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3176 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3177 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3178
3179 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3180 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3181
3182 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3183 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3184 { "IF2 ADC3 Mux", "OB45", "OB45" },
3185
3186 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3187 { "IF2 ADC4 Mux", "OB67", "OB67" },
3188 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3189
e6f6ebc1
OC		 3190 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3191 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3192 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3193 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3194
3195 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3196 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3197 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3198 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3199
3200 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3201 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3202 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3203 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3204
3205 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3206 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3207 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3208 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3209
3210 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3211 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3212 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3213 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3214
3215 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3216 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3217 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3218 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3219 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3220 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3221 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3222 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3223
0e826e86 3224 { "AIF2TX", NULL, "I2S2" },
e6f6ebc1 3225 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
0e826e86
OC		 3226
3227 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3228 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3229 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3230 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3231 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3232 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3233 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3234 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3235
3236 { "AIF3TX", NULL, "I2S3" },
3237 { "AIF3TX", NULL, "IF3 ADC Mux" },
3238
3239 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3240 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3241 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3242 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3243 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3244 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3245 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3246 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3247
3248 { "AIF4TX", NULL, "I2S4" },
3249 { "AIF4TX", NULL, "IF4 ADC Mux" },
3250
3251 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3252 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3253 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3254
3255 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3256 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3257
3258 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3259 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3260 { "SLB ADC3 Mux", "OB45", "OB45" },
3261
3262 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3263 { "SLB ADC4 Mux", "OB67", "OB67" },
3264 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3265
3266 { "SLBTX", NULL, "SLB" },
3267 { "SLBTX", NULL, "SLB ADC1 Mux" },
3268 { "SLBTX", NULL, "SLB ADC2 Mux" },
3269 { "SLBTX", NULL, "SLB ADC3 Mux" },
3270 { "SLBTX", NULL, "SLB ADC4 Mux" },
3271
3272 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3273 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3274 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3275 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3276 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3277
3278 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3279 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3280
3281 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3282 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3283 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3284 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3285 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3286 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3287
3288 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3289 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3290
3291 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3292 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3293 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3294 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3295 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3296
3297 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3298 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3299
3300 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
3301 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
3302 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3303 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3304 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3305 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3306 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3307 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3308
3309 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
3310 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
3311 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3312 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3313 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3314 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3315 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3316 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3317
3318 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3319 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3320 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3321 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3322 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3323 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3324
3325 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3326 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3327 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3328 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3329 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3330 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3331 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3332
3333 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3334 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3335 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3336 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3337 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3338 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3339 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3340
3341 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3342 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3343 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3344 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3345 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3346 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3347 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3348
3349 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3350 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3351 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3352 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3353 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3354 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3355 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3356
3357 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3358 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3359 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3360 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3361 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3362 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3363 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3364
3365 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3366 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3367 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3368 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3369 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3370 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3371 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3372
3373 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3374 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3375 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3376 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3377 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3378 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3379 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3380
3381 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3382 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3383 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3384 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3385
3386 { "OutBound2", NULL, "OB23 Bypass Mux" },
3387 { "OutBound3", NULL, "OB23 Bypass Mux" },
3388 { "OutBound4", NULL, "OB4 MIX" },
3389 { "OutBound5", NULL, "OB5 MIX" },
3390 { "OutBound6", NULL, "OB6 MIX" },
3391 { "OutBound7", NULL, "OB7 MIX" },
3392
3393 { "OB45", NULL, "OutBound4" },
3394 { "OB45", NULL, "OutBound5" },
3395 { "OB67", NULL, "OutBound6" },
3396 { "OB67", NULL, "OutBound7" },
3397
3398 { "IF1 DAC0", NULL, "AIF1RX" },
3399 { "IF1 DAC1", NULL, "AIF1RX" },
3400 { "IF1 DAC2", NULL, "AIF1RX" },
3401 { "IF1 DAC3", NULL, "AIF1RX" },
3402 { "IF1 DAC4", NULL, "AIF1RX" },
3403 { "IF1 DAC5", NULL, "AIF1RX" },
3404 { "IF1 DAC6", NULL, "AIF1RX" },
3405 { "IF1 DAC7", NULL, "AIF1RX" },
3406 { "IF1 DAC0", NULL, "I2S1" },
3407 { "IF1 DAC1", NULL, "I2S1" },
3408 { "IF1 DAC2", NULL, "I2S1" },
3409 { "IF1 DAC3", NULL, "I2S1" },
3410 { "IF1 DAC4", NULL, "I2S1" },
3411 { "IF1 DAC5", NULL, "I2S1" },
3412 { "IF1 DAC6", NULL, "I2S1" },
3413 { "IF1 DAC7", NULL, "I2S1" },
3414
91159eca
OC		 3415 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3416 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3417 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3418 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3419 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3420 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3421 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3422 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3423
3424 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3425 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3426 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3427 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3428 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3429 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3430 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3431 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3432
3433 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3434 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3435 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3436 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3437 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3438 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3439 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3440 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3441
3442 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3443 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3444 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3445 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3446 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3447 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3448 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3449 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3450
3451 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3452 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3453 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3454 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3455 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3456 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3457 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3458 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3459
3460 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3461 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3462 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3463 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3464 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3465 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3466 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3467 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3468
3469 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3470 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3471 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3472 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3473 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3474 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3475 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3476 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3477
3478 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3479 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3480 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3481 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3482 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3483 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3484 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3485 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3486
3487 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3488 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3489 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3490 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3491 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3492 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3493 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3494 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
0e826e86
OC		 3495
3496 { "IF2 DAC0", NULL, "AIF2RX" },
3497 { "IF2 DAC1", NULL, "AIF2RX" },
3498 { "IF2 DAC2", NULL, "AIF2RX" },
3499 { "IF2 DAC3", NULL, "AIF2RX" },
3500 { "IF2 DAC4", NULL, "AIF2RX" },
3501 { "IF2 DAC5", NULL, "AIF2RX" },
3502 { "IF2 DAC6", NULL, "AIF2RX" },
3503 { "IF2 DAC7", NULL, "AIF2RX" },
3504 { "IF2 DAC0", NULL, "I2S2" },
3505 { "IF2 DAC1", NULL, "I2S2" },
3506 { "IF2 DAC2", NULL, "I2S2" },
3507 { "IF2 DAC3", NULL, "I2S2" },
3508 { "IF2 DAC4", NULL, "I2S2" },
3509 { "IF2 DAC5", NULL, "I2S2" },
3510 { "IF2 DAC6", NULL, "I2S2" },
3511 { "IF2 DAC7", NULL, "I2S2" },
3512
91159eca
OC		 3513 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3514 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3515 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3516 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3517 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3518 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3519 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3520 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3521
3522 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3523 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3524 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3525 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3526 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3527 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3528 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3529 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3530
3531 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3532 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3533 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3534 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3535 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3536 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3537 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3538 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3539
3540 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3541 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3542 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3543 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3544 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3545 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3546 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3547 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3548
3549 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3550 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3551 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3552 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3553 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3554 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3555 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3556 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3557
3558 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3559 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3560 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3561 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3562 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3563 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3564 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3565 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3566
3567 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3568 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3569 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3570 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3571 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3572 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3573 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3574 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3575
3576 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3577 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3578 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3579 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3580 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3581 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3582 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3583 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3584
3585 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3586 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3587 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3588 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3589 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3590 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3591 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3592 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
0e826e86
OC		 3593
3594 { "IF3 DAC", NULL, "AIF3RX" },
3595 { "IF3 DAC", NULL, "I2S3" },
3596
3597 { "IF4 DAC", NULL, "AIF4RX" },
3598 { "IF4 DAC", NULL, "I2S4" },
3599
3600 { "IF3 DAC L", NULL, "IF3 DAC" },
3601 { "IF3 DAC R", NULL, "IF3 DAC" },
3602
3603 { "IF4 DAC L", NULL, "IF4 DAC" },
3604 { "IF4 DAC R", NULL, "IF4 DAC" },
3605
3606 { "SLB DAC0", NULL, "SLBRX" },
3607 { "SLB DAC1", NULL, "SLBRX" },
3608 { "SLB DAC2", NULL, "SLBRX" },
3609 { "SLB DAC3", NULL, "SLBRX" },
3610 { "SLB DAC4", NULL, "SLBRX" },
3611 { "SLB DAC5", NULL, "SLBRX" },
3612 { "SLB DAC6", NULL, "SLBRX" },
3613 { "SLB DAC7", NULL, "SLBRX" },
3614 { "SLB DAC0", NULL, "SLB" },
3615 { "SLB DAC1", NULL, "SLB" },
3616 { "SLB DAC2", NULL, "SLB" },
3617 { "SLB DAC3", NULL, "SLB" },
3618 { "SLB DAC4", NULL, "SLB" },
3619 { "SLB DAC5", NULL, "SLB" },
3620 { "SLB DAC6", NULL, "SLB" },
3621 { "SLB DAC7", NULL, "SLB" },
3622
3623 { "SLB DAC01", NULL, "SLB DAC0" },
3624 { "SLB DAC01", NULL, "SLB DAC1" },
3625 { "SLB DAC23", NULL, "SLB DAC2" },
3626 { "SLB DAC23", NULL, "SLB DAC3" },
3627 { "SLB DAC45", NULL, "SLB DAC4" },
3628 { "SLB DAC45", NULL, "SLB DAC5" },
3629 { "SLB DAC67", NULL, "SLB DAC6" },
3630 { "SLB DAC67", NULL, "SLB DAC7" },
3631
3632 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3633 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3634 { "ADDA1 Mux", "OB 67", "OB67" },
3635
3636 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3637 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3638 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3639 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3640 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3641 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3642
3643 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3644 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3645 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3646 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3647
3648 { "DAC1 FS", NULL, "DAC1 MIXL" },
3649 { "DAC1 FS", NULL, "DAC1 MIXR" },
3650
3651 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
3652 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
3653 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3654 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3655 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3656 { "DAC2 L Mux", "OB 2", "OutBound2" },
3657
3658 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
3659 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
3660 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3661 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3662 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3663 { "DAC2 R Mux", "OB 3", "OutBound3" },
3664 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3665 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3666
3667 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
3668 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
3669 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3670 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3671 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3672 { "DAC3 L Mux", "OB 4", "OutBound4" },
3673
3674 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
3675 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
3676 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3677 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3678 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3679 { "DAC3 R Mux", "OB 5", "OutBound5" },
3680
3681 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
3682 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
3683 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3684 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3685 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3686 { "DAC4 L Mux", "OB 6", "OutBound6" },
3687
3688 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
3689 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
3690 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3691 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3692 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3693 { "DAC4 R Mux", "OB 7", "OutBound7" },
3694
3695 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3696 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3697 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3698 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3699 { "Sidetone Mux", "ADC1", "ADC 1" },
3700 { "Sidetone Mux", "ADC2", "ADC 2" },
90bdbb46 3701 { "Sidetone Mux", NULL, "Sidetone Power" },
0e826e86
OC		 3702
3703 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3704 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3705 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3706 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3707 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3708 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3709 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3710 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3711 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3712 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
38d595e2 3713 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3714
3715 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3716 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3717 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3718 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
6800b5ba 3719 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
38d595e2 3720 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3721 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3722 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3723 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3724 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
6800b5ba 3725 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
38d595e2 3726 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3727
3728 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3729 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3730 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3731 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 3732 { "DD1 MIXL", NULL, "dac mono3 left filter" },
38d595e2 3733 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3734 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3735 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3736 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3737 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 3738 { "DD1 MIXR", NULL, "dac mono3 right filter" },
38d595e2 3739 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3740
3741 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3742 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3743 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3744 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 3745 { "DD2 MIXL", NULL, "dac mono4 left filter" },
38d595e2 3746 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3747 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3748 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3749 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3750 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 3751 { "DD2 MIXR", NULL, "dac mono4 right filter" },
38d595e2 3752 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3753
3754 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3755 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3756 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3757 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3758 { "DD1 MIX", NULL, "DD1 MIXL" },
3759 { "DD1 MIX", NULL, "DD1 MIXR" },
3760 { "DD2 MIX", NULL, "DD2 MIXL" },
3761 { "DD2 MIX", NULL, "DD2 MIXR" },
3762
3763 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3764 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3765 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3766 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3767
3768 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3769 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3770 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3771 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3772
3773 { "DAC 1", NULL, "DAC12 SRC Mux" },
0e826e86 3774 { "DAC 2", NULL, "DAC12 SRC Mux" },
0e826e86 3775 { "DAC 3", NULL, "DAC3 SRC Mux" },
0e826e86
OC		 3776
3777 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3778 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3779 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3780 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3781 { "PDM1 L Mux", NULL, "PDM1 Power" },
3782 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3783 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3784 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3785 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3786 { "PDM1 R Mux", NULL, "PDM1 Power" },
3787 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3788 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3789 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3790 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3791 { "PDM2 L Mux", NULL, "PDM2 Power" },
3792 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3793 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3794 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3795 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3796 { "PDM2 R Mux", NULL, "PDM2 Power" },
3797
3798 { "LOUT1 amp", NULL, "DAC 1" },
3799 { "LOUT2 amp", NULL, "DAC 2" },
3800 { "LOUT3 amp", NULL, "DAC 3" },
3801
683996cb
OC		 3802 { "LOUT1 vref", NULL, "LOUT1 amp" },
3803 { "LOUT2 vref", NULL, "LOUT2 amp" },
3804 { "LOUT3 vref", NULL, "LOUT3 amp" },
3805
3806 { "LOUT1", NULL, "LOUT1 vref" },
3807 { "LOUT2", NULL, "LOUT2 vref" },
3808 { "LOUT3", NULL, "LOUT3 vref" },
0e826e86
OC		 3809
3810 { "PDM1L", NULL, "PDM1 L Mux" },
3811 { "PDM1R", NULL, "PDM1 R Mux" },
3812 { "PDM2L", NULL, "PDM2 L Mux" },
3813 { "PDM2R", NULL, "PDM2 R Mux" },
3814};
3815
2d15d974
BL		 3816static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3817 { "DMIC L2", NULL, "DMIC1 power" },
3818 { "DMIC R2", NULL, "DMIC1 power" },
3819};
3820
3821static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3822 { "DMIC L2", NULL, "DMIC2 power" },
3823 { "DMIC R2", NULL, "DMIC2 power" },
3824};
3825
0e826e86
OC		 3826static int rt5677_hw_params(struct snd_pcm_substream *substream,
3827 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3828{
3829 struct snd_soc_codec *codec = dai->codec;
3830 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3831 unsigned int val_len = 0, val_clk, mask_clk;
3832 int pre_div, bclk_ms, frame_size;
3833
3834 rt5677->lrck[dai->id] = params_rate(params);
30f14b43 3835 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86 3836 if (pre_div < 0) {
8a4bd60a
AP		 3837 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3838 rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86
OC		 3839 return -EINVAL;
3840 }
3841 frame_size = snd_soc_params_to_frame_size(params);
3842 if (frame_size < 0) {
3843 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3844 return -EINVAL;
3845 }
3846 bclk_ms = frame_size > 32;
3847 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
3848
3849 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
3850 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
3851 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
3852 bclk_ms, pre_div, dai->id);
3853
3854 switch (params_width(params)) {
3855 case 16:
3856 break;
3857 case 20:
3858 val_len |= RT5677_I2S_DL_20;
3859 break;
3860 case 24:
3861 val_len |= RT5677_I2S_DL_24;
3862 break;
3863 case 8:
3864 val_len |= RT5677_I2S_DL_8;
3865 break;
3866 default:
3867 return -EINVAL;
3868 }
3869
3870 switch (dai->id) {
3871 case RT5677_AIF1:
3872 mask_clk = RT5677_I2S_PD1_MASK;
3873 val_clk = pre_div << RT5677_I2S_PD1_SFT;
3874 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3875 RT5677_I2S_DL_MASK, val_len);
3876 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3877 mask_clk, val_clk);
3878 break;
3879 case RT5677_AIF2:
3880 mask_clk = RT5677_I2S_PD2_MASK;
3881 val_clk = pre_div << RT5677_I2S_PD2_SFT;
3882 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3883 RT5677_I2S_DL_MASK, val_len);
3884 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3885 mask_clk, val_clk);
3886 break;
3887 case RT5677_AIF3:
3888 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
3889 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
3890 pre_div << RT5677_I2S_PD3_SFT;
3891 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3892 RT5677_I2S_DL_MASK, val_len);
3893 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3894 mask_clk, val_clk);
3895 break;
3896 case RT5677_AIF4:
3897 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
3898 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
3899 pre_div << RT5677_I2S_PD4_SFT;
3900 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3901 RT5677_I2S_DL_MASK, val_len);
3902 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3903 mask_clk, val_clk);
3904 break;
3905 default:
3906 break;
3907 }
3908
3909 return 0;
3910}
3911
3912static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3913{
3914 struct snd_soc_codec *codec = dai->codec;
3915 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3916 unsigned int reg_val = 0;
3917
3918 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3919 case SND_SOC_DAIFMT_CBM_CFM:
3920 rt5677->master[dai->id] = 1;
3921 break;
3922 case SND_SOC_DAIFMT_CBS_CFS:
3923 reg_val |= RT5677_I2S_MS_S;
3924 rt5677->master[dai->id] = 0;
3925 break;
3926 default:
3927 return -EINVAL;
3928 }
3929
3930 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3931 case SND_SOC_DAIFMT_NB_NF:
3932 break;
3933 case SND_SOC_DAIFMT_IB_NF:
3934 reg_val |= RT5677_I2S_BP_INV;
3935 break;
3936 default:
3937 return -EINVAL;
3938 }
3939
3940 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3941 case SND_SOC_DAIFMT_I2S:
3942 break;
3943 case SND_SOC_DAIFMT_LEFT_J:
3944 reg_val |= RT5677_I2S_DF_LEFT;
3945 break;
3946 case SND_SOC_DAIFMT_DSP_A:
3947 reg_val |= RT5677_I2S_DF_PCM_A;
3948 break;
3949 case SND_SOC_DAIFMT_DSP_B:
3950 reg_val |= RT5677_I2S_DF_PCM_B;
3951 break;
3952 default:
3953 return -EINVAL;
3954 }
3955
3956 switch (dai->id) {
3957 case RT5677_AIF1:
3958 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3959 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3960 RT5677_I2S_DF_MASK, reg_val);
3961 break;
3962 case RT5677_AIF2:
3963 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3964 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3965 RT5677_I2S_DF_MASK, reg_val);
3966 break;
3967 case RT5677_AIF3:
3968 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3969 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3970 RT5677_I2S_DF_MASK, reg_val);
3971 break;
3972 case RT5677_AIF4:
3973 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3974 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3975 RT5677_I2S_DF_MASK, reg_val);
3976 break;
3977 default:
3978 break;
3979 }
3980
3981
3982 return 0;
3983}
3984
3985static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3986 int clk_id, unsigned int freq, int dir)
3987{
3988 struct snd_soc_codec *codec = dai->codec;
3989 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3990 unsigned int reg_val = 0;
3991
3992 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
3993 return 0;
3994
3995 switch (clk_id) {
3996 case RT5677_SCLK_S_MCLK:
3997 reg_val |= RT5677_SCLK_SRC_MCLK;
3998 break;
3999 case RT5677_SCLK_S_PLL1:
4000 reg_val |= RT5677_SCLK_SRC_PLL1;
4001 break;
4002 case RT5677_SCLK_S_RCCLK:
4003 reg_val |= RT5677_SCLK_SRC_RCCLK;
4004 break;
4005 default:
4006 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4007 return -EINVAL;
4008 }
4009 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4010 RT5677_SCLK_SRC_MASK, reg_val);
4011 rt5677->sysclk = freq;
4012 rt5677->sysclk_src = clk_id;
4013
4014 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4015
4016 return 0;
4017}
4018
4019/**
4020 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4021 * @freq_in: external clock provided to codec.
4022 * @freq_out: target clock which codec works on.
4023 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4024 *
4025 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4026 *
4027 * Returns 0 for success or negative error code.
4028 */
4029static int rt5677_pll_calc(const unsigned int freq_in,
099d334e 4030 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
0e826e86 4031{
099d334e 4032 if (RT5677_PLL_INP_MIN > freq_in)
0e826e86
OC		 4033 return -EINVAL;
4034
099d334e 4035 return rl6231_pll_calc(freq_in, freq_out, pll_code);
0e826e86
OC		 4036}
4037
4038static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4039 unsigned int freq_in, unsigned int freq_out)
4040{
4041 struct snd_soc_codec *codec = dai->codec;
4042 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
099d334e 4043 struct rl6231_pll_code pll_code;
0e826e86
OC		 4044 int ret;
4045
4046 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4047 freq_out == rt5677->pll_out)
4048 return 0;
4049
4050 if (!freq_in || !freq_out) {
4051 dev_dbg(codec->dev, "PLL disabled\n");
4052
4053 rt5677->pll_in = 0;
4054 rt5677->pll_out = 0;
4055 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4056 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4057 return 0;
4058 }
4059
4060 switch (source) {
4061 case RT5677_PLL1_S_MCLK:
4062 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4063 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4064 break;
4065 case RT5677_PLL1_S_BCLK1:
4066 case RT5677_PLL1_S_BCLK2:
4067 case RT5677_PLL1_S_BCLK3:
4068 case RT5677_PLL1_S_BCLK4:
4069 switch (dai->id) {
4070 case RT5677_AIF1:
4071 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4072 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4073 break;
4074 case RT5677_AIF2:
4075 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4076 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4077 break;
4078 case RT5677_AIF3:
4079 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4080 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4081 break;
4082 case RT5677_AIF4:
4083 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4084 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4085 break;
4086 default:
4087 break;
4088 }
4089 break;
4090 default:
4091 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4092 return -EINVAL;
4093 }
4094
4095 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4096 if (ret < 0) {
4097 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4098 return ret;
4099 }
4100
099d334e
AL		 4101 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4102 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4103 pll_code.n_code, pll_code.k_code);
0e826e86
OC		 4104
4105 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
099d334e 4106 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
0e826e86
OC		 4107 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4108 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4109 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4110
4111 rt5677->pll_in = freq_in;
4112 rt5677->pll_out = freq_out;
4113 rt5677->pll_src = source;
4114
4115 return 0;
4116}
4117
48561afe
OC		 4118static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4119 unsigned int rx_mask, int slots, int slot_width)
4120{
4121 struct snd_soc_codec *codec = dai->codec;
e4b7e6a8 4122 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
9913b9f5 4123 unsigned int val = 0, slot_width_25 = 0;
48561afe
OC		 4124
4125 if (rx_mask || tx_mask)
4126 val |= (1 << 12);
4127
4128 switch (slots) {
4129 case 4:
4130 val |= (1 << 10);
4131 break;
4132 case 6:
4133 val |= (2 << 10);
4134 break;
4135 case 8:
4136 val |= (3 << 10);
4137 break;
4138 case 2:
4139 default:
4140 break;
4141 }
4142
4143 switch (slot_width) {
4144 case 20:
4145 val |= (1 << 8);
4146 break;
9913b9f5
OC		 4147 case 25:
4148 slot_width_25 = 0x8080;
48561afe
OC		 4149 case 24:
4150 val |= (2 << 8);
4151 break;
4152 case 32:
4153 val |= (3 << 8);
4154 break;
4155 case 16:
4156 default:
4157 break;
4158 }
4159
4160 switch (dai->id) {
4161 case RT5677_AIF1:
e4b7e6a8
OC		 4162 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4163 val);
9913b9f5
OC		 4164 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4165 slot_width_25);
48561afe
OC		 4166 break;
4167 case RT5677_AIF2:
e4b7e6a8
OC		 4168 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4169 val);
9913b9f5
OC		 4170 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4171 slot_width_25);
48561afe
OC		 4172 break;
4173 default:
4174 break;
4175 }
4176
4177 return 0;
4178}
4179
0e826e86
OC		 4180static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4181 enum snd_soc_bias_level level)
4182{
4183 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4184
4185 switch (level) {
4186 case SND_SOC_BIAS_ON:
4187 break;
4188
4189 case SND_SOC_BIAS_PREPARE:
4190 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
af48f1d0
OC		 4191 rt5677_set_dsp_vad(codec, false);
4192
0e826e86
OC		 4193 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4194 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4195 0x0055);
4196 regmap_update_bits(rt5677->regmap,
4197 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4198 0x0f00, 0x0f00);
4199 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
683996cb 4200 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
0e826e86
OC		 4201 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4202 RT5677_PWR_BG | RT5677_PWR_VREF2,
4203 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4204 RT5677_PWR_BG | RT5677_PWR_VREF2);
683996cb 4205 rt5677->is_vref_slow = false;
0e826e86
OC		 4206 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4207 RT5677_PWR_CORE, RT5677_PWR_CORE);
4208 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4209 0x1, 0x1);
4210 }
4211 break;
4212
4213 case SND_SOC_BIAS_STANDBY:
4214 break;
4215
4216 case SND_SOC_BIAS_OFF:
4217 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4218 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4219 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
f18803a3 4220 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
0e826e86
OC		 4221 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4222 regmap_update_bits(rt5677->regmap,
4223 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
af48f1d0
OC		 4224
4225 if (rt5677->dsp_vad_en)
4226 rt5677_set_dsp_vad(codec, true);
0e826e86
OC		 4227 break;
4228
4229 default:
4230 break;
4231 }
4232 codec->dapm.bias_level = level;
4233
4234 return 0;
4235}
4236
44caf764
OC		 4237#ifdef CONFIG_GPIOLIB
4238static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4239{
4240 return container_of(chip, struct rt5677_priv, gpio_chip);
4241}
4242
4243static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4244{
4245 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4246
4247 switch (offset) {
4248 case RT5677_GPIO1 ... RT5677_GPIO5:
4249 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4250 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4251 break;
4252
4253 case RT5677_GPIO6:
4254 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4255 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4256 break;
4257
4258 default:
4259 break;
4260 }
4261}
4262
4263static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4264 unsigned offset, int value)
4265{
4266 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4267
4268 switch (offset) {
4269 case RT5677_GPIO1 ... RT5677_GPIO5:
4270 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4271 0x3 << (offset * 3 + 1),
4272 (0x2 | !!value) << (offset * 3 + 1));
4273 break;
4274
4275 case RT5677_GPIO6:
4276 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4277 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4278 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4279 break;
4280
4281 default:
4282 break;
4283 }
4284
4285 return 0;
4286}
4287
4288static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4289{
4290 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4291 int value, ret;
4292
4293 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4294 if (ret < 0)
4295 return ret;
4296
4297 return (value & (0x1 << offset)) >> offset;
4298}
4299
4300static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4301{
4302 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4303
4304 switch (offset) {
4305 case RT5677_GPIO1 ... RT5677_GPIO5:
4306 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4307 0x1 << (offset * 3 + 2), 0x0);
4308 break;
4309
4310 case RT5677_GPIO6:
4311 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4312 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4313 break;
4314
4315 default:
4316 break;
4317 }
4318
4319 return 0;
4320}
4321
40eb90a1
AP		 4322/** Configures the gpio as
4323 * 0 - floating
4324 * 1 - pull down
4325 * 2 - pull up
4326 */
4327static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4328 int value)
4329{
4330 int shift;
4331
4332 switch (offset) {
4333 case RT5677_GPIO1 ... RT5677_GPIO2:
4334 shift = 2 * (1 - offset);
4335 regmap_update_bits(rt5677->regmap,
4336 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4337 0x3 << shift,
4338 (value & 0x3) << shift);
4339 break;
4340
4341 case RT5677_GPIO3 ... RT5677_GPIO6:
4342 shift = 2 * (9 - offset);
4343 regmap_update_bits(rt5677->regmap,
4344 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4345 0x3 << shift,
4346 (value & 0x3) << shift);
4347 break;
4348
4349 default:
4350 break;
4351 }
4352}
4353
5e3363ad
OC		 4354static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4355{
4356 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4357 struct regmap_irq_chip_data *data = rt5677->irq_data;
4358 int irq;
4359
4360 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4361 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4362 (rt5677->pdata.jd1_gpio == 2 &&
4363 offset == RT5677_GPIO2) ||
4364 (rt5677->pdata.jd1_gpio == 3 &&
4365 offset == RT5677_GPIO3)) {
4366 irq = RT5677_IRQ_JD1;
4367 } else {
4368 return -ENXIO;
4369 }
4370 }
4371
4372 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4373 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4374 (rt5677->pdata.jd2_gpio == 2 &&
4375 offset == RT5677_GPIO5) ||
4376 (rt5677->pdata.jd2_gpio == 3 &&
4377 offset == RT5677_GPIO6)) {
4378 irq = RT5677_IRQ_JD2;
4379 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4380 offset == RT5677_GPIO4) ||
4381 (rt5677->pdata.jd3_gpio == 2 &&
4382 offset == RT5677_GPIO5) ||
4383 (rt5677->pdata.jd3_gpio == 3 &&
4384 offset == RT5677_GPIO6)) {
4385 irq = RT5677_IRQ_JD3;
4386 } else {
4387 return -ENXIO;
4388 }
4389 }
4390
4391 return regmap_irq_get_virq(data, irq);
4392}
4393
44caf764
OC		 4394static struct gpio_chip rt5677_template_chip = {
4395 .label = "rt5677",
4396 .owner = THIS_MODULE,
4397 .direction_output = rt5677_gpio_direction_out,
4398 .set = rt5677_gpio_set,
4399 .direction_input = rt5677_gpio_direction_in,
4400 .get = rt5677_gpio_get,
5e3363ad 4401 .to_irq = rt5677_to_irq,
44caf764
OC		 4402 .can_sleep = 1,
4403};
4404
4405static void rt5677_init_gpio(struct i2c_client *i2c)
4406{
4407 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4408 int ret;
4409
4410 rt5677->gpio_chip = rt5677_template_chip;
4411 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4412 rt5677->gpio_chip.dev = &i2c->dev;
4413 rt5677->gpio_chip.base = -1;
4414
4415 ret = gpiochip_add(&rt5677->gpio_chip);
4416 if (ret != 0)
4417 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4418}
4419
4420static void rt5677_free_gpio(struct i2c_client *i2c)
4421{
4422 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
44caf764 4423
5d5e63af 4424 gpiochip_remove(&rt5677->gpio_chip);
44caf764
OC		 4425}
4426#else
45b6e1d3
AP		 4427static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4428 int value)
4429{
4430}
4431
44caf764
OC		 4432static void rt5677_init_gpio(struct i2c_client *i2c)
4433{
4434}
4435
4436static void rt5677_free_gpio(struct i2c_client *i2c)
4437{
4438}
4439#endif
4440
0e826e86
OC		 4441static int rt5677_probe(struct snd_soc_codec *codec)
4442{
4443 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
40eb90a1 4444 int i;
0e826e86
OC		 4445
4446 rt5677->codec = codec;
4447
2d15d974
BL		 4448 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4449 snd_soc_dapm_add_routes(&codec->dapm,
4450 rt5677_dmic2_clk_2,
4451 ARRAY_SIZE(rt5677_dmic2_clk_2));
4452 } else { /*use dmic1 clock by default*/
4453 snd_soc_dapm_add_routes(&codec->dapm,
4454 rt5677_dmic2_clk_1,
4455 ARRAY_SIZE(rt5677_dmic2_clk_1));
4456 }
4457
0e826e86
OC		 4458 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
4459
4460 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4461 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4462
40eb90a1
AP		 4463 for (i = 0; i < RT5677_GPIO_NUM; i++)
4464 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4465
5e3363ad
OC		 4466 if (rt5677->irq_data) {
4467 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4468 0x8000);
4469 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4470 0x0008);
4471
4472 if (rt5677->pdata.jd1_gpio)
4473 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4474 RT5677_SEL_GPIO_JD1_MASK,
4475 rt5677->pdata.jd1_gpio <<
4476 RT5677_SEL_GPIO_JD1_SFT);
4477
4478 if (rt5677->pdata.jd2_gpio)
4479 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4480 RT5677_SEL_GPIO_JD2_MASK,
4481 rt5677->pdata.jd2_gpio <<
4482 RT5677_SEL_GPIO_JD2_SFT);
4483
4484 if (rt5677->pdata.jd3_gpio)
4485 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4486 RT5677_SEL_GPIO_JD3_MASK,
4487 rt5677->pdata.jd3_gpio <<
4488 RT5677_SEL_GPIO_JD3_SFT);
4489 }
4490
af48f1d0 4491 mutex_init(&rt5677->dsp_cmd_lock);
6fe17da0 4492 mutex_init(&rt5677->dsp_pri_lock);
af48f1d0 4493
0e826e86
OC		 4494 return 0;
4495}
4496
4497static int rt5677_remove(struct snd_soc_codec *codec)
4498{
4499 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4500
4501 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
f9f6a592
AP		 4502 if (gpio_is_valid(rt5677->pow_ldo2))
4503 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
0e826e86
OC		 4504
4505 return 0;
4506}
4507
4508#ifdef CONFIG_PM
4509static int rt5677_suspend(struct snd_soc_codec *codec)
4510{
4511 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4512
af48f1d0
OC		 4513 if (!rt5677->dsp_vad_en) {
4514 regcache_cache_only(rt5677->regmap, true);
4515 regcache_mark_dirty(rt5677->regmap);
4516 }
4517
f9f6a592
AP		 4518 if (gpio_is_valid(rt5677->pow_ldo2))
4519 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
0e826e86
OC		 4520
4521 return 0;
4522}
4523
4524static int rt5677_resume(struct snd_soc_codec *codec)
4525{
4526 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4527
f9f6a592
AP		 4528 if (gpio_is_valid(rt5677->pow_ldo2)) {
4529 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4530 msleep(10);
4531 }
af48f1d0
OC		 4532
4533 if (!rt5677->dsp_vad_en) {
4534 regcache_cache_only(rt5677->regmap, false);
4535 regcache_sync(rt5677->regmap);
4536 }
0e826e86
OC		 4537
4538 return 0;
4539}
4540#else
4541#define rt5677_suspend NULL
4542#define rt5677_resume NULL
4543#endif
4544
19ba484d
OC		 4545static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4546{
4547 struct i2c_client *client = context;
4548 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4549
6fe17da0
OC		 4550 if (rt5677->is_dsp_mode) {
4551 if (reg > 0xff) {
4552 mutex_lock(&rt5677->dsp_pri_lock);
4553 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4554 reg & 0xff);
4555 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4556 mutex_unlock(&rt5677->dsp_pri_lock);
4557 } else {
4558 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4559 }
4560 } else {
19ba484d 4561 regmap_read(rt5677->regmap_physical, reg, val);
6fe17da0 4562 }
19ba484d
OC		 4563
4564 return 0;
4565}
4566
4567static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4568{
4569 struct i2c_client *client = context;
4570 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4571
6fe17da0
OC		 4572 if (rt5677->is_dsp_mode) {
4573 if (reg > 0xff) {
4574 mutex_lock(&rt5677->dsp_pri_lock);
4575 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4576 reg & 0xff);
4577 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4578 val);
4579 mutex_unlock(&rt5677->dsp_pri_lock);
4580 } else {
4581 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4582 }
4583 } else {
19ba484d 4584 regmap_write(rt5677->regmap_physical, reg, val);
6fe17da0 4585 }
19ba484d
OC		 4586
4587 return 0;
4588}
4589
0e826e86
OC		 4590#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4591#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4592 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4593
4594static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4595 .hw_params = rt5677_hw_params,
4596 .set_fmt = rt5677_set_dai_fmt,
4597 .set_sysclk = rt5677_set_dai_sysclk,
4598 .set_pll = rt5677_set_dai_pll,
48561afe 4599 .set_tdm_slot = rt5677_set_tdm_slot,
0e826e86
OC		 4600};
4601
4602static struct snd_soc_dai_driver rt5677_dai[] = {
4603 {
4604 .name = "rt5677-aif1",
4605 .id = RT5677_AIF1,
4606 .playback = {
4607 .stream_name = "AIF1 Playback",
4608 .channels_min = 1,
4609 .channels_max = 2,
4610 .rates = RT5677_STEREO_RATES,
4611 .formats = RT5677_FORMATS,
4612 },
4613 .capture = {
4614 .stream_name = "AIF1 Capture",
4615 .channels_min = 1,
4616 .channels_max = 2,
4617 .rates = RT5677_STEREO_RATES,
4618 .formats = RT5677_FORMATS,
4619 },
4620 .ops = &rt5677_aif_dai_ops,
4621 },
4622 {
4623 .name = "rt5677-aif2",
4624 .id = RT5677_AIF2,
4625 .playback = {
4626 .stream_name = "AIF2 Playback",
4627 .channels_min = 1,
4628 .channels_max = 2,
4629 .rates = RT5677_STEREO_RATES,
4630 .formats = RT5677_FORMATS,
4631 },
4632 .capture = {
4633 .stream_name = "AIF2 Capture",
4634 .channels_min = 1,
4635 .channels_max = 2,
4636 .rates = RT5677_STEREO_RATES,
4637 .formats = RT5677_FORMATS,
4638 },
4639 .ops = &rt5677_aif_dai_ops,
4640 },
4641 {
4642 .name = "rt5677-aif3",
4643 .id = RT5677_AIF3,
4644 .playback = {
4645 .stream_name = "AIF3 Playback",
4646 .channels_min = 1,
4647 .channels_max = 2,
4648 .rates = RT5677_STEREO_RATES,
4649 .formats = RT5677_FORMATS,
4650 },
4651 .capture = {
4652 .stream_name = "AIF3 Capture",
4653 .channels_min = 1,
4654 .channels_max = 2,
4655 .rates = RT5677_STEREO_RATES,
4656 .formats = RT5677_FORMATS,
4657 },
4658 .ops = &rt5677_aif_dai_ops,
4659 },
4660 {
4661 .name = "rt5677-aif4",
4662 .id = RT5677_AIF4,
4663 .playback = {
4664 .stream_name = "AIF4 Playback",
4665 .channels_min = 1,
4666 .channels_max = 2,
4667 .rates = RT5677_STEREO_RATES,
4668 .formats = RT5677_FORMATS,
4669 },
4670 .capture = {
4671 .stream_name = "AIF4 Capture",
4672 .channels_min = 1,
4673 .channels_max = 2,
4674 .rates = RT5677_STEREO_RATES,
4675 .formats = RT5677_FORMATS,
4676 },
4677 .ops = &rt5677_aif_dai_ops,
4678 },
4679 {
4680 .name = "rt5677-slimbus",
4681 .id = RT5677_AIF5,
4682 .playback = {
4683 .stream_name = "SLIMBus Playback",
4684 .channels_min = 1,
4685 .channels_max = 2,
4686 .rates = RT5677_STEREO_RATES,
4687 .formats = RT5677_FORMATS,
4688 },
4689 .capture = {
4690 .stream_name = "SLIMBus Capture",
4691 .channels_min = 1,
4692 .channels_max = 2,
4693 .rates = RT5677_STEREO_RATES,
4694 .formats = RT5677_FORMATS,
4695 },
4696 .ops = &rt5677_aif_dai_ops,
4697 },
4698};
4699
4700static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4701 .probe = rt5677_probe,
4702 .remove = rt5677_remove,
4703 .suspend = rt5677_suspend,
4704 .resume = rt5677_resume,
4705 .set_bias_level = rt5677_set_bias_level,
4706 .idle_bias_off = true,
4707 .controls = rt5677_snd_controls,
4708 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4709 .dapm_widgets = rt5677_dapm_widgets,
4710 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4711 .dapm_routes = rt5677_dapm_routes,
4712 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4713};
4714
19ba484d
OC		 4715static const struct regmap_config rt5677_regmap_physical = {
4716 .name = "physical",
4717 .reg_bits = 8,
4718 .val_bits = 16,
4719
6fe17da0
OC		 4720 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4721 RT5677_PR_SPACING),
19ba484d
OC		 4722 .readable_reg = rt5677_readable_register,
4723
4724 .cache_type = REGCACHE_NONE,
6fe17da0
OC		 4725 .ranges = rt5677_ranges,
4726 .num_ranges = ARRAY_SIZE(rt5677_ranges),
19ba484d
OC		 4727};
4728
0e826e86
OC		 4729static const struct regmap_config rt5677_regmap = {
4730 .reg_bits = 8,
4731 .val_bits = 16,
4732
4733 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4734 RT5677_PR_SPACING),
4735
4736 .volatile_reg = rt5677_volatile_register,
4737 .readable_reg = rt5677_readable_register,
19ba484d
OC		 4738 .reg_read = rt5677_read,
4739 .reg_write = rt5677_write,
0e826e86
OC		 4740
4741 .cache_type = REGCACHE_RBTREE,
4742 .reg_defaults = rt5677_reg,
4743 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4744 .ranges = rt5677_ranges,
4745 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4746};
4747
4748static const struct i2c_device_id rt5677_i2c_id[] = {
ab1f7095
OC		 4749 { "rt5677", RT5677 },
4750 { "rt5676", RT5676 },
0e826e86
OC		 4751 { }
4752};
4753MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4754
f9f6a592
AP		 4755static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4756{
6f67c380
AP		 4757 rt5677->pdata.in1_diff = of_property_read_bool(np,
4758 "realtek,in1-differential");
4759 rt5677->pdata.in2_diff = of_property_read_bool(np,
4760 "realtek,in2-differential");
4761 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4762 "realtek,lout1-differential");
4763 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4764 "realtek,lout2-differential");
4765 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4766 "realtek,lout3-differential");
4767
f9f6a592
AP		 4768 rt5677->pow_ldo2 = of_get_named_gpio(np,
4769 "realtek,pow-ldo2-gpio", 0);
4770
4771 /*
4772 * POW_LDO2 is optional (it may be statically tied on the board).
4773 * -ENOENT means that the property doesn't exist, i.e. there is no
4774 * GPIO, so is not an error. Any other error code means the property
4775 * exists, but could not be parsed.
4776 */
4777 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4778 (rt5677->pow_ldo2 != -ENOENT))
4779 return rt5677->pow_ldo2;
4780
40eb90a1
AP		 4781 of_property_read_u8_array(np, "realtek,gpio-config",
4782 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4783
5e3363ad
OC		 4784 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4785 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4786 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4787
f9f6a592
AP		 4788 return 0;
4789}
4790
5e3363ad
OC		 4791static struct regmap_irq rt5677_irqs[] = {
4792 [RT5677_IRQ_JD1] = {
4793 .reg_offset = 0,
4794 .mask = RT5677_EN_IRQ_GPIO_JD1,
4795 },
4796 [RT5677_IRQ_JD2] = {
4797 .reg_offset = 0,
4798 .mask = RT5677_EN_IRQ_GPIO_JD2,
4799 },
4800 [RT5677_IRQ_JD3] = {
4801 .reg_offset = 0,
4802 .mask = RT5677_EN_IRQ_GPIO_JD3,
4803 },
4804};
4805
4806static struct regmap_irq_chip rt5677_irq_chip = {
4807 .name = "rt5677",
4808 .irqs = rt5677_irqs,
4809 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4810
4811 .num_regs = 1,
4812 .status_base = RT5677_IRQ_CTRL1,
4813 .mask_base = RT5677_IRQ_CTRL1,
4814 .mask_invert = 1,
4815};
4816
35d40d10 4817static int rt5677_init_irq(struct i2c_client *i2c)
5e3363ad
OC		 4818{
4819 int ret;
4820 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4821
4822 if (!rt5677->pdata.jd1_gpio &&
4823 !rt5677->pdata.jd2_gpio &&
4824 !rt5677->pdata.jd3_gpio)
4825 return 0;
4826
4827 if (!i2c->irq) {
4828 dev_err(&i2c->dev, "No interrupt specified\n");
4829 return -EINVAL;
4830 }
4831
4832 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4833 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4834 &rt5677_irq_chip, &rt5677->irq_data);
4835
4836 if (ret != 0) {
4837 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
4838 return ret;
4839 }
4840
4841 return 0;
4842}
4843
35d40d10 4844static void rt5677_free_irq(struct i2c_client *i2c)
5e3363ad
OC		 4845{
4846 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4847
4848 if (rt5677->irq_data)
4849 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
4850}
4851
0e826e86
OC		 4852static int rt5677_i2c_probe(struct i2c_client *i2c,
4853 const struct i2c_device_id *id)
4854{
4855 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
4856 struct rt5677_priv *rt5677;
4857 int ret;
4858 unsigned int val;
4859
4860 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
4861 GFP_KERNEL);
4862 if (rt5677 == NULL)
4863 return -ENOMEM;
4864
4865 i2c_set_clientdata(i2c, rt5677);
4866
ab1f7095
OC		 4867 rt5677->type = id->driver_data;
4868
0e826e86
OC		 4869 if (pdata)
4870 rt5677->pdata = *pdata;
4871
f9f6a592
AP		 4872 if (i2c->dev.of_node) {
4873 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
4874 if (ret) {
4875 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
4876 ret);
4877 return ret;
4878 }
4879 } else {
4880 rt5677->pow_ldo2 = -EINVAL;
4881 }
4882
4883 if (gpio_is_valid(rt5677->pow_ldo2)) {
4884 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
4885 GPIOF_OUT_INIT_HIGH,
4886 "RT5677 POW_LDO2");
4887 if (ret < 0) {
4888 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
4889 rt5677->pow_ldo2, ret);
4890 return ret;
4891 }
4892 /* Wait a while until I2C bus becomes available. The datasheet
4893 * does not specify the exact we should wait but startup
4894 * sequence mentiones at least a few milliseconds.
4895 */
4896 msleep(10);
4897 }
4898
19ba484d
OC		 4899 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
4900 &rt5677_regmap_physical);
4901 if (IS_ERR(rt5677->regmap_physical)) {
4902 ret = PTR_ERR(rt5677->regmap_physical);
4903 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4904 ret);
4905 return ret;
4906 }
4907
4908 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
0e826e86
OC		 4909 if (IS_ERR(rt5677->regmap)) {
4910 ret = PTR_ERR(rt5677->regmap);
4911 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4912 ret);
4913 return ret;
4914 }
4915
4916 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
4917 if (val != RT5677_DEVICE_ID) {
4918 dev_err(&i2c->dev,
4919 "Device with ID register %x is not rt5677\n", val);
4920 return -ENODEV;
4921 }
4922
4923 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4924
4925 ret = regmap_register_patch(rt5677->regmap, init_list,
4926 ARRAY_SIZE(init_list));
4927 if (ret != 0)
4928 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4929
4930 if (rt5677->pdata.in1_diff)
4931 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4932 RT5677_IN_DF1, RT5677_IN_DF1);
4933
4934 if (rt5677->pdata.in2_diff)
4935 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4936 RT5677_IN_DF2, RT5677_IN_DF2);
4937
6f67c380
AP		 4938 if (rt5677->pdata.lout1_diff)
4939 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4940 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
4941
4942 if (rt5677->pdata.lout2_diff)
4943 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4944 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
4945
4946 if (rt5677->pdata.lout3_diff)
4947 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4948 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
4949
2d15d974
BL		 4950 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4951 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
4952 RT5677_GPIO5_FUNC_MASK,
4953 RT5677_GPIO5_FUNC_DMIC);
4954 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4955 RT5677_GPIO5_DIR_MASK,
4956 RT5677_GPIO5_DIR_OUT);
4957 }
4958
277880a3
OC		 4959 if (rt5677->pdata.micbias1_vdd_3v3)
4960 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
4961 RT5677_MICBIAS1_CTRL_VDD_MASK,
4962 RT5677_MICBIAS1_CTRL_VDD_3_3V);
4963
44caf764 4964 rt5677_init_gpio(i2c);
35d40d10 4965 rt5677_init_irq(i2c);
44caf764 4966
d0bdcb91
AL		 4967 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
4968 rt5677_dai, ARRAY_SIZE(rt5677_dai));
0e826e86
OC		 4969}
4970
4971static int rt5677_i2c_remove(struct i2c_client *i2c)
4972{
4973 snd_soc_unregister_codec(&i2c->dev);
35d40d10 4974 rt5677_free_irq(i2c);
44caf764 4975 rt5677_free_gpio(i2c);
0e826e86
OC		 4976
4977 return 0;
4978}
4979
4980static struct i2c_driver rt5677_i2c_driver = {
4981 .driver = {
4982 .name = "rt5677",
4983 .owner = THIS_MODULE,
4984 },
4985 .probe = rt5677_i2c_probe,
4986 .remove = rt5677_i2c_remove,
4987 .id_table = rt5677_i2c_id,
4988};
c8cfbec8 4989module_i2c_driver(rt5677_i2c_driver);
0e826e86
OC		 4990
4991MODULE_DESCRIPTION("ASoC RT5677 driver");
4992MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
4993MODULE_LICENSE("GPL v2");
Ubuntu Hirsute Linux kernel mirror