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[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / rt5677.c
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d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
0e826e86
OC		 2/*
3 * rt5677.c -- RT5677 ALSA SoC audio codec driver
4 *
5 * Copyright 2013 Realtek Semiconductor Corp.
6 * Author: Oder Chiou <oder_chiou@realtek.com>
0e826e86
OC		 7 */
8
89128534 9#include <linux/acpi.h>
0e826e86
OC		 10#include <linux/fs.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/regmap.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
af48f1d0 20#include <linux/firmware.h>
ddc9e69b 21#include <linux/of_device.h>
9bfde721 22#include <linux/property.h>
0e826e86
OC		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
30f14b43 31#include "rl6231.h"
0e826e86 32#include "rt5677.h"
af48f1d0 33#include "rt5677-spi.h"
0e826e86
OC		 34
35#define RT5677_DEVICE_ID 0x6327
36
37#define RT5677_PR_RANGE_BASE (0xff + 1)
38#define RT5677_PR_SPACING 0x100
39
40#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
41
42static const struct regmap_range_cfg rt5677_ranges[] = {
43 {
44 .name = "PR",
45 .range_min = RT5677_PR_BASE,
46 .range_max = RT5677_PR_BASE + 0xfd,
47 .selector_reg = RT5677_PRIV_INDEX,
48 .selector_mask = 0xff,
49 .selector_shift = 0x0,
50 .window_start = RT5677_PRIV_DATA,
51 .window_len = 0x1,
52 },
53};
54
8019ff6c 55static const struct reg_sequence init_list[] = {
2dfe2b08
OC		 56 {RT5677_ASRC_12, 0x0018},
57 {RT5677_PR_BASE + 0x3d, 0x364d},
58 {RT5677_PR_BASE + 0x17, 0x4fc0},
59 {RT5677_PR_BASE + 0x13, 0x0312},
60 {RT5677_PR_BASE + 0x1e, 0x0000},
61 {RT5677_PR_BASE + 0x12, 0x0eaa},
62 {RT5677_PR_BASE + 0x14, 0x018a},
74d6ea52
BL		 63 {RT5677_PR_BASE + 0x15, 0x0490},
64 {RT5677_PR_BASE + 0x38, 0x0f71},
65 {RT5677_PR_BASE + 0x39, 0x0f71},
0e826e86
OC		 66};
67#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
68
69static const struct reg_default rt5677_reg[] = {
70 {RT5677_RESET , 0x0000},
71 {RT5677_LOUT1 , 0xa800},
72 {RT5677_IN1 , 0x0000},
73 {RT5677_MICBIAS , 0x0000},
74 {RT5677_SLIMBUS_PARAM , 0x0000},
75 {RT5677_SLIMBUS_RX , 0x0000},
76 {RT5677_SLIMBUS_CTRL , 0x0000},
77 {RT5677_SIDETONE_CTRL , 0x000b},
78 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
79 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
80 {RT5677_DAC4_DIG_VOL , 0xafaf},
81 {RT5677_DAC3_DIG_VOL , 0xafaf},
82 {RT5677_DAC1_DIG_VOL , 0xafaf},
83 {RT5677_DAC2_DIG_VOL , 0xafaf},
84 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
85 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_STO1_2_ADC_BST , 0x0000},
88 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
89 {RT5677_ADC_BST_CTRL2 , 0x0000},
90 {RT5677_STO3_4_ADC_BST , 0x0000},
91 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
92 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
93 {RT5677_STO4_ADC_MIXER , 0xd4c0},
94 {RT5677_STO3_ADC_MIXER , 0xd4c0},
95 {RT5677_STO2_ADC_MIXER , 0xd4c0},
96 {RT5677_STO1_ADC_MIXER , 0xd4c0},
97 {RT5677_MONO_ADC_MIXER , 0xd4d1},
98 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
99 {RT5677_STO1_DAC_MIXER , 0xaaaa},
100 {RT5677_MONO_DAC_MIXER , 0xaaaa},
101 {RT5677_DD1_MIXER , 0xaaaa},
102 {RT5677_DD2_MIXER , 0xaaaa},
103 {RT5677_IF3_DATA , 0x0000},
104 {RT5677_IF4_DATA , 0x0000},
105 {RT5677_PDM_OUT_CTRL , 0x8888},
106 {RT5677_PDM_DATA_CTRL1 , 0x0000},
107 {RT5677_PDM_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
110 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
113 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
114 {RT5677_TDM1_CTRL1 , 0x0300},
115 {RT5677_TDM1_CTRL2 , 0x0000},
116 {RT5677_TDM1_CTRL3 , 0x4000},
117 {RT5677_TDM1_CTRL4 , 0x0123},
118 {RT5677_TDM1_CTRL5 , 0x4567},
119 {RT5677_TDM2_CTRL1 , 0x0300},
120 {RT5677_TDM2_CTRL2 , 0x0000},
121 {RT5677_TDM2_CTRL3 , 0x4000},
122 {RT5677_TDM2_CTRL4 , 0x0123},
123 {RT5677_TDM2_CTRL5 , 0x4567},
124 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
125 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
132 {RT5677_DMIC_CTRL1 , 0x1505},
133 {RT5677_DMIC_CTRL2 , 0x0055},
134 {RT5677_HAP_GENE_CTRL1 , 0x0111},
135 {RT5677_HAP_GENE_CTRL2 , 0x0064},
136 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
137 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
138 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
139 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
140 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
141 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
142 {RT5677_HAP_GENE_CTRL9 , 0xf000},
143 {RT5677_HAP_GENE_CTRL10 , 0x0000},
144 {RT5677_PWR_DIG1 , 0x0000},
145 {RT5677_PWR_DIG2 , 0x0000},
146 {RT5677_PWR_ANLG1 , 0x0055},
147 {RT5677_PWR_ANLG2 , 0x0000},
148 {RT5677_PWR_DSP1 , 0x0001},
149 {RT5677_PWR_DSP_ST , 0x0000},
150 {RT5677_PWR_DSP2 , 0x0000},
151 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
152 {RT5677_PRIV_INDEX , 0x0000},
153 {RT5677_PRIV_DATA , 0x0000},
154 {RT5677_I2S4_SDP , 0x8000},
155 {RT5677_I2S1_SDP , 0x8000},
156 {RT5677_I2S2_SDP , 0x8000},
157 {RT5677_I2S3_SDP , 0x8000},
158 {RT5677_CLK_TREE_CTRL1 , 0x1111},
159 {RT5677_CLK_TREE_CTRL2 , 0x1111},
160 {RT5677_CLK_TREE_CTRL3 , 0x0000},
161 {RT5677_PLL1_CTRL1 , 0x0000},
162 {RT5677_PLL1_CTRL2 , 0x0000},
163 {RT5677_PLL2_CTRL1 , 0x0c60},
164 {RT5677_PLL2_CTRL2 , 0x2000},
165 {RT5677_GLB_CLK1 , 0x0000},
166 {RT5677_GLB_CLK2 , 0x0000},
167 {RT5677_ASRC_1 , 0x0000},
168 {RT5677_ASRC_2 , 0x0000},
169 {RT5677_ASRC_3 , 0x0000},
170 {RT5677_ASRC_4 , 0x0000},
171 {RT5677_ASRC_5 , 0x0000},
172 {RT5677_ASRC_6 , 0x0000},
173 {RT5677_ASRC_7 , 0x0000},
174 {RT5677_ASRC_8 , 0x0000},
175 {RT5677_ASRC_9 , 0x0000},
176 {RT5677_ASRC_10 , 0x0000},
177 {RT5677_ASRC_11 , 0x0000},
86ae04b1 178 {RT5677_ASRC_12 , 0x0018},
0e826e86
OC		 179 {RT5677_ASRC_13 , 0x0000},
180 {RT5677_ASRC_14 , 0x0000},
181 {RT5677_ASRC_15 , 0x0000},
182 {RT5677_ASRC_16 , 0x0000},
183 {RT5677_ASRC_17 , 0x0000},
184 {RT5677_ASRC_18 , 0x0000},
185 {RT5677_ASRC_19 , 0x0000},
186 {RT5677_ASRC_20 , 0x0000},
187 {RT5677_ASRC_21 , 0x000c},
188 {RT5677_ASRC_22 , 0x0000},
189 {RT5677_ASRC_23 , 0x0000},
190 {RT5677_VAD_CTRL1 , 0x2184},
191 {RT5677_VAD_CTRL2 , 0x010a},
192 {RT5677_VAD_CTRL3 , 0x0aea},
193 {RT5677_VAD_CTRL4 , 0x000c},
194 {RT5677_VAD_CTRL5 , 0x0000},
195 {RT5677_DSP_INB_CTRL1 , 0x0000},
196 {RT5677_DSP_INB_CTRL2 , 0x0000},
197 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
198 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
201 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
202 {RT5677_ADC_EQ_CTRL1 , 0x6000},
203 {RT5677_ADC_EQ_CTRL2 , 0x0000},
204 {RT5677_EQ_CTRL1 , 0xc000},
205 {RT5677_EQ_CTRL2 , 0x0000},
206 {RT5677_EQ_CTRL3 , 0x0000},
207 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
208 {RT5677_JD_CTRL1 , 0x0000},
209 {RT5677_JD_CTRL2 , 0x0000},
210 {RT5677_JD_CTRL3 , 0x0000},
211 {RT5677_IRQ_CTRL1 , 0x0000},
212 {RT5677_IRQ_CTRL2 , 0x0000},
213 {RT5677_GPIO_ST , 0x0000},
214 {RT5677_GPIO_CTRL1 , 0x0000},
215 {RT5677_GPIO_CTRL2 , 0x0000},
216 {RT5677_GPIO_CTRL3 , 0x0000},
217 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
218 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
219 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
220 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
221 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
222 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
224 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
225 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
226 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
227 {RT5677_MB_DRC_CTRL1 , 0x0f20},
228 {RT5677_DRC1_CTRL1 , 0x001f},
229 {RT5677_DRC1_CTRL2 , 0x020c},
230 {RT5677_DRC1_CTRL3 , 0x1f00},
231 {RT5677_DRC1_CTRL4 , 0x0000},
232 {RT5677_DRC1_CTRL5 , 0x0000},
233 {RT5677_DRC1_CTRL6 , 0x0029},
234 {RT5677_DRC2_CTRL1 , 0x001f},
235 {RT5677_DRC2_CTRL2 , 0x020c},
236 {RT5677_DRC2_CTRL3 , 0x1f00},
237 {RT5677_DRC2_CTRL4 , 0x0000},
238 {RT5677_DRC2_CTRL5 , 0x0000},
239 {RT5677_DRC2_CTRL6 , 0x0029},
240 {RT5677_DRC1_HL_CTRL1 , 0x8000},
241 {RT5677_DRC1_HL_CTRL2 , 0x0200},
242 {RT5677_DRC2_HL_CTRL1 , 0x8000},
243 {RT5677_DRC2_HL_CTRL2 , 0x0200},
244 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
245 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
246 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
247 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
248 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
249 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
250 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
251 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
252 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
253 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
254 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
255 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
256 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
257 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
258 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
259 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
260 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
261 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
262 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
263 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
264 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
265 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
266 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
267 {RT5677_DIG_MISC , 0x0000},
268 {RT5677_GEN_CTRL1 , 0x0000},
269 {RT5677_GEN_CTRL2 , 0x0000},
270 {RT5677_VENDOR_ID , 0x0000},
271 {RT5677_VENDOR_ID1 , 0x10ec},
272 {RT5677_VENDOR_ID2 , 0x6327},
273};
274
275static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
276{
277 int i;
278
279 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
280 if (reg >= rt5677_ranges[i].range_min &&
281 reg <= rt5677_ranges[i].range_max) {
282 return true;
283 }
284 }
285
286 switch (reg) {
287 case RT5677_RESET:
288 case RT5677_SLIMBUS_PARAM:
289 case RT5677_PDM_DATA_CTRL1:
290 case RT5677_PDM_DATA_CTRL2:
291 case RT5677_PDM1_DATA_CTRL4:
292 case RT5677_PDM2_DATA_CTRL4:
293 case RT5677_I2C_MASTER_CTRL1:
294 case RT5677_I2C_MASTER_CTRL7:
295 case RT5677_I2C_MASTER_CTRL8:
296 case RT5677_HAP_GENE_CTRL2:
297 case RT5677_PWR_DSP_ST:
298 case RT5677_PRIV_DATA:
0e826e86
OC		 299 case RT5677_ASRC_22:
300 case RT5677_ASRC_23:
301 case RT5677_VAD_CTRL5:
302 case RT5677_ADC_EQ_CTRL1:
303 case RT5677_EQ_CTRL1:
304 case RT5677_IRQ_CTRL1:
305 case RT5677_IRQ_CTRL2:
306 case RT5677_GPIO_ST:
307 case RT5677_DSP_INB1_SRC_CTRL4:
308 case RT5677_DSP_INB2_SRC_CTRL4:
309 case RT5677_DSP_INB3_SRC_CTRL4:
310 case RT5677_DSP_OUTB1_SRC_CTRL4:
311 case RT5677_DSP_OUTB2_SRC_CTRL4:
312 case RT5677_VENDOR_ID:
313 case RT5677_VENDOR_ID1:
314 case RT5677_VENDOR_ID2:
315 return true;
316 default:
317 return false;
318 }
319}
320
321static bool rt5677_readable_register(struct device *dev, unsigned int reg)
322{
323 int i;
324
325 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
326 if (reg >= rt5677_ranges[i].range_min &&
327 reg <= rt5677_ranges[i].range_max) {
328 return true;
329 }
330 }
331
332 switch (reg) {
333 case RT5677_RESET:
334 case RT5677_LOUT1:
335 case RT5677_IN1:
336 case RT5677_MICBIAS:
337 case RT5677_SLIMBUS_PARAM:
338 case RT5677_SLIMBUS_RX:
339 case RT5677_SLIMBUS_CTRL:
340 case RT5677_SIDETONE_CTRL:
341 case RT5677_ANA_DAC1_2_3_SRC:
342 case RT5677_IF_DSP_DAC3_4_MIXER:
343 case RT5677_DAC4_DIG_VOL:
344 case RT5677_DAC3_DIG_VOL:
345 case RT5677_DAC1_DIG_VOL:
346 case RT5677_DAC2_DIG_VOL:
347 case RT5677_IF_DSP_DAC2_MIXER:
348 case RT5677_STO1_ADC_DIG_VOL:
349 case RT5677_MONO_ADC_DIG_VOL:
350 case RT5677_STO1_2_ADC_BST:
351 case RT5677_STO2_ADC_DIG_VOL:
352 case RT5677_ADC_BST_CTRL2:
353 case RT5677_STO3_4_ADC_BST:
354 case RT5677_STO3_ADC_DIG_VOL:
355 case RT5677_STO4_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_MIXER:
357 case RT5677_STO3_ADC_MIXER:
358 case RT5677_STO2_ADC_MIXER:
359 case RT5677_STO1_ADC_MIXER:
360 case RT5677_MONO_ADC_MIXER:
361 case RT5677_ADC_IF_DSP_DAC1_MIXER:
362 case RT5677_STO1_DAC_MIXER:
363 case RT5677_MONO_DAC_MIXER:
364 case RT5677_DD1_MIXER:
365 case RT5677_DD2_MIXER:
366 case RT5677_IF3_DATA:
367 case RT5677_IF4_DATA:
368 case RT5677_PDM_OUT_CTRL:
369 case RT5677_PDM_DATA_CTRL1:
370 case RT5677_PDM_DATA_CTRL2:
371 case RT5677_PDM1_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL3:
373 case RT5677_PDM1_DATA_CTRL4:
374 case RT5677_PDM2_DATA_CTRL2:
375 case RT5677_PDM2_DATA_CTRL3:
376 case RT5677_PDM2_DATA_CTRL4:
377 case RT5677_TDM1_CTRL1:
378 case RT5677_TDM1_CTRL2:
379 case RT5677_TDM1_CTRL3:
380 case RT5677_TDM1_CTRL4:
381 case RT5677_TDM1_CTRL5:
382 case RT5677_TDM2_CTRL1:
383 case RT5677_TDM2_CTRL2:
384 case RT5677_TDM2_CTRL3:
385 case RT5677_TDM2_CTRL4:
386 case RT5677_TDM2_CTRL5:
387 case RT5677_I2C_MASTER_CTRL1:
388 case RT5677_I2C_MASTER_CTRL2:
389 case RT5677_I2C_MASTER_CTRL3:
390 case RT5677_I2C_MASTER_CTRL4:
391 case RT5677_I2C_MASTER_CTRL5:
392 case RT5677_I2C_MASTER_CTRL6:
393 case RT5677_I2C_MASTER_CTRL7:
394 case RT5677_I2C_MASTER_CTRL8:
395 case RT5677_DMIC_CTRL1:
396 case RT5677_DMIC_CTRL2:
397 case RT5677_HAP_GENE_CTRL1:
398 case RT5677_HAP_GENE_CTRL2:
399 case RT5677_HAP_GENE_CTRL3:
400 case RT5677_HAP_GENE_CTRL4:
401 case RT5677_HAP_GENE_CTRL5:
402 case RT5677_HAP_GENE_CTRL6:
403 case RT5677_HAP_GENE_CTRL7:
404 case RT5677_HAP_GENE_CTRL8:
405 case RT5677_HAP_GENE_CTRL9:
406 case RT5677_HAP_GENE_CTRL10:
407 case RT5677_PWR_DIG1:
408 case RT5677_PWR_DIG2:
409 case RT5677_PWR_ANLG1:
410 case RT5677_PWR_ANLG2:
411 case RT5677_PWR_DSP1:
412 case RT5677_PWR_DSP_ST:
413 case RT5677_PWR_DSP2:
414 case RT5677_ADC_DAC_HPF_CTRL1:
415 case RT5677_PRIV_INDEX:
416 case RT5677_PRIV_DATA:
417 case RT5677_I2S4_SDP:
418 case RT5677_I2S1_SDP:
419 case RT5677_I2S2_SDP:
420 case RT5677_I2S3_SDP:
421 case RT5677_CLK_TREE_CTRL1:
422 case RT5677_CLK_TREE_CTRL2:
423 case RT5677_CLK_TREE_CTRL3:
424 case RT5677_PLL1_CTRL1:
425 case RT5677_PLL1_CTRL2:
426 case RT5677_PLL2_CTRL1:
427 case RT5677_PLL2_CTRL2:
428 case RT5677_GLB_CLK1:
429 case RT5677_GLB_CLK2:
430 case RT5677_ASRC_1:
431 case RT5677_ASRC_2:
432 case RT5677_ASRC_3:
433 case RT5677_ASRC_4:
434 case RT5677_ASRC_5:
435 case RT5677_ASRC_6:
436 case RT5677_ASRC_7:
437 case RT5677_ASRC_8:
438 case RT5677_ASRC_9:
439 case RT5677_ASRC_10:
440 case RT5677_ASRC_11:
441 case RT5677_ASRC_12:
442 case RT5677_ASRC_13:
443 case RT5677_ASRC_14:
444 case RT5677_ASRC_15:
445 case RT5677_ASRC_16:
446 case RT5677_ASRC_17:
447 case RT5677_ASRC_18:
448 case RT5677_ASRC_19:
449 case RT5677_ASRC_20:
450 case RT5677_ASRC_21:
451 case RT5677_ASRC_22:
452 case RT5677_ASRC_23:
453 case RT5677_VAD_CTRL1:
454 case RT5677_VAD_CTRL2:
455 case RT5677_VAD_CTRL3:
456 case RT5677_VAD_CTRL4:
457 case RT5677_VAD_CTRL5:
458 case RT5677_DSP_INB_CTRL1:
459 case RT5677_DSP_INB_CTRL2:
460 case RT5677_DSP_IN_OUTB_CTRL:
461 case RT5677_DSP_OUTB0_1_DIG_VOL:
462 case RT5677_DSP_OUTB2_3_DIG_VOL:
463 case RT5677_DSP_OUTB4_5_DIG_VOL:
464 case RT5677_DSP_OUTB6_7_DIG_VOL:
465 case RT5677_ADC_EQ_CTRL1:
466 case RT5677_ADC_EQ_CTRL2:
467 case RT5677_EQ_CTRL1:
468 case RT5677_EQ_CTRL2:
469 case RT5677_EQ_CTRL3:
470 case RT5677_SOFT_VOL_ZERO_CROSS1:
471 case RT5677_JD_CTRL1:
472 case RT5677_JD_CTRL2:
473 case RT5677_JD_CTRL3:
474 case RT5677_IRQ_CTRL1:
475 case RT5677_IRQ_CTRL2:
476 case RT5677_GPIO_ST:
477 case RT5677_GPIO_CTRL1:
478 case RT5677_GPIO_CTRL2:
479 case RT5677_GPIO_CTRL3:
480 case RT5677_STO1_ADC_HI_FILTER1:
481 case RT5677_STO1_ADC_HI_FILTER2:
482 case RT5677_MONO_ADC_HI_FILTER1:
483 case RT5677_MONO_ADC_HI_FILTER2:
484 case RT5677_STO2_ADC_HI_FILTER1:
485 case RT5677_STO2_ADC_HI_FILTER2:
486 case RT5677_STO3_ADC_HI_FILTER1:
487 case RT5677_STO3_ADC_HI_FILTER2:
488 case RT5677_STO4_ADC_HI_FILTER1:
489 case RT5677_STO4_ADC_HI_FILTER2:
490 case RT5677_MB_DRC_CTRL1:
491 case RT5677_DRC1_CTRL1:
492 case RT5677_DRC1_CTRL2:
493 case RT5677_DRC1_CTRL3:
494 case RT5677_DRC1_CTRL4:
495 case RT5677_DRC1_CTRL5:
496 case RT5677_DRC1_CTRL6:
497 case RT5677_DRC2_CTRL1:
498 case RT5677_DRC2_CTRL2:
499 case RT5677_DRC2_CTRL3:
500 case RT5677_DRC2_CTRL4:
501 case RT5677_DRC2_CTRL5:
502 case RT5677_DRC2_CTRL6:
503 case RT5677_DRC1_HL_CTRL1:
504 case RT5677_DRC1_HL_CTRL2:
505 case RT5677_DRC2_HL_CTRL1:
506 case RT5677_DRC2_HL_CTRL2:
507 case RT5677_DSP_INB1_SRC_CTRL1:
508 case RT5677_DSP_INB1_SRC_CTRL2:
509 case RT5677_DSP_INB1_SRC_CTRL3:
510 case RT5677_DSP_INB1_SRC_CTRL4:
511 case RT5677_DSP_INB2_SRC_CTRL1:
512 case RT5677_DSP_INB2_SRC_CTRL2:
513 case RT5677_DSP_INB2_SRC_CTRL3:
514 case RT5677_DSP_INB2_SRC_CTRL4:
515 case RT5677_DSP_INB3_SRC_CTRL1:
516 case RT5677_DSP_INB3_SRC_CTRL2:
517 case RT5677_DSP_INB3_SRC_CTRL3:
518 case RT5677_DSP_INB3_SRC_CTRL4:
519 case RT5677_DSP_OUTB1_SRC_CTRL1:
520 case RT5677_DSP_OUTB1_SRC_CTRL2:
521 case RT5677_DSP_OUTB1_SRC_CTRL3:
522 case RT5677_DSP_OUTB1_SRC_CTRL4:
523 case RT5677_DSP_OUTB2_SRC_CTRL1:
524 case RT5677_DSP_OUTB2_SRC_CTRL2:
525 case RT5677_DSP_OUTB2_SRC_CTRL3:
526 case RT5677_DSP_OUTB2_SRC_CTRL4:
527 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
528 case RT5677_DSP_OUTB_45_MIXER_CTRL:
529 case RT5677_DSP_OUTB_67_MIXER_CTRL:
530 case RT5677_DIG_MISC:
531 case RT5677_GEN_CTRL1:
532 case RT5677_GEN_CTRL2:
533 case RT5677_VENDOR_ID:
534 case RT5677_VENDOR_ID1:
535 case RT5677_VENDOR_ID2:
536 return true;
537 default:
538 return false;
539 }
540}
541
af48f1d0
OC		 542/**
543 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
19ba484d 544 * @rt5677: Private Data.
af48f1d0
OC		 545 * @addr: Address index.
546 * @value: Address data.
dc22a409 547 * @opcode: opcode value
af48f1d0
OC		 548 *
549 * Returns 0 for success or negative error code.
550 */
19ba484d 551static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
af48f1d0
OC		 552 unsigned int addr, unsigned int value, unsigned int opcode)
553{
79223bf1 554 struct snd_soc_component *component = rt5677->component;
af48f1d0
OC		 555 int ret;
556
557 mutex_lock(&rt5677->dsp_cmd_lock);
558
19ba484d
OC		 559 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
560 addr >> 16);
af48f1d0 561 if (ret < 0) {
79223bf1 562 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
af48f1d0
OC		 563 goto err;
564 }
565
19ba484d 566 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 567 addr & 0xffff);
568 if (ret < 0) {
79223bf1 569 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
af48f1d0
OC		 570 goto err;
571 }
572
19ba484d 573 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
af48f1d0
OC		 574 value >> 16);
575 if (ret < 0) {
79223bf1 576 dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
af48f1d0
OC		 577 goto err;
578 }
579
19ba484d 580 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
af48f1d0
OC		 581 value & 0xffff);
582 if (ret < 0) {
79223bf1 583 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
af48f1d0
OC		 584 goto err;
585 }
586
19ba484d
OC		 587 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
588 opcode);
af48f1d0 589 if (ret < 0) {
79223bf1 590 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
af48f1d0
OC		 591 goto err;
592 }
593
594err:
595 mutex_unlock(&rt5677->dsp_cmd_lock);
596
597 return ret;
598}
599
600/**
601 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
dc22a409 602 * @rt5677: Private Data.
af48f1d0
OC		 603 * @addr: Address index.
604 * @value: Address data.
605 *
19ba484d 606 *
af48f1d0
OC		 607 * Returns 0 for success or negative error code.
608 */
609static int rt5677_dsp_mode_i2c_read_addr(
19ba484d 610 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
af48f1d0 611{
79223bf1 612 struct snd_soc_component *component = rt5677->component;
af48f1d0
OC		 613 int ret;
614 unsigned int msb, lsb;
615
616 mutex_lock(&rt5677->dsp_cmd_lock);
617
19ba484d
OC		 618 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
619 addr >> 16);
af48f1d0 620 if (ret < 0) {
79223bf1 621 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
af48f1d0
OC		 622 goto err;
623 }
624
19ba484d 625 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 626 addr & 0xffff);
627 if (ret < 0) {
79223bf1 628 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
af48f1d0
OC		 629 goto err;
630 }
631
19ba484d
OC		 632 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
633 0x0002);
af48f1d0 634 if (ret < 0) {
79223bf1 635 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
af48f1d0
OC		 636 goto err;
637 }
638
19ba484d
OC		 639 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
af48f1d0
OC		 641 *value = (msb << 16) | lsb;
642
643err:
644 mutex_unlock(&rt5677->dsp_cmd_lock);
645
646 return ret;
647}
648
649/**
650 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
dc22a409 651 * @rt5677: Private Data.
af48f1d0
OC		 652 * @reg: Register index.
653 * @value: Register data.
654 *
655 *
656 * Returns 0 for success or negative error code.
657 */
19ba484d 658static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
af48f1d0
OC		 659 unsigned int reg, unsigned int value)
660{
19ba484d 661 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
af48f1d0
OC		 662 value, 0x0001);
663}
664
665/**
666 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
dc22a409 667 * @rt5677: Private Data
af48f1d0 668 * @reg: Register index.
19ba484d 669 * @value: Register data.
af48f1d0
OC		 670 *
671 *
19ba484d 672 * Returns 0 for success or negative error code.
af48f1d0 673 */
19ba484d
OC		 674static int rt5677_dsp_mode_i2c_read(
675 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
af48f1d0 676{
19ba484d
OC		 677 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
678 value);
af48f1d0 679
19ba484d 680 *value &= 0xffff;
af48f1d0 681
19ba484d 682 return ret;
af48f1d0
OC		 683}
684
79223bf1 685static void rt5677_set_dsp_mode(struct snd_soc_component *component, bool on)
af48f1d0 686{
79223bf1 687 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
af48f1d0 688
19ba484d
OC		 689 if (on) {
690 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
691 rt5677->is_dsp_mode = true;
692 } else {
693 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
694 rt5677->is_dsp_mode = false;
af48f1d0 695 }
af48f1d0
OC		 696}
697
79223bf1 698static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on)
af48f1d0 699{
79223bf1 700 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
af48f1d0
OC		 701 static bool activity;
702 int ret;
703
4c121129
AB		 704 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
705 return -ENXIO;
706
af48f1d0
OC		 707 if (on && !activity) {
708 activity = true;
709
710 regcache_cache_only(rt5677->regmap, false);
711 regcache_cache_bypass(rt5677->regmap, true);
712
713 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
714 regmap_update_bits(rt5677->regmap,
715 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
716 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
717 RT5677_LDO1_SEL_MASK, 0x0);
718 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
719 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
ab1f7095
OC		 720 switch (rt5677->type) {
721 case RT5677:
722 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
723 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
724 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
725 RT5677_PLL2_PR_SRC_MASK |
726 RT5677_DSP_CLK_SRC_MASK,
727 RT5677_PLL2_PR_SRC_MCLK2 |
728 RT5677_DSP_CLK_SRC_BYPASS);
729 break;
730 case RT5676:
731 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
732 RT5677_DSP_CLK_SRC_MASK,
733 RT5677_DSP_CLK_SRC_BYPASS);
734 break;
735 default:
736 break;
737 }
af48f1d0 738 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
19ba484d 739 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
79223bf1 740 rt5677_set_dsp_mode(component, true);
af48f1d0
OC		 741
742 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
79223bf1 743 component->dev);
af48f1d0 744 if (ret == 0) {
7d4d443e 745 rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
af48f1d0
OC		 746 release_firmware(rt5677->fw1);
747 }
748
749 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
79223bf1 750 component->dev);
af48f1d0 751 if (ret == 0) {
7d4d443e 752 rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
af48f1d0
OC		 753 release_firmware(rt5677->fw2);
754 }
755
19ba484d 756 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
af48f1d0
OC		 757
758 regcache_cache_bypass(rt5677->regmap, false);
759 regcache_cache_only(rt5677->regmap, true);
760 } else if (!on && activity) {
761 activity = false;
762
763 regcache_cache_only(rt5677->regmap, false);
764 regcache_cache_bypass(rt5677->regmap, true);
765
19ba484d 766 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
79223bf1 767 rt5677_set_dsp_mode(component, false);
19ba484d 768 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
af48f1d0
OC		 769
770 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
771
772 regcache_cache_bypass(rt5677->regmap, false);
773 regcache_mark_dirty(rt5677->regmap);
774 regcache_sync(rt5677->regmap);
775 }
776
777 return 0;
778}
779
40e3262e 780static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
40e3262e 781static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
0e826e86 782static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
90bdbb46 783static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
0e826e86
OC		 784
785/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
53f28609 786static const DECLARE_TLV_DB_RANGE(bst_tlv,
0e826e86
OC		 787 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
788 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
789 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
790 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
791 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
792 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
53f28609
LPC		 793 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
794);
0e826e86 795
af48f1d0
OC		 796static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
797 struct snd_ctl_elem_value *ucontrol)
798{
6087fcab
FY		 799 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
800 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
af48f1d0
OC		 801
802 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
803
804 return 0;
805}
806
807static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
808 struct snd_ctl_elem_value *ucontrol)
809{
6087fcab
FY		 810 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
811 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
af48f1d0
OC		 812
813 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
814
79223bf1
KM		 815 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
816 rt5677_set_dsp_vad(component, rt5677->dsp_vad_en);
af48f1d0
OC		 817
818 return 0;
819}
820
0e826e86
OC		 821static const struct snd_kcontrol_new rt5677_snd_controls[] = {
822 /* OUTPUT Control */
823 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
824 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
825 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
826 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
827 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
828 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
829
830 /* DAC Digital Volume */
831 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
40e3262e 832 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 833 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
40e3262e 834 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 835 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
40e3262e 836 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 837 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
40e3262e 838 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86
OC		 839
840 /* IN1/IN2 Control */
841 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
842 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
843
844 /* ADC Digital Volume Control */
845 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
846 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
847 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
848 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
849 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
850 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
851 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
852 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
853 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
854 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855
856 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
40e3262e 857 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 858 adc_vol_tlv),
859 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
40e3262e 860 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 861 adc_vol_tlv),
862 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
40e3262e 863 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 864 adc_vol_tlv),
865 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
40e3262e 866 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 867 adc_vol_tlv),
868 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
40e3262e 869 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 870 adc_vol_tlv),
871
90bdbb46
OC		 872 /* Sidetone Control */
873 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
874 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
875
0e826e86 876 /* ADC Boost Volume Control */
80220f29 877 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 878 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
879 adc_bst_tlv),
80220f29 880 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 881 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
882 adc_bst_tlv),
80220f29 883 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 884 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
885 adc_bst_tlv),
80220f29 886 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 887 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
888 adc_bst_tlv),
80220f29 889 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
0e826e86
OC		 890 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
891 adc_bst_tlv),
af48f1d0
OC		 892
893 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
894 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
0e826e86
OC		 895};
896
897/**
898 * set_dmic_clk - Set parameter of dmic.
899 *
900 * @w: DAPM widget.
901 * @kcontrol: The kcontrol of this widget.
902 * @event: Event id.
903 *
904 * Choose dmic clock between 1MHz and 3MHz.
905 * It is better for clock to approximate 3MHz.
906 */
907static int set_dmic_clk(struct snd_soc_dapm_widget *w,
908 struct snd_kcontrol *kcontrol, int event)
909{
79223bf1
KM		 910 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
911 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
00a6d6e5 912 int idx, rate;
0e826e86 913
00a6d6e5
OC		 914 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
915 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
916 idx = rl6231_calc_dmic_clk(rate);
0e826e86 917 if (idx < 0)
79223bf1 918 dev_err(component->dev, "Failed to set DMIC clock\n");
0e826e86
OC		 919 else
920 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
921 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
922 return idx;
923}
924
925static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
926 struct snd_soc_dapm_widget *sink)
927{
79223bf1
KM		 928 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
929 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 930 unsigned int val;
931
932 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
933 val &= RT5677_SCLK_SRC_MASK;
934 if (val == RT5677_SCLK_SRC_PLL1)
935 return 1;
936 else
937 return 0;
938}
939
5a8c7c26
OC		 940static int is_using_asrc(struct snd_soc_dapm_widget *source,
941 struct snd_soc_dapm_widget *sink)
942{
79223bf1
KM		 943 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
944 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
5a8c7c26
OC		 945 unsigned int reg, shift, val;
946
947 if (source->reg == RT5677_ASRC_1) {
948 switch (source->shift) {
949 case 12:
950 reg = RT5677_ASRC_4;
951 shift = 0;
952 break;
953 case 13:
954 reg = RT5677_ASRC_4;
955 shift = 4;
956 break;
957 case 14:
958 reg = RT5677_ASRC_4;
959 shift = 8;
960 break;
961 case 15:
962 reg = RT5677_ASRC_4;
963 shift = 12;
964 break;
965 default:
966 return 0;
967 }
968 } else {
969 switch (source->shift) {
970 case 0:
971 reg = RT5677_ASRC_6;
972 shift = 8;
973 break;
974 case 1:
975 reg = RT5677_ASRC_6;
976 shift = 12;
977 break;
978 case 2:
979 reg = RT5677_ASRC_5;
980 shift = 0;
981 break;
982 case 3:
983 reg = RT5677_ASRC_5;
984 shift = 4;
985 break;
986 case 4:
987 reg = RT5677_ASRC_5;
988 shift = 8;
989 break;
990 case 5:
991 reg = RT5677_ASRC_5;
992 shift = 12;
993 break;
994 case 12:
995 reg = RT5677_ASRC_3;
996 shift = 0;
997 break;
998 case 13:
999 reg = RT5677_ASRC_3;
1000 shift = 4;
1001 break;
1002 case 14:
1003 reg = RT5677_ASRC_3;
1004 shift = 12;
1005 break;
1006 default:
1007 return 0;
1008 }
1009 }
1010
e4b7e6a8
OC		 1011 regmap_read(rt5677->regmap, reg, &val);
1012 val = (val >> shift) & 0xf;
1013
5a8c7c26
OC		 1014 switch (val) {
1015 case 1 ... 6:
1016 return 1;
1017 default:
1018 return 0;
1019 }
1020
1021}
1022
1023static int can_use_asrc(struct snd_soc_dapm_widget *source,
1024 struct snd_soc_dapm_widget *sink)
1025{
79223bf1
KM		 1026 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1027 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
5a8c7c26
OC		 1028
1029 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1030 return 1;
1031
1032 return 0;
1033}
1034
c36aa0a1
OC		 1035/**
1036 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
79223bf1 1037 * @component: SoC audio component device.
c36aa0a1
OC		 1038 * @filter_mask: mask of filters.
1039 * @clk_src: clock source
1040 *
1041 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1042 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1043 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1044 * ASRC function will track i2s clock and generate a corresponding system clock
1045 * for codec. This function provides an API to select the clock source for a
1046 * set of filters specified by the mask. And the codec driver will turn on ASRC
1047 * for these filters if ASRC is selected as their clock source.
1048 */
79223bf1 1049int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
c36aa0a1
OC		 1050 unsigned int filter_mask, unsigned int clk_src)
1051{
79223bf1 1052 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
c36aa0a1
OC		 1053 unsigned int asrc3_mask = 0, asrc3_value = 0;
1054 unsigned int asrc4_mask = 0, asrc4_value = 0;
1055 unsigned int asrc5_mask = 0, asrc5_value = 0;
1056 unsigned int asrc6_mask = 0, asrc6_value = 0;
1057 unsigned int asrc7_mask = 0, asrc7_value = 0;
16ab6e18 1058 unsigned int asrc8_mask = 0, asrc8_value = 0;
c36aa0a1
OC		 1059
1060 switch (clk_src) {
1061 case RT5677_CLK_SEL_SYS:
1062 case RT5677_CLK_SEL_I2S1_ASRC:
1063 case RT5677_CLK_SEL_I2S2_ASRC:
1064 case RT5677_CLK_SEL_I2S3_ASRC:
1065 case RT5677_CLK_SEL_I2S4_ASRC:
1066 case RT5677_CLK_SEL_I2S5_ASRC:
1067 case RT5677_CLK_SEL_I2S6_ASRC:
1068 case RT5677_CLK_SEL_SYS2:
1069 case RT5677_CLK_SEL_SYS3:
1070 case RT5677_CLK_SEL_SYS4:
1071 case RT5677_CLK_SEL_SYS5:
1072 case RT5677_CLK_SEL_SYS6:
1073 case RT5677_CLK_SEL_SYS7:
1074 break;
1075
1076 default:
1077 return -EINVAL;
1078 }
1079
1080 /* ASRC 3 */
1081 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1082 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1083 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1084 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1085 }
1086
1087 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1088 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1089 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1090 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1091 }
1092
1093 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1094 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1095 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1096 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1097 }
1098
1099 if (asrc3_mask)
1100 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1101 asrc3_value);
1102
1103 /* ASRC 4 */
1104 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1105 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1106 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1107 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1108 }
1109
1110 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1111 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1112 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1113 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1114 }
1115
1116 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1117 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1118 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1119 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1120 }
1121
1122 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1123 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1124 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1125 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1126 }
1127
1128 if (asrc4_mask)
1129 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1130 asrc4_value);
1131
1132 /* ASRC 5 */
1133 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1134 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1135 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1136 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1137 }
1138
1139 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1140 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1141 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1142 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1143 }
1144
1145 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1146 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1147 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1148 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1149 }
1150
1151 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1152 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1153 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1154 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1155 }
1156
1157 if (asrc5_mask)
1158 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1159 asrc5_value);
1160
1161 /* ASRC 6 */
1162 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1163 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1164 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1165 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1166 }
1167
1168 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1169 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1170 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1171 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1172 }
1173
1174 if (asrc6_mask)
1175 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1176 asrc6_value);
1177
1178 /* ASRC 7 */
1179 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1180 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1181 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1182 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1183 }
1184
1185 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1186 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1187 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1188 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1189 }
1190
1191 if (asrc7_mask)
1192 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1193 asrc7_value);
1194
16ab6e18
BL		 1195 /* ASRC 8 */
1196 if (filter_mask & RT5677_I2S1_SOURCE) {
1197 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1198 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1199 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1200 }
1201
1202 if (filter_mask & RT5677_I2S2_SOURCE) {
1203 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1204 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1205 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1206 }
1207
1208 if (filter_mask & RT5677_I2S3_SOURCE) {
1209 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1210 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1211 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1212 }
1213
1214 if (filter_mask & RT5677_I2S4_SOURCE) {
1215 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1216 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1217 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1218 }
1219
1220 if (asrc8_mask)
1221 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1222 asrc8_value);
1223
c36aa0a1
OC		 1224 return 0;
1225}
1226EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1227
5220f7fb
OC		 1228static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1229 struct snd_soc_dapm_widget *sink)
1230{
79223bf1
KM		 1231 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1232 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
5220f7fb
OC		 1233 unsigned int asrc_setting;
1234
1235 switch (source->shift) {
1236 case 11:
1237 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1238 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1239 RT5677_AD_STO1_CLK_SEL_SFT;
5220f7fb
OC		 1240 break;
1241
1242 case 10:
1243 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1244 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1245 RT5677_AD_STO2_CLK_SEL_SFT;
5220f7fb
OC		 1246 break;
1247
1248 case 9:
1249 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1250 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1251 RT5677_AD_STO3_CLK_SEL_SFT;
5220f7fb
OC		 1252 break;
1253
1254 case 8:
1255 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1256 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1257 RT5677_AD_STO4_CLK_SEL_SFT;
5220f7fb
OC		 1258 break;
1259
1260 case 7:
1261 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1262 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1263 RT5677_AD_MONOL_CLK_SEL_SFT;
5220f7fb
OC		 1264 break;
1265
1266 case 6:
1267 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1268 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1269 RT5677_AD_MONOR_CLK_SEL_SFT;
5220f7fb
OC		 1270 break;
1271
1272 default:
2dfadff6 1273 return 0;
5220f7fb
OC		 1274 }
1275
2dfadff6
AL		 1276 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1277 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1278 return 1;
1279
5220f7fb
OC		 1280 return 0;
1281}
1282
0e826e86
OC		 1283/* Digital Mixer */
1284static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1285 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1286 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1287 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1288 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1289};
1290
1291static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1292 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1293 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1294 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1295 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1296};
1297
1298static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1299 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1300 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1301 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1302 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1303};
1304
1305static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1306 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1307 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1308 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1309 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1310};
1311
1312static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1313 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1314 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1315 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1316 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1317};
1318
1319static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1320 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1321 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1322 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1323 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1324};
1325
1326static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1327 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1328 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1329 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1330 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1331};
1332
1333static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1334 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1335 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1336 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1337 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1338};
1339
1340static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1341 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1342 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1343 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1344 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1345};
1346
1347static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1348 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1349 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1350 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1351 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1352};
1353
1354static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1355 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1356 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1357 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1358 RT5677_M_DAC1_L_SFT, 1, 1),
1359};
1360
1361static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1362 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1363 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1364 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1365 RT5677_M_DAC1_R_SFT, 1, 1),
1366};
1367
1368static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
c22d7666 1369 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1370 RT5677_M_ST_DAC1_L_SFT, 1, 1),
c22d7666 1371 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1372 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
c22d7666 1373 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1374 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
c22d7666 1375 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
0e826e86
OC		 1376 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1377};
1378
1379static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
c22d7666 1380 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1381 RT5677_M_ST_DAC1_R_SFT, 1, 1),
c22d7666 1382 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1383 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
c22d7666 1384 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1385 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
c22d7666 1386 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
0e826e86
OC		 1387 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1388};
1389
1390static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
c22d7666 1391 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1392 RT5677_M_ST_DAC2_L_SFT, 1, 1),
c22d7666 1393 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1394 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
c22d7666 1395 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1396 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
c22d7666 1397 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
0e826e86
OC		 1398 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1399};
1400
1401static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
c22d7666 1402 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1403 RT5677_M_ST_DAC2_R_SFT, 1, 1),
c22d7666 1404 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1405 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
c22d7666 1406 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1407 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
c22d7666 1408 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
0e826e86
OC		 1409 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1410};
1411
1412static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
c22d7666 1413 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
0e826e86 1414 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
c22d7666 1415 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
0e826e86 1416 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
c22d7666 1417 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
0e826e86 1418 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
c22d7666 1419 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
0e826e86
OC		 1420 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1421};
1422
1423static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
c22d7666 1424 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
0e826e86 1425 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
c22d7666 1426 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
0e826e86 1427 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
c22d7666 1428 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
0e826e86 1429 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
c22d7666 1430 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
0e826e86
OC		 1431 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1432};
1433
1434static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
c22d7666 1435 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
0e826e86 1436 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
c22d7666 1437 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
0e826e86 1438 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
c22d7666 1439 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
0e826e86 1440 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
c22d7666 1441 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
0e826e86
OC		 1442 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1443};
1444
1445static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
c22d7666 1446 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
0e826e86 1447 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
c22d7666 1448 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
0e826e86 1449 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
c22d7666 1450 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
0e826e86 1451 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
c22d7666 1452 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
0e826e86
OC		 1453 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1454};
1455
1456static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1457 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1458 RT5677_DSP_IB_01_H_SFT, 1, 1),
1459 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1460 RT5677_DSP_IB_23_H_SFT, 1, 1),
1461 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1462 RT5677_DSP_IB_45_H_SFT, 1, 1),
1463 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1464 RT5677_DSP_IB_6_H_SFT, 1, 1),
1465 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1466 RT5677_DSP_IB_7_H_SFT, 1, 1),
1467 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1468 RT5677_DSP_IB_8_H_SFT, 1, 1),
1469 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1470 RT5677_DSP_IB_9_H_SFT, 1, 1),
1471};
1472
1473static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1474 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1475 RT5677_DSP_IB_01_L_SFT, 1, 1),
1476 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1477 RT5677_DSP_IB_23_L_SFT, 1, 1),
1478 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1479 RT5677_DSP_IB_45_L_SFT, 1, 1),
1480 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1481 RT5677_DSP_IB_6_L_SFT, 1, 1),
1482 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1483 RT5677_DSP_IB_7_L_SFT, 1, 1),
1484 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1485 RT5677_DSP_IB_8_L_SFT, 1, 1),
1486 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1487 RT5677_DSP_IB_9_L_SFT, 1, 1),
1488};
1489
1490static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1491 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1492 RT5677_DSP_IB_01_H_SFT, 1, 1),
1493 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1494 RT5677_DSP_IB_23_H_SFT, 1, 1),
1495 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1496 RT5677_DSP_IB_45_H_SFT, 1, 1),
1497 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1498 RT5677_DSP_IB_6_H_SFT, 1, 1),
1499 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1500 RT5677_DSP_IB_7_H_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1502 RT5677_DSP_IB_8_H_SFT, 1, 1),
1503 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1504 RT5677_DSP_IB_9_H_SFT, 1, 1),
1505};
1506
1507static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1508 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1509 RT5677_DSP_IB_01_L_SFT, 1, 1),
1510 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1511 RT5677_DSP_IB_23_L_SFT, 1, 1),
1512 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1513 RT5677_DSP_IB_45_L_SFT, 1, 1),
1514 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1515 RT5677_DSP_IB_6_L_SFT, 1, 1),
1516 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1517 RT5677_DSP_IB_7_L_SFT, 1, 1),
1518 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1519 RT5677_DSP_IB_8_L_SFT, 1, 1),
1520 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1521 RT5677_DSP_IB_9_L_SFT, 1, 1),
1522};
1523
1524static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1525 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1526 RT5677_DSP_IB_01_H_SFT, 1, 1),
1527 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1528 RT5677_DSP_IB_23_H_SFT, 1, 1),
1529 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1530 RT5677_DSP_IB_45_H_SFT, 1, 1),
1531 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1532 RT5677_DSP_IB_6_H_SFT, 1, 1),
1533 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1534 RT5677_DSP_IB_7_H_SFT, 1, 1),
1535 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1536 RT5677_DSP_IB_8_H_SFT, 1, 1),
1537 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1538 RT5677_DSP_IB_9_H_SFT, 1, 1),
1539};
1540
1541static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1542 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1543 RT5677_DSP_IB_01_L_SFT, 1, 1),
1544 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1545 RT5677_DSP_IB_23_L_SFT, 1, 1),
1546 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1547 RT5677_DSP_IB_45_L_SFT, 1, 1),
1548 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1549 RT5677_DSP_IB_6_L_SFT, 1, 1),
1550 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1551 RT5677_DSP_IB_7_L_SFT, 1, 1),
1552 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1553 RT5677_DSP_IB_8_L_SFT, 1, 1),
1554 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1555 RT5677_DSP_IB_9_L_SFT, 1, 1),
1556};
1557
1558
1559/* Mux */
1b7fd76a 1560/* DAC1 L/R Source */ /* MX-29 [10:8] */
0e826e86
OC		 1561static const char * const rt5677_dac1_src[] = {
1562 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1563 "OB 01"
1564};
1565
1566static SOC_ENUM_SINGLE_DECL(
1567 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1568 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1569
1570static const struct snd_kcontrol_new rt5677_dac1_mux =
1b7fd76a 1571 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
0e826e86 1572
1b7fd76a 1573/* ADDA1 L/R Source */ /* MX-29 [1:0] */
0e826e86
OC		 1574static const char * const rt5677_adda1_src[] = {
1575 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1576};
1577
1578static SOC_ENUM_SINGLE_DECL(
1579 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1580 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1581
1582static const struct snd_kcontrol_new rt5677_adda1_mux =
1b7fd76a 1583 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
0e826e86
OC		 1584
1585
1b7fd76a 1586/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
0e826e86
OC		 1587static const char * const rt5677_dac2l_src[] = {
1588 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1589 "OB 2",
1590};
1591
1592static SOC_ENUM_SINGLE_DECL(
1593 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1594 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1595
1596static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1b7fd76a 1597 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
0e826e86
OC		 1598
1599static const char * const rt5677_dac2r_src[] = {
1600 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1601 "OB 3", "Haptic Generator", "VAD ADC"
1602};
1603
1604static SOC_ENUM_SINGLE_DECL(
1605 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1606 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1607
1608static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1b7fd76a 1609 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
0e826e86 1610
1b7fd76a 1611/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
0e826e86
OC		 1612static const char * const rt5677_dac3l_src[] = {
1613 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1614 "SLB DAC 4", "OB 4"
1615};
1616
1617static SOC_ENUM_SINGLE_DECL(
1618 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1619 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1620
1621static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1b7fd76a 1622 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
0e826e86
OC		 1623
1624static const char * const rt5677_dac3r_src[] = {
1625 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1626 "SLB DAC 5", "OB 5"
1627};
1628
1629static SOC_ENUM_SINGLE_DECL(
1630 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1631 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1632
1633static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1b7fd76a 1634 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
0e826e86 1635
1b7fd76a 1636/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
0e826e86
OC		 1637static const char * const rt5677_dac4l_src[] = {
1638 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1639 "SLB DAC 6", "OB 6"
1640};
1641
1642static SOC_ENUM_SINGLE_DECL(
1643 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1644 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1645
1646static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1b7fd76a 1647 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
0e826e86
OC		 1648
1649static const char * const rt5677_dac4r_src[] = {
1650 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1651 "SLB DAC 7", "OB 7"
1652};
1653
1654static SOC_ENUM_SINGLE_DECL(
1655 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1656 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1657
1658static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1b7fd76a 1659 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
0e826e86
OC		 1660
1661/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1662static const char * const rt5677_iob_bypass_src[] = {
1663 "Bypass", "Pass SRC"
1664};
1665
1666static SOC_ENUM_SINGLE_DECL(
1667 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1668 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1669
1670static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1b7fd76a 1671 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
0e826e86
OC		 1672
1673static SOC_ENUM_SINGLE_DECL(
1674 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1675 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1676
1677static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1b7fd76a 1678 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
0e826e86
OC		 1679
1680static SOC_ENUM_SINGLE_DECL(
1681 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1682 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1683
1684static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1b7fd76a 1685 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
0e826e86
OC		 1686
1687static SOC_ENUM_SINGLE_DECL(
1688 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1689 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1690
1691static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1b7fd76a 1692 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
0e826e86
OC		 1693
1694static SOC_ENUM_SINGLE_DECL(
1695 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1696 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1697
1698static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1b7fd76a 1699 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
0e826e86 1700
d65fd3a4 1701/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
0e826e86
OC		 1702static const char * const rt5677_stereo_adc2_src[] = {
1703 "DD MIX1", "DMIC", "Stereo DAC MIX"
1704};
1705
1706static SOC_ENUM_SINGLE_DECL(
1707 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1708 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1709
1710static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1b7fd76a 1711 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
0e826e86
OC		 1712
1713static SOC_ENUM_SINGLE_DECL(
1714 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1715 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1716
1717static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1b7fd76a 1718 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
0e826e86
OC		 1719
1720static SOC_ENUM_SINGLE_DECL(
1721 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1722 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1723
1724static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1b7fd76a 1725 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
0e826e86
OC		 1726
1727/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1728static const char * const rt5677_dmic_src[] = {
1729 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1730};
1731
1732static SOC_ENUM_SINGLE_DECL(
1733 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1734 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1735
1736static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1b7fd76a 1737 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
0e826e86
OC		 1738
1739static SOC_ENUM_SINGLE_DECL(
1740 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1741 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1742
1743static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1b7fd76a 1744 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
0e826e86
OC		 1745
1746static SOC_ENUM_SINGLE_DECL(
1747 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1748 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1749
1750static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1b7fd76a 1751 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
0e826e86
OC		 1752
1753static SOC_ENUM_SINGLE_DECL(
1754 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1755 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1756
1757static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1b7fd76a 1758 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
0e826e86
OC		 1759
1760static SOC_ENUM_SINGLE_DECL(
1761 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1762 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1763
1764static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1b7fd76a 1765 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
0e826e86
OC		 1766
1767static SOC_ENUM_SINGLE_DECL(
1768 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1769 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1770
1771static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1b7fd76a 1772 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
0e826e86 1773
1b7fd76a 1774/* Stereo2 ADC Source */ /* MX-26 [0] */
0e826e86
OC		 1775static const char * const rt5677_stereo2_adc_lr_src[] = {
1776 "L", "LR"
1777};
1778
1779static SOC_ENUM_SINGLE_DECL(
1780 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1781 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1782
1783static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1b7fd76a 1784 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
0e826e86 1785
d65fd3a4 1786/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
0e826e86
OC		 1787static const char * const rt5677_stereo_adc1_src[] = {
1788 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1789};
1790
1791static SOC_ENUM_SINGLE_DECL(
1792 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1793 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1794
1795static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1b7fd76a 1796 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
0e826e86
OC		 1797
1798static SOC_ENUM_SINGLE_DECL(
1799 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1800 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1801
1802static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1b7fd76a 1803 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
0e826e86
OC		 1804
1805static SOC_ENUM_SINGLE_DECL(
1806 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1807 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1808
1809static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1b7fd76a 1810 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
0e826e86 1811
1b7fd76a 1812/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
0e826e86
OC		 1813static const char * const rt5677_mono_adc2_l_src[] = {
1814 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1815};
1816
1817static SOC_ENUM_SINGLE_DECL(
1818 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1819 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1820
1821static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1b7fd76a 1822 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
0e826e86 1823
1b7fd76a 1824/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
0e826e86
OC		 1825static const char * const rt5677_mono_adc1_l_src[] = {
1826 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1827};
1828
1829static SOC_ENUM_SINGLE_DECL(
1830 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1831 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1832
1833static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1b7fd76a 1834 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
0e826e86 1835
1b7fd76a 1836/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
0e826e86
OC		 1837static const char * const rt5677_mono_adc2_r_src[] = {
1838 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1839};
1840
1841static SOC_ENUM_SINGLE_DECL(
1842 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1843 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1844
1845static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1b7fd76a 1846 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
0e826e86 1847
1b7fd76a 1848/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
0e826e86
OC		 1849static const char * const rt5677_mono_adc1_r_src[] = {
1850 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1851};
1852
1853static SOC_ENUM_SINGLE_DECL(
1854 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1855 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1856
1857static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1b7fd76a 1858 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
0e826e86
OC		 1859
1860/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1861static const char * const rt5677_stereo4_adc2_src[] = {
1862 "DD MIX1", "DMIC", "DD MIX2"
1863};
1864
1865static SOC_ENUM_SINGLE_DECL(
1866 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1867 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1868
1869static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1b7fd76a 1870 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
0e826e86
OC		 1871
1872
1873/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1874static const char * const rt5677_stereo4_adc1_src[] = {
1875 "DD MIX1", "ADC1/2", "DD MIX2"
1876};
1877
1878static SOC_ENUM_SINGLE_DECL(
1879 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1880 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1881
1882static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1b7fd76a 1883 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
0e826e86
OC		 1884
1885/* InBound0/1 Source */ /* MX-A3 [14:12] */
1886static const char * const rt5677_inbound01_src[] = {
1887 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1888 "VAD ADC/DAC1 FS"
1889};
1890
1891static SOC_ENUM_SINGLE_DECL(
1892 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1893 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1894
1895static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1896 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1897
1898/* InBound2/3 Source */ /* MX-A3 [10:8] */
1899static const char * const rt5677_inbound23_src[] = {
1900 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1901 "DAC1 FS", "IF4 DAC"
1902};
1903
1904static SOC_ENUM_SINGLE_DECL(
1905 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1906 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1907
1908static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1909 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1910
1911/* InBound4/5 Source */ /* MX-A3 [6:4] */
1912static const char * const rt5677_inbound45_src[] = {
1913 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1914 "IF3 DAC"
1915};
1916
1917static SOC_ENUM_SINGLE_DECL(
1918 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1919 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1920
1921static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1922 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1923
1924/* InBound6 Source */ /* MX-A3 [2:0] */
1925static const char * const rt5677_inbound6_src[] = {
1926 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1927 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1928};
1929
1930static SOC_ENUM_SINGLE_DECL(
1931 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1932 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1933
1934static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1935 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1936
1937/* InBound7 Source */ /* MX-A4 [14:12] */
1938static const char * const rt5677_inbound7_src[] = {
1939 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1940 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1941};
1942
1943static SOC_ENUM_SINGLE_DECL(
1944 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1945 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1946
1947static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1948 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1949
1950/* InBound8 Source */ /* MX-A4 [10:8] */
1951static const char * const rt5677_inbound8_src[] = {
1952 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1953 "MONO ADC MIX L", "DACL1 FS"
1954};
1955
1956static SOC_ENUM_SINGLE_DECL(
1957 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1958 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1959
1960static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1961 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1962
1963/* InBound9 Source */ /* MX-A4 [6:4] */
1964static const char * const rt5677_inbound9_src[] = {
1965 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1966 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1967};
1968
1969static SOC_ENUM_SINGLE_DECL(
1970 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1971 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1972
1973static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1974 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1975
1976/* VAD Source */ /* MX-9F [6:4] */
1977static const char * const rt5677_vad_src[] = {
1978 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1979 "STO3 ADC MIX L"
1980};
1981
1982static SOC_ENUM_SINGLE_DECL(
1983 rt5677_vad_enum, RT5677_VAD_CTRL4,
1984 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1985
1986static const struct snd_kcontrol_new rt5677_vad_src_mux =
1987 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1988
1989/* Sidetone Source */ /* MX-13 [11:9] */
1990static const char * const rt5677_sidetone_src[] = {
1991 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1992};
1993
1994static SOC_ENUM_SINGLE_DECL(
1995 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1996 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1997
1998static const struct snd_kcontrol_new rt5677_sidetone_mux =
1999 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2000
2001/* DAC1/2 Source */ /* MX-15 [1:0] */
2002static const char * const rt5677_dac12_src[] = {
2003 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2004};
2005
2006static SOC_ENUM_SINGLE_DECL(
2007 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2008 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2009
2010static const struct snd_kcontrol_new rt5677_dac12_mux =
2011 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2012
2013/* DAC3 Source */ /* MX-15 [5:4] */
2014static const char * const rt5677_dac3_src[] = {
2015 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2016};
2017
2018static SOC_ENUM_SINGLE_DECL(
2019 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2020 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2021
2022static const struct snd_kcontrol_new rt5677_dac3_mux =
2023 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2024
1b7fd76a 2025/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
0e826e86
OC		 2026static const char * const rt5677_pdm_src[] = {
2027 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2028};
2029
2030static SOC_ENUM_SINGLE_DECL(
2031 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2032 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2033
2034static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1b7fd76a 2035 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
0e826e86
OC		 2036
2037static SOC_ENUM_SINGLE_DECL(
2038 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2039 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2040
2041static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1b7fd76a 2042 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
0e826e86
OC		 2043
2044static SOC_ENUM_SINGLE_DECL(
2045 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2046 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2047
2048static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1b7fd76a 2049 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
0e826e86
OC		 2050
2051static SOC_ENUM_SINGLE_DECL(
2052 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2053 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2054
2055static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1b7fd76a 2056 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
0e826e86 2057
d65fd3a4 2058/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
0e826e86
OC		 2059static const char * const rt5677_if12_adc1_src[] = {
2060 "STO1 ADC MIX", "OB01", "VAD ADC"
2061};
2062
2063static SOC_ENUM_SINGLE_DECL(
2064 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2065 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2066
2067static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1b7fd76a 2068 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
0e826e86
OC		 2069
2070static SOC_ENUM_SINGLE_DECL(
2071 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2072 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2073
2074static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1b7fd76a 2075 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
0e826e86
OC		 2076
2077static SOC_ENUM_SINGLE_DECL(
2078 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2079 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2080
2081static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1b7fd76a 2082 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
0e826e86
OC		 2083
2084/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2085static const char * const rt5677_if12_adc2_src[] = {
2086 "STO2 ADC MIX", "OB23"
2087};
2088
2089static SOC_ENUM_SINGLE_DECL(
2090 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2091 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2092
2093static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1b7fd76a 2094 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
0e826e86
OC		 2095
2096static SOC_ENUM_SINGLE_DECL(
2097 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2098 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2099
2100static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1b7fd76a 2101 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
0e826e86
OC		 2102
2103static SOC_ENUM_SINGLE_DECL(
2104 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2105 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2106
2107static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1b7fd76a 2108 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
0e826e86
OC		 2109
2110/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2111static const char * const rt5677_if12_adc3_src[] = {
2112 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2113};
2114
2115static SOC_ENUM_SINGLE_DECL(
2116 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2117 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2118
2119static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1b7fd76a 2120 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
0e826e86
OC		 2121
2122static SOC_ENUM_SINGLE_DECL(
2123 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2124 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2125
2126static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1b7fd76a 2127 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
0e826e86
OC		 2128
2129static SOC_ENUM_SINGLE_DECL(
2130 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2131 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2132
2133static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1b7fd76a 2134 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
0e826e86 2135
d65fd3a4 2136/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
0e826e86
OC		 2137static const char * const rt5677_if12_adc4_src[] = {
2138 "STO4 ADC MIX", "OB67", "OB01"
2139};
2140
2141static SOC_ENUM_SINGLE_DECL(
2142 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2143 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2144
2145static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1b7fd76a 2146 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
0e826e86
OC		 2147
2148static SOC_ENUM_SINGLE_DECL(
2149 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2150 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2151
2152static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1b7fd76a 2153 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
0e826e86
OC		 2154
2155static SOC_ENUM_SINGLE_DECL(
2156 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2157 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2158
2159static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1b7fd76a 2160 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
0e826e86 2161
d65fd3a4 2162/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
0e826e86
OC		 2163static const char * const rt5677_if34_adc_src[] = {
2164 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2165 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2166};
2167
2168static SOC_ENUM_SINGLE_DECL(
2169 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2170 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2171
2172static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1b7fd76a 2173 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
0e826e86
OC		 2174
2175static SOC_ENUM_SINGLE_DECL(
2176 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2177 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2178
2179static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1b7fd76a 2180 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
0e826e86 2181
e6f6ebc1
OC		 2182/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2183static const char * const rt5677_if12_adc_swap_src[] = {
2184 "L/R", "R/L", "L/L", "R/R"
2185};
2186
2187static SOC_ENUM_SINGLE_DECL(
2188 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2189 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2190
2191static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2192 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2193
2194static SOC_ENUM_SINGLE_DECL(
2195 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2196 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2197
2198static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2199 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2200
2201static SOC_ENUM_SINGLE_DECL(
2202 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2203 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2204
2205static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2206 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2207
2208static SOC_ENUM_SINGLE_DECL(
2209 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2210 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2211
2212static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2213 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2214
2215static SOC_ENUM_SINGLE_DECL(
2216 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2217 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2218
2219static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2220 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2221
2222static SOC_ENUM_SINGLE_DECL(
2223 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2224 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2225
2226static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2227 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2228
2229static SOC_ENUM_SINGLE_DECL(
2230 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2231 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2232
2233static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2234 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2235
2236static SOC_ENUM_SINGLE_DECL(
2237 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2238 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2239
2240static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2241 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2242
d65fd3a4 2243/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
e6f6ebc1
OC		 2244static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2245 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2246 "3/1/2/4", "3/4/1/2"
2247};
2248
2249static SOC_ENUM_SINGLE_DECL(
2250 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2251 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2252
2253static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2254 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2255
2256/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2257static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2258 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2259 "2/3/1/4", "3/4/1/2"
2260};
2261
2262static SOC_ENUM_SINGLE_DECL(
2263 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2264 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2265
2266static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2267 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2268
91159eca
OC		 2269/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2270 MX-3F[14:12][10:8][6:4][2:0]
2271 MX-43[14:12][10:8][6:4][2:0]
2272 MX-44[14:12][10:8][6:4][2:0] */
2273static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2274 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2275};
2276
2277static SOC_ENUM_SINGLE_DECL(
2278 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2279 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2280
2281static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2282 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2283
2284static SOC_ENUM_SINGLE_DECL(
2285 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2286 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2287
2288static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2289 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2290
2291static SOC_ENUM_SINGLE_DECL(
2292 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2293 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2294
2295static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2296 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2297
2298static SOC_ENUM_SINGLE_DECL(
2299 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2300 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2301
2302static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2303 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2304
2305static SOC_ENUM_SINGLE_DECL(
2306 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2307 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2308
2309static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2310 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2311
2312static SOC_ENUM_SINGLE_DECL(
2313 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2314 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2315
2316static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2317 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2318
2319static SOC_ENUM_SINGLE_DECL(
2320 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2321 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2322
2323static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2324 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2325
2326static SOC_ENUM_SINGLE_DECL(
2327 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2328 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2329
2330static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2331 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2332
2333static SOC_ENUM_SINGLE_DECL(
2334 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2335 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2336
2337static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2338 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2339
2340static SOC_ENUM_SINGLE_DECL(
2341 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2342 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2343
2344static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2345 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2346
2347static SOC_ENUM_SINGLE_DECL(
2348 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2349 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2350
2351static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2352 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2353
2354static SOC_ENUM_SINGLE_DECL(
2355 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2356 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2357
2358static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2359 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2360
2361static SOC_ENUM_SINGLE_DECL(
2362 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2363 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2364
2365static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2366 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2367
2368static SOC_ENUM_SINGLE_DECL(
2369 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2370 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2371
2372static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2373 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2374
2375static SOC_ENUM_SINGLE_DECL(
2376 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2377 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2378
2379static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2380 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2381
2382static SOC_ENUM_SINGLE_DECL(
2383 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2384 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2385
2386static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2387 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2388
0e826e86
OC		 2389static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2390 struct snd_kcontrol *kcontrol, int event)
2391{
79223bf1
KM		 2392 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2393 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 2394
2395 switch (event) {
2396 case SND_SOC_DAPM_POST_PMU:
2397 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2398 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2399 break;
2400
2401 case SND_SOC_DAPM_PRE_PMD:
2402 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2403 RT5677_PWR_BST1_P, 0);
2404 break;
2405
2406 default:
2407 return 0;
2408 }
2409
2410 return 0;
2411}
2412
2413static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2414 struct snd_kcontrol *kcontrol, int event)
2415{
79223bf1
KM		 2416 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2417 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 2418
2419 switch (event) {
2420 case SND_SOC_DAPM_POST_PMU:
2421 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2422 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2423 break;
2424
2425 case SND_SOC_DAPM_PRE_PMD:
2426 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2427 RT5677_PWR_BST2_P, 0);
2428 break;
2429
2430 default:
2431 return 0;
2432 }
2433
2434 return 0;
2435}
2436
2437static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2438 struct snd_kcontrol *kcontrol, int event)
2439{
79223bf1
KM		 2440 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2441 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 2442
2443 switch (event) {
bdfbf255 2444 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2445 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2446 break;
2447
2448 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2449 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2450 break;
bdfbf255 2451
0e826e86
OC		 2452 default:
2453 return 0;
2454 }
2455
2456 return 0;
2457}
2458
2459static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2460 struct snd_kcontrol *kcontrol, int event)
2461{
79223bf1
KM		 2462 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2463 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 2464
2465 switch (event) {
bdfbf255 2466 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2467 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2468 break;
2469
2470 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2471 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2472 break;
bdfbf255 2473
0e826e86
OC		 2474 default:
2475 return 0;
2476 }
2477
2478 return 0;
2479}
2480
2481static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2482 struct snd_kcontrol *kcontrol, int event)
2483{
79223bf1
KM		 2484 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2485 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 2486
2487 switch (event) {
2488 case SND_SOC_DAPM_POST_PMU:
2489 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2490 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2491 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2492 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2493 break;
f58c3b91
OC		 2494
2495 case SND_SOC_DAPM_PRE_PMD:
2496 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2497 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2498 RT5677_PWR_CLK_MB, 0);
2499 break;
2500
0e826e86
OC		 2501 default:
2502 return 0;
2503 }
2504
2505 return 0;
2506}
2507
e6f6ebc1
OC		 2508static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2509 struct snd_kcontrol *kcontrol, int event)
2510{
79223bf1
KM		 2511 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2512 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
e6f6ebc1
OC		 2513 unsigned int value;
2514
2515 switch (event) {
2516 case SND_SOC_DAPM_PRE_PMU:
2517 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2518 if (value & RT5677_IF1_ADC_CTRL_MASK)
2519 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2520 RT5677_IF1_ADC_MODE_MASK,
2521 RT5677_IF1_ADC_MODE_TDM);
2522 break;
2523
2524 default:
2525 return 0;
2526 }
2527
2528 return 0;
2529}
2530
2531static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2532 struct snd_kcontrol *kcontrol, int event)
2533{
79223bf1
KM		 2534 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2535 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
e6f6ebc1
OC		 2536 unsigned int value;
2537
2538 switch (event) {
2539 case SND_SOC_DAPM_PRE_PMU:
2540 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2541 if (value & RT5677_IF2_ADC_CTRL_MASK)
2542 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2543 RT5677_IF2_ADC_MODE_MASK,
2544 RT5677_IF2_ADC_MODE_TDM);
2545 break;
2546
2547 default:
2548 return 0;
2549 }
2550
2551 return 0;
2552}
2553
683996cb
OC		 2554static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2555 struct snd_kcontrol *kcontrol, int event)
2556{
79223bf1
KM		 2557 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2558 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
683996cb
OC		 2559
2560 switch (event) {
2561 case SND_SOC_DAPM_POST_PMU:
79223bf1 2562 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON &&
683996cb
OC		 2563 !rt5677->is_vref_slow) {
2564 mdelay(20);
2565 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2566 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2567 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2568 rt5677->is_vref_slow = true;
2569 }
2570 break;
2571
2572 default:
2573 return 0;
2574 }
2575
2576 return 0;
2577}
2578
c22d7666
OC		 2579static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
2580 struct snd_kcontrol *kcontrol, int event)
2581{
2582 switch (event) {
2583 case SND_SOC_DAPM_POST_PMU:
2584 msleep(50);
2585 break;
2586
2587 default:
2588 return 0;
2589 }
2590
2591 return 0;
2592}
2593
0e826e86
OC		 2594static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2595 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
bdfbf255
OC		 2596 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2597 SND_SOC_DAPM_POST_PMU),
0e826e86 2598 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
bdfbf255
OC		 2599 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2600 SND_SOC_DAPM_POST_PMU),
0e826e86 2601
5a8c7c26
OC		 2602 /* ASRC */
2603 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2604 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2605 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2606 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2607 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2608 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2609 0),
2610 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2611 0),
2612 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2613 0),
2614 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2615 0),
2616 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2617 0),
2618 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2619 0),
2620 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2621 0),
2622 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2623 0),
2624 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2625 0),
2626 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2627 0),
2628 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2629 0),
2630 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2631 0),
2632 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2633 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2634 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2635 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2636 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2637 0),
2638 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2639 0),
2640
0e826e86
OC		 2641 /* Input Side */
2642 /* micbias */
3d0c03d9 2643 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
f58c3b91
OC		 2644 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2645 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 2646
2647 /* Input Lines */
2648 SND_SOC_DAPM_INPUT("DMIC L1"),
2649 SND_SOC_DAPM_INPUT("DMIC R1"),
2650 SND_SOC_DAPM_INPUT("DMIC L2"),
2651 SND_SOC_DAPM_INPUT("DMIC R2"),
2652 SND_SOC_DAPM_INPUT("DMIC L3"),
2653 SND_SOC_DAPM_INPUT("DMIC R3"),
2654 SND_SOC_DAPM_INPUT("DMIC L4"),
2655 SND_SOC_DAPM_INPUT("DMIC R4"),
2656
2657 SND_SOC_DAPM_INPUT("IN1P"),
2658 SND_SOC_DAPM_INPUT("IN1N"),
2659 SND_SOC_DAPM_INPUT("IN2P"),
2660 SND_SOC_DAPM_INPUT("IN2N"),
2661
2662 SND_SOC_DAPM_INPUT("Haptic Generator"),
2663
2d15d974
BL		 2664 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2665 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2666 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2667 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2668
2669 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2670 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2671 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2672 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2673 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2674 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2675 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2676 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
0e826e86
OC		 2677
2678 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2679 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2680
2681 /* Boost */
2682 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2683 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2684 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2685 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2686 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2687 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2688
2689 /* ADCs */
2690 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2691 0, 0),
2692 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2693 0, 0),
2694 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2695
2696 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2697 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2698 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2699 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2700 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2701 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2702 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2703 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2704
2705 /* ADC Mux */
2706 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2707 &rt5677_sto1_dmic_mux),
2708 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2709 &rt5677_sto1_adc1_mux),
2710 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2711 &rt5677_sto1_adc2_mux),
2712 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2713 &rt5677_sto2_dmic_mux),
2714 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2715 &rt5677_sto2_adc1_mux),
2716 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2717 &rt5677_sto2_adc2_mux),
2718 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2719 &rt5677_sto2_adc_lr_mux),
2720 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2721 &rt5677_sto3_dmic_mux),
2722 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2723 &rt5677_sto3_adc1_mux),
2724 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2725 &rt5677_sto3_adc2_mux),
2726 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2727 &rt5677_sto4_dmic_mux),
2728 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2729 &rt5677_sto4_adc1_mux),
2730 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2731 &rt5677_sto4_adc2_mux),
2732 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2733 &rt5677_mono_dmic_l_mux),
2734 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2735 &rt5677_mono_dmic_r_mux),
2736 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2737 &rt5677_mono_adc2_l_mux),
2738 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2739 &rt5677_mono_adc1_l_mux),
2740 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2741 &rt5677_mono_adc1_r_mux),
2742 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2743 &rt5677_mono_adc2_r_mux),
2744
2745 /* ADC Mixer */
2746 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2747 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2748 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2749 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2750 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2751 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2752 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2753 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2754 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2755 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2756 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2757 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2758 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2759 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2760 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2761 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2762 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2763 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2764 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2765 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2766 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2767 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2768 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2769 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2770 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2771 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2772 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2773 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2774 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2775 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2776 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2777 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2778
2779 /* ADC PGA */
2780 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2781 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2782 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2783 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2784 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2785 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2786 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2787 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2788 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2791 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2792 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2793 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
e6f6ebc1
OC		 2794 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
0e826e86
OC		 2796
2797 /* DSP */
2798 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2799 &rt5677_ib9_src_mux),
2800 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2801 &rt5677_ib8_src_mux),
2802 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2803 &rt5677_ib7_src_mux),
2804 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2805 &rt5677_ib6_src_mux),
2806 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2807 &rt5677_ib45_src_mux),
2808 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2809 &rt5677_ib23_src_mux),
2810 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5677_ib01_src_mux),
2812 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5677_ib45_bypass_src_mux),
2814 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5677_ib23_bypass_src_mux),
2816 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5677_ib01_bypass_src_mux),
2818 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5677_ob23_bypass_src_mux),
2820 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5677_ob01_bypass_src_mux),
2822
2823 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2824 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2825
2826 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2827 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2828 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2829 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2830 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2831 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2832
2833 /* Digital Interface */
2834 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2835 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2836 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2837 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2838 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2839 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2840 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2841 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2842 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2843 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2852
2853 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2854 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2856 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2858 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2859 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2860 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2871
2872 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2873 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2880
2881 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2882 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2886 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2887 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2888 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2889
2890 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2891 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2892 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2893 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2894 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2895 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2896 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2897 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2898 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2908
2909 /* Digital Interface Select */
2910 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2911 &rt5677_if1_adc1_mux),
2912 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2913 &rt5677_if1_adc2_mux),
2914 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2915 &rt5677_if1_adc3_mux),
2916 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5677_if1_adc4_mux),
e6f6ebc1
OC		 2918 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5677_if1_adc1_swap_mux),
2920 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5677_if1_adc2_swap_mux),
2922 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5677_if1_adc3_swap_mux),
2924 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5677_if1_adc4_swap_mux),
2926 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2927 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2928 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2929 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2930 &rt5677_if2_adc1_mux),
2931 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2932 &rt5677_if2_adc2_mux),
2933 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2934 &rt5677_if2_adc3_mux),
2935 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2936 &rt5677_if2_adc4_mux),
e6f6ebc1
OC		 2937 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2938 &rt5677_if2_adc1_swap_mux),
2939 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2940 &rt5677_if2_adc2_swap_mux),
2941 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2942 &rt5677_if2_adc3_swap_mux),
2943 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2944 &rt5677_if2_adc4_swap_mux),
2945 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2946 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2947 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2948 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2949 &rt5677_if3_adc_mux),
2950 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2951 &rt5677_if4_adc_mux),
2952 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5677_slb_adc1_mux),
2954 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5677_slb_adc2_mux),
2956 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5677_slb_adc3_mux),
2958 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5677_slb_adc4_mux),
2960
91159eca
OC		 2961 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5677_if1_dac0_tdm_sel_mux),
2963 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5677_if1_dac1_tdm_sel_mux),
2965 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5677_if1_dac2_tdm_sel_mux),
2967 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5677_if1_dac3_tdm_sel_mux),
2969 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5677_if1_dac4_tdm_sel_mux),
2971 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5677_if1_dac5_tdm_sel_mux),
2973 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5677_if1_dac6_tdm_sel_mux),
2975 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5677_if1_dac7_tdm_sel_mux),
2977
2978 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2979 &rt5677_if2_dac0_tdm_sel_mux),
2980 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2981 &rt5677_if2_dac1_tdm_sel_mux),
2982 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2983 &rt5677_if2_dac2_tdm_sel_mux),
2984 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2985 &rt5677_if2_dac3_tdm_sel_mux),
2986 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2987 &rt5677_if2_dac4_tdm_sel_mux),
2988 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2989 &rt5677_if2_dac5_tdm_sel_mux),
2990 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2991 &rt5677_if2_dac6_tdm_sel_mux),
2992 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2993 &rt5677_if2_dac7_tdm_sel_mux),
2994
0e826e86
OC		 2995 /* Audio Interface */
2996 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2997 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2998 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2999 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3000 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3001 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3002 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3003 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3006
3007 /* Sidetone Mux */
3008 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3009 &rt5677_sidetone_mux),
90bdbb46
OC		 3010 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3011 RT5677_ST_EN_SFT, 0, NULL, 0),
3012
0e826e86
OC		 3013 /* VAD Mux*/
3014 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3015 &rt5677_vad_src_mux),
3016
3017 /* Tensilica DSP */
3018 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3019 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3020 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3021 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3022 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3023 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3024 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3025 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3026 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3027 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3028 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3029 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3030 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3031
3032 /* Output Side */
d65fd3a4 3033 /* DAC mixer before sound effect */
0e826e86
OC		 3034 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3035 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3036 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3037 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3038 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3039
3040 /* DAC Mux */
3041 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3042 &rt5677_dac1_mux),
3043 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3044 &rt5677_adda1_mux),
3045 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3046 &rt5677_dac12_mux),
3047 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3048 &rt5677_dac3_mux),
3049
3050 /* DAC2 channel Mux */
3051 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3052 &rt5677_dac2_l_mux),
3053 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3054 &rt5677_dac2_r_mux),
3055
3056 /* DAC3 channel Mux */
3057 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3058 &rt5677_dac3_l_mux),
3059 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3060 &rt5677_dac3_r_mux),
3061
3062 /* DAC4 channel Mux */
3063 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3064 &rt5677_dac4_l_mux),
3065 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3066 &rt5677_dac4_r_mux),
3067
3068 /* DAC Mixer */
3069 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
c22d7666
OC		 3070 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
3071 SND_SOC_DAPM_POST_PMU),
6800b5ba 3072 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
c22d7666
OC		 3073 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
3074 SND_SOC_DAPM_POST_PMU),
6800b5ba 3075 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
c22d7666
OC		 3076 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
3077 SND_SOC_DAPM_POST_PMU),
6800b5ba 3078 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
c22d7666
OC		 3079 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
3080 SND_SOC_DAPM_POST_PMU),
6800b5ba 3081 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
c22d7666
OC		 3082 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
3083 SND_SOC_DAPM_POST_PMU),
6800b5ba 3084 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
c22d7666
OC		 3085 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
3086 SND_SOC_DAPM_POST_PMU),
6800b5ba 3087 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
c22d7666
OC		 3088 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
3089 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 3090
3091 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3092 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3093 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3094 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3095 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3096 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3097 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3098 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3099 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3100 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3101 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3102 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3103 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3104 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3105 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3106 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3107 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3108 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3109 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3110 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3111
3112 /* DACs */
3113 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3114 RT5677_PWR_DAC1_BIT, 0),
3115 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3116 RT5677_PWR_DAC2_BIT, 0),
3117 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3118 RT5677_PWR_DAC3_BIT, 0),
3119
3120 /* PDM */
3121 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3122 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3123 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3124 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3125
3126 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3127 1, &rt5677_pdm1_l_mux),
3128 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3129 1, &rt5677_pdm1_r_mux),
3130 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3131 1, &rt5677_pdm2_l_mux),
3132 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3133 1, &rt5677_pdm2_r_mux),
3134
683996cb 3135 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
0e826e86 3136 0, NULL, 0),
683996cb 3137 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
0e826e86 3138 0, NULL, 0),
683996cb 3139 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
0e826e86
OC		 3140 0, NULL, 0),
3141
683996cb
OC		 3142 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3143 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3144 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3145 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3146 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3147 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3148
0e826e86
OC		 3149 /* Output Lines */
3150 SND_SOC_DAPM_OUTPUT("LOUT1"),
3151 SND_SOC_DAPM_OUTPUT("LOUT2"),
3152 SND_SOC_DAPM_OUTPUT("LOUT3"),
3153 SND_SOC_DAPM_OUTPUT("PDM1L"),
3154 SND_SOC_DAPM_OUTPUT("PDM1R"),
3155 SND_SOC_DAPM_OUTPUT("PDM2L"),
3156 SND_SOC_DAPM_OUTPUT("PDM2R"),
683996cb
OC		 3157
3158 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
0e826e86
OC		 3159};
3160
3161static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
5220f7fb
OC		 3162 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3163 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3164 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3165 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3166 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3167 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
5a8c7c26
OC		 3168 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3169 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3170 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3171 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3172
3173 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3174 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3175 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3176 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3177 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3178 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3179 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3180 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3181 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3182 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3183 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3184 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3185 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3186
0e826e86
OC		 3187 { "DMIC1", NULL, "DMIC L1" },
3188 { "DMIC1", NULL, "DMIC R1" },
3189 { "DMIC2", NULL, "DMIC L2" },
3190 { "DMIC2", NULL, "DMIC R2" },
3191 { "DMIC3", NULL, "DMIC L3" },
3192 { "DMIC3", NULL, "DMIC R3" },
3193 { "DMIC4", NULL, "DMIC L4" },
3194 { "DMIC4", NULL, "DMIC R4" },
3195
3196 { "DMIC L1", NULL, "DMIC CLK" },
3197 { "DMIC R1", NULL, "DMIC CLK" },
3198 { "DMIC L2", NULL, "DMIC CLK" },
3199 { "DMIC R2", NULL, "DMIC CLK" },
3200 { "DMIC L3", NULL, "DMIC CLK" },
3201 { "DMIC R3", NULL, "DMIC CLK" },
3202 { "DMIC L4", NULL, "DMIC CLK" },
3203 { "DMIC R4", NULL, "DMIC CLK" },
3204
2d15d974
BL		 3205 { "DMIC L1", NULL, "DMIC1 power" },
3206 { "DMIC R1", NULL, "DMIC1 power" },
3207 { "DMIC L3", NULL, "DMIC3 power" },
3208 { "DMIC R3", NULL, "DMIC3 power" },
3209 { "DMIC L4", NULL, "DMIC4 power" },
3210 { "DMIC R4", NULL, "DMIC4 power" },
3211
0e826e86
OC		 3212 { "BST1", NULL, "IN1P" },
3213 { "BST1", NULL, "IN1N" },
3214 { "BST2", NULL, "IN2P" },
3215 { "BST2", NULL, "IN2N" },
3216
22e51345
BL		 3217 { "IN1P", NULL, "MICBIAS1" },
3218 { "IN1N", NULL, "MICBIAS1" },
3219 { "IN2P", NULL, "MICBIAS1" },
3220 { "IN2N", NULL, "MICBIAS1" },
0e826e86
OC		 3221
3222 { "ADC 1", NULL, "BST1" },
3223 { "ADC 1", NULL, "ADC 1 power" },
3224 { "ADC 1", NULL, "ADC1 clock" },
3225 { "ADC 2", NULL, "BST2" },
3226 { "ADC 2", NULL, "ADC 2 power" },
3227 { "ADC 2", NULL, "ADC2 clock" },
3228
3229 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3230 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3231 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3232 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3233
3234 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3235 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3236 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3237 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3238
3239 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3240 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3241 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3242 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3243
3244 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3245 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3246 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3247 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3248
3249 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3250 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3251 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3252 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3253
3254 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3255 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3256 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3257 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3258
3259 { "ADC 1_2", NULL, "ADC 1" },
3260 { "ADC 1_2", NULL, "ADC 2" },
3261
3262 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3263 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3264 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3265
3266 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3267 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3268 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3269
3270 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3271 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3272 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3273
3274 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3275 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3276 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3277
3278 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3279 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3280 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3281
3282 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3283 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3284 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3285
3286 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3287 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3288 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3289
3290 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3291 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3292 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3293
3294 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3295 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3296 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3297
3298 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3299 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3300 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3301
3302 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3303 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3304 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3305
3306 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3307 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3308 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3309
3310 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3311 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3312 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3313 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3314
3315 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3316 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
0e826e86
OC		 3317 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3318 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3319 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3320
3321 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3322 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3323
3324 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3325 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3326 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3327 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3328
3329 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3330 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3331
3332 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3333 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3334
3335 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3336 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
0e826e86
OC		 3337 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3338 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3339 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3340
3341 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3342 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3343
3344 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3345 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3346 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3347 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3348
3349 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3350 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
0e826e86
OC		 3351 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3352 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3353 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3354
3355 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3356 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3357
3358 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3359 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3360 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3361 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3362
3363 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3364 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
0e826e86
OC		 3365 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3366 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3367 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3368
3369 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3370 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3371
3372 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3373 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3374 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3375 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3376
3377 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3378 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3379 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3380 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3381
3382 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3383 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3384
3385 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3386 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3387 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3388 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3389 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3390
3391 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3392 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3393 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3394
3395 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3396 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3397
3398 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3399 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3400 { "IF1 ADC3 Mux", "OB45", "OB45" },
3401
3402 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3403 { "IF1 ADC4 Mux", "OB67", "OB67" },
3404 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3405
e6f6ebc1
OC		 3406 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3407 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3408 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3409 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3410
3411 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3412 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3413 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3414 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3415
3416 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3417 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3418 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3419 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3420
3421 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3422 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3423 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3424 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3425
3426 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3427 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3428 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3429 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3430
3431 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3432 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3433 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3434 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3435 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3436 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3437 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3438 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3439
0e826e86 3440 { "AIF1TX", NULL, "I2S1" },
e6f6ebc1 3441 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
0e826e86
OC		 3442
3443 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3444 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3445 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3446
3447 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3448 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3449
3450 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3451 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3452 { "IF2 ADC3 Mux", "OB45", "OB45" },
3453
3454 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3455 { "IF2 ADC4 Mux", "OB67", "OB67" },
3456 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3457
e6f6ebc1
OC		 3458 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3459 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3460 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3461 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3462
3463 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3464 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3465 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3466 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3467
3468 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3469 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3470 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3471 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3472
3473 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3474 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3475 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3476 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3477
3478 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3479 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3480 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3481 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3482
3483 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3484 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3485 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3486 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3487 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3488 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3489 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3490 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3491
0e826e86 3492 { "AIF2TX", NULL, "I2S2" },
e6f6ebc1 3493 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
0e826e86
OC		 3494
3495 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3496 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3497 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3498 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3499 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3500 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3501 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3502 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3503
3504 { "AIF3TX", NULL, "I2S3" },
3505 { "AIF3TX", NULL, "IF3 ADC Mux" },
3506
3507 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3508 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3509 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3510 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3511 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3512 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3513 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3514 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3515
3516 { "AIF4TX", NULL, "I2S4" },
3517 { "AIF4TX", NULL, "IF4 ADC Mux" },
3518
3519 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3520 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3521 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3522
3523 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3524 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3525
3526 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3527 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3528 { "SLB ADC3 Mux", "OB45", "OB45" },
3529
3530 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3531 { "SLB ADC4 Mux", "OB67", "OB67" },
3532 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3533
3534 { "SLBTX", NULL, "SLB" },
3535 { "SLBTX", NULL, "SLB ADC1 Mux" },
3536 { "SLBTX", NULL, "SLB ADC2 Mux" },
3537 { "SLBTX", NULL, "SLB ADC3 Mux" },
3538 { "SLBTX", NULL, "SLB ADC4 Mux" },
3539
3540 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3541 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3542 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3543 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3544 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3545
3546 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3547 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3548
3549 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3550 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3551 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3552 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3553 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3554 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3555
3556 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3557 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3558
3559 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3560 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3561 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3562 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3563 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3564
3565 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3566 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3567
70068776
OC		 3568 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3569 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
0e826e86
OC		 3570 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3571 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3572 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3573 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3574 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3575 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3576
70068776
OC		 3577 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3578 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
0e826e86
OC		 3579 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3580 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3581 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3582 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3583 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3584 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3585
3586 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3587 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3588 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3589 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3590 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3591 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3592
3593 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3594 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3595 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3596 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3597 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3598 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3599 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3600
3601 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3602 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3603 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3604 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3605 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3606 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3607 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3608
3609 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3610 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3611 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3612 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3613 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3614 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3615 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3616
3617 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3618 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3619 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3620 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3621 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3622 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3623 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3624
3625 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3626 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3627 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3628 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3629 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3630 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3631 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3632
3633 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3634 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3635 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3636 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3637 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3638 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3639 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3640
3641 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3642 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3643 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3644 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3645 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3646 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3647 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3648
3649 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3650 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3651 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3652 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3653
3654 { "OutBound2", NULL, "OB23 Bypass Mux" },
3655 { "OutBound3", NULL, "OB23 Bypass Mux" },
3656 { "OutBound4", NULL, "OB4 MIX" },
3657 { "OutBound5", NULL, "OB5 MIX" },
3658 { "OutBound6", NULL, "OB6 MIX" },
3659 { "OutBound7", NULL, "OB7 MIX" },
3660
3661 { "OB45", NULL, "OutBound4" },
3662 { "OB45", NULL, "OutBound5" },
3663 { "OB67", NULL, "OutBound6" },
3664 { "OB67", NULL, "OutBound7" },
3665
3666 { "IF1 DAC0", NULL, "AIF1RX" },
3667 { "IF1 DAC1", NULL, "AIF1RX" },
3668 { "IF1 DAC2", NULL, "AIF1RX" },
3669 { "IF1 DAC3", NULL, "AIF1RX" },
3670 { "IF1 DAC4", NULL, "AIF1RX" },
3671 { "IF1 DAC5", NULL, "AIF1RX" },
3672 { "IF1 DAC6", NULL, "AIF1RX" },
3673 { "IF1 DAC7", NULL, "AIF1RX" },
3674 { "IF1 DAC0", NULL, "I2S1" },
3675 { "IF1 DAC1", NULL, "I2S1" },
3676 { "IF1 DAC2", NULL, "I2S1" },
3677 { "IF1 DAC3", NULL, "I2S1" },
3678 { "IF1 DAC4", NULL, "I2S1" },
3679 { "IF1 DAC5", NULL, "I2S1" },
3680 { "IF1 DAC6", NULL, "I2S1" },
3681 { "IF1 DAC7", NULL, "I2S1" },
3682
91159eca
OC		 3683 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3684 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3685 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3686 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3687 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3688 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3689 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3690 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3691
3692 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3693 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3694 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3695 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3696 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3697 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3698 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3699 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3700
3701 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3702 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3703 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3704 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3705 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3706 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3707 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3708 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3709
3710 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3711 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3712 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3713 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3714 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3715 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3716 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3717 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3718
3719 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3720 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3721 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3722 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3723 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3724 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3725 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3726 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3727
3728 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3729 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3730 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3731 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3732 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3733 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3734 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3735 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3736
3737 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3738 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3739 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3740 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3741 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3742 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3743 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3744 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3745
3746 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3747 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3748 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3749 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3750 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3751 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3752 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3753 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3754
3755 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3756 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3757 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3758 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3759 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3760 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3761 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3762 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
0e826e86
OC		 3763
3764 { "IF2 DAC0", NULL, "AIF2RX" },
3765 { "IF2 DAC1", NULL, "AIF2RX" },
3766 { "IF2 DAC2", NULL, "AIF2RX" },
3767 { "IF2 DAC3", NULL, "AIF2RX" },
3768 { "IF2 DAC4", NULL, "AIF2RX" },
3769 { "IF2 DAC5", NULL, "AIF2RX" },
3770 { "IF2 DAC6", NULL, "AIF2RX" },
3771 { "IF2 DAC7", NULL, "AIF2RX" },
3772 { "IF2 DAC0", NULL, "I2S2" },
3773 { "IF2 DAC1", NULL, "I2S2" },
3774 { "IF2 DAC2", NULL, "I2S2" },
3775 { "IF2 DAC3", NULL, "I2S2" },
3776 { "IF2 DAC4", NULL, "I2S2" },
3777 { "IF2 DAC5", NULL, "I2S2" },
3778 { "IF2 DAC6", NULL, "I2S2" },
3779 { "IF2 DAC7", NULL, "I2S2" },
3780
91159eca
OC		 3781 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3782 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3783 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3784 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3785 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3786 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3787 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3788 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3789
3790 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3791 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3792 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3793 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3794 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3795 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3796 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3797 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3798
3799 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3800 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3801 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3802 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3803 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3804 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3805 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3806 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3807
3808 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3809 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3810 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3811 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3812 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3813 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3814 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3815 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3816
3817 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3818 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3819 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3820 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3821 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3822 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3823 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3824 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3825
3826 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3827 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3828 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3829 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3830 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3831 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3832 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3833 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3834
3835 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3836 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3837 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3838 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3839 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3840 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3841 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3842 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3843
3844 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3845 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3846 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3847 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3848 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3849 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3850 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3851 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3852
3853 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3854 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3855 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3856 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3857 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3858 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3859 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3860 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
0e826e86
OC		 3861
3862 { "IF3 DAC", NULL, "AIF3RX" },
3863 { "IF3 DAC", NULL, "I2S3" },
3864
3865 { "IF4 DAC", NULL, "AIF4RX" },
3866 { "IF4 DAC", NULL, "I2S4" },
3867
3868 { "IF3 DAC L", NULL, "IF3 DAC" },
3869 { "IF3 DAC R", NULL, "IF3 DAC" },
3870
3871 { "IF4 DAC L", NULL, "IF4 DAC" },
3872 { "IF4 DAC R", NULL, "IF4 DAC" },
3873
3874 { "SLB DAC0", NULL, "SLBRX" },
3875 { "SLB DAC1", NULL, "SLBRX" },
3876 { "SLB DAC2", NULL, "SLBRX" },
3877 { "SLB DAC3", NULL, "SLBRX" },
3878 { "SLB DAC4", NULL, "SLBRX" },
3879 { "SLB DAC5", NULL, "SLBRX" },
3880 { "SLB DAC6", NULL, "SLBRX" },
3881 { "SLB DAC7", NULL, "SLBRX" },
3882 { "SLB DAC0", NULL, "SLB" },
3883 { "SLB DAC1", NULL, "SLB" },
3884 { "SLB DAC2", NULL, "SLB" },
3885 { "SLB DAC3", NULL, "SLB" },
3886 { "SLB DAC4", NULL, "SLB" },
3887 { "SLB DAC5", NULL, "SLB" },
3888 { "SLB DAC6", NULL, "SLB" },
3889 { "SLB DAC7", NULL, "SLB" },
3890
3891 { "SLB DAC01", NULL, "SLB DAC0" },
3892 { "SLB DAC01", NULL, "SLB DAC1" },
3893 { "SLB DAC23", NULL, "SLB DAC2" },
3894 { "SLB DAC23", NULL, "SLB DAC3" },
3895 { "SLB DAC45", NULL, "SLB DAC4" },
3896 { "SLB DAC45", NULL, "SLB DAC5" },
3897 { "SLB DAC67", NULL, "SLB DAC6" },
3898 { "SLB DAC67", NULL, "SLB DAC7" },
3899
3900 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3901 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3902 { "ADDA1 Mux", "OB 67", "OB67" },
3903
3904 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3905 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3906 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3907 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3908 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3909 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3910
3911 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3912 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3913 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3914 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3915
3916 { "DAC1 FS", NULL, "DAC1 MIXL" },
3917 { "DAC1 FS", NULL, "DAC1 MIXR" },
3918
70068776
OC		 3919 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3920 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
0e826e86
OC		 3921 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3922 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3923 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3924 { "DAC2 L Mux", "OB 2", "OutBound2" },
3925
70068776
OC		 3926 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3927 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
0e826e86
OC		 3928 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3929 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3930 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3931 { "DAC2 R Mux", "OB 3", "OutBound3" },
3932 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3933 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3934
70068776
OC		 3935 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3936 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
0e826e86
OC		 3937 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3938 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3939 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3940 { "DAC3 L Mux", "OB 4", "OutBound4" },
3941
70068776
OC		 3942 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3943 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
0e826e86
OC		 3944 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3945 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3946 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3947 { "DAC3 R Mux", "OB 5", "OutBound5" },
3948
70068776
OC		 3949 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3950 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
0e826e86
OC		 3951 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3952 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3953 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3954 { "DAC4 L Mux", "OB 6", "OutBound6" },
3955
70068776
OC		 3956 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3957 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
0e826e86
OC		 3958 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3959 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3960 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3961 { "DAC4 R Mux", "OB 7", "OutBound7" },
3962
3963 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3964 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3965 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3966 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3967 { "Sidetone Mux", "ADC1", "ADC 1" },
3968 { "Sidetone Mux", "ADC2", "ADC 2" },
90bdbb46 3969 { "Sidetone Mux", NULL, "Sidetone Power" },
0e826e86
OC		 3970
3971 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3972 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3973 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3974 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3975 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3976 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3977 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3978 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3979 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3980 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
38d595e2 3981 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3982
3983 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3984 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3985 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3986 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
6800b5ba 3987 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
38d595e2 3988 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3989 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3990 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3991 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3992 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
6800b5ba 3993 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
38d595e2 3994 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3995
3996 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3997 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3998 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3999 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 4000 { "DD1 MIXL", NULL, "dac mono3 left filter" },
38d595e2 4001 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4002 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4003 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4004 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4005 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 4006 { "DD1 MIXR", NULL, "dac mono3 right filter" },
38d595e2 4007 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4008
4009 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4010 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4011 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4012 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 4013 { "DD2 MIXL", NULL, "dac mono4 left filter" },
38d595e2 4014 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4015 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4016 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4017 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4018 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 4019 { "DD2 MIXR", NULL, "dac mono4 right filter" },
38d595e2 4020 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4021
4022 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4023 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4024 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4025 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4026 { "DD1 MIX", NULL, "DD1 MIXL" },
4027 { "DD1 MIX", NULL, "DD1 MIXR" },
4028 { "DD2 MIX", NULL, "DD2 MIXL" },
4029 { "DD2 MIX", NULL, "DD2 MIXR" },
4030
4031 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4032 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4033 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4034 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4035
4036 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4037 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4038 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4039 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4040
4041 { "DAC 1", NULL, "DAC12 SRC Mux" },
0e826e86 4042 { "DAC 2", NULL, "DAC12 SRC Mux" },
0e826e86 4043 { "DAC 3", NULL, "DAC3 SRC Mux" },
0e826e86
OC		 4044
4045 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4046 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4047 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4048 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4049 { "PDM1 L Mux", NULL, "PDM1 Power" },
4050 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4051 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4052 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4053 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4054 { "PDM1 R Mux", NULL, "PDM1 Power" },
4055 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4056 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4057 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4058 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4059 { "PDM2 L Mux", NULL, "PDM2 Power" },
4060 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4061 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4062 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4063 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4064 { "PDM2 R Mux", NULL, "PDM2 Power" },
4065
4066 { "LOUT1 amp", NULL, "DAC 1" },
4067 { "LOUT2 amp", NULL, "DAC 2" },
4068 { "LOUT3 amp", NULL, "DAC 3" },
4069
683996cb
OC		 4070 { "LOUT1 vref", NULL, "LOUT1 amp" },
4071 { "LOUT2 vref", NULL, "LOUT2 amp" },
4072 { "LOUT3 vref", NULL, "LOUT3 amp" },
4073
4074 { "LOUT1", NULL, "LOUT1 vref" },
4075 { "LOUT2", NULL, "LOUT2 vref" },
4076 { "LOUT3", NULL, "LOUT3 vref" },
0e826e86
OC		 4077
4078 { "PDM1L", NULL, "PDM1 L Mux" },
4079 { "PDM1R", NULL, "PDM1 R Mux" },
4080 { "PDM2L", NULL, "PDM2 L Mux" },
4081 { "PDM2R", NULL, "PDM2 R Mux" },
4082};
4083
2d15d974
BL		 4084static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4085 { "DMIC L2", NULL, "DMIC1 power" },
4086 { "DMIC R2", NULL, "DMIC1 power" },
4087};
4088
4089static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4090 { "DMIC L2", NULL, "DMIC2 power" },
4091 { "DMIC R2", NULL, "DMIC2 power" },
4092};
4093
0e826e86
OC		 4094static int rt5677_hw_params(struct snd_pcm_substream *substream,
4095 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4096{
79223bf1
KM		 4097 struct snd_soc_component *component = dai->component;
4098 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 4099 unsigned int val_len = 0, val_clk, mask_clk;
4100 int pre_div, bclk_ms, frame_size;
4101
4102 rt5677->lrck[dai->id] = params_rate(params);
30f14b43 4103 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86 4104 if (pre_div < 0) {
79223bf1 4105 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
8a4bd60a 4106 rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86
OC		 4107 return -EINVAL;
4108 }
4109 frame_size = snd_soc_params_to_frame_size(params);
4110 if (frame_size < 0) {
79223bf1 4111 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
0e826e86
OC		 4112 return -EINVAL;
4113 }
4114 bclk_ms = frame_size > 32;
4115 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4116
4117 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4118 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4119 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4120 bclk_ms, pre_div, dai->id);
4121
4122 switch (params_width(params)) {
4123 case 16:
4124 break;
4125 case 20:
4126 val_len |= RT5677_I2S_DL_20;
4127 break;
4128 case 24:
4129 val_len |= RT5677_I2S_DL_24;
4130 break;
4131 case 8:
4132 val_len |= RT5677_I2S_DL_8;
4133 break;
4134 default:
4135 return -EINVAL;
4136 }
4137
4138 switch (dai->id) {
4139 case RT5677_AIF1:
4140 mask_clk = RT5677_I2S_PD1_MASK;
4141 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4142 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4143 RT5677_I2S_DL_MASK, val_len);
4144 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4145 mask_clk, val_clk);
4146 break;
4147 case RT5677_AIF2:
4148 mask_clk = RT5677_I2S_PD2_MASK;
4149 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4150 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4151 RT5677_I2S_DL_MASK, val_len);
4152 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4153 mask_clk, val_clk);
4154 break;
4155 case RT5677_AIF3:
4156 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4157 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4158 pre_div << RT5677_I2S_PD3_SFT;
4159 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4160 RT5677_I2S_DL_MASK, val_len);
4161 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4162 mask_clk, val_clk);
4163 break;
4164 case RT5677_AIF4:
4165 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4166 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4167 pre_div << RT5677_I2S_PD4_SFT;
4168 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4169 RT5677_I2S_DL_MASK, val_len);
4170 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4171 mask_clk, val_clk);
4172 break;
4173 default:
4174 break;
4175 }
4176
4177 return 0;
4178}
4179
4180static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4181{
79223bf1
KM		 4182 struct snd_soc_component *component = dai->component;
4183 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 4184 unsigned int reg_val = 0;
4185
4186 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4187 case SND_SOC_DAIFMT_CBM_CFM:
4188 rt5677->master[dai->id] = 1;
4189 break;
4190 case SND_SOC_DAIFMT_CBS_CFS:
4191 reg_val |= RT5677_I2S_MS_S;
4192 rt5677->master[dai->id] = 0;
4193 break;
4194 default:
4195 return -EINVAL;
4196 }
4197
4198 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4199 case SND_SOC_DAIFMT_NB_NF:
4200 break;
4201 case SND_SOC_DAIFMT_IB_NF:
4202 reg_val |= RT5677_I2S_BP_INV;
4203 break;
4204 default:
4205 return -EINVAL;
4206 }
4207
4208 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4209 case SND_SOC_DAIFMT_I2S:
4210 break;
4211 case SND_SOC_DAIFMT_LEFT_J:
4212 reg_val |= RT5677_I2S_DF_LEFT;
4213 break;
4214 case SND_SOC_DAIFMT_DSP_A:
4215 reg_val |= RT5677_I2S_DF_PCM_A;
4216 break;
4217 case SND_SOC_DAIFMT_DSP_B:
4218 reg_val |= RT5677_I2S_DF_PCM_B;
4219 break;
4220 default:
4221 return -EINVAL;
4222 }
4223
4224 switch (dai->id) {
4225 case RT5677_AIF1:
4226 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4227 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4228 RT5677_I2S_DF_MASK, reg_val);
4229 break;
4230 case RT5677_AIF2:
4231 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4232 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4233 RT5677_I2S_DF_MASK, reg_val);
4234 break;
4235 case RT5677_AIF3:
4236 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4237 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4238 RT5677_I2S_DF_MASK, reg_val);
4239 break;
4240 case RT5677_AIF4:
4241 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4242 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4243 RT5677_I2S_DF_MASK, reg_val);
4244 break;
4245 default:
4246 break;
4247 }
4248
4249
4250 return 0;
4251}
4252
4253static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4254 int clk_id, unsigned int freq, int dir)
4255{
79223bf1
KM		 4256 struct snd_soc_component *component = dai->component;
4257 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 4258 unsigned int reg_val = 0;
4259
4260 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4261 return 0;
4262
4263 switch (clk_id) {
4264 case RT5677_SCLK_S_MCLK:
4265 reg_val |= RT5677_SCLK_SRC_MCLK;
4266 break;
4267 case RT5677_SCLK_S_PLL1:
4268 reg_val |= RT5677_SCLK_SRC_PLL1;
4269 break;
4270 case RT5677_SCLK_S_RCCLK:
4271 reg_val |= RT5677_SCLK_SRC_RCCLK;
4272 break;
4273 default:
79223bf1 4274 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
0e826e86
OC		 4275 return -EINVAL;
4276 }
4277 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4278 RT5677_SCLK_SRC_MASK, reg_val);
4279 rt5677->sysclk = freq;
4280 rt5677->sysclk_src = clk_id;
4281
4282 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4283
4284 return 0;
4285}
4286
4287/**
4288 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4289 * @freq_in: external clock provided to codec.
4290 * @freq_out: target clock which codec works on.
4291 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4292 *
4293 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4294 *
4295 * Returns 0 for success or negative error code.
4296 */
4297static int rt5677_pll_calc(const unsigned int freq_in,
099d334e 4298 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
0e826e86 4299{
099d334e 4300 if (RT5677_PLL_INP_MIN > freq_in)
0e826e86
OC		 4301 return -EINVAL;
4302
099d334e 4303 return rl6231_pll_calc(freq_in, freq_out, pll_code);
0e826e86
OC		 4304}
4305
4306static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4307 unsigned int freq_in, unsigned int freq_out)
4308{
79223bf1
KM		 4309 struct snd_soc_component *component = dai->component;
4310 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
099d334e 4311 struct rl6231_pll_code pll_code;
0e826e86
OC		 4312 int ret;
4313
4314 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4315 freq_out == rt5677->pll_out)
4316 return 0;
4317
4318 if (!freq_in || !freq_out) {
79223bf1 4319 dev_dbg(component->dev, "PLL disabled\n");
0e826e86
OC		 4320
4321 rt5677->pll_in = 0;
4322 rt5677->pll_out = 0;
4323 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4324 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4325 return 0;
4326 }
4327
4328 switch (source) {
4329 case RT5677_PLL1_S_MCLK:
4330 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4331 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4332 break;
4333 case RT5677_PLL1_S_BCLK1:
4334 case RT5677_PLL1_S_BCLK2:
4335 case RT5677_PLL1_S_BCLK3:
4336 case RT5677_PLL1_S_BCLK4:
4337 switch (dai->id) {
4338 case RT5677_AIF1:
4339 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4340 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4341 break;
4342 case RT5677_AIF2:
4343 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4344 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4345 break;
4346 case RT5677_AIF3:
4347 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4348 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4349 break;
4350 case RT5677_AIF4:
4351 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4352 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4353 break;
4354 default:
4355 break;
4356 }
4357 break;
4358 default:
79223bf1 4359 dev_err(component->dev, "Unknown PLL source %d\n", source);
0e826e86
OC		 4360 return -EINVAL;
4361 }
4362
4363 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4364 if (ret < 0) {
79223bf1 4365 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
0e826e86
OC		 4366 return ret;
4367 }
4368
79223bf1 4369 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n",
099d334e
AL		 4370 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4371 pll_code.n_code, pll_code.k_code);
0e826e86
OC		 4372
4373 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
099d334e 4374 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
0e826e86
OC		 4375 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4376 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4377 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4378
4379 rt5677->pll_in = freq_in;
4380 rt5677->pll_out = freq_out;
4381 rt5677->pll_src = source;
4382
4383 return 0;
4384}
4385
48561afe
OC		 4386static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4387 unsigned int rx_mask, int slots, int slot_width)
4388{
79223bf1
KM		 4389 struct snd_soc_component *component = dai->component;
4390 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
9913b9f5 4391 unsigned int val = 0, slot_width_25 = 0;
48561afe
OC		 4392
4393 if (rx_mask || tx_mask)
4394 val |= (1 << 12);
4395
4396 switch (slots) {
4397 case 4:
4398 val |= (1 << 10);
4399 break;
4400 case 6:
4401 val |= (2 << 10);
4402 break;
4403 case 8:
4404 val |= (3 << 10);
4405 break;
4406 case 2:
4407 default:
4408 break;
4409 }
4410
4411 switch (slot_width) {
4412 case 20:
4413 val |= (1 << 8);
4414 break;
9913b9f5
OC		 4415 case 25:
4416 slot_width_25 = 0x8080;
43a26bd0 4417 /* fall through */
48561afe
OC		 4418 case 24:
4419 val |= (2 << 8);
4420 break;
4421 case 32:
4422 val |= (3 << 8);
4423 break;
4424 case 16:
4425 default:
4426 break;
4427 }
4428
4429 switch (dai->id) {
4430 case RT5677_AIF1:
e4b7e6a8
OC		 4431 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4432 val);
9913b9f5
OC		 4433 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4434 slot_width_25);
48561afe
OC		 4435 break;
4436 case RT5677_AIF2:
e4b7e6a8
OC		 4437 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4438 val);
9913b9f5
OC		 4439 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4440 slot_width_25);
48561afe
OC		 4441 break;
4442 default:
4443 break;
4444 }
4445
4446 return 0;
4447}
4448
79223bf1 4449static int rt5677_set_bias_level(struct snd_soc_component *component,
0e826e86
OC		 4450 enum snd_soc_bias_level level)
4451{
79223bf1 4452 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 4453
4454 switch (level) {
4455 case SND_SOC_BIAS_ON:
4456 break;
4457
4458 case SND_SOC_BIAS_PREPARE:
79223bf1
KM		 4459 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
4460 rt5677_set_dsp_vad(component, false);
af48f1d0 4461
0e826e86
OC		 4462 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4463 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4464 0x0055);
4465 regmap_update_bits(rt5677->regmap,
4466 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4467 0x0f00, 0x0f00);
4468 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
683996cb 4469 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
0e826e86
OC		 4470 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4471 RT5677_PWR_BG | RT5677_PWR_VREF2,
4472 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4473 RT5677_PWR_BG | RT5677_PWR_VREF2);
683996cb 4474 rt5677->is_vref_slow = false;
0e826e86
OC		 4475 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4476 RT5677_PWR_CORE, RT5677_PWR_CORE);
4477 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4478 0x1, 0x1);
4479 }
4480 break;
4481
4482 case SND_SOC_BIAS_STANDBY:
4483 break;
4484
4485 case SND_SOC_BIAS_OFF:
4486 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4487 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4488 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
f18803a3 4489 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
0e826e86
OC		 4490 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4491 regmap_update_bits(rt5677->regmap,
4492 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
af48f1d0
OC		 4493
4494 if (rt5677->dsp_vad_en)
79223bf1 4495 rt5677_set_dsp_vad(component, true);
0e826e86
OC		 4496 break;
4497
4498 default:
4499 break;
4500 }
0e826e86
OC		 4501
4502 return 0;
4503}
4504
44caf764 4505#ifdef CONFIG_GPIOLIB
44caf764
OC		 4506static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4507{
14900363 4508 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
44caf764
OC		 4509
4510 switch (offset) {
4511 case RT5677_GPIO1 ... RT5677_GPIO5:
4512 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4513 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4514 break;
4515
4516 case RT5677_GPIO6:
4517 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4518 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4519 break;
4520
4521 default:
4522 break;
4523 }
4524}
4525
4526static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4527 unsigned offset, int value)
4528{
14900363 4529 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
44caf764
OC		 4530
4531 switch (offset) {
4532 case RT5677_GPIO1 ... RT5677_GPIO5:
4533 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4534 0x3 << (offset * 3 + 1),
4535 (0x2 | !!value) << (offset * 3 + 1));
4536 break;
4537
4538 case RT5677_GPIO6:
4539 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4540 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4541 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4542 break;
4543
4544 default:
4545 break;
4546 }
4547
4548 return 0;
4549}
4550
4551static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4552{
14900363 4553 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
44caf764
OC		 4554 int value, ret;
4555
4556 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4557 if (ret < 0)
4558 return ret;
4559
4560 return (value & (0x1 << offset)) >> offset;
4561}
4562
4563static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4564{
14900363 4565 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
44caf764
OC		 4566
4567 switch (offset) {
4568 case RT5677_GPIO1 ... RT5677_GPIO5:
4569 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4570 0x1 << (offset * 3 + 2), 0x0);
4571 break;
4572
4573 case RT5677_GPIO6:
4574 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4575 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4576 break;
4577
4578 default:
4579 break;
4580 }
4581
4582 return 0;
4583}
4584
40eb90a1
AP		 4585/** Configures the gpio as
4586 * 0 - floating
4587 * 1 - pull down
4588 * 2 - pull up
4589 */
4590static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4591 int value)
4592{
4593 int shift;
4594
4595 switch (offset) {
4596 case RT5677_GPIO1 ... RT5677_GPIO2:
4597 shift = 2 * (1 - offset);
4598 regmap_update_bits(rt5677->regmap,
4599 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4600 0x3 << shift,
4601 (value & 0x3) << shift);
4602 break;
4603
4604 case RT5677_GPIO3 ... RT5677_GPIO6:
4605 shift = 2 * (9 - offset);
4606 regmap_update_bits(rt5677->regmap,
4607 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4608 0x3 << shift,
4609 (value & 0x3) << shift);
4610 break;
4611
4612 default:
4613 break;
4614 }
4615}
4616
5e3363ad
OC		 4617static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4618{
14900363 4619 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
5e3363ad
OC		 4620 struct regmap_irq_chip_data *data = rt5677->irq_data;
4621 int irq;
4622
d4e753d3
AS		 4623 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4624 (rt5677->pdata.jd1_gpio == 2 &&
4625 offset == RT5677_GPIO2) ||
4626 (rt5677->pdata.jd1_gpio == 3 &&
4627 offset == RT5677_GPIO3)) {
4628 irq = RT5677_IRQ_JD1;
4629 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4630 (rt5677->pdata.jd2_gpio == 2 &&
4631 offset == RT5677_GPIO5) ||
4632 (rt5677->pdata.jd2_gpio == 3 &&
4633 offset == RT5677_GPIO6)) {
4634 irq = RT5677_IRQ_JD2;
4635 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4636 offset == RT5677_GPIO4) ||
4637 (rt5677->pdata.jd3_gpio == 2 &&
4638 offset == RT5677_GPIO5) ||
4639 (rt5677->pdata.jd3_gpio == 3 &&
4640 offset == RT5677_GPIO6)) {
4641 irq = RT5677_IRQ_JD3;
4642 } else {
4643 return -ENXIO;
5e3363ad
OC		 4644 }
4645
4646 return regmap_irq_get_virq(data, irq);
4647}
4648
c59b24f8 4649static const struct gpio_chip rt5677_template_chip = {
44caf764
OC		 4650 .label = "rt5677",
4651 .owner = THIS_MODULE,
4652 .direction_output = rt5677_gpio_direction_out,
4653 .set = rt5677_gpio_set,
4654 .direction_input = rt5677_gpio_direction_in,
4655 .get = rt5677_gpio_get,
5e3363ad 4656 .to_irq = rt5677_to_irq,
44caf764
OC		 4657 .can_sleep = 1,
4658};
4659
4660static void rt5677_init_gpio(struct i2c_client *i2c)
4661{
4662 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4663 int ret;
4664
4665 rt5677->gpio_chip = rt5677_template_chip;
4666 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
58383c78 4667 rt5677->gpio_chip.parent = &i2c->dev;
44caf764
OC		 4668 rt5677->gpio_chip.base = -1;
4669
14900363 4670 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
44caf764
OC		 4671 if (ret != 0)
4672 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4673}
4674
4675static void rt5677_free_gpio(struct i2c_client *i2c)
4676{
4677 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
44caf764 4678
5d5e63af 4679 gpiochip_remove(&rt5677->gpio_chip);
44caf764
OC		 4680}
4681#else
45b6e1d3
AP		 4682static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4683 int value)
4684{
4685}
4686
44caf764
OC		 4687static void rt5677_init_gpio(struct i2c_client *i2c)
4688{
4689}
4690
4691static void rt5677_free_gpio(struct i2c_client *i2c)
4692{
4693}
4694#endif
4695
79223bf1 4696static int rt5677_probe(struct snd_soc_component *component)
0e826e86 4697{
79223bf1
KM		 4698 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
4699 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
40eb90a1 4700 int i;
0e826e86 4701
79223bf1 4702 rt5677->component = component;
0e826e86 4703
2d15d974 4704 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
6b43c2eb 4705 snd_soc_dapm_add_routes(dapm,
2d15d974
BL		 4706 rt5677_dmic2_clk_2,
4707 ARRAY_SIZE(rt5677_dmic2_clk_2));
4708 } else { /*use dmic1 clock by default*/
6b43c2eb 4709 snd_soc_dapm_add_routes(dapm,
2d15d974
BL		 4710 rt5677_dmic2_clk_1,
4711 ARRAY_SIZE(rt5677_dmic2_clk_1));
4712 }
4713
79223bf1 4714 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
0e826e86
OC		 4715
4716 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4717 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4718
40eb90a1
AP		 4719 for (i = 0; i < RT5677_GPIO_NUM; i++)
4720 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4721
5e3363ad
OC		 4722 if (rt5677->irq_data) {
4723 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4724 0x8000);
4725 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4726 0x0008);
4727
4728 if (rt5677->pdata.jd1_gpio)
4729 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4730 RT5677_SEL_GPIO_JD1_MASK,
4731 rt5677->pdata.jd1_gpio <<
4732 RT5677_SEL_GPIO_JD1_SFT);
4733
4734 if (rt5677->pdata.jd2_gpio)
4735 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4736 RT5677_SEL_GPIO_JD2_MASK,
4737 rt5677->pdata.jd2_gpio <<
4738 RT5677_SEL_GPIO_JD2_SFT);
4739
4740 if (rt5677->pdata.jd3_gpio)
4741 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4742 RT5677_SEL_GPIO_JD3_MASK,
4743 rt5677->pdata.jd3_gpio <<
4744 RT5677_SEL_GPIO_JD3_SFT);
4745 }
4746
af48f1d0 4747 mutex_init(&rt5677->dsp_cmd_lock);
6fe17da0 4748 mutex_init(&rt5677->dsp_pri_lock);
af48f1d0 4749
0e826e86
OC		 4750 return 0;
4751}
4752
79223bf1 4753static void rt5677_remove(struct snd_soc_component *component)
0e826e86 4754{
79223bf1 4755 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86
OC		 4756
4757 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
f285f161 4758 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
cdab0d4e 4759 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
0e826e86
OC		 4760}
4761
4762#ifdef CONFIG_PM
79223bf1 4763static int rt5677_suspend(struct snd_soc_component *component)
0e826e86 4764{
79223bf1 4765 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86 4766
af48f1d0
OC		 4767 if (!rt5677->dsp_vad_en) {
4768 regcache_cache_only(rt5677->regmap, true);
4769 regcache_mark_dirty(rt5677->regmap);
af48f1d0 4770
f285f161 4771 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
cdab0d4e 4772 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
cbca4076 4773 }
0e826e86
OC		 4774
4775 return 0;
4776}
4777
79223bf1 4778static int rt5677_resume(struct snd_soc_component *component)
0e826e86 4779{
79223bf1 4780 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
0e826e86 4781
af48f1d0 4782 if (!rt5677->dsp_vad_en) {
1aa844cd
BZ		 4783 rt5677->pll_src = 0;
4784 rt5677->pll_in = 0;
4785 rt5677->pll_out = 0;
f285f161 4786 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
cdab0d4e 4787 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
efd901ee 4788 if (rt5677->pow_ldo2 || rt5677->reset_pin)
cbca4076 4789 msleep(10);
cbca4076 4790
af48f1d0
OC		 4791 regcache_cache_only(rt5677->regmap, false);
4792 regcache_sync(rt5677->regmap);
4793 }
0e826e86
OC		 4794
4795 return 0;
4796}
4797#else
4798#define rt5677_suspend NULL
4799#define rt5677_resume NULL
4800#endif
4801
19ba484d
OC		 4802static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4803{
4804 struct i2c_client *client = context;
4805 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4806
6fe17da0
OC		 4807 if (rt5677->is_dsp_mode) {
4808 if (reg > 0xff) {
4809 mutex_lock(&rt5677->dsp_pri_lock);
4810 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4811 reg & 0xff);
4812 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4813 mutex_unlock(&rt5677->dsp_pri_lock);
4814 } else {
4815 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4816 }
4817 } else {
19ba484d 4818 regmap_read(rt5677->regmap_physical, reg, val);
6fe17da0 4819 }
19ba484d
OC		 4820
4821 return 0;
4822}
4823
4824static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4825{
4826 struct i2c_client *client = context;
4827 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4828
6fe17da0
OC		 4829 if (rt5677->is_dsp_mode) {
4830 if (reg > 0xff) {
4831 mutex_lock(&rt5677->dsp_pri_lock);
4832 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4833 reg & 0xff);
4834 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4835 val);
4836 mutex_unlock(&rt5677->dsp_pri_lock);
4837 } else {
4838 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4839 }
4840 } else {
19ba484d 4841 regmap_write(rt5677->regmap_physical, reg, val);
6fe17da0 4842 }
19ba484d
OC		 4843
4844 return 0;
4845}
4846
0e826e86
OC		 4847#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4848#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4849 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4850
64793047 4851static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
0e826e86
OC		 4852 .hw_params = rt5677_hw_params,
4853 .set_fmt = rt5677_set_dai_fmt,
4854 .set_sysclk = rt5677_set_dai_sysclk,
4855 .set_pll = rt5677_set_dai_pll,
48561afe 4856 .set_tdm_slot = rt5677_set_tdm_slot,
0e826e86
OC		 4857};
4858
4859static struct snd_soc_dai_driver rt5677_dai[] = {
4860 {
4861 .name = "rt5677-aif1",
4862 .id = RT5677_AIF1,
4863 .playback = {
4864 .stream_name = "AIF1 Playback",
4865 .channels_min = 1,
4866 .channels_max = 2,
4867 .rates = RT5677_STEREO_RATES,
4868 .formats = RT5677_FORMATS,
4869 },
4870 .capture = {
4871 .stream_name = "AIF1 Capture",
4872 .channels_min = 1,
4873 .channels_max = 2,
4874 .rates = RT5677_STEREO_RATES,
4875 .formats = RT5677_FORMATS,
4876 },
4877 .ops = &rt5677_aif_dai_ops,
4878 },
4879 {
4880 .name = "rt5677-aif2",
4881 .id = RT5677_AIF2,
4882 .playback = {
4883 .stream_name = "AIF2 Playback",
4884 .channels_min = 1,
4885 .channels_max = 2,
4886 .rates = RT5677_STEREO_RATES,
4887 .formats = RT5677_FORMATS,
4888 },
4889 .capture = {
4890 .stream_name = "AIF2 Capture",
4891 .channels_min = 1,
4892 .channels_max = 2,
4893 .rates = RT5677_STEREO_RATES,
4894 .formats = RT5677_FORMATS,
4895 },
4896 .ops = &rt5677_aif_dai_ops,
4897 },
4898 {
4899 .name = "rt5677-aif3",
4900 .id = RT5677_AIF3,
4901 .playback = {
4902 .stream_name = "AIF3 Playback",
4903 .channels_min = 1,
4904 .channels_max = 2,
4905 .rates = RT5677_STEREO_RATES,
4906 .formats = RT5677_FORMATS,
4907 },
4908 .capture = {
4909 .stream_name = "AIF3 Capture",
4910 .channels_min = 1,
4911 .channels_max = 2,
4912 .rates = RT5677_STEREO_RATES,
4913 .formats = RT5677_FORMATS,
4914 },
4915 .ops = &rt5677_aif_dai_ops,
4916 },
4917 {
4918 .name = "rt5677-aif4",
4919 .id = RT5677_AIF4,
4920 .playback = {
4921 .stream_name = "AIF4 Playback",
4922 .channels_min = 1,
4923 .channels_max = 2,
4924 .rates = RT5677_STEREO_RATES,
4925 .formats = RT5677_FORMATS,
4926 },
4927 .capture = {
4928 .stream_name = "AIF4 Capture",
4929 .channels_min = 1,
4930 .channels_max = 2,
4931 .rates = RT5677_STEREO_RATES,
4932 .formats = RT5677_FORMATS,
4933 },
4934 .ops = &rt5677_aif_dai_ops,
4935 },
4936 {
4937 .name = "rt5677-slimbus",
4938 .id = RT5677_AIF5,
4939 .playback = {
4940 .stream_name = "SLIMBus Playback",
4941 .channels_min = 1,
4942 .channels_max = 2,
4943 .rates = RT5677_STEREO_RATES,
4944 .formats = RT5677_FORMATS,
4945 },
4946 .capture = {
4947 .stream_name = "SLIMBus Capture",
4948 .channels_min = 1,
4949 .channels_max = 2,
4950 .rates = RT5677_STEREO_RATES,
4951 .formats = RT5677_FORMATS,
4952 },
4953 .ops = &rt5677_aif_dai_ops,
4954 },
4955};
4956
79223bf1
KM		 4957static const struct snd_soc_component_driver soc_component_dev_rt5677 = {
4958 .probe = rt5677_probe,
4959 .remove = rt5677_remove,
4960 .suspend = rt5677_suspend,
4961 .resume = rt5677_resume,
4962 .set_bias_level = rt5677_set_bias_level,
4963 .controls = rt5677_snd_controls,
4964 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4965 .dapm_widgets = rt5677_dapm_widgets,
4966 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4967 .dapm_routes = rt5677_dapm_routes,
4968 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4969 .use_pmdown_time = 1,
4970 .endianness = 1,
4971 .non_legacy_dai_naming = 1,
0e826e86
OC		 4972};
4973
19ba484d
OC		 4974static const struct regmap_config rt5677_regmap_physical = {
4975 .name = "physical",
4976 .reg_bits = 8,
4977 .val_bits = 16,
4978
6fe17da0
OC		 4979 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4980 RT5677_PR_SPACING),
19ba484d
OC		 4981 .readable_reg = rt5677_readable_register,
4982
4983 .cache_type = REGCACHE_NONE,
6fe17da0
OC		 4984 .ranges = rt5677_ranges,
4985 .num_ranges = ARRAY_SIZE(rt5677_ranges),
19ba484d
OC		 4986};
4987
0e826e86
OC		 4988static const struct regmap_config rt5677_regmap = {
4989 .reg_bits = 8,
4990 .val_bits = 16,
4991
4992 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4993 RT5677_PR_SPACING),
4994
4995 .volatile_reg = rt5677_volatile_register,
4996 .readable_reg = rt5677_readable_register,
19ba484d
OC		 4997 .reg_read = rt5677_read,
4998 .reg_write = rt5677_write,
0e826e86
OC		 4999
5000 .cache_type = REGCACHE_RBTREE,
5001 .reg_defaults = rt5677_reg,
5002 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5003 .ranges = rt5677_ranges,
5004 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5005};
5006
7b87463e 5007static const struct of_device_id rt5677_of_match[] = {
f861e3e2 5008 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 },
7b87463e
JMC		 5009 { }
5010};
5011MODULE_DEVICE_TABLE(of, rt5677_of_match);
5012
a36afb0a
AS		 5013static const struct acpi_device_id rt5677_acpi_match[] = {
5014 { "RT5677CE", RT5677 },
5015 { }
5016};
5017MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match);
a36afb0a 5018
89128534
JK		 5019static void rt5677_read_acpi_properties(struct rt5677_priv *rt5677,
5020 struct device *dev)
5021{
89128534
JK		 5022 u32 val;
5023
89128534
JK		 5024 if (!device_property_read_u32(dev, "DCLK", &val))
5025 rt5677->pdata.dmic2_clk_pin = val;
5026
5027 rt5677->pdata.in1_diff = device_property_read_bool(dev, "IN1");
5028 rt5677->pdata.in2_diff = device_property_read_bool(dev, "IN2");
5029 rt5677->pdata.lout1_diff = device_property_read_bool(dev, "OUT1");
5030 rt5677->pdata.lout2_diff = device_property_read_bool(dev, "OUT2");
5031 rt5677->pdata.lout3_diff = device_property_read_bool(dev, "OUT3");
5032
5033 device_property_read_u32(dev, "JD1", &rt5677->pdata.jd1_gpio);
5034 device_property_read_u32(dev, "JD2", &rt5677->pdata.jd2_gpio);
5035 device_property_read_u32(dev, "JD3", &rt5677->pdata.jd3_gpio);
5036}
5037
9bfde721
BZ		 5038static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5039 struct device *dev)
f9f6a592 5040{
9bfde721
BZ		 5041 rt5677->pdata.in1_diff = device_property_read_bool(dev,
5042 "realtek,in1-differential");
5043 rt5677->pdata.in2_diff = device_property_read_bool(dev,
5044 "realtek,in2-differential");
5045 rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5046 "realtek,lout1-differential");
5047 rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5048 "realtek,lout2-differential");
5049 rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5050 "realtek,lout3-differential");
5051
5052 device_property_read_u8_array(dev, "realtek,gpio-config",
5053 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5054
5055 device_property_read_u32(dev, "realtek,jd1-gpio",
5056 &rt5677->pdata.jd1_gpio);
5057 device_property_read_u32(dev, "realtek,jd2-gpio",
5058 &rt5677->pdata.jd2_gpio);
5059 device_property_read_u32(dev, "realtek,jd3-gpio",
5060 &rt5677->pdata.jd3_gpio);
f9f6a592
AP		 5061}
5062
5e3363ad
OC		 5063static struct regmap_irq rt5677_irqs[] = {
5064 [RT5677_IRQ_JD1] = {
5065 .reg_offset = 0,
5066 .mask = RT5677_EN_IRQ_GPIO_JD1,
5067 },
5068 [RT5677_IRQ_JD2] = {
5069 .reg_offset = 0,
5070 .mask = RT5677_EN_IRQ_GPIO_JD2,
5071 },
5072 [RT5677_IRQ_JD3] = {
5073 .reg_offset = 0,
5074 .mask = RT5677_EN_IRQ_GPIO_JD3,
5075 },
5076};
5077
5078static struct regmap_irq_chip rt5677_irq_chip = {
5079 .name = "rt5677",
5080 .irqs = rt5677_irqs,
5081 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5082
5083 .num_regs = 1,
5084 .status_base = RT5677_IRQ_CTRL1,
5085 .mask_base = RT5677_IRQ_CTRL1,
5086 .mask_invert = 1,
5087};
5088
35d40d10 5089static int rt5677_init_irq(struct i2c_client *i2c)
5e3363ad
OC		 5090{
5091 int ret;
5092 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5093
5094 if (!rt5677->pdata.jd1_gpio &&
5095 !rt5677->pdata.jd2_gpio &&
5096 !rt5677->pdata.jd3_gpio)
5097 return 0;
5098
5099 if (!i2c->irq) {
5100 dev_err(&i2c->dev, "No interrupt specified\n");
5101 return -EINVAL;
5102 }
5103
5104 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5105 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5106 &rt5677_irq_chip, &rt5677->irq_data);
5107
5108 if (ret != 0) {
5109 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5110 return ret;
5111 }
5112
5113 return 0;
5114}
5115
35d40d10 5116static void rt5677_free_irq(struct i2c_client *i2c)
5e3363ad
OC		 5117{
5118 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5119
5120 if (rt5677->irq_data)
5121 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5122}
5123
3a4f4f29 5124static int rt5677_i2c_probe(struct i2c_client *i2c)
0e826e86 5125{
0e826e86
OC		 5126 struct rt5677_priv *rt5677;
5127 int ret;
5128 unsigned int val;
5129
5130 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5131 GFP_KERNEL);
5132 if (rt5677 == NULL)
5133 return -ENOMEM;
5134
5135 i2c_set_clientdata(i2c, rt5677);
5136
ddc9e69b
AS		 5137 if (i2c->dev.of_node) {
5138 const struct of_device_id *match_id;
5139
5140 match_id = of_match_device(rt5677_of_match, &i2c->dev);
5141 if (match_id)
5142 rt5677->type = (enum rt5677_type)match_id->data;
ab1f7095 5143
9bfde721 5144 rt5677_read_device_properties(rt5677, &i2c->dev);
ddc9e69b
AS		 5145 } else if (ACPI_HANDLE(&i2c->dev)) {
5146 const struct acpi_device_id *acpi_id;
5147
5148 acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev);
5149 if (acpi_id)
5150 rt5677->type = (enum rt5677_type)acpi_id->driver_data;
5151
89128534 5152 rt5677_read_acpi_properties(rt5677, &i2c->dev);
ddc9e69b 5153 } else {
89128534 5154 return -EINVAL;
ddc9e69b 5155 }
0e826e86 5156
efd901ee
BZ		 5157 /* pow-ldo2 and reset are optional. The codec pins may be statically
5158 * connected on the board without gpios. If the gpio device property
5159 * isn't specified, devm_gpiod_get_optional returns NULL.
5160 */
5161 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5162 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5163 if (IS_ERR(rt5677->pow_ldo2)) {
5164 ret = PTR_ERR(rt5677->pow_ldo2);
5165 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
f8163c86 5166 return ret;
b3b10e99 5167 }
efd901ee 5168 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
cdab0d4e 5169 "realtek,reset", GPIOD_OUT_LOW);
efd901ee
BZ		 5170 if (IS_ERR(rt5677->reset_pin)) {
5171 ret = PTR_ERR(rt5677->reset_pin);
5172 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
f8163c86 5173 return ret;
b3b10e99
AP		 5174 }
5175
efd901ee 5176 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
f9f6a592
AP		 5177 /* Wait a while until I2C bus becomes available. The datasheet
5178 * does not specify the exact we should wait but startup
5179 * sequence mentiones at least a few milliseconds.
5180 */
5181 msleep(10);
5182 }
5183
19ba484d
OC		 5184 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5185 &rt5677_regmap_physical);
5186 if (IS_ERR(rt5677->regmap_physical)) {
5187 ret = PTR_ERR(rt5677->regmap_physical);
5188 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5189 ret);
5190 return ret;
5191 }
5192
5193 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
0e826e86
OC		 5194 if (IS_ERR(rt5677->regmap)) {
5195 ret = PTR_ERR(rt5677->regmap);
5196 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5197 ret);
5198 return ret;
5199 }
5200
5201 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5202 if (val != RT5677_DEVICE_ID) {
5203 dev_err(&i2c->dev,
aa0bcc5c 5204 "Device with ID register %#x is not rt5677\n", val);
0e826e86
OC		 5205 return -ENODEV;
5206 }
5207
5208 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5209
5210 ret = regmap_register_patch(rt5677->regmap, init_list,
5211 ARRAY_SIZE(init_list));
5212 if (ret != 0)
5213 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5214
5215 if (rt5677->pdata.in1_diff)
5216 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5217 RT5677_IN_DF1, RT5677_IN_DF1);
5218
5219 if (rt5677->pdata.in2_diff)
5220 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5221 RT5677_IN_DF2, RT5677_IN_DF2);
5222
6f67c380
AP		 5223 if (rt5677->pdata.lout1_diff)
5224 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5225 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5226
5227 if (rt5677->pdata.lout2_diff)
5228 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5229 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5230
5231 if (rt5677->pdata.lout3_diff)
5232 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5233 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5234
2d15d974
BL		 5235 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5236 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5237 RT5677_GPIO5_FUNC_MASK,
5238 RT5677_GPIO5_FUNC_DMIC);
5239 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5240 RT5677_GPIO5_DIR_MASK,
5241 RT5677_GPIO5_DIR_OUT);
5242 }
5243
277880a3
OC		 5244 if (rt5677->pdata.micbias1_vdd_3v3)
5245 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5246 RT5677_MICBIAS1_CTRL_VDD_MASK,
5247 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5248
44caf764 5249 rt5677_init_gpio(i2c);
35d40d10 5250 rt5677_init_irq(i2c);
44caf764 5251
79223bf1
KM		 5252 return devm_snd_soc_register_component(&i2c->dev,
5253 &soc_component_dev_rt5677,
d0bdcb91 5254 rt5677_dai, ARRAY_SIZE(rt5677_dai));
0e826e86
OC		 5255}
5256
5257static int rt5677_i2c_remove(struct i2c_client *i2c)
5258{
35d40d10 5259 rt5677_free_irq(i2c);
44caf764 5260 rt5677_free_gpio(i2c);
0e826e86
OC		 5261
5262 return 0;
5263}
5264
5265static struct i2c_driver rt5677_i2c_driver = {
5266 .driver = {
5267 .name = "rt5677",
7b87463e 5268 .of_match_table = rt5677_of_match,
a36afb0a 5269 .acpi_match_table = ACPI_PTR(rt5677_acpi_match),
0e826e86 5270 },
3a4f4f29 5271 .probe_new = rt5677_i2c_probe,
0e826e86 5272 .remove = rt5677_i2c_remove,
0e826e86 5273};
c8cfbec8 5274module_i2c_driver(rt5677_i2c_driver);
0e826e86
OC		 5275
5276MODULE_DESCRIPTION("ASoC RT5677 driver");
5277MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5278MODULE_LICENSE("GPL v2");
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