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ASoC: rt5677: Remove NULL test for desc before gpiod_set_value_cansleep call
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / rt5677.c
CommitLineData
0e826e86
OC		 1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/spi/spi.h>
af48f1d0 22#include <linux/firmware.h>
9bfde721 23#include <linux/property.h>
0e826e86
OC		 24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
30f14b43 32#include "rl6231.h"
0e826e86 33#include "rt5677.h"
af48f1d0 34#include "rt5677-spi.h"
0e826e86
OC		 35
36#define RT5677_DEVICE_ID 0x6327
37
38#define RT5677_PR_RANGE_BASE (0xff + 1)
39#define RT5677_PR_SPACING 0x100
40
41#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
42
43static const struct regmap_range_cfg rt5677_ranges[] = {
44 {
45 .name = "PR",
46 .range_min = RT5677_PR_BASE,
47 .range_max = RT5677_PR_BASE + 0xfd,
48 .selector_reg = RT5677_PRIV_INDEX,
49 .selector_mask = 0xff,
50 .selector_shift = 0x0,
51 .window_start = RT5677_PRIV_DATA,
52 .window_len = 0x1,
53 },
54};
55
56static const struct reg_default init_list[] = {
2dfe2b08
OC		 57 {RT5677_ASRC_12, 0x0018},
58 {RT5677_PR_BASE + 0x3d, 0x364d},
59 {RT5677_PR_BASE + 0x17, 0x4fc0},
60 {RT5677_PR_BASE + 0x13, 0x0312},
61 {RT5677_PR_BASE + 0x1e, 0x0000},
62 {RT5677_PR_BASE + 0x12, 0x0eaa},
63 {RT5677_PR_BASE + 0x14, 0x018a},
74d6ea52
BL		 64 {RT5677_PR_BASE + 0x15, 0x0490},
65 {RT5677_PR_BASE + 0x38, 0x0f71},
66 {RT5677_PR_BASE + 0x39, 0x0f71},
0e826e86
OC		 67};
68#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
69
70static const struct reg_default rt5677_reg[] = {
71 {RT5677_RESET , 0x0000},
72 {RT5677_LOUT1 , 0xa800},
73 {RT5677_IN1 , 0x0000},
74 {RT5677_MICBIAS , 0x0000},
75 {RT5677_SLIMBUS_PARAM , 0x0000},
76 {RT5677_SLIMBUS_RX , 0x0000},
77 {RT5677_SLIMBUS_CTRL , 0x0000},
78 {RT5677_SIDETONE_CTRL , 0x000b},
79 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
80 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
81 {RT5677_DAC4_DIG_VOL , 0xafaf},
82 {RT5677_DAC3_DIG_VOL , 0xafaf},
83 {RT5677_DAC1_DIG_VOL , 0xafaf},
84 {RT5677_DAC2_DIG_VOL , 0xafaf},
85 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
86 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_STO1_2_ADC_BST , 0x0000},
89 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_ADC_BST_CTRL2 , 0x0000},
91 {RT5677_STO3_4_ADC_BST , 0x0000},
92 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
93 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
94 {RT5677_STO4_ADC_MIXER , 0xd4c0},
95 {RT5677_STO3_ADC_MIXER , 0xd4c0},
96 {RT5677_STO2_ADC_MIXER , 0xd4c0},
97 {RT5677_STO1_ADC_MIXER , 0xd4c0},
98 {RT5677_MONO_ADC_MIXER , 0xd4d1},
99 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
100 {RT5677_STO1_DAC_MIXER , 0xaaaa},
101 {RT5677_MONO_DAC_MIXER , 0xaaaa},
102 {RT5677_DD1_MIXER , 0xaaaa},
103 {RT5677_DD2_MIXER , 0xaaaa},
104 {RT5677_IF3_DATA , 0x0000},
105 {RT5677_IF4_DATA , 0x0000},
106 {RT5677_PDM_OUT_CTRL , 0x8888},
107 {RT5677_PDM_DATA_CTRL1 , 0x0000},
108 {RT5677_PDM_DATA_CTRL2 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
111 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
113 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
114 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
115 {RT5677_TDM1_CTRL1 , 0x0300},
116 {RT5677_TDM1_CTRL2 , 0x0000},
117 {RT5677_TDM1_CTRL3 , 0x4000},
118 {RT5677_TDM1_CTRL4 , 0x0123},
119 {RT5677_TDM1_CTRL5 , 0x4567},
120 {RT5677_TDM2_CTRL1 , 0x0300},
121 {RT5677_TDM2_CTRL2 , 0x0000},
122 {RT5677_TDM2_CTRL3 , 0x4000},
123 {RT5677_TDM2_CTRL4 , 0x0123},
124 {RT5677_TDM2_CTRL5 , 0x4567},
125 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
126 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
132 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
133 {RT5677_DMIC_CTRL1 , 0x1505},
134 {RT5677_DMIC_CTRL2 , 0x0055},
135 {RT5677_HAP_GENE_CTRL1 , 0x0111},
136 {RT5677_HAP_GENE_CTRL2 , 0x0064},
137 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
142 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
143 {RT5677_HAP_GENE_CTRL9 , 0xf000},
144 {RT5677_HAP_GENE_CTRL10 , 0x0000},
145 {RT5677_PWR_DIG1 , 0x0000},
146 {RT5677_PWR_DIG2 , 0x0000},
147 {RT5677_PWR_ANLG1 , 0x0055},
148 {RT5677_PWR_ANLG2 , 0x0000},
149 {RT5677_PWR_DSP1 , 0x0001},
150 {RT5677_PWR_DSP_ST , 0x0000},
151 {RT5677_PWR_DSP2 , 0x0000},
152 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
153 {RT5677_PRIV_INDEX , 0x0000},
154 {RT5677_PRIV_DATA , 0x0000},
155 {RT5677_I2S4_SDP , 0x8000},
156 {RT5677_I2S1_SDP , 0x8000},
157 {RT5677_I2S2_SDP , 0x8000},
158 {RT5677_I2S3_SDP , 0x8000},
159 {RT5677_CLK_TREE_CTRL1 , 0x1111},
160 {RT5677_CLK_TREE_CTRL2 , 0x1111},
161 {RT5677_CLK_TREE_CTRL3 , 0x0000},
162 {RT5677_PLL1_CTRL1 , 0x0000},
163 {RT5677_PLL1_CTRL2 , 0x0000},
164 {RT5677_PLL2_CTRL1 , 0x0c60},
165 {RT5677_PLL2_CTRL2 , 0x2000},
166 {RT5677_GLB_CLK1 , 0x0000},
167 {RT5677_GLB_CLK2 , 0x0000},
168 {RT5677_ASRC_1 , 0x0000},
169 {RT5677_ASRC_2 , 0x0000},
170 {RT5677_ASRC_3 , 0x0000},
171 {RT5677_ASRC_4 , 0x0000},
172 {RT5677_ASRC_5 , 0x0000},
173 {RT5677_ASRC_6 , 0x0000},
174 {RT5677_ASRC_7 , 0x0000},
175 {RT5677_ASRC_8 , 0x0000},
176 {RT5677_ASRC_9 , 0x0000},
177 {RT5677_ASRC_10 , 0x0000},
178 {RT5677_ASRC_11 , 0x0000},
86ae04b1 179 {RT5677_ASRC_12 , 0x0018},
0e826e86
OC		 180 {RT5677_ASRC_13 , 0x0000},
181 {RT5677_ASRC_14 , 0x0000},
182 {RT5677_ASRC_15 , 0x0000},
183 {RT5677_ASRC_16 , 0x0000},
184 {RT5677_ASRC_17 , 0x0000},
185 {RT5677_ASRC_18 , 0x0000},
186 {RT5677_ASRC_19 , 0x0000},
187 {RT5677_ASRC_20 , 0x0000},
188 {RT5677_ASRC_21 , 0x000c},
189 {RT5677_ASRC_22 , 0x0000},
190 {RT5677_ASRC_23 , 0x0000},
191 {RT5677_VAD_CTRL1 , 0x2184},
192 {RT5677_VAD_CTRL2 , 0x010a},
193 {RT5677_VAD_CTRL3 , 0x0aea},
194 {RT5677_VAD_CTRL4 , 0x000c},
195 {RT5677_VAD_CTRL5 , 0x0000},
196 {RT5677_DSP_INB_CTRL1 , 0x0000},
197 {RT5677_DSP_INB_CTRL2 , 0x0000},
198 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
199 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
201 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
202 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
203 {RT5677_ADC_EQ_CTRL1 , 0x6000},
204 {RT5677_ADC_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL1 , 0xc000},
206 {RT5677_EQ_CTRL2 , 0x0000},
207 {RT5677_EQ_CTRL3 , 0x0000},
208 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
209 {RT5677_JD_CTRL1 , 0x0000},
210 {RT5677_JD_CTRL2 , 0x0000},
211 {RT5677_JD_CTRL3 , 0x0000},
212 {RT5677_IRQ_CTRL1 , 0x0000},
213 {RT5677_IRQ_CTRL2 , 0x0000},
214 {RT5677_GPIO_ST , 0x0000},
215 {RT5677_GPIO_CTRL1 , 0x0000},
216 {RT5677_GPIO_CTRL2 , 0x0000},
217 {RT5677_GPIO_CTRL3 , 0x0000},
218 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
219 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
227 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
228 {RT5677_MB_DRC_CTRL1 , 0x0f20},
229 {RT5677_DRC1_CTRL1 , 0x001f},
230 {RT5677_DRC1_CTRL2 , 0x020c},
231 {RT5677_DRC1_CTRL3 , 0x1f00},
232 {RT5677_DRC1_CTRL4 , 0x0000},
233 {RT5677_DRC1_CTRL5 , 0x0000},
234 {RT5677_DRC1_CTRL6 , 0x0029},
235 {RT5677_DRC2_CTRL1 , 0x001f},
236 {RT5677_DRC2_CTRL2 , 0x020c},
237 {RT5677_DRC2_CTRL3 , 0x1f00},
238 {RT5677_DRC2_CTRL4 , 0x0000},
239 {RT5677_DRC2_CTRL5 , 0x0000},
240 {RT5677_DRC2_CTRL6 , 0x0029},
241 {RT5677_DRC1_HL_CTRL1 , 0x8000},
242 {RT5677_DRC1_HL_CTRL2 , 0x0200},
243 {RT5677_DRC2_HL_CTRL1 , 0x8000},
244 {RT5677_DRC2_HL_CTRL2 , 0x0200},
245 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
246 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
247 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
248 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
249 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
250 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
251 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
252 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
253 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
254 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
255 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
256 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
257 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
258 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
259 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
260 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
261 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
262 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
263 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
264 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
265 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
266 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
267 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
268 {RT5677_DIG_MISC , 0x0000},
269 {RT5677_GEN_CTRL1 , 0x0000},
270 {RT5677_GEN_CTRL2 , 0x0000},
271 {RT5677_VENDOR_ID , 0x0000},
272 {RT5677_VENDOR_ID1 , 0x10ec},
273 {RT5677_VENDOR_ID2 , 0x6327},
274};
275
276static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
277{
278 int i;
279
280 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
281 if (reg >= rt5677_ranges[i].range_min &&
282 reg <= rt5677_ranges[i].range_max) {
283 return true;
284 }
285 }
286
287 switch (reg) {
288 case RT5677_RESET:
289 case RT5677_SLIMBUS_PARAM:
290 case RT5677_PDM_DATA_CTRL1:
291 case RT5677_PDM_DATA_CTRL2:
292 case RT5677_PDM1_DATA_CTRL4:
293 case RT5677_PDM2_DATA_CTRL4:
294 case RT5677_I2C_MASTER_CTRL1:
295 case RT5677_I2C_MASTER_CTRL7:
296 case RT5677_I2C_MASTER_CTRL8:
297 case RT5677_HAP_GENE_CTRL2:
298 case RT5677_PWR_DSP_ST:
299 case RT5677_PRIV_DATA:
300 case RT5677_PLL1_CTRL2:
301 case RT5677_PLL2_CTRL2:
302 case RT5677_ASRC_22:
303 case RT5677_ASRC_23:
304 case RT5677_VAD_CTRL5:
305 case RT5677_ADC_EQ_CTRL1:
306 case RT5677_EQ_CTRL1:
307 case RT5677_IRQ_CTRL1:
308 case RT5677_IRQ_CTRL2:
309 case RT5677_GPIO_ST:
310 case RT5677_DSP_INB1_SRC_CTRL4:
311 case RT5677_DSP_INB2_SRC_CTRL4:
312 case RT5677_DSP_INB3_SRC_CTRL4:
313 case RT5677_DSP_OUTB1_SRC_CTRL4:
314 case RT5677_DSP_OUTB2_SRC_CTRL4:
315 case RT5677_VENDOR_ID:
316 case RT5677_VENDOR_ID1:
317 case RT5677_VENDOR_ID2:
318 return true;
319 default:
320 return false;
321 }
322}
323
324static bool rt5677_readable_register(struct device *dev, unsigned int reg)
325{
326 int i;
327
328 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
329 if (reg >= rt5677_ranges[i].range_min &&
330 reg <= rt5677_ranges[i].range_max) {
331 return true;
332 }
333 }
334
335 switch (reg) {
336 case RT5677_RESET:
337 case RT5677_LOUT1:
338 case RT5677_IN1:
339 case RT5677_MICBIAS:
340 case RT5677_SLIMBUS_PARAM:
341 case RT5677_SLIMBUS_RX:
342 case RT5677_SLIMBUS_CTRL:
343 case RT5677_SIDETONE_CTRL:
344 case RT5677_ANA_DAC1_2_3_SRC:
345 case RT5677_IF_DSP_DAC3_4_MIXER:
346 case RT5677_DAC4_DIG_VOL:
347 case RT5677_DAC3_DIG_VOL:
348 case RT5677_DAC1_DIG_VOL:
349 case RT5677_DAC2_DIG_VOL:
350 case RT5677_IF_DSP_DAC2_MIXER:
351 case RT5677_STO1_ADC_DIG_VOL:
352 case RT5677_MONO_ADC_DIG_VOL:
353 case RT5677_STO1_2_ADC_BST:
354 case RT5677_STO2_ADC_DIG_VOL:
355 case RT5677_ADC_BST_CTRL2:
356 case RT5677_STO3_4_ADC_BST:
357 case RT5677_STO3_ADC_DIG_VOL:
358 case RT5677_STO4_ADC_DIG_VOL:
359 case RT5677_STO4_ADC_MIXER:
360 case RT5677_STO3_ADC_MIXER:
361 case RT5677_STO2_ADC_MIXER:
362 case RT5677_STO1_ADC_MIXER:
363 case RT5677_MONO_ADC_MIXER:
364 case RT5677_ADC_IF_DSP_DAC1_MIXER:
365 case RT5677_STO1_DAC_MIXER:
366 case RT5677_MONO_DAC_MIXER:
367 case RT5677_DD1_MIXER:
368 case RT5677_DD2_MIXER:
369 case RT5677_IF3_DATA:
370 case RT5677_IF4_DATA:
371 case RT5677_PDM_OUT_CTRL:
372 case RT5677_PDM_DATA_CTRL1:
373 case RT5677_PDM_DATA_CTRL2:
374 case RT5677_PDM1_DATA_CTRL2:
375 case RT5677_PDM1_DATA_CTRL3:
376 case RT5677_PDM1_DATA_CTRL4:
377 case RT5677_PDM2_DATA_CTRL2:
378 case RT5677_PDM2_DATA_CTRL3:
379 case RT5677_PDM2_DATA_CTRL4:
380 case RT5677_TDM1_CTRL1:
381 case RT5677_TDM1_CTRL2:
382 case RT5677_TDM1_CTRL3:
383 case RT5677_TDM1_CTRL4:
384 case RT5677_TDM1_CTRL5:
385 case RT5677_TDM2_CTRL1:
386 case RT5677_TDM2_CTRL2:
387 case RT5677_TDM2_CTRL3:
388 case RT5677_TDM2_CTRL4:
389 case RT5677_TDM2_CTRL5:
390 case RT5677_I2C_MASTER_CTRL1:
391 case RT5677_I2C_MASTER_CTRL2:
392 case RT5677_I2C_MASTER_CTRL3:
393 case RT5677_I2C_MASTER_CTRL4:
394 case RT5677_I2C_MASTER_CTRL5:
395 case RT5677_I2C_MASTER_CTRL6:
396 case RT5677_I2C_MASTER_CTRL7:
397 case RT5677_I2C_MASTER_CTRL8:
398 case RT5677_DMIC_CTRL1:
399 case RT5677_DMIC_CTRL2:
400 case RT5677_HAP_GENE_CTRL1:
401 case RT5677_HAP_GENE_CTRL2:
402 case RT5677_HAP_GENE_CTRL3:
403 case RT5677_HAP_GENE_CTRL4:
404 case RT5677_HAP_GENE_CTRL5:
405 case RT5677_HAP_GENE_CTRL6:
406 case RT5677_HAP_GENE_CTRL7:
407 case RT5677_HAP_GENE_CTRL8:
408 case RT5677_HAP_GENE_CTRL9:
409 case RT5677_HAP_GENE_CTRL10:
410 case RT5677_PWR_DIG1:
411 case RT5677_PWR_DIG2:
412 case RT5677_PWR_ANLG1:
413 case RT5677_PWR_ANLG2:
414 case RT5677_PWR_DSP1:
415 case RT5677_PWR_DSP_ST:
416 case RT5677_PWR_DSP2:
417 case RT5677_ADC_DAC_HPF_CTRL1:
418 case RT5677_PRIV_INDEX:
419 case RT5677_PRIV_DATA:
420 case RT5677_I2S4_SDP:
421 case RT5677_I2S1_SDP:
422 case RT5677_I2S2_SDP:
423 case RT5677_I2S3_SDP:
424 case RT5677_CLK_TREE_CTRL1:
425 case RT5677_CLK_TREE_CTRL2:
426 case RT5677_CLK_TREE_CTRL3:
427 case RT5677_PLL1_CTRL1:
428 case RT5677_PLL1_CTRL2:
429 case RT5677_PLL2_CTRL1:
430 case RT5677_PLL2_CTRL2:
431 case RT5677_GLB_CLK1:
432 case RT5677_GLB_CLK2:
433 case RT5677_ASRC_1:
434 case RT5677_ASRC_2:
435 case RT5677_ASRC_3:
436 case RT5677_ASRC_4:
437 case RT5677_ASRC_5:
438 case RT5677_ASRC_6:
439 case RT5677_ASRC_7:
440 case RT5677_ASRC_8:
441 case RT5677_ASRC_9:
442 case RT5677_ASRC_10:
443 case RT5677_ASRC_11:
444 case RT5677_ASRC_12:
445 case RT5677_ASRC_13:
446 case RT5677_ASRC_14:
447 case RT5677_ASRC_15:
448 case RT5677_ASRC_16:
449 case RT5677_ASRC_17:
450 case RT5677_ASRC_18:
451 case RT5677_ASRC_19:
452 case RT5677_ASRC_20:
453 case RT5677_ASRC_21:
454 case RT5677_ASRC_22:
455 case RT5677_ASRC_23:
456 case RT5677_VAD_CTRL1:
457 case RT5677_VAD_CTRL2:
458 case RT5677_VAD_CTRL3:
459 case RT5677_VAD_CTRL4:
460 case RT5677_VAD_CTRL5:
461 case RT5677_DSP_INB_CTRL1:
462 case RT5677_DSP_INB_CTRL2:
463 case RT5677_DSP_IN_OUTB_CTRL:
464 case RT5677_DSP_OUTB0_1_DIG_VOL:
465 case RT5677_DSP_OUTB2_3_DIG_VOL:
466 case RT5677_DSP_OUTB4_5_DIG_VOL:
467 case RT5677_DSP_OUTB6_7_DIG_VOL:
468 case RT5677_ADC_EQ_CTRL1:
469 case RT5677_ADC_EQ_CTRL2:
470 case RT5677_EQ_CTRL1:
471 case RT5677_EQ_CTRL2:
472 case RT5677_EQ_CTRL3:
473 case RT5677_SOFT_VOL_ZERO_CROSS1:
474 case RT5677_JD_CTRL1:
475 case RT5677_JD_CTRL2:
476 case RT5677_JD_CTRL3:
477 case RT5677_IRQ_CTRL1:
478 case RT5677_IRQ_CTRL2:
479 case RT5677_GPIO_ST:
480 case RT5677_GPIO_CTRL1:
481 case RT5677_GPIO_CTRL2:
482 case RT5677_GPIO_CTRL3:
483 case RT5677_STO1_ADC_HI_FILTER1:
484 case RT5677_STO1_ADC_HI_FILTER2:
485 case RT5677_MONO_ADC_HI_FILTER1:
486 case RT5677_MONO_ADC_HI_FILTER2:
487 case RT5677_STO2_ADC_HI_FILTER1:
488 case RT5677_STO2_ADC_HI_FILTER2:
489 case RT5677_STO3_ADC_HI_FILTER1:
490 case RT5677_STO3_ADC_HI_FILTER2:
491 case RT5677_STO4_ADC_HI_FILTER1:
492 case RT5677_STO4_ADC_HI_FILTER2:
493 case RT5677_MB_DRC_CTRL1:
494 case RT5677_DRC1_CTRL1:
495 case RT5677_DRC1_CTRL2:
496 case RT5677_DRC1_CTRL3:
497 case RT5677_DRC1_CTRL4:
498 case RT5677_DRC1_CTRL5:
499 case RT5677_DRC1_CTRL6:
500 case RT5677_DRC2_CTRL1:
501 case RT5677_DRC2_CTRL2:
502 case RT5677_DRC2_CTRL3:
503 case RT5677_DRC2_CTRL4:
504 case RT5677_DRC2_CTRL5:
505 case RT5677_DRC2_CTRL6:
506 case RT5677_DRC1_HL_CTRL1:
507 case RT5677_DRC1_HL_CTRL2:
508 case RT5677_DRC2_HL_CTRL1:
509 case RT5677_DRC2_HL_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL1:
511 case RT5677_DSP_INB1_SRC_CTRL2:
512 case RT5677_DSP_INB1_SRC_CTRL3:
513 case RT5677_DSP_INB1_SRC_CTRL4:
514 case RT5677_DSP_INB2_SRC_CTRL1:
515 case RT5677_DSP_INB2_SRC_CTRL2:
516 case RT5677_DSP_INB2_SRC_CTRL3:
517 case RT5677_DSP_INB2_SRC_CTRL4:
518 case RT5677_DSP_INB3_SRC_CTRL1:
519 case RT5677_DSP_INB3_SRC_CTRL2:
520 case RT5677_DSP_INB3_SRC_CTRL3:
521 case RT5677_DSP_INB3_SRC_CTRL4:
522 case RT5677_DSP_OUTB1_SRC_CTRL1:
523 case RT5677_DSP_OUTB1_SRC_CTRL2:
524 case RT5677_DSP_OUTB1_SRC_CTRL3:
525 case RT5677_DSP_OUTB1_SRC_CTRL4:
526 case RT5677_DSP_OUTB2_SRC_CTRL1:
527 case RT5677_DSP_OUTB2_SRC_CTRL2:
528 case RT5677_DSP_OUTB2_SRC_CTRL3:
529 case RT5677_DSP_OUTB2_SRC_CTRL4:
530 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
531 case RT5677_DSP_OUTB_45_MIXER_CTRL:
532 case RT5677_DSP_OUTB_67_MIXER_CTRL:
533 case RT5677_DIG_MISC:
534 case RT5677_GEN_CTRL1:
535 case RT5677_GEN_CTRL2:
536 case RT5677_VENDOR_ID:
537 case RT5677_VENDOR_ID1:
538 case RT5677_VENDOR_ID2:
539 return true;
540 default:
541 return false;
542 }
543}
544
af48f1d0
OC		 545/**
546 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
19ba484d 547 * @rt5677: Private Data.
af48f1d0
OC		 548 * @addr: Address index.
549 * @value: Address data.
550 *
551 *
552 * Returns 0 for success or negative error code.
553 */
19ba484d 554static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
af48f1d0
OC		 555 unsigned int addr, unsigned int value, unsigned int opcode)
556{
19ba484d 557 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 558 int ret;
559
560 mutex_lock(&rt5677->dsp_cmd_lock);
561
19ba484d
OC		 562 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
563 addr >> 16);
af48f1d0
OC		 564 if (ret < 0) {
565 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
566 goto err;
567 }
568
19ba484d 569 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 570 addr & 0xffff);
571 if (ret < 0) {
572 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
573 goto err;
574 }
575
19ba484d 576 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
af48f1d0
OC		 577 value >> 16);
578 if (ret < 0) {
579 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
580 goto err;
581 }
582
19ba484d 583 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
af48f1d0
OC		 584 value & 0xffff);
585 if (ret < 0) {
586 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
587 goto err;
588 }
589
19ba484d
OC		 590 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
591 opcode);
af48f1d0
OC		 592 if (ret < 0) {
593 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
594 goto err;
595 }
596
597err:
598 mutex_unlock(&rt5677->dsp_cmd_lock);
599
600 return ret;
601}
602
603/**
604 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
19ba484d 605 * rt5677: Private Data.
af48f1d0
OC		 606 * @addr: Address index.
607 * @value: Address data.
608 *
19ba484d 609 *
af48f1d0
OC		 610 * Returns 0 for success or negative error code.
611 */
612static int rt5677_dsp_mode_i2c_read_addr(
19ba484d 613 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
af48f1d0 614{
19ba484d 615 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 616 int ret;
617 unsigned int msb, lsb;
618
619 mutex_lock(&rt5677->dsp_cmd_lock);
620
19ba484d
OC		 621 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
622 addr >> 16);
af48f1d0
OC		 623 if (ret < 0) {
624 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
625 goto err;
626 }
627
19ba484d 628 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 629 addr & 0xffff);
630 if (ret < 0) {
631 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
632 goto err;
633 }
634
19ba484d
OC		 635 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
636 0x0002);
af48f1d0
OC		 637 if (ret < 0) {
638 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
639 goto err;
640 }
641
19ba484d
OC		 642 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
643 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
af48f1d0
OC		 644 *value = (msb << 16) | lsb;
645
646err:
647 mutex_unlock(&rt5677->dsp_cmd_lock);
648
649 return ret;
650}
651
652/**
653 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
19ba484d 654 * rt5677: Private Data.
af48f1d0
OC		 655 * @reg: Register index.
656 * @value: Register data.
657 *
658 *
659 * Returns 0 for success or negative error code.
660 */
19ba484d 661static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
af48f1d0
OC		 662 unsigned int reg, unsigned int value)
663{
19ba484d 664 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
af48f1d0
OC		 665 value, 0x0001);
666}
667
668/**
669 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
670 * @codec: SoC audio codec device.
671 * @reg: Register index.
19ba484d 672 * @value: Register data.
af48f1d0
OC		 673 *
674 *
19ba484d 675 * Returns 0 for success or negative error code.
af48f1d0 676 */
19ba484d
OC		 677static int rt5677_dsp_mode_i2c_read(
678 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
af48f1d0 679{
19ba484d
OC		 680 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
681 value);
af48f1d0 682
19ba484d 683 *value &= 0xffff;
af48f1d0 684
19ba484d 685 return ret;
af48f1d0
OC		 686}
687
19ba484d 688static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
af48f1d0 689{
19ba484d 690 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
af48f1d0 691
19ba484d
OC		 692 if (on) {
693 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
694 rt5677->is_dsp_mode = true;
695 } else {
696 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
697 rt5677->is_dsp_mode = false;
af48f1d0 698 }
af48f1d0
OC		 699}
700
701static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
702{
703 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
704 static bool activity;
705 int ret;
706
4c121129
AB		 707 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
708 return -ENXIO;
709
af48f1d0
OC		 710 if (on && !activity) {
711 activity = true;
712
713 regcache_cache_only(rt5677->regmap, false);
714 regcache_cache_bypass(rt5677->regmap, true);
715
716 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
717 regmap_update_bits(rt5677->regmap,
718 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
720 RT5677_LDO1_SEL_MASK, 0x0);
721 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
722 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
ab1f7095
OC		 723 switch (rt5677->type) {
724 case RT5677:
725 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
726 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
727 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
728 RT5677_PLL2_PR_SRC_MASK |
729 RT5677_DSP_CLK_SRC_MASK,
730 RT5677_PLL2_PR_SRC_MCLK2 |
731 RT5677_DSP_CLK_SRC_BYPASS);
732 break;
733 case RT5676:
734 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
735 RT5677_DSP_CLK_SRC_MASK,
736 RT5677_DSP_CLK_SRC_BYPASS);
737 break;
738 default:
739 break;
740 }
af48f1d0 741 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
19ba484d
OC		 742 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
743 rt5677_set_dsp_mode(codec, true);
af48f1d0
OC		 744
745 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
746 codec->dev);
747 if (ret == 0) {
748 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
749 release_firmware(rt5677->fw1);
750 }
751
752 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
753 codec->dev);
754 if (ret == 0) {
755 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
756 release_firmware(rt5677->fw2);
757 }
758
19ba484d 759 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
af48f1d0
OC		 760
761 regcache_cache_bypass(rt5677->regmap, false);
762 regcache_cache_only(rt5677->regmap, true);
763 } else if (!on && activity) {
764 activity = false;
765
766 regcache_cache_only(rt5677->regmap, false);
767 regcache_cache_bypass(rt5677->regmap, true);
768
19ba484d
OC		 769 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
770 rt5677_set_dsp_mode(codec, false);
771 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
af48f1d0
OC		 772
773 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
774
775 regcache_cache_bypass(rt5677->regmap, false);
776 regcache_mark_dirty(rt5677->regmap);
777 regcache_sync(rt5677->regmap);
778 }
779
780 return 0;
781}
782
0e826e86 783static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
40e3262e 784static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
0e826e86 785static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
40e3262e 786static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
0e826e86 787static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
90bdbb46 788static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
0e826e86
OC		 789
790/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
791static unsigned int bst_tlv[] = {
792 TLV_DB_RANGE_HEAD(7),
793 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
794 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
795 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
796 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
797 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
798 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
799 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
800};
801
af48f1d0
OC		 802static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
803 struct snd_ctl_elem_value *ucontrol)
804{
6087fcab
FY		 805 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
806 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
af48f1d0
OC		 807
808 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
809
810 return 0;
811}
812
813static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
814 struct snd_ctl_elem_value *ucontrol)
815{
6087fcab
FY		 816 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
817 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
818 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
af48f1d0
OC		 819
820 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
821
6b43c2eb 822 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
af48f1d0
OC		 823 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
824
825 return 0;
826}
827
0e826e86
OC		 828static const struct snd_kcontrol_new rt5677_snd_controls[] = {
829 /* OUTPUT Control */
830 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
831 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
832 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
833 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
834 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
835 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
836
837 /* DAC Digital Volume */
838 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
40e3262e 839 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 840 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
40e3262e 841 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 842 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
40e3262e 843 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 844 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
40e3262e 845 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86
OC		 846
847 /* IN1/IN2 Control */
848 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
849 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
850
851 /* ADC Digital Volume Control */
852 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
853 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
854 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
855 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
856 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
857 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
858 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
859 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
860 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
861 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
862
863 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
40e3262e 864 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 865 adc_vol_tlv),
866 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
40e3262e 867 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 868 adc_vol_tlv),
869 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
40e3262e 870 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 871 adc_vol_tlv),
872 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
40e3262e 873 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 874 adc_vol_tlv),
875 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
40e3262e 876 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 877 adc_vol_tlv),
878
90bdbb46
OC		 879 /* Sidetone Control */
880 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
881 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
882
0e826e86 883 /* ADC Boost Volume Control */
80220f29 884 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 885 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
886 adc_bst_tlv),
80220f29 887 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 888 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
889 adc_bst_tlv),
80220f29 890 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 891 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
892 adc_bst_tlv),
80220f29 893 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 894 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
895 adc_bst_tlv),
80220f29 896 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
0e826e86
OC		 897 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
898 adc_bst_tlv),
af48f1d0
OC		 899
900 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
901 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
0e826e86
OC		 902};
903
904/**
905 * set_dmic_clk - Set parameter of dmic.
906 *
907 * @w: DAPM widget.
908 * @kcontrol: The kcontrol of this widget.
909 * @event: Event id.
910 *
911 * Choose dmic clock between 1MHz and 3MHz.
912 * It is better for clock to approximate 3MHz.
913 */
914static int set_dmic_clk(struct snd_soc_dapm_widget *w,
915 struct snd_kcontrol *kcontrol, int event)
916{
46f20872 917 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86 918 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
60a8d62b 919 int idx = rl6231_calc_dmic_clk(rt5677->lrck[RT5677_AIF1] << 8);
0e826e86
OC		 920
921 if (idx < 0)
922 dev_err(codec->dev, "Failed to set DMIC clock\n");
923 else
924 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
925 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
926 return idx;
927}
928
929static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
930 struct snd_soc_dapm_widget *sink)
931{
46f20872
LPC		 932 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
933 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
0e826e86
OC		 934 unsigned int val;
935
936 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
937 val &= RT5677_SCLK_SRC_MASK;
938 if (val == RT5677_SCLK_SRC_PLL1)
939 return 1;
940 else
941 return 0;
942}
943
5a8c7c26
OC		 944static int is_using_asrc(struct snd_soc_dapm_widget *source,
945 struct snd_soc_dapm_widget *sink)
946{
46f20872 947 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
e4b7e6a8 948 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
5a8c7c26
OC		 949 unsigned int reg, shift, val;
950
951 if (source->reg == RT5677_ASRC_1) {
952 switch (source->shift) {
953 case 12:
954 reg = RT5677_ASRC_4;
955 shift = 0;
956 break;
957 case 13:
958 reg = RT5677_ASRC_4;
959 shift = 4;
960 break;
961 case 14:
962 reg = RT5677_ASRC_4;
963 shift = 8;
964 break;
965 case 15:
966 reg = RT5677_ASRC_4;
967 shift = 12;
968 break;
969 default:
970 return 0;
971 }
972 } else {
973 switch (source->shift) {
974 case 0:
975 reg = RT5677_ASRC_6;
976 shift = 8;
977 break;
978 case 1:
979 reg = RT5677_ASRC_6;
980 shift = 12;
981 break;
982 case 2:
983 reg = RT5677_ASRC_5;
984 shift = 0;
985 break;
986 case 3:
987 reg = RT5677_ASRC_5;
988 shift = 4;
989 break;
990 case 4:
991 reg = RT5677_ASRC_5;
992 shift = 8;
993 break;
994 case 5:
995 reg = RT5677_ASRC_5;
996 shift = 12;
997 break;
998 case 12:
999 reg = RT5677_ASRC_3;
1000 shift = 0;
1001 break;
1002 case 13:
1003 reg = RT5677_ASRC_3;
1004 shift = 4;
1005 break;
1006 case 14:
1007 reg = RT5677_ASRC_3;
1008 shift = 12;
1009 break;
1010 default:
1011 return 0;
1012 }
1013 }
1014
e4b7e6a8
OC		 1015 regmap_read(rt5677->regmap, reg, &val);
1016 val = (val >> shift) & 0xf;
1017
5a8c7c26
OC		 1018 switch (val) {
1019 case 1 ... 6:
1020 return 1;
1021 default:
1022 return 0;
1023 }
1024
1025}
1026
1027static int can_use_asrc(struct snd_soc_dapm_widget *source,
1028 struct snd_soc_dapm_widget *sink)
1029{
1030 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1031 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1032
1033 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1034 return 1;
1035
1036 return 0;
1037}
1038
c36aa0a1
OC		 1039/**
1040 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1041 * @codec: SoC audio codec device.
1042 * @filter_mask: mask of filters.
1043 * @clk_src: clock source
1044 *
1045 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1046 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1047 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1048 * ASRC function will track i2s clock and generate a corresponding system clock
1049 * for codec. This function provides an API to select the clock source for a
1050 * set of filters specified by the mask. And the codec driver will turn on ASRC
1051 * for these filters if ASRC is selected as their clock source.
1052 */
1053int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1054 unsigned int filter_mask, unsigned int clk_src)
1055{
1056 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1057 unsigned int asrc3_mask = 0, asrc3_value = 0;
1058 unsigned int asrc4_mask = 0, asrc4_value = 0;
1059 unsigned int asrc5_mask = 0, asrc5_value = 0;
1060 unsigned int asrc6_mask = 0, asrc6_value = 0;
1061 unsigned int asrc7_mask = 0, asrc7_value = 0;
16ab6e18 1062 unsigned int asrc8_mask = 0, asrc8_value = 0;
c36aa0a1
OC		 1063
1064 switch (clk_src) {
1065 case RT5677_CLK_SEL_SYS:
1066 case RT5677_CLK_SEL_I2S1_ASRC:
1067 case RT5677_CLK_SEL_I2S2_ASRC:
1068 case RT5677_CLK_SEL_I2S3_ASRC:
1069 case RT5677_CLK_SEL_I2S4_ASRC:
1070 case RT5677_CLK_SEL_I2S5_ASRC:
1071 case RT5677_CLK_SEL_I2S6_ASRC:
1072 case RT5677_CLK_SEL_SYS2:
1073 case RT5677_CLK_SEL_SYS3:
1074 case RT5677_CLK_SEL_SYS4:
1075 case RT5677_CLK_SEL_SYS5:
1076 case RT5677_CLK_SEL_SYS6:
1077 case RT5677_CLK_SEL_SYS7:
1078 break;
1079
1080 default:
1081 return -EINVAL;
1082 }
1083
1084 /* ASRC 3 */
1085 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1086 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1087 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1088 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1089 }
1090
1091 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1092 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1093 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1094 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1095 }
1096
1097 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1098 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1099 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1100 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1101 }
1102
1103 if (asrc3_mask)
1104 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1105 asrc3_value);
1106
1107 /* ASRC 4 */
1108 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1109 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1110 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1111 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1112 }
1113
1114 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1115 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1116 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1117 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1118 }
1119
1120 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1121 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1122 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1123 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1124 }
1125
1126 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1127 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1128 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1129 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1130 }
1131
1132 if (asrc4_mask)
1133 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1134 asrc4_value);
1135
1136 /* ASRC 5 */
1137 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1138 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1139 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1140 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1141 }
1142
1143 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1144 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1145 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1146 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1147 }
1148
1149 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1150 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1151 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1152 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1153 }
1154
1155 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1156 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1157 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1158 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1159 }
1160
1161 if (asrc5_mask)
1162 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1163 asrc5_value);
1164
1165 /* ASRC 6 */
1166 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1167 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1168 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1169 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1170 }
1171
1172 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1173 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1174 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1175 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1176 }
1177
1178 if (asrc6_mask)
1179 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1180 asrc6_value);
1181
1182 /* ASRC 7 */
1183 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1184 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1185 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1186 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1187 }
1188
1189 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1190 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1191 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1192 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1193 }
1194
1195 if (asrc7_mask)
1196 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1197 asrc7_value);
1198
16ab6e18
BL		 1199 /* ASRC 8 */
1200 if (filter_mask & RT5677_I2S1_SOURCE) {
1201 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1202 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1203 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1204 }
1205
1206 if (filter_mask & RT5677_I2S2_SOURCE) {
1207 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1208 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1209 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1210 }
1211
1212 if (filter_mask & RT5677_I2S3_SOURCE) {
1213 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1214 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1215 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1216 }
1217
1218 if (filter_mask & RT5677_I2S4_SOURCE) {
1219 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1220 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1221 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1222 }
1223
1224 if (asrc8_mask)
1225 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1226 asrc8_value);
1227
c36aa0a1
OC		 1228 return 0;
1229}
1230EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1231
5220f7fb
OC		 1232static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1233 struct snd_soc_dapm_widget *sink)
1234{
1235 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1236 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1237 unsigned int asrc_setting;
1238
1239 switch (source->shift) {
1240 case 11:
1241 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1242 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1243 RT5677_AD_STO1_CLK_SEL_SFT;
1244 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1245 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1246 return 1;
1247 break;
1248
1249 case 10:
1250 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1251 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1252 RT5677_AD_STO2_CLK_SEL_SFT;
1253 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1254 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1255 return 1;
1256 break;
1257
1258 case 9:
1259 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1260 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1261 RT5677_AD_STO3_CLK_SEL_SFT;
1262 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1263 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1264 return 1;
1265 break;
1266
1267 case 8:
1268 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1269 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1270 RT5677_AD_STO4_CLK_SEL_SFT;
1271 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1272 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1273 return 1;
1274 break;
1275
1276 case 7:
1277 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1278 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1279 RT5677_AD_MONOL_CLK_SEL_SFT;
1280 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1281 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1282 return 1;
1283 break;
1284
1285 case 6:
1286 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1287 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1288 RT5677_AD_MONOR_CLK_SEL_SFT;
1289 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1290 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1291 return 1;
1292 break;
1293
1294 default:
1295 break;
1296 }
1297
1298 return 0;
1299}
1300
0e826e86
OC		 1301/* Digital Mixer */
1302static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1303 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1304 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1305 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1306 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1307};
1308
1309static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1310 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1311 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1312 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1313 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1314};
1315
1316static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1317 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1318 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1319 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1320 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1321};
1322
1323static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1324 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1325 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1326 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1327 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1328};
1329
1330static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1331 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1332 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1333 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1334 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1335};
1336
1337static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1338 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1339 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1340 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1341 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1342};
1343
1344static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1345 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1346 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1347 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1348 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1349};
1350
1351static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1352 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1353 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1354 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1355 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1356};
1357
1358static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1359 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1360 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1361 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1362 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1363};
1364
1365static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1366 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1367 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1368 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1369 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1370};
1371
1372static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1373 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1374 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1375 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1376 RT5677_M_DAC1_L_SFT, 1, 1),
1377};
1378
1379static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1380 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1381 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1382 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1383 RT5677_M_DAC1_R_SFT, 1, 1),
1384};
1385
1386static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1387 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1388 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1389 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1390 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1391 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1392 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1393 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1394 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1395};
1396
1397static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1398 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1399 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1400 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1401 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1402 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1403 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1404 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1405 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1406};
1407
1408static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1409 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1410 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1411 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1412 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1413 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1414 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1415 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1416 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1417};
1418
1419static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1420 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1421 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1422 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1423 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1424 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1425 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1426 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1427 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1428};
1429
1430static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1431 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1432 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1433 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1434 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1435 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1436 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1437 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1438 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1439};
1440
1441static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1442 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1443 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1444 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1445 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1446 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1447 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1448 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1449 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1450};
1451
1452static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1453 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1454 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1455 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1456 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1457 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1458 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1459 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1460 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1461};
1462
1463static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1464 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1465 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1466 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1467 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1468 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1469 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1470 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1471 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1472};
1473
1474static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1475 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1476 RT5677_DSP_IB_01_H_SFT, 1, 1),
1477 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1478 RT5677_DSP_IB_23_H_SFT, 1, 1),
1479 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1480 RT5677_DSP_IB_45_H_SFT, 1, 1),
1481 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1482 RT5677_DSP_IB_6_H_SFT, 1, 1),
1483 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1484 RT5677_DSP_IB_7_H_SFT, 1, 1),
1485 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1486 RT5677_DSP_IB_8_H_SFT, 1, 1),
1487 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1488 RT5677_DSP_IB_9_H_SFT, 1, 1),
1489};
1490
1491static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1492 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1493 RT5677_DSP_IB_01_L_SFT, 1, 1),
1494 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1495 RT5677_DSP_IB_23_L_SFT, 1, 1),
1496 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1497 RT5677_DSP_IB_45_L_SFT, 1, 1),
1498 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1499 RT5677_DSP_IB_6_L_SFT, 1, 1),
1500 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1501 RT5677_DSP_IB_7_L_SFT, 1, 1),
1502 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1503 RT5677_DSP_IB_8_L_SFT, 1, 1),
1504 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1505 RT5677_DSP_IB_9_L_SFT, 1, 1),
1506};
1507
1508static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1509 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1510 RT5677_DSP_IB_01_H_SFT, 1, 1),
1511 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1512 RT5677_DSP_IB_23_H_SFT, 1, 1),
1513 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1514 RT5677_DSP_IB_45_H_SFT, 1, 1),
1515 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1516 RT5677_DSP_IB_6_H_SFT, 1, 1),
1517 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1518 RT5677_DSP_IB_7_H_SFT, 1, 1),
1519 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1520 RT5677_DSP_IB_8_H_SFT, 1, 1),
1521 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1522 RT5677_DSP_IB_9_H_SFT, 1, 1),
1523};
1524
1525static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1526 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1527 RT5677_DSP_IB_01_L_SFT, 1, 1),
1528 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1529 RT5677_DSP_IB_23_L_SFT, 1, 1),
1530 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1531 RT5677_DSP_IB_45_L_SFT, 1, 1),
1532 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1533 RT5677_DSP_IB_6_L_SFT, 1, 1),
1534 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1535 RT5677_DSP_IB_7_L_SFT, 1, 1),
1536 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1537 RT5677_DSP_IB_8_L_SFT, 1, 1),
1538 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1539 RT5677_DSP_IB_9_L_SFT, 1, 1),
1540};
1541
1542static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1543 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1544 RT5677_DSP_IB_01_H_SFT, 1, 1),
1545 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1546 RT5677_DSP_IB_23_H_SFT, 1, 1),
1547 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1548 RT5677_DSP_IB_45_H_SFT, 1, 1),
1549 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1550 RT5677_DSP_IB_6_H_SFT, 1, 1),
1551 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1552 RT5677_DSP_IB_7_H_SFT, 1, 1),
1553 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1554 RT5677_DSP_IB_8_H_SFT, 1, 1),
1555 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1556 RT5677_DSP_IB_9_H_SFT, 1, 1),
1557};
1558
1559static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1560 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1561 RT5677_DSP_IB_01_L_SFT, 1, 1),
1562 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1563 RT5677_DSP_IB_23_L_SFT, 1, 1),
1564 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1565 RT5677_DSP_IB_45_L_SFT, 1, 1),
1566 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1567 RT5677_DSP_IB_6_L_SFT, 1, 1),
1568 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1569 RT5677_DSP_IB_7_L_SFT, 1, 1),
1570 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1571 RT5677_DSP_IB_8_L_SFT, 1, 1),
1572 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1573 RT5677_DSP_IB_9_L_SFT, 1, 1),
1574};
1575
1576
1577/* Mux */
1b7fd76a 1578/* DAC1 L/R Source */ /* MX-29 [10:8] */
0e826e86
OC		 1579static const char * const rt5677_dac1_src[] = {
1580 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1581 "OB 01"
1582};
1583
1584static SOC_ENUM_SINGLE_DECL(
1585 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1586 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1587
1588static const struct snd_kcontrol_new rt5677_dac1_mux =
1b7fd76a 1589 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
0e826e86 1590
1b7fd76a 1591/* ADDA1 L/R Source */ /* MX-29 [1:0] */
0e826e86
OC		 1592static const char * const rt5677_adda1_src[] = {
1593 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1594};
1595
1596static SOC_ENUM_SINGLE_DECL(
1597 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1598 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1599
1600static const struct snd_kcontrol_new rt5677_adda1_mux =
1b7fd76a 1601 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
0e826e86
OC		 1602
1603
1b7fd76a 1604/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
0e826e86
OC		 1605static const char * const rt5677_dac2l_src[] = {
1606 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1607 "OB 2",
1608};
1609
1610static SOC_ENUM_SINGLE_DECL(
1611 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1612 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1613
1614static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1b7fd76a 1615 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
0e826e86
OC		 1616
1617static const char * const rt5677_dac2r_src[] = {
1618 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1619 "OB 3", "Haptic Generator", "VAD ADC"
1620};
1621
1622static SOC_ENUM_SINGLE_DECL(
1623 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1624 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1625
1626static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1b7fd76a 1627 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
0e826e86 1628
1b7fd76a 1629/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
0e826e86
OC		 1630static const char * const rt5677_dac3l_src[] = {
1631 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1632 "SLB DAC 4", "OB 4"
1633};
1634
1635static SOC_ENUM_SINGLE_DECL(
1636 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1637 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1638
1639static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1b7fd76a 1640 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
0e826e86
OC		 1641
1642static const char * const rt5677_dac3r_src[] = {
1643 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1644 "SLB DAC 5", "OB 5"
1645};
1646
1647static SOC_ENUM_SINGLE_DECL(
1648 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1649 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1650
1651static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1b7fd76a 1652 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
0e826e86 1653
1b7fd76a 1654/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
0e826e86
OC		 1655static const char * const rt5677_dac4l_src[] = {
1656 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1657 "SLB DAC 6", "OB 6"
1658};
1659
1660static SOC_ENUM_SINGLE_DECL(
1661 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1662 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1663
1664static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1b7fd76a 1665 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
0e826e86
OC		 1666
1667static const char * const rt5677_dac4r_src[] = {
1668 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1669 "SLB DAC 7", "OB 7"
1670};
1671
1672static SOC_ENUM_SINGLE_DECL(
1673 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1674 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1675
1676static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1b7fd76a 1677 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
0e826e86
OC		 1678
1679/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1680static const char * const rt5677_iob_bypass_src[] = {
1681 "Bypass", "Pass SRC"
1682};
1683
1684static SOC_ENUM_SINGLE_DECL(
1685 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1686 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1687
1688static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1b7fd76a 1689 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
0e826e86
OC		 1690
1691static SOC_ENUM_SINGLE_DECL(
1692 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1693 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1694
1695static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1b7fd76a 1696 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
0e826e86
OC		 1697
1698static SOC_ENUM_SINGLE_DECL(
1699 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1700 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1701
1702static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1b7fd76a 1703 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
0e826e86
OC		 1704
1705static SOC_ENUM_SINGLE_DECL(
1706 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1707 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1708
1709static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1b7fd76a 1710 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
0e826e86
OC		 1711
1712static SOC_ENUM_SINGLE_DECL(
1713 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1714 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1715
1716static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1b7fd76a 1717 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
0e826e86 1718
d65fd3a4 1719/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
0e826e86
OC		 1720static const char * const rt5677_stereo_adc2_src[] = {
1721 "DD MIX1", "DMIC", "Stereo DAC MIX"
1722};
1723
1724static SOC_ENUM_SINGLE_DECL(
1725 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1726 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1727
1728static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1b7fd76a 1729 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
0e826e86
OC		 1730
1731static SOC_ENUM_SINGLE_DECL(
1732 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1733 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1734
1735static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1b7fd76a 1736 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
0e826e86
OC		 1737
1738static SOC_ENUM_SINGLE_DECL(
1739 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1740 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1741
1742static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1b7fd76a 1743 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
0e826e86
OC		 1744
1745/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1746static const char * const rt5677_dmic_src[] = {
1747 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1748};
1749
1750static SOC_ENUM_SINGLE_DECL(
1751 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1752 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1753
1754static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1b7fd76a 1755 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
0e826e86
OC		 1756
1757static SOC_ENUM_SINGLE_DECL(
1758 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1759 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1760
1761static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1b7fd76a 1762 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
0e826e86
OC		 1763
1764static SOC_ENUM_SINGLE_DECL(
1765 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1766 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1767
1768static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1b7fd76a 1769 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
0e826e86
OC		 1770
1771static SOC_ENUM_SINGLE_DECL(
1772 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1773 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1774
1775static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1b7fd76a 1776 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
0e826e86
OC		 1777
1778static SOC_ENUM_SINGLE_DECL(
1779 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1780 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1781
1782static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1b7fd76a 1783 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
0e826e86
OC		 1784
1785static SOC_ENUM_SINGLE_DECL(
1786 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1787 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1788
1789static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1b7fd76a 1790 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
0e826e86 1791
1b7fd76a 1792/* Stereo2 ADC Source */ /* MX-26 [0] */
0e826e86
OC		 1793static const char * const rt5677_stereo2_adc_lr_src[] = {
1794 "L", "LR"
1795};
1796
1797static SOC_ENUM_SINGLE_DECL(
1798 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1799 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1800
1801static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1b7fd76a 1802 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
0e826e86 1803
d65fd3a4 1804/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
0e826e86
OC		 1805static const char * const rt5677_stereo_adc1_src[] = {
1806 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1807};
1808
1809static SOC_ENUM_SINGLE_DECL(
1810 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1811 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1812
1813static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1b7fd76a 1814 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
0e826e86
OC		 1815
1816static SOC_ENUM_SINGLE_DECL(
1817 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1818 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1819
1820static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1b7fd76a 1821 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
0e826e86
OC		 1822
1823static SOC_ENUM_SINGLE_DECL(
1824 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1825 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1826
1827static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1b7fd76a 1828 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
0e826e86 1829
1b7fd76a 1830/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
0e826e86
OC		 1831static const char * const rt5677_mono_adc2_l_src[] = {
1832 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1833};
1834
1835static SOC_ENUM_SINGLE_DECL(
1836 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1837 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1838
1839static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1b7fd76a 1840 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
0e826e86 1841
1b7fd76a 1842/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
0e826e86
OC		 1843static const char * const rt5677_mono_adc1_l_src[] = {
1844 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1845};
1846
1847static SOC_ENUM_SINGLE_DECL(
1848 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1849 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1850
1851static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1b7fd76a 1852 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
0e826e86 1853
1b7fd76a 1854/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
0e826e86
OC		 1855static const char * const rt5677_mono_adc2_r_src[] = {
1856 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1857};
1858
1859static SOC_ENUM_SINGLE_DECL(
1860 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1861 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1862
1863static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1b7fd76a 1864 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
0e826e86 1865
1b7fd76a 1866/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
0e826e86
OC		 1867static const char * const rt5677_mono_adc1_r_src[] = {
1868 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1869};
1870
1871static SOC_ENUM_SINGLE_DECL(
1872 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1873 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1874
1875static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1b7fd76a 1876 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
0e826e86
OC		 1877
1878/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1879static const char * const rt5677_stereo4_adc2_src[] = {
1880 "DD MIX1", "DMIC", "DD MIX2"
1881};
1882
1883static SOC_ENUM_SINGLE_DECL(
1884 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1885 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1886
1887static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1b7fd76a 1888 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
0e826e86
OC		 1889
1890
1891/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1892static const char * const rt5677_stereo4_adc1_src[] = {
1893 "DD MIX1", "ADC1/2", "DD MIX2"
1894};
1895
1896static SOC_ENUM_SINGLE_DECL(
1897 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1898 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1899
1900static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1b7fd76a 1901 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
0e826e86
OC		 1902
1903/* InBound0/1 Source */ /* MX-A3 [14:12] */
1904static const char * const rt5677_inbound01_src[] = {
1905 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1906 "VAD ADC/DAC1 FS"
1907};
1908
1909static SOC_ENUM_SINGLE_DECL(
1910 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1911 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1912
1913static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1914 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1915
1916/* InBound2/3 Source */ /* MX-A3 [10:8] */
1917static const char * const rt5677_inbound23_src[] = {
1918 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1919 "DAC1 FS", "IF4 DAC"
1920};
1921
1922static SOC_ENUM_SINGLE_DECL(
1923 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1924 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1925
1926static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1927 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1928
1929/* InBound4/5 Source */ /* MX-A3 [6:4] */
1930static const char * const rt5677_inbound45_src[] = {
1931 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1932 "IF3 DAC"
1933};
1934
1935static SOC_ENUM_SINGLE_DECL(
1936 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1937 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1938
1939static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1940 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1941
1942/* InBound6 Source */ /* MX-A3 [2:0] */
1943static const char * const rt5677_inbound6_src[] = {
1944 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1945 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1946};
1947
1948static SOC_ENUM_SINGLE_DECL(
1949 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1950 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1951
1952static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1953 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1954
1955/* InBound7 Source */ /* MX-A4 [14:12] */
1956static const char * const rt5677_inbound7_src[] = {
1957 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1958 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1959};
1960
1961static SOC_ENUM_SINGLE_DECL(
1962 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1963 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1964
1965static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1966 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1967
1968/* InBound8 Source */ /* MX-A4 [10:8] */
1969static const char * const rt5677_inbound8_src[] = {
1970 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1971 "MONO ADC MIX L", "DACL1 FS"
1972};
1973
1974static SOC_ENUM_SINGLE_DECL(
1975 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1976 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1977
1978static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1979 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1980
1981/* InBound9 Source */ /* MX-A4 [6:4] */
1982static const char * const rt5677_inbound9_src[] = {
1983 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1984 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1985};
1986
1987static SOC_ENUM_SINGLE_DECL(
1988 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1989 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1990
1991static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1992 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1993
1994/* VAD Source */ /* MX-9F [6:4] */
1995static const char * const rt5677_vad_src[] = {
1996 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1997 "STO3 ADC MIX L"
1998};
1999
2000static SOC_ENUM_SINGLE_DECL(
2001 rt5677_vad_enum, RT5677_VAD_CTRL4,
2002 RT5677_VAD_SRC_SFT, rt5677_vad_src);
2003
2004static const struct snd_kcontrol_new rt5677_vad_src_mux =
2005 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
2006
2007/* Sidetone Source */ /* MX-13 [11:9] */
2008static const char * const rt5677_sidetone_src[] = {
2009 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
2010};
2011
2012static SOC_ENUM_SINGLE_DECL(
2013 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2014 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2015
2016static const struct snd_kcontrol_new rt5677_sidetone_mux =
2017 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2018
2019/* DAC1/2 Source */ /* MX-15 [1:0] */
2020static const char * const rt5677_dac12_src[] = {
2021 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2022};
2023
2024static SOC_ENUM_SINGLE_DECL(
2025 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2026 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2027
2028static const struct snd_kcontrol_new rt5677_dac12_mux =
2029 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2030
2031/* DAC3 Source */ /* MX-15 [5:4] */
2032static const char * const rt5677_dac3_src[] = {
2033 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2034};
2035
2036static SOC_ENUM_SINGLE_DECL(
2037 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2038 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2039
2040static const struct snd_kcontrol_new rt5677_dac3_mux =
2041 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2042
1b7fd76a 2043/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
0e826e86
OC		 2044static const char * const rt5677_pdm_src[] = {
2045 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2046};
2047
2048static SOC_ENUM_SINGLE_DECL(
2049 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2050 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2051
2052static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1b7fd76a 2053 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
0e826e86
OC		 2054
2055static SOC_ENUM_SINGLE_DECL(
2056 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2057 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2058
2059static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1b7fd76a 2060 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
0e826e86
OC		 2061
2062static SOC_ENUM_SINGLE_DECL(
2063 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2064 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2065
2066static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1b7fd76a 2067 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
0e826e86
OC		 2068
2069static SOC_ENUM_SINGLE_DECL(
2070 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2071 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2072
2073static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1b7fd76a 2074 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
0e826e86 2075
d65fd3a4 2076/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
0e826e86
OC		 2077static const char * const rt5677_if12_adc1_src[] = {
2078 "STO1 ADC MIX", "OB01", "VAD ADC"
2079};
2080
2081static SOC_ENUM_SINGLE_DECL(
2082 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2083 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2084
2085static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1b7fd76a 2086 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
0e826e86
OC		 2087
2088static SOC_ENUM_SINGLE_DECL(
2089 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2090 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2091
2092static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1b7fd76a 2093 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
0e826e86
OC		 2094
2095static SOC_ENUM_SINGLE_DECL(
2096 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2097 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2098
2099static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1b7fd76a 2100 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
0e826e86
OC		 2101
2102/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2103static const char * const rt5677_if12_adc2_src[] = {
2104 "STO2 ADC MIX", "OB23"
2105};
2106
2107static SOC_ENUM_SINGLE_DECL(
2108 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2109 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2110
2111static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1b7fd76a 2112 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
0e826e86
OC		 2113
2114static SOC_ENUM_SINGLE_DECL(
2115 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2116 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2117
2118static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1b7fd76a 2119 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
0e826e86
OC		 2120
2121static SOC_ENUM_SINGLE_DECL(
2122 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2123 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2124
2125static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1b7fd76a 2126 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
0e826e86
OC		 2127
2128/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2129static const char * const rt5677_if12_adc3_src[] = {
2130 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2131};
2132
2133static SOC_ENUM_SINGLE_DECL(
2134 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2135 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2136
2137static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1b7fd76a 2138 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
0e826e86
OC		 2139
2140static SOC_ENUM_SINGLE_DECL(
2141 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2142 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2143
2144static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1b7fd76a 2145 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
0e826e86
OC		 2146
2147static SOC_ENUM_SINGLE_DECL(
2148 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2149 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2150
2151static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1b7fd76a 2152 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
0e826e86 2153
d65fd3a4 2154/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
0e826e86
OC		 2155static const char * const rt5677_if12_adc4_src[] = {
2156 "STO4 ADC MIX", "OB67", "OB01"
2157};
2158
2159static SOC_ENUM_SINGLE_DECL(
2160 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2161 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2162
2163static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1b7fd76a 2164 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
0e826e86
OC		 2165
2166static SOC_ENUM_SINGLE_DECL(
2167 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2168 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2169
2170static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1b7fd76a 2171 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
0e826e86
OC		 2172
2173static SOC_ENUM_SINGLE_DECL(
2174 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2175 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2176
2177static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1b7fd76a 2178 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
0e826e86 2179
d65fd3a4 2180/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
0e826e86
OC		 2181static const char * const rt5677_if34_adc_src[] = {
2182 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2183 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2184};
2185
2186static SOC_ENUM_SINGLE_DECL(
2187 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2188 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2189
2190static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1b7fd76a 2191 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
0e826e86
OC		 2192
2193static SOC_ENUM_SINGLE_DECL(
2194 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2195 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2196
2197static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1b7fd76a 2198 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
0e826e86 2199
e6f6ebc1
OC		 2200/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2201static const char * const rt5677_if12_adc_swap_src[] = {
2202 "L/R", "R/L", "L/L", "R/R"
2203};
2204
2205static SOC_ENUM_SINGLE_DECL(
2206 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2207 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2208
2209static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2210 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2211
2212static SOC_ENUM_SINGLE_DECL(
2213 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2214 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2215
2216static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2217 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2218
2219static SOC_ENUM_SINGLE_DECL(
2220 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2221 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2222
2223static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2224 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2225
2226static SOC_ENUM_SINGLE_DECL(
2227 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2228 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2229
2230static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2231 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2232
2233static SOC_ENUM_SINGLE_DECL(
2234 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2235 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2236
2237static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2238 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2239
2240static SOC_ENUM_SINGLE_DECL(
2241 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2242 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2243
2244static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2245 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2246
2247static SOC_ENUM_SINGLE_DECL(
2248 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2249 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2250
2251static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2252 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2253
2254static SOC_ENUM_SINGLE_DECL(
2255 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2256 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2257
2258static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2259 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2260
d65fd3a4 2261/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
e6f6ebc1
OC		 2262static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2263 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2264 "3/1/2/4", "3/4/1/2"
2265};
2266
2267static SOC_ENUM_SINGLE_DECL(
2268 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2269 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2270
2271static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2272 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2273
2274/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2275static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2276 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2277 "2/3/1/4", "3/4/1/2"
2278};
2279
2280static SOC_ENUM_SINGLE_DECL(
2281 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2282 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2283
2284static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2285 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2286
91159eca
OC		 2287/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2288 MX-3F[14:12][10:8][6:4][2:0]
2289 MX-43[14:12][10:8][6:4][2:0]
2290 MX-44[14:12][10:8][6:4][2:0] */
2291static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2292 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2293};
2294
2295static SOC_ENUM_SINGLE_DECL(
2296 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2297 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2298
2299static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2300 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2301
2302static SOC_ENUM_SINGLE_DECL(
2303 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2304 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2305
2306static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2307 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2308
2309static SOC_ENUM_SINGLE_DECL(
2310 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2311 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2312
2313static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2314 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2315
2316static SOC_ENUM_SINGLE_DECL(
2317 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2318 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2319
2320static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2321 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2322
2323static SOC_ENUM_SINGLE_DECL(
2324 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2325 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2326
2327static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2328 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2329
2330static SOC_ENUM_SINGLE_DECL(
2331 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2332 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2333
2334static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2335 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2336
2337static SOC_ENUM_SINGLE_DECL(
2338 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2339 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2340
2341static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2342 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2343
2344static SOC_ENUM_SINGLE_DECL(
2345 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2346 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2347
2348static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2349 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2350
2351static SOC_ENUM_SINGLE_DECL(
2352 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2353 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2354
2355static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2356 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2357
2358static SOC_ENUM_SINGLE_DECL(
2359 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2360 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2361
2362static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2363 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2364
2365static SOC_ENUM_SINGLE_DECL(
2366 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2367 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2368
2369static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2370 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2371
2372static SOC_ENUM_SINGLE_DECL(
2373 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2374 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2375
2376static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2377 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2378
2379static SOC_ENUM_SINGLE_DECL(
2380 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2381 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2382
2383static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2384 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2385
2386static SOC_ENUM_SINGLE_DECL(
2387 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2388 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2389
2390static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2391 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2392
2393static SOC_ENUM_SINGLE_DECL(
2394 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2395 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2396
2397static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2398 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2399
2400static SOC_ENUM_SINGLE_DECL(
2401 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2402 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2403
2404static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2405 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2406
0e826e86
OC		 2407static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2408 struct snd_kcontrol *kcontrol, int event)
2409{
46f20872 2410 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2411 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2412
2413 switch (event) {
2414 case SND_SOC_DAPM_POST_PMU:
2415 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2416 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2417 break;
2418
2419 case SND_SOC_DAPM_PRE_PMD:
2420 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2421 RT5677_PWR_BST1_P, 0);
2422 break;
2423
2424 default:
2425 return 0;
2426 }
2427
2428 return 0;
2429}
2430
2431static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2432 struct snd_kcontrol *kcontrol, int event)
2433{
46f20872 2434 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2435 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2436
2437 switch (event) {
2438 case SND_SOC_DAPM_POST_PMU:
2439 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2440 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2441 break;
2442
2443 case SND_SOC_DAPM_PRE_PMD:
2444 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2445 RT5677_PWR_BST2_P, 0);
2446 break;
2447
2448 default:
2449 return 0;
2450 }
2451
2452 return 0;
2453}
2454
2455static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2456 struct snd_kcontrol *kcontrol, int event)
2457{
46f20872 2458 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2459 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2460
2461 switch (event) {
bdfbf255 2462 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2463 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2464 break;
2465
2466 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2467 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2468 break;
bdfbf255 2469
0e826e86
OC		 2470 default:
2471 return 0;
2472 }
2473
2474 return 0;
2475}
2476
2477static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2478 struct snd_kcontrol *kcontrol, int event)
2479{
46f20872 2480 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2481 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2482
2483 switch (event) {
bdfbf255 2484 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2485 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2486 break;
2487
2488 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2489 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2490 break;
bdfbf255 2491
0e826e86
OC		 2492 default:
2493 return 0;
2494 }
2495
2496 return 0;
2497}
2498
2499static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2500 struct snd_kcontrol *kcontrol, int event)
2501{
46f20872 2502 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2503 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2504
2505 switch (event) {
2506 case SND_SOC_DAPM_POST_PMU:
2507 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2508 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2509 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2510 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2511 break;
f58c3b91
OC		 2512
2513 case SND_SOC_DAPM_PRE_PMD:
2514 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2515 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2516 RT5677_PWR_CLK_MB, 0);
2517 break;
2518
0e826e86
OC		 2519 default:
2520 return 0;
2521 }
2522
2523 return 0;
2524}
2525
e6f6ebc1
OC		 2526static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2527 struct snd_kcontrol *kcontrol, int event)
2528{
46f20872 2529 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e6f6ebc1
OC		 2530 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2531 unsigned int value;
2532
2533 switch (event) {
2534 case SND_SOC_DAPM_PRE_PMU:
2535 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2536 if (value & RT5677_IF1_ADC_CTRL_MASK)
2537 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2538 RT5677_IF1_ADC_MODE_MASK,
2539 RT5677_IF1_ADC_MODE_TDM);
2540 break;
2541
2542 default:
2543 return 0;
2544 }
2545
2546 return 0;
2547}
2548
2549static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2550 struct snd_kcontrol *kcontrol, int event)
2551{
46f20872 2552 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e6f6ebc1
OC		 2553 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2554 unsigned int value;
2555
2556 switch (event) {
2557 case SND_SOC_DAPM_PRE_PMU:
2558 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2559 if (value & RT5677_IF2_ADC_CTRL_MASK)
2560 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2561 RT5677_IF2_ADC_MODE_MASK,
2562 RT5677_IF2_ADC_MODE_TDM);
2563 break;
2564
2565 default:
2566 return 0;
2567 }
2568
2569 return 0;
2570}
2571
683996cb
OC		 2572static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2573 struct snd_kcontrol *kcontrol, int event)
2574{
46f20872 2575 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
683996cb
OC		 2576 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2577
2578 switch (event) {
2579 case SND_SOC_DAPM_POST_PMU:
6b43c2eb 2580 if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON &&
683996cb
OC		 2581 !rt5677->is_vref_slow) {
2582 mdelay(20);
2583 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2584 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2585 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2586 rt5677->is_vref_slow = true;
2587 }
2588 break;
2589
2590 default:
2591 return 0;
2592 }
2593
2594 return 0;
2595}
2596
0e826e86
OC		 2597static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2598 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
bdfbf255
OC		 2599 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2600 SND_SOC_DAPM_POST_PMU),
0e826e86 2601 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
bdfbf255
OC		 2602 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2603 SND_SOC_DAPM_POST_PMU),
0e826e86 2604
5a8c7c26
OC		 2605 /* ASRC */
2606 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2607 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2608 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2609 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2610 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2611 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2612 0),
2613 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2614 0),
2615 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2616 0),
2617 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2618 0),
2619 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2620 0),
2621 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2622 0),
2623 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2624 0),
2625 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2626 0),
2627 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2628 0),
2629 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2630 0),
2631 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2632 0),
2633 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2634 0),
2635 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2636 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2637 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2638 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2639 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2640 0),
2641 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2642 0),
2643
0e826e86
OC		 2644 /* Input Side */
2645 /* micbias */
3d0c03d9 2646 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
f58c3b91
OC		 2647 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2648 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 2649
2650 /* Input Lines */
2651 SND_SOC_DAPM_INPUT("DMIC L1"),
2652 SND_SOC_DAPM_INPUT("DMIC R1"),
2653 SND_SOC_DAPM_INPUT("DMIC L2"),
2654 SND_SOC_DAPM_INPUT("DMIC R2"),
2655 SND_SOC_DAPM_INPUT("DMIC L3"),
2656 SND_SOC_DAPM_INPUT("DMIC R3"),
2657 SND_SOC_DAPM_INPUT("DMIC L4"),
2658 SND_SOC_DAPM_INPUT("DMIC R4"),
2659
2660 SND_SOC_DAPM_INPUT("IN1P"),
2661 SND_SOC_DAPM_INPUT("IN1N"),
2662 SND_SOC_DAPM_INPUT("IN2P"),
2663 SND_SOC_DAPM_INPUT("IN2N"),
2664
2665 SND_SOC_DAPM_INPUT("Haptic Generator"),
2666
2d15d974
BL		 2667 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2668 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2669 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2670 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2671
2672 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2673 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2674 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2675 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2676 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2677 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2678 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2679 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
0e826e86
OC		 2680
2681 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2682 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2683
2684 /* Boost */
2685 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2686 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2687 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2688 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2689 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2690 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2691
2692 /* ADCs */
2693 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2694 0, 0),
2695 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2696 0, 0),
2697 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2698
2699 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2700 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2701 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2702 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2703 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2704 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2705 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2706 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2707
2708 /* ADC Mux */
2709 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2710 &rt5677_sto1_dmic_mux),
2711 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2712 &rt5677_sto1_adc1_mux),
2713 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2714 &rt5677_sto1_adc2_mux),
2715 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2716 &rt5677_sto2_dmic_mux),
2717 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2718 &rt5677_sto2_adc1_mux),
2719 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2720 &rt5677_sto2_adc2_mux),
2721 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2722 &rt5677_sto2_adc_lr_mux),
2723 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2724 &rt5677_sto3_dmic_mux),
2725 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2726 &rt5677_sto3_adc1_mux),
2727 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2728 &rt5677_sto3_adc2_mux),
2729 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2730 &rt5677_sto4_dmic_mux),
2731 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2732 &rt5677_sto4_adc1_mux),
2733 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2734 &rt5677_sto4_adc2_mux),
2735 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2736 &rt5677_mono_dmic_l_mux),
2737 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2738 &rt5677_mono_dmic_r_mux),
2739 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2740 &rt5677_mono_adc2_l_mux),
2741 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2742 &rt5677_mono_adc1_l_mux),
2743 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2744 &rt5677_mono_adc1_r_mux),
2745 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2746 &rt5677_mono_adc2_r_mux),
2747
2748 /* ADC Mixer */
2749 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2750 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2751 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2752 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2753 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2754 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2755 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2756 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2757 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2758 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2759 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2760 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2761 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2762 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2763 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2764 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2765 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2766 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2767 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2768 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2769 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2770 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2771 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2772 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2773 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2774 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2775 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2776 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2777 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2778 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2779 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2780 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2781
2782 /* ADC PGA */
2783 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2784 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2785 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2786 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2787 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2788 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2791 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2792 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2793 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
e6f6ebc1
OC		 2797 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
0e826e86
OC		 2799
2800 /* DSP */
2801 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2802 &rt5677_ib9_src_mux),
2803 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2804 &rt5677_ib8_src_mux),
2805 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2806 &rt5677_ib7_src_mux),
2807 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2808 &rt5677_ib6_src_mux),
2809 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2810 &rt5677_ib45_src_mux),
2811 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2812 &rt5677_ib23_src_mux),
2813 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2814 &rt5677_ib01_src_mux),
2815 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2816 &rt5677_ib45_bypass_src_mux),
2817 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2818 &rt5677_ib23_bypass_src_mux),
2819 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2820 &rt5677_ib01_bypass_src_mux),
2821 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2822 &rt5677_ob23_bypass_src_mux),
2823 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2824 &rt5677_ob01_bypass_src_mux),
2825
2826 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2827 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2828
2829 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2830 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2831 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2832 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2833 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2834 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2835
2836 /* Digital Interface */
2837 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2838 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2839 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2840 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2841 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2842 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2843 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2852 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2855
2856 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2857 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2858 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2859 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2860 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2874
2875 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2876 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2883
2884 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2885 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2886 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2887 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2888 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2889 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2890 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2891 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2892
2893 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2894 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2895 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2896 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2897 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2898 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2908 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2909 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2911
2912 /* Digital Interface Select */
2913 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2914 &rt5677_if1_adc1_mux),
2915 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2916 &rt5677_if1_adc2_mux),
2917 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2918 &rt5677_if1_adc3_mux),
2919 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2920 &rt5677_if1_adc4_mux),
e6f6ebc1
OC		 2921 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2922 &rt5677_if1_adc1_swap_mux),
2923 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2924 &rt5677_if1_adc2_swap_mux),
2925 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2926 &rt5677_if1_adc3_swap_mux),
2927 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2928 &rt5677_if1_adc4_swap_mux),
2929 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2930 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2931 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2932 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2933 &rt5677_if2_adc1_mux),
2934 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2935 &rt5677_if2_adc2_mux),
2936 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2937 &rt5677_if2_adc3_mux),
2938 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2939 &rt5677_if2_adc4_mux),
e6f6ebc1
OC		 2940 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5677_if2_adc1_swap_mux),
2942 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5677_if2_adc2_swap_mux),
2944 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5677_if2_adc3_swap_mux),
2946 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5677_if2_adc4_swap_mux),
2948 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2949 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2950 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2951 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2952 &rt5677_if3_adc_mux),
2953 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2954 &rt5677_if4_adc_mux),
2955 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2956 &rt5677_slb_adc1_mux),
2957 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2958 &rt5677_slb_adc2_mux),
2959 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5677_slb_adc3_mux),
2961 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5677_slb_adc4_mux),
2963
91159eca
OC		 2964 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2965 &rt5677_if1_dac0_tdm_sel_mux),
2966 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2967 &rt5677_if1_dac1_tdm_sel_mux),
2968 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2969 &rt5677_if1_dac2_tdm_sel_mux),
2970 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2971 &rt5677_if1_dac3_tdm_sel_mux),
2972 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2973 &rt5677_if1_dac4_tdm_sel_mux),
2974 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2975 &rt5677_if1_dac5_tdm_sel_mux),
2976 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2977 &rt5677_if1_dac6_tdm_sel_mux),
2978 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2979 &rt5677_if1_dac7_tdm_sel_mux),
2980
2981 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2982 &rt5677_if2_dac0_tdm_sel_mux),
2983 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5677_if2_dac1_tdm_sel_mux),
2985 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5677_if2_dac2_tdm_sel_mux),
2987 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2988 &rt5677_if2_dac3_tdm_sel_mux),
2989 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5677_if2_dac4_tdm_sel_mux),
2991 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5677_if2_dac5_tdm_sel_mux),
2993 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5677_if2_dac6_tdm_sel_mux),
2995 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5677_if2_dac7_tdm_sel_mux),
2997
0e826e86
OC		 2998 /* Audio Interface */
2999 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3000 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3001 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3002 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3003 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3007 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3009
3010 /* Sidetone Mux */
3011 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3012 &rt5677_sidetone_mux),
90bdbb46
OC		 3013 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3014 RT5677_ST_EN_SFT, 0, NULL, 0),
3015
0e826e86
OC		 3016 /* VAD Mux*/
3017 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3018 &rt5677_vad_src_mux),
3019
3020 /* Tensilica DSP */
3021 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3022 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3023 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3024 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3025 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3026 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3027 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3028 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3029 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3030 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3031 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3032 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3033 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3034
3035 /* Output Side */
d65fd3a4 3036 /* DAC mixer before sound effect */
0e826e86
OC		 3037 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3038 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3039 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3040 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3041 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3042
3043 /* DAC Mux */
3044 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3045 &rt5677_dac1_mux),
3046 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3047 &rt5677_adda1_mux),
3048 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3049 &rt5677_dac12_mux),
3050 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3051 &rt5677_dac3_mux),
3052
3053 /* DAC2 channel Mux */
3054 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3055 &rt5677_dac2_l_mux),
3056 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3057 &rt5677_dac2_r_mux),
3058
3059 /* DAC3 channel Mux */
3060 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3061 &rt5677_dac3_l_mux),
3062 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3063 &rt5677_dac3_r_mux),
3064
3065 /* DAC4 channel Mux */
3066 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3067 &rt5677_dac4_l_mux),
3068 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3069 &rt5677_dac4_r_mux),
3070
3071 /* DAC Mixer */
3072 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3073 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
6800b5ba 3074 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
0e826e86 3075 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
6800b5ba 3076 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
0e826e86 3077 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
6800b5ba
OC		 3078 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3079 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
3080 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3081 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
3082 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3083 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
3084 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3085 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
0e826e86
OC		 3086
3087 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3088 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3089 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3090 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3091 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3092 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3093 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3094 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3095 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3096 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3097 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3098 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3099 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3100 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3101 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3102 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3103 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3104 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3105 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3106 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3107
3108 /* DACs */
3109 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3110 RT5677_PWR_DAC1_BIT, 0),
3111 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3112 RT5677_PWR_DAC2_BIT, 0),
3113 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3114 RT5677_PWR_DAC3_BIT, 0),
3115
3116 /* PDM */
3117 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3118 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3119 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3120 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3121
3122 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3123 1, &rt5677_pdm1_l_mux),
3124 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3125 1, &rt5677_pdm1_r_mux),
3126 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3127 1, &rt5677_pdm2_l_mux),
3128 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3129 1, &rt5677_pdm2_r_mux),
3130
683996cb 3131 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
0e826e86 3132 0, NULL, 0),
683996cb 3133 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
0e826e86 3134 0, NULL, 0),
683996cb 3135 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
0e826e86
OC		 3136 0, NULL, 0),
3137
683996cb
OC		 3138 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3139 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3140 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3141 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3142 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3143 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3144
0e826e86
OC		 3145 /* Output Lines */
3146 SND_SOC_DAPM_OUTPUT("LOUT1"),
3147 SND_SOC_DAPM_OUTPUT("LOUT2"),
3148 SND_SOC_DAPM_OUTPUT("LOUT3"),
3149 SND_SOC_DAPM_OUTPUT("PDM1L"),
3150 SND_SOC_DAPM_OUTPUT("PDM1R"),
3151 SND_SOC_DAPM_OUTPUT("PDM2L"),
3152 SND_SOC_DAPM_OUTPUT("PDM2R"),
683996cb
OC		 3153
3154 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
0e826e86
OC		 3155};
3156
3157static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
5220f7fb
OC		 3158 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3159 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3160 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3161 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3162 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3163 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
5a8c7c26
OC		 3164 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3165 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3166 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3167 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3168
3169 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3170 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3171 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3172 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3173 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3174 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3175 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3176 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3177 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3178 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3179 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3180 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3181 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3182
0e826e86
OC		 3183 { "DMIC1", NULL, "DMIC L1" },
3184 { "DMIC1", NULL, "DMIC R1" },
3185 { "DMIC2", NULL, "DMIC L2" },
3186 { "DMIC2", NULL, "DMIC R2" },
3187 { "DMIC3", NULL, "DMIC L3" },
3188 { "DMIC3", NULL, "DMIC R3" },
3189 { "DMIC4", NULL, "DMIC L4" },
3190 { "DMIC4", NULL, "DMIC R4" },
3191
3192 { "DMIC L1", NULL, "DMIC CLK" },
3193 { "DMIC R1", NULL, "DMIC CLK" },
3194 { "DMIC L2", NULL, "DMIC CLK" },
3195 { "DMIC R2", NULL, "DMIC CLK" },
3196 { "DMIC L3", NULL, "DMIC CLK" },
3197 { "DMIC R3", NULL, "DMIC CLK" },
3198 { "DMIC L4", NULL, "DMIC CLK" },
3199 { "DMIC R4", NULL, "DMIC CLK" },
3200
2d15d974
BL		 3201 { "DMIC L1", NULL, "DMIC1 power" },
3202 { "DMIC R1", NULL, "DMIC1 power" },
3203 { "DMIC L3", NULL, "DMIC3 power" },
3204 { "DMIC R3", NULL, "DMIC3 power" },
3205 { "DMIC L4", NULL, "DMIC4 power" },
3206 { "DMIC R4", NULL, "DMIC4 power" },
3207
0e826e86
OC		 3208 { "BST1", NULL, "IN1P" },
3209 { "BST1", NULL, "IN1N" },
3210 { "BST2", NULL, "IN2P" },
3211 { "BST2", NULL, "IN2N" },
3212
22e51345
BL		 3213 { "IN1P", NULL, "MICBIAS1" },
3214 { "IN1N", NULL, "MICBIAS1" },
3215 { "IN2P", NULL, "MICBIAS1" },
3216 { "IN2N", NULL, "MICBIAS1" },
0e826e86
OC		 3217
3218 { "ADC 1", NULL, "BST1" },
3219 { "ADC 1", NULL, "ADC 1 power" },
3220 { "ADC 1", NULL, "ADC1 clock" },
3221 { "ADC 2", NULL, "BST2" },
3222 { "ADC 2", NULL, "ADC 2 power" },
3223 { "ADC 2", NULL, "ADC2 clock" },
3224
3225 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3226 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3227 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3228 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3229
3230 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3231 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3232 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3233 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3234
3235 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3236 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3237 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3238 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3239
3240 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3241 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3242 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3243 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3244
3245 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3246 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3247 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3248 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3249
3250 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3251 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3252 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3253 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3254
3255 { "ADC 1_2", NULL, "ADC 1" },
3256 { "ADC 1_2", NULL, "ADC 2" },
3257
3258 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3259 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3260 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3261
3262 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3263 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3264 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3265
3266 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3267 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3268 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3269
3270 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3271 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3272 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3273
3274 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3275 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3276 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3277
3278 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3279 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3280 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3281
3282 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3283 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3284 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3285
3286 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3287 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3288 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3289
3290 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3291 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3292 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3293
3294 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3295 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3296 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3297
3298 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3299 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3300 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3301
3302 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3303 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3304 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3305
3306 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3307 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3308 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3309 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3310
3311 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3312 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
0e826e86
OC		 3313 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3314 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3315 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3316
3317 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3318 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3319
3320 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3321 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3322 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3323 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3324
3325 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3326 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3327
3328 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3329 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3330
3331 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3332 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
0e826e86
OC		 3333 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3334 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3335 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3336
3337 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3338 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3339
3340 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3341 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3342 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3343 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3344
3345 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3346 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
0e826e86
OC		 3347 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3348 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3349 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3350
3351 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3352 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3353
3354 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3355 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3356 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3357 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3358
3359 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3360 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
0e826e86
OC		 3361 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3362 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3363 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3364
3365 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3366 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3367
3368 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3369 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3370 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3371 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3372
3373 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3374 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3375 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3376 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3377
3378 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3379 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3380
3381 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3382 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3383 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3384 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3385 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3386
3387 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3388 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3389 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3390
3391 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3392 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3393
3394 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3395 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3396 { "IF1 ADC3 Mux", "OB45", "OB45" },
3397
3398 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3399 { "IF1 ADC4 Mux", "OB67", "OB67" },
3400 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3401
e6f6ebc1
OC		 3402 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3403 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3404 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3405 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3406
3407 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3408 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3409 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3410 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3411
3412 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3413 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3414 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3415 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3416
3417 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3418 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3419 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3420 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3421
3422 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3423 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3424 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3425 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3426
3427 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3428 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3429 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3430 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3431 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3432 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3433 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3434 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3435
0e826e86 3436 { "AIF1TX", NULL, "I2S1" },
e6f6ebc1 3437 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
0e826e86
OC		 3438
3439 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3440 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3441 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3442
3443 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3444 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3445
3446 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3447 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3448 { "IF2 ADC3 Mux", "OB45", "OB45" },
3449
3450 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3451 { "IF2 ADC4 Mux", "OB67", "OB67" },
3452 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3453
e6f6ebc1
OC		 3454 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3455 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3456 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3457 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3458
3459 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3460 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3461 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3462 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3463
3464 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3465 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3466 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3467 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3468
3469 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3470 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3471 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3472 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3473
3474 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3475 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3476 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3477 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3478
3479 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3480 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3481 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3482 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3483 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3484 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3485 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3486 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3487
0e826e86 3488 { "AIF2TX", NULL, "I2S2" },
e6f6ebc1 3489 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
0e826e86
OC		 3490
3491 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3492 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3493 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3494 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3495 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3496 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3497 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3498 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3499
3500 { "AIF3TX", NULL, "I2S3" },
3501 { "AIF3TX", NULL, "IF3 ADC Mux" },
3502
3503 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3504 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3505 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3506 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3507 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3508 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3509 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3510 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3511
3512 { "AIF4TX", NULL, "I2S4" },
3513 { "AIF4TX", NULL, "IF4 ADC Mux" },
3514
3515 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3516 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3517 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3518
3519 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3520 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3521
3522 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3523 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3524 { "SLB ADC3 Mux", "OB45", "OB45" },
3525
3526 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3527 { "SLB ADC4 Mux", "OB67", "OB67" },
3528 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3529
3530 { "SLBTX", NULL, "SLB" },
3531 { "SLBTX", NULL, "SLB ADC1 Mux" },
3532 { "SLBTX", NULL, "SLB ADC2 Mux" },
3533 { "SLBTX", NULL, "SLB ADC3 Mux" },
3534 { "SLBTX", NULL, "SLB ADC4 Mux" },
3535
3536 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3537 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3538 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3539 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3540 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3541
3542 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3543 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3544
3545 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3546 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3547 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3548 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3549 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3550 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3551
3552 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3553 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3554
3555 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3556 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3557 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3558 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3559 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3560
3561 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3562 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3563
70068776
OC		 3564 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3565 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
0e826e86
OC		 3566 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3567 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3568 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3569 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3570 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3571 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3572
70068776
OC		 3573 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3574 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
0e826e86
OC		 3575 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3576 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3577 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3578 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3579 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3580 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3581
3582 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3583 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3584 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3585 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3586 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3587 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3588
3589 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3590 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3591 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3592 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3593 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3594 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3595 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3596
3597 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3598 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3599 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3600 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3601 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3602 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3603 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3604
3605 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3606 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3607 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3608 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3609 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3610 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3611 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3612
3613 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3614 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3615 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3616 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3617 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3618 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3619 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3620
3621 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3622 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3623 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3624 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3625 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3626 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3627 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3628
3629 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3630 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3631 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3632 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3633 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3634 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3635 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3636
3637 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3638 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3639 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3640 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3641 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3642 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3643 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3644
3645 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3646 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3647 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3648 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3649
3650 { "OutBound2", NULL, "OB23 Bypass Mux" },
3651 { "OutBound3", NULL, "OB23 Bypass Mux" },
3652 { "OutBound4", NULL, "OB4 MIX" },
3653 { "OutBound5", NULL, "OB5 MIX" },
3654 { "OutBound6", NULL, "OB6 MIX" },
3655 { "OutBound7", NULL, "OB7 MIX" },
3656
3657 { "OB45", NULL, "OutBound4" },
3658 { "OB45", NULL, "OutBound5" },
3659 { "OB67", NULL, "OutBound6" },
3660 { "OB67", NULL, "OutBound7" },
3661
3662 { "IF1 DAC0", NULL, "AIF1RX" },
3663 { "IF1 DAC1", NULL, "AIF1RX" },
3664 { "IF1 DAC2", NULL, "AIF1RX" },
3665 { "IF1 DAC3", NULL, "AIF1RX" },
3666 { "IF1 DAC4", NULL, "AIF1RX" },
3667 { "IF1 DAC5", NULL, "AIF1RX" },
3668 { "IF1 DAC6", NULL, "AIF1RX" },
3669 { "IF1 DAC7", NULL, "AIF1RX" },
3670 { "IF1 DAC0", NULL, "I2S1" },
3671 { "IF1 DAC1", NULL, "I2S1" },
3672 { "IF1 DAC2", NULL, "I2S1" },
3673 { "IF1 DAC3", NULL, "I2S1" },
3674 { "IF1 DAC4", NULL, "I2S1" },
3675 { "IF1 DAC5", NULL, "I2S1" },
3676 { "IF1 DAC6", NULL, "I2S1" },
3677 { "IF1 DAC7", NULL, "I2S1" },
3678
91159eca
OC		 3679 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3680 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3681 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3682 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3683 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3684 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3685 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3686 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3687
3688 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3689 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3690 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3691 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3692 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3693 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3694 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3695 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3696
3697 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3698 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3699 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3700 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3701 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3702 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3703 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3704 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3705
3706 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3707 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3708 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3709 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3710 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3711 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3712 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3713 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3714
3715 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3716 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3717 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3718 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3719 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3720 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3721 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3722 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3723
3724 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3725 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3726 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3727 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3728 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3729 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3730 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3731 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3732
3733 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3734 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3735 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3736 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3737 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3738 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3739 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3740 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3741
3742 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3743 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3744 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3745 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3746 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3747 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3748 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3749 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3750
3751 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3752 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3753 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3754 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3755 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3756 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3757 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3758 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
0e826e86
OC		 3759
3760 { "IF2 DAC0", NULL, "AIF2RX" },
3761 { "IF2 DAC1", NULL, "AIF2RX" },
3762 { "IF2 DAC2", NULL, "AIF2RX" },
3763 { "IF2 DAC3", NULL, "AIF2RX" },
3764 { "IF2 DAC4", NULL, "AIF2RX" },
3765 { "IF2 DAC5", NULL, "AIF2RX" },
3766 { "IF2 DAC6", NULL, "AIF2RX" },
3767 { "IF2 DAC7", NULL, "AIF2RX" },
3768 { "IF2 DAC0", NULL, "I2S2" },
3769 { "IF2 DAC1", NULL, "I2S2" },
3770 { "IF2 DAC2", NULL, "I2S2" },
3771 { "IF2 DAC3", NULL, "I2S2" },
3772 { "IF2 DAC4", NULL, "I2S2" },
3773 { "IF2 DAC5", NULL, "I2S2" },
3774 { "IF2 DAC6", NULL, "I2S2" },
3775 { "IF2 DAC7", NULL, "I2S2" },
3776
91159eca
OC		 3777 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3778 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3779 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3780 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3781 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3782 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3783 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3784 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3785
3786 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3787 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3788 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3789 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3790 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3791 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3792 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3793 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3794
3795 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3796 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3797 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3798 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3799 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3800 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3801 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3802 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3803
3804 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3805 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3806 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3807 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3808 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3809 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3810 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3811 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3812
3813 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3814 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3815 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3816 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3817 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3818 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3819 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3820 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3821
3822 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3823 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3824 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3825 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3826 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3827 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3828 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3829 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3830
3831 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3832 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3833 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3834 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3835 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3836 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3837 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3838 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3839
3840 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3841 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3842 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3843 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3844 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3845 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3846 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3847 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3848
3849 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3850 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3851 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3852 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3853 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3854 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3855 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3856 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
0e826e86
OC		 3857
3858 { "IF3 DAC", NULL, "AIF3RX" },
3859 { "IF3 DAC", NULL, "I2S3" },
3860
3861 { "IF4 DAC", NULL, "AIF4RX" },
3862 { "IF4 DAC", NULL, "I2S4" },
3863
3864 { "IF3 DAC L", NULL, "IF3 DAC" },
3865 { "IF3 DAC R", NULL, "IF3 DAC" },
3866
3867 { "IF4 DAC L", NULL, "IF4 DAC" },
3868 { "IF4 DAC R", NULL, "IF4 DAC" },
3869
3870 { "SLB DAC0", NULL, "SLBRX" },
3871 { "SLB DAC1", NULL, "SLBRX" },
3872 { "SLB DAC2", NULL, "SLBRX" },
3873 { "SLB DAC3", NULL, "SLBRX" },
3874 { "SLB DAC4", NULL, "SLBRX" },
3875 { "SLB DAC5", NULL, "SLBRX" },
3876 { "SLB DAC6", NULL, "SLBRX" },
3877 { "SLB DAC7", NULL, "SLBRX" },
3878 { "SLB DAC0", NULL, "SLB" },
3879 { "SLB DAC1", NULL, "SLB" },
3880 { "SLB DAC2", NULL, "SLB" },
3881 { "SLB DAC3", NULL, "SLB" },
3882 { "SLB DAC4", NULL, "SLB" },
3883 { "SLB DAC5", NULL, "SLB" },
3884 { "SLB DAC6", NULL, "SLB" },
3885 { "SLB DAC7", NULL, "SLB" },
3886
3887 { "SLB DAC01", NULL, "SLB DAC0" },
3888 { "SLB DAC01", NULL, "SLB DAC1" },
3889 { "SLB DAC23", NULL, "SLB DAC2" },
3890 { "SLB DAC23", NULL, "SLB DAC3" },
3891 { "SLB DAC45", NULL, "SLB DAC4" },
3892 { "SLB DAC45", NULL, "SLB DAC5" },
3893 { "SLB DAC67", NULL, "SLB DAC6" },
3894 { "SLB DAC67", NULL, "SLB DAC7" },
3895
3896 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3897 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3898 { "ADDA1 Mux", "OB 67", "OB67" },
3899
3900 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3901 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3902 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3903 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3904 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3905 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3906
3907 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3908 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3909 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3910 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3911
3912 { "DAC1 FS", NULL, "DAC1 MIXL" },
3913 { "DAC1 FS", NULL, "DAC1 MIXR" },
3914
70068776
OC		 3915 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3916 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
0e826e86
OC		 3917 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3918 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3919 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3920 { "DAC2 L Mux", "OB 2", "OutBound2" },
3921
70068776
OC		 3922 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3923 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
0e826e86
OC		 3924 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3925 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3926 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3927 { "DAC2 R Mux", "OB 3", "OutBound3" },
3928 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3929 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3930
70068776
OC		 3931 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3932 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
0e826e86
OC		 3933 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3934 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3935 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3936 { "DAC3 L Mux", "OB 4", "OutBound4" },
3937
70068776
OC		 3938 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3939 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
0e826e86
OC		 3940 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3941 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3942 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3943 { "DAC3 R Mux", "OB 5", "OutBound5" },
3944
70068776
OC		 3945 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3946 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
0e826e86
OC		 3947 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3948 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3949 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3950 { "DAC4 L Mux", "OB 6", "OutBound6" },
3951
70068776
OC		 3952 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3953 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
0e826e86
OC		 3954 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3955 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3956 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3957 { "DAC4 R Mux", "OB 7", "OutBound7" },
3958
3959 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3960 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3961 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3962 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3963 { "Sidetone Mux", "ADC1", "ADC 1" },
3964 { "Sidetone Mux", "ADC2", "ADC 2" },
90bdbb46 3965 { "Sidetone Mux", NULL, "Sidetone Power" },
0e826e86
OC		 3966
3967 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3968 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3969 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3970 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3971 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3972 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3973 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3974 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3975 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3976 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
38d595e2 3977 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3978
3979 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3980 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3981 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3982 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
6800b5ba 3983 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
38d595e2 3984 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3985 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3986 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3987 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3988 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
6800b5ba 3989 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
38d595e2 3990 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3991
3992 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3993 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3994 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3995 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 3996 { "DD1 MIXL", NULL, "dac mono3 left filter" },
38d595e2 3997 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 3998 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3999 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4000 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4001 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 4002 { "DD1 MIXR", NULL, "dac mono3 right filter" },
38d595e2 4003 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4004
4005 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4006 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4007 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4008 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 4009 { "DD2 MIXL", NULL, "dac mono4 left filter" },
38d595e2 4010 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4011 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4012 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4013 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4014 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 4015 { "DD2 MIXR", NULL, "dac mono4 right filter" },
38d595e2 4016 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4017
4018 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4019 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4020 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4021 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4022 { "DD1 MIX", NULL, "DD1 MIXL" },
4023 { "DD1 MIX", NULL, "DD1 MIXR" },
4024 { "DD2 MIX", NULL, "DD2 MIXL" },
4025 { "DD2 MIX", NULL, "DD2 MIXR" },
4026
4027 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4028 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4029 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4030 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4031
4032 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4033 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4034 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4035 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4036
4037 { "DAC 1", NULL, "DAC12 SRC Mux" },
0e826e86 4038 { "DAC 2", NULL, "DAC12 SRC Mux" },
0e826e86 4039 { "DAC 3", NULL, "DAC3 SRC Mux" },
0e826e86
OC		 4040
4041 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4042 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4043 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4044 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4045 { "PDM1 L Mux", NULL, "PDM1 Power" },
4046 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4047 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4048 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4049 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4050 { "PDM1 R Mux", NULL, "PDM1 Power" },
4051 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4052 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4053 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4054 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4055 { "PDM2 L Mux", NULL, "PDM2 Power" },
4056 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4057 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4058 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4059 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4060 { "PDM2 R Mux", NULL, "PDM2 Power" },
4061
4062 { "LOUT1 amp", NULL, "DAC 1" },
4063 { "LOUT2 amp", NULL, "DAC 2" },
4064 { "LOUT3 amp", NULL, "DAC 3" },
4065
683996cb
OC		 4066 { "LOUT1 vref", NULL, "LOUT1 amp" },
4067 { "LOUT2 vref", NULL, "LOUT2 amp" },
4068 { "LOUT3 vref", NULL, "LOUT3 amp" },
4069
4070 { "LOUT1", NULL, "LOUT1 vref" },
4071 { "LOUT2", NULL, "LOUT2 vref" },
4072 { "LOUT3", NULL, "LOUT3 vref" },
0e826e86
OC		 4073
4074 { "PDM1L", NULL, "PDM1 L Mux" },
4075 { "PDM1R", NULL, "PDM1 R Mux" },
4076 { "PDM2L", NULL, "PDM2 L Mux" },
4077 { "PDM2R", NULL, "PDM2 R Mux" },
4078};
4079
2d15d974
BL		 4080static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4081 { "DMIC L2", NULL, "DMIC1 power" },
4082 { "DMIC R2", NULL, "DMIC1 power" },
4083};
4084
4085static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4086 { "DMIC L2", NULL, "DMIC2 power" },
4087 { "DMIC R2", NULL, "DMIC2 power" },
4088};
4089
0e826e86
OC		 4090static int rt5677_hw_params(struct snd_pcm_substream *substream,
4091 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4092{
4093 struct snd_soc_codec *codec = dai->codec;
4094 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4095 unsigned int val_len = 0, val_clk, mask_clk;
4096 int pre_div, bclk_ms, frame_size;
4097
4098 rt5677->lrck[dai->id] = params_rate(params);
30f14b43 4099 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86 4100 if (pre_div < 0) {
8a4bd60a
AP		 4101 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4102 rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86
OC		 4103 return -EINVAL;
4104 }
4105 frame_size = snd_soc_params_to_frame_size(params);
4106 if (frame_size < 0) {
4107 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4108 return -EINVAL;
4109 }
4110 bclk_ms = frame_size > 32;
4111 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4112
4113 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4114 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4115 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4116 bclk_ms, pre_div, dai->id);
4117
4118 switch (params_width(params)) {
4119 case 16:
4120 break;
4121 case 20:
4122 val_len |= RT5677_I2S_DL_20;
4123 break;
4124 case 24:
4125 val_len |= RT5677_I2S_DL_24;
4126 break;
4127 case 8:
4128 val_len |= RT5677_I2S_DL_8;
4129 break;
4130 default:
4131 return -EINVAL;
4132 }
4133
4134 switch (dai->id) {
4135 case RT5677_AIF1:
4136 mask_clk = RT5677_I2S_PD1_MASK;
4137 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4138 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4139 RT5677_I2S_DL_MASK, val_len);
4140 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4141 mask_clk, val_clk);
4142 break;
4143 case RT5677_AIF2:
4144 mask_clk = RT5677_I2S_PD2_MASK;
4145 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4146 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4147 RT5677_I2S_DL_MASK, val_len);
4148 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4149 mask_clk, val_clk);
4150 break;
4151 case RT5677_AIF3:
4152 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4153 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4154 pre_div << RT5677_I2S_PD3_SFT;
4155 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4156 RT5677_I2S_DL_MASK, val_len);
4157 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4158 mask_clk, val_clk);
4159 break;
4160 case RT5677_AIF4:
4161 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4162 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4163 pre_div << RT5677_I2S_PD4_SFT;
4164 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4165 RT5677_I2S_DL_MASK, val_len);
4166 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4167 mask_clk, val_clk);
4168 break;
4169 default:
4170 break;
4171 }
4172
4173 return 0;
4174}
4175
4176static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4177{
4178 struct snd_soc_codec *codec = dai->codec;
4179 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4180 unsigned int reg_val = 0;
4181
4182 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4183 case SND_SOC_DAIFMT_CBM_CFM:
4184 rt5677->master[dai->id] = 1;
4185 break;
4186 case SND_SOC_DAIFMT_CBS_CFS:
4187 reg_val |= RT5677_I2S_MS_S;
4188 rt5677->master[dai->id] = 0;
4189 break;
4190 default:
4191 return -EINVAL;
4192 }
4193
4194 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4195 case SND_SOC_DAIFMT_NB_NF:
4196 break;
4197 case SND_SOC_DAIFMT_IB_NF:
4198 reg_val |= RT5677_I2S_BP_INV;
4199 break;
4200 default:
4201 return -EINVAL;
4202 }
4203
4204 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4205 case SND_SOC_DAIFMT_I2S:
4206 break;
4207 case SND_SOC_DAIFMT_LEFT_J:
4208 reg_val |= RT5677_I2S_DF_LEFT;
4209 break;
4210 case SND_SOC_DAIFMT_DSP_A:
4211 reg_val |= RT5677_I2S_DF_PCM_A;
4212 break;
4213 case SND_SOC_DAIFMT_DSP_B:
4214 reg_val |= RT5677_I2S_DF_PCM_B;
4215 break;
4216 default:
4217 return -EINVAL;
4218 }
4219
4220 switch (dai->id) {
4221 case RT5677_AIF1:
4222 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4223 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4224 RT5677_I2S_DF_MASK, reg_val);
4225 break;
4226 case RT5677_AIF2:
4227 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4228 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4229 RT5677_I2S_DF_MASK, reg_val);
4230 break;
4231 case RT5677_AIF3:
4232 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4233 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4234 RT5677_I2S_DF_MASK, reg_val);
4235 break;
4236 case RT5677_AIF4:
4237 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4238 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4239 RT5677_I2S_DF_MASK, reg_val);
4240 break;
4241 default:
4242 break;
4243 }
4244
4245
4246 return 0;
4247}
4248
4249static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4250 int clk_id, unsigned int freq, int dir)
4251{
4252 struct snd_soc_codec *codec = dai->codec;
4253 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4254 unsigned int reg_val = 0;
4255
4256 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4257 return 0;
4258
4259 switch (clk_id) {
4260 case RT5677_SCLK_S_MCLK:
4261 reg_val |= RT5677_SCLK_SRC_MCLK;
4262 break;
4263 case RT5677_SCLK_S_PLL1:
4264 reg_val |= RT5677_SCLK_SRC_PLL1;
4265 break;
4266 case RT5677_SCLK_S_RCCLK:
4267 reg_val |= RT5677_SCLK_SRC_RCCLK;
4268 break;
4269 default:
4270 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4271 return -EINVAL;
4272 }
4273 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4274 RT5677_SCLK_SRC_MASK, reg_val);
4275 rt5677->sysclk = freq;
4276 rt5677->sysclk_src = clk_id;
4277
4278 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4279
4280 return 0;
4281}
4282
4283/**
4284 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4285 * @freq_in: external clock provided to codec.
4286 * @freq_out: target clock which codec works on.
4287 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4288 *
4289 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4290 *
4291 * Returns 0 for success or negative error code.
4292 */
4293static int rt5677_pll_calc(const unsigned int freq_in,
099d334e 4294 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
0e826e86 4295{
099d334e 4296 if (RT5677_PLL_INP_MIN > freq_in)
0e826e86
OC		 4297 return -EINVAL;
4298
099d334e 4299 return rl6231_pll_calc(freq_in, freq_out, pll_code);
0e826e86
OC		 4300}
4301
4302static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4303 unsigned int freq_in, unsigned int freq_out)
4304{
4305 struct snd_soc_codec *codec = dai->codec;
4306 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
099d334e 4307 struct rl6231_pll_code pll_code;
0e826e86
OC		 4308 int ret;
4309
4310 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4311 freq_out == rt5677->pll_out)
4312 return 0;
4313
4314 if (!freq_in || !freq_out) {
4315 dev_dbg(codec->dev, "PLL disabled\n");
4316
4317 rt5677->pll_in = 0;
4318 rt5677->pll_out = 0;
4319 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4320 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4321 return 0;
4322 }
4323
4324 switch (source) {
4325 case RT5677_PLL1_S_MCLK:
4326 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4327 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4328 break;
4329 case RT5677_PLL1_S_BCLK1:
4330 case RT5677_PLL1_S_BCLK2:
4331 case RT5677_PLL1_S_BCLK3:
4332 case RT5677_PLL1_S_BCLK4:
4333 switch (dai->id) {
4334 case RT5677_AIF1:
4335 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4336 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4337 break;
4338 case RT5677_AIF2:
4339 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4340 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4341 break;
4342 case RT5677_AIF3:
4343 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4344 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4345 break;
4346 case RT5677_AIF4:
4347 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4348 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4349 break;
4350 default:
4351 break;
4352 }
4353 break;
4354 default:
4355 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4356 return -EINVAL;
4357 }
4358
4359 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4360 if (ret < 0) {
4361 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4362 return ret;
4363 }
4364
099d334e
AL		 4365 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4366 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4367 pll_code.n_code, pll_code.k_code);
0e826e86
OC		 4368
4369 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
099d334e 4370 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
0e826e86
OC		 4371 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4372 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4373 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4374
4375 rt5677->pll_in = freq_in;
4376 rt5677->pll_out = freq_out;
4377 rt5677->pll_src = source;
4378
4379 return 0;
4380}
4381
48561afe
OC		 4382static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4383 unsigned int rx_mask, int slots, int slot_width)
4384{
4385 struct snd_soc_codec *codec = dai->codec;
e4b7e6a8 4386 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
9913b9f5 4387 unsigned int val = 0, slot_width_25 = 0;
48561afe
OC		 4388
4389 if (rx_mask || tx_mask)
4390 val |= (1 << 12);
4391
4392 switch (slots) {
4393 case 4:
4394 val |= (1 << 10);
4395 break;
4396 case 6:
4397 val |= (2 << 10);
4398 break;
4399 case 8:
4400 val |= (3 << 10);
4401 break;
4402 case 2:
4403 default:
4404 break;
4405 }
4406
4407 switch (slot_width) {
4408 case 20:
4409 val |= (1 << 8);
4410 break;
9913b9f5
OC		 4411 case 25:
4412 slot_width_25 = 0x8080;
48561afe
OC		 4413 case 24:
4414 val |= (2 << 8);
4415 break;
4416 case 32:
4417 val |= (3 << 8);
4418 break;
4419 case 16:
4420 default:
4421 break;
4422 }
4423
4424 switch (dai->id) {
4425 case RT5677_AIF1:
e4b7e6a8
OC		 4426 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4427 val);
9913b9f5
OC		 4428 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4429 slot_width_25);
48561afe
OC		 4430 break;
4431 case RT5677_AIF2:
e4b7e6a8
OC		 4432 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4433 val);
9913b9f5
OC		 4434 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4435 slot_width_25);
48561afe
OC		 4436 break;
4437 default:
4438 break;
4439 }
4440
4441 return 0;
4442}
4443
0e826e86
OC		 4444static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4445 enum snd_soc_bias_level level)
4446{
4447 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4448
4449 switch (level) {
4450 case SND_SOC_BIAS_ON:
4451 break;
4452
4453 case SND_SOC_BIAS_PREPARE:
6b43c2eb 4454 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
af48f1d0
OC		 4455 rt5677_set_dsp_vad(codec, false);
4456
0e826e86
OC		 4457 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4458 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4459 0x0055);
4460 regmap_update_bits(rt5677->regmap,
4461 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4462 0x0f00, 0x0f00);
4463 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
683996cb 4464 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
0e826e86
OC		 4465 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4466 RT5677_PWR_BG | RT5677_PWR_VREF2,
4467 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4468 RT5677_PWR_BG | RT5677_PWR_VREF2);
683996cb 4469 rt5677->is_vref_slow = false;
0e826e86
OC		 4470 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4471 RT5677_PWR_CORE, RT5677_PWR_CORE);
4472 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4473 0x1, 0x1);
4474 }
4475 break;
4476
4477 case SND_SOC_BIAS_STANDBY:
4478 break;
4479
4480 case SND_SOC_BIAS_OFF:
4481 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4482 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4483 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
f18803a3 4484 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
0e826e86
OC		 4485 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4486 regmap_update_bits(rt5677->regmap,
4487 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
af48f1d0
OC		 4488
4489 if (rt5677->dsp_vad_en)
4490 rt5677_set_dsp_vad(codec, true);
0e826e86
OC		 4491 break;
4492
4493 default:
4494 break;
4495 }
0e826e86
OC		 4496
4497 return 0;
4498}
4499
44caf764
OC		 4500#ifdef CONFIG_GPIOLIB
4501static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4502{
4503 return container_of(chip, struct rt5677_priv, gpio_chip);
4504}
4505
4506static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4507{
4508 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4509
4510 switch (offset) {
4511 case RT5677_GPIO1 ... RT5677_GPIO5:
4512 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4513 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4514 break;
4515
4516 case RT5677_GPIO6:
4517 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4518 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4519 break;
4520
4521 default:
4522 break;
4523 }
4524}
4525
4526static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4527 unsigned offset, int value)
4528{
4529 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4530
4531 switch (offset) {
4532 case RT5677_GPIO1 ... RT5677_GPIO5:
4533 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4534 0x3 << (offset * 3 + 1),
4535 (0x2 | !!value) << (offset * 3 + 1));
4536 break;
4537
4538 case RT5677_GPIO6:
4539 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4540 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4541 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4542 break;
4543
4544 default:
4545 break;
4546 }
4547
4548 return 0;
4549}
4550
4551static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4552{
4553 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4554 int value, ret;
4555
4556 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4557 if (ret < 0)
4558 return ret;
4559
4560 return (value & (0x1 << offset)) >> offset;
4561}
4562
4563static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4564{
4565 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4566
4567 switch (offset) {
4568 case RT5677_GPIO1 ... RT5677_GPIO5:
4569 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4570 0x1 << (offset * 3 + 2), 0x0);
4571 break;
4572
4573 case RT5677_GPIO6:
4574 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4575 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4576 break;
4577
4578 default:
4579 break;
4580 }
4581
4582 return 0;
4583}
4584
40eb90a1
AP		 4585/** Configures the gpio as
4586 * 0 - floating
4587 * 1 - pull down
4588 * 2 - pull up
4589 */
4590static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4591 int value)
4592{
4593 int shift;
4594
4595 switch (offset) {
4596 case RT5677_GPIO1 ... RT5677_GPIO2:
4597 shift = 2 * (1 - offset);
4598 regmap_update_bits(rt5677->regmap,
4599 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4600 0x3 << shift,
4601 (value & 0x3) << shift);
4602 break;
4603
4604 case RT5677_GPIO3 ... RT5677_GPIO6:
4605 shift = 2 * (9 - offset);
4606 regmap_update_bits(rt5677->regmap,
4607 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4608 0x3 << shift,
4609 (value & 0x3) << shift);
4610 break;
4611
4612 default:
4613 break;
4614 }
4615}
4616
5e3363ad
OC		 4617static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4618{
4619 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4620 struct regmap_irq_chip_data *data = rt5677->irq_data;
4621 int irq;
4622
4623 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4624 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4625 (rt5677->pdata.jd1_gpio == 2 &&
4626 offset == RT5677_GPIO2) ||
4627 (rt5677->pdata.jd1_gpio == 3 &&
4628 offset == RT5677_GPIO3)) {
4629 irq = RT5677_IRQ_JD1;
4630 } else {
4631 return -ENXIO;
4632 }
4633 }
4634
4635 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4636 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4637 (rt5677->pdata.jd2_gpio == 2 &&
4638 offset == RT5677_GPIO5) ||
4639 (rt5677->pdata.jd2_gpio == 3 &&
4640 offset == RT5677_GPIO6)) {
4641 irq = RT5677_IRQ_JD2;
4642 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4643 offset == RT5677_GPIO4) ||
4644 (rt5677->pdata.jd3_gpio == 2 &&
4645 offset == RT5677_GPIO5) ||
4646 (rt5677->pdata.jd3_gpio == 3 &&
4647 offset == RT5677_GPIO6)) {
4648 irq = RT5677_IRQ_JD3;
4649 } else {
4650 return -ENXIO;
4651 }
4652 }
4653
4654 return regmap_irq_get_virq(data, irq);
4655}
4656
44caf764
OC		 4657static struct gpio_chip rt5677_template_chip = {
4658 .label = "rt5677",
4659 .owner = THIS_MODULE,
4660 .direction_output = rt5677_gpio_direction_out,
4661 .set = rt5677_gpio_set,
4662 .direction_input = rt5677_gpio_direction_in,
4663 .get = rt5677_gpio_get,
5e3363ad 4664 .to_irq = rt5677_to_irq,
44caf764
OC		 4665 .can_sleep = 1,
4666};
4667
4668static void rt5677_init_gpio(struct i2c_client *i2c)
4669{
4670 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4671 int ret;
4672
4673 rt5677->gpio_chip = rt5677_template_chip;
4674 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4675 rt5677->gpio_chip.dev = &i2c->dev;
4676 rt5677->gpio_chip.base = -1;
4677
4678 ret = gpiochip_add(&rt5677->gpio_chip);
4679 if (ret != 0)
4680 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4681}
4682
4683static void rt5677_free_gpio(struct i2c_client *i2c)
4684{
4685 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
44caf764 4686
5d5e63af 4687 gpiochip_remove(&rt5677->gpio_chip);
44caf764
OC		 4688}
4689#else
45b6e1d3
AP		 4690static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4691 int value)
4692{
4693}
4694
44caf764
OC		 4695static void rt5677_init_gpio(struct i2c_client *i2c)
4696{
4697}
4698
4699static void rt5677_free_gpio(struct i2c_client *i2c)
4700{
4701}
4702#endif
4703
0e826e86
OC		 4704static int rt5677_probe(struct snd_soc_codec *codec)
4705{
6b43c2eb 4706 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
0e826e86 4707 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
40eb90a1 4708 int i;
0e826e86
OC		 4709
4710 rt5677->codec = codec;
4711
2d15d974 4712 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
6b43c2eb 4713 snd_soc_dapm_add_routes(dapm,
2d15d974
BL		 4714 rt5677_dmic2_clk_2,
4715 ARRAY_SIZE(rt5677_dmic2_clk_2));
4716 } else { /*use dmic1 clock by default*/
6b43c2eb 4717 snd_soc_dapm_add_routes(dapm,
2d15d974
BL		 4718 rt5677_dmic2_clk_1,
4719 ARRAY_SIZE(rt5677_dmic2_clk_1));
4720 }
4721
bd1204cb 4722 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
0e826e86
OC		 4723
4724 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4725 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4726
40eb90a1
AP		 4727 for (i = 0; i < RT5677_GPIO_NUM; i++)
4728 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4729
5e3363ad
OC		 4730 if (rt5677->irq_data) {
4731 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4732 0x8000);
4733 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4734 0x0008);
4735
4736 if (rt5677->pdata.jd1_gpio)
4737 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4738 RT5677_SEL_GPIO_JD1_MASK,
4739 rt5677->pdata.jd1_gpio <<
4740 RT5677_SEL_GPIO_JD1_SFT);
4741
4742 if (rt5677->pdata.jd2_gpio)
4743 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4744 RT5677_SEL_GPIO_JD2_MASK,
4745 rt5677->pdata.jd2_gpio <<
4746 RT5677_SEL_GPIO_JD2_SFT);
4747
4748 if (rt5677->pdata.jd3_gpio)
4749 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4750 RT5677_SEL_GPIO_JD3_MASK,
4751 rt5677->pdata.jd3_gpio <<
4752 RT5677_SEL_GPIO_JD3_SFT);
4753 }
4754
af48f1d0 4755 mutex_init(&rt5677->dsp_cmd_lock);
6fe17da0 4756 mutex_init(&rt5677->dsp_pri_lock);
af48f1d0 4757
0e826e86
OC		 4758 return 0;
4759}
4760
4761static int rt5677_remove(struct snd_soc_codec *codec)
4762{
4763 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4764
4765 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
f285f161
AL		 4766 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4767 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
0e826e86
OC		 4768
4769 return 0;
4770}
4771
4772#ifdef CONFIG_PM
4773static int rt5677_suspend(struct snd_soc_codec *codec)
4774{
4775 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4776
af48f1d0
OC		 4777 if (!rt5677->dsp_vad_en) {
4778 regcache_cache_only(rt5677->regmap, true);
4779 regcache_mark_dirty(rt5677->regmap);
af48f1d0 4780
f285f161
AL		 4781 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4782 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
cbca4076 4783 }
0e826e86
OC		 4784
4785 return 0;
4786}
4787
4788static int rt5677_resume(struct snd_soc_codec *codec)
4789{
4790 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4791
af48f1d0 4792 if (!rt5677->dsp_vad_en) {
f285f161
AL		 4793 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4794 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
efd901ee 4795 if (rt5677->pow_ldo2 || rt5677->reset_pin)
cbca4076 4796 msleep(10);
cbca4076 4797
af48f1d0
OC		 4798 regcache_cache_only(rt5677->regmap, false);
4799 regcache_sync(rt5677->regmap);
4800 }
0e826e86
OC		 4801
4802 return 0;
4803}
4804#else
4805#define rt5677_suspend NULL
4806#define rt5677_resume NULL
4807#endif
4808
19ba484d
OC		 4809static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4810{
4811 struct i2c_client *client = context;
4812 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4813
6fe17da0
OC		 4814 if (rt5677->is_dsp_mode) {
4815 if (reg > 0xff) {
4816 mutex_lock(&rt5677->dsp_pri_lock);
4817 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4818 reg & 0xff);
4819 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4820 mutex_unlock(&rt5677->dsp_pri_lock);
4821 } else {
4822 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4823 }
4824 } else {
19ba484d 4825 regmap_read(rt5677->regmap_physical, reg, val);
6fe17da0 4826 }
19ba484d
OC		 4827
4828 return 0;
4829}
4830
4831static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4832{
4833 struct i2c_client *client = context;
4834 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4835
6fe17da0
OC		 4836 if (rt5677->is_dsp_mode) {
4837 if (reg > 0xff) {
4838 mutex_lock(&rt5677->dsp_pri_lock);
4839 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4840 reg & 0xff);
4841 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4842 val);
4843 mutex_unlock(&rt5677->dsp_pri_lock);
4844 } else {
4845 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4846 }
4847 } else {
19ba484d 4848 regmap_write(rt5677->regmap_physical, reg, val);
6fe17da0 4849 }
19ba484d
OC		 4850
4851 return 0;
4852}
4853
0e826e86
OC		 4854#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4855#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4856 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4857
4858static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4859 .hw_params = rt5677_hw_params,
4860 .set_fmt = rt5677_set_dai_fmt,
4861 .set_sysclk = rt5677_set_dai_sysclk,
4862 .set_pll = rt5677_set_dai_pll,
48561afe 4863 .set_tdm_slot = rt5677_set_tdm_slot,
0e826e86
OC		 4864};
4865
4866static struct snd_soc_dai_driver rt5677_dai[] = {
4867 {
4868 .name = "rt5677-aif1",
4869 .id = RT5677_AIF1,
4870 .playback = {
4871 .stream_name = "AIF1 Playback",
4872 .channels_min = 1,
4873 .channels_max = 2,
4874 .rates = RT5677_STEREO_RATES,
4875 .formats = RT5677_FORMATS,
4876 },
4877 .capture = {
4878 .stream_name = "AIF1 Capture",
4879 .channels_min = 1,
4880 .channels_max = 2,
4881 .rates = RT5677_STEREO_RATES,
4882 .formats = RT5677_FORMATS,
4883 },
4884 .ops = &rt5677_aif_dai_ops,
4885 },
4886 {
4887 .name = "rt5677-aif2",
4888 .id = RT5677_AIF2,
4889 .playback = {
4890 .stream_name = "AIF2 Playback",
4891 .channels_min = 1,
4892 .channels_max = 2,
4893 .rates = RT5677_STEREO_RATES,
4894 .formats = RT5677_FORMATS,
4895 },
4896 .capture = {
4897 .stream_name = "AIF2 Capture",
4898 .channels_min = 1,
4899 .channels_max = 2,
4900 .rates = RT5677_STEREO_RATES,
4901 .formats = RT5677_FORMATS,
4902 },
4903 .ops = &rt5677_aif_dai_ops,
4904 },
4905 {
4906 .name = "rt5677-aif3",
4907 .id = RT5677_AIF3,
4908 .playback = {
4909 .stream_name = "AIF3 Playback",
4910 .channels_min = 1,
4911 .channels_max = 2,
4912 .rates = RT5677_STEREO_RATES,
4913 .formats = RT5677_FORMATS,
4914 },
4915 .capture = {
4916 .stream_name = "AIF3 Capture",
4917 .channels_min = 1,
4918 .channels_max = 2,
4919 .rates = RT5677_STEREO_RATES,
4920 .formats = RT5677_FORMATS,
4921 },
4922 .ops = &rt5677_aif_dai_ops,
4923 },
4924 {
4925 .name = "rt5677-aif4",
4926 .id = RT5677_AIF4,
4927 .playback = {
4928 .stream_name = "AIF4 Playback",
4929 .channels_min = 1,
4930 .channels_max = 2,
4931 .rates = RT5677_STEREO_RATES,
4932 .formats = RT5677_FORMATS,
4933 },
4934 .capture = {
4935 .stream_name = "AIF4 Capture",
4936 .channels_min = 1,
4937 .channels_max = 2,
4938 .rates = RT5677_STEREO_RATES,
4939 .formats = RT5677_FORMATS,
4940 },
4941 .ops = &rt5677_aif_dai_ops,
4942 },
4943 {
4944 .name = "rt5677-slimbus",
4945 .id = RT5677_AIF5,
4946 .playback = {
4947 .stream_name = "SLIMBus Playback",
4948 .channels_min = 1,
4949 .channels_max = 2,
4950 .rates = RT5677_STEREO_RATES,
4951 .formats = RT5677_FORMATS,
4952 },
4953 .capture = {
4954 .stream_name = "SLIMBus Capture",
4955 .channels_min = 1,
4956 .channels_max = 2,
4957 .rates = RT5677_STEREO_RATES,
4958 .formats = RT5677_FORMATS,
4959 },
4960 .ops = &rt5677_aif_dai_ops,
4961 },
4962};
4963
4964static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4965 .probe = rt5677_probe,
4966 .remove = rt5677_remove,
4967 .suspend = rt5677_suspend,
4968 .resume = rt5677_resume,
4969 .set_bias_level = rt5677_set_bias_level,
4970 .idle_bias_off = true,
4971 .controls = rt5677_snd_controls,
4972 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4973 .dapm_widgets = rt5677_dapm_widgets,
4974 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4975 .dapm_routes = rt5677_dapm_routes,
4976 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4977};
4978
19ba484d
OC		 4979static const struct regmap_config rt5677_regmap_physical = {
4980 .name = "physical",
4981 .reg_bits = 8,
4982 .val_bits = 16,
4983
6fe17da0
OC		 4984 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4985 RT5677_PR_SPACING),
19ba484d
OC		 4986 .readable_reg = rt5677_readable_register,
4987
4988 .cache_type = REGCACHE_NONE,
6fe17da0
OC		 4989 .ranges = rt5677_ranges,
4990 .num_ranges = ARRAY_SIZE(rt5677_ranges),
19ba484d
OC		 4991};
4992
0e826e86
OC		 4993static const struct regmap_config rt5677_regmap = {
4994 .reg_bits = 8,
4995 .val_bits = 16,
4996
4997 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4998 RT5677_PR_SPACING),
4999
5000 .volatile_reg = rt5677_volatile_register,
5001 .readable_reg = rt5677_readable_register,
19ba484d
OC		 5002 .reg_read = rt5677_read,
5003 .reg_write = rt5677_write,
0e826e86
OC		 5004
5005 .cache_type = REGCACHE_RBTREE,
5006 .reg_defaults = rt5677_reg,
5007 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5008 .ranges = rt5677_ranges,
5009 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5010};
5011
5012static const struct i2c_device_id rt5677_i2c_id[] = {
ab1f7095
OC		 5013 { "rt5677", RT5677 },
5014 { "rt5676", RT5676 },
0e826e86
OC		 5015 { }
5016};
5017MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
5018
9bfde721
BZ		 5019static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5020 struct device *dev)
f9f6a592 5021{
9bfde721
BZ		 5022 rt5677->pdata.in1_diff = device_property_read_bool(dev,
5023 "realtek,in1-differential");
5024 rt5677->pdata.in2_diff = device_property_read_bool(dev,
5025 "realtek,in2-differential");
5026 rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5027 "realtek,lout1-differential");
5028 rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5029 "realtek,lout2-differential");
5030 rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5031 "realtek,lout3-differential");
5032
5033 device_property_read_u8_array(dev, "realtek,gpio-config",
5034 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5035
5036 device_property_read_u32(dev, "realtek,jd1-gpio",
5037 &rt5677->pdata.jd1_gpio);
5038 device_property_read_u32(dev, "realtek,jd2-gpio",
5039 &rt5677->pdata.jd2_gpio);
5040 device_property_read_u32(dev, "realtek,jd3-gpio",
5041 &rt5677->pdata.jd3_gpio);
f9f6a592
AP		 5042}
5043
5e3363ad
OC		 5044static struct regmap_irq rt5677_irqs[] = {
5045 [RT5677_IRQ_JD1] = {
5046 .reg_offset = 0,
5047 .mask = RT5677_EN_IRQ_GPIO_JD1,
5048 },
5049 [RT5677_IRQ_JD2] = {
5050 .reg_offset = 0,
5051 .mask = RT5677_EN_IRQ_GPIO_JD2,
5052 },
5053 [RT5677_IRQ_JD3] = {
5054 .reg_offset = 0,
5055 .mask = RT5677_EN_IRQ_GPIO_JD3,
5056 },
5057};
5058
5059static struct regmap_irq_chip rt5677_irq_chip = {
5060 .name = "rt5677",
5061 .irqs = rt5677_irqs,
5062 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5063
5064 .num_regs = 1,
5065 .status_base = RT5677_IRQ_CTRL1,
5066 .mask_base = RT5677_IRQ_CTRL1,
5067 .mask_invert = 1,
5068};
5069
35d40d10 5070static int rt5677_init_irq(struct i2c_client *i2c)
5e3363ad
OC		 5071{
5072 int ret;
5073 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5074
5075 if (!rt5677->pdata.jd1_gpio &&
5076 !rt5677->pdata.jd2_gpio &&
5077 !rt5677->pdata.jd3_gpio)
5078 return 0;
5079
5080 if (!i2c->irq) {
5081 dev_err(&i2c->dev, "No interrupt specified\n");
5082 return -EINVAL;
5083 }
5084
5085 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5086 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5087 &rt5677_irq_chip, &rt5677->irq_data);
5088
5089 if (ret != 0) {
5090 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5091 return ret;
5092 }
5093
5094 return 0;
5095}
5096
35d40d10 5097static void rt5677_free_irq(struct i2c_client *i2c)
5e3363ad
OC		 5098{
5099 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5100
5101 if (rt5677->irq_data)
5102 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5103}
5104
0e826e86
OC		 5105static int rt5677_i2c_probe(struct i2c_client *i2c,
5106 const struct i2c_device_id *id)
5107{
5108 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5109 struct rt5677_priv *rt5677;
5110 int ret;
5111 unsigned int val;
5112
5113 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5114 GFP_KERNEL);
5115 if (rt5677 == NULL)
5116 return -ENOMEM;
5117
5118 i2c_set_clientdata(i2c, rt5677);
5119
ab1f7095
OC		 5120 rt5677->type = id->driver_data;
5121
0e826e86
OC		 5122 if (pdata)
5123 rt5677->pdata = *pdata;
9bfde721
BZ		 5124 else
5125 rt5677_read_device_properties(rt5677, &i2c->dev);
f9f6a592 5126
efd901ee
BZ		 5127 /* pow-ldo2 and reset are optional. The codec pins may be statically
5128 * connected on the board without gpios. If the gpio device property
5129 * isn't specified, devm_gpiod_get_optional returns NULL.
5130 */
5131 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5132 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5133 if (IS_ERR(rt5677->pow_ldo2)) {
5134 ret = PTR_ERR(rt5677->pow_ldo2);
5135 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5136 rt5677->pow_ldo2 = 0;
b3b10e99 5137 }
efd901ee
BZ		 5138 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5139 "realtek,reset", GPIOD_OUT_HIGH);
5140 if (IS_ERR(rt5677->reset_pin)) {
5141 ret = PTR_ERR(rt5677->reset_pin);
5142 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5143 rt5677->reset_pin = 0;
b3b10e99
AP		 5144 }
5145
efd901ee 5146 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
f9f6a592
AP		 5147 /* Wait a while until I2C bus becomes available. The datasheet
5148 * does not specify the exact we should wait but startup
5149 * sequence mentiones at least a few milliseconds.
5150 */
5151 msleep(10);
5152 }
5153
19ba484d
OC		 5154 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5155 &rt5677_regmap_physical);
5156 if (IS_ERR(rt5677->regmap_physical)) {
5157 ret = PTR_ERR(rt5677->regmap_physical);
5158 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5159 ret);
5160 return ret;
5161 }
5162
5163 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
0e826e86
OC		 5164 if (IS_ERR(rt5677->regmap)) {
5165 ret = PTR_ERR(rt5677->regmap);
5166 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5167 ret);
5168 return ret;
5169 }
5170
5171 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5172 if (val != RT5677_DEVICE_ID) {
5173 dev_err(&i2c->dev,
aa0bcc5c 5174 "Device with ID register %#x is not rt5677\n", val);
0e826e86
OC		 5175 return -ENODEV;
5176 }
5177
5178 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5179
5180 ret = regmap_register_patch(rt5677->regmap, init_list,
5181 ARRAY_SIZE(init_list));
5182 if (ret != 0)
5183 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5184
5185 if (rt5677->pdata.in1_diff)
5186 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5187 RT5677_IN_DF1, RT5677_IN_DF1);
5188
5189 if (rt5677->pdata.in2_diff)
5190 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5191 RT5677_IN_DF2, RT5677_IN_DF2);
5192
6f67c380
AP		 5193 if (rt5677->pdata.lout1_diff)
5194 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5195 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5196
5197 if (rt5677->pdata.lout2_diff)
5198 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5199 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5200
5201 if (rt5677->pdata.lout3_diff)
5202 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5203 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5204
2d15d974
BL		 5205 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5206 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5207 RT5677_GPIO5_FUNC_MASK,
5208 RT5677_GPIO5_FUNC_DMIC);
5209 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5210 RT5677_GPIO5_DIR_MASK,
5211 RT5677_GPIO5_DIR_OUT);
5212 }
5213
277880a3
OC		 5214 if (rt5677->pdata.micbias1_vdd_3v3)
5215 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5216 RT5677_MICBIAS1_CTRL_VDD_MASK,
5217 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5218
44caf764 5219 rt5677_init_gpio(i2c);
35d40d10 5220 rt5677_init_irq(i2c);
44caf764 5221
d0bdcb91
AL		 5222 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5223 rt5677_dai, ARRAY_SIZE(rt5677_dai));
0e826e86
OC		 5224}
5225
5226static int rt5677_i2c_remove(struct i2c_client *i2c)
5227{
5228 snd_soc_unregister_codec(&i2c->dev);
35d40d10 5229 rt5677_free_irq(i2c);
44caf764 5230 rt5677_free_gpio(i2c);
0e826e86
OC		 5231
5232 return 0;
5233}
5234
5235static struct i2c_driver rt5677_i2c_driver = {
5236 .driver = {
5237 .name = "rt5677",
5238 .owner = THIS_MODULE,
5239 },
5240 .probe = rt5677_i2c_probe,
5241 .remove = rt5677_i2c_remove,
5242 .id_table = rt5677_i2c_id,
5243};
c8cfbec8 5244module_i2c_driver(rt5677_i2c_driver);
0e826e86
OC		 5245
5246MODULE_DESCRIPTION("ASoC RT5677 driver");
5247MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5248MODULE_LICENSE("GPL v2");
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