projects / mirror_ubuntu-hirsute-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 0ddce71c BL |
2 | /* |
| 3 | * rt5682.h -- RT5682/RT5658 ALSA SoC audio driver | |
| 4 | * | |
| 5 | * Copyright 2018 Realtek Microelectronics | |
| 6 | * Author: Bard Liao <bardliao@realtek.com> | |
| 0ddce71c BL |
7 | */ |
| 8 | ||
| 9 | #ifndef __RT5682_H__ | |
| 10 | #define __RT5682_H__ | |
| 11 | ||
| 12 | #include <sound/rt5682.h> | |
| 13 | ||
| 14 | #define DEVICE_ID 0x6530 | |
| 15 | ||
| 16 | /* Info */ | |
| 17 | #define RT5682_RESET 0x0000 | |
| 18 | #define RT5682_VERSION_ID 0x00fd | |
| 19 | #define RT5682_VENDOR_ID 0x00fe | |
| 20 | #define RT5682_DEVICE_ID 0x00ff | |
| 21 | /* I/O - Output */ | |
| 22 | #define RT5682_HP_CTRL_1 0x0002 | |
| 23 | #define RT5682_HP_CTRL_2 0x0003 | |
| 24 | #define RT5682_HPL_GAIN 0x0005 | |
| 25 | #define RT5682_HPR_GAIN 0x0006 | |
| 26 | ||
| 27 | #define RT5682_I2C_CTRL 0x0008 | |
| 28 | ||
| 29 | /* I/O - Input */ | |
| 30 | #define RT5682_CBJ_BST_CTRL 0x000b | |
| 31 | #define RT5682_CBJ_CTRL_1 0x0010 | |
| 32 | #define RT5682_CBJ_CTRL_2 0x0011 | |
| 33 | #define RT5682_CBJ_CTRL_3 0x0012 | |
| 34 | #define RT5682_CBJ_CTRL_4 0x0013 | |
| 35 | #define RT5682_CBJ_CTRL_5 0x0014 | |
| 36 | #define RT5682_CBJ_CTRL_6 0x0015 | |
| 37 | #define RT5682_CBJ_CTRL_7 0x0016 | |
| 38 | /* I/O - ADC/DAC/DMIC */ | |
| 39 | #define RT5682_DAC1_DIG_VOL 0x0019 | |
| 40 | #define RT5682_STO1_ADC_DIG_VOL 0x001c | |
| 41 | #define RT5682_STO1_ADC_BOOST 0x001f | |
| 42 | #define RT5682_HP_IMP_GAIN_1 0x0022 | |
| 43 | #define RT5682_HP_IMP_GAIN_2 0x0023 | |
| 44 | /* Mixer - D-D */ | |
| 45 | #define RT5682_SIDETONE_CTRL 0x0024 | |
| 46 | #define RT5682_STO1_ADC_MIXER 0x0026 | |
| 47 | #define RT5682_AD_DA_MIXER 0x0029 | |
| 48 | #define RT5682_STO1_DAC_MIXER 0x002a | |
| 49 | #define RT5682_A_DAC1_MUX 0x002b | |
| 50 | #define RT5682_DIG_INF2_DATA 0x0030 | |
| 51 | /* Mixer - ADC */ | |
| 52 | #define RT5682_REC_MIXER 0x003c | |
| 53 | #define RT5682_CAL_REC 0x0044 | |
| 54 | #define RT5682_ALC_BACK_GAIN 0x0049 | |
| 55 | /* Power */ | |
| 56 | #define RT5682_PWR_DIG_1 0x0061 | |
| 57 | #define RT5682_PWR_DIG_2 0x0062 | |
| 58 | #define RT5682_PWR_ANLG_1 0x0063 | |
| 59 | #define RT5682_PWR_ANLG_2 0x0064 | |
| 60 | #define RT5682_PWR_ANLG_3 0x0065 | |
| 61 | #define RT5682_PWR_MIXER 0x0066 | |
| 62 | #define RT5682_PWR_VOL 0x0067 | |
| 63 | /* Clock Detect */ | |
| 64 | #define RT5682_CLK_DET 0x006b | |
| 65 | /* Filter Auto Reset */ | |
| 66 | #define RT5682_RESET_LPF_CTRL 0x006c | |
| 67 | #define RT5682_RESET_HPF_CTRL 0x006d | |
| 68 | /* DMIC */ | |
| 69 | #define RT5682_DMIC_CTRL_1 0x006e | |
| 70 | /* Format - ADC/DAC */ | |
| 71 | #define RT5682_I2S1_SDP 0x0070 | |
| 72 | #define RT5682_I2S2_SDP 0x0071 | |
| 73 | #define RT5682_ADDA_CLK_1 0x0073 | |
| 74 | #define RT5682_ADDA_CLK_2 0x0074 | |
| 75 | #define RT5682_I2S1_F_DIV_CTRL_1 0x0075 | |
| 76 | #define RT5682_I2S1_F_DIV_CTRL_2 0x0076 | |
| 77 | /* Format - TDM Control */ | |
| 78 | #define RT5682_TDM_CTRL 0x0079 | |
| 79 | #define RT5682_TDM_ADDA_CTRL_1 0x007a | |
| 80 | #define RT5682_TDM_ADDA_CTRL_2 0x007b | |
| 81 | #define RT5682_DATA_SEL_CTRL_1 0x007c | |
| 82 | #define RT5682_TDM_TCON_CTRL 0x007e | |
| 83 | /* Function - Analog */ | |
| 84 | #define RT5682_GLB_CLK 0x0080 | |
| 85 | #define RT5682_PLL_CTRL_1 0x0081 | |
| 86 | #define RT5682_PLL_CTRL_2 0x0082 | |
| 87 | #define RT5682_PLL_TRACK_1 0x0083 | |
| 88 | #define RT5682_PLL_TRACK_2 0x0084 | |
| 89 | #define RT5682_PLL_TRACK_3 0x0085 | |
| 90 | #define RT5682_PLL_TRACK_4 0x0086 | |
| 91 | #define RT5682_PLL_TRACK_5 0x0087 | |
| 92 | #define RT5682_PLL_TRACK_6 0x0088 | |
| 93 | #define RT5682_PLL_TRACK_11 0x008c | |
| 94 | #define RT5682_SDW_REF_CLK 0x008d | |
| 95 | #define RT5682_DEPOP_1 0x008e | |
| 96 | #define RT5682_DEPOP_2 0x008f | |
| 97 | #define RT5682_HP_CHARGE_PUMP_1 0x0091 | |
| 98 | #define RT5682_HP_CHARGE_PUMP_2 0x0092 | |
| 99 | #define RT5682_MICBIAS_1 0x0093 | |
| 100 | #define RT5682_MICBIAS_2 0x0094 | |
| 101 | #define RT5682_PLL_TRACK_12 0x0098 | |
| 102 | #define RT5682_PLL_TRACK_14 0x009a | |
| 103 | #define RT5682_PLL2_CTRL_1 0x009b | |
| 104 | #define RT5682_PLL2_CTRL_2 0x009c | |
| 105 | #define RT5682_PLL2_CTRL_3 0x009d | |
| 106 | #define RT5682_PLL2_CTRL_4 0x009e | |
| 107 | #define RT5682_RC_CLK_CTRL 0x009f | |
| 108 | #define RT5682_I2S_M_CLK_CTRL_1 0x00a0 | |
| 109 | #define RT5682_I2S2_F_DIV_CTRL_1 0x00a3 | |
| 110 | #define RT5682_I2S2_F_DIV_CTRL_2 0x00a4 | |
| 111 | /* Function - Digital */ | |
| 112 | #define RT5682_EQ_CTRL_1 0x00ae | |
| 113 | #define RT5682_EQ_CTRL_2 0x00af | |
| 114 | #define RT5682_IRQ_CTRL_1 0x00b6 | |
| 115 | #define RT5682_IRQ_CTRL_2 0x00b7 | |
| 116 | #define RT5682_IRQ_CTRL_3 0x00b8 | |
| 117 | #define RT5682_IRQ_CTRL_4 0x00b9 | |
| 118 | #define RT5682_INT_ST_1 0x00be | |
| 119 | #define RT5682_GPIO_CTRL_1 0x00c0 | |
| 120 | #define RT5682_GPIO_CTRL_2 0x00c1 | |
| 121 | #define RT5682_GPIO_CTRL_3 0x00c2 | |
| 122 | #define RT5682_HP_AMP_DET_CTRL_1 0x00d0 | |
| 123 | #define RT5682_HP_AMP_DET_CTRL_2 0x00d1 | |
| 124 | #define RT5682_MID_HP_AMP_DET 0x00d2 | |
| 125 | #define RT5682_LOW_HP_AMP_DET 0x00d3 | |
| 126 | #define RT5682_DELAY_BUF_CTRL 0x00d4 | |
| 127 | #define RT5682_SV_ZCD_1 0x00d9 | |
| 128 | #define RT5682_SV_ZCD_2 0x00da | |
| 129 | #define RT5682_IL_CMD_1 0x00db | |
| 130 | #define RT5682_IL_CMD_2 0x00dc | |
| 131 | #define RT5682_IL_CMD_3 0x00dd | |
| 132 | #define RT5682_IL_CMD_4 0x00de | |
| 133 | #define RT5682_IL_CMD_5 0x00df | |
| 134 | #define RT5682_IL_CMD_6 0x00e0 | |
| 135 | #define RT5682_4BTN_IL_CMD_1 0x00e2 | |
| 136 | #define RT5682_4BTN_IL_CMD_2 0x00e3 | |
| 137 | #define RT5682_4BTN_IL_CMD_3 0x00e4 | |
| 138 | #define RT5682_4BTN_IL_CMD_4 0x00e5 | |
| 139 | #define RT5682_4BTN_IL_CMD_5 0x00e6 | |
| 140 | #define RT5682_4BTN_IL_CMD_6 0x00e7 | |
| 141 | #define RT5682_4BTN_IL_CMD_7 0x00e8 | |
| 142 | ||
| 143 | #define RT5682_ADC_STO1_HP_CTRL_1 0x00ea | |
| 144 | #define RT5682_ADC_STO1_HP_CTRL_2 0x00eb | |
| 145 | #define RT5682_AJD1_CTRL 0x00f0 | |
| 146 | #define RT5682_JD1_THD 0x00f1 | |
| 147 | #define RT5682_JD2_THD 0x00f2 | |
| 148 | #define RT5682_JD_CTRL_1 0x00f6 | |
| 149 | /* General Control */ | |
| 150 | #define RT5682_DUMMY_1 0x00fa | |
| 151 | #define RT5682_DUMMY_2 0x00fb | |
| 152 | #define RT5682_DUMMY_3 0x00fc | |
| 153 | ||
| 154 | #define RT5682_DAC_ADC_DIG_VOL1 0x0100 | |
| 155 | #define RT5682_BIAS_CUR_CTRL_2 0x010b | |
| 156 | #define RT5682_BIAS_CUR_CTRL_3 0x010c | |
| 157 | #define RT5682_BIAS_CUR_CTRL_4 0x010d | |
| 158 | #define RT5682_BIAS_CUR_CTRL_5 0x010e | |
| 159 | #define RT5682_BIAS_CUR_CTRL_6 0x010f | |
| 160 | #define RT5682_BIAS_CUR_CTRL_7 0x0110 | |
| 161 | #define RT5682_BIAS_CUR_CTRL_8 0x0111 | |
| 162 | #define RT5682_BIAS_CUR_CTRL_9 0x0112 | |
| 163 | #define RT5682_BIAS_CUR_CTRL_10 0x0113 | |
| 164 | #define RT5682_VREF_REC_OP_FB_CAP_CTRL 0x0117 | |
| 165 | #define RT5682_CHARGE_PUMP_1 0x0125 | |
| 166 | #define RT5682_DIG_IN_CTRL_1 0x0132 | |
| 167 | #define RT5682_PAD_DRIVING_CTRL 0x0136 | |
| 168 | #define RT5682_SOFT_RAMP_DEPOP 0x0138 | |
| 169 | #define RT5682_CHOP_DAC 0x013a | |
| 170 | #define RT5682_CHOP_ADC 0x013b | |
| 171 | #define RT5682_CALIB_ADC_CTRL 0x013c | |
| 172 | #define RT5682_VOL_TEST 0x013f | |
| 173 | #define RT5682_SPKVDD_DET_STA 0x0142 | |
| 174 | #define RT5682_TEST_MODE_CTRL_1 0x0145 | |
| 175 | #define RT5682_TEST_MODE_CTRL_2 0x0146 | |
| 176 | #define RT5682_TEST_MODE_CTRL_3 0x0147 | |
| 177 | #define RT5682_TEST_MODE_CTRL_4 0x0148 | |
| 178 | #define RT5682_TEST_MODE_CTRL_5 0x0149 | |
| 179 | #define RT5682_PLL1_INTERNAL 0x0150 | |
| 180 | #define RT5682_PLL2_INTERNAL 0x0151 | |
| 181 | #define RT5682_STO_NG2_CTRL_1 0x0160 | |
| 182 | #define RT5682_STO_NG2_CTRL_2 0x0161 | |
| 183 | #define RT5682_STO_NG2_CTRL_3 0x0162 | |
| 184 | #define RT5682_STO_NG2_CTRL_4 0x0163 | |
| 185 | #define RT5682_STO_NG2_CTRL_5 0x0164 | |
| 186 | #define RT5682_STO_NG2_CTRL_6 0x0165 | |
| 187 | #define RT5682_STO_NG2_CTRL_7 0x0166 | |
| 188 | #define RT5682_STO_NG2_CTRL_8 0x0167 | |
| 189 | #define RT5682_STO_NG2_CTRL_9 0x0168 | |
| 190 | #define RT5682_STO_NG2_CTRL_10 0x0169 | |
| 191 | #define RT5682_STO1_DAC_SIL_DET 0x0190 | |
| 192 | #define RT5682_SIL_PSV_CTRL1 0x0194 | |
| 193 | #define RT5682_SIL_PSV_CTRL2 0x0195 | |
| 194 | #define RT5682_SIL_PSV_CTRL3 0x0197 | |
| 195 | #define RT5682_SIL_PSV_CTRL4 0x0198 | |
| 196 | #define RT5682_SIL_PSV_CTRL5 0x0199 | |
| 197 | #define RT5682_HP_IMP_SENS_CTRL_01 0x01af | |
| 198 | #define RT5682_HP_IMP_SENS_CTRL_02 0x01b0 | |
| 199 | #define RT5682_HP_IMP_SENS_CTRL_03 0x01b1 | |
| 200 | #define RT5682_HP_IMP_SENS_CTRL_04 0x01b2 | |
| 201 | #define RT5682_HP_IMP_SENS_CTRL_05 0x01b3 | |
| 202 | #define RT5682_HP_IMP_SENS_CTRL_06 0x01b4 | |
| 203 | #define RT5682_HP_IMP_SENS_CTRL_07 0x01b5 | |
| 204 | #define RT5682_HP_IMP_SENS_CTRL_08 0x01b6 | |
| 205 | #define RT5682_HP_IMP_SENS_CTRL_09 0x01b7 | |
| 206 | #define RT5682_HP_IMP_SENS_CTRL_10 0x01b8 | |
| 207 | #define RT5682_HP_IMP_SENS_CTRL_11 0x01b9 | |
| 208 | #define RT5682_HP_IMP_SENS_CTRL_12 0x01ba | |
| 209 | #define RT5682_HP_IMP_SENS_CTRL_13 0x01bb | |
| 210 | #define RT5682_HP_IMP_SENS_CTRL_14 0x01bc | |
| 211 | #define RT5682_HP_IMP_SENS_CTRL_15 0x01bd | |
| 212 | #define RT5682_HP_IMP_SENS_CTRL_16 0x01be | |
| 213 | #define RT5682_HP_IMP_SENS_CTRL_17 0x01bf | |
| 214 | #define RT5682_HP_IMP_SENS_CTRL_18 0x01c0 | |
| 215 | #define RT5682_HP_IMP_SENS_CTRL_19 0x01c1 | |
| 216 | #define RT5682_HP_IMP_SENS_CTRL_20 0x01c2 | |
| 217 | #define RT5682_HP_IMP_SENS_CTRL_21 0x01c3 | |
| 218 | #define RT5682_HP_IMP_SENS_CTRL_22 0x01c4 | |
| 219 | #define RT5682_HP_IMP_SENS_CTRL_23 0x01c5 | |
| 220 | #define RT5682_HP_IMP_SENS_CTRL_24 0x01c6 | |
| 221 | #define RT5682_HP_IMP_SENS_CTRL_25 0x01c7 | |
| 222 | #define RT5682_HP_IMP_SENS_CTRL_26 0x01c8 | |
| 223 | #define RT5682_HP_IMP_SENS_CTRL_27 0x01c9 | |
| 224 | #define RT5682_HP_IMP_SENS_CTRL_28 0x01ca | |
| 225 | #define RT5682_HP_IMP_SENS_CTRL_29 0x01cb | |
| 226 | #define RT5682_HP_IMP_SENS_CTRL_30 0x01cc | |
| 227 | #define RT5682_HP_IMP_SENS_CTRL_31 0x01cd | |
| 228 | #define RT5682_HP_IMP_SENS_CTRL_32 0x01ce | |
| 229 | #define RT5682_HP_IMP_SENS_CTRL_33 0x01cf | |
| 230 | #define RT5682_HP_IMP_SENS_CTRL_34 0x01d0 | |
| 231 | #define RT5682_HP_IMP_SENS_CTRL_35 0x01d1 | |
| 232 | #define RT5682_HP_IMP_SENS_CTRL_36 0x01d2 | |
| 233 | #define RT5682_HP_IMP_SENS_CTRL_37 0x01d3 | |
| 234 | #define RT5682_HP_IMP_SENS_CTRL_38 0x01d4 | |
| 235 | #define RT5682_HP_IMP_SENS_CTRL_39 0x01d5 | |
| 236 | #define RT5682_HP_IMP_SENS_CTRL_40 0x01d6 | |
| 237 | #define RT5682_HP_IMP_SENS_CTRL_41 0x01d7 | |
| 238 | #define RT5682_HP_IMP_SENS_CTRL_42 0x01d8 | |
| 239 | #define RT5682_HP_IMP_SENS_CTRL_43 0x01d9 | |
| 240 | #define RT5682_HP_LOGIC_CTRL_1 0x01da | |
| 241 | #define RT5682_HP_LOGIC_CTRL_2 0x01db | |
| 242 | #define RT5682_HP_LOGIC_CTRL_3 0x01dc | |
| 243 | #define RT5682_HP_CALIB_CTRL_1 0x01de | |
| 244 | #define RT5682_HP_CALIB_CTRL_2 0x01df | |
| 245 | #define RT5682_HP_CALIB_CTRL_3 0x01e0 | |
| 246 | #define RT5682_HP_CALIB_CTRL_4 0x01e1 | |
| 247 | #define RT5682_HP_CALIB_CTRL_5 0x01e2 | |
| 248 | #define RT5682_HP_CALIB_CTRL_6 0x01e3 | |
| 249 | #define RT5682_HP_CALIB_CTRL_7 0x01e4 | |
| 250 | #define RT5682_HP_CALIB_CTRL_9 0x01e6 | |
| 251 | #define RT5682_HP_CALIB_CTRL_10 0x01e7 | |
| 252 | #define RT5682_HP_CALIB_CTRL_11 0x01e8 | |
| 253 | #define RT5682_HP_CALIB_STA_1 0x01ea | |
| 254 | #define RT5682_HP_CALIB_STA_2 0x01eb | |
| 255 | #define RT5682_HP_CALIB_STA_3 0x01ec | |
| 256 | #define RT5682_HP_CALIB_STA_4 0x01ed | |
| 257 | #define RT5682_HP_CALIB_STA_5 0x01ee | |
| 258 | #define RT5682_HP_CALIB_STA_6 0x01ef | |
| 259 | #define RT5682_HP_CALIB_STA_7 0x01f0 | |
| 260 | #define RT5682_HP_CALIB_STA_8 0x01f1 | |
| 261 | #define RT5682_HP_CALIB_STA_9 0x01f2 | |
| 262 | #define RT5682_HP_CALIB_STA_10 0x01f3 | |
| 263 | #define RT5682_HP_CALIB_STA_11 0x01f4 | |
| 264 | #define RT5682_SAR_IL_CMD_1 0x0210 | |
| 265 | #define RT5682_SAR_IL_CMD_2 0x0211 | |
| 266 | #define RT5682_SAR_IL_CMD_3 0x0212 | |
| 267 | #define RT5682_SAR_IL_CMD_4 0x0213 | |
| 268 | #define RT5682_SAR_IL_CMD_5 0x0214 | |
| 269 | #define RT5682_SAR_IL_CMD_6 0x0215 | |
| 270 | #define RT5682_SAR_IL_CMD_7 0x0216 | |
| 271 | #define RT5682_SAR_IL_CMD_8 0x0217 | |
| 272 | #define RT5682_SAR_IL_CMD_9 0x0218 | |
| 273 | #define RT5682_SAR_IL_CMD_10 0x0219 | |
| 274 | #define RT5682_SAR_IL_CMD_11 0x021a | |
| 275 | #define RT5682_SAR_IL_CMD_12 0x021b | |
| 276 | #define RT5682_SAR_IL_CMD_13 0x021c | |
| 277 | #define RT5682_EFUSE_CTRL_1 0x0250 | |
| 278 | #define RT5682_EFUSE_CTRL_2 0x0251 | |
| 279 | #define RT5682_EFUSE_CTRL_3 0x0252 | |
| 280 | #define RT5682_EFUSE_CTRL_4 0x0253 | |
| 281 | #define RT5682_EFUSE_CTRL_5 0x0254 | |
| 282 | #define RT5682_EFUSE_CTRL_6 0x0255 | |
| 283 | #define RT5682_EFUSE_CTRL_7 0x0256 | |
| 284 | #define RT5682_EFUSE_CTRL_8 0x0257 | |
| 285 | #define RT5682_EFUSE_CTRL_9 0x0258 | |
| 286 | #define RT5682_EFUSE_CTRL_10 0x0259 | |
| 287 | #define RT5682_EFUSE_CTRL_11 0x025a | |
| 288 | #define RT5682_JD_TOP_VC_VTRL 0x0270 | |
| 289 | #define RT5682_DRC1_CTRL_0 0x02ff | |
| 290 | #define RT5682_DRC1_CTRL_1 0x0300 | |
| 291 | #define RT5682_DRC1_CTRL_2 0x0301 | |
| 292 | #define RT5682_DRC1_CTRL_3 0x0302 | |
| 293 | #define RT5682_DRC1_CTRL_4 0x0303 | |
| 294 | #define RT5682_DRC1_CTRL_5 0x0304 | |
| 295 | #define RT5682_DRC1_CTRL_6 0x0305 | |
| 296 | #define RT5682_DRC1_HARD_LMT_CTRL_1 0x0306 | |
| 297 | #define RT5682_DRC1_HARD_LMT_CTRL_2 0x0307 | |
| 298 | #define RT5682_DRC1_PRIV_1 0x0310 | |
| 299 | #define RT5682_DRC1_PRIV_2 0x0311 | |
| 300 | #define RT5682_DRC1_PRIV_3 0x0312 | |
| 301 | #define RT5682_DRC1_PRIV_4 0x0313 | |
| 302 | #define RT5682_DRC1_PRIV_5 0x0314 | |
| 303 | #define RT5682_DRC1_PRIV_6 0x0315 | |
| 304 | #define RT5682_DRC1_PRIV_7 0x0316 | |
| 305 | #define RT5682_DRC1_PRIV_8 0x0317 | |
| 306 | #define RT5682_EQ_AUTO_RCV_CTRL1 0x03c0 | |
| 307 | #define RT5682_EQ_AUTO_RCV_CTRL2 0x03c1 | |
| 308 | #define RT5682_EQ_AUTO_RCV_CTRL3 0x03c2 | |
| 309 | #define RT5682_EQ_AUTO_RCV_CTRL4 0x03c3 | |
| 310 | #define RT5682_EQ_AUTO_RCV_CTRL5 0x03c4 | |
| 311 | #define RT5682_EQ_AUTO_RCV_CTRL6 0x03c5 | |
| 312 | #define RT5682_EQ_AUTO_RCV_CTRL7 0x03c6 | |
| 313 | #define RT5682_EQ_AUTO_RCV_CTRL8 0x03c7 | |
| 314 | #define RT5682_EQ_AUTO_RCV_CTRL9 0x03c8 | |
| 315 | #define RT5682_EQ_AUTO_RCV_CTRL10 0x03c9 | |
| 316 | #define RT5682_EQ_AUTO_RCV_CTRL11 0x03ca | |
| 317 | #define RT5682_EQ_AUTO_RCV_CTRL12 0x03cb | |
| 318 | #define RT5682_EQ_AUTO_RCV_CTRL13 0x03cc | |
| 319 | #define RT5682_ADC_L_EQ_LPF1_A1 0x03d0 | |
| 320 | #define RT5682_R_EQ_LPF1_A1 0x03d1 | |
| 321 | #define RT5682_L_EQ_LPF1_H0 0x03d2 | |
| 322 | #define RT5682_R_EQ_LPF1_H0 0x03d3 | |
| 323 | #define RT5682_L_EQ_BPF1_A1 0x03d4 | |
| 324 | #define RT5682_R_EQ_BPF1_A1 0x03d5 | |
| 325 | #define RT5682_L_EQ_BPF1_A2 0x03d6 | |
| 326 | #define RT5682_R_EQ_BPF1_A2 0x03d7 | |
| 327 | #define RT5682_L_EQ_BPF1_H0 0x03d8 | |
| 328 | #define RT5682_R_EQ_BPF1_H0 0x03d9 | |
| 329 | #define RT5682_L_EQ_BPF2_A1 0x03da | |
| 330 | #define RT5682_R_EQ_BPF2_A1 0x03db | |
| 331 | #define RT5682_L_EQ_BPF2_A2 0x03dc | |
| 332 | #define RT5682_R_EQ_BPF2_A2 0x03dd | |
| 333 | #define RT5682_L_EQ_BPF2_H0 0x03de | |
| 334 | #define RT5682_R_EQ_BPF2_H0 0x03df | |
| 335 | #define RT5682_L_EQ_BPF3_A1 0x03e0 | |
| 336 | #define RT5682_R_EQ_BPF3_A1 0x03e1 | |
| 337 | #define RT5682_L_EQ_BPF3_A2 0x03e2 | |
| 338 | #define RT5682_R_EQ_BPF3_A2 0x03e3 | |
| 339 | #define RT5682_L_EQ_BPF3_H0 0x03e4 | |
| 340 | #define RT5682_R_EQ_BPF3_H0 0x03e5 | |
| 341 | #define RT5682_L_EQ_BPF4_A1 0x03e6 | |
| 342 | #define RT5682_R_EQ_BPF4_A1 0x03e7 | |
| 343 | #define RT5682_L_EQ_BPF4_A2 0x03e8 | |
| 344 | #define RT5682_R_EQ_BPF4_A2 0x03e9 | |
| 345 | #define RT5682_L_EQ_BPF4_H0 0x03ea | |
| 346 | #define RT5682_R_EQ_BPF4_H0 0x03eb | |
| 347 | #define RT5682_L_EQ_HPF1_A1 0x03ec | |
| 348 | #define RT5682_R_EQ_HPF1_A1 0x03ed | |
| 349 | #define RT5682_L_EQ_HPF1_H0 0x03ee | |
| 350 | #define RT5682_R_EQ_HPF1_H0 0x03ef | |
| 351 | #define RT5682_L_EQ_PRE_VOL 0x03f0 | |
| 352 | #define RT5682_R_EQ_PRE_VOL 0x03f1 | |
| 353 | #define RT5682_L_EQ_POST_VOL 0x03f2 | |
| 354 | #define RT5682_R_EQ_POST_VOL 0x03f3 | |
| 355 | #define RT5682_I2C_MODE 0xffff | |
| 356 | ||
| 357 | ||
| 358 | /* global definition */ | |
| 359 | #define RT5682_L_MUTE (0x1 << 15) | |
| 360 | #define RT5682_L_MUTE_SFT 15 | |
| 361 | #define RT5682_VOL_L_MUTE (0x1 << 14) | |
| 362 | #define RT5682_VOL_L_SFT 14 | |
| 363 | #define RT5682_R_MUTE (0x1 << 7) | |
| 364 | #define RT5682_R_MUTE_SFT 7 | |
| 365 | #define RT5682_VOL_R_MUTE (0x1 << 6) | |
| 366 | #define RT5682_VOL_R_SFT 6 | |
| 367 | #define RT5682_L_VOL_MASK (0x3f << 8) | |
| 368 | #define RT5682_L_VOL_SFT 8 | |
| 369 | #define RT5682_R_VOL_MASK (0x3f) | |
| 370 | #define RT5682_R_VOL_SFT 0 | |
| 371 | ||
| 372 | /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ | |
| 373 | #define RT5682_G_HP (0xf << 8) | |
| 374 | #define RT5682_G_HP_SFT 8 | |
| 375 | #define RT5682_G_STO_DA_DMIX (0xf) | |
| 376 | #define RT5682_G_STO_DA_SFT 0 | |
| 377 | ||
| 378 | /* CBJ Control (0x000b) */ | |
| 379 | #define RT5682_BST_CBJ_MASK (0xf << 8) | |
| 380 | #define RT5682_BST_CBJ_SFT 8 | |
| 381 | ||
| 382 | /* Embeeded Jack and Type Detection Control 1 (0x0010) */ | |
| 383 | #define RT5682_EMB_JD_EN (0x1 << 15) | |
| 384 | #define RT5682_EMB_JD_EN_SFT 15 | |
| 385 | #define RT5682_EMB_JD_RST (0x1 << 14) | |
| 386 | #define RT5682_JD_MODE (0x1 << 13) | |
| 387 | #define RT5682_JD_MODE_SFT 13 | |
| 388 | #define RT5682_DET_TYPE (0x1 << 12) | |
| 389 | #define RT5682_DET_TYPE_SFT 12 | |
| 390 | #define RT5682_POLA_EXT_JD_MASK (0x1 << 11) | |
| 391 | #define RT5682_POLA_EXT_JD_LOW (0x1 << 11) | |
| 392 | #define RT5682_POLA_EXT_JD_HIGH (0x0 << 11) | |
| 393 | #define RT5682_EXT_JD_DIG (0x1 << 9) | |
| 394 | #define RT5682_POL_FAST_OFF_MASK (0x1 << 8) | |
| 395 | #define RT5682_POL_FAST_OFF_HIGH (0x1 << 8) | |
| 396 | #define RT5682_POL_FAST_OFF_LOW (0x0 << 8) | |
| 397 | #define RT5682_FAST_OFF_MASK (0x1 << 7) | |
| 398 | #define RT5682_FAST_OFF_EN (0x1 << 7) | |
| 399 | #define RT5682_FAST_OFF_DIS (0x0 << 7) | |
| 400 | #define RT5682_VREF_POW_MASK (0x1 << 6) | |
| 401 | #define RT5682_VREF_POW_FSM (0x0 << 6) | |
| 402 | #define RT5682_VREF_POW_REG (0x1 << 6) | |
| 403 | #define RT5682_MB1_PATH_MASK (0x1 << 5) | |
| 404 | #define RT5682_CTRL_MB1_REG (0x1 << 5) | |
| 405 | #define RT5682_CTRL_MB1_FSM (0x0 << 5) | |
| 406 | #define RT5682_MB2_PATH_MASK (0x1 << 4) | |
| 407 | #define RT5682_CTRL_MB2_REG (0x1 << 4) | |
| 408 | #define RT5682_CTRL_MB2_FSM (0x0 << 4) | |
| 409 | #define RT5682_TRIG_JD_MASK (0x1 << 3) | |
| 410 | #define RT5682_TRIG_JD_HIGH (0x1 << 3) | |
| 411 | #define RT5682_TRIG_JD_LOW (0x0 << 3) | |
| 412 | #define RT5682_MIC_CAP_MASK (0x1 << 1) | |
| 413 | #define RT5682_MIC_CAP_HS (0x1 << 1) | |
| 414 | #define RT5682_MIC_CAP_HP (0x0 << 1) | |
| 415 | #define RT5682_MIC_CAP_SRC_MASK (0x1) | |
| 416 | #define RT5682_MIC_CAP_SRC_REG (0x1) | |
| 417 | #define RT5682_MIC_CAP_SRC_ANA (0x0) | |
| 418 | ||
| 419 | /* Embeeded Jack and Type Detection Control 2 (0x0011) */ | |
| 420 | #define RT5682_EXT_JD_SRC (0x7 << 4) | |
| 421 | #define RT5682_EXT_JD_SRC_SFT 4 | |
| 422 | #define RT5682_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) | |
| 423 | #define RT5682_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) | |
| 424 | #define RT5682_EXT_JD_SRC_JDH (0x2 << 4) | |
| 425 | #define RT5682_EXT_JD_SRC_JDL (0x3 << 4) | |
| 426 | #define RT5682_EXT_JD_SRC_MANUAL (0x4 << 4) | |
| 427 | #define RT5682_JACK_TYPE_MASK (0x3) | |
| 428 | ||
| 429 | /* Combo Jack and Type Detection Control 3 (0x0012) */ | |
| 430 | #define RT5682_CBJ_IN_BUF_EN (0x1 << 7) | |
| 431 | ||
| 432 | /* Combo Jack and Type Detection Control 4 (0x0013) */ | |
| 433 | #define RT5682_SEL_SHT_MID_TON_MASK (0x3 << 12) | |
| 434 | #define RT5682_SEL_SHT_MID_TON_2 (0x0 << 12) | |
| 435 | #define RT5682_SEL_SHT_MID_TON_3 (0x1 << 12) | |
| 436 | #define RT5682_CBJ_JD_TEST_MASK (0x1 << 6) | |
| 437 | #define RT5682_CBJ_JD_TEST_NORM (0x0 << 6) | |
| 438 | #define RT5682_CBJ_JD_TEST_MODE (0x1 << 6) | |
| 439 | ||
| 440 | /* DAC1 Digital Volume (0x0019) */ | |
| 441 | #define RT5682_DAC_L1_VOL_MASK (0xff << 8) | |
| 442 | #define RT5682_DAC_L1_VOL_SFT 8 | |
| 443 | #define RT5682_DAC_R1_VOL_MASK (0xff) | |
| 444 | #define RT5682_DAC_R1_VOL_SFT 0 | |
| 445 | ||
| 446 | /* ADC Digital Volume Control (0x001c) */ | |
| 447 | #define RT5682_ADC_L_VOL_MASK (0x7f << 8) | |
| 448 | #define RT5682_ADC_L_VOL_SFT 8 | |
| 449 | #define RT5682_ADC_R_VOL_MASK (0x7f) | |
| 450 | #define RT5682_ADC_R_VOL_SFT 0 | |
| 451 | ||
| 452 | /* Stereo1 ADC Boost Gain Control (0x001f) */ | |
| 453 | #define RT5682_STO1_ADC_L_BST_MASK (0x3 << 14) | |
| 454 | #define RT5682_STO1_ADC_L_BST_SFT 14 | |
| 455 | #define RT5682_STO1_ADC_R_BST_MASK (0x3 << 12) | |
| 456 | #define RT5682_STO1_ADC_R_BST_SFT 12 | |
| 457 | ||
| 458 | /* Sidetone Control (0x0024) */ | |
| 459 | #define RT5682_ST_SRC_SEL (0x1 << 8) | |
| 460 | #define RT5682_ST_SRC_SFT 8 | |
| 461 | #define RT5682_ST_EN_MASK (0x1 << 6) | |
| 462 | #define RT5682_ST_DIS (0x0 << 6) | |
| 463 | #define RT5682_ST_EN (0x1 << 6) | |
| 464 | #define RT5682_ST_EN_SFT 6 | |
| 465 | ||
| 466 | /* Stereo1 ADC Mixer Control (0x0026) */ | |
| 467 | #define RT5682_M_STO1_ADC_L1 (0x1 << 15) | |
| 468 | #define RT5682_M_STO1_ADC_L1_SFT 15 | |
| 469 | #define RT5682_M_STO1_ADC_L2 (0x1 << 14) | |
| 470 | #define RT5682_M_STO1_ADC_L2_SFT 14 | |
| 471 | #define RT5682_STO1_ADC1L_SRC_MASK (0x1 << 13) | |
| 472 | #define RT5682_STO1_ADC1L_SRC_SFT 13 | |
| 473 | #define RT5682_STO1_ADC1_SRC_ADC (0x1 << 13) | |
| 474 | #define RT5682_STO1_ADC1_SRC_DACMIX (0x0 << 13) | |
| 475 | #define RT5682_STO1_ADC2L_SRC_MASK (0x1 << 12) | |
| 476 | #define RT5682_STO1_ADC2L_SRC_SFT 12 | |
| 477 | #define RT5682_STO1_ADCL_SRC_MASK (0x3 << 10) | |
| 478 | #define RT5682_STO1_ADCL_SRC_SFT 10 | |
| 479 | #define RT5682_STO1_DD_L_SRC_MASK (0x1 << 9) | |
| 480 | #define RT5682_STO1_DD_L_SRC_SFT 9 | |
| 481 | #define RT5682_STO1_DMIC_SRC_MASK (0x1 << 8) | |
| 482 | #define RT5682_STO1_DMIC_SRC_SFT 8 | |
| 483 | #define RT5682_STO1_DMIC_SRC_DMIC2 (0x1 << 8) | |
| 484 | #define RT5682_STO1_DMIC_SRC_DMIC1 (0x0 << 8) | |
| 485 | #define RT5682_M_STO1_ADC_R1 (0x1 << 7) | |
| 486 | #define RT5682_M_STO1_ADC_R1_SFT 7 | |
| 487 | #define RT5682_M_STO1_ADC_R2 (0x1 << 6) | |
| 488 | #define RT5682_M_STO1_ADC_R2_SFT 6 | |
| 489 | #define RT5682_STO1_ADC1R_SRC_MASK (0x1 << 5) | |
| 490 | #define RT5682_STO1_ADC1R_SRC_SFT 5 | |
| 491 | #define RT5682_STO1_ADC2R_SRC_MASK (0x1 << 4) | |
| 492 | #define RT5682_STO1_ADC2R_SRC_SFT 4 | |
| 493 | #define RT5682_STO1_ADCR_SRC_MASK (0x3 << 2) | |
| 494 | #define RT5682_STO1_ADCR_SRC_SFT 2 | |
| 495 | ||
| 496 | /* ADC Mixer to DAC Mixer Control (0x0029) */ | |
| 497 | #define RT5682_M_ADCMIX_L (0x1 << 15) | |
| 498 | #define RT5682_M_ADCMIX_L_SFT 15 | |
| 499 | #define RT5682_M_DAC1_L (0x1 << 14) | |
| 500 | #define RT5682_M_DAC1_L_SFT 14 | |
| 501 | #define RT5682_DAC1_R_SEL_MASK (0x1 << 10) | |
| 502 | #define RT5682_DAC1_R_SEL_SFT 10 | |
| 503 | #define RT5682_DAC1_L_SEL_MASK (0x1 << 8) | |
| 504 | #define RT5682_DAC1_L_SEL_SFT 8 | |
| 505 | #define RT5682_M_ADCMIX_R (0x1 << 7) | |
| 506 | #define RT5682_M_ADCMIX_R_SFT 7 | |
| 507 | #define RT5682_M_DAC1_R (0x1 << 6) | |
| 508 | #define RT5682_M_DAC1_R_SFT 6 | |
| 509 | ||
| 510 | /* Stereo1 DAC Mixer Control (0x002a) */ | |
| 511 | #define RT5682_M_DAC_L1_STO_L (0x1 << 15) | |
| 512 | #define RT5682_M_DAC_L1_STO_L_SFT 15 | |
| 513 | #define RT5682_G_DAC_L1_STO_L_MASK (0x1 << 14) | |
| 514 | #define RT5682_G_DAC_L1_STO_L_SFT 14 | |
| 515 | #define RT5682_M_DAC_R1_STO_L (0x1 << 13) | |
| 516 | #define RT5682_M_DAC_R1_STO_L_SFT 13 | |
| 517 | #define RT5682_G_DAC_R1_STO_L_MASK (0x1 << 12) | |
| 518 | #define RT5682_G_DAC_R1_STO_L_SFT 12 | |
| 519 | #define RT5682_M_DAC_L1_STO_R (0x1 << 7) | |
| 520 | #define RT5682_M_DAC_L1_STO_R_SFT 7 | |
| 521 | #define RT5682_G_DAC_L1_STO_R_MASK (0x1 << 6) | |
| 522 | #define RT5682_G_DAC_L1_STO_R_SFT 6 | |
| 523 | #define RT5682_M_DAC_R1_STO_R (0x1 << 5) | |
| 524 | #define RT5682_M_DAC_R1_STO_R_SFT 5 | |
| 525 | #define RT5682_G_DAC_R1_STO_R_MASK (0x1 << 4) | |
| 526 | #define RT5682_G_DAC_R1_STO_R_SFT 4 | |
| 527 | ||
| 528 | /* Analog DAC1 Input Source Control (0x002b) */ | |
| 529 | #define RT5682_M_ST_STO_L (0x1 << 9) | |
| 530 | #define RT5682_M_ST_STO_L_SFT 9 | |
| 531 | #define RT5682_M_ST_STO_R (0x1 << 8) | |
| 532 | #define RT5682_M_ST_STO_R_SFT 8 | |
| 533 | #define RT5682_DAC_L1_SRC_MASK (0x3 << 4) | |
| 534 | #define RT5682_A_DACL1_SFT 4 | |
| 535 | #define RT5682_DAC_R1_SRC_MASK (0x3) | |
| 536 | #define RT5682_A_DACR1_SFT 0 | |
| 537 | ||
| 538 | /* Digital Interface Data Control (0x0030) */ | |
| 539 | #define RT5682_IF2_ADC_SEL_MASK (0x3 << 0) | |
| 540 | #define RT5682_IF2_ADC_SEL_SFT 0 | |
| 541 | ||
| 542 | /* REC Left Mixer Control 2 (0x003c) */ | |
| 543 | #define RT5682_G_CBJ_RM1_L (0x7 << 10) | |
| 544 | #define RT5682_G_CBJ_RM1_L_SFT 10 | |
| 545 | #define RT5682_M_CBJ_RM1_L (0x1 << 7) | |
| 546 | #define RT5682_M_CBJ_RM1_L_SFT 7 | |
| 547 | ||
| 548 | /* Power Management for Digital 1 (0x0061) */ | |
| 549 | #define RT5682_PWR_I2S1 (0x1 << 15) | |
| 550 | #define RT5682_PWR_I2S1_BIT 15 | |
| 551 | #define RT5682_PWR_I2S2 (0x1 << 14) | |
| 552 | #define RT5682_PWR_I2S2_BIT 14 | |
| 553 | #define RT5682_PWR_DAC_L1 (0x1 << 11) | |
| 554 | #define RT5682_PWR_DAC_L1_BIT 11 | |
| 555 | #define RT5682_PWR_DAC_R1 (0x1 << 10) | |
| 556 | #define RT5682_PWR_DAC_R1_BIT 10 | |
| 557 | #define RT5682_PWR_LDO (0x1 << 8) | |
| 558 | #define RT5682_PWR_LDO_BIT 8 | |
| 559 | #define RT5682_PWR_ADC_L1 (0x1 << 4) | |
| 560 | #define RT5682_PWR_ADC_L1_BIT 4 | |
| 561 | #define RT5682_PWR_ADC_R1 (0x1 << 3) | |
| 562 | #define RT5682_PWR_ADC_R1_BIT 3 | |
| 563 | #define RT5682_DIG_GATE_CTRL (0x1 << 0) | |
| 564 | #define RT5682_DIG_GATE_CTRL_SFT 0 | |
| 565 | ||
| 566 | ||
| 567 | /* Power Management for Digital 2 (0x0062) */ | |
| 568 | #define RT5682_PWR_ADC_S1F (0x1 << 15) | |
| 569 | #define RT5682_PWR_ADC_S1F_BIT 15 | |
| 570 | #define RT5682_PWR_DAC_S1F (0x1 << 10) | |
| 571 | #define RT5682_PWR_DAC_S1F_BIT 10 | |
| 572 | ||
| 573 | /* Power Management for Analog 1 (0x0063) */ | |
| 574 | #define RT5682_PWR_VREF1 (0x1 << 15) | |
| 575 | #define RT5682_PWR_VREF1_BIT 15 | |
| 576 | #define RT5682_PWR_FV1 (0x1 << 14) | |
| 577 | #define RT5682_PWR_FV1_BIT 14 | |
| 578 | #define RT5682_PWR_VREF2 (0x1 << 13) | |
| 579 | #define RT5682_PWR_VREF2_BIT 13 | |
| 580 | #define RT5682_PWR_FV2 (0x1 << 12) | |
| 581 | #define RT5682_PWR_FV2_BIT 12 | |
| 582 | #define RT5682_LDO1_DBG_MASK (0x3 << 10) | |
| 583 | #define RT5682_PWR_MB (0x1 << 9) | |
| 584 | #define RT5682_PWR_MB_BIT 9 | |
| 585 | #define RT5682_PWR_BG (0x1 << 7) | |
| 586 | #define RT5682_PWR_BG_BIT 7 | |
| 587 | #define RT5682_LDO1_BYPASS_MASK (0x1 << 6) | |
| 588 | #define RT5682_LDO1_BYPASS (0x1 << 6) | |
| 589 | #define RT5682_LDO1_NOT_BYPASS (0x0 << 6) | |
| 590 | #define RT5682_PWR_MA_BIT 6 | |
| 591 | #define RT5682_LDO1_DVO_MASK (0x3 << 4) | |
| 592 | #define RT5682_LDO1_DVO_09 (0x0 << 4) | |
| 593 | #define RT5682_LDO1_DVO_10 (0x1 << 4) | |
| 594 | #define RT5682_LDO1_DVO_12 (0x2 << 4) | |
| 595 | #define RT5682_LDO1_DVO_14 (0x3 << 4) | |
| 596 | #define RT5682_HP_DRIVER_MASK (0x3 << 2) | |
| 597 | #define RT5682_HP_DRIVER_1X (0x0 << 2) | |
| 598 | #define RT5682_HP_DRIVER_3X (0x1 << 2) | |
| 599 | #define RT5682_HP_DRIVER_5X (0x3 << 2) | |
| 600 | #define RT5682_PWR_HA_L (0x1 << 1) | |
| 601 | #define RT5682_PWR_HA_L_BIT 1 | |
| 602 | #define RT5682_PWR_HA_R (0x1 << 0) | |
| 603 | #define RT5682_PWR_HA_R_BIT 0 | |
| 604 | ||
| 605 | /* Power Management for Analog 2 (0x0064) */ | |
| 606 | #define RT5682_PWR_MB1 (0x1 << 11) | |
| 607 | #define RT5682_PWR_MB1_PWR_DOWN (0x0 << 11) | |
| 608 | #define RT5682_PWR_MB1_BIT 11 | |
| 609 | #define RT5682_PWR_MB2 (0x1 << 10) | |
| 610 | #define RT5682_PWR_MB2_PWR_DOWN (0x0 << 10) | |
| 611 | #define RT5682_PWR_MB2_BIT 10 | |
| 612 | #define RT5682_PWR_JDH (0x1 << 3) | |
| 613 | #define RT5682_PWR_JDH_BIT 3 | |
| 614 | #define RT5682_PWR_JDL (0x1 << 2) | |
| 615 | #define RT5682_PWR_JDL_BIT 2 | |
| 616 | #define RT5682_PWR_RM1_L (0x1 << 1) | |
| 617 | #define RT5682_PWR_RM1_L_BIT 1 | |
| 618 | ||
| 619 | /* Power Management for Analog 3 (0x0065) */ | |
| 620 | #define RT5682_PWR_CBJ (0x1 << 9) | |
| 621 | #define RT5682_PWR_CBJ_BIT 9 | |
| 622 | #define RT5682_PWR_PLL (0x1 << 6) | |
| 623 | #define RT5682_PWR_PLL_BIT 6 | |
| 624 | #define RT5682_PWR_PLL2B (0x1 << 5) | |
| 625 | #define RT5682_PWR_PLL2B_BIT 5 | |
| 626 | #define RT5682_PWR_PLL2F (0x1 << 4) | |
| 627 | #define RT5682_PWR_PLL2F_BIT 4 | |
| 628 | #define RT5682_PWR_LDO2 (0x1 << 2) | |
| 629 | #define RT5682_PWR_LDO2_BIT 2 | |
| 630 | #define RT5682_PWR_DET_SPKVDD (0x1 << 1) | |
| 631 | #define RT5682_PWR_DET_SPKVDD_BIT 1 | |
| 632 | ||
| 633 | /* Power Management for Mixer (0x0066) */ | |
| 634 | #define RT5682_PWR_STO1_DAC_L (0x1 << 5) | |
| 635 | #define RT5682_PWR_STO1_DAC_L_BIT 5 | |
| 636 | #define RT5682_PWR_STO1_DAC_R (0x1 << 4) | |
| 637 | #define RT5682_PWR_STO1_DAC_R_BIT 4 | |
| 638 | ||
| 639 | /* MCLK and System Clock Detection Control (0x006b) */ | |
| 640 | #define RT5682_SYS_CLK_DET (0x1 << 15) | |
| 641 | #define RT5682_SYS_CLK_DET_SFT 15 | |
| 642 | #define RT5682_PLL1_CLK_DET (0x1 << 14) | |
| 643 | #define RT5682_PLL1_CLK_DET_SFT 14 | |
| 644 | #define RT5682_PLL2_CLK_DET (0x1 << 13) | |
| 645 | #define RT5682_PLL2_CLK_DET_SFT 13 | |
| 646 | #define RT5682_POW_CLK_DET2_SFT 8 | |
| 647 | #define RT5682_POW_CLK_DET_SFT 0 | |
| 648 | ||
| 649 | /* Digital Microphone Control 1 (0x006e) */ | |
| 650 | #define RT5682_DMIC_1_EN_MASK (0x1 << 15) | |
| 651 | #define RT5682_DMIC_1_EN_SFT 15 | |
| 652 | #define RT5682_DMIC_1_DIS (0x0 << 15) | |
| 653 | #define RT5682_DMIC_1_EN (0x1 << 15) | |
| 654 | #define RT5682_DMIC_1_DP_MASK (0x3 << 4) | |
| 655 | #define RT5682_DMIC_1_DP_SFT 4 | |
| 656 | #define RT5682_DMIC_1_DP_GPIO2 (0x0 << 4) | |
| 657 | #define RT5682_DMIC_1_DP_GPIO5 (0x1 << 4) | |
| 658 | #define RT5682_DMIC_CLK_MASK (0xf << 0) | |
| 659 | #define RT5682_DMIC_CLK_SFT 0 | |
| 660 | ||
| 661 | /* I2S1 Audio Serial Data Port Control (0x0070) */ | |
| 662 | #define RT5682_SEL_ADCDAT_MASK (0x1 << 15) | |
| 663 | #define RT5682_SEL_ADCDAT_OUT (0x0 << 15) | |
| 664 | #define RT5682_SEL_ADCDAT_IN (0x1 << 15) | |
| 665 | #define RT5682_SEL_ADCDAT_SFT 15 | |
| 666 | #define RT5682_I2S1_TX_CHL_MASK (0x7 << 12) | |
| 667 | #define RT5682_I2S1_TX_CHL_SFT 12 | |
| 668 | #define RT5682_I2S1_TX_CHL_16 (0x0 << 12) | |
| 669 | #define RT5682_I2S1_TX_CHL_20 (0x1 << 12) | |
| 670 | #define RT5682_I2S1_TX_CHL_24 (0x2 << 12) | |
| 671 | #define RT5682_I2S1_TX_CHL_32 (0x3 << 12) | |
| 672 | #define RT5682_I2S1_TX_CHL_8 (0x4 << 12) | |
| 673 | #define RT5682_I2S1_RX_CHL_MASK (0x7 << 8) | |
| 674 | #define RT5682_I2S1_RX_CHL_SFT 8 | |
| 675 | #define RT5682_I2S1_RX_CHL_16 (0x0 << 8) | |
| 676 | #define RT5682_I2S1_RX_CHL_20 (0x1 << 8) | |
| 677 | #define RT5682_I2S1_RX_CHL_24 (0x2 << 8) | |
| 678 | #define RT5682_I2S1_RX_CHL_32 (0x3 << 8) | |
| 679 | #define RT5682_I2S1_RX_CHL_8 (0x4 << 8) | |
| 680 | #define RT5682_I2S1_MONO_MASK (0x1 << 7) | |
| 681 | #define RT5682_I2S1_MONO_EN (0x1 << 7) | |
| 682 | #define RT5682_I2S1_MONO_DIS (0x0 << 7) | |
| 683 | #define RT5682_I2S2_MONO_MASK (0x1 << 6) | |
| 684 | #define RT5682_I2S2_MONO_EN (0x1 << 6) | |
| 685 | #define RT5682_I2S2_MONO_DIS (0x0 << 6) | |
| 686 | #define RT5682_I2S1_DL_MASK (0x7 << 4) | |
| 687 | #define RT5682_I2S1_DL_SFT 4 | |
| 688 | #define RT5682_I2S1_DL_16 (0x0 << 4) | |
| 689 | #define RT5682_I2S1_DL_20 (0x1 << 4) | |
| 690 | #define RT5682_I2S1_DL_24 (0x2 << 4) | |
| 691 | #define RT5682_I2S1_DL_32 (0x3 << 4) | |
| 692 | #define RT5682_I2S1_DL_8 (0x4 << 4) | |
| 693 | ||
| 694 | /* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */ | |
| 695 | #define RT5682_I2S2_MS_MASK (0x1 << 15) | |
| 696 | #define RT5682_I2S2_MS_SFT 15 | |
| 697 | #define RT5682_I2S2_MS_M (0x0 << 15) | |
| 698 | #define RT5682_I2S2_MS_S (0x1 << 15) | |
| 699 | #define RT5682_I2S2_PIN_CFG_MASK (0x1 << 14) | |
| 700 | #define RT5682_I2S2_PIN_CFG_SFT 14 | |
| 701 | #define RT5682_I2S2_CLK_SEL_MASK (0x1 << 11) | |
| 702 | #define RT5682_I2S2_CLK_SEL_SFT 11 | |
| 703 | #define RT5682_I2S2_OUT_MASK (0x1 << 9) | |
| 704 | #define RT5682_I2S2_OUT_SFT 9 | |
| 705 | #define RT5682_I2S2_OUT_UM (0x0 << 9) | |
| 706 | #define RT5682_I2S2_OUT_M (0x1 << 9) | |
| 707 | #define RT5682_I2S_BP_MASK (0x1 << 8) | |
| 708 | #define RT5682_I2S_BP_SFT 8 | |
| 709 | #define RT5682_I2S_BP_NOR (0x0 << 8) | |
| 710 | #define RT5682_I2S_BP_INV (0x1 << 8) | |
| 711 | #define RT5682_I2S2_MONO_EN (0x1 << 6) | |
| 712 | #define RT5682_I2S2_MONO_DIS (0x0 << 6) | |
| 713 | #define RT5682_I2S2_DL_MASK (0x3 << 4) | |
| 714 | #define RT5682_I2S2_DL_SFT 4 | |
| 715 | #define RT5682_I2S2_DL_16 (0x0 << 4) | |
| 716 | #define RT5682_I2S2_DL_20 (0x1 << 4) | |
| 717 | #define RT5682_I2S2_DL_24 (0x2 << 4) | |
| 718 | #define RT5682_I2S2_DL_8 (0x3 << 4) | |
| 719 | #define RT5682_I2S_DF_MASK (0x7) | |
| 720 | #define RT5682_I2S_DF_SFT 0 | |
| 721 | #define RT5682_I2S_DF_I2S (0x0) | |
| 722 | #define RT5682_I2S_DF_LEFT (0x1) | |
| 723 | #define RT5682_I2S_DF_PCM_A (0x2) | |
| 724 | #define RT5682_I2S_DF_PCM_B (0x3) | |
| 725 | #define RT5682_I2S_DF_PCM_A_N (0x6) | |
| 726 | #define RT5682_I2S_DF_PCM_B_N (0x7) | |
| 727 | ||
| 728 | /* ADC/DAC Clock Control 1 (0x0073) */ | |
| 729 | #define RT5682_ADC_OSR_MASK (0xf << 12) | |
| 730 | #define RT5682_ADC_OSR_SFT 12 | |
| 731 | #define RT5682_ADC_OSR_D_1 (0x0 << 12) | |
| 732 | #define RT5682_ADC_OSR_D_2 (0x1 << 12) | |
| 733 | #define RT5682_ADC_OSR_D_4 (0x2 << 12) | |
| 734 | #define RT5682_ADC_OSR_D_6 (0x3 << 12) | |
| 735 | #define RT5682_ADC_OSR_D_8 (0x4 << 12) | |
| 736 | #define RT5682_ADC_OSR_D_12 (0x5 << 12) | |
| 737 | #define RT5682_ADC_OSR_D_16 (0x6 << 12) | |
| 738 | #define RT5682_ADC_OSR_D_24 (0x7 << 12) | |
| 739 | #define RT5682_ADC_OSR_D_32 (0x8 << 12) | |
| 740 | #define RT5682_ADC_OSR_D_48 (0x9 << 12) | |
| 741 | #define RT5682_I2S_M_DIV_MASK (0xf << 12) | |
| 742 | #define RT5682_I2S_M_DIV_SFT 8 | |
| 743 | #define RT5682_I2S_M_D_1 (0x0 << 8) | |
| 744 | #define RT5682_I2S_M_D_2 (0x1 << 8) | |
| 745 | #define RT5682_I2S_M_D_3 (0x2 << 8) | |
| 746 | #define RT5682_I2S_M_D_4 (0x3 << 8) | |
| 747 | #define RT5682_I2S_M_D_6 (0x4 << 8) | |
| 748 | #define RT5682_I2S_M_D_8 (0x5 << 8) | |
| 749 | #define RT5682_I2S_M_D_12 (0x6 << 8) | |
| 750 | #define RT5682_I2S_M_D_16 (0x7 << 8) | |
| 751 | #define RT5682_I2S_M_D_24 (0x8 << 8) | |
| 752 | #define RT5682_I2S_M_D_32 (0x9 << 8) | |
| 753 | #define RT5682_I2S_M_D_48 (0x10 << 8) | |
| 754 | #define RT5682_I2S_CLK_SRC_MASK (0x7 << 4) | |
| 755 | #define RT5682_I2S_CLK_SRC_SFT 4 | |
| 756 | #define RT5682_I2S_CLK_SRC_MCLK (0x0 << 4) | |
| 757 | #define RT5682_I2S_CLK_SRC_PLL1 (0x1 << 4) | |
| 758 | #define RT5682_I2S_CLK_SRC_PLL2 (0x2 << 4) | |
| 759 | #define RT5682_I2S_CLK_SRC_SDW (0x3 << 4) | |
| 760 | #define RT5682_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */ | |
| 761 | #define RT5682_DAC_OSR_MASK (0xf << 0) | |
| 762 | #define RT5682_DAC_OSR_SFT 0 | |
| 763 | #define RT5682_DAC_OSR_D_1 (0x0 << 0) | |
| 764 | #define RT5682_DAC_OSR_D_2 (0x1 << 0) | |
| 765 | #define RT5682_DAC_OSR_D_4 (0x2 << 0) | |
| 766 | #define RT5682_DAC_OSR_D_6 (0x3 << 0) | |
| 767 | #define RT5682_DAC_OSR_D_8 (0x4 << 0) | |
| 768 | #define RT5682_DAC_OSR_D_12 (0x5 << 0) | |
| 769 | #define RT5682_DAC_OSR_D_16 (0x6 << 0) | |
| 770 | #define RT5682_DAC_OSR_D_24 (0x7 << 0) | |
| 771 | #define RT5682_DAC_OSR_D_32 (0x8 << 0) | |
| 772 | #define RT5682_DAC_OSR_D_48 (0x9 << 0) | |
| 773 | ||
| 774 | /* ADC/DAC Clock Control 2 (0x0074) */ | |
| 775 | #define RT5682_I2S2_BCLK_MS2_MASK (0x1 << 11) | |
| 776 | #define RT5682_I2S2_BCLK_MS2_SFT 11 | |
| 777 | #define RT5682_I2S2_BCLK_MS2_32 (0x0 << 11) | |
| 778 | #define RT5682_I2S2_BCLK_MS2_64 (0x1 << 11) | |
| 779 | ||
| 780 | ||
| 781 | /* TDM control 1 (0x0079) */ | |
| 782 | #define RT5682_TDM_TX_CH_MASK (0x3 << 12) | |
| 783 | #define RT5682_TDM_TX_CH_2 (0x0 << 12) | |
| 784 | #define RT5682_TDM_TX_CH_4 (0x1 << 12) | |
| 785 | #define RT5682_TDM_TX_CH_6 (0x2 << 12) | |
| 786 | #define RT5682_TDM_TX_CH_8 (0x3 << 12) | |
| 787 | #define RT5682_TDM_RX_CH_MASK (0x3 << 8) | |
| 788 | #define RT5682_TDM_RX_CH_2 (0x0 << 8) | |
| 789 | #define RT5682_TDM_RX_CH_4 (0x1 << 8) | |
| 790 | #define RT5682_TDM_RX_CH_6 (0x2 << 8) | |
| 791 | #define RT5682_TDM_RX_CH_8 (0x3 << 8) | |
| 792 | #define RT5682_TDM_ADC_LCA_MASK (0xf << 4) | |
| 793 | #define RT5682_TDM_ADC_LCA_SFT 4 | |
| 794 | #define RT5682_TDM_ADC_DL_SFT 0 | |
| 795 | ||
| 796 | /* TDM control 2 (0x007a) */ | |
| 797 | #define RT5682_IF1_ADC1_SEL_SFT 14 | |
| 798 | #define RT5682_IF1_ADC2_SEL_SFT 12 | |
| 799 | #define RT5682_IF1_ADC3_SEL_SFT 10 | |
| 800 | #define RT5682_IF1_ADC4_SEL_SFT 8 | |
| 801 | #define RT5682_TDM_ADC_SEL_SFT 4 | |
| 802 | ||
| 803 | /* TDM control 3 (0x007b) */ | |
| 804 | #define RT5682_TDM_EN (0x1 << 7) | |
| 805 | ||
| 806 | /* TDM/I2S control (0x007e) */ | |
| 807 | #define RT5682_TDM_S_BP_MASK (0x1 << 15) | |
| 808 | #define RT5682_TDM_S_BP_SFT 15 | |
| 809 | #define RT5682_TDM_S_BP_NOR (0x0 << 15) | |
| 810 | #define RT5682_TDM_S_BP_INV (0x1 << 15) | |
| 811 | #define RT5682_TDM_S_LP_MASK (0x1 << 14) | |
| 812 | #define RT5682_TDM_S_LP_SFT 14 | |
| 813 | #define RT5682_TDM_S_LP_NOR (0x0 << 14) | |
| 814 | #define RT5682_TDM_S_LP_INV (0x1 << 14) | |
| 815 | #define RT5682_TDM_DF_MASK (0x7 << 11) | |
| 816 | #define RT5682_TDM_DF_SFT 11 | |
| 817 | #define RT5682_TDM_DF_I2S (0x0 << 11) | |
| 818 | #define RT5682_TDM_DF_LEFT (0x1 << 11) | |
| 819 | #define RT5682_TDM_DF_PCM_A (0x2 << 11) | |
| 820 | #define RT5682_TDM_DF_PCM_B (0x3 << 11) | |
| 821 | #define RT5682_TDM_DF_PCM_A_N (0x6 << 11) | |
| 822 | #define RT5682_TDM_DF_PCM_B_N (0x7 << 11) | |
| 823 | #define RT5682_TDM_CL_MASK (0x3 << 4) | |
| 824 | #define RT5682_TDM_CL_16 (0x0 << 4) | |
| 825 | #define RT5682_TDM_CL_20 (0x1 << 4) | |
| 826 | #define RT5682_TDM_CL_24 (0x2 << 4) | |
| 827 | #define RT5682_TDM_CL_32 (0x3 << 4) | |
| 828 | #define RT5682_TDM_M_BP_MASK (0x1 << 2) | |
| 829 | #define RT5682_TDM_M_BP_SFT 2 | |
| 830 | #define RT5682_TDM_M_BP_NOR (0x0 << 2) | |
| 831 | #define RT5682_TDM_M_BP_INV (0x1 << 2) | |
| 832 | #define RT5682_TDM_M_LP_MASK (0x1 << 1) | |
| 833 | #define RT5682_TDM_M_LP_SFT 1 | |
| 834 | #define RT5682_TDM_M_LP_NOR (0x0 << 1) | |
| 835 | #define RT5682_TDM_M_LP_INV (0x1 << 1) | |
| 836 | #define RT5682_TDM_MS_MASK (0x1 << 0) | |
| 837 | #define RT5682_TDM_MS_SFT 0 | |
| 838 | #define RT5682_TDM_MS_M (0x0 << 0) | |
| 839 | #define RT5682_TDM_MS_S (0x1 << 0) | |
| 840 | ||
| 841 | /* Global Clock Control (0x0080) */ | |
| 842 | #define RT5682_SCLK_SRC_MASK (0x7 << 13) | |
| 843 | #define RT5682_SCLK_SRC_SFT 13 | |
| 844 | #define RT5682_SCLK_SRC_MCLK (0x0 << 13) | |
| 845 | #define RT5682_SCLK_SRC_PLL1 (0x1 << 13) | |
| 846 | #define RT5682_SCLK_SRC_PLL2 (0x2 << 13) | |
| 847 | #define RT5682_SCLK_SRC_SDW (0x3 << 13) | |
| 848 | #define RT5682_SCLK_SRC_RCCLK (0x4 << 13) | |
| ee7ea2a9 SF |
849 | #define RT5682_PLL2_SRC_MASK (0x3 << 10) |
| 850 | #define RT5682_PLL2_SRC_SFT 10 | |
| 851 | #define RT5682_PLL2_SRC_MCLK (0x0 << 10) | |
| 852 | #define RT5682_PLL2_SRC_BCLK1 (0x1 << 10) | |
| 853 | #define RT5682_PLL2_SRC_SDW (0x2 << 10) | |
| 854 | #define RT5682_PLL2_SRC_RC (0x3 << 10) | |
| 855 | #define RT5682_PLL1_SRC_MASK (0x3 << 8) | |
| 856 | #define RT5682_PLL1_SRC_SFT 8 | |
| 857 | #define RT5682_PLL1_SRC_MCLK (0x0 << 8) | |
| 858 | #define RT5682_PLL1_SRC_BCLK1 (0x1 << 8) | |
| 859 | #define RT5682_PLL1_SRC_SDW (0x2 << 8) | |
| 860 | #define RT5682_PLL1_SRC_RC (0x3 << 8) | |
| 0ddce71c BL |
861 | |
| 862 | ||
| 863 | ||
| 864 | #define RT5682_PLL_INP_MAX 40000000 | |
| 865 | #define RT5682_PLL_INP_MIN 256000 | |
| 866 | /* PLL M/N/K Code Control 1 (0x0081) */ | |
| 867 | #define RT5682_PLL_N_MAX 0x001ff | |
| 868 | #define RT5682_PLL_N_MASK (RT5682_PLL_N_MAX << 7) | |
| 869 | #define RT5682_PLL_N_SFT 7 | |
| 870 | #define RT5682_PLL_K_MAX 0x001f | |
| 871 | #define RT5682_PLL_K_MASK (RT5682_PLL_K_MAX) | |
| 872 | #define RT5682_PLL_K_SFT 0 | |
| 873 | ||
| 874 | /* PLL M/N/K Code Control 2 (0x0082) */ | |
| 875 | #define RT5682_PLL_M_MAX 0x00f | |
| 876 | #define RT5682_PLL_M_MASK (RT5682_PLL_M_MAX << 12) | |
| 877 | #define RT5682_PLL_M_SFT 12 | |
| 878 | #define RT5682_PLL_M_BP (0x1 << 11) | |
| 879 | #define RT5682_PLL_M_BP_SFT 11 | |
| 880 | #define RT5682_PLL_K_BP (0x1 << 10) | |
| 881 | #define RT5682_PLL_K_BP_SFT 10 | |
| 882 | #define RT5682_PLL_RST (0x1 << 1) | |
| 883 | ||
| 884 | /* PLL tracking mode 1 (0x0083) */ | |
| 885 | #define RT5682_DA_ASRC_MASK (0x1 << 13) | |
| 886 | #define RT5682_DA_ASRC_SFT 13 | |
| 887 | #define RT5682_DAC_STO1_ASRC_MASK (0x1 << 12) | |
| 888 | #define RT5682_DAC_STO1_ASRC_SFT 12 | |
| 889 | #define RT5682_AD_ASRC_MASK (0x1 << 8) | |
| 890 | #define RT5682_AD_ASRC_SFT 8 | |
| 891 | #define RT5682_AD_ASRC_SEL_MASK (0x1 << 4) | |
| 892 | #define RT5682_AD_ASRC_SEL_SFT 4 | |
| 893 | #define RT5682_DMIC_ASRC_MASK (0x1 << 3) | |
| 894 | #define RT5682_DMIC_ASRC_SFT 3 | |
| 895 | #define RT5682_ADC_STO1_ASRC_MASK (0x1 << 2) | |
| 896 | #define RT5682_ADC_STO1_ASRC_SFT 2 | |
| 897 | #define RT5682_DA_ASRC_SEL_MASK (0x1 << 0) | |
| 898 | #define RT5682_DA_ASRC_SEL_SFT 0 | |
| 899 | ||
| 900 | /* PLL tracking mode 2 3 (0x0084)(0x0085)*/ | |
| 901 | #define RT5682_FILTER_CLK_SEL_MASK (0x7 << 12) | |
| 902 | #define RT5682_FILTER_CLK_SEL_SFT 12 | |
| 903 | #define RT5682_FILTER_CLK_DIV_MASK (0xf << 8) | |
| 904 | #define RT5682_FILTER_CLK_DIV_SFT 8 | |
| 905 | ||
| 906 | /* ASRC Control 4 (0x0086) */ | |
| 907 | #define RT5682_ASRCIN_FTK_N1_MASK (0x3 << 14) | |
| 908 | #define RT5682_ASRCIN_FTK_N1_SFT 14 | |
| 909 | #define RT5682_ASRCIN_FTK_N2_MASK (0x3 << 12) | |
| 910 | #define RT5682_ASRCIN_FTK_N2_SFT 12 | |
| 911 | #define RT5682_ASRCIN_FTK_M1_MASK (0x7 << 8) | |
| 912 | #define RT5682_ASRCIN_FTK_M1_SFT 8 | |
| 913 | #define RT5682_ASRCIN_FTK_M2_MASK (0x7 << 4) | |
| 914 | #define RT5682_ASRCIN_FTK_M2_SFT 4 | |
| 915 | ||
| 916 | /* SoundWire reference clk (0x008d) */ | |
| 917 | #define RT5682_PLL2_OUT_MASK (0x1 << 8) | |
| 918 | #define RT5682_PLL2_OUT_98M (0x0 << 8) | |
| 919 | #define RT5682_PLL2_OUT_49M (0x1 << 8) | |
| 920 | #define RT5682_SDW_REF_2_MASK (0xf << 4) | |
| 921 | #define RT5682_SDW_REF_2_SFT 4 | |
| 922 | #define RT5682_SDW_REF_2_48K (0x0 << 4) | |
| 923 | #define RT5682_SDW_REF_2_96K (0x1 << 4) | |
| 924 | #define RT5682_SDW_REF_2_192K (0x2 << 4) | |
| 925 | #define RT5682_SDW_REF_2_32K (0x3 << 4) | |
| 926 | #define RT5682_SDW_REF_2_24K (0x4 << 4) | |
| 927 | #define RT5682_SDW_REF_2_16K (0x5 << 4) | |
| 928 | #define RT5682_SDW_REF_2_12K (0x6 << 4) | |
| 929 | #define RT5682_SDW_REF_2_8K (0x7 << 4) | |
| 930 | #define RT5682_SDW_REF_2_44K (0x8 << 4) | |
| 931 | #define RT5682_SDW_REF_2_88K (0x9 << 4) | |
| 932 | #define RT5682_SDW_REF_2_176K (0xa << 4) | |
| 933 | #define RT5682_SDW_REF_2_353K (0xb << 4) | |
| 934 | #define RT5682_SDW_REF_2_22K (0xc << 4) | |
| 935 | #define RT5682_SDW_REF_2_384K (0xd << 4) | |
| 936 | #define RT5682_SDW_REF_2_11K (0xe << 4) | |
| 937 | #define RT5682_SDW_REF_1_MASK (0xf << 0) | |
| 938 | #define RT5682_SDW_REF_1_SFT 0 | |
| 939 | #define RT5682_SDW_REF_1_48K (0x0 << 0) | |
| 940 | #define RT5682_SDW_REF_1_96K (0x1 << 0) | |
| 941 | #define RT5682_SDW_REF_1_192K (0x2 << 0) | |
| 942 | #define RT5682_SDW_REF_1_32K (0x3 << 0) | |
| 943 | #define RT5682_SDW_REF_1_24K (0x4 << 0) | |
| 944 | #define RT5682_SDW_REF_1_16K (0x5 << 0) | |
| 945 | #define RT5682_SDW_REF_1_12K (0x6 << 0) | |
| 946 | #define RT5682_SDW_REF_1_8K (0x7 << 0) | |
| 947 | #define RT5682_SDW_REF_1_44K (0x8 << 0) | |
| 948 | #define RT5682_SDW_REF_1_88K (0x9 << 0) | |
| 949 | #define RT5682_SDW_REF_1_176K (0xa << 0) | |
| 950 | #define RT5682_SDW_REF_1_353K (0xb << 0) | |
| 951 | #define RT5682_SDW_REF_1_22K (0xc << 0) | |
| 952 | #define RT5682_SDW_REF_1_384K (0xd << 0) | |
| 953 | #define RT5682_SDW_REF_1_11K (0xe << 0) | |
| 954 | ||
| 955 | /* Depop Mode Control 1 (0x008e) */ | |
| 956 | #define RT5682_PUMP_EN (0x1 << 3) | |
| 957 | #define RT5682_PUMP_EN_SFT 3 | |
| 958 | #define RT5682_CAPLESS_EN (0x1 << 0) | |
| 959 | #define RT5682_CAPLESS_EN_SFT 0 | |
| 960 | ||
| 961 | /* Depop Mode Control 2 (0x8f) */ | |
| 962 | #define RT5682_RAMP_MASK (0x1 << 12) | |
| 963 | #define RT5682_RAMP_SFT 12 | |
| 964 | #define RT5682_RAMP_DIS (0x0 << 12) | |
| 965 | #define RT5682_RAMP_EN (0x1 << 12) | |
| 966 | #define RT5682_BPS_MASK (0x1 << 11) | |
| 967 | #define RT5682_BPS_SFT 11 | |
| 968 | #define RT5682_BPS_DIS (0x0 << 11) | |
| 969 | #define RT5682_BPS_EN (0x1 << 11) | |
| 970 | #define RT5682_FAST_UPDN_MASK (0x1 << 10) | |
| 971 | #define RT5682_FAST_UPDN_SFT 10 | |
| 972 | #define RT5682_FAST_UPDN_DIS (0x0 << 10) | |
| 973 | #define RT5682_FAST_UPDN_EN (0x1 << 10) | |
| 974 | #define RT5682_VLO_MASK (0x1 << 7) | |
| 975 | #define RT5682_VLO_SFT 7 | |
| 976 | #define RT5682_VLO_3V (0x0 << 7) | |
| 977 | #define RT5682_VLO_33V (0x1 << 7) | |
| 978 | ||
| 979 | /* HPOUT charge pump 1 (0x0091) */ | |
| 980 | #define RT5682_OSW_L_MASK (0x1 << 11) | |
| 981 | #define RT5682_OSW_L_SFT 11 | |
| 982 | #define RT5682_OSW_L_DIS (0x0 << 11) | |
| 983 | #define RT5682_OSW_L_EN (0x1 << 11) | |
| 984 | #define RT5682_OSW_R_MASK (0x1 << 10) | |
| 985 | #define RT5682_OSW_R_SFT 10 | |
| 986 | #define RT5682_OSW_R_DIS (0x0 << 10) | |
| 987 | #define RT5682_OSW_R_EN (0x1 << 10) | |
| 988 | #define RT5682_PM_HP_MASK (0x3 << 8) | |
| 989 | #define RT5682_PM_HP_SFT 8 | |
| 990 | #define RT5682_PM_HP_LV (0x0 << 8) | |
| 991 | #define RT5682_PM_HP_MV (0x1 << 8) | |
| 992 | #define RT5682_PM_HP_HV (0x2 << 8) | |
| 993 | #define RT5682_IB_HP_MASK (0x3 << 6) | |
| 994 | #define RT5682_IB_HP_SFT 6 | |
| 995 | #define RT5682_IB_HP_125IL (0x0 << 6) | |
| 996 | #define RT5682_IB_HP_25IL (0x1 << 6) | |
| 997 | #define RT5682_IB_HP_5IL (0x2 << 6) | |
| 998 | #define RT5682_IB_HP_1IL (0x3 << 6) | |
| 999 | ||
| 1000 | /* Micbias Control1 (0x93) */ | |
| 1001 | #define RT5682_MIC1_OV_MASK (0x3 << 14) | |
| 1002 | #define RT5682_MIC1_OV_SFT 14 | |
| 1003 | #define RT5682_MIC1_OV_2V7 (0x0 << 14) | |
| 1004 | #define RT5682_MIC1_OV_2V4 (0x1 << 14) | |
| 1005 | #define RT5682_MIC1_OV_2V25 (0x3 << 14) | |
| 1006 | #define RT5682_MIC1_OV_1V8 (0x4 << 14) | |
| 1007 | #define RT5682_MIC1_CLK_MASK (0x1 << 13) | |
| 1008 | #define RT5682_MIC1_CLK_SFT 13 | |
| 1009 | #define RT5682_MIC1_CLK_DIS (0x0 << 13) | |
| 1010 | #define RT5682_MIC1_CLK_EN (0x1 << 13) | |
| 1011 | #define RT5682_MIC1_OVCD_MASK (0x1 << 12) | |
| 1012 | #define RT5682_MIC1_OVCD_SFT 12 | |
| 1013 | #define RT5682_MIC1_OVCD_DIS (0x0 << 12) | |
| 1014 | #define RT5682_MIC1_OVCD_EN (0x1 << 12) | |
| 1015 | #define RT5682_MIC1_OVTH_MASK (0x3 << 10) | |
| 1016 | #define RT5682_MIC1_OVTH_SFT 10 | |
| 1017 | #define RT5682_MIC1_OVTH_768UA (0x0 << 10) | |
| 1018 | #define RT5682_MIC1_OVTH_960UA (0x1 << 10) | |
| 1019 | #define RT5682_MIC1_OVTH_1152UA (0x2 << 10) | |
| 1020 | #define RT5682_MIC1_OVTH_1960UA (0x3 << 10) | |
| 1021 | #define RT5682_MIC2_OV_MASK (0x3 << 8) | |
| 1022 | #define RT5682_MIC2_OV_SFT 8 | |
| 1023 | #define RT5682_MIC2_OV_2V7 (0x0 << 8) | |
| 1024 | #define RT5682_MIC2_OV_2V4 (0x1 << 8) | |
| 1025 | #define RT5682_MIC2_OV_2V25 (0x3 << 8) | |
| 1026 | #define RT5682_MIC2_OV_1V8 (0x4 << 8) | |
| 1027 | #define RT5682_MIC2_CLK_MASK (0x1 << 7) | |
| 1028 | #define RT5682_MIC2_CLK_SFT 7 | |
| 1029 | #define RT5682_MIC2_CLK_DIS (0x0 << 7) | |
| 1030 | #define RT5682_MIC2_CLK_EN (0x1 << 7) | |
| 1031 | #define RT5682_MIC2_OVTH_MASK (0x3 << 4) | |
| 1032 | #define RT5682_MIC2_OVTH_SFT 4 | |
| 1033 | #define RT5682_MIC2_OVTH_768UA (0x0 << 4) | |
| 1034 | #define RT5682_MIC2_OVTH_960UA (0x1 << 4) | |
| 1035 | #define RT5682_MIC2_OVTH_1152UA (0x2 << 4) | |
| 1036 | #define RT5682_MIC2_OVTH_1960UA (0x3 << 4) | |
| 1037 | #define RT5682_PWR_MB_MASK (0x1 << 3) | |
| 1038 | #define RT5682_PWR_MB_SFT 3 | |
| 1039 | #define RT5682_PWR_MB_PD (0x0 << 3) | |
| 1040 | #define RT5682_PWR_MB_PU (0x1 << 3) | |
| 1041 | ||
| 1042 | /* Micbias Control2 (0x0094) */ | |
| 1043 | #define RT5682_PWR_CLK25M_MASK (0x1 << 9) | |
| 1044 | #define RT5682_PWR_CLK25M_SFT 9 | |
| 1045 | #define RT5682_PWR_CLK25M_PD (0x0 << 9) | |
| 1046 | #define RT5682_PWR_CLK25M_PU (0x1 << 9) | |
| 1047 | #define RT5682_PWR_CLK1M_MASK (0x1 << 8) | |
| 1048 | #define RT5682_PWR_CLK1M_SFT 8 | |
| 1049 | #define RT5682_PWR_CLK1M_PD (0x0 << 8) | |
| 1050 | #define RT5682_PWR_CLK1M_PU (0x1 << 8) | |
| 1051 | ||
| 1052 | /* RC Clock Control (0x009f) */ | |
| 1053 | #define RT5682_POW_IRQ (0x1 << 15) | |
| 1054 | #define RT5682_POW_JDH (0x1 << 14) | |
| 1055 | #define RT5682_POW_JDL (0x1 << 13) | |
| 1056 | #define RT5682_POW_ANA (0x1 << 12) | |
| 1057 | ||
| 1058 | /* I2S Master Mode Clock Control 1 (0x00a0) */ | |
| 1059 | #define RT5682_CLK_SRC_MCLK (0x0) | |
| 1060 | #define RT5682_CLK_SRC_PLL1 (0x1) | |
| 1061 | #define RT5682_CLK_SRC_PLL2 (0x2) | |
| 1062 | #define RT5682_CLK_SRC_SDW (0x3) | |
| 1063 | #define RT5682_CLK_SRC_RCCLK (0x4) | |
| 1064 | #define RT5682_I2S_PD_1 (0x0) | |
| 1065 | #define RT5682_I2S_PD_2 (0x1) | |
| 1066 | #define RT5682_I2S_PD_3 (0x2) | |
| 1067 | #define RT5682_I2S_PD_4 (0x3) | |
| 1068 | #define RT5682_I2S_PD_6 (0x4) | |
| 1069 | #define RT5682_I2S_PD_8 (0x5) | |
| 1070 | #define RT5682_I2S_PD_12 (0x6) | |
| 1071 | #define RT5682_I2S_PD_16 (0x7) | |
| 1072 | #define RT5682_I2S_PD_24 (0x8) | |
| 1073 | #define RT5682_I2S_PD_32 (0x9) | |
| 1074 | #define RT5682_I2S_PD_48 (0xa) | |
| 1075 | #define RT5682_I2S2_SRC_MASK (0x3 << 4) | |
| 1076 | #define RT5682_I2S2_SRC_SFT 4 | |
| 1077 | #define RT5682_I2S2_M_PD_MASK (0xf << 0) | |
| 1078 | #define RT5682_I2S2_M_PD_SFT 0 | |
| 1079 | ||
| 1080 | /* IRQ Control 1 (0x00b6) */ | |
| 1081 | #define RT5682_JD1_PULSE_EN_MASK (0x1 << 10) | |
| 1082 | #define RT5682_JD1_PULSE_EN_SFT 10 | |
| 1083 | #define RT5682_JD1_PULSE_DIS (0x0 << 10) | |
| 1084 | #define RT5682_JD1_PULSE_EN (0x1 << 10) | |
| 1085 | ||
| 1086 | /* IRQ Control 2 (0x00b7) */ | |
| 1087 | #define RT5682_JD1_EN_MASK (0x1 << 15) | |
| 1088 | #define RT5682_JD1_EN_SFT 15 | |
| 1089 | #define RT5682_JD1_DIS (0x0 << 15) | |
| 1090 | #define RT5682_JD1_EN (0x1 << 15) | |
| 1091 | #define RT5682_JD1_POL_MASK (0x1 << 13) | |
| 1092 | #define RT5682_JD1_POL_NOR (0x0 << 13) | |
| 1093 | #define RT5682_JD1_POL_INV (0x1 << 13) | |
| 1094 | ||
| 1095 | /* IRQ Control 3 (0x00b8) */ | |
| 1096 | #define RT5682_IL_IRQ_MASK (0x1 << 7) | |
| 1097 | #define RT5682_IL_IRQ_DIS (0x0 << 7) | |
| 1098 | #define RT5682_IL_IRQ_EN (0x1 << 7) | |
| 1099 | ||
| 1100 | /* GPIO Control 1 (0x00c0) */ | |
| 1101 | #define RT5682_GP1_PIN_MASK (0x3 << 14) | |
| 1102 | #define RT5682_GP1_PIN_SFT 14 | |
| 1103 | #define RT5682_GP1_PIN_GPIO1 (0x0 << 14) | |
| 1104 | #define RT5682_GP1_PIN_IRQ (0x1 << 14) | |
| 1105 | #define RT5682_GP1_PIN_DMIC_CLK (0x2 << 14) | |
| 1106 | #define RT5682_GP2_PIN_MASK (0x3 << 12) | |
| 1107 | #define RT5682_GP2_PIN_SFT 12 | |
| 1108 | #define RT5682_GP2_PIN_GPIO2 (0x0 << 12) | |
| 1109 | #define RT5682_GP2_PIN_LRCK2 (0x1 << 12) | |
| 1110 | #define RT5682_GP2_PIN_DMIC_SDA (0x2 << 12) | |
| 1111 | #define RT5682_GP3_PIN_MASK (0x3 << 10) | |
| 1112 | #define RT5682_GP3_PIN_SFT 10 | |
| 1113 | #define RT5682_GP3_PIN_GPIO3 (0x0 << 10) | |
| 1114 | #define RT5682_GP3_PIN_BCLK2 (0x1 << 10) | |
| 1115 | #define RT5682_GP3_PIN_DMIC_CLK (0x2 << 10) | |
| 1116 | #define RT5682_GP4_PIN_MASK (0x3 << 8) | |
| 1117 | #define RT5682_GP4_PIN_SFT 8 | |
| 1118 | #define RT5682_GP4_PIN_GPIO4 (0x0 << 8) | |
| 1119 | #define RT5682_GP4_PIN_ADCDAT1 (0x1 << 8) | |
| 1120 | #define RT5682_GP4_PIN_DMIC_CLK (0x2 << 8) | |
| 1121 | #define RT5682_GP4_PIN_ADCDAT2 (0x3 << 8) | |
| 1122 | #define RT5682_GP5_PIN_MASK (0x3 << 6) | |
| 1123 | #define RT5682_GP5_PIN_SFT 6 | |
| 1124 | #define RT5682_GP5_PIN_GPIO5 (0x0 << 6) | |
| 1125 | #define RT5682_GP5_PIN_DACDAT1 (0x1 << 6) | |
| 1126 | #define RT5682_GP5_PIN_DMIC_SDA (0x2 << 6) | |
| 1127 | #define RT5682_GP6_PIN_MASK (0x1 << 5) | |
| 1128 | #define RT5682_GP6_PIN_SFT 5 | |
| 1129 | #define RT5682_GP6_PIN_GPIO6 (0x0 << 5) | |
| 1130 | #define RT5682_GP6_PIN_LRCK1 (0x1 << 5) | |
| 1131 | ||
| 1132 | /* GPIO Control 2 (0x00c1)*/ | |
| 1133 | #define RT5682_GP1_PF_MASK (0x1 << 15) | |
| 1134 | #define RT5682_GP1_PF_IN (0x0 << 15) | |
| 1135 | #define RT5682_GP1_PF_OUT (0x1 << 15) | |
| 1136 | #define RT5682_GP1_OUT_MASK (0x1 << 14) | |
| 1137 | #define RT5682_GP1_OUT_L (0x0 << 14) | |
| 1138 | #define RT5682_GP1_OUT_H (0x1 << 14) | |
| 1139 | #define RT5682_GP2_PF_MASK (0x1 << 13) | |
| 1140 | #define RT5682_GP2_PF_IN (0x0 << 13) | |
| 1141 | #define RT5682_GP2_PF_OUT (0x1 << 13) | |
| 1142 | #define RT5682_GP2_OUT_MASK (0x1 << 12) | |
| 1143 | #define RT5682_GP2_OUT_L (0x0 << 12) | |
| 1144 | #define RT5682_GP2_OUT_H (0x1 << 12) | |
| 1145 | #define RT5682_GP3_PF_MASK (0x1 << 11) | |
| 1146 | #define RT5682_GP3_PF_IN (0x0 << 11) | |
| 1147 | #define RT5682_GP3_PF_OUT (0x1 << 11) | |
| 1148 | #define RT5682_GP3_OUT_MASK (0x1 << 10) | |
| 1149 | #define RT5682_GP3_OUT_L (0x0 << 10) | |
| 1150 | #define RT5682_GP3_OUT_H (0x1 << 10) | |
| 1151 | #define RT5682_GP4_PF_MASK (0x1 << 9) | |
| 1152 | #define RT5682_GP4_PF_IN (0x0 << 9) | |
| 1153 | #define RT5682_GP4_PF_OUT (0x1 << 9) | |
| 1154 | #define RT5682_GP4_OUT_MASK (0x1 << 8) | |
| 1155 | #define RT5682_GP4_OUT_L (0x0 << 8) | |
| 1156 | #define RT5682_GP4_OUT_H (0x1 << 8) | |
| 1157 | #define RT5682_GP5_PF_MASK (0x1 << 7) | |
| 1158 | #define RT5682_GP5_PF_IN (0x0 << 7) | |
| 1159 | #define RT5682_GP5_PF_OUT (0x1 << 7) | |
| 1160 | #define RT5682_GP5_OUT_MASK (0x1 << 6) | |
| 1161 | #define RT5682_GP5_OUT_L (0x0 << 6) | |
| 1162 | #define RT5682_GP5_OUT_H (0x1 << 6) | |
| 1163 | #define RT5682_GP6_PF_MASK (0x1 << 5) | |
| 1164 | #define RT5682_GP6_PF_IN (0x0 << 5) | |
| 1165 | #define RT5682_GP6_PF_OUT (0x1 << 5) | |
| 1166 | #define RT5682_GP6_OUT_MASK (0x1 << 4) | |
| 1167 | #define RT5682_GP6_OUT_L (0x0 << 4) | |
| 1168 | #define RT5682_GP6_OUT_H (0x1 << 4) | |
| 1169 | ||
| 1170 | ||
| 1171 | /* GPIO Status (0x00c2) */ | |
| 1172 | #define RT5682_GP6_STA (0x1 << 6) | |
| 1173 | #define RT5682_GP5_STA (0x1 << 5) | |
| 1174 | #define RT5682_GP4_STA (0x1 << 4) | |
| 1175 | #define RT5682_GP3_STA (0x1 << 3) | |
| 1176 | #define RT5682_GP2_STA (0x1 << 2) | |
| 1177 | #define RT5682_GP1_STA (0x1 << 1) | |
| 1178 | ||
| 1179 | /* Soft volume and zero cross control 1 (0x00d9) */ | |
| 1180 | #define RT5682_SV_MASK (0x1 << 15) | |
| 1181 | #define RT5682_SV_SFT 15 | |
| 1182 | #define RT5682_SV_DIS (0x0 << 15) | |
| 1183 | #define RT5682_SV_EN (0x1 << 15) | |
| 1184 | #define RT5682_ZCD_MASK (0x1 << 10) | |
| 1185 | #define RT5682_ZCD_SFT 10 | |
| 1186 | #define RT5682_ZCD_PD (0x0 << 10) | |
| 1187 | #define RT5682_ZCD_PU (0x1 << 10) | |
| 1188 | #define RT5682_SV_DLY_MASK (0xf) | |
| 1189 | #define RT5682_SV_DLY_SFT 0 | |
| 1190 | ||
| 1191 | /* Soft volume and zero cross control 2 (0x00da) */ | |
| 1192 | #define RT5682_ZCD_BST1_CBJ_MASK (0x1 << 7) | |
| 1193 | #define RT5682_ZCD_BST1_CBJ_SFT 7 | |
| 1194 | #define RT5682_ZCD_BST1_CBJ_DIS (0x0 << 7) | |
| 1195 | #define RT5682_ZCD_BST1_CBJ_EN (0x1 << 7) | |
| 1196 | #define RT5682_ZCD_RECMIX_MASK (0x1) | |
| 1197 | #define RT5682_ZCD_RECMIX_SFT 0 | |
| 1198 | #define RT5682_ZCD_RECMIX_DIS (0x0) | |
| 1199 | #define RT5682_ZCD_RECMIX_EN (0x1) | |
| 1200 | ||
| 1201 | /* 4 Button Inline Command Control 2 (0x00e3) */ | |
| 1202 | #define RT5682_4BTN_IL_MASK (0x1 << 15) | |
| 1203 | #define RT5682_4BTN_IL_EN (0x1 << 15) | |
| 1204 | #define RT5682_4BTN_IL_DIS (0x0 << 15) | |
| 1205 | #define RT5682_4BTN_IL_RST_MASK (0x1 << 14) | |
| 1206 | #define RT5682_4BTN_IL_NOR (0x1 << 14) | |
| 1207 | #define RT5682_4BTN_IL_RST (0x0 << 14) | |
| 1208 | ||
| 1209 | /* Analog JD Control (0x00f0) */ | |
| 1210 | #define RT5682_JDH_RS_MASK (0x1 << 4) | |
| 1211 | #define RT5682_JDH_NO_PLUG (0x1 << 4) | |
| 1212 | #define RT5682_JDH_PLUG (0x0 << 4) | |
| 1213 | ||
| bf0fa00f SF |
1214 | /* Bias current control 8 (0x0111) */ |
| 1215 | #define RT5682_HPA_CP_BIAS_CTRL_MASK (0x3 << 2) | |
| 1216 | #define RT5682_HPA_CP_BIAS_2UA (0x0 << 2) | |
| 1217 | #define RT5682_HPA_CP_BIAS_3UA (0x1 << 2) | |
| 1218 | #define RT5682_HPA_CP_BIAS_4UA (0x2 << 2) | |
| 1219 | #define RT5682_HPA_CP_BIAS_6UA (0x3 << 2) | |
| 1220 | ||
| 1221 | /* Charge Pump Internal Register1 (0x0125) */ | |
| 1222 | #define RT5682_CP_CLK_HP_MASK (0x3 << 4) | |
| 1223 | #define RT5682_CP_CLK_HP_100KHZ (0x0 << 4) | |
| 1224 | #define RT5682_CP_CLK_HP_200KHZ (0x1 << 4) | |
| 1225 | #define RT5682_CP_CLK_HP_300KHZ (0x2 << 4) | |
| 1226 | #define RT5682_CP_CLK_HP_600KHZ (0x3 << 4) | |
| 1227 | ||
| 0ddce71c BL |
1228 | /* Chopper and Clock control for DAC (0x013a)*/ |
| 1229 | #define RT5682_CKXEN_DAC1_MASK (0x1 << 13) | |
| 1230 | #define RT5682_CKXEN_DAC1_SFT 13 | |
| 1231 | #define RT5682_CKGEN_DAC1_MASK (0x1 << 12) | |
| 1232 | #define RT5682_CKGEN_DAC1_SFT 12 | |
| 1233 | ||
| 1234 | /* Chopper and Clock control for ADC (0x013b)*/ | |
| 1235 | #define RT5682_CKXEN_ADC1_MASK (0x1 << 13) | |
| 1236 | #define RT5682_CKXEN_ADC1_SFT 13 | |
| 1237 | #define RT5682_CKGEN_ADC1_MASK (0x1 << 12) | |
| 1238 | #define RT5682_CKGEN_ADC1_SFT 12 | |
| 1239 | ||
| 1240 | /* Volume test (0x013f)*/ | |
| 1241 | #define RT5682_SEL_CLK_VOL_MASK (0x1 << 15) | |
| 1242 | #define RT5682_SEL_CLK_VOL_EN (0x1 << 15) | |
| 1243 | #define RT5682_SEL_CLK_VOL_DIS (0x0 << 15) | |
| 1244 | ||
| 1245 | /* Test Mode Control 1 (0x0145) */ | |
| 1246 | #define RT5682_AD2DA_LB_MASK (0x1 << 10) | |
| 1247 | #define RT5682_AD2DA_LB_SFT 10 | |
| 1248 | ||
| 1249 | /* Stereo Noise Gate Control 1 (0x0160) */ | |
| 1250 | #define RT5682_NG2_EN_MASK (0x1 << 15) | |
| 1251 | #define RT5682_NG2_EN (0x1 << 15) | |
| 1252 | #define RT5682_NG2_DIS (0x0 << 15) | |
| 1253 | ||
| 1254 | /* Stereo1 DAC Silence Detection Control (0x0190) */ | |
| 1255 | #define RT5682_DEB_STO_DAC_MASK (0x7 << 4) | |
| 1256 | #define RT5682_DEB_80_MS (0x0 << 4) | |
| 1257 | ||
| 1258 | /* SAR ADC Inline Command Control 1 (0x0210) */ | |
| 1259 | #define RT5682_SAR_BUTT_DET_MASK (0x1 << 15) | |
| 1260 | #define RT5682_SAR_BUTT_DET_EN (0x1 << 15) | |
| 1261 | #define RT5682_SAR_BUTT_DET_DIS (0x0 << 15) | |
| 1262 | #define RT5682_SAR_BUTDET_MODE_MASK (0x1 << 14) | |
| 1263 | #define RT5682_SAR_BUTDET_POW_SAV (0x1 << 14) | |
| 1264 | #define RT5682_SAR_BUTDET_POW_NORM (0x0 << 14) | |
| 1265 | #define RT5682_SAR_BUTDET_RST_MASK (0x1 << 13) | |
| 1266 | #define RT5682_SAR_BUTDET_RST_NORMAL (0x1 << 13) | |
| 1267 | #define RT5682_SAR_BUTDET_RST (0x0 << 13) | |
| 1268 | #define RT5682_SAR_POW_MASK (0x1 << 12) | |
| 1269 | #define RT5682_SAR_POW_EN (0x1 << 12) | |
| 1270 | #define RT5682_SAR_POW_DIS (0x0 << 12) | |
| 1271 | #define RT5682_SAR_RST_MASK (0x1 << 11) | |
| 1272 | #define RT5682_SAR_RST_NORMAL (0x1 << 11) | |
| 1273 | #define RT5682_SAR_RST (0x0 << 11) | |
| 1274 | #define RT5682_SAR_BYPASS_MASK (0x1 << 10) | |
| 1275 | #define RT5682_SAR_BYPASS_EN (0x1 << 10) | |
| 1276 | #define RT5682_SAR_BYPASS_DIS (0x0 << 10) | |
| 1277 | #define RT5682_SAR_SEL_MB1_MASK (0x1 << 9) | |
| 1278 | #define RT5682_SAR_SEL_MB1_SEL (0x1 << 9) | |
| 1279 | #define RT5682_SAR_SEL_MB1_NOSEL (0x0 << 9) | |
| 1280 | #define RT5682_SAR_SEL_MB2_MASK (0x1 << 8) | |
| 1281 | #define RT5682_SAR_SEL_MB2_SEL (0x1 << 8) | |
| 1282 | #define RT5682_SAR_SEL_MB2_NOSEL (0x0 << 8) | |
| 1283 | #define RT5682_SAR_SEL_MODE_MASK (0x1 << 7) | |
| 1284 | #define RT5682_SAR_SEL_MODE_CMP (0x1 << 7) | |
| 1285 | #define RT5682_SAR_SEL_MODE_ADC (0x0 << 7) | |
| 1286 | #define RT5682_SAR_SEL_MB1_MB2_MASK (0x1 << 5) | |
| 1287 | #define RT5682_SAR_SEL_MB1_MB2_AUTO (0x1 << 5) | |
| 1288 | #define RT5682_SAR_SEL_MB1_MB2_MANU (0x0 << 5) | |
| 1289 | #define RT5682_SAR_SEL_SIGNAL_MASK (0x1 << 4) | |
| 1290 | #define RT5682_SAR_SEL_SIGNAL_AUTO (0x1 << 4) | |
| 1291 | #define RT5682_SAR_SEL_SIGNAL_MANU (0x0 << 4) | |
| 1292 | ||
| 1293 | /* SAR ADC Inline Command Control 13 (0x021c) */ | |
| 1294 | #define RT5682_SAR_SOUR_MASK (0x3f) | |
| 1295 | #define RT5682_SAR_SOUR_BTN (0x3f) | |
| 1296 | #define RT5682_SAR_SOUR_TYPE (0x0) | |
| 1297 | ||
| 1298 | ||
| 1299 | /* System Clock Source */ | |
| 1300 | enum { | |
| 1301 | RT5682_SCLK_S_MCLK, | |
| 1302 | RT5682_SCLK_S_PLL1, | |
| 1303 | RT5682_SCLK_S_PLL2, | |
| 1304 | RT5682_SCLK_S_RCCLK, | |
| 1305 | }; | |
| 1306 | ||
| 1307 | /* PLL Source */ | |
| 1308 | enum { | |
| 1309 | RT5682_PLL1_S_MCLK, | |
| 1310 | RT5682_PLL1_S_BCLK1, | |
| 1311 | RT5682_PLL1_S_RCCLK, | |
| 1312 | }; | |
| 1313 | ||
| 1314 | enum { | |
| 1315 | RT5682_AIF1, | |
| 1316 | RT5682_AIF2, | |
| 1317 | RT5682_AIFS | |
| 1318 | }; | |
| 1319 | ||
| 1320 | /* filter mask */ | |
| 1321 | enum { | |
| 1322 | RT5682_DA_STEREO1_FILTER = 0x1, | |
| 1323 | RT5682_AD_STEREO1_FILTER = (0x1 << 1), | |
| 1324 | }; | |
| 1325 | ||
| 1326 | enum { | |
| 1327 | RT5682_CLK_SEL_SYS, | |
| 1328 | RT5682_CLK_SEL_I2S1_ASRC, | |
| 1329 | RT5682_CLK_SEL_I2S2_ASRC, | |
| 1330 | }; | |
| 1331 | ||
| 1332 | int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, | |
| 1333 | unsigned int filter_mask, unsigned int clk_src); | |
| 1334 | ||
| 1335 | #endif /* __RT5682_H__ */ |