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9b34e6cc ZZ |
1 | /* |
2 | * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/clk.h> | |
9b34e6cc ZZ |
19 | #include <linux/regulator/driver.h> |
20 | #include <linux/regulator/machine.h> | |
21 | #include <linux/regulator/consumer.h> | |
58e49424 | 22 | #include <linux/of_device.h> |
9b34e6cc ZZ |
23 | #include <sound/core.h> |
24 | #include <sound/tlv.h> | |
25 | #include <sound/pcm.h> | |
26 | #include <sound/pcm_params.h> | |
27 | #include <sound/soc.h> | |
28 | #include <sound/soc-dapm.h> | |
29 | #include <sound/initval.h> | |
9b34e6cc ZZ |
30 | |
31 | #include "sgtl5000.h" | |
32 | ||
33 | #define SGTL5000_DAP_REG_OFFSET 0x0100 | |
34 | #define SGTL5000_MAX_REG_OFFSET 0x013A | |
35 | ||
151798f8 WS |
36 | /* default value of sgtl5000 registers */ |
37 | static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = { | |
38 | [SGTL5000_CHIP_CLK_CTRL] = 0x0008, | |
39 | [SGTL5000_CHIP_I2S_CTRL] = 0x0010, | |
40 | [SGTL5000_CHIP_SSS_CTRL] = 0x0008, | |
41 | [SGTL5000_CHIP_DAC_VOL] = 0x3c3c, | |
42 | [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f, | |
43 | [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818, | |
44 | [SGTL5000_CHIP_ANA_CTRL] = 0x0111, | |
45 | [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404, | |
46 | [SGTL5000_CHIP_ANA_POWER] = 0x7060, | |
47 | [SGTL5000_CHIP_PLL_CTRL] = 0x5000, | |
48 | [SGTL5000_DAP_BASS_ENHANCE] = 0x0040, | |
49 | [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f, | |
50 | [SGTL5000_DAP_SURROUND] = 0x0040, | |
51 | [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f, | |
52 | [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f, | |
53 | [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f, | |
54 | [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f, | |
55 | [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f, | |
56 | [SGTL5000_DAP_MAIN_CHAN] = 0x8000, | |
57 | [SGTL5000_DAP_AVC_CTRL] = 0x0510, | |
58 | [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473, | |
59 | [SGTL5000_DAP_AVC_ATTACK] = 0x0028, | |
60 | [SGTL5000_DAP_AVC_DECAY] = 0x0050, | |
9b34e6cc ZZ |
61 | }; |
62 | ||
63 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ | |
64 | enum sgtl5000_regulator_supplies { | |
65 | VDDA, | |
66 | VDDIO, | |
67 | VDDD, | |
68 | SGTL5000_SUPPLY_NUM | |
69 | }; | |
70 | ||
71 | /* vddd is optional supply */ | |
72 | static const char *supply_names[SGTL5000_SUPPLY_NUM] = { | |
73 | "VDDA", | |
74 | "VDDIO", | |
75 | "VDDD" | |
76 | }; | |
77 | ||
78 | #define LDO_CONSUMER_NAME "VDDD_LDO" | |
79 | #define LDO_VOLTAGE 1200000 | |
80 | ||
81 | static struct regulator_consumer_supply ldo_consumer[] = { | |
82 | REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), | |
83 | }; | |
84 | ||
61a142b7 | 85 | static struct regulator_init_data ldo_init_data = { |
9b34e6cc | 86 | .constraints = { |
cd041f64 FE |
87 | .min_uV = 1200000, |
88 | .max_uV = 1200000, | |
9b34e6cc ZZ |
89 | .valid_modes_mask = REGULATOR_MODE_NORMAL, |
90 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
91 | }, | |
92 | .num_consumer_supplies = 1, | |
93 | .consumer_supplies = &ldo_consumer[0], | |
94 | }; | |
95 | ||
96 | /* | |
97 | * sgtl5000 internal ldo regulator, | |
98 | * enabled when VDDD not provided | |
99 | */ | |
100 | struct ldo_regulator { | |
101 | struct regulator_desc desc; | |
102 | struct regulator_dev *dev; | |
103 | int voltage; | |
104 | void *codec_data; | |
105 | bool enabled; | |
106 | }; | |
107 | ||
108 | /* sgtl5000 private structure in codec */ | |
109 | struct sgtl5000_priv { | |
110 | int sysclk; /* sysclk rate */ | |
111 | int master; /* i2s master or not */ | |
112 | int fmt; /* i2s data format */ | |
113 | struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; | |
114 | struct ldo_regulator *ldo; | |
115 | }; | |
116 | ||
117 | /* | |
118 | * mic_bias power on/off share the same register bits with | |
119 | * output impedance of mic bias, when power on mic bias, we | |
120 | * need reclaim it to impedance value. | |
121 | * 0x0 = Powered off | |
122 | * 0x1 = 2Kohm | |
123 | * 0x2 = 4Kohm | |
124 | * 0x3 = 8Kohm | |
125 | */ | |
126 | static int mic_bias_event(struct snd_soc_dapm_widget *w, | |
127 | struct snd_kcontrol *kcontrol, int event) | |
128 | { | |
129 | switch (event) { | |
130 | case SND_SOC_DAPM_POST_PMU: | |
131 | /* change mic bias resistor to 4Kohm */ | |
132 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, | |
dc56c5a8 AL |
133 | SGTL5000_BIAS_R_MASK, |
134 | SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT); | |
9b34e6cc ZZ |
135 | break; |
136 | ||
137 | case SND_SOC_DAPM_PRE_PMD: | |
9b34e6cc | 138 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, |
dc56c5a8 | 139 | SGTL5000_BIAS_R_MASK, 0); |
9b34e6cc ZZ |
140 | break; |
141 | } | |
142 | return 0; | |
143 | } | |
144 | ||
145 | /* | |
f0cdcf3a ZZ |
146 | * As manual described, ADC/DAC only works when VAG powerup, |
147 | * So enabled VAG before ADC/DAC up. | |
148 | * In power down case, we need wait 400ms when vag fully ramped down. | |
9b34e6cc | 149 | */ |
f0cdcf3a | 150 | static int power_vag_event(struct snd_soc_dapm_widget *w, |
9b34e6cc ZZ |
151 | struct snd_kcontrol *kcontrol, int event) |
152 | { | |
153 | switch (event) { | |
154 | case SND_SOC_DAPM_PRE_PMU: | |
155 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, | |
156 | SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); | |
157 | break; | |
158 | ||
f0cdcf3a | 159 | case SND_SOC_DAPM_POST_PMD: |
9b34e6cc ZZ |
160 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, |
161 | SGTL5000_VAG_POWERUP, 0); | |
162 | msleep(400); | |
163 | break; | |
164 | default: | |
165 | break; | |
166 | } | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
171 | /* input sources for ADC */ | |
172 | static const char *adc_mux_text[] = { | |
173 | "MIC_IN", "LINE_IN" | |
174 | }; | |
175 | ||
176 | static const struct soc_enum adc_enum = | |
177 | SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text); | |
178 | ||
179 | static const struct snd_kcontrol_new adc_mux = | |
180 | SOC_DAPM_ENUM("Capture Mux", adc_enum); | |
181 | ||
182 | /* input sources for DAC */ | |
183 | static const char *dac_mux_text[] = { | |
184 | "DAC", "LINE_IN" | |
185 | }; | |
186 | ||
187 | static const struct soc_enum dac_enum = | |
188 | SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text); | |
189 | ||
190 | static const struct snd_kcontrol_new dac_mux = | |
191 | SOC_DAPM_ENUM("Headphone Mux", dac_enum); | |
192 | ||
193 | static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { | |
194 | SND_SOC_DAPM_INPUT("LINE_IN"), | |
195 | SND_SOC_DAPM_INPUT("MIC_IN"), | |
196 | ||
197 | SND_SOC_DAPM_OUTPUT("HP_OUT"), | |
198 | SND_SOC_DAPM_OUTPUT("LINE_OUT"), | |
199 | ||
8fc8ec92 MB |
200 | SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, |
201 | mic_bias_event, | |
202 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
9b34e6cc | 203 | |
f0cdcf3a ZZ |
204 | SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), |
205 | SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), | |
9b34e6cc ZZ |
206 | |
207 | SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), | |
208 | SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), | |
209 | ||
210 | /* aif for i2s input */ | |
211 | SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", | |
212 | 0, SGTL5000_CHIP_DIG_POWER, | |
213 | 0, 0), | |
214 | ||
215 | /* aif for i2s output */ | |
216 | SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", | |
217 | 0, SGTL5000_CHIP_DIG_POWER, | |
218 | 1, 0), | |
219 | ||
f0cdcf3a ZZ |
220 | SND_SOC_DAPM_SUPPLY("VAG_POWER", SGTL5000_CHIP_ANA_POWER, 7, 0, |
221 | power_vag_event, | |
222 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
9b34e6cc | 223 | |
f0cdcf3a | 224 | SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), |
9b34e6cc ZZ |
225 | SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), |
226 | }; | |
227 | ||
228 | /* routes for sgtl5000 */ | |
89989637 | 229 | static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { |
9b34e6cc ZZ |
230 | {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ |
231 | {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ | |
232 | ||
f0cdcf3a | 233 | {"ADC", NULL, "VAG_POWER"}, |
9b34e6cc ZZ |
234 | {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ |
235 | {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ | |
236 | ||
f0cdcf3a | 237 | {"DAC", NULL, "VAG_POWER"}, |
9b34e6cc ZZ |
238 | {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ |
239 | {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ | |
240 | {"LO", NULL, "DAC"}, /* dac --> line_out */ | |
241 | ||
eef69ac7 | 242 | {"LINE_IN", NULL, "VAG_POWER"}, |
9b34e6cc ZZ |
243 | {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ |
244 | {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ | |
245 | ||
246 | {"LINE_OUT", NULL, "LO"}, | |
247 | {"HP_OUT", NULL, "HP"}, | |
248 | }; | |
249 | ||
250 | /* custom function to fetch info of PCM playback volume */ | |
251 | static int dac_info_volsw(struct snd_kcontrol *kcontrol, | |
252 | struct snd_ctl_elem_info *uinfo) | |
253 | { | |
254 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
255 | uinfo->count = 2; | |
256 | uinfo->value.integer.min = 0; | |
257 | uinfo->value.integer.max = 0xfc - 0x3c; | |
258 | return 0; | |
259 | } | |
260 | ||
261 | /* | |
262 | * custom function to get of PCM playback volume | |
263 | * | |
264 | * dac volume register | |
265 | * 15-------------8-7--------------0 | |
266 | * | R channel vol | L channel vol | | |
267 | * ------------------------------- | |
268 | * | |
269 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
270 | * | |
271 | * register values map to dB | |
272 | * 0x3B and less = Reserved | |
273 | * 0x3C = 0 dB | |
274 | * 0x3D = -0.5 dB | |
275 | * 0xF0 = -90 dB | |
276 | * 0xFC and greater = Muted | |
277 | * | |
278 | * register value map to userspace value | |
279 | * | |
280 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
281 | * ------------------------------ | |
282 | * userspace value 0xc0 0 | |
283 | */ | |
284 | static int dac_get_volsw(struct snd_kcontrol *kcontrol, | |
285 | struct snd_ctl_elem_value *ucontrol) | |
286 | { | |
287 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
288 | int reg; | |
289 | int l; | |
290 | int r; | |
291 | ||
292 | reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); | |
293 | ||
294 | /* get left channel volume */ | |
295 | l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; | |
296 | ||
297 | /* get right channel volume */ | |
298 | r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
299 | ||
300 | /* make sure value fall in (0x3c,0xfc) */ | |
301 | l = clamp(l, 0x3c, 0xfc); | |
302 | r = clamp(r, 0x3c, 0xfc); | |
303 | ||
304 | /* invert it and map to userspace value */ | |
305 | l = 0xfc - l; | |
306 | r = 0xfc - r; | |
307 | ||
308 | ucontrol->value.integer.value[0] = l; | |
309 | ucontrol->value.integer.value[1] = r; | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | /* | |
315 | * custom function to put of PCM playback volume | |
316 | * | |
317 | * dac volume register | |
318 | * 15-------------8-7--------------0 | |
319 | * | R channel vol | L channel vol | | |
320 | * ------------------------------- | |
321 | * | |
322 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
323 | * | |
324 | * register values map to dB | |
325 | * 0x3B and less = Reserved | |
326 | * 0x3C = 0 dB | |
327 | * 0x3D = -0.5 dB | |
328 | * 0xF0 = -90 dB | |
329 | * 0xFC and greater = Muted | |
330 | * | |
331 | * userspace value map to register value | |
332 | * | |
333 | * userspace value 0xc0 0 | |
334 | * ------------------------------ | |
335 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
336 | */ | |
337 | static int dac_put_volsw(struct snd_kcontrol *kcontrol, | |
338 | struct snd_ctl_elem_value *ucontrol) | |
339 | { | |
340 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
341 | int reg; | |
342 | int l; | |
343 | int r; | |
344 | ||
345 | l = ucontrol->value.integer.value[0]; | |
346 | r = ucontrol->value.integer.value[1]; | |
347 | ||
348 | /* make sure userspace volume fall in (0, 0xfc-0x3c) */ | |
349 | l = clamp(l, 0, 0xfc - 0x3c); | |
350 | r = clamp(r, 0, 0xfc - 0x3c); | |
351 | ||
352 | /* invert it, get the value can be set to register */ | |
353 | l = 0xfc - l; | |
354 | r = 0xfc - r; | |
355 | ||
356 | /* shift to get the register value */ | |
357 | reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | | |
358 | r << SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
359 | ||
360 | snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); | |
366 | ||
367 | /* tlv for mic gain, 0db 20db 30db 40db */ | |
368 | static const unsigned int mic_gain_tlv[] = { | |
740fb9d5 | 369 | TLV_DB_RANGE_HEAD(2), |
9b34e6cc ZZ |
370 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
371 | 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), | |
372 | }; | |
373 | ||
374 | /* tlv for hp volume, -51.5db to 12.0db, step .5db */ | |
375 | static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); | |
376 | ||
377 | static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { | |
378 | /* SOC_DOUBLE_S8_TLV with invert */ | |
379 | { | |
380 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
381 | .name = "PCM Playback Volume", | |
382 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | | |
383 | SNDRV_CTL_ELEM_ACCESS_READWRITE, | |
384 | .info = dac_info_volsw, | |
385 | .get = dac_get_volsw, | |
386 | .put = dac_put_volsw, | |
387 | }, | |
388 | ||
389 | SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), | |
390 | SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", | |
391 | SGTL5000_CHIP_ANA_ADC_CTRL, | |
392 | 8, 2, 0, capture_6db_attenuate), | |
393 | SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), | |
394 | ||
395 | SOC_DOUBLE_TLV("Headphone Playback Volume", | |
396 | SGTL5000_CHIP_ANA_HP_CTRL, | |
397 | 0, 8, | |
398 | 0x7f, 1, | |
399 | headphone_volume), | |
400 | SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, | |
401 | 5, 1, 0), | |
402 | ||
403 | SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, | |
b50684da | 404 | 0, 3, 0, mic_gain_tlv), |
9b34e6cc ZZ |
405 | }; |
406 | ||
407 | /* mute the codec used by alsa core */ | |
408 | static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
409 | { | |
410 | struct snd_soc_codec *codec = codec_dai->codec; | |
411 | u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; | |
412 | ||
413 | snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, | |
414 | adcdac_ctrl, mute ? adcdac_ctrl : 0); | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
419 | /* set codec format */ | |
420 | static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
421 | { | |
422 | struct snd_soc_codec *codec = codec_dai->codec; | |
423 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
424 | u16 i2sctl = 0; | |
425 | ||
426 | sgtl5000->master = 0; | |
427 | /* | |
428 | * i2s clock and frame master setting. | |
429 | * ONLY support: | |
430 | * - clock and frame slave, | |
431 | * - clock and frame master | |
432 | */ | |
433 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
434 | case SND_SOC_DAIFMT_CBS_CFS: | |
435 | break; | |
436 | case SND_SOC_DAIFMT_CBM_CFM: | |
437 | i2sctl |= SGTL5000_I2S_MASTER; | |
438 | sgtl5000->master = 1; | |
439 | break; | |
440 | default: | |
441 | return -EINVAL; | |
442 | } | |
443 | ||
444 | /* setting i2s data format */ | |
445 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
446 | case SND_SOC_DAIFMT_DSP_A: | |
447 | i2sctl |= SGTL5000_I2S_MODE_PCM; | |
448 | break; | |
449 | case SND_SOC_DAIFMT_DSP_B: | |
450 | i2sctl |= SGTL5000_I2S_MODE_PCM; | |
451 | i2sctl |= SGTL5000_I2S_LRALIGN; | |
452 | break; | |
453 | case SND_SOC_DAIFMT_I2S: | |
454 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; | |
455 | break; | |
456 | case SND_SOC_DAIFMT_RIGHT_J: | |
457 | i2sctl |= SGTL5000_I2S_MODE_RJ; | |
458 | i2sctl |= SGTL5000_I2S_LRPOL; | |
459 | break; | |
460 | case SND_SOC_DAIFMT_LEFT_J: | |
461 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; | |
462 | i2sctl |= SGTL5000_I2S_LRALIGN; | |
463 | break; | |
464 | default: | |
465 | return -EINVAL; | |
466 | } | |
467 | ||
468 | sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
469 | ||
470 | /* Clock inversion */ | |
471 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
472 | case SND_SOC_DAIFMT_NB_NF: | |
473 | break; | |
474 | case SND_SOC_DAIFMT_IB_NF: | |
475 | i2sctl |= SGTL5000_I2S_SCLK_INV; | |
476 | break; | |
477 | default: | |
478 | return -EINVAL; | |
479 | } | |
480 | ||
481 | snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | /* set codec sysclk */ | |
487 | static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
488 | int clk_id, unsigned int freq, int dir) | |
489 | { | |
490 | struct snd_soc_codec *codec = codec_dai->codec; | |
491 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
492 | ||
493 | switch (clk_id) { | |
494 | case SGTL5000_SYSCLK: | |
495 | sgtl5000->sysclk = freq; | |
496 | break; | |
497 | default: | |
498 | return -EINVAL; | |
499 | } | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | /* | |
505 | * set clock according to i2s frame clock, | |
506 | * sgtl5000 provide 2 clock sources. | |
507 | * 1. sys_mclk. sample freq can only configure to | |
508 | * 1/256, 1/384, 1/512 of sys_mclk. | |
509 | * 2. pll. can derive any audio clocks. | |
510 | * | |
511 | * clock setting rules: | |
512 | * 1. in slave mode, only sys_mclk can use. | |
513 | * 2. as constraint by sys_mclk, sample freq should | |
514 | * set to 32k, 44.1k and above. | |
515 | * 3. using sys_mclk prefer to pll to save power. | |
516 | */ | |
517 | static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) | |
518 | { | |
519 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
520 | int clk_ctl = 0; | |
521 | int sys_fs; /* sample freq */ | |
522 | ||
523 | /* | |
524 | * sample freq should be divided by frame clock, | |
525 | * if frame clock lower than 44.1khz, sample feq should set to | |
526 | * 32khz or 44.1khz. | |
527 | */ | |
528 | switch (frame_rate) { | |
529 | case 8000: | |
530 | case 16000: | |
531 | sys_fs = 32000; | |
532 | break; | |
533 | case 11025: | |
534 | case 22050: | |
535 | sys_fs = 44100; | |
536 | break; | |
537 | default: | |
538 | sys_fs = frame_rate; | |
539 | break; | |
540 | } | |
541 | ||
542 | /* set divided factor of frame clock */ | |
543 | switch (sys_fs / frame_rate) { | |
544 | case 4: | |
545 | clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; | |
546 | break; | |
547 | case 2: | |
548 | clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; | |
549 | break; | |
550 | case 1: | |
551 | clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; | |
552 | break; | |
553 | default: | |
554 | return -EINVAL; | |
555 | } | |
556 | ||
557 | /* set the sys_fs according to frame rate */ | |
558 | switch (sys_fs) { | |
559 | case 32000: | |
560 | clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; | |
561 | break; | |
562 | case 44100: | |
563 | clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; | |
564 | break; | |
565 | case 48000: | |
566 | clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; | |
567 | break; | |
568 | case 96000: | |
569 | clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; | |
570 | break; | |
571 | default: | |
572 | dev_err(codec->dev, "frame rate %d not supported\n", | |
573 | frame_rate); | |
574 | return -EINVAL; | |
575 | } | |
576 | ||
577 | /* | |
578 | * calculate the divider of mclk/sample_freq, | |
579 | * factor of freq =96k can only be 256, since mclk in range (12m,27m) | |
580 | */ | |
581 | switch (sgtl5000->sysclk / sys_fs) { | |
582 | case 256: | |
583 | clk_ctl |= SGTL5000_MCLK_FREQ_256FS << | |
584 | SGTL5000_MCLK_FREQ_SHIFT; | |
585 | break; | |
586 | case 384: | |
587 | clk_ctl |= SGTL5000_MCLK_FREQ_384FS << | |
588 | SGTL5000_MCLK_FREQ_SHIFT; | |
589 | break; | |
590 | case 512: | |
591 | clk_ctl |= SGTL5000_MCLK_FREQ_512FS << | |
592 | SGTL5000_MCLK_FREQ_SHIFT; | |
593 | break; | |
594 | default: | |
595 | /* if mclk not satisify the divider, use pll */ | |
596 | if (sgtl5000->master) { | |
597 | clk_ctl |= SGTL5000_MCLK_FREQ_PLL << | |
598 | SGTL5000_MCLK_FREQ_SHIFT; | |
599 | } else { | |
600 | dev_err(codec->dev, | |
601 | "PLL not supported in slave mode\n"); | |
602 | return -EINVAL; | |
603 | } | |
604 | } | |
605 | ||
606 | /* if using pll, please check manual 6.4.2 for detail */ | |
607 | if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { | |
608 | u64 out, t; | |
609 | int div2; | |
610 | int pll_ctl; | |
611 | unsigned int in, int_div, frac_div; | |
612 | ||
613 | if (sgtl5000->sysclk > 17000000) { | |
614 | div2 = 1; | |
615 | in = sgtl5000->sysclk / 2; | |
616 | } else { | |
617 | div2 = 0; | |
618 | in = sgtl5000->sysclk; | |
619 | } | |
620 | if (sys_fs == 44100) | |
621 | out = 180633600; | |
622 | else | |
623 | out = 196608000; | |
624 | t = do_div(out, in); | |
625 | int_div = out; | |
626 | t *= 2048; | |
627 | do_div(t, in); | |
628 | frac_div = t; | |
629 | pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | | |
630 | frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; | |
631 | ||
632 | snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); | |
633 | if (div2) | |
634 | snd_soc_update_bits(codec, | |
635 | SGTL5000_CHIP_CLK_TOP_CTRL, | |
636 | SGTL5000_INPUT_FREQ_DIV2, | |
637 | SGTL5000_INPUT_FREQ_DIV2); | |
638 | else | |
639 | snd_soc_update_bits(codec, | |
640 | SGTL5000_CHIP_CLK_TOP_CTRL, | |
641 | SGTL5000_INPUT_FREQ_DIV2, | |
642 | 0); | |
643 | ||
644 | /* power up pll */ | |
645 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
646 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, | |
647 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); | |
648 | } else { | |
649 | /* power down pll */ | |
650 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
651 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, | |
652 | 0); | |
653 | } | |
654 | ||
655 | /* if using pll, clk_ctrl must be set after pll power up */ | |
656 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | /* | |
662 | * Set PCM DAI bit size and sample rate. | |
663 | * input: params_rate, params_fmt | |
664 | */ | |
665 | static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, | |
666 | struct snd_pcm_hw_params *params, | |
667 | struct snd_soc_dai *dai) | |
668 | { | |
e6968a17 | 669 | struct snd_soc_codec *codec = dai->codec; |
9b34e6cc ZZ |
670 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); |
671 | int channels = params_channels(params); | |
672 | int i2s_ctl = 0; | |
673 | int stereo; | |
674 | int ret; | |
675 | ||
676 | /* sysclk should already set */ | |
677 | if (!sgtl5000->sysclk) { | |
678 | dev_err(codec->dev, "%s: set sysclk first!\n", __func__); | |
679 | return -EFAULT; | |
680 | } | |
681 | ||
682 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
683 | stereo = SGTL5000_DAC_STEREO; | |
684 | else | |
685 | stereo = SGTL5000_ADC_STEREO; | |
686 | ||
687 | /* set mono to save power */ | |
688 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, | |
689 | channels == 1 ? 0 : stereo); | |
690 | ||
691 | /* set codec clock base on lrclk */ | |
692 | ret = sgtl5000_set_clock(codec, params_rate(params)); | |
693 | if (ret) | |
694 | return ret; | |
695 | ||
696 | /* set i2s data format */ | |
697 | switch (params_format(params)) { | |
698 | case SNDRV_PCM_FORMAT_S16_LE: | |
699 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) | |
700 | return -EINVAL; | |
701 | i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; | |
702 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << | |
703 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
704 | break; | |
705 | case SNDRV_PCM_FORMAT_S20_3LE: | |
706 | i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; | |
707 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
708 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
709 | break; | |
710 | case SNDRV_PCM_FORMAT_S24_LE: | |
711 | i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; | |
712 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
713 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
714 | break; | |
715 | case SNDRV_PCM_FORMAT_S32_LE: | |
716 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) | |
717 | return -EINVAL; | |
718 | i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; | |
719 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
720 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
721 | break; | |
722 | default: | |
723 | return -EINVAL; | |
724 | } | |
725 | ||
33cb92cf AL |
726 | snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, |
727 | SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, | |
728 | i2s_ctl); | |
9b34e6cc ZZ |
729 | |
730 | return 0; | |
731 | } | |
732 | ||
333802e9 | 733 | #ifdef CONFIG_REGULATOR |
9b34e6cc ZZ |
734 | static int ldo_regulator_is_enabled(struct regulator_dev *dev) |
735 | { | |
736 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
737 | ||
738 | return ldo->enabled; | |
739 | } | |
740 | ||
741 | static int ldo_regulator_enable(struct regulator_dev *dev) | |
742 | { | |
743 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
744 | struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; | |
745 | int reg; | |
746 | ||
747 | if (ldo_regulator_is_enabled(dev)) | |
748 | return 0; | |
749 | ||
750 | /* set regulator value firstly */ | |
751 | reg = (1600 - ldo->voltage / 1000) / 50; | |
752 | reg = clamp(reg, 0x0, 0xf); | |
753 | ||
754 | /* amend the voltage value, unit: uV */ | |
755 | ldo->voltage = (1600 - reg * 50) * 1000; | |
756 | ||
757 | /* set voltage to register */ | |
758 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, | |
064a4bce | 759 | SGTL5000_LINREG_VDDD_MASK, reg); |
9b34e6cc ZZ |
760 | |
761 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
762 | SGTL5000_LINEREG_D_POWERUP, | |
763 | SGTL5000_LINEREG_D_POWERUP); | |
764 | ||
765 | /* when internal ldo enabled, simple digital power can be disabled */ | |
766 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
767 | SGTL5000_LINREG_SIMPLE_POWERUP, | |
768 | 0); | |
769 | ||
770 | ldo->enabled = 1; | |
771 | return 0; | |
772 | } | |
773 | ||
774 | static int ldo_regulator_disable(struct regulator_dev *dev) | |
775 | { | |
776 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
777 | struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; | |
778 | ||
779 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
780 | SGTL5000_LINEREG_D_POWERUP, | |
781 | 0); | |
782 | ||
783 | /* clear voltage info */ | |
784 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, | |
064a4bce | 785 | SGTL5000_LINREG_VDDD_MASK, 0); |
9b34e6cc ZZ |
786 | |
787 | ldo->enabled = 0; | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
792 | static int ldo_regulator_get_voltage(struct regulator_dev *dev) | |
793 | { | |
794 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
795 | ||
796 | return ldo->voltage; | |
797 | } | |
798 | ||
799 | static struct regulator_ops ldo_regulator_ops = { | |
800 | .is_enabled = ldo_regulator_is_enabled, | |
801 | .enable = ldo_regulator_enable, | |
802 | .disable = ldo_regulator_disable, | |
803 | .get_voltage = ldo_regulator_get_voltage, | |
804 | }; | |
805 | ||
806 | static int ldo_regulator_register(struct snd_soc_codec *codec, | |
807 | struct regulator_init_data *init_data, | |
808 | int voltage) | |
809 | { | |
810 | struct ldo_regulator *ldo; | |
5b13de7a | 811 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); |
c172708d | 812 | struct regulator_config config = { }; |
9b34e6cc ZZ |
813 | |
814 | ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); | |
815 | ||
816 | if (!ldo) { | |
817 | dev_err(codec->dev, "failed to allocate ldo_regulator\n"); | |
818 | return -ENOMEM; | |
819 | } | |
820 | ||
821 | ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); | |
822 | if (!ldo->desc.name) { | |
823 | kfree(ldo); | |
824 | dev_err(codec->dev, "failed to allocate decs name memory\n"); | |
825 | return -ENOMEM; | |
826 | } | |
827 | ||
828 | ldo->desc.type = REGULATOR_VOLTAGE; | |
829 | ldo->desc.owner = THIS_MODULE; | |
830 | ldo->desc.ops = &ldo_regulator_ops; | |
831 | ldo->desc.n_voltages = 1; | |
832 | ||
833 | ldo->codec_data = codec; | |
834 | ldo->voltage = voltage; | |
835 | ||
c172708d MB |
836 | config.dev = codec->dev; |
837 | config.driver_data = ldo; | |
838 | config.init_data = init_data; | |
839 | ||
840 | ldo->dev = regulator_register(&ldo->desc, &config); | |
9b34e6cc | 841 | if (IS_ERR(ldo->dev)) { |
62f75aaf DC |
842 | int ret = PTR_ERR(ldo->dev); |
843 | ||
9b34e6cc ZZ |
844 | dev_err(codec->dev, "failed to register regulator\n"); |
845 | kfree(ldo->desc.name); | |
846 | kfree(ldo); | |
847 | ||
62f75aaf | 848 | return ret; |
9b34e6cc | 849 | } |
5b13de7a | 850 | sgtl5000->ldo = ldo; |
9b34e6cc ZZ |
851 | |
852 | return 0; | |
853 | } | |
854 | ||
855 | static int ldo_regulator_remove(struct snd_soc_codec *codec) | |
856 | { | |
857 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
858 | struct ldo_regulator *ldo = sgtl5000->ldo; | |
859 | ||
860 | if (!ldo) | |
861 | return 0; | |
862 | ||
863 | regulator_unregister(ldo->dev); | |
864 | kfree(ldo->desc.name); | |
865 | kfree(ldo); | |
866 | ||
867 | return 0; | |
868 | } | |
333802e9 MB |
869 | #else |
870 | static int ldo_regulator_register(struct snd_soc_codec *codec, | |
871 | struct regulator_init_data *init_data, | |
872 | int voltage) | |
873 | { | |
09bddc8e | 874 | dev_err(codec->dev, "this setup needs regulator support in the kernel\n"); |
333802e9 MB |
875 | return -EINVAL; |
876 | } | |
877 | ||
878 | static int ldo_regulator_remove(struct snd_soc_codec *codec) | |
879 | { | |
880 | return 0; | |
881 | } | |
882 | #endif | |
9b34e6cc ZZ |
883 | |
884 | /* | |
885 | * set dac bias | |
886 | * common state changes: | |
887 | * startup: | |
888 | * off --> standby --> prepare --> on | |
889 | * standby --> prepare --> on | |
890 | * | |
891 | * stop: | |
892 | * on --> prepare --> standby | |
893 | */ | |
894 | static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, | |
895 | enum snd_soc_bias_level level) | |
896 | { | |
897 | int ret; | |
898 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
899 | ||
900 | switch (level) { | |
901 | case SND_SOC_BIAS_ON: | |
902 | case SND_SOC_BIAS_PREPARE: | |
903 | break; | |
904 | case SND_SOC_BIAS_STANDBY: | |
905 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
906 | ret = regulator_bulk_enable( | |
907 | ARRAY_SIZE(sgtl5000->supplies), | |
908 | sgtl5000->supplies); | |
909 | if (ret) | |
910 | return ret; | |
911 | udelay(10); | |
912 | } | |
913 | ||
914 | break; | |
915 | case SND_SOC_BIAS_OFF: | |
916 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
917 | sgtl5000->supplies); | |
918 | break; | |
919 | } | |
920 | ||
921 | codec->dapm.bias_level = level; | |
922 | return 0; | |
923 | } | |
924 | ||
925 | #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
926 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
927 | SNDRV_PCM_FMTBIT_S24_LE |\ | |
928 | SNDRV_PCM_FMTBIT_S32_LE) | |
929 | ||
85e7652d | 930 | static const struct snd_soc_dai_ops sgtl5000_ops = { |
9b34e6cc ZZ |
931 | .hw_params = sgtl5000_pcm_hw_params, |
932 | .digital_mute = sgtl5000_digital_mute, | |
933 | .set_fmt = sgtl5000_set_dai_fmt, | |
934 | .set_sysclk = sgtl5000_set_dai_sysclk, | |
935 | }; | |
936 | ||
937 | static struct snd_soc_dai_driver sgtl5000_dai = { | |
938 | .name = "sgtl5000", | |
939 | .playback = { | |
940 | .stream_name = "Playback", | |
941 | .channels_min = 1, | |
942 | .channels_max = 2, | |
943 | /* | |
944 | * only support 8~48K + 96K, | |
945 | * TODO modify hw_param to support more | |
946 | */ | |
947 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
948 | .formats = SGTL5000_FORMATS, | |
949 | }, | |
950 | .capture = { | |
951 | .stream_name = "Capture", | |
952 | .channels_min = 1, | |
953 | .channels_max = 2, | |
954 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
955 | .formats = SGTL5000_FORMATS, | |
956 | }, | |
957 | .ops = &sgtl5000_ops, | |
958 | .symmetric_rates = 1, | |
959 | }; | |
960 | ||
961 | static int sgtl5000_volatile_register(struct snd_soc_codec *codec, | |
962 | unsigned int reg) | |
963 | { | |
964 | switch (reg) { | |
965 | case SGTL5000_CHIP_ID: | |
966 | case SGTL5000_CHIP_ADCDAC_CTRL: | |
967 | case SGTL5000_CHIP_ANA_STATUS: | |
968 | return 1; | |
969 | } | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
974 | #ifdef CONFIG_SUSPEND | |
84b315ee | 975 | static int sgtl5000_suspend(struct snd_soc_codec *codec) |
9b34e6cc ZZ |
976 | { |
977 | sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
982 | /* | |
983 | * restore all sgtl5000 registers, | |
984 | * since a big hole between dap and regular registers, | |
985 | * we will restore them respectively. | |
986 | */ | |
987 | static int sgtl5000_restore_regs(struct snd_soc_codec *codec) | |
988 | { | |
989 | u16 *cache = codec->reg_cache; | |
151798f8 | 990 | u16 reg; |
9b34e6cc ZZ |
991 | |
992 | /* restore regular registers */ | |
151798f8 | 993 | for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { |
9b34e6cc | 994 | |
bb362e2e | 995 | /* These regs should restore in particular order */ |
9b34e6cc ZZ |
996 | if (reg == SGTL5000_CHIP_ANA_POWER || |
997 | reg == SGTL5000_CHIP_CLK_CTRL || | |
998 | reg == SGTL5000_CHIP_LINREG_CTRL || | |
999 | reg == SGTL5000_CHIP_LINE_OUT_CTRL || | |
bb362e2e | 1000 | reg == SGTL5000_CHIP_REF_CTRL) |
9b34e6cc ZZ |
1001 | continue; |
1002 | ||
151798f8 | 1003 | snd_soc_write(codec, reg, cache[reg]); |
9b34e6cc ZZ |
1004 | } |
1005 | ||
1006 | /* restore dap registers */ | |
151798f8 WS |
1007 | for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2) |
1008 | snd_soc_write(codec, reg, cache[reg]); | |
9b34e6cc ZZ |
1009 | |
1010 | /* | |
bb362e2e ZZ |
1011 | * restore these regs according to the power setting sequence in |
1012 | * sgtl5000_set_power_regs() and clock setting sequence in | |
1013 | * sgtl5000_set_clock(). | |
1014 | * | |
1015 | * The order of restore is: | |
1016 | * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after | |
1017 | * SGTL5000_CHIP_ANA_POWER PLL bits set | |
1018 | * 2. SGTL5000_CHIP_LINREG_CTRL should be set before | |
1019 | * SGTL5000_CHIP_ANA_POWER LINREG_D restored | |
1020 | * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage, | |
1021 | * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored | |
9b34e6cc ZZ |
1022 | */ |
1023 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, | |
151798f8 | 1024 | cache[SGTL5000_CHIP_LINREG_CTRL]); |
9b34e6cc ZZ |
1025 | |
1026 | snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, | |
151798f8 | 1027 | cache[SGTL5000_CHIP_ANA_POWER]); |
9b34e6cc ZZ |
1028 | |
1029 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, | |
151798f8 | 1030 | cache[SGTL5000_CHIP_CLK_CTRL]); |
9b34e6cc ZZ |
1031 | |
1032 | snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, | |
151798f8 | 1033 | cache[SGTL5000_CHIP_REF_CTRL]); |
9b34e6cc ZZ |
1034 | |
1035 | snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, | |
151798f8 | 1036 | cache[SGTL5000_CHIP_LINE_OUT_CTRL]); |
9b34e6cc ZZ |
1037 | return 0; |
1038 | } | |
1039 | ||
1040 | static int sgtl5000_resume(struct snd_soc_codec *codec) | |
1041 | { | |
1042 | /* Bring the codec back up to standby to enable regulators */ | |
1043 | sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1044 | ||
1045 | /* Restore registers by cached in memory */ | |
1046 | sgtl5000_restore_regs(codec); | |
1047 | return 0; | |
1048 | } | |
1049 | #else | |
1050 | #define sgtl5000_suspend NULL | |
1051 | #define sgtl5000_resume NULL | |
1052 | #endif /* CONFIG_SUSPEND */ | |
1053 | ||
1054 | /* | |
1055 | * sgtl5000 has 3 internal power supplies: | |
1056 | * 1. VAG, normally set to vdda/2 | |
1057 | * 2. chargepump, set to different value | |
1058 | * according to voltage of vdda and vddio | |
1059 | * 3. line out VAG, normally set to vddio/2 | |
1060 | * | |
1061 | * and should be set according to: | |
1062 | * 1. vddd provided by external or not | |
1063 | * 2. vdda and vddio voltage value. > 3.1v or not | |
1064 | * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. | |
1065 | */ | |
1066 | static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) | |
1067 | { | |
1068 | int vddd; | |
1069 | int vdda; | |
1070 | int vddio; | |
1071 | u16 ana_pwr; | |
1072 | u16 lreg_ctrl; | |
1073 | int vag; | |
1074 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1075 | ||
1076 | vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); | |
1077 | vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); | |
1078 | vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); | |
1079 | ||
1080 | vdda = vdda / 1000; | |
1081 | vddio = vddio / 1000; | |
1082 | vddd = vddd / 1000; | |
1083 | ||
1084 | if (vdda <= 0 || vddio <= 0 || vddd < 0) { | |
1085 | dev_err(codec->dev, "regulator voltage not set correctly\n"); | |
1086 | ||
1087 | return -EINVAL; | |
1088 | } | |
1089 | ||
1090 | /* according to datasheet, maximum voltage of supplies */ | |
1091 | if (vdda > 3600 || vddio > 3600 || vddd > 1980) { | |
1092 | dev_err(codec->dev, | |
cf1ee98d | 1093 | "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", |
9b34e6cc ZZ |
1094 | vdda, vddio, vddd); |
1095 | ||
1096 | return -EINVAL; | |
1097 | } | |
1098 | ||
1099 | /* reset value */ | |
1100 | ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); | |
1101 | ana_pwr |= SGTL5000_DAC_STEREO | | |
1102 | SGTL5000_ADC_STEREO | | |
1103 | SGTL5000_REFTOP_POWERUP; | |
1104 | lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); | |
1105 | ||
1106 | if (vddio < 3100 && vdda < 3100) { | |
1107 | /* enable internal oscillator used for charge pump */ | |
1108 | snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, | |
1109 | SGTL5000_INT_OSC_EN, | |
1110 | SGTL5000_INT_OSC_EN); | |
1111 | /* Enable VDDC charge pump */ | |
1112 | ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; | |
1113 | } else if (vddio >= 3100 && vdda >= 3100) { | |
1114 | /* | |
1115 | * if vddio and vddd > 3.1v, | |
1116 | * charge pump should be clean before set ana_pwr | |
1117 | */ | |
1118 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
1119 | SGTL5000_VDDC_CHRGPMP_POWERUP, 0); | |
1120 | ||
1121 | /* VDDC use VDDIO rail */ | |
1122 | lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; | |
1123 | lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << | |
1124 | SGTL5000_VDDC_MAN_ASSN_SHIFT; | |
1125 | } | |
1126 | ||
1127 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); | |
1128 | ||
1129 | snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); | |
1130 | ||
1131 | /* set voltage to register */ | |
1132 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, | |
064a4bce | 1133 | SGTL5000_LINREG_VDDD_MASK, 0x8); |
9b34e6cc ZZ |
1134 | |
1135 | /* | |
1136 | * if vddd linear reg has been enabled, | |
1137 | * simple digital supply should be clear to get | |
1138 | * proper VDDD voltage. | |
1139 | */ | |
1140 | if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) | |
1141 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
1142 | SGTL5000_LINREG_SIMPLE_POWERUP, | |
1143 | 0); | |
1144 | else | |
1145 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
1146 | SGTL5000_LINREG_SIMPLE_POWERUP | | |
1147 | SGTL5000_STARTUP_POWERUP, | |
1148 | 0); | |
1149 | ||
1150 | /* | |
1151 | * set ADC/DAC VAG to vdda / 2, | |
1152 | * should stay in range (0.8v, 1.575v) | |
1153 | */ | |
1154 | vag = vdda / 2; | |
1155 | if (vag <= SGTL5000_ANA_GND_BASE) | |
1156 | vag = 0; | |
1157 | else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * | |
1158 | (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) | |
1159 | vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; | |
1160 | else | |
1161 | vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; | |
1162 | ||
1163 | snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, | |
33cb92cf | 1164 | SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); |
9b34e6cc ZZ |
1165 | |
1166 | /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ | |
1167 | vag = vddio / 2; | |
1168 | if (vag <= SGTL5000_LINE_OUT_GND_BASE) | |
1169 | vag = 0; | |
1170 | else if (vag >= SGTL5000_LINE_OUT_GND_BASE + | |
1171 | SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) | |
1172 | vag = SGTL5000_LINE_OUT_GND_MAX; | |
1173 | else | |
1174 | vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / | |
1175 | SGTL5000_LINE_OUT_GND_STP; | |
1176 | ||
1177 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, | |
33cb92cf AL |
1178 | SGTL5000_LINE_OUT_CURRENT_MASK | |
1179 | SGTL5000_LINE_OUT_GND_MASK, | |
9b34e6cc ZZ |
1180 | vag << SGTL5000_LINE_OUT_GND_SHIFT | |
1181 | SGTL5000_LINE_OUT_CURRENT_360u << | |
1182 | SGTL5000_LINE_OUT_CURRENT_SHIFT); | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
e94a4062 WS |
1187 | static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) |
1188 | { | |
1189 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1190 | int ret; | |
1191 | ||
1192 | /* set internal ldo to 1.2v */ | |
1193 | ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE); | |
1194 | if (ret) { | |
1195 | dev_err(codec->dev, | |
1196 | "Failed to register vddd internal supplies: %d\n", ret); | |
1197 | return ret; | |
1198 | } | |
1199 | ||
1200 | sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; | |
1201 | ||
1202 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), | |
1203 | sgtl5000->supplies); | |
1204 | ||
1205 | if (ret) { | |
1206 | ldo_regulator_remove(codec); | |
1207 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
1208 | return ret; | |
1209 | } | |
1210 | ||
1211 | dev_info(codec->dev, "Using internal LDO instead of VDDD\n"); | |
1212 | return 0; | |
1213 | } | |
1214 | ||
9b34e6cc ZZ |
1215 | static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) |
1216 | { | |
1217 | u16 reg; | |
1218 | int ret; | |
1219 | int rev; | |
1220 | int i; | |
1221 | int external_vddd = 0; | |
1222 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1223 | ||
1224 | for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) | |
1225 | sgtl5000->supplies[i].supply = supply_names[i]; | |
1226 | ||
1227 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), | |
1228 | sgtl5000->supplies); | |
1229 | if (!ret) | |
1230 | external_vddd = 1; | |
1231 | else { | |
e94a4062 WS |
1232 | ret = sgtl5000_replace_vddd_with_ldo(codec); |
1233 | if (ret) | |
9b34e6cc | 1234 | return ret; |
9b34e6cc ZZ |
1235 | } |
1236 | ||
1237 | ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), | |
1238 | sgtl5000->supplies); | |
1239 | if (ret) | |
1240 | goto err_regulator_free; | |
1241 | ||
1242 | /* wait for all power rails bring up */ | |
1243 | udelay(10); | |
1244 | ||
1245 | /* read chip information */ | |
1246 | reg = snd_soc_read(codec, SGTL5000_CHIP_ID); | |
1247 | if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != | |
1248 | SGTL5000_PARTID_PART_ID) { | |
1249 | dev_err(codec->dev, | |
1250 | "Device with ID register %x is not a sgtl5000\n", reg); | |
1251 | ret = -ENODEV; | |
1252 | goto err_regulator_disable; | |
1253 | } | |
1254 | ||
1255 | rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; | |
f2c6e757 | 1256 | dev_info(codec->dev, "sgtl5000 revision 0x%x\n", rev); |
9b34e6cc ZZ |
1257 | |
1258 | /* | |
1259 | * workaround for revision 0x11 and later, | |
1260 | * roll back to use internal LDO | |
1261 | */ | |
1262 | if (external_vddd && rev >= 0x11) { | |
9b34e6cc ZZ |
1263 | /* disable all regulator first */ |
1264 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1265 | sgtl5000->supplies); | |
1266 | /* free VDDD regulator */ | |
1267 | regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), | |
1268 | sgtl5000->supplies); | |
1269 | ||
e94a4062 | 1270 | ret = sgtl5000_replace_vddd_with_ldo(codec); |
9b34e6cc ZZ |
1271 | if (ret) |
1272 | return ret; | |
1273 | ||
9b34e6cc ZZ |
1274 | ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), |
1275 | sgtl5000->supplies); | |
1276 | if (ret) | |
1277 | goto err_regulator_free; | |
1278 | ||
1279 | /* wait for all power rails bring up */ | |
1280 | udelay(10); | |
1281 | } | |
1282 | ||
1283 | return 0; | |
1284 | ||
1285 | err_regulator_disable: | |
1286 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1287 | sgtl5000->supplies); | |
1288 | err_regulator_free: | |
1289 | regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), | |
1290 | sgtl5000->supplies); | |
1291 | if (external_vddd) | |
1292 | ldo_regulator_remove(codec); | |
1293 | return ret; | |
1294 | ||
1295 | } | |
1296 | ||
1297 | static int sgtl5000_probe(struct snd_soc_codec *codec) | |
1298 | { | |
1299 | int ret; | |
1300 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1301 | ||
1302 | /* setup i2c data ops */ | |
1303 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); | |
1304 | if (ret < 0) { | |
1305 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
1306 | return ret; | |
1307 | } | |
1308 | ||
1309 | ret = sgtl5000_enable_regulators(codec); | |
1310 | if (ret) | |
1311 | return ret; | |
1312 | ||
1313 | /* power up sgtl5000 */ | |
1314 | ret = sgtl5000_set_power_regs(codec); | |
1315 | if (ret) | |
1316 | goto err; | |
1317 | ||
1318 | /* enable small pop, introduce 400ms delay in turning off */ | |
1319 | snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, | |
1320 | SGTL5000_SMALL_POP, | |
1321 | SGTL5000_SMALL_POP); | |
1322 | ||
1323 | /* disable short cut detector */ | |
1324 | snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); | |
1325 | ||
1326 | /* | |
1327 | * set i2s as default input of sound switch | |
1328 | * TODO: add sound switch to control and dapm widge. | |
1329 | */ | |
1330 | snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, | |
1331 | SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); | |
1332 | snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, | |
1333 | SGTL5000_ADC_EN | SGTL5000_DAC_EN); | |
1334 | ||
1335 | /* enable dac volume ramp by default */ | |
1336 | snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, | |
1337 | SGTL5000_DAC_VOL_RAMP_EN | | |
1338 | SGTL5000_DAC_MUTE_RIGHT | | |
1339 | SGTL5000_DAC_MUTE_LEFT); | |
1340 | ||
1341 | snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); | |
1342 | ||
1343 | snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, | |
1344 | SGTL5000_HP_ZCD_EN | | |
1345 | SGTL5000_ADC_ZCD_EN); | |
1346 | ||
b50684da | 1347 | snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2); |
9b34e6cc ZZ |
1348 | |
1349 | /* | |
1350 | * disable DAP | |
1351 | * TODO: | |
1352 | * Enable DAP in kcontrol and dapm. | |
1353 | */ | |
1354 | snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); | |
1355 | ||
1356 | /* leading to standby state */ | |
1357 | ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1358 | if (ret) | |
1359 | goto err; | |
1360 | ||
9b34e6cc ZZ |
1361 | return 0; |
1362 | ||
1363 | err: | |
1364 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1365 | sgtl5000->supplies); | |
1366 | regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), | |
1367 | sgtl5000->supplies); | |
1368 | ldo_regulator_remove(codec); | |
1369 | ||
1370 | return ret; | |
1371 | } | |
1372 | ||
1373 | static int sgtl5000_remove(struct snd_soc_codec *codec) | |
1374 | { | |
1375 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1376 | ||
1377 | sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1378 | ||
1379 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1380 | sgtl5000->supplies); | |
1381 | regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), | |
1382 | sgtl5000->supplies); | |
1383 | ldo_regulator_remove(codec); | |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
61a142b7 | 1388 | static struct snd_soc_codec_driver sgtl5000_driver = { |
9b34e6cc ZZ |
1389 | .probe = sgtl5000_probe, |
1390 | .remove = sgtl5000_remove, | |
1391 | .suspend = sgtl5000_suspend, | |
1392 | .resume = sgtl5000_resume, | |
1393 | .set_bias_level = sgtl5000_set_bias_level, | |
1394 | .reg_cache_size = ARRAY_SIZE(sgtl5000_regs), | |
1395 | .reg_word_size = sizeof(u16), | |
1396 | .reg_cache_step = 2, | |
1397 | .reg_cache_default = sgtl5000_regs, | |
1398 | .volatile_register = sgtl5000_volatile_register, | |
89989637 FE |
1399 | .controls = sgtl5000_snd_controls, |
1400 | .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), | |
5e0ac527 MB |
1401 | .dapm_widgets = sgtl5000_dapm_widgets, |
1402 | .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), | |
1403 | .dapm_routes = sgtl5000_dapm_routes, | |
1404 | .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), | |
9b34e6cc ZZ |
1405 | }; |
1406 | ||
7a79e94e BP |
1407 | static int sgtl5000_i2c_probe(struct i2c_client *client, |
1408 | const struct i2c_device_id *id) | |
9b34e6cc ZZ |
1409 | { |
1410 | struct sgtl5000_priv *sgtl5000; | |
1411 | int ret; | |
1412 | ||
512fa7c4 FE |
1413 | sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv), |
1414 | GFP_KERNEL); | |
9b34e6cc ZZ |
1415 | if (!sgtl5000) |
1416 | return -ENOMEM; | |
1417 | ||
9b34e6cc ZZ |
1418 | i2c_set_clientdata(client, sgtl5000); |
1419 | ||
1420 | ret = snd_soc_register_codec(&client->dev, | |
1421 | &sgtl5000_driver, &sgtl5000_dai, 1); | |
512fa7c4 | 1422 | return ret; |
9b34e6cc ZZ |
1423 | } |
1424 | ||
7a79e94e | 1425 | static int sgtl5000_i2c_remove(struct i2c_client *client) |
9b34e6cc | 1426 | { |
9b34e6cc ZZ |
1427 | snd_soc_unregister_codec(&client->dev); |
1428 | ||
9b34e6cc ZZ |
1429 | return 0; |
1430 | } | |
1431 | ||
1432 | static const struct i2c_device_id sgtl5000_id[] = { | |
1433 | {"sgtl5000", 0}, | |
1434 | {}, | |
1435 | }; | |
1436 | ||
1437 | MODULE_DEVICE_TABLE(i2c, sgtl5000_id); | |
1438 | ||
58e49424 SG |
1439 | static const struct of_device_id sgtl5000_dt_ids[] = { |
1440 | { .compatible = "fsl,sgtl5000", }, | |
1441 | { /* sentinel */ } | |
1442 | }; | |
4c54c6de | 1443 | MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); |
58e49424 | 1444 | |
9b34e6cc ZZ |
1445 | static struct i2c_driver sgtl5000_i2c_driver = { |
1446 | .driver = { | |
1447 | .name = "sgtl5000", | |
1448 | .owner = THIS_MODULE, | |
58e49424 | 1449 | .of_match_table = sgtl5000_dt_ids, |
9b34e6cc ZZ |
1450 | }, |
1451 | .probe = sgtl5000_i2c_probe, | |
7a79e94e | 1452 | .remove = sgtl5000_i2c_remove, |
9b34e6cc ZZ |
1453 | .id_table = sgtl5000_id, |
1454 | }; | |
1455 | ||
67d45090 | 1456 | module_i2c_driver(sgtl5000_i2c_driver); |
9b34e6cc ZZ |
1457 | |
1458 | MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); | |
f7cb8a4b | 1459 | MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); |
9b34e6cc | 1460 | MODULE_LICENSE("GPL"); |