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9b34e6cc ZZ |
1 | /* |
2 | * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/regulator/driver.h> | |
21 | #include <linux/regulator/machine.h> | |
22 | #include <linux/regulator/consumer.h> | |
23 | #include <sound/core.h> | |
24 | #include <sound/tlv.h> | |
25 | #include <sound/pcm.h> | |
26 | #include <sound/pcm_params.h> | |
27 | #include <sound/soc.h> | |
28 | #include <sound/soc-dapm.h> | |
29 | #include <sound/initval.h> | |
30 | #include <mach/hardware.h> | |
31 | ||
32 | #include "sgtl5000.h" | |
33 | ||
34 | #define SGTL5000_DAP_REG_OFFSET 0x0100 | |
35 | #define SGTL5000_MAX_REG_OFFSET 0x013A | |
36 | ||
37 | /* default value of sgtl5000 registers except DAP */ | |
38 | static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET >> 1] = { | |
39 | 0xa011, /* 0x0000, CHIP_ID. 11 stand for revison 17 */ | |
40 | 0x0000, /* 0x0002, CHIP_DIG_POWER. */ | |
41 | 0x0008, /* 0x0004, CHIP_CKL_CTRL */ | |
42 | 0x0010, /* 0x0006, CHIP_I2S_CTRL */ | |
43 | 0x0000, /* 0x0008, reserved */ | |
44 | 0x0008, /* 0x000A, CHIP_SSS_CTRL */ | |
45 | 0x0000, /* 0x000C, reserved */ | |
46 | 0x020c, /* 0x000E, CHIP_ADCDAC_CTRL */ | |
47 | 0x3c3c, /* 0x0010, CHIP_DAC_VOL */ | |
48 | 0x0000, /* 0x0012, reserved */ | |
49 | 0x015f, /* 0x0014, CHIP_PAD_STRENGTH */ | |
50 | 0x0000, /* 0x0016, reserved */ | |
51 | 0x0000, /* 0x0018, reserved */ | |
52 | 0x0000, /* 0x001A, reserved */ | |
53 | 0x0000, /* 0x001E, reserved */ | |
54 | 0x0000, /* 0x0020, CHIP_ANA_ADC_CTRL */ | |
55 | 0x1818, /* 0x0022, CHIP_ANA_HP_CTRL */ | |
56 | 0x0111, /* 0x0024, CHIP_ANN_CTRL */ | |
57 | 0x0000, /* 0x0026, CHIP_LINREG_CTRL */ | |
58 | 0x0000, /* 0x0028, CHIP_REF_CTRL */ | |
59 | 0x0000, /* 0x002A, CHIP_MIC_CTRL */ | |
60 | 0x0000, /* 0x002C, CHIP_LINE_OUT_CTRL */ | |
61 | 0x0404, /* 0x002E, CHIP_LINE_OUT_VOL */ | |
62 | 0x7060, /* 0x0030, CHIP_ANA_POWER */ | |
63 | 0x5000, /* 0x0032, CHIP_PLL_CTRL */ | |
64 | 0x0000, /* 0x0034, CHIP_CLK_TOP_CTRL */ | |
65 | 0x0000, /* 0x0036, CHIP_ANA_STATUS */ | |
66 | 0x0000, /* 0x0038, reserved */ | |
67 | 0x0000, /* 0x003A, CHIP_ANA_TEST2 */ | |
68 | 0x0000, /* 0x003C, CHIP_SHORT_CTRL */ | |
69 | 0x0000, /* reserved */ | |
70 | }; | |
71 | ||
72 | /* default value of dap registers */ | |
73 | static const u16 sgtl5000_dap_regs[] = { | |
74 | 0x0000, /* 0x0100, DAP_CONTROL */ | |
75 | 0x0000, /* 0x0102, DAP_PEQ */ | |
76 | 0x0040, /* 0x0104, DAP_BASS_ENHANCE */ | |
77 | 0x051f, /* 0x0106, DAP_BASS_ENHANCE_CTRL */ | |
78 | 0x0000, /* 0x0108, DAP_AUDIO_EQ */ | |
79 | 0x0040, /* 0x010A, DAP_SGTL_SURROUND */ | |
80 | 0x0000, /* 0x010C, DAP_FILTER_COEF_ACCESS */ | |
81 | 0x0000, /* 0x010E, DAP_COEF_WR_B0_MSB */ | |
82 | 0x0000, /* 0x0110, DAP_COEF_WR_B0_LSB */ | |
83 | 0x0000, /* 0x0112, reserved */ | |
84 | 0x0000, /* 0x0114, reserved */ | |
85 | 0x002f, /* 0x0116, DAP_AUDIO_EQ_BASS_BAND0 */ | |
86 | 0x002f, /* 0x0118, DAP_AUDIO_EQ_BAND0 */ | |
87 | 0x002f, /* 0x011A, DAP_AUDIO_EQ_BAND2 */ | |
88 | 0x002f, /* 0x011C, DAP_AUDIO_EQ_BAND3 */ | |
89 | 0x002f, /* 0x011E, DAP_AUDIO_EQ_TREBLE_BAND4 */ | |
90 | 0x8000, /* 0x0120, DAP_MAIN_CHAN */ | |
91 | 0x0000, /* 0x0122, DAP_MIX_CHAN */ | |
92 | 0x0510, /* 0x0124, DAP_AVC_CTRL */ | |
93 | 0x1473, /* 0x0126, DAP_AVC_THRESHOLD */ | |
94 | 0x0028, /* 0x0128, DAP_AVC_ATTACK */ | |
95 | 0x0050, /* 0x012A, DAP_AVC_DECAY */ | |
96 | 0x0000, /* 0x012C, DAP_COEF_WR_B1_MSB */ | |
97 | 0x0000, /* 0x012E, DAP_COEF_WR_B1_LSB */ | |
98 | 0x0000, /* 0x0130, DAP_COEF_WR_B2_MSB */ | |
99 | 0x0000, /* 0x0132, DAP_COEF_WR_B2_LSB */ | |
100 | 0x0000, /* 0x0134, DAP_COEF_WR_A1_MSB */ | |
101 | 0x0000, /* 0x0136, DAP_COEF_WR_A1_LSB */ | |
102 | 0x0000, /* 0x0138, DAP_COEF_WR_A2_MSB */ | |
103 | 0x0000, /* 0x013A, DAP_COEF_WR_A2_LSB */ | |
104 | }; | |
105 | ||
106 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ | |
107 | enum sgtl5000_regulator_supplies { | |
108 | VDDA, | |
109 | VDDIO, | |
110 | VDDD, | |
111 | SGTL5000_SUPPLY_NUM | |
112 | }; | |
113 | ||
114 | /* vddd is optional supply */ | |
115 | static const char *supply_names[SGTL5000_SUPPLY_NUM] = { | |
116 | "VDDA", | |
117 | "VDDIO", | |
118 | "VDDD" | |
119 | }; | |
120 | ||
121 | #define LDO_CONSUMER_NAME "VDDD_LDO" | |
122 | #define LDO_VOLTAGE 1200000 | |
123 | ||
124 | static struct regulator_consumer_supply ldo_consumer[] = { | |
125 | REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), | |
126 | }; | |
127 | ||
128 | struct regulator_init_data ldo_init_data = { | |
129 | .constraints = { | |
130 | .min_uV = 850000, | |
131 | .max_uV = 1600000, | |
132 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | |
133 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
134 | }, | |
135 | .num_consumer_supplies = 1, | |
136 | .consumer_supplies = &ldo_consumer[0], | |
137 | }; | |
138 | ||
139 | /* | |
140 | * sgtl5000 internal ldo regulator, | |
141 | * enabled when VDDD not provided | |
142 | */ | |
143 | struct ldo_regulator { | |
144 | struct regulator_desc desc; | |
145 | struct regulator_dev *dev; | |
146 | int voltage; | |
147 | void *codec_data; | |
148 | bool enabled; | |
149 | }; | |
150 | ||
151 | /* sgtl5000 private structure in codec */ | |
152 | struct sgtl5000_priv { | |
153 | int sysclk; /* sysclk rate */ | |
154 | int master; /* i2s master or not */ | |
155 | int fmt; /* i2s data format */ | |
156 | struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; | |
157 | struct ldo_regulator *ldo; | |
158 | }; | |
159 | ||
160 | /* | |
161 | * mic_bias power on/off share the same register bits with | |
162 | * output impedance of mic bias, when power on mic bias, we | |
163 | * need reclaim it to impedance value. | |
164 | * 0x0 = Powered off | |
165 | * 0x1 = 2Kohm | |
166 | * 0x2 = 4Kohm | |
167 | * 0x3 = 8Kohm | |
168 | */ | |
169 | static int mic_bias_event(struct snd_soc_dapm_widget *w, | |
170 | struct snd_kcontrol *kcontrol, int event) | |
171 | { | |
172 | switch (event) { | |
173 | case SND_SOC_DAPM_POST_PMU: | |
174 | /* change mic bias resistor to 4Kohm */ | |
175 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, | |
176 | SGTL5000_BIAS_R_4k, SGTL5000_BIAS_R_4k); | |
177 | break; | |
178 | ||
179 | case SND_SOC_DAPM_PRE_PMD: | |
180 | /* | |
181 | * SGTL5000_BIAS_R_8k as mask to clean the two bits | |
182 | * of mic bias and output impedance | |
183 | */ | |
184 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, | |
185 | SGTL5000_BIAS_R_8k, 0); | |
186 | break; | |
187 | } | |
188 | return 0; | |
189 | } | |
190 | ||
191 | /* | |
192 | * using codec assist to small pop, hp_powerup or lineout_powerup | |
193 | * should stay setting until vag_powerup is fully ramped down, | |
194 | * vag fully ramped down require 400ms. | |
195 | */ | |
196 | static int small_pop_event(struct snd_soc_dapm_widget *w, | |
197 | struct snd_kcontrol *kcontrol, int event) | |
198 | { | |
199 | switch (event) { | |
200 | case SND_SOC_DAPM_PRE_PMU: | |
201 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, | |
202 | SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); | |
203 | break; | |
204 | ||
205 | case SND_SOC_DAPM_PRE_PMD: | |
206 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, | |
207 | SGTL5000_VAG_POWERUP, 0); | |
208 | msleep(400); | |
209 | break; | |
210 | default: | |
211 | break; | |
212 | } | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | /* input sources for ADC */ | |
218 | static const char *adc_mux_text[] = { | |
219 | "MIC_IN", "LINE_IN" | |
220 | }; | |
221 | ||
222 | static const struct soc_enum adc_enum = | |
223 | SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text); | |
224 | ||
225 | static const struct snd_kcontrol_new adc_mux = | |
226 | SOC_DAPM_ENUM("Capture Mux", adc_enum); | |
227 | ||
228 | /* input sources for DAC */ | |
229 | static const char *dac_mux_text[] = { | |
230 | "DAC", "LINE_IN" | |
231 | }; | |
232 | ||
233 | static const struct soc_enum dac_enum = | |
234 | SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text); | |
235 | ||
236 | static const struct snd_kcontrol_new dac_mux = | |
237 | SOC_DAPM_ENUM("Headphone Mux", dac_enum); | |
238 | ||
239 | static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { | |
240 | SND_SOC_DAPM_INPUT("LINE_IN"), | |
241 | SND_SOC_DAPM_INPUT("MIC_IN"), | |
242 | ||
243 | SND_SOC_DAPM_OUTPUT("HP_OUT"), | |
244 | SND_SOC_DAPM_OUTPUT("LINE_OUT"), | |
245 | ||
246 | SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, | |
247 | mic_bias_event, | |
248 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
249 | ||
250 | SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0, | |
251 | small_pop_event, | |
252 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
253 | SND_SOC_DAPM_PGA_E("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0, | |
254 | small_pop_event, | |
255 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
256 | ||
257 | SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), | |
258 | SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), | |
259 | ||
260 | /* aif for i2s input */ | |
261 | SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", | |
262 | 0, SGTL5000_CHIP_DIG_POWER, | |
263 | 0, 0), | |
264 | ||
265 | /* aif for i2s output */ | |
266 | SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", | |
267 | 0, SGTL5000_CHIP_DIG_POWER, | |
268 | 1, 0), | |
269 | ||
270 | SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), | |
271 | ||
272 | SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), | |
273 | }; | |
274 | ||
275 | /* routes for sgtl5000 */ | |
276 | static const struct snd_soc_dapm_route audio_map[] = { | |
277 | {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ | |
278 | {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ | |
279 | ||
280 | {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ | |
281 | {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ | |
282 | ||
283 | {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ | |
284 | {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ | |
285 | {"LO", NULL, "DAC"}, /* dac --> line_out */ | |
286 | ||
287 | {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ | |
288 | {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ | |
289 | ||
290 | {"LINE_OUT", NULL, "LO"}, | |
291 | {"HP_OUT", NULL, "HP"}, | |
292 | }; | |
293 | ||
294 | /* custom function to fetch info of PCM playback volume */ | |
295 | static int dac_info_volsw(struct snd_kcontrol *kcontrol, | |
296 | struct snd_ctl_elem_info *uinfo) | |
297 | { | |
298 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
299 | uinfo->count = 2; | |
300 | uinfo->value.integer.min = 0; | |
301 | uinfo->value.integer.max = 0xfc - 0x3c; | |
302 | return 0; | |
303 | } | |
304 | ||
305 | /* | |
306 | * custom function to get of PCM playback volume | |
307 | * | |
308 | * dac volume register | |
309 | * 15-------------8-7--------------0 | |
310 | * | R channel vol | L channel vol | | |
311 | * ------------------------------- | |
312 | * | |
313 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
314 | * | |
315 | * register values map to dB | |
316 | * 0x3B and less = Reserved | |
317 | * 0x3C = 0 dB | |
318 | * 0x3D = -0.5 dB | |
319 | * 0xF0 = -90 dB | |
320 | * 0xFC and greater = Muted | |
321 | * | |
322 | * register value map to userspace value | |
323 | * | |
324 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
325 | * ------------------------------ | |
326 | * userspace value 0xc0 0 | |
327 | */ | |
328 | static int dac_get_volsw(struct snd_kcontrol *kcontrol, | |
329 | struct snd_ctl_elem_value *ucontrol) | |
330 | { | |
331 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
332 | int reg; | |
333 | int l; | |
334 | int r; | |
335 | ||
336 | reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); | |
337 | ||
338 | /* get left channel volume */ | |
339 | l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; | |
340 | ||
341 | /* get right channel volume */ | |
342 | r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
343 | ||
344 | /* make sure value fall in (0x3c,0xfc) */ | |
345 | l = clamp(l, 0x3c, 0xfc); | |
346 | r = clamp(r, 0x3c, 0xfc); | |
347 | ||
348 | /* invert it and map to userspace value */ | |
349 | l = 0xfc - l; | |
350 | r = 0xfc - r; | |
351 | ||
352 | ucontrol->value.integer.value[0] = l; | |
353 | ucontrol->value.integer.value[1] = r; | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | /* | |
359 | * custom function to put of PCM playback volume | |
360 | * | |
361 | * dac volume register | |
362 | * 15-------------8-7--------------0 | |
363 | * | R channel vol | L channel vol | | |
364 | * ------------------------------- | |
365 | * | |
366 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
367 | * | |
368 | * register values map to dB | |
369 | * 0x3B and less = Reserved | |
370 | * 0x3C = 0 dB | |
371 | * 0x3D = -0.5 dB | |
372 | * 0xF0 = -90 dB | |
373 | * 0xFC and greater = Muted | |
374 | * | |
375 | * userspace value map to register value | |
376 | * | |
377 | * userspace value 0xc0 0 | |
378 | * ------------------------------ | |
379 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
380 | */ | |
381 | static int dac_put_volsw(struct snd_kcontrol *kcontrol, | |
382 | struct snd_ctl_elem_value *ucontrol) | |
383 | { | |
384 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
385 | int reg; | |
386 | int l; | |
387 | int r; | |
388 | ||
389 | l = ucontrol->value.integer.value[0]; | |
390 | r = ucontrol->value.integer.value[1]; | |
391 | ||
392 | /* make sure userspace volume fall in (0, 0xfc-0x3c) */ | |
393 | l = clamp(l, 0, 0xfc - 0x3c); | |
394 | r = clamp(r, 0, 0xfc - 0x3c); | |
395 | ||
396 | /* invert it, get the value can be set to register */ | |
397 | l = 0xfc - l; | |
398 | r = 0xfc - r; | |
399 | ||
400 | /* shift to get the register value */ | |
401 | reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | | |
402 | r << SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
403 | ||
404 | snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); | |
410 | ||
411 | /* tlv for mic gain, 0db 20db 30db 40db */ | |
412 | static const unsigned int mic_gain_tlv[] = { | |
413 | TLV_DB_RANGE_HEAD(4), | |
414 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), | |
415 | 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), | |
416 | }; | |
417 | ||
418 | /* tlv for hp volume, -51.5db to 12.0db, step .5db */ | |
419 | static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); | |
420 | ||
421 | static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { | |
422 | /* SOC_DOUBLE_S8_TLV with invert */ | |
423 | { | |
424 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
425 | .name = "PCM Playback Volume", | |
426 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | | |
427 | SNDRV_CTL_ELEM_ACCESS_READWRITE, | |
428 | .info = dac_info_volsw, | |
429 | .get = dac_get_volsw, | |
430 | .put = dac_put_volsw, | |
431 | }, | |
432 | ||
433 | SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), | |
434 | SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", | |
435 | SGTL5000_CHIP_ANA_ADC_CTRL, | |
436 | 8, 2, 0, capture_6db_attenuate), | |
437 | SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), | |
438 | ||
439 | SOC_DOUBLE_TLV("Headphone Playback Volume", | |
440 | SGTL5000_CHIP_ANA_HP_CTRL, | |
441 | 0, 8, | |
442 | 0x7f, 1, | |
443 | headphone_volume), | |
444 | SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, | |
445 | 5, 1, 0), | |
446 | ||
447 | SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, | |
448 | 0, 4, 0, mic_gain_tlv), | |
449 | }; | |
450 | ||
451 | /* mute the codec used by alsa core */ | |
452 | static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
453 | { | |
454 | struct snd_soc_codec *codec = codec_dai->codec; | |
455 | u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; | |
456 | ||
457 | snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, | |
458 | adcdac_ctrl, mute ? adcdac_ctrl : 0); | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | /* set codec format */ | |
464 | static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
465 | { | |
466 | struct snd_soc_codec *codec = codec_dai->codec; | |
467 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
468 | u16 i2sctl = 0; | |
469 | ||
470 | sgtl5000->master = 0; | |
471 | /* | |
472 | * i2s clock and frame master setting. | |
473 | * ONLY support: | |
474 | * - clock and frame slave, | |
475 | * - clock and frame master | |
476 | */ | |
477 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
478 | case SND_SOC_DAIFMT_CBS_CFS: | |
479 | break; | |
480 | case SND_SOC_DAIFMT_CBM_CFM: | |
481 | i2sctl |= SGTL5000_I2S_MASTER; | |
482 | sgtl5000->master = 1; | |
483 | break; | |
484 | default: | |
485 | return -EINVAL; | |
486 | } | |
487 | ||
488 | /* setting i2s data format */ | |
489 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
490 | case SND_SOC_DAIFMT_DSP_A: | |
491 | i2sctl |= SGTL5000_I2S_MODE_PCM; | |
492 | break; | |
493 | case SND_SOC_DAIFMT_DSP_B: | |
494 | i2sctl |= SGTL5000_I2S_MODE_PCM; | |
495 | i2sctl |= SGTL5000_I2S_LRALIGN; | |
496 | break; | |
497 | case SND_SOC_DAIFMT_I2S: | |
498 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; | |
499 | break; | |
500 | case SND_SOC_DAIFMT_RIGHT_J: | |
501 | i2sctl |= SGTL5000_I2S_MODE_RJ; | |
502 | i2sctl |= SGTL5000_I2S_LRPOL; | |
503 | break; | |
504 | case SND_SOC_DAIFMT_LEFT_J: | |
505 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; | |
506 | i2sctl |= SGTL5000_I2S_LRALIGN; | |
507 | break; | |
508 | default: | |
509 | return -EINVAL; | |
510 | } | |
511 | ||
512 | sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
513 | ||
514 | /* Clock inversion */ | |
515 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
516 | case SND_SOC_DAIFMT_NB_NF: | |
517 | break; | |
518 | case SND_SOC_DAIFMT_IB_NF: | |
519 | i2sctl |= SGTL5000_I2S_SCLK_INV; | |
520 | break; | |
521 | default: | |
522 | return -EINVAL; | |
523 | } | |
524 | ||
525 | snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
530 | /* set codec sysclk */ | |
531 | static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
532 | int clk_id, unsigned int freq, int dir) | |
533 | { | |
534 | struct snd_soc_codec *codec = codec_dai->codec; | |
535 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
536 | ||
537 | switch (clk_id) { | |
538 | case SGTL5000_SYSCLK: | |
539 | sgtl5000->sysclk = freq; | |
540 | break; | |
541 | default: | |
542 | return -EINVAL; | |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | /* | |
549 | * set clock according to i2s frame clock, | |
550 | * sgtl5000 provide 2 clock sources. | |
551 | * 1. sys_mclk. sample freq can only configure to | |
552 | * 1/256, 1/384, 1/512 of sys_mclk. | |
553 | * 2. pll. can derive any audio clocks. | |
554 | * | |
555 | * clock setting rules: | |
556 | * 1. in slave mode, only sys_mclk can use. | |
557 | * 2. as constraint by sys_mclk, sample freq should | |
558 | * set to 32k, 44.1k and above. | |
559 | * 3. using sys_mclk prefer to pll to save power. | |
560 | */ | |
561 | static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) | |
562 | { | |
563 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
564 | int clk_ctl = 0; | |
565 | int sys_fs; /* sample freq */ | |
566 | ||
567 | /* | |
568 | * sample freq should be divided by frame clock, | |
569 | * if frame clock lower than 44.1khz, sample feq should set to | |
570 | * 32khz or 44.1khz. | |
571 | */ | |
572 | switch (frame_rate) { | |
573 | case 8000: | |
574 | case 16000: | |
575 | sys_fs = 32000; | |
576 | break; | |
577 | case 11025: | |
578 | case 22050: | |
579 | sys_fs = 44100; | |
580 | break; | |
581 | default: | |
582 | sys_fs = frame_rate; | |
583 | break; | |
584 | } | |
585 | ||
586 | /* set divided factor of frame clock */ | |
587 | switch (sys_fs / frame_rate) { | |
588 | case 4: | |
589 | clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; | |
590 | break; | |
591 | case 2: | |
592 | clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; | |
593 | break; | |
594 | case 1: | |
595 | clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; | |
596 | break; | |
597 | default: | |
598 | return -EINVAL; | |
599 | } | |
600 | ||
601 | /* set the sys_fs according to frame rate */ | |
602 | switch (sys_fs) { | |
603 | case 32000: | |
604 | clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; | |
605 | break; | |
606 | case 44100: | |
607 | clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; | |
608 | break; | |
609 | case 48000: | |
610 | clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; | |
611 | break; | |
612 | case 96000: | |
613 | clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; | |
614 | break; | |
615 | default: | |
616 | dev_err(codec->dev, "frame rate %d not supported\n", | |
617 | frame_rate); | |
618 | return -EINVAL; | |
619 | } | |
620 | ||
621 | /* | |
622 | * calculate the divider of mclk/sample_freq, | |
623 | * factor of freq =96k can only be 256, since mclk in range (12m,27m) | |
624 | */ | |
625 | switch (sgtl5000->sysclk / sys_fs) { | |
626 | case 256: | |
627 | clk_ctl |= SGTL5000_MCLK_FREQ_256FS << | |
628 | SGTL5000_MCLK_FREQ_SHIFT; | |
629 | break; | |
630 | case 384: | |
631 | clk_ctl |= SGTL5000_MCLK_FREQ_384FS << | |
632 | SGTL5000_MCLK_FREQ_SHIFT; | |
633 | break; | |
634 | case 512: | |
635 | clk_ctl |= SGTL5000_MCLK_FREQ_512FS << | |
636 | SGTL5000_MCLK_FREQ_SHIFT; | |
637 | break; | |
638 | default: | |
639 | /* if mclk not satisify the divider, use pll */ | |
640 | if (sgtl5000->master) { | |
641 | clk_ctl |= SGTL5000_MCLK_FREQ_PLL << | |
642 | SGTL5000_MCLK_FREQ_SHIFT; | |
643 | } else { | |
644 | dev_err(codec->dev, | |
645 | "PLL not supported in slave mode\n"); | |
646 | return -EINVAL; | |
647 | } | |
648 | } | |
649 | ||
650 | /* if using pll, please check manual 6.4.2 for detail */ | |
651 | if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { | |
652 | u64 out, t; | |
653 | int div2; | |
654 | int pll_ctl; | |
655 | unsigned int in, int_div, frac_div; | |
656 | ||
657 | if (sgtl5000->sysclk > 17000000) { | |
658 | div2 = 1; | |
659 | in = sgtl5000->sysclk / 2; | |
660 | } else { | |
661 | div2 = 0; | |
662 | in = sgtl5000->sysclk; | |
663 | } | |
664 | if (sys_fs == 44100) | |
665 | out = 180633600; | |
666 | else | |
667 | out = 196608000; | |
668 | t = do_div(out, in); | |
669 | int_div = out; | |
670 | t *= 2048; | |
671 | do_div(t, in); | |
672 | frac_div = t; | |
673 | pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | | |
674 | frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; | |
675 | ||
676 | snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); | |
677 | if (div2) | |
678 | snd_soc_update_bits(codec, | |
679 | SGTL5000_CHIP_CLK_TOP_CTRL, | |
680 | SGTL5000_INPUT_FREQ_DIV2, | |
681 | SGTL5000_INPUT_FREQ_DIV2); | |
682 | else | |
683 | snd_soc_update_bits(codec, | |
684 | SGTL5000_CHIP_CLK_TOP_CTRL, | |
685 | SGTL5000_INPUT_FREQ_DIV2, | |
686 | 0); | |
687 | ||
688 | /* power up pll */ | |
689 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
690 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, | |
691 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); | |
692 | } else { | |
693 | /* power down pll */ | |
694 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
695 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, | |
696 | 0); | |
697 | } | |
698 | ||
699 | /* if using pll, clk_ctrl must be set after pll power up */ | |
700 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
705 | /* | |
706 | * Set PCM DAI bit size and sample rate. | |
707 | * input: params_rate, params_fmt | |
708 | */ | |
709 | static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, | |
710 | struct snd_pcm_hw_params *params, | |
711 | struct snd_soc_dai *dai) | |
712 | { | |
713 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
714 | struct snd_soc_codec *codec = rtd->codec; | |
715 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
716 | int channels = params_channels(params); | |
717 | int i2s_ctl = 0; | |
718 | int stereo; | |
719 | int ret; | |
720 | ||
721 | /* sysclk should already set */ | |
722 | if (!sgtl5000->sysclk) { | |
723 | dev_err(codec->dev, "%s: set sysclk first!\n", __func__); | |
724 | return -EFAULT; | |
725 | } | |
726 | ||
727 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
728 | stereo = SGTL5000_DAC_STEREO; | |
729 | else | |
730 | stereo = SGTL5000_ADC_STEREO; | |
731 | ||
732 | /* set mono to save power */ | |
733 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, | |
734 | channels == 1 ? 0 : stereo); | |
735 | ||
736 | /* set codec clock base on lrclk */ | |
737 | ret = sgtl5000_set_clock(codec, params_rate(params)); | |
738 | if (ret) | |
739 | return ret; | |
740 | ||
741 | /* set i2s data format */ | |
742 | switch (params_format(params)) { | |
743 | case SNDRV_PCM_FORMAT_S16_LE: | |
744 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) | |
745 | return -EINVAL; | |
746 | i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; | |
747 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << | |
748 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
749 | break; | |
750 | case SNDRV_PCM_FORMAT_S20_3LE: | |
751 | i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; | |
752 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
753 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
754 | break; | |
755 | case SNDRV_PCM_FORMAT_S24_LE: | |
756 | i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; | |
757 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
758 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
759 | break; | |
760 | case SNDRV_PCM_FORMAT_S32_LE: | |
761 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) | |
762 | return -EINVAL; | |
763 | i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; | |
764 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
765 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
766 | break; | |
767 | default: | |
768 | return -EINVAL; | |
769 | } | |
770 | ||
771 | snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, i2s_ctl, i2s_ctl); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static int ldo_regulator_is_enabled(struct regulator_dev *dev) | |
777 | { | |
778 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
779 | ||
780 | return ldo->enabled; | |
781 | } | |
782 | ||
783 | static int ldo_regulator_enable(struct regulator_dev *dev) | |
784 | { | |
785 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
786 | struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; | |
787 | int reg; | |
788 | ||
789 | if (ldo_regulator_is_enabled(dev)) | |
790 | return 0; | |
791 | ||
792 | /* set regulator value firstly */ | |
793 | reg = (1600 - ldo->voltage / 1000) / 50; | |
794 | reg = clamp(reg, 0x0, 0xf); | |
795 | ||
796 | /* amend the voltage value, unit: uV */ | |
797 | ldo->voltage = (1600 - reg * 50) * 1000; | |
798 | ||
799 | /* set voltage to register */ | |
800 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, | |
801 | (0x1 << 4) - 1, reg); | |
802 | ||
803 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
804 | SGTL5000_LINEREG_D_POWERUP, | |
805 | SGTL5000_LINEREG_D_POWERUP); | |
806 | ||
807 | /* when internal ldo enabled, simple digital power can be disabled */ | |
808 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
809 | SGTL5000_LINREG_SIMPLE_POWERUP, | |
810 | 0); | |
811 | ||
812 | ldo->enabled = 1; | |
813 | return 0; | |
814 | } | |
815 | ||
816 | static int ldo_regulator_disable(struct regulator_dev *dev) | |
817 | { | |
818 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
819 | struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; | |
820 | ||
821 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
822 | SGTL5000_LINEREG_D_POWERUP, | |
823 | 0); | |
824 | ||
825 | /* clear voltage info */ | |
826 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, | |
827 | (0x1 << 4) - 1, 0); | |
828 | ||
829 | ldo->enabled = 0; | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
834 | static int ldo_regulator_get_voltage(struct regulator_dev *dev) | |
835 | { | |
836 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
837 | ||
838 | return ldo->voltage; | |
839 | } | |
840 | ||
841 | static struct regulator_ops ldo_regulator_ops = { | |
842 | .is_enabled = ldo_regulator_is_enabled, | |
843 | .enable = ldo_regulator_enable, | |
844 | .disable = ldo_regulator_disable, | |
845 | .get_voltage = ldo_regulator_get_voltage, | |
846 | }; | |
847 | ||
848 | static int ldo_regulator_register(struct snd_soc_codec *codec, | |
849 | struct regulator_init_data *init_data, | |
850 | int voltage) | |
851 | { | |
852 | struct ldo_regulator *ldo; | |
853 | ||
854 | ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); | |
855 | ||
856 | if (!ldo) { | |
857 | dev_err(codec->dev, "failed to allocate ldo_regulator\n"); | |
858 | return -ENOMEM; | |
859 | } | |
860 | ||
861 | ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); | |
862 | if (!ldo->desc.name) { | |
863 | kfree(ldo); | |
864 | dev_err(codec->dev, "failed to allocate decs name memory\n"); | |
865 | return -ENOMEM; | |
866 | } | |
867 | ||
868 | ldo->desc.type = REGULATOR_VOLTAGE; | |
869 | ldo->desc.owner = THIS_MODULE; | |
870 | ldo->desc.ops = &ldo_regulator_ops; | |
871 | ldo->desc.n_voltages = 1; | |
872 | ||
873 | ldo->codec_data = codec; | |
874 | ldo->voltage = voltage; | |
875 | ||
876 | ldo->dev = regulator_register(&ldo->desc, codec->dev, | |
877 | init_data, ldo); | |
878 | if (IS_ERR(ldo->dev)) { | |
879 | dev_err(codec->dev, "failed to register regulator\n"); | |
880 | kfree(ldo->desc.name); | |
881 | kfree(ldo); | |
882 | ||
883 | return PTR_ERR(ldo->dev); | |
884 | } | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
889 | static int ldo_regulator_remove(struct snd_soc_codec *codec) | |
890 | { | |
891 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
892 | struct ldo_regulator *ldo = sgtl5000->ldo; | |
893 | ||
894 | if (!ldo) | |
895 | return 0; | |
896 | ||
897 | regulator_unregister(ldo->dev); | |
898 | kfree(ldo->desc.name); | |
899 | kfree(ldo); | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
904 | /* | |
905 | * set dac bias | |
906 | * common state changes: | |
907 | * startup: | |
908 | * off --> standby --> prepare --> on | |
909 | * standby --> prepare --> on | |
910 | * | |
911 | * stop: | |
912 | * on --> prepare --> standby | |
913 | */ | |
914 | static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, | |
915 | enum snd_soc_bias_level level) | |
916 | { | |
917 | int ret; | |
918 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
919 | ||
920 | switch (level) { | |
921 | case SND_SOC_BIAS_ON: | |
922 | case SND_SOC_BIAS_PREPARE: | |
923 | break; | |
924 | case SND_SOC_BIAS_STANDBY: | |
925 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
926 | ret = regulator_bulk_enable( | |
927 | ARRAY_SIZE(sgtl5000->supplies), | |
928 | sgtl5000->supplies); | |
929 | if (ret) | |
930 | return ret; | |
931 | udelay(10); | |
932 | } | |
933 | ||
934 | break; | |
935 | case SND_SOC_BIAS_OFF: | |
936 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
937 | sgtl5000->supplies); | |
938 | break; | |
939 | } | |
940 | ||
941 | codec->dapm.bias_level = level; | |
942 | return 0; | |
943 | } | |
944 | ||
945 | #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
946 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
947 | SNDRV_PCM_FMTBIT_S24_LE |\ | |
948 | SNDRV_PCM_FMTBIT_S32_LE) | |
949 | ||
950 | struct snd_soc_dai_ops sgtl5000_ops = { | |
951 | .hw_params = sgtl5000_pcm_hw_params, | |
952 | .digital_mute = sgtl5000_digital_mute, | |
953 | .set_fmt = sgtl5000_set_dai_fmt, | |
954 | .set_sysclk = sgtl5000_set_dai_sysclk, | |
955 | }; | |
956 | ||
957 | static struct snd_soc_dai_driver sgtl5000_dai = { | |
958 | .name = "sgtl5000", | |
959 | .playback = { | |
960 | .stream_name = "Playback", | |
961 | .channels_min = 1, | |
962 | .channels_max = 2, | |
963 | /* | |
964 | * only support 8~48K + 96K, | |
965 | * TODO modify hw_param to support more | |
966 | */ | |
967 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
968 | .formats = SGTL5000_FORMATS, | |
969 | }, | |
970 | .capture = { | |
971 | .stream_name = "Capture", | |
972 | .channels_min = 1, | |
973 | .channels_max = 2, | |
974 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
975 | .formats = SGTL5000_FORMATS, | |
976 | }, | |
977 | .ops = &sgtl5000_ops, | |
978 | .symmetric_rates = 1, | |
979 | }; | |
980 | ||
981 | static int sgtl5000_volatile_register(struct snd_soc_codec *codec, | |
982 | unsigned int reg) | |
983 | { | |
984 | switch (reg) { | |
985 | case SGTL5000_CHIP_ID: | |
986 | case SGTL5000_CHIP_ADCDAC_CTRL: | |
987 | case SGTL5000_CHIP_ANA_STATUS: | |
988 | return 1; | |
989 | } | |
990 | ||
991 | return 0; | |
992 | } | |
993 | ||
994 | #ifdef CONFIG_SUSPEND | |
995 | static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state) | |
996 | { | |
997 | sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | /* | |
1003 | * restore all sgtl5000 registers, | |
1004 | * since a big hole between dap and regular registers, | |
1005 | * we will restore them respectively. | |
1006 | */ | |
1007 | static int sgtl5000_restore_regs(struct snd_soc_codec *codec) | |
1008 | { | |
1009 | u16 *cache = codec->reg_cache; | |
1010 | int i; | |
1011 | int regular_regs = SGTL5000_CHIP_SHORT_CTRL >> 1; | |
1012 | ||
1013 | /* restore regular registers */ | |
1014 | for (i = 0; i < regular_regs; i++) { | |
1015 | int reg = i << 1; | |
1016 | ||
1017 | /* this regs depends on the others */ | |
1018 | if (reg == SGTL5000_CHIP_ANA_POWER || | |
1019 | reg == SGTL5000_CHIP_CLK_CTRL || | |
1020 | reg == SGTL5000_CHIP_LINREG_CTRL || | |
1021 | reg == SGTL5000_CHIP_LINE_OUT_CTRL || | |
1022 | reg == SGTL5000_CHIP_CLK_CTRL) | |
1023 | continue; | |
1024 | ||
1025 | snd_soc_write(codec, reg, cache[i]); | |
1026 | } | |
1027 | ||
1028 | /* restore dap registers */ | |
1029 | for (i = SGTL5000_DAP_REG_OFFSET >> 1; | |
1030 | i < SGTL5000_MAX_REG_OFFSET >> 1; i++) { | |
1031 | int reg = i << 1; | |
1032 | ||
1033 | snd_soc_write(codec, reg, cache[i]); | |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * restore power and other regs according | |
1038 | * to set_power() and set_clock() | |
1039 | */ | |
1040 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, | |
1041 | cache[SGTL5000_CHIP_LINREG_CTRL >> 1]); | |
1042 | ||
1043 | snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, | |
1044 | cache[SGTL5000_CHIP_ANA_POWER >> 1]); | |
1045 | ||
1046 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, | |
1047 | cache[SGTL5000_CHIP_CLK_CTRL >> 1]); | |
1048 | ||
1049 | snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, | |
1050 | cache[SGTL5000_CHIP_REF_CTRL >> 1]); | |
1051 | ||
1052 | snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, | |
1053 | cache[SGTL5000_CHIP_LINE_OUT_CTRL >> 1]); | |
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | static int sgtl5000_resume(struct snd_soc_codec *codec) | |
1058 | { | |
1059 | /* Bring the codec back up to standby to enable regulators */ | |
1060 | sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1061 | ||
1062 | /* Restore registers by cached in memory */ | |
1063 | sgtl5000_restore_regs(codec); | |
1064 | return 0; | |
1065 | } | |
1066 | #else | |
1067 | #define sgtl5000_suspend NULL | |
1068 | #define sgtl5000_resume NULL | |
1069 | #endif /* CONFIG_SUSPEND */ | |
1070 | ||
1071 | /* | |
1072 | * sgtl5000 has 3 internal power supplies: | |
1073 | * 1. VAG, normally set to vdda/2 | |
1074 | * 2. chargepump, set to different value | |
1075 | * according to voltage of vdda and vddio | |
1076 | * 3. line out VAG, normally set to vddio/2 | |
1077 | * | |
1078 | * and should be set according to: | |
1079 | * 1. vddd provided by external or not | |
1080 | * 2. vdda and vddio voltage value. > 3.1v or not | |
1081 | * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. | |
1082 | */ | |
1083 | static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) | |
1084 | { | |
1085 | int vddd; | |
1086 | int vdda; | |
1087 | int vddio; | |
1088 | u16 ana_pwr; | |
1089 | u16 lreg_ctrl; | |
1090 | int vag; | |
1091 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1092 | ||
1093 | vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); | |
1094 | vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); | |
1095 | vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); | |
1096 | ||
1097 | vdda = vdda / 1000; | |
1098 | vddio = vddio / 1000; | |
1099 | vddd = vddd / 1000; | |
1100 | ||
1101 | if (vdda <= 0 || vddio <= 0 || vddd < 0) { | |
1102 | dev_err(codec->dev, "regulator voltage not set correctly\n"); | |
1103 | ||
1104 | return -EINVAL; | |
1105 | } | |
1106 | ||
1107 | /* according to datasheet, maximum voltage of supplies */ | |
1108 | if (vdda > 3600 || vddio > 3600 || vddd > 1980) { | |
1109 | dev_err(codec->dev, | |
1110 | "exceed max voltage vdda %dmv vddio %dma vddd %dma\n", | |
1111 | vdda, vddio, vddd); | |
1112 | ||
1113 | return -EINVAL; | |
1114 | } | |
1115 | ||
1116 | /* reset value */ | |
1117 | ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); | |
1118 | ana_pwr |= SGTL5000_DAC_STEREO | | |
1119 | SGTL5000_ADC_STEREO | | |
1120 | SGTL5000_REFTOP_POWERUP; | |
1121 | lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); | |
1122 | ||
1123 | if (vddio < 3100 && vdda < 3100) { | |
1124 | /* enable internal oscillator used for charge pump */ | |
1125 | snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, | |
1126 | SGTL5000_INT_OSC_EN, | |
1127 | SGTL5000_INT_OSC_EN); | |
1128 | /* Enable VDDC charge pump */ | |
1129 | ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; | |
1130 | } else if (vddio >= 3100 && vdda >= 3100) { | |
1131 | /* | |
1132 | * if vddio and vddd > 3.1v, | |
1133 | * charge pump should be clean before set ana_pwr | |
1134 | */ | |
1135 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
1136 | SGTL5000_VDDC_CHRGPMP_POWERUP, 0); | |
1137 | ||
1138 | /* VDDC use VDDIO rail */ | |
1139 | lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; | |
1140 | lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << | |
1141 | SGTL5000_VDDC_MAN_ASSN_SHIFT; | |
1142 | } | |
1143 | ||
1144 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); | |
1145 | ||
1146 | snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); | |
1147 | ||
1148 | /* set voltage to register */ | |
1149 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, | |
1150 | (0x1 << 4) - 1, 0x8); | |
1151 | ||
1152 | /* | |
1153 | * if vddd linear reg has been enabled, | |
1154 | * simple digital supply should be clear to get | |
1155 | * proper VDDD voltage. | |
1156 | */ | |
1157 | if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) | |
1158 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
1159 | SGTL5000_LINREG_SIMPLE_POWERUP, | |
1160 | 0); | |
1161 | else | |
1162 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
1163 | SGTL5000_LINREG_SIMPLE_POWERUP | | |
1164 | SGTL5000_STARTUP_POWERUP, | |
1165 | 0); | |
1166 | ||
1167 | /* | |
1168 | * set ADC/DAC VAG to vdda / 2, | |
1169 | * should stay in range (0.8v, 1.575v) | |
1170 | */ | |
1171 | vag = vdda / 2; | |
1172 | if (vag <= SGTL5000_ANA_GND_BASE) | |
1173 | vag = 0; | |
1174 | else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * | |
1175 | (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) | |
1176 | vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; | |
1177 | else | |
1178 | vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; | |
1179 | ||
1180 | snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, | |
1181 | vag << SGTL5000_ANA_GND_SHIFT, | |
1182 | vag << SGTL5000_ANA_GND_SHIFT); | |
1183 | ||
1184 | /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ | |
1185 | vag = vddio / 2; | |
1186 | if (vag <= SGTL5000_LINE_OUT_GND_BASE) | |
1187 | vag = 0; | |
1188 | else if (vag >= SGTL5000_LINE_OUT_GND_BASE + | |
1189 | SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) | |
1190 | vag = SGTL5000_LINE_OUT_GND_MAX; | |
1191 | else | |
1192 | vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / | |
1193 | SGTL5000_LINE_OUT_GND_STP; | |
1194 | ||
1195 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, | |
1196 | vag << SGTL5000_LINE_OUT_GND_SHIFT | | |
1197 | SGTL5000_LINE_OUT_CURRENT_360u << | |
1198 | SGTL5000_LINE_OUT_CURRENT_SHIFT, | |
1199 | vag << SGTL5000_LINE_OUT_GND_SHIFT | | |
1200 | SGTL5000_LINE_OUT_CURRENT_360u << | |
1201 | SGTL5000_LINE_OUT_CURRENT_SHIFT); | |
1202 | ||
1203 | return 0; | |
1204 | } | |
1205 | ||
1206 | static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) | |
1207 | { | |
1208 | u16 reg; | |
1209 | int ret; | |
1210 | int rev; | |
1211 | int i; | |
1212 | int external_vddd = 0; | |
1213 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1214 | ||
1215 | for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) | |
1216 | sgtl5000->supplies[i].supply = supply_names[i]; | |
1217 | ||
1218 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), | |
1219 | sgtl5000->supplies); | |
1220 | if (!ret) | |
1221 | external_vddd = 1; | |
1222 | else { | |
1223 | /* set internal ldo to 1.2v */ | |
1224 | int voltage = LDO_VOLTAGE; | |
1225 | ||
1226 | ret = ldo_regulator_register(codec, &ldo_init_data, voltage); | |
1227 | if (ret) { | |
1228 | dev_err(codec->dev, | |
1229 | "Failed to register vddd internal supplies: %d\n", | |
1230 | ret); | |
1231 | return ret; | |
1232 | } | |
1233 | ||
1234 | sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; | |
1235 | ||
1236 | ret = regulator_bulk_get(codec->dev, | |
1237 | ARRAY_SIZE(sgtl5000->supplies), | |
1238 | sgtl5000->supplies); | |
1239 | ||
1240 | if (ret) { | |
1241 | ldo_regulator_remove(codec); | |
1242 | dev_err(codec->dev, | |
1243 | "Failed to request supplies: %d\n", ret); | |
1244 | ||
1245 | return ret; | |
1246 | } | |
1247 | } | |
1248 | ||
1249 | ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), | |
1250 | sgtl5000->supplies); | |
1251 | if (ret) | |
1252 | goto err_regulator_free; | |
1253 | ||
1254 | /* wait for all power rails bring up */ | |
1255 | udelay(10); | |
1256 | ||
1257 | /* read chip information */ | |
1258 | reg = snd_soc_read(codec, SGTL5000_CHIP_ID); | |
1259 | if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != | |
1260 | SGTL5000_PARTID_PART_ID) { | |
1261 | dev_err(codec->dev, | |
1262 | "Device with ID register %x is not a sgtl5000\n", reg); | |
1263 | ret = -ENODEV; | |
1264 | goto err_regulator_disable; | |
1265 | } | |
1266 | ||
1267 | rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; | |
1268 | dev_info(codec->dev, "sgtl5000 revision %d\n", rev); | |
1269 | ||
1270 | /* | |
1271 | * workaround for revision 0x11 and later, | |
1272 | * roll back to use internal LDO | |
1273 | */ | |
1274 | if (external_vddd && rev >= 0x11) { | |
1275 | int voltage = LDO_VOLTAGE; | |
1276 | /* disable all regulator first */ | |
1277 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1278 | sgtl5000->supplies); | |
1279 | /* free VDDD regulator */ | |
1280 | regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), | |
1281 | sgtl5000->supplies); | |
1282 | ||
1283 | ret = ldo_regulator_register(codec, &ldo_init_data, voltage); | |
1284 | if (ret) | |
1285 | return ret; | |
1286 | ||
1287 | sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; | |
1288 | ||
1289 | ret = regulator_bulk_get(codec->dev, | |
1290 | ARRAY_SIZE(sgtl5000->supplies), | |
1291 | sgtl5000->supplies); | |
1292 | if (ret) { | |
1293 | ldo_regulator_remove(codec); | |
1294 | dev_err(codec->dev, | |
1295 | "Failed to request supplies: %d\n", ret); | |
1296 | ||
1297 | return ret; | |
1298 | } | |
1299 | ||
1300 | ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), | |
1301 | sgtl5000->supplies); | |
1302 | if (ret) | |
1303 | goto err_regulator_free; | |
1304 | ||
1305 | /* wait for all power rails bring up */ | |
1306 | udelay(10); | |
1307 | } | |
1308 | ||
1309 | return 0; | |
1310 | ||
1311 | err_regulator_disable: | |
1312 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1313 | sgtl5000->supplies); | |
1314 | err_regulator_free: | |
1315 | regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), | |
1316 | sgtl5000->supplies); | |
1317 | if (external_vddd) | |
1318 | ldo_regulator_remove(codec); | |
1319 | return ret; | |
1320 | ||
1321 | } | |
1322 | ||
1323 | static int sgtl5000_probe(struct snd_soc_codec *codec) | |
1324 | { | |
1325 | int ret; | |
1326 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1327 | ||
1328 | /* setup i2c data ops */ | |
1329 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); | |
1330 | if (ret < 0) { | |
1331 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
1332 | return ret; | |
1333 | } | |
1334 | ||
1335 | ret = sgtl5000_enable_regulators(codec); | |
1336 | if (ret) | |
1337 | return ret; | |
1338 | ||
1339 | /* power up sgtl5000 */ | |
1340 | ret = sgtl5000_set_power_regs(codec); | |
1341 | if (ret) | |
1342 | goto err; | |
1343 | ||
1344 | /* enable small pop, introduce 400ms delay in turning off */ | |
1345 | snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, | |
1346 | SGTL5000_SMALL_POP, | |
1347 | SGTL5000_SMALL_POP); | |
1348 | ||
1349 | /* disable short cut detector */ | |
1350 | snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); | |
1351 | ||
1352 | /* | |
1353 | * set i2s as default input of sound switch | |
1354 | * TODO: add sound switch to control and dapm widge. | |
1355 | */ | |
1356 | snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, | |
1357 | SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); | |
1358 | snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, | |
1359 | SGTL5000_ADC_EN | SGTL5000_DAC_EN); | |
1360 | ||
1361 | /* enable dac volume ramp by default */ | |
1362 | snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, | |
1363 | SGTL5000_DAC_VOL_RAMP_EN | | |
1364 | SGTL5000_DAC_MUTE_RIGHT | | |
1365 | SGTL5000_DAC_MUTE_LEFT); | |
1366 | ||
1367 | snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); | |
1368 | ||
1369 | snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, | |
1370 | SGTL5000_HP_ZCD_EN | | |
1371 | SGTL5000_ADC_ZCD_EN); | |
1372 | ||
1373 | snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0); | |
1374 | ||
1375 | /* | |
1376 | * disable DAP | |
1377 | * TODO: | |
1378 | * Enable DAP in kcontrol and dapm. | |
1379 | */ | |
1380 | snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); | |
1381 | ||
1382 | /* leading to standby state */ | |
1383 | ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1384 | if (ret) | |
1385 | goto err; | |
1386 | ||
1387 | snd_soc_add_controls(codec, sgtl5000_snd_controls, | |
1388 | ARRAY_SIZE(sgtl5000_snd_controls)); | |
1389 | ||
1390 | snd_soc_dapm_new_controls(&codec->dapm, sgtl5000_dapm_widgets, | |
1391 | ARRAY_SIZE(sgtl5000_dapm_widgets)); | |
1392 | ||
1393 | snd_soc_dapm_add_routes(&codec->dapm, audio_map, | |
1394 | ARRAY_SIZE(audio_map)); | |
1395 | ||
1396 | snd_soc_dapm_new_widgets(&codec->dapm); | |
1397 | ||
1398 | return 0; | |
1399 | ||
1400 | err: | |
1401 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1402 | sgtl5000->supplies); | |
1403 | regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), | |
1404 | sgtl5000->supplies); | |
1405 | ldo_regulator_remove(codec); | |
1406 | ||
1407 | return ret; | |
1408 | } | |
1409 | ||
1410 | static int sgtl5000_remove(struct snd_soc_codec *codec) | |
1411 | { | |
1412 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1413 | ||
1414 | sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1415 | ||
1416 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1417 | sgtl5000->supplies); | |
1418 | regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), | |
1419 | sgtl5000->supplies); | |
1420 | ldo_regulator_remove(codec); | |
1421 | ||
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | struct snd_soc_codec_driver sgtl5000_driver = { | |
1426 | .probe = sgtl5000_probe, | |
1427 | .remove = sgtl5000_remove, | |
1428 | .suspend = sgtl5000_suspend, | |
1429 | .resume = sgtl5000_resume, | |
1430 | .set_bias_level = sgtl5000_set_bias_level, | |
1431 | .reg_cache_size = ARRAY_SIZE(sgtl5000_regs), | |
1432 | .reg_word_size = sizeof(u16), | |
1433 | .reg_cache_step = 2, | |
1434 | .reg_cache_default = sgtl5000_regs, | |
1435 | .volatile_register = sgtl5000_volatile_register, | |
1436 | }; | |
1437 | ||
1438 | static __devinit int sgtl5000_i2c_probe(struct i2c_client *client, | |
1439 | const struct i2c_device_id *id) | |
1440 | { | |
1441 | struct sgtl5000_priv *sgtl5000; | |
1442 | int ret; | |
1443 | ||
1444 | sgtl5000 = kzalloc(sizeof(struct sgtl5000_priv), GFP_KERNEL); | |
1445 | if (!sgtl5000) | |
1446 | return -ENOMEM; | |
1447 | ||
1448 | /* | |
1449 | * copy DAP default values to default value array. | |
1450 | * sgtl5000 register space has a big hole, merge it | |
1451 | * at init phase makes life easy. | |
1452 | * FIXME: should we drop 'const' of sgtl5000_regs? | |
1453 | */ | |
1454 | memcpy((void *)(&sgtl5000_regs[0] + (SGTL5000_DAP_REG_OFFSET >> 1)), | |
1455 | sgtl5000_dap_regs, | |
1456 | SGTL5000_MAX_REG_OFFSET - SGTL5000_DAP_REG_OFFSET); | |
1457 | ||
1458 | i2c_set_clientdata(client, sgtl5000); | |
1459 | ||
1460 | ret = snd_soc_register_codec(&client->dev, | |
1461 | &sgtl5000_driver, &sgtl5000_dai, 1); | |
1462 | if (ret) { | |
1463 | dev_err(&client->dev, "Failed to register codec: %d\n", ret); | |
1464 | kfree(sgtl5000); | |
1465 | return ret; | |
1466 | } | |
1467 | ||
1468 | return 0; | |
1469 | } | |
1470 | ||
1471 | static __devexit int sgtl5000_i2c_remove(struct i2c_client *client) | |
1472 | { | |
1473 | struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); | |
1474 | ||
1475 | snd_soc_unregister_codec(&client->dev); | |
1476 | ||
1477 | kfree(sgtl5000); | |
1478 | return 0; | |
1479 | } | |
1480 | ||
1481 | static const struct i2c_device_id sgtl5000_id[] = { | |
1482 | {"sgtl5000", 0}, | |
1483 | {}, | |
1484 | }; | |
1485 | ||
1486 | MODULE_DEVICE_TABLE(i2c, sgtl5000_id); | |
1487 | ||
1488 | static struct i2c_driver sgtl5000_i2c_driver = { | |
1489 | .driver = { | |
1490 | .name = "sgtl5000", | |
1491 | .owner = THIS_MODULE, | |
1492 | }, | |
1493 | .probe = sgtl5000_i2c_probe, | |
1494 | .remove = __devexit_p(sgtl5000_i2c_remove), | |
1495 | .id_table = sgtl5000_id, | |
1496 | }; | |
1497 | ||
1498 | static int __init sgtl5000_modinit(void) | |
1499 | { | |
1500 | return i2c_add_driver(&sgtl5000_i2c_driver); | |
1501 | } | |
1502 | module_init(sgtl5000_modinit); | |
1503 | ||
1504 | static void __exit sgtl5000_exit(void) | |
1505 | { | |
1506 | i2c_del_driver(&sgtl5000_i2c_driver); | |
1507 | } | |
1508 | module_exit(sgtl5000_exit); | |
1509 | ||
1510 | MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); | |
1511 | MODULE_AUTHOR("Zeng Zhaoming <zhaoming.zeng@freescale.com>"); | |
1512 | MODULE_LICENSE("GPL"); |