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Merge tag 'char-misc-3.3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / sgtl5000.c
CommitLineData
9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
9b34e6cc
ZZ		 19#include <linux/regulator/driver.h>
20#include <linux/regulator/machine.h>
21#include <linux/regulator/consumer.h>
58e49424 22#include <linux/of_device.h>
9b34e6cc
ZZ		 23#include <sound/core.h>
24#include <sound/tlv.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
9b34e6cc
ZZ		 30
31#include "sgtl5000.h"
32
33#define SGTL5000_DAP_REG_OFFSET 0x0100
34#define SGTL5000_MAX_REG_OFFSET 0x013A
35
151798f8
WS		 36/* default value of sgtl5000 registers */
37static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = {
38 [SGTL5000_CHIP_CLK_CTRL] = 0x0008,
39 [SGTL5000_CHIP_I2S_CTRL] = 0x0010,
40 [SGTL5000_CHIP_SSS_CTRL] = 0x0008,
41 [SGTL5000_CHIP_DAC_VOL] = 0x3c3c,
42 [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f,
43 [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818,
44 [SGTL5000_CHIP_ANA_CTRL] = 0x0111,
45 [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404,
46 [SGTL5000_CHIP_ANA_POWER] = 0x7060,
47 [SGTL5000_CHIP_PLL_CTRL] = 0x5000,
48 [SGTL5000_DAP_BASS_ENHANCE] = 0x0040,
49 [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f,
50 [SGTL5000_DAP_SURROUND] = 0x0040,
51 [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f,
52 [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f,
53 [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f,
54 [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f,
55 [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f,
56 [SGTL5000_DAP_MAIN_CHAN] = 0x8000,
57 [SGTL5000_DAP_AVC_CTRL] = 0x0510,
58 [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473,
59 [SGTL5000_DAP_AVC_ATTACK] = 0x0028,
60 [SGTL5000_DAP_AVC_DECAY] = 0x0050,
9b34e6cc
ZZ		 61};
62
63/* regulator supplies for sgtl5000, VDDD is an optional external supply */
64enum sgtl5000_regulator_supplies {
65 VDDA,
66 VDDIO,
67 VDDD,
68 SGTL5000_SUPPLY_NUM
69};
70
71/* vddd is optional supply */
72static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
73 "VDDA",
74 "VDDIO",
75 "VDDD"
76};
77
78#define LDO_CONSUMER_NAME "VDDD_LDO"
79#define LDO_VOLTAGE 1200000
80
81static struct regulator_consumer_supply ldo_consumer[] = {
82 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
83};
84
61a142b7 85static struct regulator_init_data ldo_init_data = {
9b34e6cc
ZZ		 86 .constraints = {
87 .min_uV = 850000,
88 .max_uV = 1600000,
89 .valid_modes_mask = REGULATOR_MODE_NORMAL,
90 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
91 },
92 .num_consumer_supplies = 1,
93 .consumer_supplies = &ldo_consumer[0],
94};
95
96/*
97 * sgtl5000 internal ldo regulator,
98 * enabled when VDDD not provided
99 */
100struct ldo_regulator {
101 struct regulator_desc desc;
102 struct regulator_dev *dev;
103 int voltage;
104 void *codec_data;
105 bool enabled;
106};
107
108/* sgtl5000 private structure in codec */
109struct sgtl5000_priv {
110 int sysclk; /* sysclk rate */
111 int master; /* i2s master or not */
112 int fmt; /* i2s data format */
113 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
114 struct ldo_regulator *ldo;
115};
116
117/*
118 * mic_bias power on/off share the same register bits with
119 * output impedance of mic bias, when power on mic bias, we
120 * need reclaim it to impedance value.
121 * 0x0 = Powered off
122 * 0x1 = 2Kohm
123 * 0x2 = 4Kohm
124 * 0x3 = 8Kohm
125 */
126static int mic_bias_event(struct snd_soc_dapm_widget *w,
127 struct snd_kcontrol *kcontrol, int event)
128{
129 switch (event) {
130 case SND_SOC_DAPM_POST_PMU:
131 /* change mic bias resistor to 4Kohm */
132 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8
AL		 133 SGTL5000_BIAS_R_MASK,
134 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 135 break;
136
137 case SND_SOC_DAPM_PRE_PMD:
9b34e6cc 138 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 139 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 140 break;
141 }
142 return 0;
143}
144
145/*
146 * using codec assist to small pop, hp_powerup or lineout_powerup
147 * should stay setting until vag_powerup is fully ramped down,
148 * vag fully ramped down require 400ms.
149 */
150static int small_pop_event(struct snd_soc_dapm_widget *w,
151 struct snd_kcontrol *kcontrol, int event)
152{
153 switch (event) {
154 case SND_SOC_DAPM_PRE_PMU:
155 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
156 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
157 break;
158
159 case SND_SOC_DAPM_PRE_PMD:
160 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
161 SGTL5000_VAG_POWERUP, 0);
162 msleep(400);
163 break;
164 default:
165 break;
166 }
167
168 return 0;
169}
170
171/* input sources for ADC */
172static const char *adc_mux_text[] = {
173 "MIC_IN", "LINE_IN"
174};
175
176static const struct soc_enum adc_enum =
177SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
178
179static const struct snd_kcontrol_new adc_mux =
180SOC_DAPM_ENUM("Capture Mux", adc_enum);
181
182/* input sources for DAC */
183static const char *dac_mux_text[] = {
184 "DAC", "LINE_IN"
185};
186
187static const struct soc_enum dac_enum =
188SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
189
190static const struct snd_kcontrol_new dac_mux =
191SOC_DAPM_ENUM("Headphone Mux", dac_enum);
192
193static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
194 SND_SOC_DAPM_INPUT("LINE_IN"),
195 SND_SOC_DAPM_INPUT("MIC_IN"),
196
197 SND_SOC_DAPM_OUTPUT("HP_OUT"),
198 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
199
200 SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
201 mic_bias_event,
202 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
203
204 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
205 small_pop_event,
206 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
207 SND_SOC_DAPM_PGA_E("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0,
208 small_pop_event,
209 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
210
211 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
212 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
213
214 /* aif for i2s input */
215 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
216 0, SGTL5000_CHIP_DIG_POWER,
217 0, 0),
218
219 /* aif for i2s output */
220 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
221 0, SGTL5000_CHIP_DIG_POWER,
222 1, 0),
223
224 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
225
226 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
227};
228
229/* routes for sgtl5000 */
230static const struct snd_soc_dapm_route audio_map[] = {
231 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
232 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
233
234 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
235 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
236
237 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
238 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
239 {"LO", NULL, "DAC"}, /* dac --> line_out */
240
241 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
242 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
243
244 {"LINE_OUT", NULL, "LO"},
245 {"HP_OUT", NULL, "HP"},
246};
247
248/* custom function to fetch info of PCM playback volume */
249static int dac_info_volsw(struct snd_kcontrol *kcontrol,
250 struct snd_ctl_elem_info *uinfo)
251{
252 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
253 uinfo->count = 2;
254 uinfo->value.integer.min = 0;
255 uinfo->value.integer.max = 0xfc - 0x3c;
256 return 0;
257}
258
259/*
260 * custom function to get of PCM playback volume
261 *
262 * dac volume register
263 * 15-------------8-7--------------0
264 * | R channel vol | L channel vol |
265 * -------------------------------
266 *
267 * PCM volume with 0.5017 dB steps from 0 to -90 dB
268 *
269 * register values map to dB
270 * 0x3B and less = Reserved
271 * 0x3C = 0 dB
272 * 0x3D = -0.5 dB
273 * 0xF0 = -90 dB
274 * 0xFC and greater = Muted
275 *
276 * register value map to userspace value
277 *
278 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
279 * ------------------------------
280 * userspace value 0xc0 0
281 */
282static int dac_get_volsw(struct snd_kcontrol *kcontrol,
283 struct snd_ctl_elem_value *ucontrol)
284{
285 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
286 int reg;
287 int l;
288 int r;
289
290 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
291
292 /* get left channel volume */
293 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
294
295 /* get right channel volume */
296 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
297
298 /* make sure value fall in (0x3c,0xfc) */
299 l = clamp(l, 0x3c, 0xfc);
300 r = clamp(r, 0x3c, 0xfc);
301
302 /* invert it and map to userspace value */
303 l = 0xfc - l;
304 r = 0xfc - r;
305
306 ucontrol->value.integer.value[0] = l;
307 ucontrol->value.integer.value[1] = r;
308
309 return 0;
310}
311
312/*
313 * custom function to put of PCM playback volume
314 *
315 * dac volume register
316 * 15-------------8-7--------------0
317 * | R channel vol | L channel vol |
318 * -------------------------------
319 *
320 * PCM volume with 0.5017 dB steps from 0 to -90 dB
321 *
322 * register values map to dB
323 * 0x3B and less = Reserved
324 * 0x3C = 0 dB
325 * 0x3D = -0.5 dB
326 * 0xF0 = -90 dB
327 * 0xFC and greater = Muted
328 *
329 * userspace value map to register value
330 *
331 * userspace value 0xc0 0
332 * ------------------------------
333 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
334 */
335static int dac_put_volsw(struct snd_kcontrol *kcontrol,
336 struct snd_ctl_elem_value *ucontrol)
337{
338 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
339 int reg;
340 int l;
341 int r;
342
343 l = ucontrol->value.integer.value[0];
344 r = ucontrol->value.integer.value[1];
345
346 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
347 l = clamp(l, 0, 0xfc - 0x3c);
348 r = clamp(r, 0, 0xfc - 0x3c);
349
350 /* invert it, get the value can be set to register */
351 l = 0xfc - l;
352 r = 0xfc - r;
353
354 /* shift to get the register value */
355 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
356 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
357
358 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
359
360 return 0;
361}
362
363static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
364
365/* tlv for mic gain, 0db 20db 30db 40db */
366static const unsigned int mic_gain_tlv[] = {
740fb9d5 367 TLV_DB_RANGE_HEAD(2),
9b34e6cc
ZZ		 368 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
369 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
370};
371
372/* tlv for hp volume, -51.5db to 12.0db, step .5db */
373static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
374
375static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
376 /* SOC_DOUBLE_S8_TLV with invert */
377 {
378 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
379 .name = "PCM Playback Volume",
380 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
381 SNDRV_CTL_ELEM_ACCESS_READWRITE,
382 .info = dac_info_volsw,
383 .get = dac_get_volsw,
384 .put = dac_put_volsw,
385 },
386
387 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
388 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
389 SGTL5000_CHIP_ANA_ADC_CTRL,
390 8, 2, 0, capture_6db_attenuate),
391 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
392
393 SOC_DOUBLE_TLV("Headphone Playback Volume",
394 SGTL5000_CHIP_ANA_HP_CTRL,
395 0, 8,
396 0x7f, 1,
397 headphone_volume),
398 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
399 5, 1, 0),
400
401 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
402 0, 4, 0, mic_gain_tlv),
403};
404
405/* mute the codec used by alsa core */
406static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
407{
408 struct snd_soc_codec *codec = codec_dai->codec;
409 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
410
411 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
412 adcdac_ctrl, mute ? adcdac_ctrl : 0);
413
414 return 0;
415}
416
417/* set codec format */
418static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
419{
420 struct snd_soc_codec *codec = codec_dai->codec;
421 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
422 u16 i2sctl = 0;
423
424 sgtl5000->master = 0;
425 /*
426 * i2s clock and frame master setting.
427 * ONLY support:
428 * - clock and frame slave,
429 * - clock and frame master
430 */
431 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
432 case SND_SOC_DAIFMT_CBS_CFS:
433 break;
434 case SND_SOC_DAIFMT_CBM_CFM:
435 i2sctl |= SGTL5000_I2S_MASTER;
436 sgtl5000->master = 1;
437 break;
438 default:
439 return -EINVAL;
440 }
441
442 /* setting i2s data format */
443 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
444 case SND_SOC_DAIFMT_DSP_A:
445 i2sctl |= SGTL5000_I2S_MODE_PCM;
446 break;
447 case SND_SOC_DAIFMT_DSP_B:
448 i2sctl |= SGTL5000_I2S_MODE_PCM;
449 i2sctl |= SGTL5000_I2S_LRALIGN;
450 break;
451 case SND_SOC_DAIFMT_I2S:
452 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
453 break;
454 case SND_SOC_DAIFMT_RIGHT_J:
455 i2sctl |= SGTL5000_I2S_MODE_RJ;
456 i2sctl |= SGTL5000_I2S_LRPOL;
457 break;
458 case SND_SOC_DAIFMT_LEFT_J:
459 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
460 i2sctl |= SGTL5000_I2S_LRALIGN;
461 break;
462 default:
463 return -EINVAL;
464 }
465
466 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
467
468 /* Clock inversion */
469 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
470 case SND_SOC_DAIFMT_NB_NF:
471 break;
472 case SND_SOC_DAIFMT_IB_NF:
473 i2sctl |= SGTL5000_I2S_SCLK_INV;
474 break;
475 default:
476 return -EINVAL;
477 }
478
479 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
480
481 return 0;
482}
483
484/* set codec sysclk */
485static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
486 int clk_id, unsigned int freq, int dir)
487{
488 struct snd_soc_codec *codec = codec_dai->codec;
489 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
490
491 switch (clk_id) {
492 case SGTL5000_SYSCLK:
493 sgtl5000->sysclk = freq;
494 break;
495 default:
496 return -EINVAL;
497 }
498
499 return 0;
500}
501
502/*
503 * set clock according to i2s frame clock,
504 * sgtl5000 provide 2 clock sources.
505 * 1. sys_mclk. sample freq can only configure to
506 * 1/256, 1/384, 1/512 of sys_mclk.
507 * 2. pll. can derive any audio clocks.
508 *
509 * clock setting rules:
510 * 1. in slave mode, only sys_mclk can use.
511 * 2. as constraint by sys_mclk, sample freq should
512 * set to 32k, 44.1k and above.
513 * 3. using sys_mclk prefer to pll to save power.
514 */
515static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
516{
517 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
518 int clk_ctl = 0;
519 int sys_fs; /* sample freq */
520
521 /*
522 * sample freq should be divided by frame clock,
523 * if frame clock lower than 44.1khz, sample feq should set to
524 * 32khz or 44.1khz.
525 */
526 switch (frame_rate) {
527 case 8000:
528 case 16000:
529 sys_fs = 32000;
530 break;
531 case 11025:
532 case 22050:
533 sys_fs = 44100;
534 break;
535 default:
536 sys_fs = frame_rate;
537 break;
538 }
539
540 /* set divided factor of frame clock */
541 switch (sys_fs / frame_rate) {
542 case 4:
543 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
544 break;
545 case 2:
546 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
547 break;
548 case 1:
549 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
550 break;
551 default:
552 return -EINVAL;
553 }
554
555 /* set the sys_fs according to frame rate */
556 switch (sys_fs) {
557 case 32000:
558 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
559 break;
560 case 44100:
561 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
562 break;
563 case 48000:
564 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
565 break;
566 case 96000:
567 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
568 break;
569 default:
570 dev_err(codec->dev, "frame rate %d not supported\n",
571 frame_rate);
572 return -EINVAL;
573 }
574
575 /*
576 * calculate the divider of mclk/sample_freq,
577 * factor of freq =96k can only be 256, since mclk in range (12m,27m)
578 */
579 switch (sgtl5000->sysclk / sys_fs) {
580 case 256:
581 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
582 SGTL5000_MCLK_FREQ_SHIFT;
583 break;
584 case 384:
585 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
586 SGTL5000_MCLK_FREQ_SHIFT;
587 break;
588 case 512:
589 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
590 SGTL5000_MCLK_FREQ_SHIFT;
591 break;
592 default:
593 /* if mclk not satisify the divider, use pll */
594 if (sgtl5000->master) {
595 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
596 SGTL5000_MCLK_FREQ_SHIFT;
597 } else {
598 dev_err(codec->dev,
599 "PLL not supported in slave mode\n");
600 return -EINVAL;
601 }
602 }
603
604 /* if using pll, please check manual 6.4.2 for detail */
605 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
606 u64 out, t;
607 int div2;
608 int pll_ctl;
609 unsigned int in, int_div, frac_div;
610
611 if (sgtl5000->sysclk > 17000000) {
612 div2 = 1;
613 in = sgtl5000->sysclk / 2;
614 } else {
615 div2 = 0;
616 in = sgtl5000->sysclk;
617 }
618 if (sys_fs == 44100)
619 out = 180633600;
620 else
621 out = 196608000;
622 t = do_div(out, in);
623 int_div = out;
624 t *= 2048;
625 do_div(t, in);
626 frac_div = t;
627 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
628 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
629
630 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
631 if (div2)
632 snd_soc_update_bits(codec,
633 SGTL5000_CHIP_CLK_TOP_CTRL,
634 SGTL5000_INPUT_FREQ_DIV2,
635 SGTL5000_INPUT_FREQ_DIV2);
636 else
637 snd_soc_update_bits(codec,
638 SGTL5000_CHIP_CLK_TOP_CTRL,
639 SGTL5000_INPUT_FREQ_DIV2,
640 0);
641
642 /* power up pll */
643 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
644 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
645 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
646 } else {
647 /* power down pll */
648 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
649 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
650 0);
651 }
652
653 /* if using pll, clk_ctrl must be set after pll power up */
654 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
655
656 return 0;
657}
658
659/*
660 * Set PCM DAI bit size and sample rate.
661 * input: params_rate, params_fmt
662 */
663static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
664 struct snd_pcm_hw_params *params,
665 struct snd_soc_dai *dai)
666{
667 struct snd_soc_pcm_runtime *rtd = substream->private_data;
668 struct snd_soc_codec *codec = rtd->codec;
669 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
670 int channels = params_channels(params);
671 int i2s_ctl = 0;
672 int stereo;
673 int ret;
674
675 /* sysclk should already set */
676 if (!sgtl5000->sysclk) {
677 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
678 return -EFAULT;
679 }
680
681 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
682 stereo = SGTL5000_DAC_STEREO;
683 else
684 stereo = SGTL5000_ADC_STEREO;
685
686 /* set mono to save power */
687 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
688 channels == 1 ? 0 : stereo);
689
690 /* set codec clock base on lrclk */
691 ret = sgtl5000_set_clock(codec, params_rate(params));
692 if (ret)
693 return ret;
694
695 /* set i2s data format */
696 switch (params_format(params)) {
697 case SNDRV_PCM_FORMAT_S16_LE:
698 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
699 return -EINVAL;
700 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
701 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
702 SGTL5000_I2S_SCLKFREQ_SHIFT;
703 break;
704 case SNDRV_PCM_FORMAT_S20_3LE:
705 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
706 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
707 SGTL5000_I2S_SCLKFREQ_SHIFT;
708 break;
709 case SNDRV_PCM_FORMAT_S24_LE:
710 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
711 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
712 SGTL5000_I2S_SCLKFREQ_SHIFT;
713 break;
714 case SNDRV_PCM_FORMAT_S32_LE:
715 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
716 return -EINVAL;
717 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
718 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
719 SGTL5000_I2S_SCLKFREQ_SHIFT;
720 break;
721 default:
722 return -EINVAL;
723 }
724
33cb92cf
AL		 725 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
726 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
727 i2s_ctl);
9b34e6cc
ZZ		 728
729 return 0;
730}
731
333802e9 732#ifdef CONFIG_REGULATOR
9b34e6cc
ZZ		 733static int ldo_regulator_is_enabled(struct regulator_dev *dev)
734{
735 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
736
737 return ldo->enabled;
738}
739
740static int ldo_regulator_enable(struct regulator_dev *dev)
741{
742 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
743 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
744 int reg;
745
746 if (ldo_regulator_is_enabled(dev))
747 return 0;
748
749 /* set regulator value firstly */
750 reg = (1600 - ldo->voltage / 1000) / 50;
751 reg = clamp(reg, 0x0, 0xf);
752
753 /* amend the voltage value, unit: uV */
754 ldo->voltage = (1600 - reg * 50) * 1000;
755
756 /* set voltage to register */
757 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 758 SGTL5000_LINREG_VDDD_MASK, reg);
9b34e6cc
ZZ		 759
760 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
761 SGTL5000_LINEREG_D_POWERUP,
762 SGTL5000_LINEREG_D_POWERUP);
763
764 /* when internal ldo enabled, simple digital power can be disabled */
765 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
766 SGTL5000_LINREG_SIMPLE_POWERUP,
767 0);
768
769 ldo->enabled = 1;
770 return 0;
771}
772
773static int ldo_regulator_disable(struct regulator_dev *dev)
774{
775 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
776 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
777
778 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
779 SGTL5000_LINEREG_D_POWERUP,
780 0);
781
782 /* clear voltage info */
783 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 784 SGTL5000_LINREG_VDDD_MASK, 0);
9b34e6cc
ZZ		 785
786 ldo->enabled = 0;
787
788 return 0;
789}
790
791static int ldo_regulator_get_voltage(struct regulator_dev *dev)
792{
793 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
794
795 return ldo->voltage;
796}
797
798static struct regulator_ops ldo_regulator_ops = {
799 .is_enabled = ldo_regulator_is_enabled,
800 .enable = ldo_regulator_enable,
801 .disable = ldo_regulator_disable,
802 .get_voltage = ldo_regulator_get_voltage,
803};
804
805static int ldo_regulator_register(struct snd_soc_codec *codec,
806 struct regulator_init_data *init_data,
807 int voltage)
808{
809 struct ldo_regulator *ldo;
5b13de7a 810 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
9b34e6cc
ZZ		 811
812 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
813
814 if (!ldo) {
815 dev_err(codec->dev, "failed to allocate ldo_regulator\n");
816 return -ENOMEM;
817 }
818
819 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
820 if (!ldo->desc.name) {
821 kfree(ldo);
822 dev_err(codec->dev, "failed to allocate decs name memory\n");
823 return -ENOMEM;
824 }
825
826 ldo->desc.type = REGULATOR_VOLTAGE;
827 ldo->desc.owner = THIS_MODULE;
828 ldo->desc.ops = &ldo_regulator_ops;
829 ldo->desc.n_voltages = 1;
830
831 ldo->codec_data = codec;
832 ldo->voltage = voltage;
833
834 ldo->dev = regulator_register(&ldo->desc, codec->dev,
2c043bcb 835 init_data, ldo, NULL);
9b34e6cc 836 if (IS_ERR(ldo->dev)) {
62f75aaf
DC		 837 int ret = PTR_ERR(ldo->dev);
838
9b34e6cc
ZZ		 839 dev_err(codec->dev, "failed to register regulator\n");
840 kfree(ldo->desc.name);
841 kfree(ldo);
842
62f75aaf 843 return ret;
9b34e6cc 844 }
5b13de7a 845 sgtl5000->ldo = ldo;
9b34e6cc
ZZ		 846
847 return 0;
848}
849
850static int ldo_regulator_remove(struct snd_soc_codec *codec)
851{
852 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
853 struct ldo_regulator *ldo = sgtl5000->ldo;
854
855 if (!ldo)
856 return 0;
857
858 regulator_unregister(ldo->dev);
859 kfree(ldo->desc.name);
860 kfree(ldo);
861
862 return 0;
863}
333802e9
MB		 864#else
865static int ldo_regulator_register(struct snd_soc_codec *codec,
866 struct regulator_init_data *init_data,
867 int voltage)
868{
09bddc8e 869 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
333802e9
MB		 870 return -EINVAL;
871}
872
873static int ldo_regulator_remove(struct snd_soc_codec *codec)
874{
875 return 0;
876}
877#endif
9b34e6cc
ZZ		 878
879/*
880 * set dac bias
881 * common state changes:
882 * startup:
883 * off --> standby --> prepare --> on
884 * standby --> prepare --> on
885 *
886 * stop:
887 * on --> prepare --> standby
888 */
889static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
890 enum snd_soc_bias_level level)
891{
892 int ret;
893 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
894
895 switch (level) {
896 case SND_SOC_BIAS_ON:
897 case SND_SOC_BIAS_PREPARE:
898 break;
899 case SND_SOC_BIAS_STANDBY:
900 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
901 ret = regulator_bulk_enable(
902 ARRAY_SIZE(sgtl5000->supplies),
903 sgtl5000->supplies);
904 if (ret)
905 return ret;
906 udelay(10);
907 }
908
909 break;
910 case SND_SOC_BIAS_OFF:
911 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
912 sgtl5000->supplies);
913 break;
914 }
915
916 codec->dapm.bias_level = level;
917 return 0;
918}
919
920#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
921 SNDRV_PCM_FMTBIT_S20_3LE |\
922 SNDRV_PCM_FMTBIT_S24_LE |\
923 SNDRV_PCM_FMTBIT_S32_LE)
924
85e7652d 925static const struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 926 .hw_params = sgtl5000_pcm_hw_params,
927 .digital_mute = sgtl5000_digital_mute,
928 .set_fmt = sgtl5000_set_dai_fmt,
929 .set_sysclk = sgtl5000_set_dai_sysclk,
930};
931
932static struct snd_soc_dai_driver sgtl5000_dai = {
933 .name = "sgtl5000",
934 .playback = {
935 .stream_name = "Playback",
936 .channels_min = 1,
937 .channels_max = 2,
938 /*
939 * only support 8~48K + 96K,
940 * TODO modify hw_param to support more
941 */
942 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
943 .formats = SGTL5000_FORMATS,
944 },
945 .capture = {
946 .stream_name = "Capture",
947 .channels_min = 1,
948 .channels_max = 2,
949 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
950 .formats = SGTL5000_FORMATS,
951 },
952 .ops = &sgtl5000_ops,
953 .symmetric_rates = 1,
954};
955
956static int sgtl5000_volatile_register(struct snd_soc_codec *codec,
957 unsigned int reg)
958{
959 switch (reg) {
960 case SGTL5000_CHIP_ID:
961 case SGTL5000_CHIP_ADCDAC_CTRL:
962 case SGTL5000_CHIP_ANA_STATUS:
963 return 1;
964 }
965
966 return 0;
967}
968
969#ifdef CONFIG_SUSPEND
84b315ee 970static int sgtl5000_suspend(struct snd_soc_codec *codec)
9b34e6cc
ZZ		 971{
972 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
973
974 return 0;
975}
976
977/*
978 * restore all sgtl5000 registers,
979 * since a big hole between dap and regular registers,
980 * we will restore them respectively.
981 */
982static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
983{
984 u16 *cache = codec->reg_cache;
151798f8 985 u16 reg;
9b34e6cc
ZZ		 986
987 /* restore regular registers */
151798f8 988 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
9b34e6cc 989
bb362e2e 990 /* These regs should restore in particular order */
9b34e6cc
ZZ		 991 if (reg == SGTL5000_CHIP_ANA_POWER ||
992 reg == SGTL5000_CHIP_CLK_CTRL ||
993 reg == SGTL5000_CHIP_LINREG_CTRL ||
994 reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
bb362e2e 995 reg == SGTL5000_CHIP_REF_CTRL)
9b34e6cc
ZZ		 996 continue;
997
151798f8 998 snd_soc_write(codec, reg, cache[reg]);
9b34e6cc
ZZ		 999 }
1000
1001 /* restore dap registers */
151798f8
WS		 1002 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
1003 snd_soc_write(codec, reg, cache[reg]);
9b34e6cc
ZZ		 1004
1005 /*
bb362e2e
ZZ		 1006 * restore these regs according to the power setting sequence in
1007 * sgtl5000_set_power_regs() and clock setting sequence in
1008 * sgtl5000_set_clock().
1009 *
1010 * The order of restore is:
1011 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
1012 * SGTL5000_CHIP_ANA_POWER PLL bits set
1013 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
1014 * SGTL5000_CHIP_ANA_POWER LINREG_D restored
1015 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
1016 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
9b34e6cc
ZZ		 1017 */
1018 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
151798f8 1019 cache[SGTL5000_CHIP_LINREG_CTRL]);
9b34e6cc
ZZ		 1020
1021 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
151798f8 1022 cache[SGTL5000_CHIP_ANA_POWER]);
9b34e6cc
ZZ		 1023
1024 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
151798f8 1025 cache[SGTL5000_CHIP_CLK_CTRL]);
9b34e6cc
ZZ		 1026
1027 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
151798f8 1028 cache[SGTL5000_CHIP_REF_CTRL]);
9b34e6cc
ZZ		 1029
1030 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
151798f8 1031 cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
9b34e6cc
ZZ		 1032 return 0;
1033}
1034
1035static int sgtl5000_resume(struct snd_soc_codec *codec)
1036{
1037 /* Bring the codec back up to standby to enable regulators */
1038 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1039
1040 /* Restore registers by cached in memory */
1041 sgtl5000_restore_regs(codec);
1042 return 0;
1043}
1044#else
1045#define sgtl5000_suspend NULL
1046#define sgtl5000_resume NULL
1047#endif /* CONFIG_SUSPEND */
1048
1049/*
1050 * sgtl5000 has 3 internal power supplies:
1051 * 1. VAG, normally set to vdda/2
1052 * 2. chargepump, set to different value
1053 * according to voltage of vdda and vddio
1054 * 3. line out VAG, normally set to vddio/2
1055 *
1056 * and should be set according to:
1057 * 1. vddd provided by external or not
1058 * 2. vdda and vddio voltage value. > 3.1v or not
1059 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1060 */
1061static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1062{
1063 int vddd;
1064 int vdda;
1065 int vddio;
1066 u16 ana_pwr;
1067 u16 lreg_ctrl;
1068 int vag;
1069 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1070
1071 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1072 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1073 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1074
1075 vdda = vdda / 1000;
1076 vddio = vddio / 1000;
1077 vddd = vddd / 1000;
1078
1079 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1080 dev_err(codec->dev, "regulator voltage not set correctly\n");
1081
1082 return -EINVAL;
1083 }
1084
1085 /* according to datasheet, maximum voltage of supplies */
1086 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1087 dev_err(codec->dev,
cf1ee98d 1088 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
9b34e6cc
ZZ		 1089 vdda, vddio, vddd);
1090
1091 return -EINVAL;
1092 }
1093
1094 /* reset value */
1095 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1096 ana_pwr |= SGTL5000_DAC_STEREO |
1097 SGTL5000_ADC_STEREO |
1098 SGTL5000_REFTOP_POWERUP;
1099 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1100
1101 if (vddio < 3100 && vdda < 3100) {
1102 /* enable internal oscillator used for charge pump */
1103 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1104 SGTL5000_INT_OSC_EN,
1105 SGTL5000_INT_OSC_EN);
1106 /* Enable VDDC charge pump */
1107 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1108 } else if (vddio >= 3100 && vdda >= 3100) {
1109 /*
1110 * if vddio and vddd > 3.1v,
1111 * charge pump should be clean before set ana_pwr
1112 */
1113 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1114 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1115
1116 /* VDDC use VDDIO rail */
1117 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1118 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1119 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1120 }
1121
1122 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1123
1124 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1125
1126 /* set voltage to register */
1127 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 1128 SGTL5000_LINREG_VDDD_MASK, 0x8);
9b34e6cc
ZZ		 1129
1130 /*
1131 * if vddd linear reg has been enabled,
1132 * simple digital supply should be clear to get
1133 * proper VDDD voltage.
1134 */
1135 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1136 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1137 SGTL5000_LINREG_SIMPLE_POWERUP,
1138 0);
1139 else
1140 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1141 SGTL5000_LINREG_SIMPLE_POWERUP |
1142 SGTL5000_STARTUP_POWERUP,
1143 0);
1144
1145 /*
1146 * set ADC/DAC VAG to vdda / 2,
1147 * should stay in range (0.8v, 1.575v)
1148 */
1149 vag = vdda / 2;
1150 if (vag <= SGTL5000_ANA_GND_BASE)
1151 vag = 0;
1152 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1153 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1154 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1155 else
1156 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1157
1158 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
33cb92cf 1159 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
9b34e6cc
ZZ		 1160
1161 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1162 vag = vddio / 2;
1163 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1164 vag = 0;
1165 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1166 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1167 vag = SGTL5000_LINE_OUT_GND_MAX;
1168 else
1169 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1170 SGTL5000_LINE_OUT_GND_STP;
1171
1172 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
33cb92cf
AL		 1173 SGTL5000_LINE_OUT_CURRENT_MASK |
1174 SGTL5000_LINE_OUT_GND_MASK,
9b34e6cc
ZZ		 1175 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1176 SGTL5000_LINE_OUT_CURRENT_360u <<
1177 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1178
1179 return 0;
1180}
1181
e94a4062
WS		 1182static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1183{
1184 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1185 int ret;
1186
1187 /* set internal ldo to 1.2v */
1188 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1189 if (ret) {
1190 dev_err(codec->dev,
1191 "Failed to register vddd internal supplies: %d\n", ret);
1192 return ret;
1193 }
1194
1195 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1196
1197 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1198 sgtl5000->supplies);
1199
1200 if (ret) {
1201 ldo_regulator_remove(codec);
1202 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1203 return ret;
1204 }
1205
1206 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1207 return 0;
1208}
1209
9b34e6cc
ZZ		 1210static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1211{
1212 u16 reg;
1213 int ret;
1214 int rev;
1215 int i;
1216 int external_vddd = 0;
1217 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1218
1219 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1220 sgtl5000->supplies[i].supply = supply_names[i];
1221
1222 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1223 sgtl5000->supplies);
1224 if (!ret)
1225 external_vddd = 1;
1226 else {
e94a4062
WS		 1227 ret = sgtl5000_replace_vddd_with_ldo(codec);
1228 if (ret)
9b34e6cc 1229 return ret;
9b34e6cc
ZZ		 1230 }
1231
1232 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1233 sgtl5000->supplies);
1234 if (ret)
1235 goto err_regulator_free;
1236
1237 /* wait for all power rails bring up */
1238 udelay(10);
1239
1240 /* read chip information */
1241 reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
1242 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1243 SGTL5000_PARTID_PART_ID) {
1244 dev_err(codec->dev,
1245 "Device with ID register %x is not a sgtl5000\n", reg);
1246 ret = -ENODEV;
1247 goto err_regulator_disable;
1248 }
1249
1250 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1251 dev_info(codec->dev, "sgtl5000 revision %d\n", rev);
1252
1253 /*
1254 * workaround for revision 0x11 and later,
1255 * roll back to use internal LDO
1256 */
1257 if (external_vddd && rev >= 0x11) {
9b34e6cc
ZZ		 1258 /* disable all regulator first */
1259 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1260 sgtl5000->supplies);
1261 /* free VDDD regulator */
1262 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1263 sgtl5000->supplies);
1264
e94a4062 1265 ret = sgtl5000_replace_vddd_with_ldo(codec);
9b34e6cc
ZZ		 1266 if (ret)
1267 return ret;
1268
9b34e6cc
ZZ		 1269 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1270 sgtl5000->supplies);
1271 if (ret)
1272 goto err_regulator_free;
1273
1274 /* wait for all power rails bring up */
1275 udelay(10);
1276 }
1277
1278 return 0;
1279
1280err_regulator_disable:
1281 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1282 sgtl5000->supplies);
1283err_regulator_free:
1284 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1285 sgtl5000->supplies);
1286 if (external_vddd)
1287 ldo_regulator_remove(codec);
1288 return ret;
1289
1290}
1291
1292static int sgtl5000_probe(struct snd_soc_codec *codec)
1293{
1294 int ret;
1295 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1296
1297 /* setup i2c data ops */
1298 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
1299 if (ret < 0) {
1300 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1301 return ret;
1302 }
1303
1304 ret = sgtl5000_enable_regulators(codec);
1305 if (ret)
1306 return ret;
1307
1308 /* power up sgtl5000 */
1309 ret = sgtl5000_set_power_regs(codec);
1310 if (ret)
1311 goto err;
1312
1313 /* enable small pop, introduce 400ms delay in turning off */
1314 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1315 SGTL5000_SMALL_POP,
1316 SGTL5000_SMALL_POP);
1317
1318 /* disable short cut detector */
1319 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1320
1321 /*
1322 * set i2s as default input of sound switch
1323 * TODO: add sound switch to control and dapm widge.
1324 */
1325 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1326 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1327 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1328 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1329
1330 /* enable dac volume ramp by default */
1331 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1332 SGTL5000_DAC_VOL_RAMP_EN |
1333 SGTL5000_DAC_MUTE_RIGHT |
1334 SGTL5000_DAC_MUTE_LEFT);
1335
1336 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1337
1338 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1339 SGTL5000_HP_ZCD_EN |
1340 SGTL5000_ADC_ZCD_EN);
1341
1342 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0);
1343
1344 /*
1345 * disable DAP
1346 * TODO:
1347 * Enable DAP in kcontrol and dapm.
1348 */
1349 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1350
1351 /* leading to standby state */
1352 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1353 if (ret)
1354 goto err;
1355
1356 snd_soc_add_controls(codec, sgtl5000_snd_controls,
1357 ARRAY_SIZE(sgtl5000_snd_controls));
1358
1359 snd_soc_dapm_new_controls(&codec->dapm, sgtl5000_dapm_widgets,
1360 ARRAY_SIZE(sgtl5000_dapm_widgets));
1361
1362 snd_soc_dapm_add_routes(&codec->dapm, audio_map,
1363 ARRAY_SIZE(audio_map));
1364
1365 snd_soc_dapm_new_widgets(&codec->dapm);
1366
1367 return 0;
1368
1369err:
1370 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1371 sgtl5000->supplies);
1372 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1373 sgtl5000->supplies);
1374 ldo_regulator_remove(codec);
1375
1376 return ret;
1377}
1378
1379static int sgtl5000_remove(struct snd_soc_codec *codec)
1380{
1381 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1382
1383 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1384
1385 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1386 sgtl5000->supplies);
1387 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1388 sgtl5000->supplies);
1389 ldo_regulator_remove(codec);
1390
1391 return 0;
1392}
1393
61a142b7 1394static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1395 .probe = sgtl5000_probe,
1396 .remove = sgtl5000_remove,
1397 .suspend = sgtl5000_suspend,
1398 .resume = sgtl5000_resume,
1399 .set_bias_level = sgtl5000_set_bias_level,
1400 .reg_cache_size = ARRAY_SIZE(sgtl5000_regs),
1401 .reg_word_size = sizeof(u16),
1402 .reg_cache_step = 2,
1403 .reg_cache_default = sgtl5000_regs,
1404 .volatile_register = sgtl5000_volatile_register,
1405};
1406
1407static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
1408 const struct i2c_device_id *id)
1409{
1410 struct sgtl5000_priv *sgtl5000;
1411 int ret;
1412
512fa7c4
FE		 1413 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
1414 GFP_KERNEL);
9b34e6cc
ZZ		 1415 if (!sgtl5000)
1416 return -ENOMEM;
1417
9b34e6cc
ZZ		 1418 i2c_set_clientdata(client, sgtl5000);
1419
1420 ret = snd_soc_register_codec(&client->dev,
1421 &sgtl5000_driver, &sgtl5000_dai, 1);
512fa7c4 1422 return ret;
9b34e6cc
ZZ		 1423}
1424
1425static __devexit int sgtl5000_i2c_remove(struct i2c_client *client)
1426{
9b34e6cc
ZZ		 1427 snd_soc_unregister_codec(&client->dev);
1428
9b34e6cc
ZZ		 1429 return 0;
1430}
1431
1432static const struct i2c_device_id sgtl5000_id[] = {
1433 {"sgtl5000", 0},
1434 {},
1435};
1436
1437MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1438
58e49424
SG		 1439static const struct of_device_id sgtl5000_dt_ids[] = {
1440 { .compatible = "fsl,sgtl5000", },
1441 { /* sentinel */ }
1442};
4c54c6de 1443MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1444
9b34e6cc
ZZ		 1445static struct i2c_driver sgtl5000_i2c_driver = {
1446 .driver = {
1447 .name = "sgtl5000",
1448 .owner = THIS_MODULE,
58e49424 1449 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1450 },
1451 .probe = sgtl5000_i2c_probe,
1452 .remove = __devexit_p(sgtl5000_i2c_remove),
1453 .id_table = sgtl5000_id,
1454};
1455
1456static int __init sgtl5000_modinit(void)
1457{
1458 return i2c_add_driver(&sgtl5000_i2c_driver);
1459}
1460module_init(sgtl5000_modinit);
1461
1462static void __exit sgtl5000_exit(void)
1463{
1464 i2c_del_driver(&sgtl5000_i2c_driver);
1465}
1466module_exit(sgtl5000_exit);
1467
1468MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
f7cb8a4b 1469MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
9b34e6cc 1470MODULE_LICENSE("GPL");
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