]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - sound/soc/codecs/sgtl5000.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / sgtl5000.c
CommitLineData
9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
bd0593f5 19#include <linux/log2.h>
e5d80e82 20#include <linux/regmap.h>
9b34e6cc
ZZ		 21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/regulator/consumer.h>
58e49424 24#include <linux/of_device.h>
9b34e6cc
ZZ		 25#include <sound/core.h>
26#include <sound/tlv.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
9b34e6cc
ZZ		 32
33#include "sgtl5000.h"
34
35#define SGTL5000_DAP_REG_OFFSET 0x0100
36#define SGTL5000_MAX_REG_OFFSET 0x013A
37
3a478877
OS		 38/* Delay for the VAG ramp up */
39#define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */
40/* Delay for the VAG ramp down */
41#define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
42
43#define SGTL5000_OUTPUTS_MUTE (SGTL5000_HP_MUTE | SGTL5000_LINE_OUT_MUTE)
44
151798f8 45/* default value of sgtl5000 registers */
e5d80e82 46static const struct reg_default sgtl5000_reg_defaults[] = {
29aa37cd 47 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
e5d80e82 48 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
016fcab8 49 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
29aa37cd 50 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
e5d80e82
FE		 51 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
52 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
29aa37cd 53 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
e5d80e82
FE		 54 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
55 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
29aa37cd
FE		 56 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
57 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
58 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
e5d80e82 59 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
e5d80e82 60 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
29aa37cd
FE		 61 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
62 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
63 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
64 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
65 { SGTL5000_DAP_CTRL, 0x0000 },
66 { SGTL5000_DAP_PEQ, 0x0000 },
e5d80e82
FE		 67 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
68 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
29aa37cd 69 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
e5d80e82
FE		 70 { SGTL5000_DAP_SURROUND, 0x0040 },
71 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
72 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
73 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
74 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
75 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
76 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
29aa37cd 77 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
e5d80e82
FE		 78 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
79 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
80 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
81 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
9b34e6cc
ZZ		 82};
83
a7295267
RL		 84/* AVC: Threshold dB -> register: pre-calculated values */
85static const u16 avc_thr_db2reg[97] = {
86 0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068,
87 0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F,
88 0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414,
89 0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172,
90 0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083,
91 0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E,
92 0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010,
93 0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005,
94 0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002,
95 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
97
9b34e6cc
ZZ		 98/* regulator supplies for sgtl5000, VDDD is an optional external supply */
99enum sgtl5000_regulator_supplies {
100 VDDA,
101 VDDIO,
102 VDDD,
103 SGTL5000_SUPPLY_NUM
104};
105
106/* vddd is optional supply */
107static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
108 "VDDA",
109 "VDDIO",
110 "VDDD"
111};
112
9b34e6cc 113#define LDO_VOLTAGE 1200000
3d632cc8 114#define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
9b34e6cc 115
bd0593f5
JMH		 116enum sgtl5000_micbias_resistor {
117 SGTL5000_MICBIAS_OFF = 0,
118 SGTL5000_MICBIAS_2K = 2,
119 SGTL5000_MICBIAS_4K = 4,
120 SGTL5000_MICBIAS_8K = 8,
121};
122
570c70a6
FE		 123enum {
124 I2S_LRCLK_STRENGTH_DISABLE,
125 I2S_LRCLK_STRENGTH_LOW,
126 I2S_LRCLK_STRENGTH_MEDIUM,
127 I2S_LRCLK_STRENGTH_HIGH,
128};
129
3a478877
OS		 130enum {
131 HP_POWER_EVENT,
132 DAC_POWER_EVENT,
133 ADC_POWER_EVENT,
134 LAST_POWER_EVENT = ADC_POWER_EVENT
135};
136
9b34e6cc
ZZ		 137/* sgtl5000 private structure in codec */
138struct sgtl5000_priv {
139 int sysclk; /* sysclk rate */
140 int master; /* i2s master or not */
141 int fmt; /* i2s data format */
142 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
940adb28 143 int num_supplies;
e5d80e82 144 struct regmap *regmap;
9e13f345 145 struct clk *mclk;
252e91ff 146 int revision;
bd0593f5 147 u8 micbias_resistor;
87357797 148 u8 micbias_voltage;
570c70a6 149 u8 lrclk_strength;
3a478877 150 u16 mute_state[LAST_POWER_EVENT + 1];
9b34e6cc
ZZ		 151};
152
3a478877
OS		 153static inline int hp_sel_input(struct snd_soc_component *component)
154{
155 unsigned int ana_reg = 0;
156
157 snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL, &ana_reg);
158
159 return (ana_reg & SGTL5000_HP_SEL_MASK) >> SGTL5000_HP_SEL_SHIFT;
160}
161
162static inline u16 mute_output(struct snd_soc_component *component,
163 u16 mute_mask)
164{
165 unsigned int mute_reg = 0;
166
167 snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL, &mute_reg);
168
169 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
170 mute_mask, mute_mask);
171 return mute_reg;
172}
173
174static inline void restore_output(struct snd_soc_component *component,
175 u16 mute_mask, u16 mute_reg)
176{
177 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
178 mute_mask, mute_reg);
179}
180
181static void vag_power_on(struct snd_soc_component *component, u32 source)
182{
183 unsigned int ana_reg = 0;
184
185 snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER, &ana_reg);
186
187 if (ana_reg & SGTL5000_VAG_POWERUP)
188 return;
189
190 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
191 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
192
193 /* When VAG powering on to get local loop from Line-In, the sleep
194 * is required to avoid loud pop.
195 */
196 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN &&
197 source == HP_POWER_EVENT)
198 msleep(SGTL5000_VAG_POWERUP_DELAY);
199}
200
201static int vag_power_consumers(struct snd_soc_component *component,
202 u16 ana_pwr_reg, u32 source)
203{
204 int consumers = 0;
205
206 /* count dac/adc consumers unconditional */
207 if (ana_pwr_reg & SGTL5000_DAC_POWERUP)
208 consumers++;
209 if (ana_pwr_reg & SGTL5000_ADC_POWERUP)
210 consumers++;
211
212 /*
213 * If the event comes from HP and Line-In is selected,
214 * current action is 'DAC to be powered down'.
215 * As HP_POWERUP is not set when HP muxed to line-in,
216 * we need to keep VAG power ON.
217 */
218 if (source == HP_POWER_EVENT) {
219 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN)
220 consumers++;
221 } else {
222 if (ana_pwr_reg & SGTL5000_HP_POWERUP)
223 consumers++;
224 }
225
226 return consumers;
227}
228
229static void vag_power_off(struct snd_soc_component *component, u32 source)
230{
231 unsigned int ana_pwr = SGTL5000_VAG_POWERUP;
232
233 snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER, &ana_pwr);
234
235 if (!(ana_pwr & SGTL5000_VAG_POWERUP))
236 return;
237
238 /*
239 * This function calls when any of VAG power consumers is disappearing.
240 * Thus, if there is more than one consumer at the moment, as minimum
241 * one consumer will definitely stay after the end of the current
242 * event.
243 * Don't clear VAG_POWERUP if 2 or more consumers of VAG present:
244 * - LINE_IN (for HP events) / HP (for DAC/ADC events)
245 * - DAC
246 * - ADC
247 * (the current consumer is disappearing right now)
248 */
249 if (vag_power_consumers(component, ana_pwr, source) >= 2)
250 return;
251
252 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
253 SGTL5000_VAG_POWERUP, 0);
254 /* In power down case, we need wait 400-1000 ms
255 * when VAG fully ramped down.
256 * As longer we wait, as smaller pop we've got.
257 */
258 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
259}
260
9b34e6cc
ZZ		 261/*
262 * mic_bias power on/off share the same register bits with
263 * output impedance of mic bias, when power on mic bias, we
264 * need reclaim it to impedance value.
265 * 0x0 = Powered off
266 * 0x1 = 2Kohm
267 * 0x2 = 4Kohm
268 * 0x3 = 8Kohm
269 */
270static int mic_bias_event(struct snd_soc_dapm_widget *w,
271 struct snd_kcontrol *kcontrol, int event)
272{
73bffd17
LPC		 273 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
274 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
bd0593f5 275
9b34e6cc
ZZ		 276 switch (event) {
277 case SND_SOC_DAPM_POST_PMU:
bd0593f5 278 /* change mic bias resistor */
73bffd17 279 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
bd0593f5
JMH		 280 SGTL5000_BIAS_R_MASK,
281 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 282 break;
283
284 case SND_SOC_DAPM_PRE_PMD:
73bffd17 285 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 286 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 287 break;
288 }
289 return 0;
290}
291
3a478877
OS		 292static int vag_and_mute_control(struct snd_soc_component *component,
293 int event, int event_source)
9b34e6cc 294{
3a478877
OS		 295 static const u16 mute_mask[] = {
296 /*
297 * Mask for HP_POWER_EVENT.
298 * Muxing Headphones have to be wrapped with mute/unmute
299 * headphones only.
300 */
301 SGTL5000_HP_MUTE,
302 /*
303 * Masks for DAC_POWER_EVENT/ADC_POWER_EVENT.
304 * Muxing DAC or ADC block have to be wrapped with mute/unmute
305 * both headphones and line-out.
306 */
307 SGTL5000_OUTPUTS_MUTE,
308 SGTL5000_OUTPUTS_MUTE
309 };
310
311 struct sgtl5000_priv *sgtl5000 =
312 snd_soc_component_get_drvdata(component);
f091f3f0 313
9b34e6cc 314 switch (event) {
3a478877
OS		 315 case SND_SOC_DAPM_PRE_PMU:
316 sgtl5000->mute_state[event_source] =
317 mute_output(component, mute_mask[event_source]);
318 break;
dd4d2d6d 319 case SND_SOC_DAPM_POST_PMU:
3a478877
OS		 320 vag_power_on(component, event_source);
321 restore_output(component, mute_mask[event_source],
322 sgtl5000->mute_state[event_source]);
9b34e6cc 323 break;
dd4d2d6d 324 case SND_SOC_DAPM_PRE_PMD:
3a478877
OS		 325 sgtl5000->mute_state[event_source] =
326 mute_output(component, mute_mask[event_source]);
327 vag_power_off(component, event_source);
328 break;
329 case SND_SOC_DAPM_POST_PMD:
330 restore_output(component, mute_mask[event_source],
331 sgtl5000->mute_state[event_source]);
9b34e6cc
ZZ		 332 break;
333 default:
334 break;
335 }
336
337 return 0;
338}
339
3a478877
OS		 340/*
341 * Mute Headphone when power it up/down.
342 * Control VAG power on HP power path.
343 */
344static int headphone_pga_event(struct snd_soc_dapm_widget *w,
345 struct snd_kcontrol *kcontrol, int event)
346{
347 struct snd_soc_component *component =
348 snd_soc_dapm_to_component(w->dapm);
349
350 return vag_and_mute_control(component, event, HP_POWER_EVENT);
351}
352
353/* As manual describes, ADC/DAC powering up/down requires
354 * to mute outputs to avoid pops.
355 * Control VAG power on ADC/DAC power path.
356 */
357static int adc_updown_depop(struct snd_soc_dapm_widget *w,
358 struct snd_kcontrol *kcontrol, int event)
359{
360 struct snd_soc_component *component =
361 snd_soc_dapm_to_component(w->dapm);
362
363 return vag_and_mute_control(component, event, ADC_POWER_EVENT);
364}
365
366static int dac_updown_depop(struct snd_soc_dapm_widget *w,
367 struct snd_kcontrol *kcontrol, int event)
368{
369 struct snd_soc_component *component =
370 snd_soc_dapm_to_component(w->dapm);
371
372 return vag_and_mute_control(component, event, DAC_POWER_EVENT);
373}
374
9b34e6cc
ZZ		 375/* input sources for ADC */
376static const char *adc_mux_text[] = {
377 "MIC_IN", "LINE_IN"
378};
379
c8ed6504
TI		 380static SOC_ENUM_SINGLE_DECL(adc_enum,
381 SGTL5000_CHIP_ANA_CTRL, 2,
382 adc_mux_text);
9b34e6cc
ZZ		 383
384static const struct snd_kcontrol_new adc_mux =
385SOC_DAPM_ENUM("Capture Mux", adc_enum);
386
387/* input sources for DAC */
388static const char *dac_mux_text[] = {
389 "DAC", "LINE_IN"
390};
391
c8ed6504
TI		 392static SOC_ENUM_SINGLE_DECL(dac_enum,
393 SGTL5000_CHIP_ANA_CTRL, 6,
394 dac_mux_text);
9b34e6cc
ZZ		 395
396static const struct snd_kcontrol_new dac_mux =
397SOC_DAPM_ENUM("Headphone Mux", dac_enum);
398
399static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
400 SND_SOC_DAPM_INPUT("LINE_IN"),
401 SND_SOC_DAPM_INPUT("MIC_IN"),
402
403 SND_SOC_DAPM_OUTPUT("HP_OUT"),
404 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
405
8fc8ec92
MB		 406 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
407 mic_bias_event,
408 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9b34e6cc 409
3a478877
OS		 410 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
411 headphone_pga_event,
412 SND_SOC_DAPM_PRE_POST_PMU |
413 SND_SOC_DAPM_PRE_POST_PMD),
f0cdcf3a 414 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
9b34e6cc
ZZ		 415
416 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
417 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
418
419 /* aif for i2s input */
420 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
421 0, SGTL5000_CHIP_DIG_POWER,
422 0, 0),
423
424 /* aif for i2s output */
425 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
426 0, SGTL5000_CHIP_DIG_POWER,
427 1, 0),
428
3a478877
OS		 429 SND_SOC_DAPM_ADC_E("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0,
430 adc_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
431 SND_SOC_DAPM_PRE_POST_PMD),
432 SND_SOC_DAPM_DAC_E("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0,
433 dac_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
434 SND_SOC_DAPM_PRE_POST_PMD),
9b34e6cc
ZZ		 435};
436
437/* routes for sgtl5000 */
89989637 438static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
9b34e6cc
ZZ		 439 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
440 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
441
442 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
443 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
444
445 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
446 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
447 {"LO", NULL, "DAC"}, /* dac --> line_out */
448
449 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
450 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
451
452 {"LINE_OUT", NULL, "LO"},
453 {"HP_OUT", NULL, "HP"},
454};
455
456/* custom function to fetch info of PCM playback volume */
457static int dac_info_volsw(struct snd_kcontrol *kcontrol,
458 struct snd_ctl_elem_info *uinfo)
459{
460 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
461 uinfo->count = 2;
462 uinfo->value.integer.min = 0;
463 uinfo->value.integer.max = 0xfc - 0x3c;
464 return 0;
465}
466
467/*
468 * custom function to get of PCM playback volume
469 *
470 * dac volume register
471 * 15-------------8-7--------------0
472 * | R channel vol | L channel vol |
473 * -------------------------------
474 *
475 * PCM volume with 0.5017 dB steps from 0 to -90 dB
476 *
477 * register values map to dB
478 * 0x3B and less = Reserved
479 * 0x3C = 0 dB
480 * 0x3D = -0.5 dB
481 * 0xF0 = -90 dB
482 * 0xFC and greater = Muted
483 *
484 * register value map to userspace value
485 *
486 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
487 * ------------------------------
488 * userspace value 0xc0 0
489 */
490static int dac_get_volsw(struct snd_kcontrol *kcontrol,
491 struct snd_ctl_elem_value *ucontrol)
492{
ea53bf77 493 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 494 int reg;
495 int l;
496 int r;
497
498 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
499
500 /* get left channel volume */
501 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
502
503 /* get right channel volume */
504 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
505
506 /* make sure value fall in (0x3c,0xfc) */
507 l = clamp(l, 0x3c, 0xfc);
508 r = clamp(r, 0x3c, 0xfc);
509
510 /* invert it and map to userspace value */
511 l = 0xfc - l;
512 r = 0xfc - r;
513
514 ucontrol->value.integer.value[0] = l;
515 ucontrol->value.integer.value[1] = r;
516
517 return 0;
518}
519
520/*
521 * custom function to put of PCM playback volume
522 *
523 * dac volume register
524 * 15-------------8-7--------------0
525 * | R channel vol | L channel vol |
526 * -------------------------------
527 *
528 * PCM volume with 0.5017 dB steps from 0 to -90 dB
529 *
530 * register values map to dB
531 * 0x3B and less = Reserved
532 * 0x3C = 0 dB
533 * 0x3D = -0.5 dB
534 * 0xF0 = -90 dB
535 * 0xFC and greater = Muted
536 *
537 * userspace value map to register value
538 *
539 * userspace value 0xc0 0
540 * ------------------------------
541 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
542 */
543static int dac_put_volsw(struct snd_kcontrol *kcontrol,
544 struct snd_ctl_elem_value *ucontrol)
545{
ea53bf77 546 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 547 int reg;
548 int l;
549 int r;
550
551 l = ucontrol->value.integer.value[0];
552 r = ucontrol->value.integer.value[1];
553
554 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
555 l = clamp(l, 0, 0xfc - 0x3c);
556 r = clamp(r, 0, 0xfc - 0x3c);
557
558 /* invert it, get the value can be set to register */
559 l = 0xfc - l;
560 r = 0xfc - r;
561
562 /* shift to get the register value */
563 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
564 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
565
566 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
567
568 return 0;
569}
570
a7295267
RL		 571/*
572 * custom function to get AVC threshold
573 *
574 * The threshold dB is calculated by rearranging the calculation from the
575 * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
576 * dB = ( fls(register_value) - 14.347 ) * 6.02
577 *
578 * As this calculation is expensive and the threshold dB values may not exeed
579 * 0 to 96 we use pre-calculated values.
580 */
581static int avc_get_threshold(struct snd_kcontrol *kcontrol,
582 struct snd_ctl_elem_value *ucontrol)
583{
364e93ca 584 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
a7295267
RL		 585 int db, i;
586 u16 reg = snd_soc_read(codec, SGTL5000_DAP_AVC_THRESHOLD);
587
588 /* register value 0 => -96dB */
589 if (!reg) {
590 ucontrol->value.integer.value[0] = 96;
591 ucontrol->value.integer.value[1] = 96;
592 return 0;
593 }
594
595 /* get dB from register value (rounded down) */
596 for (i = 0; avc_thr_db2reg[i] > reg; i++)
597 ;
598 db = i;
599
600 ucontrol->value.integer.value[0] = db;
601 ucontrol->value.integer.value[1] = db;
602
603 return 0;
604}
605
606/*
607 * custom function to put AVC threshold
608 *
609 * The register value is calculated by following formula:
610 * register_value = 10^(dB/20) * 0.636 * 2^15
611 * As this calculation is expensive and the threshold dB values may not exeed
612 * 0 to 96 we use pre-calculated values.
613 */
614static int avc_put_threshold(struct snd_kcontrol *kcontrol,
615 struct snd_ctl_elem_value *ucontrol)
616{
364e93ca 617 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
a7295267
RL		 618 int db;
619 u16 reg;
620
621 db = (int)ucontrol->value.integer.value[0];
622 if (db < 0 || db > 96)
623 return -EINVAL;
624 reg = avc_thr_db2reg[db];
625 snd_soc_write(codec, SGTL5000_DAP_AVC_THRESHOLD, reg);
626
627 return 0;
628}
629
9b34e6cc
ZZ		 630static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
631
632/* tlv for mic gain, 0db 20db 30db 40db */
53eb1ca3 633static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
9b34e6cc 634 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
53eb1ca3
LPC		 635 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
636);
9b34e6cc
ZZ		 637
638/* tlv for hp volume, -51.5db to 12.0db, step .5db */
639static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
640
0593d461
KK		 641/* tlv for lineout volume, 31 steps of .5db each */
642static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
643
a7295267
RL		 644/* tlv for dap avc max gain, 0db, 6db, 12db */
645static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0);
646
647/* tlv for dap avc threshold, */
648static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600);
649
9b34e6cc
ZZ		 650static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
651 /* SOC_DOUBLE_S8_TLV with invert */
652 {
653 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
654 .name = "PCM Playback Volume",
655 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
656 SNDRV_CTL_ELEM_ACCESS_READWRITE,
657 .info = dac_info_volsw,
658 .get = dac_get_volsw,
659 .put = dac_put_volsw,
660 },
661
662 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
663 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
664 SGTL5000_CHIP_ANA_ADC_CTRL,
65f2b226 665 8, 1, 0, capture_6db_attenuate),
9b34e6cc
ZZ		 666 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
667
668 SOC_DOUBLE_TLV("Headphone Playback Volume",
669 SGTL5000_CHIP_ANA_HP_CTRL,
670 0, 8,
671 0x7f, 1,
672 headphone_volume),
904a9873
RL		 673 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
674 4, 1, 1),
9b34e6cc
ZZ		 675 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
676 5, 1, 0),
677
678 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
b50684da 679 0, 3, 0, mic_gain_tlv),
0593d461
KK		 680
681 SOC_DOUBLE_TLV("Lineout Playback Volume",
682 SGTL5000_CHIP_LINE_OUT_VOL,
683 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
684 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
685 0x1f, 1,
686 lineout_volume),
904a9873 687 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
a7295267
RL		 688
689 /* Automatic Volume Control (DAP AVC) */
690 SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0),
691 SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0),
692 SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
693 avc_max_gain),
694 SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0),
695 SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD,
696 0, 96, 0, avc_get_threshold, avc_put_threshold,
697 avc_threshold),
9b34e6cc
ZZ		 698};
699
700/* mute the codec used by alsa core */
701static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
702{
703 struct snd_soc_codec *codec = codec_dai->codec;
704 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
705
706 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
707 adcdac_ctrl, mute ? adcdac_ctrl : 0);
708
709 return 0;
710}
711
712/* set codec format */
713static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
714{
715 struct snd_soc_codec *codec = codec_dai->codec;
716 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
717 u16 i2sctl = 0;
718
719 sgtl5000->master = 0;
720 /*
721 * i2s clock and frame master setting.
722 * ONLY support:
723 * - clock and frame slave,
724 * - clock and frame master
725 */
726 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
727 case SND_SOC_DAIFMT_CBS_CFS:
728 break;
729 case SND_SOC_DAIFMT_CBM_CFM:
730 i2sctl |= SGTL5000_I2S_MASTER;
731 sgtl5000->master = 1;
732 break;
733 default:
734 return -EINVAL;
735 }
736
737 /* setting i2s data format */
738 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
739 case SND_SOC_DAIFMT_DSP_A:
9ee802ec 740 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 741 break;
742 case SND_SOC_DAIFMT_DSP_B:
9ee802ec 743 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 744 i2sctl |= SGTL5000_I2S_LRALIGN;
745 break;
746 case SND_SOC_DAIFMT_I2S:
9ee802ec 747 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 748 break;
749 case SND_SOC_DAIFMT_RIGHT_J:
9ee802ec 750 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 751 i2sctl |= SGTL5000_I2S_LRPOL;
752 break;
753 case SND_SOC_DAIFMT_LEFT_J:
9ee802ec 754 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 755 i2sctl |= SGTL5000_I2S_LRALIGN;
756 break;
757 default:
758 return -EINVAL;
759 }
760
761 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
762
763 /* Clock inversion */
764 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
765 case SND_SOC_DAIFMT_NB_NF:
766 break;
767 case SND_SOC_DAIFMT_IB_NF:
768 i2sctl |= SGTL5000_I2S_SCLK_INV;
769 break;
770 default:
771 return -EINVAL;
772 }
773
774 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
775
776 return 0;
777}
778
779/* set codec sysclk */
780static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
781 int clk_id, unsigned int freq, int dir)
782{
783 struct snd_soc_codec *codec = codec_dai->codec;
784 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
785
786 switch (clk_id) {
787 case SGTL5000_SYSCLK:
788 sgtl5000->sysclk = freq;
789 break;
790 default:
791 return -EINVAL;
792 }
793
794 return 0;
795}
796
797/*
798 * set clock according to i2s frame clock,
7f6d75d7
FE		 799 * sgtl5000 provides 2 clock sources:
800 * 1. sys_mclk: sample freq can only be configured to
9b34e6cc 801 * 1/256, 1/384, 1/512 of sys_mclk.
7f6d75d7 802 * 2. pll: can derive any audio clocks.
9b34e6cc
ZZ		 803 *
804 * clock setting rules:
7f6d75d7
FE		 805 * 1. in slave mode, only sys_mclk can be used
806 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
807 * and above.
808 * 3. usage of sys_mclk is preferred over pll to save power.
9b34e6cc
ZZ		 809 */
810static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
811{
812 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
813 int clk_ctl = 0;
814 int sys_fs; /* sample freq */
815
816 /*
817 * sample freq should be divided by frame clock,
7f6d75d7
FE		 818 * if frame clock is lower than 44.1 kHz, sample freq should be set to
819 * 32 kHz or 44.1 kHz.
9b34e6cc
ZZ		 820 */
821 switch (frame_rate) {
822 case 8000:
823 case 16000:
824 sys_fs = 32000;
825 break;
826 case 11025:
827 case 22050:
828 sys_fs = 44100;
829 break;
830 default:
831 sys_fs = frame_rate;
832 break;
833 }
834
835 /* set divided factor of frame clock */
836 switch (sys_fs / frame_rate) {
837 case 4:
838 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
839 break;
840 case 2:
841 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
842 break;
843 case 1:
844 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
845 break;
846 default:
847 return -EINVAL;
848 }
849
850 /* set the sys_fs according to frame rate */
851 switch (sys_fs) {
852 case 32000:
853 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
854 break;
855 case 44100:
856 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
857 break;
858 case 48000:
859 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
860 break;
861 case 96000:
862 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
863 break;
864 default:
865 dev_err(codec->dev, "frame rate %d not supported\n",
866 frame_rate);
867 return -EINVAL;
868 }
869
870 /*
871 * calculate the divider of mclk/sample_freq,
7f6d75d7
FE		 872 * factor of freq = 96 kHz can only be 256, since mclk is in the range
873 * of 8 MHz - 27 MHz
9b34e6cc 874 */
2a4cfd10 875 switch (sgtl5000->sysclk / frame_rate) {
9b34e6cc
ZZ		 876 case 256:
877 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
878 SGTL5000_MCLK_FREQ_SHIFT;
879 break;
880 case 384:
881 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
882 SGTL5000_MCLK_FREQ_SHIFT;
883 break;
884 case 512:
885 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
886 SGTL5000_MCLK_FREQ_SHIFT;
887 break;
888 default:
7f6d75d7 889 /* if mclk does not satisfy the divider, use pll */
9b34e6cc
ZZ		 890 if (sgtl5000->master) {
891 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
892 SGTL5000_MCLK_FREQ_SHIFT;
893 } else {
894 dev_err(codec->dev,
895 "PLL not supported in slave mode\n");
fa558d01
FE		 896 dev_err(codec->dev, "%d ratio is not supported. "
897 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
2a4cfd10 898 sgtl5000->sysclk / frame_rate);
9b34e6cc
ZZ		 899 return -EINVAL;
900 }
901 }
902
903 /* if using pll, please check manual 6.4.2 for detail */
904 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
905 u64 out, t;
906 int div2;
907 int pll_ctl;
908 unsigned int in, int_div, frac_div;
909
910 if (sgtl5000->sysclk > 17000000) {
911 div2 = 1;
912 in = sgtl5000->sysclk / 2;
913 } else {
914 div2 = 0;
915 in = sgtl5000->sysclk;
916 }
917 if (sys_fs == 44100)
918 out = 180633600;
919 else
920 out = 196608000;
921 t = do_div(out, in);
922 int_div = out;
923 t *= 2048;
924 do_div(t, in);
925 frac_div = t;
926 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
927 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
928
929 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
930 if (div2)
931 snd_soc_update_bits(codec,
932 SGTL5000_CHIP_CLK_TOP_CTRL,
933 SGTL5000_INPUT_FREQ_DIV2,
934 SGTL5000_INPUT_FREQ_DIV2);
935 else
936 snd_soc_update_bits(codec,
937 SGTL5000_CHIP_CLK_TOP_CTRL,
938 SGTL5000_INPUT_FREQ_DIV2,
939 0);
940
941 /* power up pll */
942 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
943 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
944 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
e06e4c2d
OS		 945
946 /* if using pll, clk_ctrl must be set after pll power up */
947 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
9b34e6cc 948 } else {
e06e4c2d
OS		 949 /* otherwise, clk_ctrl must be set before pll power down */
950 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
951
9b34e6cc
ZZ		 952 /* power down pll */
953 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
954 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
955 0);
956 }
957
9b34e6cc
ZZ		 958 return 0;
959}
960
961/*
962 * Set PCM DAI bit size and sample rate.
963 * input: params_rate, params_fmt
964 */
965static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
966 struct snd_pcm_hw_params *params,
967 struct snd_soc_dai *dai)
968{
e6968a17 969 struct snd_soc_codec *codec = dai->codec;
9b34e6cc
ZZ		 970 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
971 int channels = params_channels(params);
972 int i2s_ctl = 0;
973 int stereo;
974 int ret;
975
976 /* sysclk should already set */
977 if (!sgtl5000->sysclk) {
978 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
979 return -EFAULT;
980 }
981
982 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
983 stereo = SGTL5000_DAC_STEREO;
984 else
985 stereo = SGTL5000_ADC_STEREO;
986
987 /* set mono to save power */
988 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
989 channels == 1 ? 0 : stereo);
990
991 /* set codec clock base on lrclk */
992 ret = sgtl5000_set_clock(codec, params_rate(params));
993 if (ret)
994 return ret;
995
996 /* set i2s data format */
dacc2aef
MB		 997 switch (params_width(params)) {
998 case 16:
9b34e6cc
ZZ		 999 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1000 return -EINVAL;
1001 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
1002 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
1003 SGTL5000_I2S_SCLKFREQ_SHIFT;
1004 break;
dacc2aef 1005 case 20:
9b34e6cc
ZZ		 1006 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
1007 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1008 SGTL5000_I2S_SCLKFREQ_SHIFT;
1009 break;
dacc2aef 1010 case 24:
9b34e6cc
ZZ		 1011 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
1012 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1013 SGTL5000_I2S_SCLKFREQ_SHIFT;
1014 break;
dacc2aef 1015 case 32:
9b34e6cc
ZZ		 1016 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1017 return -EINVAL;
1018 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
1019 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1020 SGTL5000_I2S_SCLKFREQ_SHIFT;
1021 break;
1022 default:
1023 return -EINVAL;
1024 }
1025
33cb92cf
AL		 1026 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
1027 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
1028 i2s_ctl);
9b34e6cc
ZZ		 1029
1030 return 0;
1031}
1032
9b34e6cc
ZZ		 1033/*
1034 * set dac bias
1035 * common state changes:
1036 * startup:
1037 * off --> standby --> prepare --> on
1038 * standby --> prepare --> on
1039 *
1040 * stop:
1041 * on --> prepare --> standby
1042 */
1043static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
1044 enum snd_soc_bias_level level)
1045{
7c248448
FE		 1046 struct sgtl5000_priv *sgtl = snd_soc_codec_get_drvdata(codec);
1047 int ret;
1048
9b34e6cc
ZZ		 1049 switch (level) {
1050 case SND_SOC_BIAS_ON:
1051 case SND_SOC_BIAS_PREPARE:
9b34e6cc 1052 case SND_SOC_BIAS_STANDBY:
7c248448
FE		 1053 regcache_cache_only(sgtl->regmap, false);
1054 ret = regcache_sync(sgtl->regmap);
1055 if (ret) {
1056 regcache_cache_only(sgtl->regmap, true);
1057 return ret;
1058 }
1059
8419caa7
EN		 1060 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1061 SGTL5000_REFTOP_POWERUP,
1062 SGTL5000_REFTOP_POWERUP);
9b34e6cc
ZZ		 1063 break;
1064 case SND_SOC_BIAS_OFF:
7c248448 1065 regcache_cache_only(sgtl->regmap, true);
8419caa7
EN		 1066 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1067 SGTL5000_REFTOP_POWERUP, 0);
9b34e6cc
ZZ		 1068 break;
1069 }
1070
9b34e6cc
ZZ		 1071 return 0;
1072}
1073
1074#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1075 SNDRV_PCM_FMTBIT_S20_3LE |\
1076 SNDRV_PCM_FMTBIT_S24_LE |\
1077 SNDRV_PCM_FMTBIT_S32_LE)
1078
85e7652d 1079static const struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 1080 .hw_params = sgtl5000_pcm_hw_params,
1081 .digital_mute = sgtl5000_digital_mute,
1082 .set_fmt = sgtl5000_set_dai_fmt,
1083 .set_sysclk = sgtl5000_set_dai_sysclk,
1084};
1085
1086static struct snd_soc_dai_driver sgtl5000_dai = {
1087 .name = "sgtl5000",
1088 .playback = {
1089 .stream_name = "Playback",
1090 .channels_min = 1,
1091 .channels_max = 2,
1092 /*
1093 * only support 8~48K + 96K,
1094 * TODO modify hw_param to support more
1095 */
1096 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1097 .formats = SGTL5000_FORMATS,
1098 },
1099 .capture = {
1100 .stream_name = "Capture",
1101 .channels_min = 1,
1102 .channels_max = 2,
1103 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1104 .formats = SGTL5000_FORMATS,
1105 },
1106 .ops = &sgtl5000_ops,
1107 .symmetric_rates = 1,
1108};
1109
e5d80e82 1110static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
9b34e6cc
ZZ		 1111{
1112 switch (reg) {
1113 case SGTL5000_CHIP_ID:
1114 case SGTL5000_CHIP_ADCDAC_CTRL:
1115 case SGTL5000_CHIP_ANA_STATUS:
e5d80e82 1116 return true;
9b34e6cc
ZZ		 1117 }
1118
e5d80e82
FE		 1119 return false;
1120}
1121
1122static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1123{
1124 switch (reg) {
1125 case SGTL5000_CHIP_ID:
1126 case SGTL5000_CHIP_DIG_POWER:
1127 case SGTL5000_CHIP_CLK_CTRL:
1128 case SGTL5000_CHIP_I2S_CTRL:
1129 case SGTL5000_CHIP_SSS_CTRL:
1130 case SGTL5000_CHIP_ADCDAC_CTRL:
1131 case SGTL5000_CHIP_DAC_VOL:
1132 case SGTL5000_CHIP_PAD_STRENGTH:
1133 case SGTL5000_CHIP_ANA_ADC_CTRL:
1134 case SGTL5000_CHIP_ANA_HP_CTRL:
1135 case SGTL5000_CHIP_ANA_CTRL:
1136 case SGTL5000_CHIP_LINREG_CTRL:
1137 case SGTL5000_CHIP_REF_CTRL:
1138 case SGTL5000_CHIP_MIC_CTRL:
1139 case SGTL5000_CHIP_LINE_OUT_CTRL:
1140 case SGTL5000_CHIP_LINE_OUT_VOL:
1141 case SGTL5000_CHIP_ANA_POWER:
1142 case SGTL5000_CHIP_PLL_CTRL:
1143 case SGTL5000_CHIP_CLK_TOP_CTRL:
1144 case SGTL5000_CHIP_ANA_STATUS:
1145 case SGTL5000_CHIP_SHORT_CTRL:
1146 case SGTL5000_CHIP_ANA_TEST2:
1147 case SGTL5000_DAP_CTRL:
1148 case SGTL5000_DAP_PEQ:
1149 case SGTL5000_DAP_BASS_ENHANCE:
1150 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1151 case SGTL5000_DAP_AUDIO_EQ:
1152 case SGTL5000_DAP_SURROUND:
1153 case SGTL5000_DAP_FLT_COEF_ACCESS:
1154 case SGTL5000_DAP_COEF_WR_B0_MSB:
1155 case SGTL5000_DAP_COEF_WR_B0_LSB:
1156 case SGTL5000_DAP_EQ_BASS_BAND0:
1157 case SGTL5000_DAP_EQ_BASS_BAND1:
1158 case SGTL5000_DAP_EQ_BASS_BAND2:
1159 case SGTL5000_DAP_EQ_BASS_BAND3:
1160 case SGTL5000_DAP_EQ_BASS_BAND4:
1161 case SGTL5000_DAP_MAIN_CHAN:
1162 case SGTL5000_DAP_MIX_CHAN:
1163 case SGTL5000_DAP_AVC_CTRL:
1164 case SGTL5000_DAP_AVC_THRESHOLD:
1165 case SGTL5000_DAP_AVC_ATTACK:
1166 case SGTL5000_DAP_AVC_DECAY:
1167 case SGTL5000_DAP_COEF_WR_B1_MSB:
1168 case SGTL5000_DAP_COEF_WR_B1_LSB:
1169 case SGTL5000_DAP_COEF_WR_B2_MSB:
1170 case SGTL5000_DAP_COEF_WR_B2_LSB:
1171 case SGTL5000_DAP_COEF_WR_A1_MSB:
1172 case SGTL5000_DAP_COEF_WR_A1_LSB:
1173 case SGTL5000_DAP_COEF_WR_A2_MSB:
1174 case SGTL5000_DAP_COEF_WR_A2_LSB:
1175 return true;
1176
1177 default:
1178 return false;
1179 }
9b34e6cc
ZZ		 1180}
1181
1f39d939
AS		 1182/*
1183 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1184 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1185 * The calculatation was done for all possible register values which
1186 * is the array index and the following formula: 10^((idx−15)/40) * 100
1187 */
1188static const u8 vol_quot_table[] = {
1189 42, 45, 47, 50, 53, 56, 60, 63,
1190 67, 71, 75, 79, 84, 89, 94, 100,
1191 106, 112, 119, 126, 133, 141, 150, 158,
1192 168, 178, 188, 200, 211, 224, 237, 251
1193};
1194
9b34e6cc
ZZ		 1195/*
1196 * sgtl5000 has 3 internal power supplies:
1197 * 1. VAG, normally set to vdda/2
7f6d75d7 1198 * 2. charge pump, set to different value
9b34e6cc
ZZ		 1199 * according to voltage of vdda and vddio
1200 * 3. line out VAG, normally set to vddio/2
1201 *
1202 * and should be set according to:
1203 * 1. vddd provided by external or not
1204 * 2. vdda and vddio voltage value. > 3.1v or not
9b34e6cc
ZZ		 1205 */
1206static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1207{
1208 int vddd;
1209 int vdda;
1210 int vddio;
1211 u16 ana_pwr;
1212 u16 lreg_ctrl;
1213 int vag;
d2b7c2aa 1214 int lo_vag;
1f39d939
AS		 1215 int vol_quot;
1216 int lo_vol;
1217 size_t i;
9b34e6cc
ZZ		 1218 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1219
1220 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1221 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
940adb28
EN		 1222 vddd = (sgtl5000->num_supplies > VDDD)
1223 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
1224 : LDO_VOLTAGE;
9b34e6cc
ZZ		 1225
1226 vdda = vdda / 1000;
1227 vddio = vddio / 1000;
1228 vddd = vddd / 1000;
1229
1230 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1231 dev_err(codec->dev, "regulator voltage not set correctly\n");
1232
1233 return -EINVAL;
1234 }
1235
1236 /* according to datasheet, maximum voltage of supplies */
1237 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1238 dev_err(codec->dev,
cf1ee98d 1239 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
9b34e6cc
ZZ		 1240 vdda, vddio, vddd);
1241
1242 return -EINVAL;
1243 }
1244
1245 /* reset value */
1246 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1247 ana_pwr |= SGTL5000_DAC_STEREO |
1248 SGTL5000_ADC_STEREO |
1249 SGTL5000_REFTOP_POWERUP;
1250 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1251
1252 if (vddio < 3100 && vdda < 3100) {
1253 /* enable internal oscillator used for charge pump */
1254 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1255 SGTL5000_INT_OSC_EN,
1256 SGTL5000_INT_OSC_EN);
1257 /* Enable VDDC charge pump */
1258 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
75fad334 1259 } else {
c7d910b8 1260 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
75fad334
OS		 1261 /*
1262 * if vddio == vdda the source of charge pump should be
1263 * assigned manually to VDDIO
1264 */
1265 if (vddio == vdda) {
1266 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1267 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1268 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1269 }
9b34e6cc
ZZ		 1270 }
1271
1272 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1273
1274 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1275
9b34e6cc
ZZ		 1276 /*
1277 * set ADC/DAC VAG to vdda / 2,
1278 * should stay in range (0.8v, 1.575v)
1279 */
1280 vag = vdda / 2;
1281 if (vag <= SGTL5000_ANA_GND_BASE)
1282 vag = 0;
1283 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1284 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1285 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1286 else
1287 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1288
1289 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
33cb92cf 1290 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
9b34e6cc
ZZ		 1291
1292 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
d2b7c2aa
AS		 1293 lo_vag = vddio / 2;
1294 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1295 lo_vag = 0;
1296 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
9b34e6cc 1297 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
d2b7c2aa 1298 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
9b34e6cc 1299 else
d2b7c2aa 1300 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
9b34e6cc
ZZ		 1301 SGTL5000_LINE_OUT_GND_STP;
1302
1303 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
33cb92cf
AL		 1304 SGTL5000_LINE_OUT_CURRENT_MASK |
1305 SGTL5000_LINE_OUT_GND_MASK,
d2b7c2aa 1306 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
9b34e6cc
ZZ		 1307 SGTL5000_LINE_OUT_CURRENT_360u <<
1308 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1309
1f39d939
AS		 1310 /*
1311 * Set lineout output level in range (0..31)
1312 * the same value is used for right and left channel
1313 *
1314 * Searching for a suitable index solving this formula:
1315 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1316 */
deb8e453 1317 vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
1f39d939
AS		 1318 lo_vol = 0;
1319 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1320 if (vol_quot >= vol_quot_table[i])
1321 lo_vol = i;
1322 else
1323 break;
1324 }
1325
1326 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1327 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1328 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1329 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1330 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1331
9b34e6cc
ZZ		 1332 return 0;
1333}
1334
940adb28 1335static int sgtl5000_enable_regulators(struct i2c_client *client)
9b34e6cc 1336{
9b34e6cc 1337 int ret;
9b34e6cc
ZZ		 1338 int i;
1339 int external_vddd = 0;
11db0da8 1340 struct regulator *vddd;
940adb28 1341 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc
ZZ		 1342
1343 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1344 sgtl5000->supplies[i].supply = supply_names[i];
1345
940adb28
EN		 1346 vddd = regulator_get_optional(&client->dev, "VDDD");
1347 if (IS_ERR(vddd)) {
1348 /* See if it's just not registered yet */
1349 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1350 return -EPROBE_DEFER;
1351 } else {
1352 external_vddd = 1;
1353 regulator_put(vddd);
9b34e6cc
ZZ		 1354 }
1355
940adb28
EN		 1356 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1357 - 1 + external_vddd;
1358 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
11db0da8
SG		 1359 sgtl5000->supplies);
1360 if (ret)
940adb28 1361 return ret;
9b34e6cc 1362
940adb28
EN		 1363 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1364 sgtl5000->supplies);
1365 if (!ret)
1366 usleep_range(10, 20);
1367 else
1368 regulator_bulk_free(sgtl5000->num_supplies,
1369 sgtl5000->supplies);
9b34e6cc 1370
9b34e6cc 1371 return ret;
9b34e6cc
ZZ		 1372}
1373
1374static int sgtl5000_probe(struct snd_soc_codec *codec)
1375{
1376 int ret;
570c70a6 1377 u16 reg;
9b34e6cc
ZZ		 1378 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1379
9b34e6cc
ZZ		 1380 /* power up sgtl5000 */
1381 ret = sgtl5000_set_power_regs(codec);
1382 if (ret)
1383 goto err;
1384
1385 /* enable small pop, introduce 400ms delay in turning off */
1386 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
c251ea7b 1387 SGTL5000_SMALL_POP, 1);
9b34e6cc
ZZ		 1388
1389 /* disable short cut detector */
1390 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1391
1392 /*
1393 * set i2s as default input of sound switch
1394 * TODO: add sound switch to control and dapm widge.
1395 */
1396 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1397 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1398 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1399 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1400
1401 /* enable dac volume ramp by default */
1402 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1403 SGTL5000_DAC_VOL_RAMP_EN |
1404 SGTL5000_DAC_MUTE_RIGHT |
1405 SGTL5000_DAC_MUTE_LEFT);
1406
570c70a6
FE		 1407 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f);
1408 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, reg);
9b34e6cc
ZZ		 1409
1410 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1411 SGTL5000_HP_ZCD_EN |
1412 SGTL5000_ADC_ZCD_EN);
1413
bd0593f5
JMH		 1414 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1415 SGTL5000_BIAS_R_MASK,
1416 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc 1417
87357797 1418 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
e256da84
GR		 1419 SGTL5000_BIAS_VOLT_MASK,
1420 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
9b34e6cc
ZZ		 1421 /*
1422 * disable DAP
1423 * TODO:
1424 * Enable DAP in kcontrol and dapm.
1425 */
1426 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1427
9b34e6cc
ZZ		 1428 return 0;
1429
1430err:
9b34e6cc
ZZ		 1431 return ret;
1432}
1433
1434static int sgtl5000_remove(struct snd_soc_codec *codec)
1435{
9b34e6cc
ZZ		 1436 return 0;
1437}
1438
a180ba45 1439static const struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1440 .probe = sgtl5000_probe,
1441 .remove = sgtl5000_remove,
9b34e6cc 1442 .set_bias_level = sgtl5000_set_bias_level,
e649057a 1443 .suspend_bias_off = true,
a324dbe5
KM		 1444 .component_driver = {
1445 .controls = sgtl5000_snd_controls,
1446 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1447 .dapm_widgets = sgtl5000_dapm_widgets,
1448 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1449 .dapm_routes = sgtl5000_dapm_routes,
1450 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1451 },
9b34e6cc
ZZ		 1452};
1453
e5d80e82
FE		 1454static const struct regmap_config sgtl5000_regmap = {
1455 .reg_bits = 16,
1456 .val_bits = 16,
cb23e852 1457 .reg_stride = 2,
e5d80e82
FE		 1458
1459 .max_register = SGTL5000_MAX_REG_OFFSET,
1460 .volatile_reg = sgtl5000_volatile,
1461 .readable_reg = sgtl5000_readable,
1462
1463 .cache_type = REGCACHE_RBTREE,
1464 .reg_defaults = sgtl5000_reg_defaults,
1465 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1466};
1467
af8ee112
FE		 1468/*
1469 * Write all the default values from sgtl5000_reg_defaults[] array into the
1470 * sgtl5000 registers, to make sure we always start with the sane registers
1471 * values as stated in the datasheet.
1472 *
1473 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1474 * we follow this approach to guarantee we always start from the default values
1475 * and avoid problems like, not being able to probe after an audio playback
1476 * followed by a system reset or a 'reboot' command in Linux
1477 */
f219b169 1478static void sgtl5000_fill_defaults(struct i2c_client *client)
af8ee112 1479{
f219b169 1480 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
af8ee112
FE		 1481 int i, ret, val, index;
1482
1483 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1484 val = sgtl5000_reg_defaults[i].def;
1485 index = sgtl5000_reg_defaults[i].reg;
1486 ret = regmap_write(sgtl5000->regmap, index, val);
1487 if (ret)
f219b169
EN		 1488 dev_err(&client->dev,
1489 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1490 __func__, ret, index, val);
af8ee112 1491 }
af8ee112
FE		 1492}
1493
7a79e94e
BP		 1494static int sgtl5000_i2c_probe(struct i2c_client *client,
1495 const struct i2c_device_id *id)
9b34e6cc
ZZ		 1496{
1497 struct sgtl5000_priv *sgtl5000;
b871f1ad 1498 int ret, reg, rev;
bd0593f5
JMH		 1499 struct device_node *np = client->dev.of_node;
1500 u32 value;
3d632cc8 1501 u16 ana_pwr;
9b34e6cc 1502
3f7256fe 1503 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
9b34e6cc
ZZ		 1504 if (!sgtl5000)
1505 return -ENOMEM;
1506
940adb28
EN		 1507 i2c_set_clientdata(client, sgtl5000);
1508
1509 ret = sgtl5000_enable_regulators(client);
1510 if (ret)
1511 return ret;
1512
e5d80e82
FE		 1513 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1514 if (IS_ERR(sgtl5000->regmap)) {
1515 ret = PTR_ERR(sgtl5000->regmap);
1516 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
940adb28 1517 goto disable_regs;
e5d80e82
FE		 1518 }
1519
9e13f345
FE		 1520 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1521 if (IS_ERR(sgtl5000->mclk)) {
1522 ret = PTR_ERR(sgtl5000->mclk);
1523 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
46a5905e
SG		 1524 /* Defer the probe to see if the clk will be provided later */
1525 if (ret == -ENOENT)
940adb28
EN		 1526 ret = -EPROBE_DEFER;
1527 goto disable_regs;
9e13f345
FE		 1528 }
1529
1530 ret = clk_prepare_enable(sgtl5000->mclk);
940adb28
EN		 1531 if (ret) {
1532 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1533 goto disable_regs;
1534 }
9e13f345 1535
58cc9c9a
EN		 1536 /* Need 8 clocks before I2C accesses */
1537 udelay(1);
1538
b871f1ad
FE		 1539 /* read chip information */
1540 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
940adb28
EN		 1541 if (ret) {
1542 dev_err(&client->dev, "Error reading chip id %d\n", ret);
9e13f345 1543 goto disable_clk;
940adb28 1544 }
b871f1ad
FE		 1545
1546 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1547 SGTL5000_PARTID_PART_ID) {
1548 dev_err(&client->dev,
1549 "Device with ID register %x is not a sgtl5000\n", reg);
9e13f345
FE		 1550 ret = -ENODEV;
1551 goto disable_clk;
b871f1ad
FE		 1552 }
1553
1554 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1555 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
252e91ff 1556 sgtl5000->revision = rev;
b871f1ad 1557
08dea16e
EN		 1558 /* reconfigure the clocks in case we're using the PLL */
1559 ret = regmap_write(sgtl5000->regmap,
1560 SGTL5000_CHIP_CLK_CTRL,
1561 SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1562 if (ret)
1563 dev_err(&client->dev,
1564 "Error %d initializing CHIP_CLK_CTRL\n", ret);
1565
940adb28 1566 /* Follow section 2.2.1.1 of AN3663 */
3d632cc8 1567 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
940adb28
EN		 1568 if (sgtl5000->num_supplies <= VDDD) {
1569 /* internal VDDD at 1.2V */
3d632cc8
EN		 1570 ret = regmap_update_bits(sgtl5000->regmap,
1571 SGTL5000_CHIP_LINREG_CTRL,
1572 SGTL5000_LINREG_VDDD_MASK,
1573 LINREG_VDDD);
1574 if (ret)
1575 dev_err(&client->dev,
1576 "Error %d setting LINREG_VDDD\n", ret);
1577
1578 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1579 dev_info(&client->dev,
1580 "Using internal LDO instead of VDDD: check ER1\n");
940adb28
EN		 1581 } else {
1582 /* using external LDO for VDDD
1583 * Clear startup powerup and simple powerup
1584 * bits to save power
1585 */
3d632cc8
EN		 1586 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1587 | SGTL5000_LINREG_SIMPLE_POWERUP);
940adb28
EN		 1588 dev_dbg(&client->dev, "Using external VDDD\n");
1589 }
3d632cc8
EN		 1590 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1591 if (ret)
1592 dev_err(&client->dev,
1593 "Error %d setting CHIP_ANA_POWER to %04x\n",
1594 ret, ana_pwr);
940adb28 1595
bd0593f5
JMH		 1596 if (np) {
1597 if (!of_property_read_u32(np,
1598 "micbias-resistor-k-ohms", &value)) {
1599 switch (value) {
1600 case SGTL5000_MICBIAS_OFF:
1601 sgtl5000->micbias_resistor = 0;
1602 break;
1603 case SGTL5000_MICBIAS_2K:
1604 sgtl5000->micbias_resistor = 1;
1605 break;
1606 case SGTL5000_MICBIAS_4K:
1607 sgtl5000->micbias_resistor = 2;
1608 break;
1609 case SGTL5000_MICBIAS_8K:
1610 sgtl5000->micbias_resistor = 3;
1611 break;
1612 default:
1613 sgtl5000->micbias_resistor = 2;
1614 dev_err(&client->dev,
1615 "Unsuitable MicBias resistor\n");
1616 }
1617 } else {
1618 /* default is 4Kohms */
1619 sgtl5000->micbias_resistor = 2;
1620 }
87357797
JMH		 1621 if (!of_property_read_u32(np,
1622 "micbias-voltage-m-volts", &value)) {
1623 /* 1250mV => 0 */
1624 /* steps of 250mV */
1625 if ((value >= 1250) && (value <= 3000))
1626 sgtl5000->micbias_voltage = (value / 250) - 5;
1627 else {
1628 sgtl5000->micbias_voltage = 0;
bd0593f5 1629 dev_err(&client->dev,
fb97d75b 1630 "Unsuitable MicBias voltage\n");
bd0593f5
JMH		 1631 }
1632 } else {
87357797 1633 sgtl5000->micbias_voltage = 0;
bd0593f5
JMH		 1634 }
1635 }
1636
570c70a6
FE		 1637 sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
1638 if (!of_property_read_u32(np, "lrclk-strength", &value)) {
1639 if (value > I2S_LRCLK_STRENGTH_HIGH)
1640 value = I2S_LRCLK_STRENGTH_LOW;
1641 sgtl5000->lrclk_strength = value;
1642 }
1643
af8ee112 1644 /* Ensure sgtl5000 will start with sane register values */
f219b169 1645 sgtl5000_fill_defaults(client);
af8ee112 1646
9b34e6cc
ZZ		 1647 ret = snd_soc_register_codec(&client->dev,
1648 &sgtl5000_driver, &sgtl5000_dai, 1);
9e13f345
FE		 1649 if (ret)
1650 goto disable_clk;
1651
1652 return 0;
1653
1654disable_clk:
1655 clk_disable_unprepare(sgtl5000->mclk);
940adb28
EN		 1656
1657disable_regs:
1658 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1659 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1660
512fa7c4 1661 return ret;
9b34e6cc
ZZ		 1662}
1663
7a79e94e 1664static int sgtl5000_i2c_remove(struct i2c_client *client)
9b34e6cc 1665{
7c647af4 1666 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc 1667
9e13f345
FE		 1668 snd_soc_unregister_codec(&client->dev);
1669 clk_disable_unprepare(sgtl5000->mclk);
940adb28
EN		 1670 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1671 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1672
9b34e6cc
ZZ		 1673 return 0;
1674}
1675
1676static const struct i2c_device_id sgtl5000_id[] = {
1677 {"sgtl5000", 0},
1678 {},
1679};
1680
1681MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1682
58e49424
SG		 1683static const struct of_device_id sgtl5000_dt_ids[] = {
1684 { .compatible = "fsl,sgtl5000", },
1685 { /* sentinel */ }
1686};
4c54c6de 1687MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1688
9b34e6cc
ZZ		 1689static struct i2c_driver sgtl5000_i2c_driver = {
1690 .driver = {
1691 .name = "sgtl5000",
58e49424 1692 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1693 },
1694 .probe = sgtl5000_i2c_probe,
7a79e94e 1695 .remove = sgtl5000_i2c_remove,
9b34e6cc
ZZ		 1696 .id_table = sgtl5000_id,
1697};
1698
67d45090 1699module_i2c_driver(sgtl5000_i2c_driver);
9b34e6cc
ZZ		 1700
1701MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
f7cb8a4b 1702MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
9b34e6cc 1703MODULE_LICENSE("GPL");
ubuntu-bionic-kernel mirror