]>
Commit | Line | Data |
---|---|---|
c034abf6 JS |
1 | /* |
2 | * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system | |
3 | * | |
4 | * Copyright: 2011 Raumfeld GmbH | |
5 | * Author: Johannes Stezenbach <js@sig21.net> | |
6 | * | |
7 | * based on code from: | |
8 | * Wolfson Microelectronics PLC. | |
9 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | |
10 | * Freescale Semiconductor, Inc. | |
11 | * Timur Tabi <timur@freescale.com> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
19 | #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/moduleparam.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/pm.h> | |
26 | #include <linux/i2c.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/regulator/consumer.h> | |
29 | #include <linux/slab.h> | |
30 | #include <sound/core.h> | |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/soc-dapm.h> | |
35 | #include <sound/initval.h> | |
36 | #include <sound/tlv.h> | |
37 | ||
38 | #include "sta32x.h" | |
39 | ||
40 | #define STA32X_RATES (SNDRV_PCM_RATE_32000 | \ | |
41 | SNDRV_PCM_RATE_44100 | \ | |
42 | SNDRV_PCM_RATE_48000 | \ | |
43 | SNDRV_PCM_RATE_88200 | \ | |
44 | SNDRV_PCM_RATE_96000 | \ | |
45 | SNDRV_PCM_RATE_176400 | \ | |
46 | SNDRV_PCM_RATE_192000) | |
47 | ||
48 | #define STA32X_FORMATS \ | |
49 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \ | |
50 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \ | |
51 | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
52 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \ | |
53 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \ | |
54 | SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE) | |
55 | ||
56 | /* Power-up register defaults */ | |
57 | static const u8 sta32x_regs[STA32X_REGISTER_COUNT] = { | |
58 | 0x63, 0x80, 0xc2, 0x40, 0xc2, 0x5c, 0x10, 0xff, 0x60, 0x60, | |
59 | 0x60, 0x80, 0x00, 0x00, 0x00, 0x40, 0x80, 0x77, 0x6a, 0x69, | |
60 | 0x6a, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
61 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2d, | |
62 | 0xc0, 0xf3, 0x33, 0x00, 0x0c, | |
63 | }; | |
64 | ||
65 | /* regulator power supply names */ | |
66 | static const char *sta32x_supply_names[] = { | |
67 | "Vdda", /* analog supply, 3.3VV */ | |
68 | "Vdd3", /* digital supply, 3.3V */ | |
69 | "Vcc" /* power amp spply, 10V - 36V */ | |
70 | }; | |
71 | ||
72 | /* codec private data */ | |
73 | struct sta32x_priv { | |
74 | struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)]; | |
75 | struct snd_soc_codec *codec; | |
76 | ||
77 | unsigned int mclk; | |
78 | unsigned int format; | |
79 | }; | |
80 | ||
81 | static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1); | |
82 | static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1); | |
83 | static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0); | |
84 | ||
85 | static const char *sta32x_drc_ac[] = { | |
86 | "Anti-Clipping", "Dynamic Range Compression" }; | |
87 | static const char *sta32x_auto_eq_mode[] = { | |
88 | "User", "Preset", "Loudness" }; | |
89 | static const char *sta32x_auto_gc_mode[] = { | |
90 | "User", "AC no clipping", "AC limited clipping (10%)", | |
91 | "DRC nighttime listening mode" }; | |
92 | static const char *sta32x_auto_xo_mode[] = { | |
93 | "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz", | |
94 | "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" }; | |
95 | static const char *sta32x_preset_eq_mode[] = { | |
96 | "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft", | |
97 | "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1", | |
98 | "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2", | |
99 | "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7", | |
100 | "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12", | |
101 | "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" }; | |
102 | static const char *sta32x_limiter_select[] = { | |
103 | "Limiter Disabled", "Limiter #1", "Limiter #2" }; | |
104 | static const char *sta32x_limiter_attack_rate[] = { | |
105 | "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024", | |
106 | "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752", | |
107 | "0.0645", "0.0564", "0.0501", "0.0451" }; | |
108 | static const char *sta32x_limiter_release_rate[] = { | |
109 | "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299", | |
110 | "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137", | |
111 | "0.0134", "0.0117", "0.0110", "0.0104" }; | |
112 | ||
113 | static const unsigned int sta32x_limiter_ac_attack_tlv[] = { | |
114 | TLV_DB_RANGE_HEAD(2), | |
115 | 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0), | |
116 | 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0), | |
117 | }; | |
118 | ||
119 | static const unsigned int sta32x_limiter_ac_release_tlv[] = { | |
120 | TLV_DB_RANGE_HEAD(5), | |
121 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), | |
122 | 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0), | |
123 | 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0), | |
124 | 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0), | |
125 | 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0), | |
126 | }; | |
127 | ||
128 | static const unsigned int sta32x_limiter_drc_attack_tlv[] = { | |
129 | TLV_DB_RANGE_HEAD(3), | |
130 | 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0), | |
131 | 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0), | |
132 | 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0), | |
133 | }; | |
134 | ||
135 | static const unsigned int sta32x_limiter_drc_release_tlv[] = { | |
136 | TLV_DB_RANGE_HEAD(5), | |
137 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), | |
138 | 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0), | |
139 | 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0), | |
140 | 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0), | |
141 | 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0), | |
142 | }; | |
143 | ||
144 | static const struct soc_enum sta32x_drc_ac_enum = | |
145 | SOC_ENUM_SINGLE(STA32X_CONFD, STA32X_CONFD_DRC_SHIFT, | |
146 | 2, sta32x_drc_ac); | |
147 | static const struct soc_enum sta32x_auto_eq_enum = | |
148 | SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT, | |
149 | 3, sta32x_auto_eq_mode); | |
150 | static const struct soc_enum sta32x_auto_gc_enum = | |
151 | SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT, | |
152 | 4, sta32x_auto_gc_mode); | |
153 | static const struct soc_enum sta32x_auto_xo_enum = | |
154 | SOC_ENUM_SINGLE(STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT, | |
155 | 16, sta32x_auto_xo_mode); | |
156 | static const struct soc_enum sta32x_preset_eq_enum = | |
157 | SOC_ENUM_SINGLE(STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT, | |
158 | 32, sta32x_preset_eq_mode); | |
159 | static const struct soc_enum sta32x_limiter_ch1_enum = | |
160 | SOC_ENUM_SINGLE(STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT, | |
161 | 3, sta32x_limiter_select); | |
162 | static const struct soc_enum sta32x_limiter_ch2_enum = | |
163 | SOC_ENUM_SINGLE(STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT, | |
164 | 3, sta32x_limiter_select); | |
165 | static const struct soc_enum sta32x_limiter_ch3_enum = | |
166 | SOC_ENUM_SINGLE(STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT, | |
167 | 3, sta32x_limiter_select); | |
168 | static const struct soc_enum sta32x_limiter1_attack_rate_enum = | |
169 | SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxA_SHIFT, | |
170 | 16, sta32x_limiter_attack_rate); | |
171 | static const struct soc_enum sta32x_limiter2_attack_rate_enum = | |
172 | SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxA_SHIFT, | |
173 | 16, sta32x_limiter_attack_rate); | |
174 | static const struct soc_enum sta32x_limiter1_release_rate_enum = | |
175 | SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxR_SHIFT, | |
176 | 16, sta32x_limiter_release_rate); | |
177 | static const struct soc_enum sta32x_limiter2_release_rate_enum = | |
178 | SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxR_SHIFT, | |
179 | 16, sta32x_limiter_release_rate); | |
79688439 JS |
180 | |
181 | /* byte array controls for setting biquad, mixer, scaling coefficients; | |
182 | * for biquads all five coefficients need to be set in one go, | |
183 | * mixer and pre/postscale coefs can be set individually; | |
184 | * each coef is 24bit, the bytes are ordered in the same way | |
185 | * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0) | |
186 | */ | |
187 | ||
188 | static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol, | |
189 | struct snd_ctl_elem_info *uinfo) | |
190 | { | |
191 | int numcoef = kcontrol->private_value >> 16; | |
192 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; | |
193 | uinfo->count = 3 * numcoef; | |
194 | return 0; | |
195 | } | |
196 | ||
197 | static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol, | |
198 | struct snd_ctl_elem_value *ucontrol) | |
199 | { | |
200 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
201 | int numcoef = kcontrol->private_value >> 16; | |
202 | int index = kcontrol->private_value & 0xffff; | |
203 | unsigned int cfud; | |
204 | int i; | |
205 | ||
206 | /* preserve reserved bits in STA32X_CFUD */ | |
207 | cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; | |
208 | /* chip documentation does not say if the bits are self clearing, | |
209 | * so do it explicitly */ | |
210 | snd_soc_write(codec, STA32X_CFUD, cfud); | |
211 | ||
212 | snd_soc_write(codec, STA32X_CFADDR2, index); | |
213 | if (numcoef == 1) | |
214 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x04); | |
215 | else if (numcoef == 5) | |
216 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x08); | |
217 | else | |
218 | return -EINVAL; | |
219 | for (i = 0; i < 3 * numcoef; i++) | |
220 | ucontrol->value.bytes.data[i] = | |
221 | snd_soc_read(codec, STA32X_B1CF1 + i); | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol, | |
227 | struct snd_ctl_elem_value *ucontrol) | |
228 | { | |
229 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
230 | int numcoef = kcontrol->private_value >> 16; | |
231 | int index = kcontrol->private_value & 0xffff; | |
232 | unsigned int cfud; | |
233 | int i; | |
234 | ||
235 | /* preserve reserved bits in STA32X_CFUD */ | |
236 | cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; | |
237 | /* chip documentation does not say if the bits are self clearing, | |
238 | * so do it explicitly */ | |
239 | snd_soc_write(codec, STA32X_CFUD, cfud); | |
240 | ||
241 | snd_soc_write(codec, STA32X_CFADDR2, index); | |
242 | for (i = 0; i < 3 * numcoef; i++) | |
243 | snd_soc_write(codec, STA32X_B1CF1 + i, | |
244 | ucontrol->value.bytes.data[i]); | |
245 | if (numcoef == 1) | |
246 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x01); | |
247 | else if (numcoef == 5) | |
248 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x02); | |
249 | else | |
250 | return -EINVAL; | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | #define SINGLE_COEF(xname, index) \ | |
256 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
257 | .info = sta32x_coefficient_info, \ | |
258 | .get = sta32x_coefficient_get,\ | |
259 | .put = sta32x_coefficient_put, \ | |
260 | .private_value = index | (1 << 16) } | |
261 | ||
262 | #define BIQUAD_COEFS(xname, index) \ | |
263 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
264 | .info = sta32x_coefficient_info, \ | |
265 | .get = sta32x_coefficient_get,\ | |
266 | .put = sta32x_coefficient_put, \ | |
267 | .private_value = index | (5 << 16) } | |
268 | ||
c034abf6 JS |
269 | static const struct snd_kcontrol_new sta32x_snd_controls[] = { |
270 | SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv), | |
271 | SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1), | |
272 | SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1), | |
273 | SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1), | |
274 | SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1), | |
275 | SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv), | |
276 | SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv), | |
277 | SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv), | |
278 | SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0), | |
279 | SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum), | |
280 | SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0), | |
281 | SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0), | |
282 | SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0), | |
283 | SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0), | |
284 | SOC_ENUM("Automode EQ", sta32x_auto_eq_enum), | |
285 | SOC_ENUM("Automode GC", sta32x_auto_gc_enum), | |
286 | SOC_ENUM("Automode XO", sta32x_auto_xo_enum), | |
287 | SOC_ENUM("Preset EQ", sta32x_preset_eq_enum), | |
288 | SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), | |
289 | SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), | |
290 | SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), | |
291 | SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), | |
292 | SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), | |
293 | SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), | |
294 | SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), | |
295 | SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum), | |
296 | SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum), | |
297 | SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum), | |
298 | SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv), | |
299 | SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv), | |
300 | SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum), | |
301 | SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum), | |
302 | SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum), | |
303 | SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum), | |
304 | ||
305 | /* depending on mode, the attack/release thresholds have | |
306 | * two different enum definitions; provide both | |
307 | */ | |
308 | SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, | |
309 | 16, 0, sta32x_limiter_ac_attack_tlv), | |
310 | SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, | |
311 | 16, 0, sta32x_limiter_ac_attack_tlv), | |
312 | SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, | |
313 | 16, 0, sta32x_limiter_ac_release_tlv), | |
314 | SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, | |
315 | 16, 0, sta32x_limiter_ac_release_tlv), | |
316 | SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, | |
317 | 16, 0, sta32x_limiter_drc_attack_tlv), | |
318 | SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, | |
319 | 16, 0, sta32x_limiter_drc_attack_tlv), | |
320 | SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, | |
321 | 16, 0, sta32x_limiter_drc_release_tlv), | |
322 | SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, | |
323 | 16, 0, sta32x_limiter_drc_release_tlv), | |
79688439 JS |
324 | |
325 | BIQUAD_COEFS("Ch1 - Biquad 1", 0), | |
326 | BIQUAD_COEFS("Ch1 - Biquad 2", 5), | |
327 | BIQUAD_COEFS("Ch1 - Biquad 3", 10), | |
328 | BIQUAD_COEFS("Ch1 - Biquad 4", 15), | |
329 | BIQUAD_COEFS("Ch2 - Biquad 1", 20), | |
330 | BIQUAD_COEFS("Ch2 - Biquad 2", 25), | |
331 | BIQUAD_COEFS("Ch2 - Biquad 3", 30), | |
332 | BIQUAD_COEFS("Ch2 - Biquad 4", 35), | |
333 | BIQUAD_COEFS("High-pass", 40), | |
334 | BIQUAD_COEFS("Low-pass", 45), | |
335 | SINGLE_COEF("Ch1 - Prescale", 50), | |
336 | SINGLE_COEF("Ch2 - Prescale", 51), | |
337 | SINGLE_COEF("Ch1 - Postscale", 52), | |
338 | SINGLE_COEF("Ch2 - Postscale", 53), | |
339 | SINGLE_COEF("Ch3 - Postscale", 54), | |
340 | SINGLE_COEF("Thermal warning - Postscale", 55), | |
341 | SINGLE_COEF("Ch1 - Mix 1", 56), | |
342 | SINGLE_COEF("Ch1 - Mix 2", 57), | |
343 | SINGLE_COEF("Ch2 - Mix 1", 58), | |
344 | SINGLE_COEF("Ch2 - Mix 2", 59), | |
345 | SINGLE_COEF("Ch3 - Mix 1", 60), | |
346 | SINGLE_COEF("Ch3 - Mix 2", 61), | |
c034abf6 JS |
347 | }; |
348 | ||
349 | static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = { | |
350 | SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0), | |
351 | SND_SOC_DAPM_OUTPUT("LEFT"), | |
352 | SND_SOC_DAPM_OUTPUT("RIGHT"), | |
353 | SND_SOC_DAPM_OUTPUT("SUB"), | |
354 | }; | |
355 | ||
356 | static const struct snd_soc_dapm_route sta32x_dapm_routes[] = { | |
357 | { "LEFT", NULL, "DAC" }, | |
358 | { "RIGHT", NULL, "DAC" }, | |
359 | { "SUB", NULL, "DAC" }, | |
360 | }; | |
361 | ||
362 | /* MCLK interpolation ratio per fs */ | |
363 | static struct { | |
364 | int fs; | |
365 | int ir; | |
366 | } interpolation_ratios[] = { | |
367 | { 32000, 0 }, | |
368 | { 44100, 0 }, | |
369 | { 48000, 0 }, | |
370 | { 88200, 1 }, | |
371 | { 96000, 1 }, | |
372 | { 176400, 2 }, | |
373 | { 192000, 2 }, | |
374 | }; | |
375 | ||
376 | /* MCLK to fs clock ratios */ | |
377 | static struct { | |
378 | int ratio; | |
379 | int mcs; | |
380 | } mclk_ratios[3][7] = { | |
381 | { { 768, 0 }, { 512, 1 }, { 384, 2 }, { 256, 3 }, | |
382 | { 128, 4 }, { 576, 5 }, { 0, 0 } }, | |
383 | { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } }, | |
384 | { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } }, | |
385 | }; | |
386 | ||
387 | ||
388 | /** | |
389 | * sta32x_set_dai_sysclk - configure MCLK | |
390 | * @codec_dai: the codec DAI | |
391 | * @clk_id: the clock ID (ignored) | |
392 | * @freq: the MCLK input frequency | |
393 | * @dir: the clock direction (ignored) | |
394 | * | |
395 | * The value of MCLK is used to determine which sample rates are supported | |
396 | * by the STA32X, based on the mclk_ratios table. | |
397 | * | |
398 | * This function must be called by the machine driver's 'startup' function, | |
399 | * otherwise the list of supported sample rates will not be available in | |
400 | * time for ALSA. | |
401 | * | |
402 | * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause | |
403 | * theoretically possible sample rates to be enabled. Call it again with a | |
404 | * proper value set one the external clock is set (most probably you would do | |
405 | * that from a machine's driver 'hw_param' hook. | |
406 | */ | |
407 | static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
408 | int clk_id, unsigned int freq, int dir) | |
409 | { | |
410 | struct snd_soc_codec *codec = codec_dai->codec; | |
411 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
412 | int i, j, ir, fs; | |
413 | unsigned int rates = 0; | |
414 | unsigned int rate_min = -1; | |
415 | unsigned int rate_max = 0; | |
416 | ||
417 | pr_debug("mclk=%u\n", freq); | |
418 | sta32x->mclk = freq; | |
419 | ||
420 | if (sta32x->mclk) { | |
421 | for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) { | |
422 | ir = interpolation_ratios[i].ir; | |
423 | fs = interpolation_ratios[i].fs; | |
424 | for (j = 0; mclk_ratios[ir][j].ratio; j++) { | |
425 | if (mclk_ratios[ir][j].ratio * fs == freq) { | |
426 | rates |= snd_pcm_rate_to_rate_bit(fs); | |
427 | if (fs < rate_min) | |
428 | rate_min = fs; | |
429 | if (fs > rate_max) | |
430 | rate_max = fs; | |
431 | } | |
432 | } | |
433 | } | |
434 | /* FIXME: soc should support a rate list */ | |
435 | rates &= ~SNDRV_PCM_RATE_KNOT; | |
436 | ||
437 | if (!rates) { | |
438 | dev_err(codec->dev, "could not find a valid sample rate\n"); | |
439 | return -EINVAL; | |
440 | } | |
441 | } else { | |
442 | /* enable all possible rates */ | |
443 | rates = STA32X_RATES; | |
444 | rate_min = 32000; | |
445 | rate_max = 192000; | |
446 | } | |
447 | ||
448 | codec_dai->driver->playback.rates = rates; | |
449 | codec_dai->driver->playback.rate_min = rate_min; | |
450 | codec_dai->driver->playback.rate_max = rate_max; | |
451 | return 0; | |
452 | } | |
453 | ||
454 | /** | |
455 | * sta32x_set_dai_fmt - configure the codec for the selected audio format | |
456 | * @codec_dai: the codec DAI | |
457 | * @fmt: a SND_SOC_DAIFMT_x value indicating the data format | |
458 | * | |
459 | * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the | |
460 | * codec accordingly. | |
461 | */ | |
462 | static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
463 | unsigned int fmt) | |
464 | { | |
465 | struct snd_soc_codec *codec = codec_dai->codec; | |
466 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
467 | u8 confb = snd_soc_read(codec, STA32X_CONFB); | |
468 | ||
469 | pr_debug("\n"); | |
470 | confb &= ~(STA32X_CONFB_C1IM | STA32X_CONFB_C2IM); | |
471 | ||
472 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
473 | case SND_SOC_DAIFMT_CBS_CFS: | |
474 | break; | |
475 | default: | |
476 | return -EINVAL; | |
477 | } | |
478 | ||
479 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
480 | case SND_SOC_DAIFMT_I2S: | |
481 | case SND_SOC_DAIFMT_RIGHT_J: | |
482 | case SND_SOC_DAIFMT_LEFT_J: | |
483 | sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
484 | break; | |
485 | default: | |
486 | return -EINVAL; | |
487 | } | |
488 | ||
489 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
490 | case SND_SOC_DAIFMT_NB_NF: | |
491 | confb |= STA32X_CONFB_C2IM; | |
492 | break; | |
493 | case SND_SOC_DAIFMT_NB_IF: | |
494 | confb |= STA32X_CONFB_C1IM; | |
495 | break; | |
496 | default: | |
497 | return -EINVAL; | |
498 | } | |
499 | ||
500 | snd_soc_write(codec, STA32X_CONFB, confb); | |
501 | return 0; | |
502 | } | |
503 | ||
504 | /** | |
505 | * sta32x_hw_params - program the STA32X with the given hardware parameters. | |
506 | * @substream: the audio stream | |
507 | * @params: the hardware parameters to set | |
508 | * @dai: the SOC DAI (ignored) | |
509 | * | |
510 | * This function programs the hardware with the values provided. | |
511 | * Specifically, the sample rate and the data format. | |
512 | */ | |
513 | static int sta32x_hw_params(struct snd_pcm_substream *substream, | |
514 | struct snd_pcm_hw_params *params, | |
515 | struct snd_soc_dai *dai) | |
516 | { | |
517 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
518 | struct snd_soc_codec *codec = rtd->codec; | |
519 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
520 | unsigned int rate; | |
521 | int i, mcs = -1, ir = -1; | |
522 | u8 confa, confb; | |
523 | ||
524 | rate = params_rate(params); | |
525 | pr_debug("rate: %u\n", rate); | |
526 | for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) | |
a595238b | 527 | if (interpolation_ratios[i].fs == rate) { |
c034abf6 | 528 | ir = interpolation_ratios[i].ir; |
a595238b AL |
529 | break; |
530 | } | |
c034abf6 JS |
531 | if (ir < 0) |
532 | return -EINVAL; | |
533 | for (i = 0; mclk_ratios[ir][i].ratio; i++) | |
a595238b | 534 | if (mclk_ratios[ir][i].ratio * rate == sta32x->mclk) { |
c034abf6 | 535 | mcs = mclk_ratios[ir][i].mcs; |
a595238b AL |
536 | break; |
537 | } | |
c034abf6 JS |
538 | if (mcs < 0) |
539 | return -EINVAL; | |
540 | ||
541 | confa = snd_soc_read(codec, STA32X_CONFA); | |
542 | confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK); | |
543 | confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT); | |
544 | ||
545 | confb = snd_soc_read(codec, STA32X_CONFB); | |
546 | confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB); | |
547 | switch (params_format(params)) { | |
548 | case SNDRV_PCM_FORMAT_S24_LE: | |
549 | case SNDRV_PCM_FORMAT_S24_BE: | |
550 | case SNDRV_PCM_FORMAT_S24_3LE: | |
551 | case SNDRV_PCM_FORMAT_S24_3BE: | |
552 | pr_debug("24bit\n"); | |
553 | /* fall through */ | |
554 | case SNDRV_PCM_FORMAT_S32_LE: | |
555 | case SNDRV_PCM_FORMAT_S32_BE: | |
556 | pr_debug("24bit or 32bit\n"); | |
557 | switch (sta32x->format) { | |
558 | case SND_SOC_DAIFMT_I2S: | |
559 | confb |= 0x0; | |
560 | break; | |
561 | case SND_SOC_DAIFMT_LEFT_J: | |
562 | confb |= 0x1; | |
563 | break; | |
564 | case SND_SOC_DAIFMT_RIGHT_J: | |
565 | confb |= 0x2; | |
566 | break; | |
567 | } | |
568 | ||
569 | break; | |
570 | case SNDRV_PCM_FORMAT_S20_3LE: | |
571 | case SNDRV_PCM_FORMAT_S20_3BE: | |
572 | pr_debug("20bit\n"); | |
573 | switch (sta32x->format) { | |
574 | case SND_SOC_DAIFMT_I2S: | |
575 | confb |= 0x4; | |
576 | break; | |
577 | case SND_SOC_DAIFMT_LEFT_J: | |
578 | confb |= 0x5; | |
579 | break; | |
580 | case SND_SOC_DAIFMT_RIGHT_J: | |
581 | confb |= 0x6; | |
582 | break; | |
583 | } | |
584 | ||
585 | break; | |
586 | case SNDRV_PCM_FORMAT_S18_3LE: | |
587 | case SNDRV_PCM_FORMAT_S18_3BE: | |
588 | pr_debug("18bit\n"); | |
589 | switch (sta32x->format) { | |
590 | case SND_SOC_DAIFMT_I2S: | |
591 | confb |= 0x8; | |
592 | break; | |
593 | case SND_SOC_DAIFMT_LEFT_J: | |
594 | confb |= 0x9; | |
595 | break; | |
596 | case SND_SOC_DAIFMT_RIGHT_J: | |
597 | confb |= 0xa; | |
598 | break; | |
599 | } | |
600 | ||
601 | break; | |
602 | case SNDRV_PCM_FORMAT_S16_LE: | |
603 | case SNDRV_PCM_FORMAT_S16_BE: | |
604 | pr_debug("16bit\n"); | |
605 | switch (sta32x->format) { | |
606 | case SND_SOC_DAIFMT_I2S: | |
607 | confb |= 0x0; | |
608 | break; | |
609 | case SND_SOC_DAIFMT_LEFT_J: | |
610 | confb |= 0xd; | |
611 | break; | |
612 | case SND_SOC_DAIFMT_RIGHT_J: | |
613 | confb |= 0xe; | |
614 | break; | |
615 | } | |
616 | ||
617 | break; | |
618 | default: | |
619 | return -EINVAL; | |
620 | } | |
621 | ||
622 | snd_soc_write(codec, STA32X_CONFA, confa); | |
623 | snd_soc_write(codec, STA32X_CONFB, confb); | |
624 | return 0; | |
625 | } | |
626 | ||
627 | /** | |
628 | * sta32x_set_bias_level - DAPM callback | |
629 | * @codec: the codec device | |
630 | * @level: DAPM power level | |
631 | * | |
632 | * This is called by ALSA to put the codec into low power mode | |
633 | * or to wake it up. If the codec is powered off completely | |
634 | * all registers must be restored after power on. | |
635 | */ | |
636 | static int sta32x_set_bias_level(struct snd_soc_codec *codec, | |
637 | enum snd_soc_bias_level level) | |
638 | { | |
639 | int ret; | |
640 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
641 | ||
642 | pr_debug("level = %d\n", level); | |
643 | switch (level) { | |
644 | case SND_SOC_BIAS_ON: | |
645 | break; | |
646 | ||
647 | case SND_SOC_BIAS_PREPARE: | |
648 | /* Full power on */ | |
649 | snd_soc_update_bits(codec, STA32X_CONFF, | |
650 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | |
651 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); | |
652 | break; | |
653 | ||
654 | case SND_SOC_BIAS_STANDBY: | |
655 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
656 | ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), | |
657 | sta32x->supplies); | |
658 | if (ret != 0) { | |
659 | dev_err(codec->dev, | |
660 | "Failed to enable supplies: %d\n", ret); | |
661 | return ret; | |
662 | } | |
663 | ||
664 | snd_soc_cache_sync(codec); | |
665 | } | |
666 | ||
667 | /* Power up to mute */ | |
668 | /* FIXME */ | |
669 | snd_soc_update_bits(codec, STA32X_CONFF, | |
670 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | |
671 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); | |
672 | ||
673 | break; | |
674 | ||
675 | case SND_SOC_BIAS_OFF: | |
676 | /* The chip runs through the power down sequence for us. */ | |
677 | snd_soc_update_bits(codec, STA32X_CONFF, | |
678 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | |
679 | STA32X_CONFF_PWDN); | |
680 | msleep(300); | |
681 | ||
682 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), | |
683 | sta32x->supplies); | |
684 | break; | |
685 | } | |
686 | codec->dapm.bias_level = level; | |
687 | return 0; | |
688 | } | |
689 | ||
690 | static struct snd_soc_dai_ops sta32x_dai_ops = { | |
691 | .hw_params = sta32x_hw_params, | |
692 | .set_sysclk = sta32x_set_dai_sysclk, | |
693 | .set_fmt = sta32x_set_dai_fmt, | |
694 | }; | |
695 | ||
696 | static struct snd_soc_dai_driver sta32x_dai = { | |
697 | .name = "STA32X", | |
698 | .playback = { | |
699 | .stream_name = "Playback", | |
700 | .channels_min = 2, | |
701 | .channels_max = 2, | |
702 | .rates = STA32X_RATES, | |
703 | .formats = STA32X_FORMATS, | |
704 | }, | |
705 | .ops = &sta32x_dai_ops, | |
706 | }; | |
707 | ||
708 | #ifdef CONFIG_PM | |
709 | static int sta32x_suspend(struct snd_soc_codec *codec, pm_message_t state) | |
710 | { | |
711 | sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
712 | return 0; | |
713 | } | |
714 | ||
715 | static int sta32x_resume(struct snd_soc_codec *codec) | |
716 | { | |
717 | sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
718 | return 0; | |
719 | } | |
720 | #else | |
721 | #define sta32x_suspend NULL | |
722 | #define sta32x_resume NULL | |
723 | #endif | |
724 | ||
725 | static int sta32x_probe(struct snd_soc_codec *codec) | |
726 | { | |
727 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
728 | int i, ret = 0; | |
729 | ||
730 | sta32x->codec = codec; | |
731 | ||
732 | /* regulators */ | |
733 | for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++) | |
734 | sta32x->supplies[i].supply = sta32x_supply_names[i]; | |
735 | ||
736 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sta32x->supplies), | |
737 | sta32x->supplies); | |
738 | if (ret != 0) { | |
739 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
740 | goto err; | |
741 | } | |
742 | ||
743 | ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), | |
744 | sta32x->supplies); | |
745 | if (ret != 0) { | |
746 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
747 | goto err_get; | |
748 | } | |
749 | ||
750 | /* Tell ASoC what kind of I/O to use to read the registers. ASoC will | |
751 | * then do the I2C transactions itself. | |
752 | */ | |
753 | ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); | |
754 | if (ret < 0) { | |
755 | dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret); | |
756 | return ret; | |
757 | } | |
758 | ||
edf413f6 AL |
759 | /* Chip documentation explicitly requires that the reset values |
760 | * of reserved register bits are left untouched. | |
761 | * Write the register default value to cache for reserved registers, | |
762 | * so the write to the these registers are suppressed by the cache | |
763 | * restore code when it skips writes of default registers. | |
764 | */ | |
765 | snd_soc_cache_write(codec, STA32X_CONFC, 0xc2); | |
766 | snd_soc_cache_write(codec, STA32X_CONFE, 0xc2); | |
767 | snd_soc_cache_write(codec, STA32X_CONFF, 0x5c); | |
768 | snd_soc_cache_write(codec, STA32X_MMUTE, 0x10); | |
769 | snd_soc_cache_write(codec, STA32X_AUTO1, 0x60); | |
770 | snd_soc_cache_write(codec, STA32X_AUTO3, 0x00); | |
771 | snd_soc_cache_write(codec, STA32X_C3CFG, 0x40); | |
889ebae5 | 772 | |
c034abf6 JS |
773 | /* FIXME enable thermal warning adjustment and recovery */ |
774 | snd_soc_update_bits(codec, STA32X_CONFA, | |
775 | STA32X_CONFA_TWAB | STA32X_CONFA_TWRB, 0); | |
776 | ||
777 | /* FIXME select 2.1 mode */ | |
778 | snd_soc_update_bits(codec, STA32X_CONFF, | |
779 | STA32X_CONFF_OCFG_MASK, | |
780 | 1 << STA32X_CONFF_OCFG_SHIFT); | |
781 | ||
782 | /* FIXME channel to output mapping */ | |
783 | snd_soc_update_bits(codec, STA32X_C1CFG, | |
784 | STA32X_CxCFG_OM_MASK, | |
785 | 0 << STA32X_CxCFG_OM_SHIFT); | |
786 | snd_soc_update_bits(codec, STA32X_C2CFG, | |
787 | STA32X_CxCFG_OM_MASK, | |
788 | 1 << STA32X_CxCFG_OM_SHIFT); | |
789 | snd_soc_update_bits(codec, STA32X_C3CFG, | |
790 | STA32X_CxCFG_OM_MASK, | |
791 | 2 << STA32X_CxCFG_OM_SHIFT); | |
792 | ||
793 | sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
794 | /* Bias level configuration will have done an extra enable */ | |
795 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); | |
796 | ||
797 | return 0; | |
798 | ||
799 | err_get: | |
800 | regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); | |
801 | err: | |
802 | return ret; | |
803 | } | |
804 | ||
805 | static int sta32x_remove(struct snd_soc_codec *codec) | |
806 | { | |
807 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
808 | ||
e3d73c1b | 809 | sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF); |
c034abf6 JS |
810 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); |
811 | regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
79688439 JS |
816 | static int sta32x_reg_is_volatile(struct snd_soc_codec *codec, |
817 | unsigned int reg) | |
818 | { | |
819 | switch (reg) { | |
820 | case STA32X_CONFA ... STA32X_L2ATRT: | |
821 | case STA32X_MPCC1 ... STA32X_FDRC2: | |
822 | return 0; | |
823 | } | |
824 | return 1; | |
825 | } | |
826 | ||
c034abf6 JS |
827 | static const struct snd_soc_codec_driver sta32x_codec = { |
828 | .probe = sta32x_probe, | |
829 | .remove = sta32x_remove, | |
830 | .suspend = sta32x_suspend, | |
831 | .resume = sta32x_resume, | |
832 | .reg_cache_size = STA32X_REGISTER_COUNT, | |
833 | .reg_word_size = sizeof(u8), | |
f0bbc2b5 | 834 | .reg_cache_default = sta32x_regs, |
79688439 | 835 | .volatile_register = sta32x_reg_is_volatile, |
c034abf6 JS |
836 | .set_bias_level = sta32x_set_bias_level, |
837 | .controls = sta32x_snd_controls, | |
838 | .num_controls = ARRAY_SIZE(sta32x_snd_controls), | |
839 | .dapm_widgets = sta32x_dapm_widgets, | |
840 | .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets), | |
841 | .dapm_routes = sta32x_dapm_routes, | |
842 | .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes), | |
843 | }; | |
844 | ||
845 | static __devinit int sta32x_i2c_probe(struct i2c_client *i2c, | |
846 | const struct i2c_device_id *id) | |
847 | { | |
848 | struct sta32x_priv *sta32x; | |
849 | int ret; | |
850 | ||
851 | sta32x = kzalloc(sizeof(struct sta32x_priv), GFP_KERNEL); | |
852 | if (!sta32x) | |
853 | return -ENOMEM; | |
854 | ||
855 | i2c_set_clientdata(i2c, sta32x); | |
856 | ||
857 | ret = snd_soc_register_codec(&i2c->dev, &sta32x_codec, &sta32x_dai, 1); | |
858 | if (ret != 0) { | |
859 | dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret); | |
161d55c3 | 860 | kfree(sta32x); |
c034abf6 JS |
861 | return ret; |
862 | } | |
863 | ||
864 | return 0; | |
865 | } | |
866 | ||
867 | static __devexit int sta32x_i2c_remove(struct i2c_client *client) | |
868 | { | |
869 | struct sta32x_priv *sta32x = i2c_get_clientdata(client); | |
c034abf6 | 870 | |
e3d73c1b | 871 | snd_soc_unregister_codec(&client->dev); |
c034abf6 JS |
872 | kfree(sta32x); |
873 | return 0; | |
874 | } | |
875 | ||
876 | static const struct i2c_device_id sta32x_i2c_id[] = { | |
877 | { "sta326", 0 }, | |
878 | { "sta328", 0 }, | |
879 | { "sta329", 0 }, | |
880 | { } | |
881 | }; | |
882 | MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id); | |
883 | ||
884 | static struct i2c_driver sta32x_i2c_driver = { | |
885 | .driver = { | |
886 | .name = "sta32x", | |
887 | .owner = THIS_MODULE, | |
888 | }, | |
889 | .probe = sta32x_i2c_probe, | |
890 | .remove = __devexit_p(sta32x_i2c_remove), | |
891 | .id_table = sta32x_i2c_id, | |
892 | }; | |
893 | ||
894 | static int __init sta32x_init(void) | |
895 | { | |
896 | return i2c_add_driver(&sta32x_i2c_driver); | |
897 | } | |
898 | module_init(sta32x_init); | |
899 | ||
900 | static void __exit sta32x_exit(void) | |
901 | { | |
902 | i2c_del_driver(&sta32x_i2c_driver); | |
903 | } | |
904 | module_exit(sta32x_exit); | |
905 | ||
906 | MODULE_DESCRIPTION("ASoC STA32X driver"); | |
907 | MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>"); | |
908 | MODULE_LICENSE("GPL"); |