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1 | /* |
2 | * ALSA SoC TLV320AIC31XX codec driver | |
3 | * | |
4 | * Copyright (C) 2014 Texas Instruments, Inc. | |
5 | * | |
6 | * Author: Jyri Sarha <jsarha@ti.com> | |
7 | * | |
8 | * Based on ground work by: Ajit Kulkarni <x0175765@ti.com> | |
9 | * | |
10 | * This package is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * THIS PACKAGE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR | |
15 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED | |
16 | * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
17 | * | |
18 | * The TLV320AIC31xx series of audio codec is a low-power, highly integrated | |
19 | * high performance codec which provides a stereo DAC, a mono ADC, | |
20 | * and mono/stereo Class-D speaker driver. | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/pm.h> | |
28 | #include <linux/i2c.h> | |
29 | #include <linux/gpio.h> | |
30 | #include <linux/regulator/consumer.h> | |
0faabc4f | 31 | #include <linux/of.h> |
e00447fa JS |
32 | #include <linux/of_gpio.h> |
33 | #include <linux/slab.h> | |
34 | #include <sound/core.h> | |
35 | #include <sound/pcm.h> | |
36 | #include <sound/pcm_params.h> | |
37 | #include <sound/soc.h> | |
38 | #include <sound/initval.h> | |
39 | #include <sound/tlv.h> | |
40 | #include <dt-bindings/sound/tlv320aic31xx-micbias.h> | |
41 | ||
42 | #include "tlv320aic31xx.h" | |
43 | ||
44 | static const struct reg_default aic31xx_reg_defaults[] = { | |
45 | { AIC31XX_CLKMUX, 0x00 }, | |
46 | { AIC31XX_PLLPR, 0x11 }, | |
47 | { AIC31XX_PLLJ, 0x04 }, | |
48 | { AIC31XX_PLLDMSB, 0x00 }, | |
49 | { AIC31XX_PLLDLSB, 0x00 }, | |
50 | { AIC31XX_NDAC, 0x01 }, | |
51 | { AIC31XX_MDAC, 0x01 }, | |
52 | { AIC31XX_DOSRMSB, 0x00 }, | |
53 | { AIC31XX_DOSRLSB, 0x80 }, | |
54 | { AIC31XX_NADC, 0x01 }, | |
55 | { AIC31XX_MADC, 0x01 }, | |
56 | { AIC31XX_AOSR, 0x80 }, | |
57 | { AIC31XX_IFACE1, 0x00 }, | |
58 | { AIC31XX_DATA_OFFSET, 0x00 }, | |
59 | { AIC31XX_IFACE2, 0x00 }, | |
60 | { AIC31XX_BCLKN, 0x01 }, | |
61 | { AIC31XX_DACSETUP, 0x14 }, | |
62 | { AIC31XX_DACMUTE, 0x0c }, | |
63 | { AIC31XX_LDACVOL, 0x00 }, | |
64 | { AIC31XX_RDACVOL, 0x00 }, | |
65 | { AIC31XX_ADCSETUP, 0x00 }, | |
66 | { AIC31XX_ADCFGA, 0x80 }, | |
67 | { AIC31XX_ADCVOL, 0x00 }, | |
68 | { AIC31XX_HPDRIVER, 0x04 }, | |
69 | { AIC31XX_SPKAMP, 0x06 }, | |
70 | { AIC31XX_DACMIXERROUTE, 0x00 }, | |
71 | { AIC31XX_LANALOGHPL, 0x7f }, | |
72 | { AIC31XX_RANALOGHPR, 0x7f }, | |
73 | { AIC31XX_LANALOGSPL, 0x7f }, | |
74 | { AIC31XX_RANALOGSPR, 0x7f }, | |
75 | { AIC31XX_HPLGAIN, 0x02 }, | |
76 | { AIC31XX_HPRGAIN, 0x02 }, | |
77 | { AIC31XX_SPLGAIN, 0x00 }, | |
78 | { AIC31XX_SPRGAIN, 0x00 }, | |
79 | { AIC31XX_MICBIAS, 0x00 }, | |
80 | { AIC31XX_MICPGA, 0x80 }, | |
81 | { AIC31XX_MICPGAPI, 0x00 }, | |
82 | { AIC31XX_MICPGAMI, 0x00 }, | |
83 | }; | |
84 | ||
85 | static bool aic31xx_volatile(struct device *dev, unsigned int reg) | |
86 | { | |
87 | switch (reg) { | |
88 | case AIC31XX_PAGECTL: /* regmap implementation requires this */ | |
89 | case AIC31XX_RESET: /* always clears after write */ | |
90 | case AIC31XX_OT_FLAG: | |
91 | case AIC31XX_ADCFLAG: | |
92 | case AIC31XX_DACFLAG1: | |
93 | case AIC31XX_DACFLAG2: | |
94 | case AIC31XX_OFFLAG: /* Sticky interrupt flags */ | |
95 | case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ | |
96 | case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ | |
97 | case AIC31XX_INTRDACFLAG2: | |
98 | case AIC31XX_INTRADCFLAG2: | |
99 | return true; | |
100 | } | |
101 | return false; | |
102 | } | |
103 | ||
104 | static bool aic31xx_writeable(struct device *dev, unsigned int reg) | |
105 | { | |
106 | switch (reg) { | |
107 | case AIC31XX_OT_FLAG: | |
108 | case AIC31XX_ADCFLAG: | |
109 | case AIC31XX_DACFLAG1: | |
110 | case AIC31XX_DACFLAG2: | |
111 | case AIC31XX_OFFLAG: /* Sticky interrupt flags */ | |
112 | case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ | |
113 | case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ | |
114 | case AIC31XX_INTRDACFLAG2: | |
115 | case AIC31XX_INTRADCFLAG2: | |
116 | return false; | |
117 | } | |
118 | return true; | |
119 | } | |
120 | ||
121 | static const struct regmap_range_cfg aic31xx_ranges[] = { | |
122 | { | |
123 | .range_min = 0, | |
124 | .range_max = 12 * 128, | |
125 | .selector_reg = AIC31XX_PAGECTL, | |
126 | .selector_mask = 0xff, | |
127 | .selector_shift = 0, | |
128 | .window_start = 0, | |
129 | .window_len = 128, | |
130 | }, | |
131 | }; | |
132 | ||
9296f4da | 133 | static const struct regmap_config aic31xx_i2c_regmap = { |
e00447fa JS |
134 | .reg_bits = 8, |
135 | .val_bits = 8, | |
136 | .writeable_reg = aic31xx_writeable, | |
137 | .volatile_reg = aic31xx_volatile, | |
138 | .reg_defaults = aic31xx_reg_defaults, | |
139 | .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), | |
140 | .cache_type = REGCACHE_RBTREE, | |
141 | .ranges = aic31xx_ranges, | |
142 | .num_ranges = ARRAY_SIZE(aic31xx_ranges), | |
143 | .max_register = 12 * 128, | |
144 | }; | |
145 | ||
146 | #define AIC31XX_NUM_SUPPLIES 6 | |
147 | static const char * const aic31xx_supply_names[AIC31XX_NUM_SUPPLIES] = { | |
148 | "HPVDD", | |
149 | "SPRVDD", | |
150 | "SPLVDD", | |
151 | "AVDD", | |
152 | "IOVDD", | |
153 | "DVDD", | |
154 | }; | |
155 | ||
156 | struct aic31xx_disable_nb { | |
157 | struct notifier_block nb; | |
158 | struct aic31xx_priv *aic31xx; | |
159 | }; | |
160 | ||
161 | struct aic31xx_priv { | |
162 | struct snd_soc_codec *codec; | |
163 | u8 i2c_regs_status; | |
164 | struct device *dev; | |
165 | struct regmap *regmap; | |
166 | struct aic31xx_pdata pdata; | |
167 | struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; | |
168 | struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; | |
169 | unsigned int sysclk; | |
170 | int rate_div_line; | |
171 | }; | |
172 | ||
173 | struct aic31xx_rate_divs { | |
174 | u32 mclk; | |
175 | u32 rate; | |
176 | u8 p_val; | |
177 | u8 pll_j; | |
178 | u16 pll_d; | |
179 | u16 dosr; | |
180 | u8 ndac; | |
181 | u8 mdac; | |
182 | u8 aosr; | |
183 | u8 nadc; | |
184 | u8 madc; | |
185 | }; | |
186 | ||
187 | /* ADC dividers can be disabled by cofiguring them to 0 */ | |
188 | static const struct aic31xx_rate_divs aic31xx_divs[] = { | |
189 | /* mclk rate pll: p j d dosr ndac mdac aors nadc madc */ | |
190 | /* 8k rate */ | |
191 | {12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2}, | |
192 | {24000000, 8000, 2, 8, 1920, 128, 48, 2, 128, 48, 2}, | |
193 | {25000000, 8000, 2, 7, 8643, 128, 48, 2, 128, 48, 2}, | |
194 | /* 11.025k rate */ | |
195 | {12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2}, | |
196 | {24000000, 11025, 2, 7, 5264, 128, 32, 2, 128, 32, 2}, | |
197 | {25000000, 11025, 2, 7, 2253, 128, 32, 2, 128, 32, 2}, | |
198 | /* 16k rate */ | |
199 | {12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2}, | |
200 | {24000000, 16000, 2, 8, 1920, 128, 24, 2, 128, 24, 2}, | |
201 | {25000000, 16000, 2, 7, 8643, 128, 24, 2, 128, 24, 2}, | |
202 | /* 22.05k rate */ | |
203 | {12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2}, | |
204 | {24000000, 22050, 2, 7, 5264, 128, 16, 2, 128, 16, 2}, | |
205 | {25000000, 22050, 2, 7, 2253, 128, 16, 2, 128, 16, 2}, | |
206 | /* 32k rate */ | |
207 | {12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2}, | |
208 | {24000000, 32000, 2, 8, 1920, 128, 12, 2, 128, 12, 2}, | |
209 | {25000000, 32000, 2, 7, 8643, 128, 12, 2, 128, 12, 2}, | |
210 | /* 44.1k rate */ | |
211 | {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2}, | |
212 | {24000000, 44100, 2, 7, 5264, 128, 8, 2, 128, 8, 2}, | |
213 | {25000000, 44100, 2, 7, 2253, 128, 8, 2, 128, 8, 2}, | |
214 | /* 48k rate */ | |
215 | {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2}, | |
216 | {24000000, 48000, 2, 8, 1920, 128, 8, 2, 128, 8, 2}, | |
217 | {25000000, 48000, 2, 7, 8643, 128, 8, 2, 128, 8, 2}, | |
218 | /* 88.2k rate */ | |
219 | {12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2}, | |
220 | {24000000, 88200, 2, 7, 5264, 64, 8, 2, 64, 8, 2}, | |
221 | {25000000, 88200, 2, 7, 2253, 64, 8, 2, 64, 8, 2}, | |
222 | /* 96k rate */ | |
223 | {12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2}, | |
224 | {24000000, 96000, 2, 8, 1920, 64, 8, 2, 64, 8, 2}, | |
225 | {25000000, 96000, 2, 7, 8643, 64, 8, 2, 64, 8, 2}, | |
226 | /* 176.4k rate */ | |
227 | {12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2}, | |
228 | {24000000, 176400, 2, 7, 5264, 32, 8, 2, 32, 8, 2}, | |
229 | {25000000, 176400, 2, 7, 2253, 32, 8, 2, 32, 8, 2}, | |
230 | /* 192k rate */ | |
231 | {12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2}, | |
232 | {24000000, 192000, 2, 8, 1920, 32, 8, 2, 32, 8, 2}, | |
233 | {25000000, 192000, 2, 7, 8643, 32, 8, 2, 32, 8, 2}, | |
234 | }; | |
235 | ||
236 | static const char * const ldac_in_text[] = { | |
237 | "Off", "Left Data", "Right Data", "Mono" | |
238 | }; | |
239 | ||
240 | static const char * const rdac_in_text[] = { | |
241 | "Off", "Right Data", "Left Data", "Mono" | |
242 | }; | |
243 | ||
244 | static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); | |
245 | ||
246 | static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); | |
247 | ||
248 | static const char * const mic_select_text[] = { | |
249 | "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" | |
250 | }; | |
251 | ||
252 | static const | |
253 | SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, mic_select_text); | |
254 | static const | |
255 | SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, mic_select_text); | |
256 | static const | |
257 | SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, mic_select_text); | |
258 | ||
259 | static const | |
260 | SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text); | |
261 | static const | |
262 | SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, mic_select_text); | |
263 | ||
264 | static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); | |
265 | static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); | |
266 | static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); | |
267 | static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); | |
268 | static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); | |
269 | static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); | |
270 | static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); | |
271 | static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); | |
272 | ||
273 | /* | |
274 | * controls to be exported to the user space | |
275 | */ | |
276 | static const struct snd_kcontrol_new aic31xx_snd_controls[] = { | |
277 | SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, | |
278 | AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), | |
279 | ||
280 | SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, | |
281 | adc_fgain_tlv), | |
282 | ||
283 | SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), | |
284 | SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, | |
285 | 0, -24, 40, 6, 0, adc_cgain_tlv), | |
286 | ||
287 | SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, | |
288 | 119, 0, mic_pga_tlv), | |
289 | ||
290 | SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, | |
291 | AIC31XX_HPRGAIN, 2, 1, 0), | |
292 | SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, | |
293 | AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), | |
294 | ||
295 | SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, | |
296 | AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), | |
297 | }; | |
298 | ||
299 | static const struct snd_kcontrol_new aic311x_snd_controls[] = { | |
300 | SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, | |
301 | AIC31XX_SPRGAIN, 2, 1, 0), | |
302 | SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, | |
303 | AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), | |
304 | ||
305 | SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, | |
306 | AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), | |
307 | }; | |
308 | ||
309 | static const struct snd_kcontrol_new aic310x_snd_controls[] = { | |
310 | SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, | |
311 | 2, 1, 0), | |
312 | SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, | |
313 | 3, 3, 0, class_D_drv_tlv), | |
314 | ||
315 | SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, | |
316 | 0, 0x7F, 1, sp_vol_tlv), | |
317 | }; | |
318 | ||
319 | static const struct snd_kcontrol_new ldac_in_control = | |
320 | SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); | |
321 | ||
322 | static const struct snd_kcontrol_new rdac_in_control = | |
323 | SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); | |
324 | ||
9296f4da MB |
325 | static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, |
326 | unsigned int mask, unsigned int wbits, int sleep, | |
327 | int count) | |
e00447fa JS |
328 | { |
329 | unsigned int bits; | |
330 | int counter = count; | |
331 | int ret = regmap_read(aic31xx->regmap, reg, &bits); | |
332 | while ((bits & mask) != wbits && counter && !ret) { | |
333 | usleep_range(sleep, sleep * 2); | |
334 | ret = regmap_read(aic31xx->regmap, reg, &bits); | |
335 | counter--; | |
336 | } | |
337 | if ((bits & mask) != wbits) { | |
338 | dev_err(aic31xx->dev, | |
339 | "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", | |
340 | __func__, reg, bits, wbits, ret, mask, | |
341 | (count - counter) * sleep); | |
342 | ret = -1; | |
343 | } | |
344 | return ret; | |
345 | } | |
346 | ||
347 | #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) | |
348 | ||
349 | static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w, | |
350 | struct snd_kcontrol *kcontrol, int event) | |
351 | { | |
352 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(w->codec); | |
353 | unsigned int reg = AIC31XX_DACFLAG1; | |
354 | unsigned int mask; | |
355 | ||
356 | switch (WIDGET_BIT(w->reg, w->shift)) { | |
357 | case WIDGET_BIT(AIC31XX_DACSETUP, 7): | |
358 | mask = AIC31XX_LDACPWRSTATUS_MASK; | |
359 | break; | |
360 | case WIDGET_BIT(AIC31XX_DACSETUP, 6): | |
361 | mask = AIC31XX_RDACPWRSTATUS_MASK; | |
362 | break; | |
363 | case WIDGET_BIT(AIC31XX_HPDRIVER, 7): | |
364 | mask = AIC31XX_HPLDRVPWRSTATUS_MASK; | |
365 | break; | |
366 | case WIDGET_BIT(AIC31XX_HPDRIVER, 6): | |
367 | mask = AIC31XX_HPRDRVPWRSTATUS_MASK; | |
368 | break; | |
369 | case WIDGET_BIT(AIC31XX_SPKAMP, 7): | |
370 | mask = AIC31XX_SPLDRVPWRSTATUS_MASK; | |
371 | break; | |
372 | case WIDGET_BIT(AIC31XX_SPKAMP, 6): | |
373 | mask = AIC31XX_SPRDRVPWRSTATUS_MASK; | |
374 | break; | |
375 | case WIDGET_BIT(AIC31XX_ADCSETUP, 7): | |
376 | mask = AIC31XX_ADCPWRSTATUS_MASK; | |
377 | reg = AIC31XX_ADCFLAG; | |
378 | break; | |
379 | default: | |
2a1c23e3 | 380 | dev_err(w->codec->dev, "Unknown widget '%s' calling %s\n", |
e00447fa JS |
381 | w->name, __func__); |
382 | return -EINVAL; | |
383 | } | |
384 | ||
385 | switch (event) { | |
386 | case SND_SOC_DAPM_POST_PMU: | |
387 | return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100); | |
388 | case SND_SOC_DAPM_POST_PMD: | |
389 | return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100); | |
390 | default: | |
391 | dev_dbg(w->codec->dev, | |
392 | "Unhandled dapm widget event %d from %s\n", | |
393 | event, w->name); | |
394 | } | |
395 | return 0; | |
396 | } | |
397 | ||
398 | static const struct snd_kcontrol_new left_output_switches[] = { | |
399 | SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), | |
400 | SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0), | |
401 | SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0), | |
402 | }; | |
403 | ||
404 | static const struct snd_kcontrol_new right_output_switches[] = { | |
405 | SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), | |
406 | SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0), | |
407 | }; | |
408 | ||
409 | static const struct snd_kcontrol_new p_term_mic1lp = | |
410 | SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum); | |
411 | ||
412 | static const struct snd_kcontrol_new p_term_mic1rp = | |
413 | SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum); | |
414 | ||
415 | static const struct snd_kcontrol_new p_term_mic1lm = | |
416 | SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum); | |
417 | ||
418 | static const struct snd_kcontrol_new m_term_mic1lm = | |
419 | SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum); | |
420 | ||
421 | static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch = | |
422 | SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0); | |
423 | ||
424 | static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch = | |
425 | SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0); | |
426 | ||
427 | static const struct snd_kcontrol_new aic31xx_dapm_spl_switch = | |
428 | SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0); | |
429 | ||
430 | static const struct snd_kcontrol_new aic31xx_dapm_spr_switch = | |
431 | SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0); | |
432 | ||
433 | static int mic_bias_event(struct snd_soc_dapm_widget *w, | |
434 | struct snd_kcontrol *kcontrol, int event) | |
435 | { | |
436 | struct snd_soc_codec *codec = w->codec; | |
437 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
438 | switch (event) { | |
439 | case SND_SOC_DAPM_POST_PMU: | |
440 | /* change mic bias voltage to user defined */ | |
441 | snd_soc_update_bits(codec, AIC31XX_MICBIAS, | |
442 | AIC31XX_MICBIAS_MASK, | |
443 | aic31xx->pdata.micbias_vg << | |
444 | AIC31XX_MICBIAS_SHIFT); | |
445 | dev_dbg(codec->dev, "%s: turned on\n", __func__); | |
446 | break; | |
447 | case SND_SOC_DAPM_PRE_PMD: | |
448 | /* turn mic bias off */ | |
449 | snd_soc_update_bits(codec, AIC31XX_MICBIAS, | |
450 | AIC31XX_MICBIAS_MASK, 0); | |
451 | dev_dbg(codec->dev, "%s: turned off\n", __func__); | |
452 | break; | |
453 | } | |
454 | return 0; | |
455 | } | |
456 | ||
457 | static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = { | |
458 | SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0), | |
459 | ||
460 | SND_SOC_DAPM_MUX("DAC Left Input", | |
461 | SND_SOC_NOPM, 0, 0, &ldac_in_control), | |
462 | SND_SOC_DAPM_MUX("DAC Right Input", | |
463 | SND_SOC_NOPM, 0, 0, &rdac_in_control), | |
464 | /* DACs */ | |
465 | SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback", | |
466 | AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event, | |
467 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
468 | ||
469 | SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback", | |
470 | AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event, | |
471 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
472 | ||
473 | /* Output Mixers */ | |
474 | SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, | |
475 | left_output_switches, | |
476 | ARRAY_SIZE(left_output_switches)), | |
477 | SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, | |
478 | right_output_switches, | |
479 | ARRAY_SIZE(right_output_switches)), | |
480 | ||
481 | SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0, | |
482 | &aic31xx_dapm_hpl_switch), | |
483 | SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0, | |
484 | &aic31xx_dapm_hpr_switch), | |
485 | ||
486 | /* Output drivers */ | |
487 | SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0, | |
488 | NULL, 0, aic31xx_dapm_power_event, | |
489 | SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), | |
490 | SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0, | |
491 | NULL, 0, aic31xx_dapm_power_event, | |
492 | SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), | |
493 | ||
494 | /* ADC */ | |
495 | SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0, | |
496 | aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | | |
497 | SND_SOC_DAPM_POST_PMD), | |
498 | ||
499 | /* Input Selection to MIC_PGA */ | |
500 | SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0, | |
501 | &p_term_mic1lp), | |
502 | SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0, | |
503 | &p_term_mic1rp), | |
504 | SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0, | |
505 | &p_term_mic1lm), | |
506 | ||
507 | SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0, | |
508 | &m_term_mic1lm), | |
509 | /* Enabling & Disabling MIC Gain Ctl */ | |
510 | SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA, | |
511 | 7, 1, NULL, 0), | |
512 | ||
513 | /* Mic Bias */ | |
514 | SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event, | |
515 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
516 | ||
517 | /* Outputs */ | |
518 | SND_SOC_DAPM_OUTPUT("HPL"), | |
519 | SND_SOC_DAPM_OUTPUT("HPR"), | |
520 | ||
521 | /* Inputs */ | |
522 | SND_SOC_DAPM_INPUT("MIC1LP"), | |
523 | SND_SOC_DAPM_INPUT("MIC1RP"), | |
524 | SND_SOC_DAPM_INPUT("MIC1LM"), | |
525 | }; | |
526 | ||
527 | static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = { | |
528 | /* AIC3111 and AIC3110 have stereo class-D amplifier */ | |
529 | SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, | |
530 | aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | | |
531 | SND_SOC_DAPM_POST_PMD), | |
532 | SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0, | |
533 | aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | | |
534 | SND_SOC_DAPM_POST_PMD), | |
535 | SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0, | |
536 | &aic31xx_dapm_spl_switch), | |
537 | SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0, | |
538 | &aic31xx_dapm_spr_switch), | |
539 | SND_SOC_DAPM_OUTPUT("SPL"), | |
540 | SND_SOC_DAPM_OUTPUT("SPR"), | |
541 | }; | |
542 | ||
543 | /* AIC3100 and AIC3120 have only mono class-D amplifier */ | |
544 | static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = { | |
545 | SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, | |
546 | aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | | |
547 | SND_SOC_DAPM_POST_PMD), | |
548 | SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0, | |
549 | &aic31xx_dapm_spl_switch), | |
550 | SND_SOC_DAPM_OUTPUT("SPK"), | |
551 | }; | |
552 | ||
553 | static const struct snd_soc_dapm_route | |
554 | aic31xx_audio_map[] = { | |
555 | /* DAC Input Routing */ | |
556 | {"DAC Left Input", "Left Data", "DAC IN"}, | |
557 | {"DAC Left Input", "Right Data", "DAC IN"}, | |
558 | {"DAC Left Input", "Mono", "DAC IN"}, | |
559 | {"DAC Right Input", "Left Data", "DAC IN"}, | |
560 | {"DAC Right Input", "Right Data", "DAC IN"}, | |
561 | {"DAC Right Input", "Mono", "DAC IN"}, | |
562 | {"DAC Left", NULL, "DAC Left Input"}, | |
563 | {"DAC Right", NULL, "DAC Right Input"}, | |
564 | ||
565 | /* Mic input */ | |
566 | {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"}, | |
567 | {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"}, | |
568 | {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"}, | |
569 | {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"}, | |
570 | {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"}, | |
571 | {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"}, | |
572 | {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"}, | |
573 | {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"}, | |
574 | {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"}, | |
575 | ||
576 | {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"}, | |
577 | {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"}, | |
578 | {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"}, | |
579 | ||
580 | {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"}, | |
581 | {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"}, | |
582 | {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"}, | |
583 | {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"}, | |
584 | ||
585 | {"ADC", NULL, "MIC_GAIN_CTL"}, | |
586 | ||
587 | /* Left Output */ | |
588 | {"Output Left", "From Left DAC", "DAC Left"}, | |
589 | {"Output Left", "From MIC1LP", "MIC1LP"}, | |
590 | {"Output Left", "From MIC1RP", "MIC1RP"}, | |
591 | ||
592 | /* Right Output */ | |
593 | {"Output Right", "From Right DAC", "DAC Right"}, | |
594 | {"Output Right", "From MIC1RP", "MIC1RP"}, | |
595 | ||
596 | /* HPL path */ | |
597 | {"HP Left", "Switch", "Output Left"}, | |
598 | {"HPL Driver", NULL, "HP Left"}, | |
599 | {"HPL", NULL, "HPL Driver"}, | |
600 | ||
601 | /* HPR path */ | |
602 | {"HP Right", "Switch", "Output Right"}, | |
603 | {"HPR Driver", NULL, "HP Right"}, | |
604 | {"HPR", NULL, "HPR Driver"}, | |
605 | }; | |
606 | ||
607 | static const struct snd_soc_dapm_route | |
608 | aic311x_audio_map[] = { | |
609 | /* SP L path */ | |
610 | {"Speaker Left", "Switch", "Output Left"}, | |
611 | {"SPL ClassD", NULL, "Speaker Left"}, | |
612 | {"SPL", NULL, "SPL ClassD"}, | |
613 | ||
614 | /* SP R path */ | |
615 | {"Speaker Right", "Switch", "Output Right"}, | |
616 | {"SPR ClassD", NULL, "Speaker Right"}, | |
617 | {"SPR", NULL, "SPR ClassD"}, | |
618 | }; | |
619 | ||
620 | static const struct snd_soc_dapm_route | |
621 | aic310x_audio_map[] = { | |
622 | /* SP L path */ | |
623 | {"Speaker", "Switch", "Output Left"}, | |
624 | {"SPK ClassD", NULL, "Speaker"}, | |
625 | {"SPK", NULL, "SPK ClassD"}, | |
626 | }; | |
627 | ||
628 | static int aic31xx_add_controls(struct snd_soc_codec *codec) | |
629 | { | |
630 | int ret = 0; | |
631 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
632 | ||
633 | if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) | |
634 | ret = snd_soc_add_codec_controls( | |
635 | codec, aic311x_snd_controls, | |
636 | ARRAY_SIZE(aic311x_snd_controls)); | |
637 | else | |
638 | ret = snd_soc_add_codec_controls( | |
639 | codec, aic310x_snd_controls, | |
640 | ARRAY_SIZE(aic310x_snd_controls)); | |
641 | ||
642 | return ret; | |
643 | } | |
644 | ||
645 | static int aic31xx_add_widgets(struct snd_soc_codec *codec) | |
646 | { | |
647 | struct snd_soc_dapm_context *dapm = &codec->dapm; | |
648 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
649 | int ret = 0; | |
650 | ||
651 | if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) { | |
652 | ret = snd_soc_dapm_new_controls( | |
653 | dapm, aic311x_dapm_widgets, | |
654 | ARRAY_SIZE(aic311x_dapm_widgets)); | |
655 | if (ret) | |
656 | return ret; | |
657 | ||
658 | ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map, | |
659 | ARRAY_SIZE(aic311x_audio_map)); | |
660 | if (ret) | |
661 | return ret; | |
662 | } else { | |
663 | ret = snd_soc_dapm_new_controls( | |
664 | dapm, aic310x_dapm_widgets, | |
665 | ARRAY_SIZE(aic310x_dapm_widgets)); | |
666 | if (ret) | |
667 | return ret; | |
668 | ||
669 | ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map, | |
670 | ARRAY_SIZE(aic310x_audio_map)); | |
671 | if (ret) | |
672 | return ret; | |
673 | } | |
674 | ||
675 | return 0; | |
676 | } | |
677 | ||
678 | static int aic31xx_setup_pll(struct snd_soc_codec *codec, | |
679 | struct snd_pcm_hw_params *params) | |
680 | { | |
681 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
682 | int bclk_n = 0; | |
683 | int i; | |
684 | ||
685 | /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ | |
686 | snd_soc_update_bits(codec, AIC31XX_CLKMUX, | |
687 | AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); | |
688 | snd_soc_update_bits(codec, AIC31XX_IFACE2, | |
689 | AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); | |
690 | ||
691 | for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { | |
692 | if (aic31xx_divs[i].rate == params_rate(params) && | |
693 | aic31xx_divs[i].mclk == aic31xx->sysclk) | |
694 | break; | |
695 | } | |
696 | ||
697 | if (i == ARRAY_SIZE(aic31xx_divs)) { | |
698 | dev_err(codec->dev, "%s: Sampling rate %u not supported\n", | |
699 | __func__, params_rate(params)); | |
700 | return -EINVAL; | |
701 | } | |
702 | ||
703 | /* PLL configuration */ | |
704 | snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK, | |
705 | (aic31xx_divs[i].p_val << 4) | 0x01); | |
706 | snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); | |
707 | ||
708 | snd_soc_write(codec, AIC31XX_PLLDMSB, | |
709 | aic31xx_divs[i].pll_d >> 8); | |
710 | snd_soc_write(codec, AIC31XX_PLLDLSB, | |
711 | aic31xx_divs[i].pll_d & 0xff); | |
712 | ||
713 | /* DAC dividers configuration */ | |
714 | snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK, | |
715 | aic31xx_divs[i].ndac); | |
716 | snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK, | |
717 | aic31xx_divs[i].mdac); | |
718 | ||
719 | snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); | |
720 | snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); | |
721 | ||
722 | /* ADC dividers configuration. Write reset value 1 if not used. */ | |
723 | snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK, | |
724 | aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); | |
725 | snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK, | |
726 | aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); | |
727 | ||
728 | snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr); | |
729 | ||
730 | /* Bit clock divider configuration. */ | |
731 | bclk_n = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) | |
732 | / snd_soc_params_to_frame_size(params); | |
733 | if (bclk_n == 0) { | |
734 | dev_err(codec->dev, "%s: Not enough BLCK bandwidth\n", | |
735 | __func__); | |
736 | return -EINVAL; | |
737 | } | |
738 | ||
739 | snd_soc_update_bits(codec, AIC31XX_BCLKN, | |
740 | AIC31XX_PLL_MASK, bclk_n); | |
741 | ||
742 | aic31xx->rate_div_line = i; | |
743 | ||
744 | dev_dbg(codec->dev, | |
745 | "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", | |
746 | aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d, | |
747 | aic31xx_divs[i].p_val, aic31xx_divs[i].dosr, | |
748 | aic31xx_divs[i].ndac, aic31xx_divs[i].mdac, | |
749 | aic31xx_divs[i].aosr, aic31xx_divs[i].nadc, | |
750 | aic31xx_divs[i].madc, bclk_n); | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | static int aic31xx_hw_params(struct snd_pcm_substream *substream, | |
756 | struct snd_pcm_hw_params *params, | |
ab64246c | 757 | struct snd_soc_dai *dai) |
e00447fa | 758 | { |
ab64246c | 759 | struct snd_soc_codec *codec = dai->codec; |
e00447fa JS |
760 | u8 data = 0; |
761 | ||
762 | dev_dbg(codec->dev, "## %s: format %d width %d rate %d\n", | |
763 | __func__, params_format(params), params_width(params), | |
764 | params_rate(params)); | |
765 | ||
766 | switch (params_width(params)) { | |
767 | case 16: | |
768 | break; | |
769 | case 20: | |
770 | data = (AIC31XX_WORD_LEN_20BITS << | |
771 | AIC31XX_IFACE1_DATALEN_SHIFT); | |
772 | break; | |
773 | case 24: | |
774 | data = (AIC31XX_WORD_LEN_24BITS << | |
775 | AIC31XX_IFACE1_DATALEN_SHIFT); | |
776 | break; | |
777 | case 32: | |
778 | data = (AIC31XX_WORD_LEN_32BITS << | |
779 | AIC31XX_IFACE1_DATALEN_SHIFT); | |
780 | break; | |
781 | default: | |
782 | dev_err(codec->dev, "%s: Unsupported format %d\n", | |
783 | __func__, params_format(params)); | |
784 | return -EINVAL; | |
785 | } | |
786 | ||
787 | snd_soc_update_bits(codec, AIC31XX_IFACE1, | |
788 | AIC31XX_IFACE1_DATALEN_MASK, | |
789 | data); | |
790 | ||
791 | return aic31xx_setup_pll(codec, params); | |
792 | } | |
793 | ||
794 | static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute) | |
795 | { | |
796 | struct snd_soc_codec *codec = codec_dai->codec; | |
797 | ||
798 | if (mute) { | |
799 | snd_soc_update_bits(codec, AIC31XX_DACMUTE, | |
800 | AIC31XX_DACMUTE_MASK, | |
801 | AIC31XX_DACMUTE_MASK); | |
802 | } else { | |
803 | snd_soc_update_bits(codec, AIC31XX_DACMUTE, | |
804 | AIC31XX_DACMUTE_MASK, 0x0); | |
805 | } | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
811 | unsigned int fmt) | |
812 | { | |
813 | struct snd_soc_codec *codec = codec_dai->codec; | |
814 | u8 iface_reg1 = 0; | |
815 | u8 iface_reg3 = 0; | |
816 | u8 dsp_a_val = 0; | |
817 | ||
818 | dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt); | |
819 | ||
820 | /* set master/slave audio interface */ | |
821 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
822 | case SND_SOC_DAIFMT_CBM_CFM: | |
823 | iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER; | |
824 | break; | |
825 | default: | |
826 | dev_alert(codec->dev, "Invalid DAI master/slave interface\n"); | |
827 | return -EINVAL; | |
828 | } | |
829 | ||
830 | /* interface format */ | |
831 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
832 | case SND_SOC_DAIFMT_I2S: | |
833 | break; | |
834 | case SND_SOC_DAIFMT_DSP_A: | |
835 | dsp_a_val = 0x1; | |
836 | case SND_SOC_DAIFMT_DSP_B: | |
837 | /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */ | |
838 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
839 | case SND_SOC_DAIFMT_NB_NF: | |
840 | iface_reg3 |= AIC31XX_BCLKINV_MASK; | |
841 | break; | |
842 | case SND_SOC_DAIFMT_IB_NF: | |
843 | break; | |
844 | default: | |
845 | return -EINVAL; | |
846 | } | |
847 | iface_reg1 |= (AIC31XX_DSP_MODE << | |
848 | AIC31XX_IFACE1_DATATYPE_SHIFT); | |
849 | break; | |
850 | case SND_SOC_DAIFMT_RIGHT_J: | |
851 | iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE << | |
852 | AIC31XX_IFACE1_DATATYPE_SHIFT); | |
853 | break; | |
854 | case SND_SOC_DAIFMT_LEFT_J: | |
855 | iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE << | |
856 | AIC31XX_IFACE1_DATATYPE_SHIFT); | |
857 | break; | |
858 | default: | |
859 | dev_err(codec->dev, "Invalid DAI interface format\n"); | |
860 | return -EINVAL; | |
861 | } | |
862 | ||
863 | snd_soc_update_bits(codec, AIC31XX_IFACE1, | |
864 | AIC31XX_IFACE1_DATATYPE_MASK | | |
865 | AIC31XX_IFACE1_MASTER_MASK, | |
866 | iface_reg1); | |
867 | snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET, | |
868 | AIC31XX_DATA_OFFSET_MASK, | |
869 | dsp_a_val); | |
870 | snd_soc_update_bits(codec, AIC31XX_IFACE2, | |
871 | AIC31XX_BCLKINV_MASK, | |
872 | iface_reg3); | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
877 | static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
878 | int clk_id, unsigned int freq, int dir) | |
879 | { | |
880 | struct snd_soc_codec *codec = codec_dai->codec; | |
881 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
882 | int i; | |
883 | ||
884 | dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", | |
885 | __func__, clk_id, freq, dir); | |
886 | ||
887 | for (i = 0; aic31xx_divs[i].mclk != freq; i++) { | |
888 | if (i == ARRAY_SIZE(aic31xx_divs)) { | |
889 | dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", | |
890 | __func__, freq); | |
891 | return -EINVAL; | |
892 | } | |
893 | } | |
894 | ||
895 | /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ | |
896 | snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK, | |
897 | clk_id << AIC31XX_PLL_CLKIN_SHIFT); | |
898 | ||
899 | aic31xx->sysclk = freq; | |
900 | return 0; | |
901 | } | |
902 | ||
903 | static int aic31xx_regulator_event(struct notifier_block *nb, | |
904 | unsigned long event, void *data) | |
905 | { | |
906 | struct aic31xx_disable_nb *disable_nb = | |
907 | container_of(nb, struct aic31xx_disable_nb, nb); | |
908 | struct aic31xx_priv *aic31xx = disable_nb->aic31xx; | |
909 | ||
910 | if (event & REGULATOR_EVENT_DISABLE) { | |
911 | /* | |
912 | * Put codec to reset and as at least one of the | |
913 | * supplies was disabled. | |
914 | */ | |
915 | if (gpio_is_valid(aic31xx->pdata.gpio_reset)) | |
916 | gpio_set_value(aic31xx->pdata.gpio_reset, 0); | |
917 | ||
918 | regcache_mark_dirty(aic31xx->regmap); | |
919 | dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); | |
920 | } | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
925 | static void aic31xx_clk_on(struct snd_soc_codec *codec) | |
926 | { | |
927 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
928 | u8 mask = AIC31XX_PM_MASK; | |
929 | u8 on = AIC31XX_PM_MASK; | |
930 | ||
931 | dev_dbg(codec->dev, "codec clock -> on (rate %d)\n", | |
932 | aic31xx_divs[aic31xx->rate_div_line].rate); | |
933 | snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on); | |
934 | mdelay(10); | |
935 | snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on); | |
936 | snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on); | |
937 | if (aic31xx_divs[aic31xx->rate_div_line].nadc) | |
938 | snd_soc_update_bits(codec, AIC31XX_NADC, mask, on); | |
939 | if (aic31xx_divs[aic31xx->rate_div_line].madc) | |
940 | snd_soc_update_bits(codec, AIC31XX_MADC, mask, on); | |
941 | snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on); | |
942 | } | |
943 | ||
944 | static void aic31xx_clk_off(struct snd_soc_codec *codec) | |
945 | { | |
e00447fa JS |
946 | u8 mask = AIC31XX_PM_MASK; |
947 | u8 off = 0; | |
948 | ||
949 | dev_dbg(codec->dev, "codec clock -> off\n"); | |
950 | snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off); | |
951 | snd_soc_update_bits(codec, AIC31XX_MADC, mask, off); | |
952 | snd_soc_update_bits(codec, AIC31XX_NADC, mask, off); | |
953 | snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off); | |
954 | snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off); | |
955 | snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off); | |
956 | } | |
957 | ||
958 | static int aic31xx_power_on(struct snd_soc_codec *codec) | |
959 | { | |
960 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
961 | int ret = 0; | |
962 | ||
963 | ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), | |
964 | aic31xx->supplies); | |
965 | if (ret) | |
966 | return ret; | |
967 | ||
968 | if (gpio_is_valid(aic31xx->pdata.gpio_reset)) { | |
969 | gpio_set_value(aic31xx->pdata.gpio_reset, 1); | |
970 | udelay(100); | |
971 | } | |
972 | regcache_cache_only(aic31xx->regmap, false); | |
973 | ret = regcache_sync(aic31xx->regmap); | |
974 | if (ret != 0) { | |
975 | dev_err(codec->dev, | |
976 | "Failed to restore cache: %d\n", ret); | |
977 | regcache_cache_only(aic31xx->regmap, true); | |
978 | regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), | |
979 | aic31xx->supplies); | |
980 | return ret; | |
981 | } | |
982 | return 0; | |
983 | } | |
984 | ||
985 | static int aic31xx_power_off(struct snd_soc_codec *codec) | |
986 | { | |
987 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
988 | int ret = 0; | |
989 | ||
990 | regcache_cache_only(aic31xx->regmap, true); | |
991 | ret = regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), | |
992 | aic31xx->supplies); | |
993 | ||
994 | return ret; | |
995 | } | |
996 | ||
997 | static int aic31xx_set_bias_level(struct snd_soc_codec *codec, | |
998 | enum snd_soc_bias_level level) | |
999 | { | |
1000 | dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__, | |
1001 | codec->dapm.bias_level, level); | |
1002 | ||
1003 | switch (level) { | |
1004 | case SND_SOC_BIAS_ON: | |
1005 | break; | |
1006 | case SND_SOC_BIAS_PREPARE: | |
1007 | if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) | |
1008 | aic31xx_clk_on(codec); | |
1009 | break; | |
1010 | case SND_SOC_BIAS_STANDBY: | |
1011 | switch (codec->dapm.bias_level) { | |
1012 | case SND_SOC_BIAS_OFF: | |
1013 | aic31xx_power_on(codec); | |
1014 | break; | |
1015 | case SND_SOC_BIAS_PREPARE: | |
1016 | aic31xx_clk_off(codec); | |
1017 | break; | |
1018 | default: | |
1019 | BUG(); | |
1020 | } | |
1021 | break; | |
1022 | case SND_SOC_BIAS_OFF: | |
fd218aa3 JS |
1023 | if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) |
1024 | aic31xx_power_off(codec); | |
e00447fa JS |
1025 | break; |
1026 | } | |
1027 | codec->dapm.bias_level = level; | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | static int aic31xx_suspend(struct snd_soc_codec *codec) | |
1033 | { | |
1034 | aic31xx_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | static int aic31xx_resume(struct snd_soc_codec *codec) | |
1039 | { | |
1040 | aic31xx_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | static int aic31xx_codec_probe(struct snd_soc_codec *codec) | |
1045 | { | |
1046 | int ret = 0; | |
1047 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
1048 | int i; | |
1049 | ||
1050 | dev_dbg(aic31xx->dev, "## %s\n", __func__); | |
1051 | ||
1052 | aic31xx = snd_soc_codec_get_drvdata(codec); | |
e00447fa JS |
1053 | |
1054 | aic31xx->codec = codec; | |
1055 | ||
e00447fa JS |
1056 | for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { |
1057 | aic31xx->disable_nb[i].nb.notifier_call = | |
1058 | aic31xx_regulator_event; | |
1059 | aic31xx->disable_nb[i].aic31xx = aic31xx; | |
1060 | ret = regulator_register_notifier(aic31xx->supplies[i].consumer, | |
1061 | &aic31xx->disable_nb[i].nb); | |
1062 | if (ret) { | |
1063 | dev_err(codec->dev, | |
1064 | "Failed to request regulator notifier: %d\n", | |
1065 | ret); | |
1066 | return ret; | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | regcache_cache_only(aic31xx->regmap, true); | |
1071 | regcache_mark_dirty(aic31xx->regmap); | |
1072 | ||
1073 | ret = aic31xx_add_controls(codec); | |
1074 | if (ret) | |
1075 | return ret; | |
1076 | ||
1077 | ret = aic31xx_add_widgets(codec); | |
1078 | ||
1079 | return ret; | |
1080 | } | |
1081 | ||
1082 | static int aic31xx_codec_remove(struct snd_soc_codec *codec) | |
1083 | { | |
1084 | struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); | |
1085 | int i; | |
1086 | /* power down chip */ | |
1087 | aic31xx_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1088 | ||
1089 | for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) | |
1090 | regulator_unregister_notifier(aic31xx->supplies[i].consumer, | |
1091 | &aic31xx->disable_nb[i].nb); | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | static struct snd_soc_codec_driver soc_codec_driver_aic31xx = { | |
1097 | .probe = aic31xx_codec_probe, | |
1098 | .remove = aic31xx_codec_remove, | |
1099 | .suspend = aic31xx_suspend, | |
1100 | .resume = aic31xx_resume, | |
1101 | .set_bias_level = aic31xx_set_bias_level, | |
1102 | .controls = aic31xx_snd_controls, | |
1103 | .num_controls = ARRAY_SIZE(aic31xx_snd_controls), | |
1104 | .dapm_widgets = aic31xx_dapm_widgets, | |
1105 | .num_dapm_widgets = ARRAY_SIZE(aic31xx_dapm_widgets), | |
1106 | .dapm_routes = aic31xx_audio_map, | |
1107 | .num_dapm_routes = ARRAY_SIZE(aic31xx_audio_map), | |
1108 | }; | |
1109 | ||
1110 | static struct snd_soc_dai_ops aic31xx_dai_ops = { | |
1111 | .hw_params = aic31xx_hw_params, | |
1112 | .set_sysclk = aic31xx_set_dai_sysclk, | |
1113 | .set_fmt = aic31xx_set_dai_fmt, | |
1114 | .digital_mute = aic31xx_dac_mute, | |
1115 | }; | |
1116 | ||
1117 | static struct snd_soc_dai_driver aic31xx_dai_driver[] = { | |
1118 | { | |
1119 | .name = "tlv320aic31xx-hifi", | |
1120 | .playback = { | |
1121 | .stream_name = "Playback", | |
1122 | .channels_min = 1, | |
1123 | .channels_max = 2, | |
1124 | .rates = AIC31XX_RATES, | |
1125 | .formats = AIC31XX_FORMATS, | |
1126 | }, | |
1127 | .capture = { | |
1128 | .stream_name = "Capture", | |
1129 | .channels_min = 1, | |
1130 | .channels_max = 2, | |
1131 | .rates = AIC31XX_RATES, | |
1132 | .formats = AIC31XX_FORMATS, | |
1133 | }, | |
1134 | .ops = &aic31xx_dai_ops, | |
1135 | .symmetric_rates = 1, | |
1136 | } | |
1137 | }; | |
1138 | ||
1139 | #if defined(CONFIG_OF) | |
1140 | static const struct of_device_id tlv320aic31xx_of_match[] = { | |
1141 | { .compatible = "ti,tlv320aic310x" }, | |
1142 | { .compatible = "ti,tlv320aic311x" }, | |
1143 | { .compatible = "ti,tlv320aic3100" }, | |
1144 | { .compatible = "ti,tlv320aic3110" }, | |
1145 | { .compatible = "ti,tlv320aic3120" }, | |
1146 | { .compatible = "ti,tlv320aic3111" }, | |
1147 | {}, | |
1148 | }; | |
1149 | MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match); | |
1150 | ||
1151 | static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx) | |
1152 | { | |
1153 | struct device_node *np = aic31xx->dev->of_node; | |
1154 | unsigned int value = MICBIAS_2_0V; | |
1155 | int ret; | |
1156 | ||
1157 | of_property_read_u32(np, "ai31xx-micbias-vg", &value); | |
1158 | switch (value) { | |
1159 | case MICBIAS_2_0V: | |
1160 | case MICBIAS_2_5V: | |
1161 | case MICBIAS_AVDDV: | |
1162 | aic31xx->pdata.micbias_vg = value; | |
1163 | break; | |
1164 | default: | |
1165 | dev_err(aic31xx->dev, | |
1166 | "Bad ai31xx-micbias-vg value %d DT\n", | |
1167 | value); | |
1168 | aic31xx->pdata.micbias_vg = MICBIAS_2_0V; | |
1169 | } | |
1170 | ||
1171 | ret = of_get_named_gpio(np, "gpio-reset", 0); | |
1172 | if (ret > 0) | |
1173 | aic31xx->pdata.gpio_reset = ret; | |
1174 | } | |
1175 | #else /* CONFIG_OF */ | |
1176 | static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx) | |
1177 | { | |
1178 | } | |
1179 | #endif /* CONFIG_OF */ | |
1180 | ||
9296f4da | 1181 | static void aic31xx_device_init(struct aic31xx_priv *aic31xx) |
e00447fa JS |
1182 | { |
1183 | int ret, i; | |
1184 | ||
1185 | dev_set_drvdata(aic31xx->dev, aic31xx); | |
1186 | ||
1187 | if (dev_get_platdata(aic31xx->dev)) | |
1188 | memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), | |
1189 | sizeof(aic31xx->pdata)); | |
1190 | else if (aic31xx->dev->of_node) | |
1191 | aic31xx_pdata_from_of(aic31xx); | |
1192 | ||
1193 | if (aic31xx->pdata.gpio_reset) { | |
1194 | ret = devm_gpio_request_one(aic31xx->dev, | |
1195 | aic31xx->pdata.gpio_reset, | |
1196 | GPIOF_OUT_INIT_HIGH, | |
1197 | "aic31xx-reset-pin"); | |
1198 | if (ret < 0) { | |
1199 | dev_err(aic31xx->dev, "not able to acquire gpio\n"); | |
1200 | return; | |
1201 | } | |
1202 | } | |
1203 | ||
1204 | for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) | |
1205 | aic31xx->supplies[i].supply = aic31xx_supply_names[i]; | |
1206 | ||
1207 | ret = devm_regulator_bulk_get(aic31xx->dev, | |
1208 | ARRAY_SIZE(aic31xx->supplies), | |
1209 | aic31xx->supplies); | |
1210 | if (ret != 0) | |
1211 | dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret); | |
1212 | ||
1213 | } | |
1214 | ||
1215 | static int aic31xx_i2c_probe(struct i2c_client *i2c, | |
1216 | const struct i2c_device_id *id) | |
1217 | { | |
1218 | struct aic31xx_priv *aic31xx; | |
1219 | int ret; | |
1220 | const struct regmap_config *regmap_config; | |
1221 | ||
1222 | dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__, | |
1223 | id->name, (int) id->driver_data); | |
1224 | ||
1225 | regmap_config = &aic31xx_i2c_regmap; | |
1226 | ||
1227 | aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); | |
1228 | if (aic31xx == NULL) | |
1229 | return -ENOMEM; | |
1230 | ||
1231 | aic31xx->regmap = devm_regmap_init_i2c(i2c, regmap_config); | |
e00447fa JS |
1232 | if (IS_ERR(aic31xx->regmap)) { |
1233 | ret = PTR_ERR(aic31xx->regmap); | |
1234 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
1235 | ret); | |
1236 | return ret; | |
1237 | } | |
1238 | aic31xx->dev = &i2c->dev; | |
1239 | ||
1240 | aic31xx->pdata.codec_type = id->driver_data; | |
1241 | ||
1242 | aic31xx_device_init(aic31xx); | |
1243 | ||
dac7e404 | 1244 | return snd_soc_register_codec(&i2c->dev, &soc_codec_driver_aic31xx, |
e00447fa JS |
1245 | aic31xx_dai_driver, |
1246 | ARRAY_SIZE(aic31xx_dai_driver)); | |
e00447fa JS |
1247 | } |
1248 | ||
1249 | static int aic31xx_i2c_remove(struct i2c_client *i2c) | |
1250 | { | |
dac7e404 | 1251 | snd_soc_unregister_codec(&i2c->dev); |
e00447fa JS |
1252 | return 0; |
1253 | } | |
1254 | ||
1255 | static const struct i2c_device_id aic31xx_i2c_id[] = { | |
1256 | { "tlv320aic310x", AIC3100 }, | |
1257 | { "tlv320aic311x", AIC3110 }, | |
1258 | { "tlv320aic3100", AIC3100 }, | |
1259 | { "tlv320aic3110", AIC3110 }, | |
1260 | { "tlv320aic3120", AIC3120 }, | |
1261 | { "tlv320aic3111", AIC3111 }, | |
1262 | { } | |
1263 | }; | |
1264 | MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id); | |
1265 | ||
1266 | static struct i2c_driver aic31xx_i2c_driver = { | |
1267 | .driver = { | |
1268 | .name = "tlv320aic31xx-codec", | |
1269 | .owner = THIS_MODULE, | |
1270 | .of_match_table = of_match_ptr(tlv320aic31xx_of_match), | |
1271 | }, | |
1272 | .probe = aic31xx_i2c_probe, | |
dac7e404 | 1273 | .remove = aic31xx_i2c_remove, |
e00447fa JS |
1274 | .id_table = aic31xx_i2c_id, |
1275 | }; | |
1276 | ||
1277 | module_i2c_driver(aic31xx_i2c_driver); | |
1278 | ||
1279 | MODULE_DESCRIPTION("ASoC TLV320AIC3111 codec driver"); | |
1280 | MODULE_AUTHOR("Jyri Sarha"); | |
1281 | MODULE_LICENSE("GPL"); |