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UBUNTU: Ubuntu-5.15.0-39.42
[mirror_ubuntu-jammy-kernel.git] / sound / soc / codecs / tlv320aic31xx.c
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b1c52b7e 1// SPDX-License-Identifier: GPL-2.0
e00447fa 2/*
b1c52b7e 3 * ALSA SoC TLV320AIC31xx CODEC Driver
e00447fa 4 *
5856d8bd 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
b1c52b7e 6 * Jyri Sarha <jsarha@ti.com>
e00447fa
JS		 7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
b1c52b7e
AD		 10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
11 * high performance codecs which provides a stereo DAC, a mono ADC,
e00447fa
JS		 12 * and mono/stereo Class-D speaker driver.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
283c3506 21#include <linux/gpio/consumer.h>
e00447fa 22#include <linux/regulator/consumer.h>
f5cc1772 23#include <linux/acpi.h>
0faabc4f 24#include <linux/of.h>
e00447fa
JS		 25#include <linux/of_gpio.h>
26#include <linux/slab.h>
27#include <sound/core.h>
ebf3326c 28#include <sound/jack.h>
e00447fa
JS		 29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
35
36#include "tlv320aic31xx.h"
37
2c39ca68
MB		 38static int aic31xx_set_jack(struct snd_soc_component *component,
39 struct snd_soc_jack *jack, void *data);
40
e00447fa
JS		 41static const struct reg_default aic31xx_reg_defaults[] = {
42 { AIC31XX_CLKMUX, 0x00 },
43 { AIC31XX_PLLPR, 0x11 },
44 { AIC31XX_PLLJ, 0x04 },
45 { AIC31XX_PLLDMSB, 0x00 },
46 { AIC31XX_PLLDLSB, 0x00 },
47 { AIC31XX_NDAC, 0x01 },
48 { AIC31XX_MDAC, 0x01 },
49 { AIC31XX_DOSRMSB, 0x00 },
50 { AIC31XX_DOSRLSB, 0x80 },
51 { AIC31XX_NADC, 0x01 },
52 { AIC31XX_MADC, 0x01 },
53 { AIC31XX_AOSR, 0x80 },
54 { AIC31XX_IFACE1, 0x00 },
55 { AIC31XX_DATA_OFFSET, 0x00 },
56 { AIC31XX_IFACE2, 0x00 },
57 { AIC31XX_BCLKN, 0x01 },
58 { AIC31XX_DACSETUP, 0x14 },
59 { AIC31XX_DACMUTE, 0x0c },
60 { AIC31XX_LDACVOL, 0x00 },
61 { AIC31XX_RDACVOL, 0x00 },
62 { AIC31XX_ADCSETUP, 0x00 },
63 { AIC31XX_ADCFGA, 0x80 },
64 { AIC31XX_ADCVOL, 0x00 },
65 { AIC31XX_HPDRIVER, 0x04 },
66 { AIC31XX_SPKAMP, 0x06 },
67 { AIC31XX_DACMIXERROUTE, 0x00 },
68 { AIC31XX_LANALOGHPL, 0x7f },
69 { AIC31XX_RANALOGHPR, 0x7f },
70 { AIC31XX_LANALOGSPL, 0x7f },
71 { AIC31XX_RANALOGSPR, 0x7f },
72 { AIC31XX_HPLGAIN, 0x02 },
73 { AIC31XX_HPRGAIN, 0x02 },
74 { AIC31XX_SPLGAIN, 0x00 },
75 { AIC31XX_SPRGAIN, 0x00 },
76 { AIC31XX_MICBIAS, 0x00 },
77 { AIC31XX_MICPGA, 0x80 },
78 { AIC31XX_MICPGAPI, 0x00 },
79 { AIC31XX_MICPGAMI, 0x00 },
80};
81
82static bool aic31xx_volatile(struct device *dev, unsigned int reg)
83{
84 switch (reg) {
85 case AIC31XX_PAGECTL: /* regmap implementation requires this */
86 case AIC31XX_RESET: /* always clears after write */
87 case AIC31XX_OT_FLAG:
88 case AIC31XX_ADCFLAG:
89 case AIC31XX_DACFLAG1:
90 case AIC31XX_DACFLAG2:
91 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
92 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
93 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
94 case AIC31XX_INTRDACFLAG2:
95 case AIC31XX_INTRADCFLAG2:
ebf3326c 96 case AIC31XX_HSDETECT:
e00447fa
JS		 97 return true;
98 }
99 return false;
100}
101
102static bool aic31xx_writeable(struct device *dev, unsigned int reg)
103{
104 switch (reg) {
105 case AIC31XX_OT_FLAG:
106 case AIC31XX_ADCFLAG:
107 case AIC31XX_DACFLAG1:
108 case AIC31XX_DACFLAG2:
109 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
110 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
111 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
112 case AIC31XX_INTRDACFLAG2:
113 case AIC31XX_INTRADCFLAG2:
114 return false;
115 }
116 return true;
117}
118
119static const struct regmap_range_cfg aic31xx_ranges[] = {
120 {
121 .range_min = 0,
122 .range_max = 12 * 128,
123 .selector_reg = AIC31XX_PAGECTL,
124 .selector_mask = 0xff,
125 .selector_shift = 0,
126 .window_start = 0,
127 .window_len = 128,
128 },
129};
130
9296f4da 131static const struct regmap_config aic31xx_i2c_regmap = {
e00447fa
JS		 132 .reg_bits = 8,
133 .val_bits = 8,
134 .writeable_reg = aic31xx_writeable,
135 .volatile_reg = aic31xx_volatile,
136 .reg_defaults = aic31xx_reg_defaults,
137 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
138 .cache_type = REGCACHE_RBTREE,
139 .ranges = aic31xx_ranges,
140 .num_ranges = ARRAY_SIZE(aic31xx_ranges),
141 .max_register = 12 * 128,
142};
143
ca7840fb 144static const char * const aic31xx_supply_names[] = {
e00447fa
JS		 145 "HPVDD",
146 "SPRVDD",
147 "SPLVDD",
148 "AVDD",
149 "IOVDD",
150 "DVDD",
151};
152
ca7840fb
AD		 153#define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names)
154
e00447fa
JS		 155struct aic31xx_disable_nb {
156 struct notifier_block nb;
157 struct aic31xx_priv *aic31xx;
158};
159
160struct aic31xx_priv {
f2e6f95b 161 struct snd_soc_component *component;
e00447fa
JS		 162 u8 i2c_regs_status;
163 struct device *dev;
164 struct regmap *regmap;
cd15da88 165 enum aic31xx_type codec_type;
b6b247cd 166 struct gpio_desc *gpio_reset;
cd15da88 167 int micbias_vg;
e00447fa
JS		 168 struct aic31xx_pdata pdata;
169 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
170 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
ebf3326c 171 struct snd_soc_jack *jack;
e00447fa 172 unsigned int sysclk;
7ed36e96 173 u8 p_div;
e00447fa 174 int rate_div_line;
d460b3f8 175 bool master_dapm_route_applied;
80863ee2 176 int irq;
e48fdb53 177 u8 ocmv; /* output common-mode voltage */
e00447fa
JS		 178};
179
180struct aic31xx_rate_divs {
7ed36e96 181 u32 mclk_p;
e00447fa 182 u32 rate;
e00447fa
JS		 183 u8 pll_j;
184 u16 pll_d;
185 u16 dosr;
186 u8 ndac;
187 u8 mdac;
188 u8 aosr;
189 u8 nadc;
190 u8 madc;
191};
192
ca7840fb 193/* ADC dividers can be disabled by configuring them to 0 */
e00447fa 194static const struct aic31xx_rate_divs aic31xx_divs[] = {
7ed36e96 195 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
e00447fa 196 /* 8k rate */
7ed36e96
JS		 197 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
198 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
199 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
e00447fa 200 /* 11.025k rate */
7ed36e96
JS		 201 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
202 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
203 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
e00447fa 204 /* 16k rate */
7ed36e96
JS		 205 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
206 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
207 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
e00447fa 208 /* 22.05k rate */
7ed36e96
JS		 209 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
210 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
211 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
e00447fa 212 /* 32k rate */
7ed36e96
JS		 213 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
214 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
215 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
e00447fa 216 /* 44.1k rate */
7ed36e96
JS		 217 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
218 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
219 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
e00447fa 220 /* 48k rate */
7ed36e96
JS		 221 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
222 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
223 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
e00447fa 224 /* 88.2k rate */
7ed36e96
JS		 225 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
226 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
227 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
e00447fa 228 /* 96k rate */
7ed36e96
JS		 229 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
230 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
231 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
e00447fa 232 /* 176.4k rate */
7ed36e96
JS		 233 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
234 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
235 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
e00447fa 236 /* 192k rate */
7ed36e96
JS		 237 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
238 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
239 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
e00447fa
JS		 240};
241
242static const char * const ldac_in_text[] = {
243 "Off", "Left Data", "Right Data", "Mono"
244};
245
246static const char * const rdac_in_text[] = {
247 "Off", "Right Data", "Left Data", "Mono"
248};
249
250static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
251
252static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
253
254static const char * const mic_select_text[] = {
255 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
256};
257
914bc160
LPC		 258static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
259 mic_select_text);
260static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
261 mic_select_text);
262static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
263 mic_select_text);
e00447fa 264
914bc160
LPC		 265static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
266 mic_select_text);
e00447fa 267
0bb1306f
NY		 268static const char * const hp_poweron_time_text[] = {
269 "0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms",
270 "153ms", "304ms", "610ms", "1.22s", "3.04s", "6.1s" };
271
272static SOC_ENUM_SINGLE_DECL(hp_poweron_time_enum, AIC31XX_HPPOP, 3,
273 hp_poweron_time_text);
274
275static const char * const hp_rampup_step_text[] = {
276 "0ms", "0.98ms", "1.95ms", "3.9ms" };
277
278static SOC_ENUM_SINGLE_DECL(hp_rampup_step_enum, AIC31XX_HPPOP, 1,
279 hp_rampup_step_text);
280
3176f94c
NY		 281static const char * const vol_soft_step_mode_text[] = {
282 "fast", "slow", "disabled" };
283
284static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0,
285 vol_soft_step_mode_text);
286
e00447fa
JS		 287static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
288static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
289static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
290static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
291static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
292static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
293static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
294static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
295
296/*
297 * controls to be exported to the user space
298 */
ef9656b6 299static const struct snd_kcontrol_new common31xx_snd_controls[] = {
e00447fa
JS		 300 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
301 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
302
ef9656b6
NY		 303 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
304 AIC31XX_HPRGAIN, 2, 1, 0),
305 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
306 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
307
308 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
309 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
0bb1306f
NY		 310
311 /* HP de-pop control: apply power not immediately but via ramp
312 * function with these psarameters. Note that power up sequence
313 * has to wait for this to complete; this is implemented by
314 * polling HP driver status in aic31xx_dapm_power_event()
315 */
316 SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum),
317 SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum),
3176f94c
NY		 318
319 SOC_ENUM("Volume Soft Stepping", vol_soft_step_mode_enum),
ef9656b6
NY		 320};
321
322static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
e00447fa
JS		 323 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
324 adc_fgain_tlv),
325
326 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
327 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
328 0, -24, 40, 6, 0, adc_cgain_tlv),
329
330 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
331 119, 0, mic_pga_tlv),
e00447fa
JS		 332};
333
334static const struct snd_kcontrol_new aic311x_snd_controls[] = {
335 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
336 AIC31XX_SPRGAIN, 2, 1, 0),
337 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
338 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
339
340 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
341 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
342};
343
344static const struct snd_kcontrol_new aic310x_snd_controls[] = {
345 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
346 2, 1, 0),
347 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
348 3, 3, 0, class_D_drv_tlv),
349
350 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
351 0, 0x7F, 1, sp_vol_tlv),
352};
353
354static const struct snd_kcontrol_new ldac_in_control =
355 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
356
357static const struct snd_kcontrol_new rdac_in_control =
358 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
359
9296f4da
MB		 360static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
361 unsigned int mask, unsigned int wbits, int sleep,
362 int count)
e00447fa
JS		 363{
364 unsigned int bits;
365 int counter = count;
366 int ret = regmap_read(aic31xx->regmap, reg, &bits);
423ca88e 367
e00447fa
JS		 368 while ((bits & mask) != wbits && counter && !ret) {
369 usleep_range(sleep, sleep * 2);
370 ret = regmap_read(aic31xx->regmap, reg, &bits);
371 counter--;
372 }
373 if ((bits & mask) != wbits) {
374 dev_err(aic31xx->dev,
375 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
376 __func__, reg, bits, wbits, ret, mask,
377 (count - counter) * sleep);
378 ret = -1;
379 }
380 return ret;
381}
382
383#define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
384
385static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
386 struct snd_kcontrol *kcontrol, int event)
387{
f2e6f95b
KM		 388 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
389 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
e00447fa
JS		 390 unsigned int reg = AIC31XX_DACFLAG1;
391 unsigned int mask;
0bb1306f 392 unsigned int timeout = 500 * USEC_PER_MSEC;
e00447fa
JS		 393
394 switch (WIDGET_BIT(w->reg, w->shift)) {
395 case WIDGET_BIT(AIC31XX_DACSETUP, 7):
396 mask = AIC31XX_LDACPWRSTATUS_MASK;
397 break;
398 case WIDGET_BIT(AIC31XX_DACSETUP, 6):
399 mask = AIC31XX_RDACPWRSTATUS_MASK;
400 break;
401 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
402 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
0bb1306f
NY		 403 if (event == SND_SOC_DAPM_POST_PMU)
404 timeout = 7 * USEC_PER_SEC;
e00447fa
JS		 405 break;
406 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
407 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
0bb1306f
NY		 408 if (event == SND_SOC_DAPM_POST_PMU)
409 timeout = 7 * USEC_PER_SEC;
e00447fa
JS		 410 break;
411 case WIDGET_BIT(AIC31XX_SPKAMP, 7):
412 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
413 break;
414 case WIDGET_BIT(AIC31XX_SPKAMP, 6):
415 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
416 break;
417 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
418 mask = AIC31XX_ADCPWRSTATUS_MASK;
419 reg = AIC31XX_ADCFLAG;
420 break;
421 default:
f2e6f95b 422 dev_err(component->dev, "Unknown widget '%s' calling %s\n",
e00447fa
JS		 423 w->name, __func__);
424 return -EINVAL;
425 }
426
427 switch (event) {
428 case SND_SOC_DAPM_POST_PMU:
0bb1306f
NY		 429 return aic31xx_wait_bits(aic31xx, reg, mask, mask,
430 5000, timeout / 5000);
e00447fa 431 case SND_SOC_DAPM_POST_PMD:
0bb1306f
NY		 432 return aic31xx_wait_bits(aic31xx, reg, mask, 0,
433 5000, timeout / 5000);
e00447fa 434 default:
f2e6f95b 435 dev_dbg(component->dev,
e00447fa
JS		 436 "Unhandled dapm widget event %d from %s\n",
437 event, w->name);
438 }
439 return 0;
440}
441
ef9656b6 442static const struct snd_kcontrol_new aic31xx_left_output_switches[] = {
e00447fa
JS		 443 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
444 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
445 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
446};
447
ef9656b6 448static const struct snd_kcontrol_new aic31xx_right_output_switches[] = {
e00447fa
JS		 449 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
450 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
451};
452
ef9656b6
NY		 453static const struct snd_kcontrol_new dac31xx_left_output_switches[] = {
454 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
455 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),
456 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),
457};
458
459static const struct snd_kcontrol_new dac31xx_right_output_switches[] = {
460 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
461 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),
462};
463
e00447fa
JS		 464static const struct snd_kcontrol_new p_term_mic1lp =
465 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
466
467static const struct snd_kcontrol_new p_term_mic1rp =
468 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
469
470static const struct snd_kcontrol_new p_term_mic1lm =
471 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
472
473static const struct snd_kcontrol_new m_term_mic1lm =
474 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
475
476static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
477 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
478
479static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
480 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
481
482static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
483 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
484
485static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
486 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
487
488static int mic_bias_event(struct snd_soc_dapm_widget *w,
489 struct snd_kcontrol *kcontrol, int event)
490{
f2e6f95b
KM		 491 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
492 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
423ca88e 493
e00447fa
JS		 494 switch (event) {
495 case SND_SOC_DAPM_POST_PMU:
496 /* change mic bias voltage to user defined */
f2e6f95b 497 snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
e00447fa 498 AIC31XX_MICBIAS_MASK,
cd15da88 499 aic31xx->micbias_vg <<
e00447fa 500 AIC31XX_MICBIAS_SHIFT);
f2e6f95b 501 dev_dbg(component->dev, "%s: turned on\n", __func__);
e00447fa
JS		 502 break;
503 case SND_SOC_DAPM_PRE_PMD:
504 /* turn mic bias off */
f2e6f95b 505 snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
e00447fa 506 AIC31XX_MICBIAS_MASK, 0);
f2e6f95b 507 dev_dbg(component->dev, "%s: turned off\n", __func__);
e00447fa
JS		 508 break;
509 }
510 return 0;
511}
512
ef9656b6 513static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = {
7d41bc28 514 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
e00447fa
JS		 515
516 SND_SOC_DAPM_MUX("DAC Left Input",
517 SND_SOC_NOPM, 0, 0, &ldac_in_control),
518 SND_SOC_DAPM_MUX("DAC Right Input",
519 SND_SOC_NOPM, 0, 0, &rdac_in_control),
520 /* DACs */
521 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
522 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
523 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
524
525 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
526 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
527 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
528
ef9656b6 529 /* HP */
e00447fa
JS		 530 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
531 &aic31xx_dapm_hpl_switch),
532 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
533 &aic31xx_dapm_hpr_switch),
534
535 /* Output drivers */
536 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
537 NULL, 0, aic31xx_dapm_power_event,
538 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
539 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
540 NULL, 0, aic31xx_dapm_power_event,
541 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
542
ef9656b6
NY		 543 /* Mic Bias */
544 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
545 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
546
a16be2a6
PU		 547 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */
548 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0,
549 NULL, 0),
550
ef9656b6
NY		 551 /* Outputs */
552 SND_SOC_DAPM_OUTPUT("HPL"),
553 SND_SOC_DAPM_OUTPUT("HPR"),
554};
555
556static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = {
557 /* Inputs */
558 SND_SOC_DAPM_INPUT("AIN1"),
559 SND_SOC_DAPM_INPUT("AIN2"),
560
561 /* Output Mixers */
562 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
563 dac31xx_left_output_switches,
564 ARRAY_SIZE(dac31xx_left_output_switches)),
565 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
566 dac31xx_right_output_switches,
567 ARRAY_SIZE(dac31xx_right_output_switches)),
568};
569
570static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
571 /* Inputs */
572 SND_SOC_DAPM_INPUT("MIC1LP"),
573 SND_SOC_DAPM_INPUT("MIC1RP"),
574 SND_SOC_DAPM_INPUT("MIC1LM"),
e00447fa
JS		 575
576 /* Input Selection to MIC_PGA */
577 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
578 &p_term_mic1lp),
579 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
580 &p_term_mic1rp),
581 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
582 &p_term_mic1lm),
583
ef9656b6
NY		 584 /* ADC */
585 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
586 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
587 SND_SOC_DAPM_POST_PMD),
588
e00447fa
JS		 589 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
590 &m_term_mic1lm),
ef9656b6 591
e00447fa
JS		 592 /* Enabling & Disabling MIC Gain Ctl */
593 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
594 7, 1, NULL, 0),
595
ef9656b6
NY		 596 /* Output Mixers */
597 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
598 aic31xx_left_output_switches,
599 ARRAY_SIZE(aic31xx_left_output_switches)),
600 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
601 aic31xx_right_output_switches,
602 ARRAY_SIZE(aic31xx_right_output_switches)),
a16be2a6
PU		 603
604 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
e00447fa
JS		 605};
606
607static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
608 /* AIC3111 and AIC3110 have stereo class-D amplifier */
609 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
610 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
611 SND_SOC_DAPM_POST_PMD),
612 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
613 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
614 SND_SOC_DAPM_POST_PMD),
615 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
616 &aic31xx_dapm_spl_switch),
617 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
618 &aic31xx_dapm_spr_switch),
619 SND_SOC_DAPM_OUTPUT("SPL"),
620 SND_SOC_DAPM_OUTPUT("SPR"),
621};
622
623/* AIC3100 and AIC3120 have only mono class-D amplifier */
624static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
625 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
626 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
627 SND_SOC_DAPM_POST_PMD),
628 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
629 &aic31xx_dapm_spl_switch),
630 SND_SOC_DAPM_OUTPUT("SPK"),
631};
632
633static const struct snd_soc_dapm_route
ef9656b6 634common31xx_audio_map[] = {
e00447fa 635 /* DAC Input Routing */
7d41bc28
PU		 636 {"DAC Left Input", "Left Data", "AIF IN"},
637 {"DAC Left Input", "Right Data", "AIF IN"},
638 {"DAC Left Input", "Mono", "AIF IN"},
639 {"DAC Right Input", "Left Data", "AIF IN"},
640 {"DAC Right Input", "Right Data", "AIF IN"},
641 {"DAC Right Input", "Mono", "AIF IN"},
e00447fa
JS		 642 {"DAC Left", NULL, "DAC Left Input"},
643 {"DAC Right", NULL, "DAC Right Input"},
644
ef9656b6
NY		 645 /* HPL path */
646 {"HP Left", "Switch", "Output Left"},
647 {"HPL Driver", NULL, "HP Left"},
648 {"HPL", NULL, "HPL Driver"},
649
650 /* HPR path */
651 {"HP Right", "Switch", "Output Right"},
652 {"HPR Driver", NULL, "HP Right"},
653 {"HPR", NULL, "HPR Driver"},
654};
655
656static const struct snd_soc_dapm_route
657dac31xx_audio_map[] = {
658 /* Left Output */
659 {"Output Left", "From Left DAC", "DAC Left"},
660 {"Output Left", "From AIN1", "AIN1"},
661 {"Output Left", "From AIN2", "AIN2"},
662
663 /* Right Output */
664 {"Output Right", "From Right DAC", "DAC Right"},
665 {"Output Right", "From AIN2", "AIN2"},
666};
667
668static const struct snd_soc_dapm_route
669aic31xx_audio_map[] = {
e00447fa
JS		 670 /* Mic input */
671 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
672 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
673 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
674 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
675 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
676 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
677 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
678 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
679 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
680
681 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
682 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
683 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
684
685 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
686 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
687 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
688 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
689
690 {"ADC", NULL, "MIC_GAIN_CTL"},
691
a16be2a6
PU		 692 {"AIF OUT", NULL, "ADC"},
693
e00447fa
JS		 694 /* Left Output */
695 {"Output Left", "From Left DAC", "DAC Left"},
696 {"Output Left", "From MIC1LP", "MIC1LP"},
697 {"Output Left", "From MIC1RP", "MIC1RP"},
698
699 /* Right Output */
700 {"Output Right", "From Right DAC", "DAC Right"},
701 {"Output Right", "From MIC1RP", "MIC1RP"},
e00447fa
JS		 702};
703
704static const struct snd_soc_dapm_route
705aic311x_audio_map[] = {
706 /* SP L path */
707 {"Speaker Left", "Switch", "Output Left"},
708 {"SPL ClassD", NULL, "Speaker Left"},
709 {"SPL", NULL, "SPL ClassD"},
710
711 /* SP R path */
712 {"Speaker Right", "Switch", "Output Right"},
713 {"SPR ClassD", NULL, "Speaker Right"},
714 {"SPR", NULL, "SPR ClassD"},
715};
716
717static const struct snd_soc_dapm_route
718aic310x_audio_map[] = {
719 /* SP L path */
720 {"Speaker", "Switch", "Output Left"},
721 {"SPK ClassD", NULL, "Speaker"},
722 {"SPK", NULL, "SPK ClassD"},
723};
724
d460b3f8
PU		 725/*
726 * Always connected DAPM routes for codec clock master modes.
a16be2a6
PU		 727 * If the codec is the master on the I2S bus, we need to power up components
728 * to have valid DAC_CLK.
729 *
730 * In order to have the I2S clocks on the bus either the DACs/ADC need to be
731 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set.
732 *
d460b3f8
PU		 733 * Otherwise the codec will not generate clocks on the bus.
734 */
735static const struct snd_soc_dapm_route
736common31xx_cm_audio_map[] = {
a16be2a6
PU		 737 {"HPL", NULL, "AIF IN"},
738 {"HPR", NULL, "AIF IN"},
d460b3f8 739
a16be2a6 740 {"AIF IN", NULL, "Activate I2S clocks"},
d460b3f8
PU		 741};
742
743static const struct snd_soc_dapm_route
744aic31xx_cm_audio_map[] = {
a16be2a6
PU		 745 {"AIF OUT", NULL, "MIC1LP"},
746 {"AIF OUT", NULL, "MIC1RP"},
747 {"AIF OUT", NULL, "MIC1LM"},
748
749 {"AIF OUT", NULL, "Activate I2S clocks"},
d460b3f8
PU		 750};
751
f2e6f95b 752static int aic31xx_add_controls(struct snd_soc_component *component)
e00447fa
JS		 753{
754 int ret = 0;
f2e6f95b 755 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
e00447fa 756
cd15da88 757 if (!(aic31xx->codec_type & DAC31XX_BIT))
f2e6f95b
KM		 758 ret = snd_soc_add_component_controls(
759 component, aic31xx_snd_controls,
ef9656b6
NY		 760 ARRAY_SIZE(aic31xx_snd_controls));
761 if (ret)
762 return ret;
763
cd15da88 764 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT)
f2e6f95b
KM		 765 ret = snd_soc_add_component_controls(
766 component, aic311x_snd_controls,
e00447fa
JS		 767 ARRAY_SIZE(aic311x_snd_controls));
768 else
f2e6f95b
KM		 769 ret = snd_soc_add_component_controls(
770 component, aic310x_snd_controls,
e00447fa
JS		 771 ARRAY_SIZE(aic310x_snd_controls));
772
773 return ret;
774}
775
f2e6f95b 776static int aic31xx_add_widgets(struct snd_soc_component *component)
e00447fa 777{
f2e6f95b
KM		 778 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
779 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
e00447fa
JS		 780 int ret = 0;
781
cd15da88 782 if (aic31xx->codec_type & DAC31XX_BIT) {
ef9656b6
NY		 783 ret = snd_soc_dapm_new_controls(
784 dapm, dac31xx_dapm_widgets,
785 ARRAY_SIZE(dac31xx_dapm_widgets));
786 if (ret)
787 return ret;
788
789 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map,
790 ARRAY_SIZE(dac31xx_audio_map));
791 if (ret)
792 return ret;
793 } else {
794 ret = snd_soc_dapm_new_controls(
795 dapm, aic31xx_dapm_widgets,
796 ARRAY_SIZE(aic31xx_dapm_widgets));
797 if (ret)
798 return ret;
799
800 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map,
801 ARRAY_SIZE(aic31xx_audio_map));
802 if (ret)
803 return ret;
804 }
805
cd15da88 806 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
e00447fa
JS		 807 ret = snd_soc_dapm_new_controls(
808 dapm, aic311x_dapm_widgets,
809 ARRAY_SIZE(aic311x_dapm_widgets));
810 if (ret)
811 return ret;
812
813 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
814 ARRAY_SIZE(aic311x_audio_map));
815 if (ret)
816 return ret;
817 } else {
818 ret = snd_soc_dapm_new_controls(
819 dapm, aic310x_dapm_widgets,
820 ARRAY_SIZE(aic310x_dapm_widgets));
821 if (ret)
822 return ret;
823
824 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
825 ARRAY_SIZE(aic310x_audio_map));
826 if (ret)
827 return ret;
828 }
829
830 return 0;
831}
832
f2e6f95b 833static int aic31xx_setup_pll(struct snd_soc_component *component,
e00447fa
JS		 834 struct snd_pcm_hw_params *params)
835{
f2e6f95b 836 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
03be88ee 837 int bclk_score = snd_soc_params_to_frame_size(params);
c6b8c779 838 int mclk_p;
e00447fa 839 int bclk_n = 0;
03be88ee 840 int match = -1;
e00447fa
JS		 841 int i;
842
c6b8c779 843 if (!aic31xx->sysclk || !aic31xx->p_div) {
f2e6f95b 844 dev_err(component->dev, "Master clock not supplied\n");
c6b8c779
AD		 845 return -EINVAL;
846 }
847 mclk_p = aic31xx->sysclk / aic31xx->p_div;
848
e00447fa 849 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
f2e6f95b 850 snd_soc_component_update_bits(component, AIC31XX_CLKMUX,
e00447fa 851 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
f2e6f95b 852 snd_soc_component_update_bits(component, AIC31XX_IFACE2,
e00447fa
JS		 853 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
854
855 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
856 if (aic31xx_divs[i].rate == params_rate(params) &&
7ed36e96 857 aic31xx_divs[i].mclk_p == mclk_p) {
03be88ee
JS		 858 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
859 snd_soc_params_to_frame_size(params);
860 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
861 snd_soc_params_to_frame_size(params);
862 if (s < bclk_score && bn > 0) {
863 match = i;
864 bclk_n = bn;
865 bclk_score = s;
866 }
867 }
e00447fa
JS		 868 }
869
03be88ee 870 if (match == -1) {
f2e6f95b 871 dev_err(component->dev,
03be88ee 872 "%s: Sample rate (%u) and format not supported\n",
e00447fa 873 __func__, params_rate(params));
03be88ee 874 /* See bellow for details how fix this. */
e00447fa
JS		 875 return -EINVAL;
876 }
03be88ee 877 if (bclk_score != 0) {
f2e6f95b 878 dev_warn(component->dev, "Can not produce exact bitclock");
03be88ee
JS		 879 /* This is fine if using dsp format, but if using i2s
880 there may be trouble. To fix the issue edit the
881 aic31xx_divs table for your mclk and sample
882 rate. Details can be found from:
5856d8bd 883 https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
03be88ee
JS		 884 Section: 5.6 CLOCK Generation and PLL
885 */
886 }
887 i = match;
e00447fa
JS		 888
889 /* PLL configuration */
f2e6f95b 890 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
7ed36e96 891 (aic31xx->p_div << 4) | 0x01);
f2e6f95b 892 snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
e00447fa 893
f2e6f95b 894 snd_soc_component_write(component, AIC31XX_PLLDMSB,
e00447fa 895 aic31xx_divs[i].pll_d >> 8);
f2e6f95b 896 snd_soc_component_write(component, AIC31XX_PLLDLSB,
e00447fa
JS		 897 aic31xx_divs[i].pll_d & 0xff);
898
899 /* DAC dividers configuration */
f2e6f95b 900 snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK,
e00447fa 901 aic31xx_divs[i].ndac);
f2e6f95b 902 snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK,
e00447fa
JS		 903 aic31xx_divs[i].mdac);
904
f2e6f95b
KM		 905 snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
906 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
e00447fa
JS		 907
908 /* ADC dividers configuration. Write reset value 1 if not used. */
f2e6f95b 909 snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK,
e00447fa 910 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
f2e6f95b 911 snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK,
e00447fa
JS		 912 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
913
f2e6f95b 914 snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr);
e00447fa
JS		 915
916 /* Bit clock divider configuration. */
f2e6f95b 917 snd_soc_component_update_bits(component, AIC31XX_BCLKN,
e00447fa
JS		 918 AIC31XX_PLL_MASK, bclk_n);
919
920 aic31xx->rate_div_line = i;
921
f2e6f95b 922 dev_dbg(component->dev,
e00447fa 923 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
ca7840fb
AD		 924 aic31xx_divs[i].pll_j,
925 aic31xx_divs[i].pll_d,
926 aic31xx->p_div,
927 aic31xx_divs[i].dosr,
928 aic31xx_divs[i].ndac,
929 aic31xx_divs[i].mdac,
930 aic31xx_divs[i].aosr,
931 aic31xx_divs[i].nadc,
932 aic31xx_divs[i].madc,
933 bclk_n
934 );
e00447fa
JS		 935
936 return 0;
937}
938
939static int aic31xx_hw_params(struct snd_pcm_substream *substream,
940 struct snd_pcm_hw_params *params,
ab64246c 941 struct snd_soc_dai *dai)
e00447fa 942{
f2e6f95b 943 struct snd_soc_component *component = dai->component;
e00447fa
JS		 944 u8 data = 0;
945
f2e6f95b 946 dev_dbg(component->dev, "## %s: width %d rate %d\n",
88be681b 947 __func__, params_width(params),
e00447fa
JS		 948 params_rate(params));
949
950 switch (params_width(params)) {
951 case 16:
952 break;
953 case 20:
954 data = (AIC31XX_WORD_LEN_20BITS <<
955 AIC31XX_IFACE1_DATALEN_SHIFT);
956 break;
957 case 24:
958 data = (AIC31XX_WORD_LEN_24BITS <<
959 AIC31XX_IFACE1_DATALEN_SHIFT);
960 break;
961 case 32:
962 data = (AIC31XX_WORD_LEN_32BITS <<
963 AIC31XX_IFACE1_DATALEN_SHIFT);
964 break;
965 default:
f2e6f95b 966 dev_err(component->dev, "%s: Unsupported width %d\n",
88be681b 967 __func__, params_width(params));
e00447fa
JS		 968 return -EINVAL;
969 }
970
f2e6f95b 971 snd_soc_component_update_bits(component, AIC31XX_IFACE1,
e00447fa
JS		 972 AIC31XX_IFACE1_DATALEN_MASK,
973 data);
974
f2e6f95b 975 return aic31xx_setup_pll(component, params);
e00447fa
JS		 976}
977
960af79d
KM		 978static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute,
979 int direction)
e00447fa 980{
f2e6f95b 981 struct snd_soc_component *component = codec_dai->component;
e00447fa
JS		 982
983 if (mute) {
f2e6f95b 984 snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
e00447fa
JS		 985 AIC31XX_DACMUTE_MASK,
986 AIC31XX_DACMUTE_MASK);
987 } else {
f2e6f95b 988 snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
e00447fa
JS		 989 AIC31XX_DACMUTE_MASK, 0x0);
990 }
991
992 return 0;
993}
994
d460b3f8
PU		 995static int aic31xx_clock_master_routes(struct snd_soc_component *component,
996 unsigned int fmt)
997{
998 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
999 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1000 int ret;
1001
1002 fmt &= SND_SOC_DAIFMT_MASTER_MASK;
1003 if (fmt == SND_SOC_DAIFMT_CBS_CFS &&
1004 aic31xx->master_dapm_route_applied) {
1005 /*
1006 * Remove the DAPM route(s) for codec clock master modes,
1007 * if applied
1008 */
1009 ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map,
1010 ARRAY_SIZE(common31xx_cm_audio_map));
1011 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
1012 ret = snd_soc_dapm_del_routes(dapm,
1013 aic31xx_cm_audio_map,
1014 ARRAY_SIZE(aic31xx_cm_audio_map));
1015
1016 if (ret)
1017 return ret;
1018
1019 aic31xx->master_dapm_route_applied = false;
1020 } else if (fmt != SND_SOC_DAIFMT_CBS_CFS &&
1021 !aic31xx->master_dapm_route_applied) {
1022 /*
1023 * Add the needed DAPM route(s) for codec clock master modes,
1024 * if it is not done already
1025 */
1026 ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map,
1027 ARRAY_SIZE(common31xx_cm_audio_map));
1028 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
1029 ret = snd_soc_dapm_add_routes(dapm,
1030 aic31xx_cm_audio_map,
1031 ARRAY_SIZE(aic31xx_cm_audio_map));
1032
1033 if (ret)
1034 return ret;
1035
1036 aic31xx->master_dapm_route_applied = true;
1037 }
1038
1039 return 0;
1040}
1041
e00447fa
JS		 1042static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
1043 unsigned int fmt)
1044{
f2e6f95b 1045 struct snd_soc_component *component = codec_dai->component;
e00447fa 1046 u8 iface_reg1 = 0;
085f3ec6 1047 u8 iface_reg2 = 0;
e00447fa
JS		 1048 u8 dsp_a_val = 0;
1049
f2e6f95b 1050 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
e00447fa
JS		 1051
1052 /* set master/slave audio interface */
1053 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1054 case SND_SOC_DAIFMT_CBM_CFM:
1055 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
1056 break;
77f8b3cf
AD		 1057 case SND_SOC_DAIFMT_CBS_CFM:
1058 iface_reg1 |= AIC31XX_WCLK_MASTER;
1059 break;
1060 case SND_SOC_DAIFMT_CBM_CFS:
1061 iface_reg1 |= AIC31XX_BCLK_MASTER;
1062 break;
1063 case SND_SOC_DAIFMT_CBS_CFS:
1064 break;
e00447fa 1065 default:
f2e6f95b 1066 dev_err(component->dev, "Invalid DAI master/slave interface\n");
e00447fa
JS		 1067 return -EINVAL;
1068 }
1069
dcb407b2
AD		 1070 /* signal polarity */
1071 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1072 case SND_SOC_DAIFMT_NB_NF:
1073 break;
1074 case SND_SOC_DAIFMT_IB_NF:
1075 iface_reg2 |= AIC31XX_BCLKINV_MASK;
1076 break;
1077 default:
f2e6f95b 1078 dev_err(component->dev, "Invalid DAI clock signal polarity\n");
dcb407b2
AD		 1079 return -EINVAL;
1080 }
1081
e00447fa
JS		 1082 /* interface format */
1083 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1084 case SND_SOC_DAIFMT_I2S:
1085 break;
1086 case SND_SOC_DAIFMT_DSP_A:
3e146b55
GS		 1087 dsp_a_val = 0x1;
1088 fallthrough;
e00447fa 1089 case SND_SOC_DAIFMT_DSP_B:
dcb407b2
AD		 1090 /*
1091 * NOTE: This CODEC samples on the falling edge of BCLK in
1092 * DSP mode, this is inverted compared to what most DAIs
1093 * expect, so we invert for this mode
1094 */
1095 iface_reg2 ^= AIC31XX_BCLKINV_MASK;
e00447fa
JS		 1096 iface_reg1 |= (AIC31XX_DSP_MODE <<
1097 AIC31XX_IFACE1_DATATYPE_SHIFT);
1098 break;
1099 case SND_SOC_DAIFMT_RIGHT_J:
1100 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
1101 AIC31XX_IFACE1_DATATYPE_SHIFT);
1102 break;
1103 case SND_SOC_DAIFMT_LEFT_J:
1104 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
1105 AIC31XX_IFACE1_DATATYPE_SHIFT);
1106 break;
1107 default:
f2e6f95b 1108 dev_err(component->dev, "Invalid DAI interface format\n");
e00447fa
JS		 1109 return -EINVAL;
1110 }
1111
f2e6f95b 1112 snd_soc_component_update_bits(component, AIC31XX_IFACE1,
e00447fa
JS		 1113 AIC31XX_IFACE1_DATATYPE_MASK |
1114 AIC31XX_IFACE1_MASTER_MASK,
1115 iface_reg1);
f2e6f95b 1116 snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET,
e00447fa
JS		 1117 AIC31XX_DATA_OFFSET_MASK,
1118 dsp_a_val);
f2e6f95b 1119 snd_soc_component_update_bits(component, AIC31XX_IFACE2,
e00447fa 1120 AIC31XX_BCLKINV_MASK,
085f3ec6 1121 iface_reg2);
e00447fa 1122
d460b3f8 1123 return aic31xx_clock_master_routes(component, fmt);
e00447fa
JS		 1124}
1125
1126static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1127 int clk_id, unsigned int freq, int dir)
1128{
f2e6f95b
KM		 1129 struct snd_soc_component *component = codec_dai->component;
1130 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
e00447fa
JS		 1131 int i;
1132
f2e6f95b 1133 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
e00447fa
JS		 1134 __func__, clk_id, freq, dir);
1135
ca7840fb
AD		 1136 for (i = 1; i < 8; i++)
1137 if (freq / i <= 20000000)
1138 break;
7ed36e96
JS		 1139 if (freq/i > 20000000) {
1140 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
1141 __func__, freq);
7806869c 1142 return -EINVAL;
7ed36e96
JS		 1143 }
1144 aic31xx->p_div = i;
1145
ca7840fb
AD		 1146 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++)
1147 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div)
1148 break;
bbc686b3
JS		 1149 if (i == ARRAY_SIZE(aic31xx_divs)) {
1150 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
1151 __func__, freq);
1152 return -EINVAL;
e00447fa
JS		 1153 }
1154
1155 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
f2e6f95b 1156 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
e00447fa
JS		 1157 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
1158
1159 aic31xx->sysclk = freq;
ca7840fb 1160
e00447fa
JS		 1161 return 0;
1162}
1163
1164static int aic31xx_regulator_event(struct notifier_block *nb,
1165 unsigned long event, void *data)
1166{
1167 struct aic31xx_disable_nb *disable_nb =
1168 container_of(nb, struct aic31xx_disable_nb, nb);
1169 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
1170
1171 if (event & REGULATOR_EVENT_DISABLE) {
1172 /*
1173 * Put codec to reset and as at least one of the
1174 * supplies was disabled.
1175 */
b6b247cd
AD		 1176 if (aic31xx->gpio_reset)
1177 gpiod_set_value(aic31xx->gpio_reset, 1);
e00447fa
JS		 1178
1179 regcache_mark_dirty(aic31xx->regmap);
1180 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
1181 }
1182
1183 return 0;
1184}
1185
0ce918c9
AD		 1186static int aic31xx_reset(struct aic31xx_priv *aic31xx)
1187{
1188 int ret = 0;
1189
1190 if (aic31xx->gpio_reset) {
1191 gpiod_set_value(aic31xx->gpio_reset, 1);
1192 ndelay(10); /* At least 10ns */
1193 gpiod_set_value(aic31xx->gpio_reset, 0);
1194 } else {
1195 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1);
1196 }
1197 mdelay(1); /* At least 1ms */
1198
1199 return ret;
1200}
1201
f2e6f95b 1202static void aic31xx_clk_on(struct snd_soc_component *component)
e00447fa 1203{
f2e6f95b 1204 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
e00447fa
JS		 1205 u8 mask = AIC31XX_PM_MASK;
1206 u8 on = AIC31XX_PM_MASK;
1207
f2e6f95b 1208 dev_dbg(component->dev, "codec clock -> on (rate %d)\n",
e00447fa 1209 aic31xx_divs[aic31xx->rate_div_line].rate);
f2e6f95b 1210 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on);
e00447fa 1211 mdelay(10);
f2e6f95b
KM		 1212 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on);
1213 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on);
e00447fa 1214 if (aic31xx_divs[aic31xx->rate_div_line].nadc)
f2e6f95b 1215 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on);
e00447fa 1216 if (aic31xx_divs[aic31xx->rate_div_line].madc)
f2e6f95b
KM		 1217 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on);
1218 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on);
e00447fa
JS		 1219}
1220
f2e6f95b 1221static void aic31xx_clk_off(struct snd_soc_component *component)
e00447fa 1222{
e00447fa
JS		 1223 u8 mask = AIC31XX_PM_MASK;
1224 u8 off = 0;
1225
f2e6f95b
KM		 1226 dev_dbg(component->dev, "codec clock -> off\n");
1227 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off);
1228 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off);
1229 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off);
1230 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off);
1231 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off);
1232 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off);
e00447fa
JS		 1233}
1234
f2e6f95b 1235static int aic31xx_power_on(struct snd_soc_component *component)
e00447fa 1236{
f2e6f95b 1237 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
ca7840fb 1238 int ret;
e00447fa
JS		 1239
1240 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
1241 aic31xx->supplies);
1242 if (ret)
1243 return ret;
1244
e00447fa 1245 regcache_cache_only(aic31xx->regmap, false);
0ce918c9
AD		 1246
1247 /* Reset device registers for a consistent power-on like state */
1248 ret = aic31xx_reset(aic31xx);
1249 if (ret < 0)
1250 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret);
1251
e00447fa 1252 ret = regcache_sync(aic31xx->regmap);
ca7840fb 1253 if (ret) {
f2e6f95b 1254 dev_err(component->dev,
e00447fa
JS		 1255 "Failed to restore cache: %d\n", ret);
1256 regcache_cache_only(aic31xx->regmap, true);
1257 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1258 aic31xx->supplies);
1259 return ret;
1260 }
ca7840fb 1261
2c39ca68
MB		 1262 /*
1263 * The jack detection configuration is in the same register
1264 * that is used to report jack detect status so is volatile
1265 * and not covered by the cache sync, restore it separately.
1266 */
1267 aic31xx_set_jack(component, aic31xx->jack, NULL);
1268
e00447fa
JS		 1269 return 0;
1270}
1271
f2e6f95b 1272static void aic31xx_power_off(struct snd_soc_component *component)
e00447fa 1273{
f2e6f95b 1274 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
e00447fa
JS		 1275
1276 regcache_cache_only(aic31xx->regmap, true);
c7734e8e
AD		 1277 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1278 aic31xx->supplies);
e00447fa
JS		 1279}
1280
f2e6f95b 1281static int aic31xx_set_bias_level(struct snd_soc_component *component,
e00447fa
JS		 1282 enum snd_soc_bias_level level)
1283{
f2e6f95b
KM		 1284 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,
1285 snd_soc_component_get_bias_level(component), level);
e00447fa
JS		 1286
1287 switch (level) {
1288 case SND_SOC_BIAS_ON:
1289 break;
1290 case SND_SOC_BIAS_PREPARE:
f2e6f95b
KM		 1291 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
1292 aic31xx_clk_on(component);
e00447fa
JS		 1293 break;
1294 case SND_SOC_BIAS_STANDBY:
f2e6f95b 1295 switch (snd_soc_component_get_bias_level(component)) {
e00447fa 1296 case SND_SOC_BIAS_OFF:
f2e6f95b 1297 aic31xx_power_on(component);
e00447fa
JS		 1298 break;
1299 case SND_SOC_BIAS_PREPARE:
f2e6f95b 1300 aic31xx_clk_off(component);
e00447fa
JS		 1301 break;
1302 default:
1303 BUG();
1304 }
1305 break;
1306 case SND_SOC_BIAS_OFF:
f2e6f95b
KM		 1307 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
1308 aic31xx_power_off(component);
e00447fa
JS		 1309 break;
1310 }
e00447fa
JS		 1311
1312 return 0;
1313}
1314
7742a5b4 1315static int aic31xx_set_jack(struct snd_soc_component *component,
1316 struct snd_soc_jack *jack, void *data)
ebf3326c
AD		 1317{
1318 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1319
1320 aic31xx->jack = jack;
1321
1322 /* Enable/Disable jack detection */
1323 regmap_write(aic31xx->regmap, AIC31XX_HSDETECT,
1324 jack ? AIC31XX_HSD_ENABLE : 0);
1325
1326 return 0;
1327}
1328
f2e6f95b 1329static int aic31xx_codec_probe(struct snd_soc_component *component)
e00447fa 1330{
f2e6f95b 1331 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
ca7840fb 1332 int i, ret;
e00447fa
JS		 1333
1334 dev_dbg(aic31xx->dev, "## %s\n", __func__);
1335
f2e6f95b 1336 aic31xx->component = component;
e00447fa 1337
e00447fa
JS		 1338 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1339 aic31xx->disable_nb[i].nb.notifier_call =
1340 aic31xx_regulator_event;
1341 aic31xx->disable_nb[i].aic31xx = aic31xx;
0bb423f2
GL		 1342 ret = devm_regulator_register_notifier(
1343 aic31xx->supplies[i].consumer,
1344 &aic31xx->disable_nb[i].nb);
e00447fa 1345 if (ret) {
f2e6f95b 1346 dev_err(component->dev,
e00447fa
JS		 1347 "Failed to request regulator notifier: %d\n",
1348 ret);
1349 return ret;
1350 }
1351 }
1352
1353 regcache_cache_only(aic31xx->regmap, true);
1354 regcache_mark_dirty(aic31xx->regmap);
1355
f2e6f95b 1356 ret = aic31xx_add_controls(component);
e00447fa
JS		 1357 if (ret)
1358 return ret;
1359
f2e6f95b 1360 ret = aic31xx_add_widgets(component);
ca7840fb
AD		 1361 if (ret)
1362 return ret;
e00447fa 1363
e48fdb53
LS		 1364 /* set output common-mode voltage */
1365 snd_soc_component_update_bits(component, AIC31XX_HPDRIVER,
1366 AIC31XX_HPD_OCMV_MASK,
1367 aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT);
1368
ca7840fb 1369 return 0;
e00447fa
JS		 1370}
1371
f2e6f95b 1372static const struct snd_soc_component_driver soc_codec_driver_aic31xx = {
e00447fa 1373 .probe = aic31xx_codec_probe,
ebf3326c 1374 .set_jack = aic31xx_set_jack,
e00447fa 1375 .set_bias_level = aic31xx_set_bias_level,
f2e6f95b
KM		 1376 .controls = common31xx_snd_controls,
1377 .num_controls = ARRAY_SIZE(common31xx_snd_controls),
1378 .dapm_widgets = common31xx_dapm_widgets,
1379 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets),
1380 .dapm_routes = common31xx_audio_map,
1381 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map),
1382 .suspend_bias_off = 1,
1383 .idle_bias_on = 1,
1384 .use_pmdown_time = 1,
1385 .endianness = 1,
1386 .non_legacy_dai_naming = 1,
e00447fa
JS		 1387};
1388
64793047 1389static const struct snd_soc_dai_ops aic31xx_dai_ops = {
e00447fa
JS		 1390 .hw_params = aic31xx_hw_params,
1391 .set_sysclk = aic31xx_set_dai_sysclk,
1392 .set_fmt = aic31xx_set_dai_fmt,
960af79d
KM		 1393 .mute_stream = aic31xx_dac_mute,
1394 .no_capture_mute = 1,
e00447fa
JS		 1395};
1396
ef9656b6
NY		 1397static struct snd_soc_dai_driver dac31xx_dai_driver[] = {
1398 {
51827c41 1399 .name = "tlv320dac31xx-hifi",
ef9656b6
NY		 1400 .playback = {
1401 .stream_name = "Playback",
3520646d 1402 .channels_min = 2,
ef9656b6
NY		 1403 .channels_max = 2,
1404 .rates = AIC31XX_RATES,
1405 .formats = AIC31XX_FORMATS,
1406 },
1407 .ops = &aic31xx_dai_ops,
a9aef184 1408 .symmetric_rate = 1,
ef9656b6
NY		 1409 }
1410};
1411
e00447fa
JS		 1412static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1413 {
1414 .name = "tlv320aic31xx-hifi",
1415 .playback = {
1416 .stream_name = "Playback",
3520646d 1417 .channels_min = 2,
e00447fa
JS		 1418 .channels_max = 2,
1419 .rates = AIC31XX_RATES,
1420 .formats = AIC31XX_FORMATS,
1421 },
1422 .capture = {
1423 .stream_name = "Capture",
3520646d 1424 .channels_min = 2,
e00447fa
JS		 1425 .channels_max = 2,
1426 .rates = AIC31XX_RATES,
1427 .formats = AIC31XX_FORMATS,
1428 },
1429 .ops = &aic31xx_dai_ops,
a9aef184 1430 .symmetric_rate = 1,
e00447fa
JS		 1431 }
1432};
1433
1434#if defined(CONFIG_OF)
1435static const struct of_device_id tlv320aic31xx_of_match[] = {
1436 { .compatible = "ti,tlv320aic310x" },
1437 { .compatible = "ti,tlv320aic311x" },
1438 { .compatible = "ti,tlv320aic3100" },
1439 { .compatible = "ti,tlv320aic3110" },
1440 { .compatible = "ti,tlv320aic3120" },
1441 { .compatible = "ti,tlv320aic3111" },
a4a1d79e 1442 { .compatible = "ti,tlv320dac3100" },
4e2cc814 1443 { .compatible = "ti,tlv320dac3101" },
e00447fa
JS		 1444 {},
1445};
1446MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
e00447fa
JS		 1447#endif /* CONFIG_OF */
1448
09303601
AD		 1449#ifdef CONFIG_ACPI
1450static const struct acpi_device_id aic31xx_acpi_match[] = {
1451 { "10TI3100", 0 },
1452 { }
1453};
1454MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);
1455#endif
1456
80863ee2
AD		 1457static irqreturn_t aic31xx_irq(int irq, void *data)
1458{
1459 struct aic31xx_priv *aic31xx = data;
1460 struct device *dev = aic31xx->dev;
1461 unsigned int value;
1462 bool handled = false;
1463 int ret;
1464
1465 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value);
1466 if (ret) {
1467 dev_err(dev, "Failed to read interrupt mask: %d\n", ret);
1468 goto exit;
1469 }
1470
1471 if (value)
1472 handled = true;
1473 else
18d545bb 1474 goto read_overflow;
80863ee2
AD		 1475
1476 if (value & AIC31XX_HPLSCDETECT)
1477 dev_err(dev, "Short circuit on Left output is detected\n");
1478 if (value & AIC31XX_HPRSCDETECT)
1479 dev_err(dev, "Short circuit on Right output is detected\n");
90f0202b 1480 if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) {
ebf3326c
AD		 1481 unsigned int val;
1482 int status = 0;
1483
90f0202b
AD		 1484 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2,
1485 &val);
1486 if (ret) {
1487 dev_err(dev, "Failed to read interrupt mask: %d\n",
1488 ret);
1489 goto exit;
1490 }
1491
1492 if (val & AIC31XX_BUTTONPRESS)
1493 status |= SND_JACK_BTN_0;
1494
ebf3326c
AD		 1495 ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val);
1496 if (ret) {
1497 dev_err(dev, "Failed to read headset type: %d\n", ret);
1498 goto exit;
1499 }
1500
1501 switch ((val & AIC31XX_HSD_TYPE_MASK) >>
1502 AIC31XX_HSD_TYPE_SHIFT) {
1503 case AIC31XX_HSD_HP:
1504 status |= SND_JACK_HEADPHONE;
1505 break;
1506 case AIC31XX_HSD_HS:
1507 status |= SND_JACK_HEADSET;
1508 break;
1509 default:
1510 break;
1511 }
1512
1513 if (aic31xx->jack)
1514 snd_soc_jack_report(aic31xx->jack, status,
1515 AIC31XX_JACK_MASK);
1516 }
80863ee2 1517 if (value & ~(AIC31XX_HPLSCDETECT |
ebf3326c 1518 AIC31XX_HPRSCDETECT |
90f0202b
AD		 1519 AIC31XX_HSPLUG |
1520 AIC31XX_BUTTONPRESS))
80863ee2
AD		 1521 dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value);
1522
18d545bb
AD		 1523read_overflow:
1524 ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value);
1525 if (ret) {
1526 dev_err(dev, "Failed to read overflow flag: %d\n", ret);
1527 goto exit;
1528 }
1529
1530 if (value)
1531 handled = true;
1532 else
1533 goto exit;
1534
1535 if (value & AIC31XX_DAC_OF_LEFT)
1536 dev_warn(dev, "Left-channel DAC overflow has occurred\n");
1537 if (value & AIC31XX_DAC_OF_RIGHT)
1538 dev_warn(dev, "Right-channel DAC overflow has occurred\n");
1539 if (value & AIC31XX_DAC_OF_SHIFTER)
1540 dev_warn(dev, "DAC barrel shifter overflow has occurred\n");
1541 if (value & AIC31XX_ADC_OF)
1542 dev_warn(dev, "ADC overflow has occurred\n");
1543 if (value & AIC31XX_ADC_OF_SHIFTER)
1544 dev_warn(dev, "ADC barrel shifter overflow has occurred\n");
1545 if (value & ~(AIC31XX_DAC_OF_LEFT |
1546 AIC31XX_DAC_OF_RIGHT |
1547 AIC31XX_DAC_OF_SHIFTER |
1548 AIC31XX_ADC_OF |
1549 AIC31XX_ADC_OF_SHIFTER))
1550 dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value);
1551
80863ee2
AD		 1552exit:
1553 if (handled)
1554 return IRQ_HANDLED;
1555 else
1556 return IRQ_NONE;
1557}
1558
e48fdb53
LS		 1559static void aic31xx_configure_ocmv(struct aic31xx_priv *priv)
1560{
1561 struct device *dev = priv->dev;
1562 int dvdd, avdd;
1563 u32 value;
1564
1565 if (dev->fwnode &&
1566 fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) {
1567 /* OCMV setting is forced by DT */
1568 if (value <= 3) {
1569 priv->ocmv = value;
1570 return;
1571 }
1572 }
1573
1574 avdd = regulator_get_voltage(priv->supplies[3].consumer);
1575 dvdd = regulator_get_voltage(priv->supplies[5].consumer);
1576
1577 if (avdd > 3600000 || dvdd > 1950000) {
1578 dev_warn(dev,
1579 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
1580 avdd, dvdd);
1581 } else if (avdd == 3600000 && dvdd == 1950000) {
1582 priv->ocmv = AIC31XX_HPD_OCMV_1_8V;
1583 } else if (avdd >= 3300000 && dvdd >= 1800000) {
1584 priv->ocmv = AIC31XX_HPD_OCMV_1_65V;
1585 } else if (avdd >= 3000000 && dvdd >= 1650000) {
1586 priv->ocmv = AIC31XX_HPD_OCMV_1_5V;
1587 } else if (avdd >= 2700000 && dvdd >= 1525000) {
1588 priv->ocmv = AIC31XX_HPD_OCMV_1_35V;
1589 } else {
1590 dev_warn(dev,
1591 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
1592 avdd, dvdd);
1593 }
1594}
1595
e88c3881
AD		 1596static int aic31xx_i2c_probe(struct i2c_client *i2c,
1597 const struct i2c_device_id *id)
e00447fa 1598{
e88c3881 1599 struct aic31xx_priv *aic31xx;
cd15da88 1600 unsigned int micbias_value = MICBIAS_2_0V;
e88c3881
AD		 1601 int i, ret;
1602
1603 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1604 id->name, (int)id->driver_data);
1605
1606 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
1607 if (!aic31xx)
1608 return -ENOMEM;
1609
1610 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap);
1611 if (IS_ERR(aic31xx->regmap)) {
1612 ret = PTR_ERR(aic31xx->regmap);
1613 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1614 ret);
1615 return ret;
1616 }
6c621b81
MB		 1617 regcache_cache_only(aic31xx->regmap, true);
1618
e88c3881 1619 aic31xx->dev = &i2c->dev;
80863ee2 1620 aic31xx->irq = i2c->irq;
e88c3881 1621
cd15da88 1622 aic31xx->codec_type = id->driver_data;
e00447fa
JS		 1623
1624 dev_set_drvdata(aic31xx->dev, aic31xx);
1625
cd15da88
AD		 1626 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg",
1627 &micbias_value);
1628 switch (micbias_value) {
1629 case MICBIAS_2_0V:
1630 case MICBIAS_2_5V:
1631 case MICBIAS_AVDDV:
1632 aic31xx->micbias_vg = micbias_value;
1633 break;
1634 default:
1635 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n",
1636 micbias_value);
1637 aic31xx->micbias_vg = MICBIAS_2_0V;
1638 }
1639
1640 if (dev_get_platdata(aic31xx->dev)) {
1641 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata));
1642 aic31xx->codec_type = aic31xx->pdata.codec_type;
1643 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg;
1644 }
e00447fa 1645
b6b247cd
AD		 1646 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset",
1647 GPIOD_OUT_LOW);
1648 if (IS_ERR(aic31xx->gpio_reset)) {
b7e814de
LS		 1649 if (PTR_ERR(aic31xx->gpio_reset) != -EPROBE_DEFER)
1650 dev_err(aic31xx->dev, "not able to acquire gpio\n");
b6b247cd 1651 return PTR_ERR(aic31xx->gpio_reset);
e00447fa
JS		 1652 }
1653
1654 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1655 aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1656
1657 ret = devm_regulator_bulk_get(aic31xx->dev,
1658 ARRAY_SIZE(aic31xx->supplies),
1659 aic31xx->supplies);
ca7840fb 1660 if (ret) {
b7e814de
LS		 1661 if (ret != -EPROBE_DEFER)
1662 dev_err(aic31xx->dev,
1663 "Failed to request supplies: %d\n", ret);
ca7840fb
AD		 1664 return ret;
1665 }
e00447fa 1666
e48fdb53
LS		 1667 aic31xx_configure_ocmv(aic31xx);
1668
80863ee2
AD		 1669 if (aic31xx->irq > 0) {
1670 regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1,
1671 AIC31XX_GPIO1_FUNC_MASK,
1672 AIC31XX_GPIO1_INT1 <<
1673 AIC31XX_GPIO1_FUNC_SHIFT);
1674
1675 regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL,
ebf3326c 1676 AIC31XX_HSPLUGDET |
90f0202b 1677 AIC31XX_BUTTONPRESSDET |
18d545bb
AD		 1678 AIC31XX_SC |
1679 AIC31XX_ENGINE);
80863ee2
AD		 1680
1681 ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq,
1682 NULL, aic31xx_irq,
1683 IRQF_ONESHOT, "aic31xx-irq",
1684 aic31xx);
1685 if (ret) {
1686 dev_err(aic31xx->dev, "Unable to request IRQ\n");
1687 return ret;
1688 }
1689 }
1690
cd15da88 1691 if (aic31xx->codec_type & DAC31XX_BIT)
f2e6f95b 1692 return devm_snd_soc_register_component(&i2c->dev,
ef9656b6
NY		 1693 &soc_codec_driver_aic31xx,
1694 dac31xx_dai_driver,
1695 ARRAY_SIZE(dac31xx_dai_driver));
1696 else
f2e6f95b 1697 return devm_snd_soc_register_component(&i2c->dev,
ef9656b6
NY		 1698 &soc_codec_driver_aic31xx,
1699 aic31xx_dai_driver,
1700 ARRAY_SIZE(aic31xx_dai_driver));
e00447fa
JS		 1701}
1702
e00447fa
JS		 1703static const struct i2c_device_id aic31xx_i2c_id[] = {
1704 { "tlv320aic310x", AIC3100 },
1705 { "tlv320aic311x", AIC3110 },
1706 { "tlv320aic3100", AIC3100 },
1707 { "tlv320aic3110", AIC3110 },
1708 { "tlv320aic3120", AIC3120 },
1709 { "tlv320aic3111", AIC3111 },
ef9656b6 1710 { "tlv320dac3100", DAC3100 },
4e2cc814 1711 { "tlv320dac3101", DAC3101 },
e00447fa
JS		 1712 { }
1713};
1714MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1715
1716static struct i2c_driver aic31xx_i2c_driver = {
1717 .driver = {
1718 .name = "tlv320aic31xx-codec",
e00447fa 1719 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
f5cc1772 1720 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match),
e00447fa
JS		 1721 },
1722 .probe = aic31xx_i2c_probe,
e00447fa
JS		 1723 .id_table = aic31xx_i2c_id,
1724};
e00447fa
JS		 1725module_i2c_driver(aic31xx_i2c_driver);
1726
b1c52b7e
AD		 1727MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
1728MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");
1729MODULE_LICENSE("GPL v2");
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