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[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / tlv320aic32x4.c
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16216333 1// SPDX-License-Identifier: GPL-2.0-or-later
1d471cd1
JM		 2/*
3 * linux/sound/soc/codecs/tlv320aic32x4.c
4 *
5 * Copyright 2011 Vista Silicon S.L.
6 *
7 * Author: Javier Martin <javier.martin@vista-silicon.com>
8 *
9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
1d471cd1
JM		 10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
1858fe97 17#include <linux/gpio.h>
4d16700d 18#include <linux/of_gpio.h>
1d471cd1
JM		 19#include <linux/cdev.h>
20#include <linux/slab.h>
98b664e2 21#include <linux/clk.h>
514b044c 22#include <linux/of_clk.h>
239b669b 23#include <linux/regulator/consumer.h>
1d471cd1
JM		 24
25#include <sound/tlv320aic32x4.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
34#include "tlv320aic32x4.h"
35
1d471cd1 36struct aic32x4_priv {
4d208ca4 37 struct regmap *regmap;
1d471cd1
JM		 38 u32 power_cfg;
39 u32 micpga_routing;
40 bool swapdacs;
1858fe97 41 int rstn_gpio;
514b044c 42 const char *mclk_name;
239b669b
MP		 43
44 struct regulator *supply_ldo;
45 struct regulator *supply_iov;
46 struct regulator *supply_dv;
47 struct regulator *supply_av;
b9045b9c
DM		 48
49 struct aic32x4_setup_data *setup;
50 struct device *dev;
51};
52
04d979d7 53static int mic_bias_event(struct snd_soc_dapm_widget *w,
54 struct snd_kcontrol *kcontrol, int event)
55{
56 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
57
58 switch (event) {
59 case SND_SOC_DAPM_POST_PMU:
60 /* Change Mic Bias Registor */
61 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
62 AIC32x4_MICBIAS_MASK,
63 AIC32X4_MICBIAS_LDOIN |
64 AIC32X4_MICBIAS_2075V);
65 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
66 break;
67 case SND_SOC_DAPM_PRE_PMD:
68 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
69 AIC32x4_MICBIAS_MASK, 0);
70 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
71 __func__);
72 break;
73 }
74
75 return 0;
76}
77
78
b9045b9c
DM		 79static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
80 struct snd_ctl_elem_value *ucontrol)
81{
b154dc5d 82 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 83 u8 val;
84
b154dc5d 85 val = snd_soc_component_read32(component, AIC32X4_DINCTL);
b9045b9c
DM		 86
87 ucontrol->value.integer.value[0] = (val & 0x01);
88
89 return 0;
90};
91
92static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
93 struct snd_ctl_elem_value *ucontrol)
94{
b154dc5d 95 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 96 u8 val;
97 u8 gpio_check;
98
b154dc5d 99 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL);
b9045b9c
DM		 100 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
101 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
102 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
103 __func__);
104 return -EINVAL;
105 }
106
107 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
108 return 0;
109
110 if (ucontrol->value.integer.value[0])
111 val |= ucontrol->value.integer.value[0];
112 else
113 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
114
b154dc5d 115 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
b9045b9c
DM		 116
117 return 0;
118};
119
120static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
121 struct snd_ctl_elem_value *ucontrol)
122{
b154dc5d 123 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 124 u8 val;
125
b154dc5d 126 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL);
b9045b9c
DM		 127
128 ucontrol->value.integer.value[0] = (val & 0x01);
129
130 return 0;
131};
132
133static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
134 struct snd_ctl_elem_value *ucontrol)
135{
b154dc5d 136 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 137 u8 val;
138 u8 gpio_check;
139
b154dc5d 140 val = snd_soc_component_read32(component, AIC32X4_MISOCTL);
b9045b9c
DM		 141 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
142 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
143 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
144 __func__);
145 return -EINVAL;
146 }
147
148 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
149 return 0;
150
151 if (ucontrol->value.integer.value[0])
152 val |= ucontrol->value.integer.value[0];
153 else
154 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
155
b154dc5d 156 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
b9045b9c
DM		 157
158 return 0;
159};
160
161static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
162 struct snd_ctl_elem_value *ucontrol)
163{
b154dc5d 164 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 165 u8 val;
166
b154dc5d 167 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
b9045b9c
DM		 168 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
169
170 return 0;
171};
172
173static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
174 struct snd_ctl_elem_value *ucontrol)
175{
b154dc5d 176 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 177 u8 val;
178 u8 gpio_check;
179
b154dc5d 180 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
b9045b9c
DM		 181 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
182 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
183 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
184 __func__);
185 return -EINVAL;
186 }
187
188 if (ucontrol->value.integer.value[0] == (val & 0x1))
189 return 0;
190
191 if (ucontrol->value.integer.value[0])
192 val |= ucontrol->value.integer.value[0];
193 else
194 val &= 0xfe;
195
b154dc5d 196 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
b9045b9c
DM		 197
198 return 0;
199};
200
201static const struct snd_kcontrol_new aic32x4_mfp1[] = {
202 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
203};
204
205static const struct snd_kcontrol_new aic32x4_mfp2[] = {
206 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
207};
208
209static const struct snd_kcontrol_new aic32x4_mfp3[] = {
210 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
211};
212
213static const struct snd_kcontrol_new aic32x4_mfp4[] = {
214 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
215};
216
217static const struct snd_kcontrol_new aic32x4_mfp5[] = {
218 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
219 aic32x4_set_mfp5_gpio),
1d471cd1
JM		 220};
221
1d471cd1
JM		 222/* 0dB min, 0.5dB steps */
223static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
c671e79d
MP		 224/* -63.5dB min, 0.5dB steps */
225static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
226/* -6dB min, 1dB steps */
227static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
228/* -12dB min, 0.5dB steps */
229static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
1d471cd1 230
44ceee84
AM		 231static const char * const lo_cm_text[] = {
232 "Full Chip", "1.65V",
233};
234
235static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
236
d3e6e374
AM		 237static const char * const ptm_text[] = {
238 "P3", "P2", "P1",
239};
240
241static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
242static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
243
1d471cd1 244static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
c671e79d
MP		 245 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
246 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
d3e6e374
AM		 247 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
248 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
c671e79d
MP		 249 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
250 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
251 tlv_driver_gain),
252 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
253 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
254 tlv_driver_gain),
1d471cd1
JM		 255 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
256 AIC32X4_HPRGAIN, 6, 0x01, 1),
257 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
258 AIC32X4_LORGAIN, 6, 0x01, 1),
44ceee84 259 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
1d471cd1
JM		 260 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
261 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
262
263 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
264 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
265
c671e79d
MP		 266 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
267 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
1d471cd1
JM		 268 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
269 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
270
271 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
272
273 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
274 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
275 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
276 4, 0x07, 0),
277 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
278 0, 0x03, 0),
279 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
280 6, 0x03, 0),
281 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
282 1, 0x1F, 0),
283 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
284 0, 0x7F, 0),
285 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
286 3, 0x1F, 0),
287 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
288 3, 0x1F, 0),
289 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
290 0, 0x1F, 0),
291 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
292 0, 0x0F, 0),
293};
294
1d471cd1
JM		 295static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
296 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
297 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
298};
299
300static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
301 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
302 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
303};
304
305static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
306 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
307};
308
309static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
310 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
311};
312
20d2cecb
JM		 313static const char * const resistor_text[] = {
314 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
315};
316
2213fc35
JM		 317/* Left mixer pins */
318static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
319static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
320static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
321static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
322
323static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
324static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
325static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
326
327static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
328 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
329};
330static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
331 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
332};
333static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
334 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
335};
336static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
337 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
338};
339static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
340 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
341};
342static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
343 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
344};
345static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
346 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
1d471cd1
JM		 347};
348
514b044c 349/* Right mixer pins */
2213fc35
JM		 350static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
351static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
352static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
353static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
354static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
355static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
356static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
357
358static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
359 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
360};
361static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
362 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
363};
364static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
365 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
366};
367static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
368 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
369};
370static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
371 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
372};
373static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
374 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
375};
376static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
377 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
1d471cd1
JM		 378};
379
380static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
381 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
382 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
383 &hpl_output_mixer_controls[0],
384 ARRAY_SIZE(hpl_output_mixer_controls)),
385 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
386
387 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
388 &lol_output_mixer_controls[0],
389 ARRAY_SIZE(lol_output_mixer_controls)),
390 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
391
392 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
393 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
394 &hpr_output_mixer_controls[0],
395 ARRAY_SIZE(hpr_output_mixer_controls)),
396 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
397 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
398 &lor_output_mixer_controls[0],
399 ARRAY_SIZE(lor_output_mixer_controls)),
400 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
2213fc35 401
1d471cd1 402 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
2213fc35
JM		 403 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
404 in1r_to_rmixer_controls),
405 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
406 in2r_to_rmixer_controls),
407 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
408 in3r_to_rmixer_controls),
409 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
410 in2l_to_rmixer_controls),
411 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
412 cmr_to_rmixer_controls),
413 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
414 in1l_to_rmixer_controls),
415 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
416 in3l_to_rmixer_controls),
417
418 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
419 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
420 in1l_to_lmixer_controls),
421 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
422 in2l_to_lmixer_controls),
423 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
424 in3l_to_lmixer_controls),
425 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
426 in1r_to_lmixer_controls),
427 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
428 cml_to_lmixer_controls),
429 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
430 in2r_to_lmixer_controls),
431 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
432 in3r_to_lmixer_controls),
433
04d979d7 434 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
435 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
436
1d471cd1
JM		 437
438 SND_SOC_DAPM_OUTPUT("HPL"),
439 SND_SOC_DAPM_OUTPUT("HPR"),
440 SND_SOC_DAPM_OUTPUT("LOL"),
441 SND_SOC_DAPM_OUTPUT("LOR"),
442 SND_SOC_DAPM_INPUT("IN1_L"),
443 SND_SOC_DAPM_INPUT("IN1_R"),
444 SND_SOC_DAPM_INPUT("IN2_L"),
445 SND_SOC_DAPM_INPUT("IN2_R"),
446 SND_SOC_DAPM_INPUT("IN3_L"),
447 SND_SOC_DAPM_INPUT("IN3_R"),
c63adb28
AM		 448 SND_SOC_DAPM_INPUT("CM_L"),
449 SND_SOC_DAPM_INPUT("CM_R"),
1d471cd1
JM		 450};
451
452static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
453 /* Left Output */
454 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
455 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
456
457 {"HPL Power", NULL, "HPL Output Mixer"},
458 {"HPL", NULL, "HPL Power"},
459
460 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
461
462 {"LOL Power", NULL, "LOL Output Mixer"},
463 {"LOL", NULL, "LOL Power"},
464
465 /* Right Output */
466 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
467 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
468
469 {"HPR Power", NULL, "HPR Output Mixer"},
470 {"HPR", NULL, "HPR Power"},
471
472 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
473
474 {"LOR Power", NULL, "LOR Output Mixer"},
475 {"LOR", NULL, "LOR Power"},
476
1d471cd1 477 /* Right Input */
2213fc35
JM		 478 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
479 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
480 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
481 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
482
483 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
484 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
485 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
486 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
487
488 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
489 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
490 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
491 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
492
493 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
494 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
495 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
496 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
497
498 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
499 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
500 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
501 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
502
503 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
504 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
505 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
506 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
507
508 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
509 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
510 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
511 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
512
513 /* Left Input */
514 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
515 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
516 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
517 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
518
519 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
520 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
521 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
522 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
523
524 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
525 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
526 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
527 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
528
529 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
530 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
531 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
532 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
533
534 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
535 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
536 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
537 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
538
539 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
540 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
541 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
542 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
543
544 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
545 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
546 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
547 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
1d471cd1
JM		 548};
549
4d208ca4
MB		 550static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
551 {
552 .selector_reg = 0,
514b044c 553 .selector_mask = 0xff,
4d208ca4
MB		 554 .window_start = 0,
555 .window_len = 128,
e8e08c52 556 .range_min = 0,
6d0d5103 557 .range_max = AIC32X4_RMICPGAVOL,
4d208ca4
MB		 558 },
559};
1d471cd1 560
3bcfd222 561const struct regmap_config aic32x4_regmap_config = {
4d208ca4
MB		 562 .max_register = AIC32X4_RMICPGAVOL,
563 .ranges = aic32x4_regmap_pages,
564 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
565};
3bcfd222 566EXPORT_SYMBOL(aic32x4_regmap_config);
1d471cd1 567
1d471cd1
JM		 568static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
569 int clk_id, unsigned int freq, int dir)
570{
b154dc5d 571 struct snd_soc_component *component = codec_dai->component;
aa6a60f7
AM		 572 struct clk *mclk;
573 struct clk *pll;
1d471cd1 574
aa6a60f7 575 pll = devm_clk_get(component->dev, "pll");
1092b097
CY		 576 if (IS_ERR(pll))
577 return PTR_ERR(pll);
578
aa6a60f7
AM		 579 mclk = clk_get_parent(pll);
580
581 return clk_set_rate(mclk, freq);
1d471cd1
JM		 582}
583
584static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
585{
b154dc5d 586 struct snd_soc_component *component = codec_dai->component;
60fb4be5
AD		 587 u8 iface_reg_1 = 0;
588 u8 iface_reg_2 = 0;
589 u8 iface_reg_3 = 0;
1d471cd1
JM		 590
591 /* set master/slave audio interface */
592 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
593 case SND_SOC_DAIFMT_CBM_CFM:
1d471cd1
JM		 594 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
595 break;
596 case SND_SOC_DAIFMT_CBS_CFS:
1d471cd1
JM		 597 break;
598 default:
599 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
600 return -EINVAL;
601 }
602
603 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
604 case SND_SOC_DAIFMT_I2S:
605 break;
606 case SND_SOC_DAIFMT_DSP_A:
4483521d
AD		 607 iface_reg_1 |= (AIC32X4_DSP_MODE <<
608 AIC32X4_IFACE1_DATATYPE_SHIFT);
60fb4be5 609 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
1d471cd1
JM		 610 iface_reg_2 = 0x01; /* add offset 1 */
611 break;
612 case SND_SOC_DAIFMT_DSP_B:
4483521d
AD		 613 iface_reg_1 |= (AIC32X4_DSP_MODE <<
614 AIC32X4_IFACE1_DATATYPE_SHIFT);
60fb4be5 615 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
1d471cd1
JM		 616 break;
617 case SND_SOC_DAIFMT_RIGHT_J:
4483521d
AD		 618 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
619 AIC32X4_IFACE1_DATATYPE_SHIFT);
1d471cd1
JM		 620 break;
621 case SND_SOC_DAIFMT_LEFT_J:
4483521d
AD		 622 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
623 AIC32X4_IFACE1_DATATYPE_SHIFT);
1d471cd1
JM		 624 break;
625 default:
626 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
627 return -EINVAL;
628 }
629
b154dc5d 630 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
514b044c
AM		 631 AIC32X4_IFACE1_DATATYPE_MASK |
632 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
b154dc5d 633 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
514b044c 634 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
b154dc5d 635 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
514b044c 636 AIC32X4_BCLKINV_MASK, iface_reg_3);
60fb4be5 637
1d471cd1
JM		 638 return 0;
639}
640
fbafbf65
AM		 641static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
642{
643 return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
644}
645
646static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
647{
648 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
649 snd_soc_component_write(component, AIC32X4_DOSRLSB,
650 (dosr & 0xff));
651
652 return 0;
653}
654
c95e3a4b
AM		 655static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
656 u8 r_block, u8 p_block)
657{
658 if (r_block > 18 || p_block > 25)
659 return -EINVAL;
660
661 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
662 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
663
664 return 0;
665}
666
bf31cbfb 667static int aic32x4_setup_clocks(struct snd_soc_component *component,
96c3bb00 668 unsigned int sample_rate)
1d471cd1 669{
96c3bb00
AM		 670 u8 aosr;
671 u16 dosr;
672 u8 adc_resource_class, dac_resource_class;
673 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
674 u8 dosr_increment;
675 u16 max_dosr, min_dosr;
83b4f50c 676 unsigned long adc_clock_rate, dac_clock_rate;
514b044c
AM		 677 int ret;
678
679 struct clk_bulk_data clocks[] = {
680 { .id = "pll" },
a51b5006
AM		 681 { .id = "nadc" },
682 { .id = "madc" },
683 { .id = "ndac" },
684 { .id = "mdac" },
9b484124 685 { .id = "bdiv" },
514b044c 686 };
514b044c
AM		 687 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
688 if (ret)
689 return ret;
690
96c3bb00
AM		 691 if (sample_rate <= 48000) {
692 aosr = 128;
693 adc_resource_class = 6;
694 dac_resource_class = 8;
695 dosr_increment = 8;
696 aic32x4_set_processing_blocks(component, 1, 1);
697 } else if (sample_rate <= 96000) {
698 aosr = 64;
699 adc_resource_class = 6;
700 dac_resource_class = 8;
701 dosr_increment = 4;
702 aic32x4_set_processing_blocks(component, 1, 9);
703 } else if (sample_rate == 192000) {
704 aosr = 32;
705 adc_resource_class = 3;
706 dac_resource_class = 4;
707 dosr_increment = 2;
708 aic32x4_set_processing_blocks(component, 13, 19);
709 } else {
710 dev_err(component->dev, "Sampling rate not supported\n");
711 return -EINVAL;
712 }
c95e3a4b 713
96c3bb00
AM		 714 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
715 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
716 dosr_increment;
717 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
718 dosr_increment;
719 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
720
721 for (nadc = max_nadc; nadc > 0; --nadc) {
722 adc_clock_rate = nadc * madc * aosr * sample_rate;
723 for (dosr = max_dosr; dosr >= min_dosr;
724 dosr -= dosr_increment) {
725 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
726 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
727 (min_mdac * dosr * sample_rate);
728 for (mdac = min_mdac; mdac <= 128; ++mdac) {
729 for (ndac = max_ndac; ndac > 0; --ndac) {
730 dac_clock_rate = ndac * mdac * dosr *
731 sample_rate;
732 if (dac_clock_rate == adc_clock_rate) {
733 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
734 continue;
735
736 clk_set_rate(clocks[0].clk,
737 dac_clock_rate);
738
739 clk_set_rate(clocks[1].clk,
740 sample_rate * aosr *
741 madc);
742 clk_set_rate(clocks[2].clk,
743 sample_rate * aosr);
744 aic32x4_set_aosr(component,
745 aosr);
746
747 clk_set_rate(clocks[3].clk,
748 sample_rate * dosr *
749 mdac);
750 clk_set_rate(clocks[4].clk,
751 sample_rate * dosr);
752 aic32x4_set_dosr(component,
753 dosr);
754
755 clk_set_rate(clocks[5].clk,
756 sample_rate * 32);
757 return 0;
758 }
759 }
760 }
761 }
762 }
1d471cd1 763
96c3bb00
AM		 764 dev_err(component->dev,
765 "Could not set clocks to support sample rate.\n");
766 return -EINVAL;
bf31cbfb
AM		 767}
768
769static int aic32x4_hw_params(struct snd_pcm_substream *substream,
a51b5006
AM		 770 struct snd_pcm_hw_params *params,
771 struct snd_soc_dai *dai)
bf31cbfb
AM		 772{
773 struct snd_soc_component *component = dai->component;
774 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
775 u8 iface1_reg = 0;
776 u8 dacsetup_reg = 0;
777
96c3bb00 778 aic32x4_setup_clocks(component, params_rate(params));
bf31cbfb 779
bd8a5711
MB		 780 switch (params_width(params)) {
781 case 16:
64aab899 782 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
514b044c 783 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1 784 break;
bd8a5711 785 case 20:
64aab899 786 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
514b044c 787 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1 788 break;
bd8a5711 789 case 24:
64aab899 790 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
514b044c 791 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1 792 break;
bd8a5711 793 case 32:
64aab899 794 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
514b044c 795 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1
JM		 796 break;
797 }
b154dc5d 798 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
514b044c 799 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
1d471cd1 800
b44aa40f 801 if (params_channels(params) == 1) {
64aab899 802 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
b44aa40f
MP		 803 } else {
804 if (aic32x4->swapdacs)
64aab899 805 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
b44aa40f 806 else
64aab899 807 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
b44aa40f 808 }
b154dc5d 809 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
514b044c 810 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
b44aa40f 811
1d471cd1
JM		 812 return 0;
813}
814
815static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
816{
b154dc5d 817 struct snd_soc_component *component = dai->component;
1d471cd1 818
b154dc5d 819 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
514b044c 820 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
b7ddd9ca 821
1d471cd1
JM		 822 return 0;
823}
824
b154dc5d 825static int aic32x4_set_bias_level(struct snd_soc_component *component,
1d471cd1
JM		 826 enum snd_soc_bias_level level)
827{
98b664e2
MP		 828 int ret;
829
d25970b5
AM		 830 struct clk_bulk_data clocks[] = {
831 { .id = "madc" },
832 { .id = "mdac" },
833 { .id = "bdiv" },
834 };
835
836 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
837 if (ret)
838 return ret;
839
1d471cd1
JM		 840 switch (level) {
841 case SND_SOC_BIAS_ON:
d25970b5 842 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
98b664e2 843 if (ret) {
d25970b5 844 dev_err(component->dev, "Failed to enable clocks\n");
98b664e2
MP		 845 return ret;
846 }
1d471cd1
JM		 847 break;
848 case SND_SOC_BIAS_PREPARE:
849 break;
850 case SND_SOC_BIAS_STANDBY:
667e9334 851 /* Initial cold start */
852 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
853 break;
854
d25970b5 855 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
1d471cd1
JM		 856 break;
857 case SND_SOC_BIAS_OFF:
858 break;
859 }
1d471cd1
JM		 860 return 0;
861}
862
6d56ee15 863#define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000
514b044c 864#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1d471cd1
JM		 865 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
866
85e7652d 867static const struct snd_soc_dai_ops aic32x4_ops = {
1d471cd1
JM		 868 .hw_params = aic32x4_hw_params,
869 .digital_mute = aic32x4_mute,
870 .set_fmt = aic32x4_set_dai_fmt,
871 .set_sysclk = aic32x4_set_dai_sysclk,
872};
873
874static struct snd_soc_dai_driver aic32x4_dai = {
875 .name = "tlv320aic32x4-hifi",
876 .playback = {
514b044c
AM		 877 .stream_name = "Playback",
878 .channels_min = 1,
879 .channels_max = 2,
880 .rates = AIC32X4_RATES,
881 .formats = AIC32X4_FORMATS,},
1d471cd1 882 .capture = {
514b044c
AM		 883 .stream_name = "Capture",
884 .channels_min = 1,
885 .channels_max = 2,
886 .rates = AIC32X4_RATES,
887 .formats = AIC32X4_FORMATS,},
1d471cd1
JM		 888 .ops = &aic32x4_ops,
889 .symmetric_rates = 1,
890};
891
b154dc5d 892static void aic32x4_setup_gpios(struct snd_soc_component *component)
b9045b9c 893{
b154dc5d 894 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
b9045b9c
DM		 895
896 /* setup GPIO functions */
897 /* MFP1 */
898 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 899 snd_soc_component_write(component, AIC32X4_DINCTL,
514b044c 900 aic32x4->setup->gpio_func[0]);
b154dc5d 901 snd_soc_add_component_controls(component, aic32x4_mfp1,
b9045b9c
DM		 902 ARRAY_SIZE(aic32x4_mfp1));
903 }
904
905 /* MFP2 */
906 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 907 snd_soc_component_write(component, AIC32X4_DOUTCTL,
514b044c 908 aic32x4->setup->gpio_func[1]);
b154dc5d 909 snd_soc_add_component_controls(component, aic32x4_mfp2,
b9045b9c
DM		 910 ARRAY_SIZE(aic32x4_mfp2));
911 }
912
913 /* MFP3 */
914 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 915 snd_soc_component_write(component, AIC32X4_SCLKCTL,
514b044c 916 aic32x4->setup->gpio_func[2]);
b154dc5d 917 snd_soc_add_component_controls(component, aic32x4_mfp3,
b9045b9c
DM		 918 ARRAY_SIZE(aic32x4_mfp3));
919 }
920
921 /* MFP4 */
922 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 923 snd_soc_component_write(component, AIC32X4_MISOCTL,
514b044c 924 aic32x4->setup->gpio_func[3]);
b154dc5d 925 snd_soc_add_component_controls(component, aic32x4_mfp4,
b9045b9c
DM		 926 ARRAY_SIZE(aic32x4_mfp4));
927 }
928
929 /* MFP5 */
930 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 931 snd_soc_component_write(component, AIC32X4_GPIOCTL,
514b044c 932 aic32x4->setup->gpio_func[4]);
b154dc5d 933 snd_soc_add_component_controls(component, aic32x4_mfp5,
b9045b9c
DM		 934 ARRAY_SIZE(aic32x4_mfp5));
935 }
936}
937
b154dc5d 938static int aic32x4_component_probe(struct snd_soc_component *component)
1d471cd1 939{
b154dc5d 940 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1d471cd1 941 u32 tmp_reg;
fd2df3ae
AM		 942 int ret;
943
944 struct clk_bulk_data clocks[] = {
a51b5006
AM		 945 { .id = "codec_clkin" },
946 { .id = "pll" },
9b484124
AM		 947 { .id = "bdiv" },
948 { .id = "mdac" },
fd2df3ae
AM		 949 };
950
951 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
952 if (ret)
953 return ret;
1d471cd1 954
a74ab512 955 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1858fe97
JM		 956 ndelay(10);
957 gpio_set_value(aic32x4->rstn_gpio, 1);
674f9abd 958 mdelay(1);
1858fe97
JM		 959 }
960
b154dc5d 961 snd_soc_component_write(component, AIC32X4_RESET, 0x01);
1d471cd1 962
b9045b9c 963 if (aic32x4->setup)
b154dc5d 964 aic32x4_setup_gpios(component);
b9045b9c 965
fd2df3ae 966 clk_set_parent(clocks[0].clk, clocks[1].clk);
9b484124 967 clk_set_parent(clocks[2].clk, clocks[3].clk);
fd2df3ae 968
1d471cd1
JM		 969 /* Power platform configuration */
970 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
514b044c
AM		 971 snd_soc_component_write(component, AIC32X4_MICBIAS,
972 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1d471cd1 973 }
eb72cbdf 974 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
b154dc5d 975 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
0c93a167
WS		 976
977 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
978 AIC32X4_LDOCTLEN : 0;
b154dc5d 979 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
0c93a167 980
b154dc5d 981 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE);
eb72cbdf 982 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1d471cd1 983 tmp_reg |= AIC32X4_LDOIN_18_36;
eb72cbdf 984 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1d471cd1 985 tmp_reg |= AIC32X4_LDOIN2HP;
b154dc5d 986 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1d471cd1 987
1d471cd1 988 /* Mic PGA routing */
609e6025 989 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
b154dc5d 990 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
43bf38ba 991 AIC32X4_LMICPGANIN_IN2R_10K);
609e6025 992 else
b154dc5d 993 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
43bf38ba 994 AIC32X4_LMICPGANIN_CM1L_10K);
609e6025 995 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
b154dc5d 996 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
43bf38ba 997 AIC32X4_RMICPGANIN_IN1L_10K);
609e6025 998 else
b154dc5d 999 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
43bf38ba 1000 AIC32X4_RMICPGANIN_CM1R_10K);
1d471cd1 1001
a405387c
JM		 1002 /*
1003 * Workaround: for an unknown reason, the ADC needs to be powered up
1004 * and down for the first capture to work properly. It seems related to
1005 * a HW BUG or some kind of behavior not documented in the datasheet.
1006 */
b154dc5d
KM		 1007 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);
1008 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
a405387c 1009 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
b154dc5d 1010 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
a405387c 1011
1d471cd1
JM		 1012 return 0;
1013}
1014
b154dc5d
KM		 1015static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1016 .probe = aic32x4_component_probe,
1017 .set_bias_level = aic32x4_set_bias_level,
1018 .controls = aic32x4_snd_controls,
1019 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1020 .dapm_widgets = aic32x4_dapm_widgets,
1021 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1022 .dapm_routes = aic32x4_dapm_routes,
1023 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1024 .suspend_bias_off = 1,
1025 .idle_bias_on = 1,
1026 .use_pmdown_time = 1,
1027 .endianness = 1,
1028 .non_legacy_dai_naming = 1,
1d471cd1
JM		 1029};
1030
4d16700d
MP		 1031static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1032 struct device_node *np)
1033{
b9045b9c 1034 struct aic32x4_setup_data *aic32x4_setup;
514b044c 1035 int ret;
b9045b9c
DM		 1036
1037 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1038 GFP_KERNEL);
1039 if (!aic32x4_setup)
1040 return -ENOMEM;
1041
514b044c
AM		 1042 ret = of_property_match_string(np, "clock-names", "mclk");
1043 if (ret < 0)
1044 return -EINVAL;
1045 aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1046
4d16700d
MP		 1047 aic32x4->swapdacs = false;
1048 aic32x4->micpga_routing = 0;
1049 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1050
b9045b9c
DM		 1051 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1052 aic32x4_setup->gpio_func, 5) >= 0)
1053 aic32x4->setup = aic32x4_setup;
4d16700d
MP		 1054 return 0;
1055}
1056
239b669b
MP		 1057static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1058{
1059 regulator_disable(aic32x4->supply_iov);
1060
1061 if (!IS_ERR(aic32x4->supply_ldo))
1062 regulator_disable(aic32x4->supply_ldo);
1063
1064 if (!IS_ERR(aic32x4->supply_dv))
1065 regulator_disable(aic32x4->supply_dv);
1066
1067 if (!IS_ERR(aic32x4->supply_av))
1068 regulator_disable(aic32x4->supply_av);
1069}
1070
1071static int aic32x4_setup_regulators(struct device *dev,
1072 struct aic32x4_priv *aic32x4)
1073{
1074 int ret = 0;
1075
1076 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1077 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1078 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1079 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1080
1081 /* Check if the regulator requirements are fulfilled */
1082
1083 if (IS_ERR(aic32x4->supply_iov)) {
1084 dev_err(dev, "Missing supply 'iov'\n");
1085 return PTR_ERR(aic32x4->supply_iov);
1086 }
1087
1088 if (IS_ERR(aic32x4->supply_ldo)) {
1089 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1090 return -EPROBE_DEFER;
1091
1092 if (IS_ERR(aic32x4->supply_dv)) {
1093 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1094 return PTR_ERR(aic32x4->supply_dv);
1095 }
1096 if (IS_ERR(aic32x4->supply_av)) {
1097 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1098 return PTR_ERR(aic32x4->supply_av);
1099 }
1100 } else {
45586c70 1101 if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
239b669b 1102 return -EPROBE_DEFER;
45586c70 1103 if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
239b669b
MP		 1104 return -EPROBE_DEFER;
1105 }
1106
1107 ret = regulator_enable(aic32x4->supply_iov);
1108 if (ret) {
1109 dev_err(dev, "Failed to enable regulator iov\n");
1110 return ret;
1111 }
1112
1113 if (!IS_ERR(aic32x4->supply_ldo)) {
1114 ret = regulator_enable(aic32x4->supply_ldo);
1115 if (ret) {
1116 dev_err(dev, "Failed to enable regulator ldo\n");
1117 goto error_ldo;
1118 }
1119 }
1120
1121 if (!IS_ERR(aic32x4->supply_dv)) {
1122 ret = regulator_enable(aic32x4->supply_dv);
1123 if (ret) {
1124 dev_err(dev, "Failed to enable regulator dv\n");
1125 goto error_dv;
1126 }
1127 }
1128
1129 if (!IS_ERR(aic32x4->supply_av)) {
1130 ret = regulator_enable(aic32x4->supply_av);
1131 if (ret) {
1132 dev_err(dev, "Failed to enable regulator av\n");
1133 goto error_av;
1134 }
1135 }
1136
1137 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1138 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1139
1140 return 0;
1141
1142error_av:
1143 if (!IS_ERR(aic32x4->supply_dv))
1144 regulator_disable(aic32x4->supply_dv);
1145
1146error_dv:
1147 if (!IS_ERR(aic32x4->supply_ldo))
1148 regulator_disable(aic32x4->supply_ldo);
1149
1150error_ldo:
1151 regulator_disable(aic32x4->supply_iov);
1152 return ret;
1153}
1154
3bcfd222 1155int aic32x4_probe(struct device *dev, struct regmap *regmap)
1d471cd1 1156{
1d471cd1 1157 struct aic32x4_priv *aic32x4;
3bcfd222
JM		 1158 struct aic32x4_pdata *pdata = dev->platform_data;
1159 struct device_node *np = dev->of_node;
1d471cd1
JM		 1160 int ret;
1161
3bcfd222
JM		 1162 if (IS_ERR(regmap))
1163 return PTR_ERR(regmap);
1164
1165 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
514b044c 1166 GFP_KERNEL);
1d471cd1
JM		 1167 if (aic32x4 == NULL)
1168 return -ENOMEM;
1169
b9045b9c 1170 aic32x4->dev = dev;
3bcfd222 1171 dev_set_drvdata(dev, aic32x4);
1d471cd1
JM		 1172
1173 if (pdata) {
1174 aic32x4->power_cfg = pdata->power_cfg;
1175 aic32x4->swapdacs = pdata->swapdacs;
1176 aic32x4->micpga_routing = pdata->micpga_routing;
1858fe97 1177 aic32x4->rstn_gpio = pdata->rstn_gpio;
514b044c 1178 aic32x4->mclk_name = "mclk";
4d16700d
MP		 1179 } else if (np) {
1180 ret = aic32x4_parse_dt(aic32x4, np);
1181 if (ret) {
3bcfd222 1182 dev_err(dev, "Failed to parse DT node\n");
4d16700d
MP		 1183 return ret;
1184 }
1d471cd1
JM		 1185 } else {
1186 aic32x4->power_cfg = 0;
1187 aic32x4->swapdacs = false;
1188 aic32x4->micpga_routing = 0;
1858fe97 1189 aic32x4->rstn_gpio = -1;
514b044c 1190 aic32x4->mclk_name = "mclk";
1d471cd1
JM		 1191 }
1192
514b044c
AM		 1193 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1194 if (ret)
1195 return ret;
1196
a74ab512 1197 if (gpio_is_valid(aic32x4->rstn_gpio)) {
3bcfd222 1198 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
752b7764
MB		 1199 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1200 if (ret != 0)
1201 return ret;
1202 }
1203
3bcfd222 1204 ret = aic32x4_setup_regulators(dev, aic32x4);
239b669b 1205 if (ret) {
3bcfd222 1206 dev_err(dev, "Failed to setup regulators\n");
239b669b
MP		 1207 return ret;
1208 }
1209
b154dc5d
KM		 1210 ret = devm_snd_soc_register_component(dev,
1211 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
239b669b 1212 if (ret) {
b154dc5d 1213 dev_err(dev, "Failed to register component\n");
239b669b
MP		 1214 aic32x4_disable_regulators(aic32x4);
1215 return ret;
1216 }
1217
239b669b 1218 return 0;
1d471cd1 1219}
3bcfd222 1220EXPORT_SYMBOL(aic32x4_probe);
1d471cd1 1221
3bcfd222 1222int aic32x4_remove(struct device *dev)
1d471cd1 1223{
3bcfd222 1224 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
239b669b
MP		 1225
1226 aic32x4_disable_regulators(aic32x4);
1227
1d471cd1
JM		 1228 return 0;
1229}
3bcfd222 1230EXPORT_SYMBOL(aic32x4_remove);
1d471cd1
JM		 1231
1232MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1233MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1234MODULE_LICENSE("GPL");
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