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ASoC: tlv320aic32x4: Add Switch for Setting Common Mode Voltage
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / tlv320aic32x4.c
CommitLineData
1d471cd1
JM		 1/*
2 * linux/sound/soc/codecs/tlv320aic32x4.c
3 *
4 * Copyright 2011 Vista Silicon S.L.
5 *
6 * Author: Javier Martin <javier.martin@vista-silicon.com>
7 *
8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
514b044c 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1d471cd1
JM		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 * MA 02110-1301, USA.
24 */
25
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
1858fe97 31#include <linux/gpio.h>
4d16700d 32#include <linux/of_gpio.h>
1d471cd1
JM		 33#include <linux/cdev.h>
34#include <linux/slab.h>
98b664e2 35#include <linux/clk.h>
514b044c 36#include <linux/of_clk.h>
239b669b 37#include <linux/regulator/consumer.h>
1d471cd1
JM		 38
39#include <sound/tlv320aic32x4.h>
40#include <sound/core.h>
41#include <sound/pcm.h>
42#include <sound/pcm_params.h>
43#include <sound/soc.h>
44#include <sound/soc-dapm.h>
45#include <sound/initval.h>
46#include <sound/tlv.h>
47
48#include "tlv320aic32x4.h"
49
1d471cd1 50struct aic32x4_priv {
4d208ca4 51 struct regmap *regmap;
1d471cd1
JM		 52 u32 power_cfg;
53 u32 micpga_routing;
54 bool swapdacs;
1858fe97 55 int rstn_gpio;
514b044c 56 const char *mclk_name;
239b669b
MP		 57
58 struct regulator *supply_ldo;
59 struct regulator *supply_iov;
60 struct regulator *supply_dv;
61 struct regulator *supply_av;
b9045b9c
DM		 62
63 struct aic32x4_setup_data *setup;
64 struct device *dev;
65};
66
04d979d7 67static int mic_bias_event(struct snd_soc_dapm_widget *w,
68 struct snd_kcontrol *kcontrol, int event)
69{
70 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
71
72 switch (event) {
73 case SND_SOC_DAPM_POST_PMU:
74 /* Change Mic Bias Registor */
75 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
76 AIC32x4_MICBIAS_MASK,
77 AIC32X4_MICBIAS_LDOIN |
78 AIC32X4_MICBIAS_2075V);
79 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
80 break;
81 case SND_SOC_DAPM_PRE_PMD:
82 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
83 AIC32x4_MICBIAS_MASK, 0);
84 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
85 __func__);
86 break;
87 }
88
89 return 0;
90}
91
92
b9045b9c
DM		 93static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
94 struct snd_ctl_elem_value *ucontrol)
95{
b154dc5d 96 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 97 u8 val;
98
b154dc5d 99 val = snd_soc_component_read32(component, AIC32X4_DINCTL);
b9045b9c
DM		 100
101 ucontrol->value.integer.value[0] = (val & 0x01);
102
103 return 0;
104};
105
106static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
107 struct snd_ctl_elem_value *ucontrol)
108{
b154dc5d 109 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 110 u8 val;
111 u8 gpio_check;
112
b154dc5d 113 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL);
b9045b9c
DM		 114 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
115 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
116 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
117 __func__);
118 return -EINVAL;
119 }
120
121 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
122 return 0;
123
124 if (ucontrol->value.integer.value[0])
125 val |= ucontrol->value.integer.value[0];
126 else
127 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
128
b154dc5d 129 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
b9045b9c
DM		 130
131 return 0;
132};
133
134static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
135 struct snd_ctl_elem_value *ucontrol)
136{
b154dc5d 137 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 138 u8 val;
139
b154dc5d 140 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL);
b9045b9c
DM		 141
142 ucontrol->value.integer.value[0] = (val & 0x01);
143
144 return 0;
145};
146
147static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
148 struct snd_ctl_elem_value *ucontrol)
149{
b154dc5d 150 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 151 u8 val;
152 u8 gpio_check;
153
b154dc5d 154 val = snd_soc_component_read32(component, AIC32X4_MISOCTL);
b9045b9c
DM		 155 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
156 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
157 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
158 __func__);
159 return -EINVAL;
160 }
161
162 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
163 return 0;
164
165 if (ucontrol->value.integer.value[0])
166 val |= ucontrol->value.integer.value[0];
167 else
168 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
169
b154dc5d 170 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
b9045b9c
DM		 171
172 return 0;
173};
174
175static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
176 struct snd_ctl_elem_value *ucontrol)
177{
b154dc5d 178 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 179 u8 val;
180
b154dc5d 181 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
b9045b9c
DM		 182 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
183
184 return 0;
185};
186
187static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
188 struct snd_ctl_elem_value *ucontrol)
189{
b154dc5d 190 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 191 u8 val;
192 u8 gpio_check;
193
b154dc5d 194 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
b9045b9c
DM		 195 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
196 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
197 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
198 __func__);
199 return -EINVAL;
200 }
201
202 if (ucontrol->value.integer.value[0] == (val & 0x1))
203 return 0;
204
205 if (ucontrol->value.integer.value[0])
206 val |= ucontrol->value.integer.value[0];
207 else
208 val &= 0xfe;
209
b154dc5d 210 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
b9045b9c
DM		 211
212 return 0;
213};
214
215static const struct snd_kcontrol_new aic32x4_mfp1[] = {
216 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
217};
218
219static const struct snd_kcontrol_new aic32x4_mfp2[] = {
220 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
221};
222
223static const struct snd_kcontrol_new aic32x4_mfp3[] = {
224 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
225};
226
227static const struct snd_kcontrol_new aic32x4_mfp4[] = {
228 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
229};
230
231static const struct snd_kcontrol_new aic32x4_mfp5[] = {
232 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
233 aic32x4_set_mfp5_gpio),
1d471cd1
JM		 234};
235
1d471cd1
JM		 236/* 0dB min, 0.5dB steps */
237static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
c671e79d
MP		 238/* -63.5dB min, 0.5dB steps */
239static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
240/* -6dB min, 1dB steps */
241static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
242/* -12dB min, 0.5dB steps */
243static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
1d471cd1 244
44ceee84
AM		 245static const char * const lo_cm_text[] = {
246 "Full Chip", "1.65V",
247};
248
249static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
250
1d471cd1 251static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
c671e79d
MP		 252 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
253 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
254 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
255 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
256 tlv_driver_gain),
257 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
258 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
259 tlv_driver_gain),
1d471cd1
JM		 260 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
261 AIC32X4_HPRGAIN, 6, 0x01, 1),
262 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
263 AIC32X4_LORGAIN, 6, 0x01, 1),
44ceee84 264 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
1d471cd1
JM		 265 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
266 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
267
268 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
269 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
270
c671e79d
MP		 271 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
272 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
1d471cd1
JM		 273 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
274 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
275
276 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
277
278 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
279 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
280 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
281 4, 0x07, 0),
282 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
283 0, 0x03, 0),
284 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
285 6, 0x03, 0),
286 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
287 1, 0x1F, 0),
288 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
289 0, 0x7F, 0),
290 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
291 3, 0x1F, 0),
292 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
293 3, 0x1F, 0),
294 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
295 0, 0x1F, 0),
296 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
297 0, 0x0F, 0),
298};
299
1d471cd1
JM		 300static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
301 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
302 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
303};
304
305static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
306 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
307 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
308};
309
310static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
311 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
312};
313
314static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
315 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
316};
317
20d2cecb
JM		 318static const char * const resistor_text[] = {
319 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
320};
321
2213fc35
JM		 322/* Left mixer pins */
323static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
324static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
325static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
326static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
327
328static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
329static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
330static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
331
332static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
333 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
334};
335static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
336 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
337};
338static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
339 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
340};
341static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
342 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
343};
344static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
345 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
346};
347static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
348 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
349};
350static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
351 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
1d471cd1
JM		 352};
353
514b044c 354/* Right mixer pins */
2213fc35
JM		 355static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
356static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
357static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
358static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
359static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
360static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
361static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
362
363static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
364 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
365};
366static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
367 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
368};
369static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
370 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
371};
372static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
373 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
374};
375static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
376 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
377};
378static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
379 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
380};
381static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
382 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
1d471cd1
JM		 383};
384
385static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
386 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
387 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
388 &hpl_output_mixer_controls[0],
389 ARRAY_SIZE(hpl_output_mixer_controls)),
390 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
391
392 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
393 &lol_output_mixer_controls[0],
394 ARRAY_SIZE(lol_output_mixer_controls)),
395 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
396
397 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
398 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
399 &hpr_output_mixer_controls[0],
400 ARRAY_SIZE(hpr_output_mixer_controls)),
401 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
402 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
403 &lor_output_mixer_controls[0],
404 ARRAY_SIZE(lor_output_mixer_controls)),
405 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
2213fc35 406
1d471cd1 407 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
2213fc35
JM		 408 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
409 in1r_to_rmixer_controls),
410 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
411 in2r_to_rmixer_controls),
412 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
413 in3r_to_rmixer_controls),
414 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
415 in2l_to_rmixer_controls),
416 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
417 cmr_to_rmixer_controls),
418 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
419 in1l_to_rmixer_controls),
420 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
421 in3l_to_rmixer_controls),
422
423 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
424 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
425 in1l_to_lmixer_controls),
426 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
427 in2l_to_lmixer_controls),
428 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
429 in3l_to_lmixer_controls),
430 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
431 in1r_to_lmixer_controls),
432 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
433 cml_to_lmixer_controls),
434 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
435 in2r_to_lmixer_controls),
436 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
437 in3r_to_lmixer_controls),
438
04d979d7 439 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
440 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
441
1d471cd1
JM		 442
443 SND_SOC_DAPM_OUTPUT("HPL"),
444 SND_SOC_DAPM_OUTPUT("HPR"),
445 SND_SOC_DAPM_OUTPUT("LOL"),
446 SND_SOC_DAPM_OUTPUT("LOR"),
447 SND_SOC_DAPM_INPUT("IN1_L"),
448 SND_SOC_DAPM_INPUT("IN1_R"),
449 SND_SOC_DAPM_INPUT("IN2_L"),
450 SND_SOC_DAPM_INPUT("IN2_R"),
451 SND_SOC_DAPM_INPUT("IN3_L"),
452 SND_SOC_DAPM_INPUT("IN3_R"),
c63adb28
AM		 453 SND_SOC_DAPM_INPUT("CM_L"),
454 SND_SOC_DAPM_INPUT("CM_R"),
1d471cd1
JM		 455};
456
457static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
458 /* Left Output */
459 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
460 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
461
462 {"HPL Power", NULL, "HPL Output Mixer"},
463 {"HPL", NULL, "HPL Power"},
464
465 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
466
467 {"LOL Power", NULL, "LOL Output Mixer"},
468 {"LOL", NULL, "LOL Power"},
469
470 /* Right Output */
471 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
472 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
473
474 {"HPR Power", NULL, "HPR Output Mixer"},
475 {"HPR", NULL, "HPR Power"},
476
477 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
478
479 {"LOR Power", NULL, "LOR Output Mixer"},
480 {"LOR", NULL, "LOR Power"},
481
1d471cd1 482 /* Right Input */
2213fc35
JM		 483 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
484 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
485 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
486 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
487
488 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
489 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
490 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
491 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
492
493 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
494 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
495 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
496 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
497
498 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
499 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
500 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
501 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
502
503 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
504 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
505 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
506 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
507
508 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
509 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
510 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
511 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
512
513 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
514 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
515 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
516 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
517
518 /* Left Input */
519 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
520 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
521 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
522 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
523
524 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
525 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
526 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
527 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
528
529 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
530 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
531 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
532 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
533
534 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
535 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
536 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
537 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
538
539 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
540 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
541 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
542 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
543
544 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
545 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
546 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
547 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
548
549 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
550 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
551 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
552 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
1d471cd1
JM		 553};
554
4d208ca4
MB		 555static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
556 {
557 .selector_reg = 0,
514b044c 558 .selector_mask = 0xff,
4d208ca4
MB		 559 .window_start = 0,
560 .window_len = 128,
e8e08c52 561 .range_min = 0,
6d0d5103 562 .range_max = AIC32X4_RMICPGAVOL,
4d208ca4
MB		 563 },
564};
1d471cd1 565
3bcfd222 566const struct regmap_config aic32x4_regmap_config = {
4d208ca4
MB		 567 .max_register = AIC32X4_RMICPGAVOL,
568 .ranges = aic32x4_regmap_pages,
569 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
570};
3bcfd222 571EXPORT_SYMBOL(aic32x4_regmap_config);
1d471cd1 572
1d471cd1
JM		 573static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
574 int clk_id, unsigned int freq, int dir)
575{
b154dc5d 576 struct snd_soc_component *component = codec_dai->component;
aa6a60f7
AM		 577 struct clk *mclk;
578 struct clk *pll;
1d471cd1 579
aa6a60f7
AM		 580 pll = devm_clk_get(component->dev, "pll");
581 mclk = clk_get_parent(pll);
582
583 return clk_set_rate(mclk, freq);
1d471cd1
JM		 584}
585
586static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
587{
b154dc5d 588 struct snd_soc_component *component = codec_dai->component;
60fb4be5
AD		 589 u8 iface_reg_1 = 0;
590 u8 iface_reg_2 = 0;
591 u8 iface_reg_3 = 0;
1d471cd1
JM		 592
593 /* set master/slave audio interface */
594 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
595 case SND_SOC_DAIFMT_CBM_CFM:
1d471cd1
JM		 596 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
597 break;
598 case SND_SOC_DAIFMT_CBS_CFS:
1d471cd1
JM		 599 break;
600 default:
601 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
602 return -EINVAL;
603 }
604
605 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
606 case SND_SOC_DAIFMT_I2S:
607 break;
608 case SND_SOC_DAIFMT_DSP_A:
4483521d
AD		 609 iface_reg_1 |= (AIC32X4_DSP_MODE <<
610 AIC32X4_IFACE1_DATATYPE_SHIFT);
60fb4be5 611 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
1d471cd1
JM		 612 iface_reg_2 = 0x01; /* add offset 1 */
613 break;
614 case SND_SOC_DAIFMT_DSP_B:
4483521d
AD		 615 iface_reg_1 |= (AIC32X4_DSP_MODE <<
616 AIC32X4_IFACE1_DATATYPE_SHIFT);
60fb4be5 617 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
1d471cd1
JM		 618 break;
619 case SND_SOC_DAIFMT_RIGHT_J:
4483521d
AD		 620 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
621 AIC32X4_IFACE1_DATATYPE_SHIFT);
1d471cd1
JM		 622 break;
623 case SND_SOC_DAIFMT_LEFT_J:
4483521d
AD		 624 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
625 AIC32X4_IFACE1_DATATYPE_SHIFT);
1d471cd1
JM		 626 break;
627 default:
628 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
629 return -EINVAL;
630 }
631
b154dc5d 632 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
514b044c
AM		 633 AIC32X4_IFACE1_DATATYPE_MASK |
634 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
b154dc5d 635 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
514b044c 636 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
b154dc5d 637 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
514b044c 638 AIC32X4_BCLKINV_MASK, iface_reg_3);
60fb4be5 639
1d471cd1
JM		 640 return 0;
641}
642
fbafbf65
AM		 643static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
644{
645 return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
646}
647
648static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
649{
650 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
651 snd_soc_component_write(component, AIC32X4_DOSRLSB,
652 (dosr & 0xff));
653
654 return 0;
655}
656
c95e3a4b
AM		 657static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
658 u8 r_block, u8 p_block)
659{
660 if (r_block > 18 || p_block > 25)
661 return -EINVAL;
662
663 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
664 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
665
666 return 0;
667}
668
bf31cbfb 669static int aic32x4_setup_clocks(struct snd_soc_component *component,
96c3bb00 670 unsigned int sample_rate)
1d471cd1 671{
96c3bb00
AM		 672 u8 aosr;
673 u16 dosr;
674 u8 adc_resource_class, dac_resource_class;
675 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
676 u8 dosr_increment;
677 u16 max_dosr, min_dosr;
678 unsigned long mclk_rate, adc_clock_rate, dac_clock_rate;
514b044c 679 int ret;
96c3bb00 680 struct clk *mclk;
514b044c
AM		 681
682 struct clk_bulk_data clocks[] = {
683 { .id = "pll" },
a51b5006
AM		 684 { .id = "nadc" },
685 { .id = "madc" },
686 { .id = "ndac" },
687 { .id = "mdac" },
9b484124 688 { .id = "bdiv" },
514b044c 689 };
514b044c
AM		 690 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
691 if (ret)
692 return ret;
693
96c3bb00
AM		 694 mclk = clk_get_parent(clocks[1].clk);
695 mclk_rate = clk_get_rate(mclk);
696
697 if (sample_rate <= 48000) {
698 aosr = 128;
699 adc_resource_class = 6;
700 dac_resource_class = 8;
701 dosr_increment = 8;
702 aic32x4_set_processing_blocks(component, 1, 1);
703 } else if (sample_rate <= 96000) {
704 aosr = 64;
705 adc_resource_class = 6;
706 dac_resource_class = 8;
707 dosr_increment = 4;
708 aic32x4_set_processing_blocks(component, 1, 9);
709 } else if (sample_rate == 192000) {
710 aosr = 32;
711 adc_resource_class = 3;
712 dac_resource_class = 4;
713 dosr_increment = 2;
714 aic32x4_set_processing_blocks(component, 13, 19);
715 } else {
716 dev_err(component->dev, "Sampling rate not supported\n");
717 return -EINVAL;
718 }
c95e3a4b 719
96c3bb00
AM		 720 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
721 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
722 dosr_increment;
723 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
724 dosr_increment;
725 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
726
727 for (nadc = max_nadc; nadc > 0; --nadc) {
728 adc_clock_rate = nadc * madc * aosr * sample_rate;
729 for (dosr = max_dosr; dosr >= min_dosr;
730 dosr -= dosr_increment) {
731 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
732 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
733 (min_mdac * dosr * sample_rate);
734 for (mdac = min_mdac; mdac <= 128; ++mdac) {
735 for (ndac = max_ndac; ndac > 0; --ndac) {
736 dac_clock_rate = ndac * mdac * dosr *
737 sample_rate;
738 if (dac_clock_rate == adc_clock_rate) {
739 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
740 continue;
741
742 clk_set_rate(clocks[0].clk,
743 dac_clock_rate);
744
745 clk_set_rate(clocks[1].clk,
746 sample_rate * aosr *
747 madc);
748 clk_set_rate(clocks[2].clk,
749 sample_rate * aosr);
750 aic32x4_set_aosr(component,
751 aosr);
752
753 clk_set_rate(clocks[3].clk,
754 sample_rate * dosr *
755 mdac);
756 clk_set_rate(clocks[4].clk,
757 sample_rate * dosr);
758 aic32x4_set_dosr(component,
759 dosr);
760
761 clk_set_rate(clocks[5].clk,
762 sample_rate * 32);
763 return 0;
764 }
765 }
766 }
767 }
768 }
1d471cd1 769
96c3bb00
AM		 770 dev_err(component->dev,
771 "Could not set clocks to support sample rate.\n");
772 return -EINVAL;
bf31cbfb
AM		 773}
774
775static int aic32x4_hw_params(struct snd_pcm_substream *substream,
a51b5006
AM		 776 struct snd_pcm_hw_params *params,
777 struct snd_soc_dai *dai)
bf31cbfb
AM		 778{
779 struct snd_soc_component *component = dai->component;
780 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
781 u8 iface1_reg = 0;
782 u8 dacsetup_reg = 0;
783
96c3bb00 784 aic32x4_setup_clocks(component, params_rate(params));
bf31cbfb 785
bd8a5711
MB		 786 switch (params_width(params)) {
787 case 16:
64aab899 788 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
514b044c 789 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1 790 break;
bd8a5711 791 case 20:
64aab899 792 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
514b044c 793 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1 794 break;
bd8a5711 795 case 24:
64aab899 796 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
514b044c 797 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1 798 break;
bd8a5711 799 case 32:
64aab899 800 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
514b044c 801 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1
JM		 802 break;
803 }
b154dc5d 804 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
514b044c 805 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
1d471cd1 806
b44aa40f 807 if (params_channels(params) == 1) {
64aab899 808 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
b44aa40f
MP		 809 } else {
810 if (aic32x4->swapdacs)
64aab899 811 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
b44aa40f 812 else
64aab899 813 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
b44aa40f 814 }
b154dc5d 815 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
514b044c 816 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
b44aa40f 817
1d471cd1
JM		 818 return 0;
819}
820
821static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
822{
b154dc5d 823 struct snd_soc_component *component = dai->component;
1d471cd1 824
b154dc5d 825 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
514b044c 826 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
b7ddd9ca 827
1d471cd1
JM		 828 return 0;
829}
830
b154dc5d 831static int aic32x4_set_bias_level(struct snd_soc_component *component,
1d471cd1
JM		 832 enum snd_soc_bias_level level)
833{
98b664e2
MP		 834 int ret;
835
d25970b5
AM		 836 struct clk_bulk_data clocks[] = {
837 { .id = "madc" },
838 { .id = "mdac" },
839 { .id = "bdiv" },
840 };
841
842 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
843 if (ret)
844 return ret;
845
1d471cd1
JM		 846 switch (level) {
847 case SND_SOC_BIAS_ON:
d25970b5 848 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
98b664e2 849 if (ret) {
d25970b5 850 dev_err(component->dev, "Failed to enable clocks\n");
98b664e2
MP		 851 return ret;
852 }
1d471cd1
JM		 853 break;
854 case SND_SOC_BIAS_PREPARE:
855 break;
856 case SND_SOC_BIAS_STANDBY:
667e9334 857 /* Initial cold start */
858 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
859 break;
860
d25970b5 861 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
1d471cd1
JM		 862 break;
863 case SND_SOC_BIAS_OFF:
864 break;
865 }
1d471cd1
JM		 866 return 0;
867}
868
6d56ee15 869#define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000
514b044c 870#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1d471cd1
JM		 871 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
872
85e7652d 873static const struct snd_soc_dai_ops aic32x4_ops = {
1d471cd1
JM		 874 .hw_params = aic32x4_hw_params,
875 .digital_mute = aic32x4_mute,
876 .set_fmt = aic32x4_set_dai_fmt,
877 .set_sysclk = aic32x4_set_dai_sysclk,
878};
879
880static struct snd_soc_dai_driver aic32x4_dai = {
881 .name = "tlv320aic32x4-hifi",
882 .playback = {
514b044c
AM		 883 .stream_name = "Playback",
884 .channels_min = 1,
885 .channels_max = 2,
886 .rates = AIC32X4_RATES,
887 .formats = AIC32X4_FORMATS,},
1d471cd1 888 .capture = {
514b044c
AM		 889 .stream_name = "Capture",
890 .channels_min = 1,
891 .channels_max = 2,
892 .rates = AIC32X4_RATES,
893 .formats = AIC32X4_FORMATS,},
1d471cd1
JM		 894 .ops = &aic32x4_ops,
895 .symmetric_rates = 1,
896};
897
b154dc5d 898static void aic32x4_setup_gpios(struct snd_soc_component *component)
b9045b9c 899{
b154dc5d 900 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
b9045b9c
DM		 901
902 /* setup GPIO functions */
903 /* MFP1 */
904 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 905 snd_soc_component_write(component, AIC32X4_DINCTL,
514b044c 906 aic32x4->setup->gpio_func[0]);
b154dc5d 907 snd_soc_add_component_controls(component, aic32x4_mfp1,
b9045b9c
DM		 908 ARRAY_SIZE(aic32x4_mfp1));
909 }
910
911 /* MFP2 */
912 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 913 snd_soc_component_write(component, AIC32X4_DOUTCTL,
514b044c 914 aic32x4->setup->gpio_func[1]);
b154dc5d 915 snd_soc_add_component_controls(component, aic32x4_mfp2,
b9045b9c
DM		 916 ARRAY_SIZE(aic32x4_mfp2));
917 }
918
919 /* MFP3 */
920 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 921 snd_soc_component_write(component, AIC32X4_SCLKCTL,
514b044c 922 aic32x4->setup->gpio_func[2]);
b154dc5d 923 snd_soc_add_component_controls(component, aic32x4_mfp3,
b9045b9c
DM		 924 ARRAY_SIZE(aic32x4_mfp3));
925 }
926
927 /* MFP4 */
928 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 929 snd_soc_component_write(component, AIC32X4_MISOCTL,
514b044c 930 aic32x4->setup->gpio_func[3]);
b154dc5d 931 snd_soc_add_component_controls(component, aic32x4_mfp4,
b9045b9c
DM		 932 ARRAY_SIZE(aic32x4_mfp4));
933 }
934
935 /* MFP5 */
936 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 937 snd_soc_component_write(component, AIC32X4_GPIOCTL,
514b044c 938 aic32x4->setup->gpio_func[4]);
b154dc5d 939 snd_soc_add_component_controls(component, aic32x4_mfp5,
b9045b9c
DM		 940 ARRAY_SIZE(aic32x4_mfp5));
941 }
942}
943
b154dc5d 944static int aic32x4_component_probe(struct snd_soc_component *component)
1d471cd1 945{
b154dc5d 946 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1d471cd1 947 u32 tmp_reg;
fd2df3ae
AM		 948 int ret;
949
950 struct clk_bulk_data clocks[] = {
a51b5006
AM		 951 { .id = "codec_clkin" },
952 { .id = "pll" },
9b484124
AM		 953 { .id = "bdiv" },
954 { .id = "mdac" },
fd2df3ae
AM		 955 };
956
957 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
958 if (ret)
959 return ret;
1d471cd1 960
a74ab512 961 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1858fe97
JM		 962 ndelay(10);
963 gpio_set_value(aic32x4->rstn_gpio, 1);
674f9abd 964 mdelay(1);
1858fe97
JM		 965 }
966
b154dc5d 967 snd_soc_component_write(component, AIC32X4_RESET, 0x01);
1d471cd1 968
b9045b9c 969 if (aic32x4->setup)
b154dc5d 970 aic32x4_setup_gpios(component);
b9045b9c 971
fd2df3ae 972 clk_set_parent(clocks[0].clk, clocks[1].clk);
9b484124 973 clk_set_parent(clocks[2].clk, clocks[3].clk);
fd2df3ae 974
1d471cd1
JM		 975 /* Power platform configuration */
976 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
514b044c
AM		 977 snd_soc_component_write(component, AIC32X4_MICBIAS,
978 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1d471cd1 979 }
eb72cbdf 980 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
b154dc5d 981 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
0c93a167
WS		 982
983 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
984 AIC32X4_LDOCTLEN : 0;
b154dc5d 985 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
0c93a167 986
b154dc5d 987 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE);
eb72cbdf 988 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1d471cd1 989 tmp_reg |= AIC32X4_LDOIN_18_36;
eb72cbdf 990 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1d471cd1 991 tmp_reg |= AIC32X4_LDOIN2HP;
b154dc5d 992 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1d471cd1 993
1d471cd1 994 /* Mic PGA routing */
609e6025 995 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
b154dc5d 996 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
43bf38ba 997 AIC32X4_LMICPGANIN_IN2R_10K);
609e6025 998 else
b154dc5d 999 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
43bf38ba 1000 AIC32X4_LMICPGANIN_CM1L_10K);
609e6025 1001 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
b154dc5d 1002 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
43bf38ba 1003 AIC32X4_RMICPGANIN_IN1L_10K);
609e6025 1004 else
b154dc5d 1005 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
43bf38ba 1006 AIC32X4_RMICPGANIN_CM1R_10K);
1d471cd1 1007
a405387c
JM		 1008 /*
1009 * Workaround: for an unknown reason, the ADC needs to be powered up
1010 * and down for the first capture to work properly. It seems related to
1011 * a HW BUG or some kind of behavior not documented in the datasheet.
1012 */
b154dc5d
KM		 1013 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);
1014 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
a405387c 1015 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
b154dc5d 1016 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
a405387c 1017
1d471cd1
JM		 1018 return 0;
1019}
1020
b154dc5d
KM		 1021static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1022 .probe = aic32x4_component_probe,
1023 .set_bias_level = aic32x4_set_bias_level,
1024 .controls = aic32x4_snd_controls,
1025 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1026 .dapm_widgets = aic32x4_dapm_widgets,
1027 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1028 .dapm_routes = aic32x4_dapm_routes,
1029 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1030 .suspend_bias_off = 1,
1031 .idle_bias_on = 1,
1032 .use_pmdown_time = 1,
1033 .endianness = 1,
1034 .non_legacy_dai_naming = 1,
1d471cd1
JM		 1035};
1036
4d16700d
MP		 1037static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1038 struct device_node *np)
1039{
b9045b9c 1040 struct aic32x4_setup_data *aic32x4_setup;
514b044c 1041 int ret;
b9045b9c
DM		 1042
1043 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1044 GFP_KERNEL);
1045 if (!aic32x4_setup)
1046 return -ENOMEM;
1047
514b044c
AM		 1048 ret = of_property_match_string(np, "clock-names", "mclk");
1049 if (ret < 0)
1050 return -EINVAL;
1051 aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1052
4d16700d
MP		 1053 aic32x4->swapdacs = false;
1054 aic32x4->micpga_routing = 0;
1055 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1056
b9045b9c
DM		 1057 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1058 aic32x4_setup->gpio_func, 5) >= 0)
1059 aic32x4->setup = aic32x4_setup;
4d16700d
MP		 1060 return 0;
1061}
1062
239b669b
MP		 1063static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1064{
1065 regulator_disable(aic32x4->supply_iov);
1066
1067 if (!IS_ERR(aic32x4->supply_ldo))
1068 regulator_disable(aic32x4->supply_ldo);
1069
1070 if (!IS_ERR(aic32x4->supply_dv))
1071 regulator_disable(aic32x4->supply_dv);
1072
1073 if (!IS_ERR(aic32x4->supply_av))
1074 regulator_disable(aic32x4->supply_av);
1075}
1076
1077static int aic32x4_setup_regulators(struct device *dev,
1078 struct aic32x4_priv *aic32x4)
1079{
1080 int ret = 0;
1081
1082 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1083 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1084 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1085 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1086
1087 /* Check if the regulator requirements are fulfilled */
1088
1089 if (IS_ERR(aic32x4->supply_iov)) {
1090 dev_err(dev, "Missing supply 'iov'\n");
1091 return PTR_ERR(aic32x4->supply_iov);
1092 }
1093
1094 if (IS_ERR(aic32x4->supply_ldo)) {
1095 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1096 return -EPROBE_DEFER;
1097
1098 if (IS_ERR(aic32x4->supply_dv)) {
1099 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1100 return PTR_ERR(aic32x4->supply_dv);
1101 }
1102 if (IS_ERR(aic32x4->supply_av)) {
1103 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1104 return PTR_ERR(aic32x4->supply_av);
1105 }
1106 } else {
1107 if (IS_ERR(aic32x4->supply_dv) &&
1108 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1109 return -EPROBE_DEFER;
1110 if (IS_ERR(aic32x4->supply_av) &&
1111 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1112 return -EPROBE_DEFER;
1113 }
1114
1115 ret = regulator_enable(aic32x4->supply_iov);
1116 if (ret) {
1117 dev_err(dev, "Failed to enable regulator iov\n");
1118 return ret;
1119 }
1120
1121 if (!IS_ERR(aic32x4->supply_ldo)) {
1122 ret = regulator_enable(aic32x4->supply_ldo);
1123 if (ret) {
1124 dev_err(dev, "Failed to enable regulator ldo\n");
1125 goto error_ldo;
1126 }
1127 }
1128
1129 if (!IS_ERR(aic32x4->supply_dv)) {
1130 ret = regulator_enable(aic32x4->supply_dv);
1131 if (ret) {
1132 dev_err(dev, "Failed to enable regulator dv\n");
1133 goto error_dv;
1134 }
1135 }
1136
1137 if (!IS_ERR(aic32x4->supply_av)) {
1138 ret = regulator_enable(aic32x4->supply_av);
1139 if (ret) {
1140 dev_err(dev, "Failed to enable regulator av\n");
1141 goto error_av;
1142 }
1143 }
1144
1145 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1146 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1147
1148 return 0;
1149
1150error_av:
1151 if (!IS_ERR(aic32x4->supply_dv))
1152 regulator_disable(aic32x4->supply_dv);
1153
1154error_dv:
1155 if (!IS_ERR(aic32x4->supply_ldo))
1156 regulator_disable(aic32x4->supply_ldo);
1157
1158error_ldo:
1159 regulator_disable(aic32x4->supply_iov);
1160 return ret;
1161}
1162
3bcfd222 1163int aic32x4_probe(struct device *dev, struct regmap *regmap)
1d471cd1 1164{
1d471cd1 1165 struct aic32x4_priv *aic32x4;
3bcfd222
JM		 1166 struct aic32x4_pdata *pdata = dev->platform_data;
1167 struct device_node *np = dev->of_node;
1d471cd1
JM		 1168 int ret;
1169
3bcfd222
JM		 1170 if (IS_ERR(regmap))
1171 return PTR_ERR(regmap);
1172
1173 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
514b044c 1174 GFP_KERNEL);
1d471cd1
JM		 1175 if (aic32x4 == NULL)
1176 return -ENOMEM;
1177
b9045b9c 1178 aic32x4->dev = dev;
3bcfd222 1179 dev_set_drvdata(dev, aic32x4);
1d471cd1
JM		 1180
1181 if (pdata) {
1182 aic32x4->power_cfg = pdata->power_cfg;
1183 aic32x4->swapdacs = pdata->swapdacs;
1184 aic32x4->micpga_routing = pdata->micpga_routing;
1858fe97 1185 aic32x4->rstn_gpio = pdata->rstn_gpio;
514b044c 1186 aic32x4->mclk_name = "mclk";
4d16700d
MP		 1187 } else if (np) {
1188 ret = aic32x4_parse_dt(aic32x4, np);
1189 if (ret) {
3bcfd222 1190 dev_err(dev, "Failed to parse DT node\n");
4d16700d
MP		 1191 return ret;
1192 }
1d471cd1
JM		 1193 } else {
1194 aic32x4->power_cfg = 0;
1195 aic32x4->swapdacs = false;
1196 aic32x4->micpga_routing = 0;
1858fe97 1197 aic32x4->rstn_gpio = -1;
514b044c 1198 aic32x4->mclk_name = "mclk";
1d471cd1
JM		 1199 }
1200
514b044c
AM		 1201 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1202 if (ret)
1203 return ret;
1204
a74ab512 1205 if (gpio_is_valid(aic32x4->rstn_gpio)) {
3bcfd222 1206 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
752b7764
MB		 1207 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1208 if (ret != 0)
1209 return ret;
1210 }
1211
3bcfd222 1212 ret = aic32x4_setup_regulators(dev, aic32x4);
239b669b 1213 if (ret) {
3bcfd222 1214 dev_err(dev, "Failed to setup regulators\n");
239b669b
MP		 1215 return ret;
1216 }
1217
b154dc5d
KM		 1218 ret = devm_snd_soc_register_component(dev,
1219 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
239b669b 1220 if (ret) {
b154dc5d 1221 dev_err(dev, "Failed to register component\n");
239b669b
MP		 1222 aic32x4_disable_regulators(aic32x4);
1223 return ret;
1224 }
1225
239b669b 1226 return 0;
1d471cd1 1227}
3bcfd222 1228EXPORT_SYMBOL(aic32x4_probe);
1d471cd1 1229
3bcfd222 1230int aic32x4_remove(struct device *dev)
1d471cd1 1231{
3bcfd222 1232 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
239b669b
MP		 1233
1234 aic32x4_disable_regulators(aic32x4);
1235
1d471cd1
JM		 1236 return 0;
1237}
3bcfd222 1238EXPORT_SYMBOL(aic32x4_remove);
1d471cd1
JM		 1239
1240MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1241MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1242MODULE_LICENSE("GPL");
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