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ASoC: tlv320aic32x4: Model PLL in CCF
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / tlv320aic32x4.c
CommitLineData
1d471cd1
JM		 1/*
2 * linux/sound/soc/codecs/tlv320aic32x4.c
3 *
4 * Copyright 2011 Vista Silicon S.L.
5 *
6 * Author: Javier Martin <javier.martin@vista-silicon.com>
7 *
8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
514b044c 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1d471cd1
JM		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 * MA 02110-1301, USA.
24 */
25
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
1858fe97 31#include <linux/gpio.h>
4d16700d 32#include <linux/of_gpio.h>
1d471cd1
JM		 33#include <linux/cdev.h>
34#include <linux/slab.h>
98b664e2 35#include <linux/clk.h>
514b044c 36#include <linux/of_clk.h>
239b669b 37#include <linux/regulator/consumer.h>
1d471cd1
JM		 38
39#include <sound/tlv320aic32x4.h>
40#include <sound/core.h>
41#include <sound/pcm.h>
42#include <sound/pcm_params.h>
43#include <sound/soc.h>
44#include <sound/soc-dapm.h>
45#include <sound/initval.h>
46#include <sound/tlv.h>
47
48#include "tlv320aic32x4.h"
49
50struct aic32x4_rate_divs {
51 u32 mclk;
52 u32 rate;
514b044c 53 unsigned long pll_rate;
1d471cd1
JM		 54 u16 dosr;
55 u8 ndac;
56 u8 mdac;
57 u8 aosr;
58 u8 nadc;
59 u8 madc;
60 u8 blck_N;
c95e3a4b
AM		 61 u8 r_block;
62 u8 p_block;
1d471cd1
JM		 63};
64
65struct aic32x4_priv {
4d208ca4 66 struct regmap *regmap;
1d471cd1 67 u32 sysclk;
1d471cd1
JM		 68 u32 power_cfg;
69 u32 micpga_routing;
70 bool swapdacs;
1858fe97 71 int rstn_gpio;
98b664e2 72 struct clk *mclk;
514b044c 73 const char *mclk_name;
239b669b
MP		 74
75 struct regulator *supply_ldo;
76 struct regulator *supply_iov;
77 struct regulator *supply_dv;
78 struct regulator *supply_av;
b9045b9c
DM		 79
80 struct aic32x4_setup_data *setup;
81 struct device *dev;
82};
83
04d979d7 84static int mic_bias_event(struct snd_soc_dapm_widget *w,
85 struct snd_kcontrol *kcontrol, int event)
86{
87 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
88
89 switch (event) {
90 case SND_SOC_DAPM_POST_PMU:
91 /* Change Mic Bias Registor */
92 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
93 AIC32x4_MICBIAS_MASK,
94 AIC32X4_MICBIAS_LDOIN |
95 AIC32X4_MICBIAS_2075V);
96 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
97 break;
98 case SND_SOC_DAPM_PRE_PMD:
99 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
100 AIC32x4_MICBIAS_MASK, 0);
101 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
102 __func__);
103 break;
104 }
105
106 return 0;
107}
108
109
b9045b9c
DM		 110static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
111 struct snd_ctl_elem_value *ucontrol)
112{
b154dc5d 113 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 114 u8 val;
115
b154dc5d 116 val = snd_soc_component_read32(component, AIC32X4_DINCTL);
b9045b9c
DM		 117
118 ucontrol->value.integer.value[0] = (val & 0x01);
119
120 return 0;
121};
122
123static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
124 struct snd_ctl_elem_value *ucontrol)
125{
b154dc5d 126 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 127 u8 val;
128 u8 gpio_check;
129
b154dc5d 130 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL);
b9045b9c
DM		 131 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
132 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
133 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
134 __func__);
135 return -EINVAL;
136 }
137
138 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
139 return 0;
140
141 if (ucontrol->value.integer.value[0])
142 val |= ucontrol->value.integer.value[0];
143 else
144 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
145
b154dc5d 146 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
b9045b9c
DM		 147
148 return 0;
149};
150
151static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
152 struct snd_ctl_elem_value *ucontrol)
153{
b154dc5d 154 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 155 u8 val;
156
b154dc5d 157 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL);
b9045b9c
DM		 158
159 ucontrol->value.integer.value[0] = (val & 0x01);
160
161 return 0;
162};
163
164static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
165 struct snd_ctl_elem_value *ucontrol)
166{
b154dc5d 167 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 168 u8 val;
169 u8 gpio_check;
170
b154dc5d 171 val = snd_soc_component_read32(component, AIC32X4_MISOCTL);
b9045b9c
DM		 172 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
173 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
174 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
175 __func__);
176 return -EINVAL;
177 }
178
179 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
180 return 0;
181
182 if (ucontrol->value.integer.value[0])
183 val |= ucontrol->value.integer.value[0];
184 else
185 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
186
b154dc5d 187 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
b9045b9c
DM		 188
189 return 0;
190};
191
192static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
193 struct snd_ctl_elem_value *ucontrol)
194{
b154dc5d 195 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 196 u8 val;
197
b154dc5d 198 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
b9045b9c
DM		 199 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
200
201 return 0;
202};
203
204static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
205 struct snd_ctl_elem_value *ucontrol)
206{
b154dc5d 207 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
b9045b9c
DM		 208 u8 val;
209 u8 gpio_check;
210
b154dc5d 211 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
b9045b9c
DM		 212 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
213 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
214 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
215 __func__);
216 return -EINVAL;
217 }
218
219 if (ucontrol->value.integer.value[0] == (val & 0x1))
220 return 0;
221
222 if (ucontrol->value.integer.value[0])
223 val |= ucontrol->value.integer.value[0];
224 else
225 val &= 0xfe;
226
b154dc5d 227 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
b9045b9c
DM		 228
229 return 0;
230};
231
232static const struct snd_kcontrol_new aic32x4_mfp1[] = {
233 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
234};
235
236static const struct snd_kcontrol_new aic32x4_mfp2[] = {
237 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
238};
239
240static const struct snd_kcontrol_new aic32x4_mfp3[] = {
241 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
242};
243
244static const struct snd_kcontrol_new aic32x4_mfp4[] = {
245 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
246};
247
248static const struct snd_kcontrol_new aic32x4_mfp5[] = {
249 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
250 aic32x4_set_mfp5_gpio),
1d471cd1
JM		 251};
252
1d471cd1
JM		 253/* 0dB min, 0.5dB steps */
254static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
c671e79d
MP		 255/* -63.5dB min, 0.5dB steps */
256static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
257/* -6dB min, 1dB steps */
258static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
259/* -12dB min, 0.5dB steps */
260static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
1d471cd1
JM		 261
262static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
c671e79d
MP		 263 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
264 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
265 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
266 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
267 tlv_driver_gain),
268 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
269 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
270 tlv_driver_gain),
1d471cd1
JM		 271 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
272 AIC32X4_HPRGAIN, 6, 0x01, 1),
273 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
274 AIC32X4_LORGAIN, 6, 0x01, 1),
275 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
276 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
277
278 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
279 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
280
c671e79d
MP		 281 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
282 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
1d471cd1
JM		 283 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
284 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
285
286 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
287
288 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
289 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
290 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
291 4, 0x07, 0),
292 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
293 0, 0x03, 0),
294 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
295 6, 0x03, 0),
296 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
297 1, 0x1F, 0),
298 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
299 0, 0x7F, 0),
300 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
301 3, 0x1F, 0),
302 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
303 3, 0x1F, 0),
304 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
305 0, 0x1F, 0),
306 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
307 0, 0x0F, 0),
308};
309
310static const struct aic32x4_rate_divs aic32x4_divs[] = {
311 /* 8k rate */
514b044c
AM		 312 { 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 },
313 { 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
314 { 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
1d471cd1 315 /* 11.025k rate */
514b044c
AM		 316 { 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 },
317 { 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 },
1d471cd1 318 /* 16k rate */
514b044c
AM		 319 { 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 },
320 { 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
321 { 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
1d471cd1 322 /* 22.05k rate */
514b044c
AM		 323 { 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 },
324 { 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
325 { 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
1d471cd1 326 /* 32k rate */
514b044c
AM		 327 { 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 },
328 { 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 },
1d471cd1 329 /* 44.1k rate */
514b044c
AM		 330 { 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
331 { 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
332 { 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
1d471cd1 333 /* 48k rate */
514b044c
AM		 334 { 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
335 { 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
336 { 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
041f9d33
JM		 337
338 /* 96k rate */
514b044c 339 { 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 },
1d471cd1
JM		 340};
341
342static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
343 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
344 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
345};
346
347static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
348 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
349 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
350};
351
352static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
353 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
354};
355
356static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
357 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
358};
359
20d2cecb
JM		 360static const char * const resistor_text[] = {
361 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
362};
363
2213fc35
JM		 364/* Left mixer pins */
365static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
366static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
367static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
368static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
369
370static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
371static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
372static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
373
374static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
375 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
376};
377static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
378 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
379};
380static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
381 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
382};
383static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
384 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
385};
386static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
387 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
388};
389static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
390 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
391};
392static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
393 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
1d471cd1
JM		 394};
395
514b044c 396/* Right mixer pins */
2213fc35
JM		 397static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
398static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
399static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
400static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
401static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
402static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
403static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
404
405static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
406 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
407};
408static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
409 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
410};
411static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
412 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
413};
414static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
415 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
416};
417static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
418 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
419};
420static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
421 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
422};
423static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
424 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
1d471cd1
JM		 425};
426
427static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
428 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
429 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
430 &hpl_output_mixer_controls[0],
431 ARRAY_SIZE(hpl_output_mixer_controls)),
432 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
433
434 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
435 &lol_output_mixer_controls[0],
436 ARRAY_SIZE(lol_output_mixer_controls)),
437 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
438
439 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
440 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
441 &hpr_output_mixer_controls[0],
442 ARRAY_SIZE(hpr_output_mixer_controls)),
443 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
444 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
445 &lor_output_mixer_controls[0],
446 ARRAY_SIZE(lor_output_mixer_controls)),
447 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
2213fc35 448
1d471cd1 449 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
2213fc35
JM		 450 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
451 in1r_to_rmixer_controls),
452 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
453 in2r_to_rmixer_controls),
454 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
455 in3r_to_rmixer_controls),
456 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
457 in2l_to_rmixer_controls),
458 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
459 cmr_to_rmixer_controls),
460 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
461 in1l_to_rmixer_controls),
462 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
463 in3l_to_rmixer_controls),
464
465 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
466 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
467 in1l_to_lmixer_controls),
468 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
469 in2l_to_lmixer_controls),
470 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
471 in3l_to_lmixer_controls),
472 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
473 in1r_to_lmixer_controls),
474 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
475 cml_to_lmixer_controls),
476 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
477 in2r_to_lmixer_controls),
478 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
479 in3r_to_lmixer_controls),
480
04d979d7 481 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
482 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
483
1d471cd1
JM		 484
485 SND_SOC_DAPM_OUTPUT("HPL"),
486 SND_SOC_DAPM_OUTPUT("HPR"),
487 SND_SOC_DAPM_OUTPUT("LOL"),
488 SND_SOC_DAPM_OUTPUT("LOR"),
489 SND_SOC_DAPM_INPUT("IN1_L"),
490 SND_SOC_DAPM_INPUT("IN1_R"),
491 SND_SOC_DAPM_INPUT("IN2_L"),
492 SND_SOC_DAPM_INPUT("IN2_R"),
493 SND_SOC_DAPM_INPUT("IN3_L"),
494 SND_SOC_DAPM_INPUT("IN3_R"),
495};
496
497static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
498 /* Left Output */
499 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
500 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
501
502 {"HPL Power", NULL, "HPL Output Mixer"},
503 {"HPL", NULL, "HPL Power"},
504
505 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
506
507 {"LOL Power", NULL, "LOL Output Mixer"},
508 {"LOL", NULL, "LOL Power"},
509
510 /* Right Output */
511 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
512 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
513
514 {"HPR Power", NULL, "HPR Output Mixer"},
515 {"HPR", NULL, "HPR Power"},
516
517 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
518
519 {"LOR Power", NULL, "LOR Output Mixer"},
520 {"LOR", NULL, "LOR Power"},
521
1d471cd1 522 /* Right Input */
2213fc35
JM		 523 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
524 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
525 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
526 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
527
528 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
529 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
530 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
531 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
532
533 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
534 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
535 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
536 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
537
538 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
539 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
540 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
541 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
542
543 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
544 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
545 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
546 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
547
548 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
549 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
550 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
551 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
552
553 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
554 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
555 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
556 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
557
558 /* Left Input */
559 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
560 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
561 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
562 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
563
564 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
565 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
566 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
567 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
568
569 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
570 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
571 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
572 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
573
574 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
575 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
576 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
577 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
578
579 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
580 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
581 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
582 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
583
584 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
585 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
586 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
587 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
588
589 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
590 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
591 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
592 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
1d471cd1
JM		 593};
594
4d208ca4
MB		 595static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
596 {
597 .selector_reg = 0,
514b044c 598 .selector_mask = 0xff,
4d208ca4
MB		 599 .window_start = 0,
600 .window_len = 128,
e8e08c52 601 .range_min = 0,
6d0d5103 602 .range_max = AIC32X4_RMICPGAVOL,
4d208ca4
MB		 603 },
604};
1d471cd1 605
3bcfd222 606const struct regmap_config aic32x4_regmap_config = {
4d208ca4
MB		 607 .max_register = AIC32X4_RMICPGAVOL,
608 .ranges = aic32x4_regmap_pages,
609 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
610};
3bcfd222 611EXPORT_SYMBOL(aic32x4_regmap_config);
1d471cd1
JM		 612
613static inline int aic32x4_get_divs(int mclk, int rate)
614{
615 int i;
616
617 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
618 if ((aic32x4_divs[i].rate == rate)
514b044c 619 && (aic32x4_divs[i].mclk == mclk)) {
1d471cd1
JM		 620 return i;
621 }
622 }
623 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
624 return -EINVAL;
625}
626
1d471cd1
JM		 627static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
628 int clk_id, unsigned int freq, int dir)
629{
b154dc5d
KM		 630 struct snd_soc_component *component = codec_dai->component;
631 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1d471cd1
JM		 632
633 switch (freq) {
7e2a4dc5
AD		 634 case 12000000:
635 case 24000000:
636 case 25000000:
1d471cd1
JM		 637 aic32x4->sysclk = freq;
638 return 0;
639 }
640 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
641 return -EINVAL;
642}
643
644static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
645{
b154dc5d 646 struct snd_soc_component *component = codec_dai->component;
60fb4be5
AD		 647 u8 iface_reg_1 = 0;
648 u8 iface_reg_2 = 0;
649 u8 iface_reg_3 = 0;
1d471cd1
JM		 650
651 /* set master/slave audio interface */
652 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
653 case SND_SOC_DAIFMT_CBM_CFM:
1d471cd1
JM		 654 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
655 break;
656 case SND_SOC_DAIFMT_CBS_CFS:
1d471cd1
JM		 657 break;
658 default:
659 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
660 return -EINVAL;
661 }
662
663 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
664 case SND_SOC_DAIFMT_I2S:
665 break;
666 case SND_SOC_DAIFMT_DSP_A:
4483521d
AD		 667 iface_reg_1 |= (AIC32X4_DSP_MODE <<
668 AIC32X4_IFACE1_DATATYPE_SHIFT);
60fb4be5 669 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
1d471cd1
JM		 670 iface_reg_2 = 0x01; /* add offset 1 */
671 break;
672 case SND_SOC_DAIFMT_DSP_B:
4483521d
AD		 673 iface_reg_1 |= (AIC32X4_DSP_MODE <<
674 AIC32X4_IFACE1_DATATYPE_SHIFT);
60fb4be5 675 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
1d471cd1
JM		 676 break;
677 case SND_SOC_DAIFMT_RIGHT_J:
4483521d
AD		 678 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
679 AIC32X4_IFACE1_DATATYPE_SHIFT);
1d471cd1
JM		 680 break;
681 case SND_SOC_DAIFMT_LEFT_J:
4483521d
AD		 682 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
683 AIC32X4_IFACE1_DATATYPE_SHIFT);
1d471cd1
JM		 684 break;
685 default:
686 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
687 return -EINVAL;
688 }
689
b154dc5d 690 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
514b044c
AM		 691 AIC32X4_IFACE1_DATATYPE_MASK |
692 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
b154dc5d 693 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
514b044c 694 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
b154dc5d 695 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
514b044c 696 AIC32X4_BCLKINV_MASK, iface_reg_3);
60fb4be5 697
1d471cd1
JM		 698 return 0;
699}
700
c95e3a4b
AM		 701static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
702 u8 r_block, u8 p_block)
703{
704 if (r_block > 18 || p_block > 25)
705 return -EINVAL;
706
707 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
708 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
709
710 return 0;
711}
712
bf31cbfb
AM		 713static int aic32x4_setup_clocks(struct snd_soc_component *component,
714 unsigned int sample_rate,
715 unsigned int parent_rate)
1d471cd1 716{
1d471cd1 717 int i;
514b044c
AM		 718 int ret;
719
720 struct clk_bulk_data clocks[] = {
721 { .id = "pll" },
722 };
1d471cd1 723
bf31cbfb 724 i = aic32x4_get_divs(parent_rate, sample_rate);
1d471cd1
JM		 725 if (i < 0) {
726 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
727 return i;
728 }
729
514b044c
AM		 730 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
731 if (ret)
732 return ret;
733
734 clk_set_rate(clocks[0].clk, sample_rate);
735
c95e3a4b
AM		 736 aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
737
64aab899 738 /* PLL as CODEC_CLKIN */
514b044c
AM		 739 snd_soc_component_update_bits(component, AIC32X4_CLKMUX,
740 AIC32X4_CODEC_CLKIN_MASK,
741 AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
64aab899 742 /* DAC_MOD_CLK as BDIV_CLKIN */
b154dc5d 743 snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
514b044c 744 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
1d471cd1
JM		 745
746 /* NDAC divider value */
b154dc5d 747 snd_soc_component_update_bits(component, AIC32X4_NDAC,
514b044c 748 AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
1d471cd1
JM		 749
750 /* MDAC divider value */
b154dc5d 751 snd_soc_component_update_bits(component, AIC32X4_MDAC,
514b044c 752 AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
1d471cd1
JM		 753
754 /* DOSR MSB & LSB values */
b154dc5d
KM		 755 snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
756 snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
1d471cd1
JM		 757
758 /* NADC divider value */
b154dc5d 759 snd_soc_component_update_bits(component, AIC32X4_NADC,
514b044c 760 AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
1d471cd1
JM		 761
762 /* MADC divider value */
b154dc5d 763 snd_soc_component_update_bits(component, AIC32X4_MADC,
514b044c 764 AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
1d471cd1
JM		 765
766 /* AOSR value */
b154dc5d 767 snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
1d471cd1
JM		 768
769 /* BCLK N divider */
b154dc5d 770 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
514b044c 771 AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
1d471cd1 772
bf31cbfb
AM		 773 return 0;
774}
775
776static int aic32x4_hw_params(struct snd_pcm_substream *substream,
777 struct snd_pcm_hw_params *params,
778 struct snd_soc_dai *dai)
779{
780 struct snd_soc_component *component = dai->component;
781 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
782 u8 iface1_reg = 0;
783 u8 dacsetup_reg = 0;
784
785 aic32x4_setup_clocks(component, params_rate(params), aic32x4->sysclk);
786
bd8a5711
MB		 787 switch (params_width(params)) {
788 case 16:
64aab899 789 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
514b044c 790 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1 791 break;
bd8a5711 792 case 20:
64aab899 793 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
514b044c 794 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1 795 break;
bd8a5711 796 case 24:
64aab899 797 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
514b044c 798 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1 799 break;
bd8a5711 800 case 32:
64aab899 801 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
514b044c 802 AIC32X4_IFACE1_DATALEN_SHIFT);
1d471cd1
JM		 803 break;
804 }
b154dc5d 805 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
514b044c 806 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
1d471cd1 807
b44aa40f 808 if (params_channels(params) == 1) {
64aab899 809 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
b44aa40f
MP		 810 } else {
811 if (aic32x4->swapdacs)
64aab899 812 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
b44aa40f 813 else
64aab899 814 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
b44aa40f 815 }
b154dc5d 816 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
514b044c 817 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
b44aa40f 818
1d471cd1
JM		 819 return 0;
820}
821
822static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
823{
b154dc5d 824 struct snd_soc_component *component = dai->component;
1d471cd1 825
b154dc5d 826 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
514b044c 827 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
b7ddd9ca 828
1d471cd1
JM		 829 return 0;
830}
831
b154dc5d 832static int aic32x4_set_bias_level(struct snd_soc_component *component,
1d471cd1
JM		 833 enum snd_soc_bias_level level)
834{
b154dc5d 835 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
98b664e2
MP		 836 int ret;
837
1d471cd1
JM		 838 switch (level) {
839 case SND_SOC_BIAS_ON:
98b664e2
MP		 840 /* Switch on master clock */
841 ret = clk_prepare_enable(aic32x4->mclk);
842 if (ret) {
b154dc5d 843 dev_err(component->dev, "Failed to enable master clock\n");
98b664e2
MP		 844 return ret;
845 }
846
01b37e94 847 /* Switch on PLL */
b154dc5d 848 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
514b044c 849 AIC32X4_PLLEN, AIC32X4_PLLEN);
01b37e94
WS		 850
851 /* Switch on NDAC Divider */
b154dc5d 852 snd_soc_component_update_bits(component, AIC32X4_NDAC,
514b044c 853 AIC32X4_NDACEN, AIC32X4_NDACEN);
01b37e94
WS		 854
855 /* Switch on MDAC Divider */
b154dc5d 856 snd_soc_component_update_bits(component, AIC32X4_MDAC,
514b044c 857 AIC32X4_MDACEN, AIC32X4_MDACEN);
01b37e94
WS		 858
859 /* Switch on NADC Divider */
b154dc5d 860 snd_soc_component_update_bits(component, AIC32X4_NADC,
514b044c 861 AIC32X4_NADCEN, AIC32X4_NADCEN);
01b37e94
WS		 862
863 /* Switch on MADC Divider */
b154dc5d 864 snd_soc_component_update_bits(component, AIC32X4_MADC,
514b044c 865 AIC32X4_MADCEN, AIC32X4_MADCEN);
01b37e94
WS		 866
867 /* Switch on BCLK_N Divider */
b154dc5d 868 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
514b044c 869 AIC32X4_BCLKEN, AIC32X4_BCLKEN);
1d471cd1
JM		 870 break;
871 case SND_SOC_BIAS_PREPARE:
872 break;
873 case SND_SOC_BIAS_STANDBY:
667e9334 874 /* Initial cold start */
875 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
876 break;
877
3154cc74 878 /* Switch off BCLK_N Divider */
b154dc5d 879 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
514b044c 880 AIC32X4_BCLKEN, 0);
01b37e94 881
3154cc74 882 /* Switch off MADC Divider */
b154dc5d 883 snd_soc_component_update_bits(component, AIC32X4_MADC,
514b044c 884 AIC32X4_MADCEN, 0);
01b37e94
WS		 885
886 /* Switch off NADC Divider */
b154dc5d 887 snd_soc_component_update_bits(component, AIC32X4_NADC,
514b044c 888 AIC32X4_NADCEN, 0);
01b37e94 889
3154cc74 890 /* Switch off MDAC Divider */
b154dc5d 891 snd_soc_component_update_bits(component, AIC32X4_MDAC,
514b044c 892 AIC32X4_MDACEN, 0);
01b37e94 893
3154cc74 894 /* Switch off NDAC Divider */
b154dc5d 895 snd_soc_component_update_bits(component, AIC32X4_NDAC,
514b044c 896 AIC32X4_NDACEN, 0);
3154cc74
MP		 897
898 /* Switch off PLL */
b154dc5d 899 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
514b044c 900 AIC32X4_PLLEN, 0);
98b664e2
MP		 901
902 /* Switch off master clock */
903 clk_disable_unprepare(aic32x4->mclk);
1d471cd1
JM		 904 break;
905 case SND_SOC_BIAS_OFF:
906 break;
907 }
1d471cd1
JM		 908 return 0;
909}
910
041f9d33 911#define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000
514b044c 912#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1d471cd1
JM		 913 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
914
85e7652d 915static const struct snd_soc_dai_ops aic32x4_ops = {
1d471cd1
JM		 916 .hw_params = aic32x4_hw_params,
917 .digital_mute = aic32x4_mute,
918 .set_fmt = aic32x4_set_dai_fmt,
919 .set_sysclk = aic32x4_set_dai_sysclk,
920};
921
922static struct snd_soc_dai_driver aic32x4_dai = {
923 .name = "tlv320aic32x4-hifi",
924 .playback = {
514b044c
AM		 925 .stream_name = "Playback",
926 .channels_min = 1,
927 .channels_max = 2,
928 .rates = AIC32X4_RATES,
929 .formats = AIC32X4_FORMATS,},
1d471cd1 930 .capture = {
514b044c
AM		 931 .stream_name = "Capture",
932 .channels_min = 1,
933 .channels_max = 2,
934 .rates = AIC32X4_RATES,
935 .formats = AIC32X4_FORMATS,},
1d471cd1
JM		 936 .ops = &aic32x4_ops,
937 .symmetric_rates = 1,
938};
939
b154dc5d 940static void aic32x4_setup_gpios(struct snd_soc_component *component)
b9045b9c 941{
b154dc5d 942 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
b9045b9c
DM		 943
944 /* setup GPIO functions */
945 /* MFP1 */
946 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 947 snd_soc_component_write(component, AIC32X4_DINCTL,
514b044c 948 aic32x4->setup->gpio_func[0]);
b154dc5d 949 snd_soc_add_component_controls(component, aic32x4_mfp1,
b9045b9c
DM		 950 ARRAY_SIZE(aic32x4_mfp1));
951 }
952
953 /* MFP2 */
954 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 955 snd_soc_component_write(component, AIC32X4_DOUTCTL,
514b044c 956 aic32x4->setup->gpio_func[1]);
b154dc5d 957 snd_soc_add_component_controls(component, aic32x4_mfp2,
b9045b9c
DM		 958 ARRAY_SIZE(aic32x4_mfp2));
959 }
960
961 /* MFP3 */
962 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 963 snd_soc_component_write(component, AIC32X4_SCLKCTL,
514b044c 964 aic32x4->setup->gpio_func[2]);
b154dc5d 965 snd_soc_add_component_controls(component, aic32x4_mfp3,
b9045b9c
DM		 966 ARRAY_SIZE(aic32x4_mfp3));
967 }
968
969 /* MFP4 */
970 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 971 snd_soc_component_write(component, AIC32X4_MISOCTL,
514b044c 972 aic32x4->setup->gpio_func[3]);
b154dc5d 973 snd_soc_add_component_controls(component, aic32x4_mfp4,
b9045b9c
DM		 974 ARRAY_SIZE(aic32x4_mfp4));
975 }
976
977 /* MFP5 */
978 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
b154dc5d 979 snd_soc_component_write(component, AIC32X4_GPIOCTL,
514b044c 980 aic32x4->setup->gpio_func[4]);
b154dc5d 981 snd_soc_add_component_controls(component, aic32x4_mfp5,
b9045b9c
DM		 982 ARRAY_SIZE(aic32x4_mfp5));
983 }
984}
985
b154dc5d 986static int aic32x4_component_probe(struct snd_soc_component *component)
1d471cd1 987{
b154dc5d 988 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1d471cd1
JM		 989 u32 tmp_reg;
990
a74ab512 991 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1858fe97
JM		 992 ndelay(10);
993 gpio_set_value(aic32x4->rstn_gpio, 1);
674f9abd 994 mdelay(1);
1858fe97
JM		 995 }
996
b154dc5d 997 snd_soc_component_write(component, AIC32X4_RESET, 0x01);
1d471cd1 998
b9045b9c 999 if (aic32x4->setup)
b154dc5d 1000 aic32x4_setup_gpios(component);
b9045b9c 1001
1d471cd1
JM		 1002 /* Power platform configuration */
1003 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
514b044c
AM		 1004 snd_soc_component_write(component, AIC32X4_MICBIAS,
1005 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1d471cd1 1006 }
eb72cbdf 1007 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
b154dc5d 1008 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
0c93a167
WS		 1009
1010 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1011 AIC32X4_LDOCTLEN : 0;
b154dc5d 1012 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
0c93a167 1013
b154dc5d 1014 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE);
eb72cbdf 1015 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1d471cd1 1016 tmp_reg |= AIC32X4_LDOIN_18_36;
eb72cbdf 1017 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1d471cd1 1018 tmp_reg |= AIC32X4_LDOIN2HP;
b154dc5d 1019 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1d471cd1 1020
1d471cd1 1021 /* Mic PGA routing */
609e6025 1022 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
b154dc5d 1023 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
43bf38ba 1024 AIC32X4_LMICPGANIN_IN2R_10K);
609e6025 1025 else
b154dc5d 1026 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
43bf38ba 1027 AIC32X4_LMICPGANIN_CM1L_10K);
609e6025 1028 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
b154dc5d 1029 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
43bf38ba 1030 AIC32X4_RMICPGANIN_IN1L_10K);
609e6025 1031 else
b154dc5d 1032 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
43bf38ba 1033 AIC32X4_RMICPGANIN_CM1R_10K);
1d471cd1 1034
a405387c
JM		 1035 /*
1036 * Workaround: for an unknown reason, the ADC needs to be powered up
1037 * and down for the first capture to work properly. It seems related to
1038 * a HW BUG or some kind of behavior not documented in the datasheet.
1039 */
b154dc5d
KM		 1040 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);
1041 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
a405387c 1042 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
b154dc5d 1043 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
a405387c 1044
1d471cd1
JM		 1045 return 0;
1046}
1047
b154dc5d
KM		 1048static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1049 .probe = aic32x4_component_probe,
1050 .set_bias_level = aic32x4_set_bias_level,
1051 .controls = aic32x4_snd_controls,
1052 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1053 .dapm_widgets = aic32x4_dapm_widgets,
1054 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1055 .dapm_routes = aic32x4_dapm_routes,
1056 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1057 .suspend_bias_off = 1,
1058 .idle_bias_on = 1,
1059 .use_pmdown_time = 1,
1060 .endianness = 1,
1061 .non_legacy_dai_naming = 1,
1d471cd1
JM		 1062};
1063
4d16700d
MP		 1064static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1065 struct device_node *np)
1066{
b9045b9c 1067 struct aic32x4_setup_data *aic32x4_setup;
514b044c 1068 int ret;
b9045b9c
DM		 1069
1070 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1071 GFP_KERNEL);
1072 if (!aic32x4_setup)
1073 return -ENOMEM;
1074
514b044c
AM		 1075 ret = of_property_match_string(np, "clock-names", "mclk");
1076 if (ret < 0)
1077 return -EINVAL;
1078 aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1079
4d16700d
MP		 1080 aic32x4->swapdacs = false;
1081 aic32x4->micpga_routing = 0;
1082 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1083
b9045b9c
DM		 1084 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1085 aic32x4_setup->gpio_func, 5) >= 0)
1086 aic32x4->setup = aic32x4_setup;
4d16700d
MP		 1087 return 0;
1088}
1089
239b669b
MP		 1090static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1091{
1092 regulator_disable(aic32x4->supply_iov);
1093
1094 if (!IS_ERR(aic32x4->supply_ldo))
1095 regulator_disable(aic32x4->supply_ldo);
1096
1097 if (!IS_ERR(aic32x4->supply_dv))
1098 regulator_disable(aic32x4->supply_dv);
1099
1100 if (!IS_ERR(aic32x4->supply_av))
1101 regulator_disable(aic32x4->supply_av);
1102}
1103
1104static int aic32x4_setup_regulators(struct device *dev,
1105 struct aic32x4_priv *aic32x4)
1106{
1107 int ret = 0;
1108
1109 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1110 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1111 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1112 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1113
1114 /* Check if the regulator requirements are fulfilled */
1115
1116 if (IS_ERR(aic32x4->supply_iov)) {
1117 dev_err(dev, "Missing supply 'iov'\n");
1118 return PTR_ERR(aic32x4->supply_iov);
1119 }
1120
1121 if (IS_ERR(aic32x4->supply_ldo)) {
1122 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1123 return -EPROBE_DEFER;
1124
1125 if (IS_ERR(aic32x4->supply_dv)) {
1126 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1127 return PTR_ERR(aic32x4->supply_dv);
1128 }
1129 if (IS_ERR(aic32x4->supply_av)) {
1130 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1131 return PTR_ERR(aic32x4->supply_av);
1132 }
1133 } else {
1134 if (IS_ERR(aic32x4->supply_dv) &&
1135 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1136 return -EPROBE_DEFER;
1137 if (IS_ERR(aic32x4->supply_av) &&
1138 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1139 return -EPROBE_DEFER;
1140 }
1141
1142 ret = regulator_enable(aic32x4->supply_iov);
1143 if (ret) {
1144 dev_err(dev, "Failed to enable regulator iov\n");
1145 return ret;
1146 }
1147
1148 if (!IS_ERR(aic32x4->supply_ldo)) {
1149 ret = regulator_enable(aic32x4->supply_ldo);
1150 if (ret) {
1151 dev_err(dev, "Failed to enable regulator ldo\n");
1152 goto error_ldo;
1153 }
1154 }
1155
1156 if (!IS_ERR(aic32x4->supply_dv)) {
1157 ret = regulator_enable(aic32x4->supply_dv);
1158 if (ret) {
1159 dev_err(dev, "Failed to enable regulator dv\n");
1160 goto error_dv;
1161 }
1162 }
1163
1164 if (!IS_ERR(aic32x4->supply_av)) {
1165 ret = regulator_enable(aic32x4->supply_av);
1166 if (ret) {
1167 dev_err(dev, "Failed to enable regulator av\n");
1168 goto error_av;
1169 }
1170 }
1171
1172 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1173 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1174
1175 return 0;
1176
1177error_av:
1178 if (!IS_ERR(aic32x4->supply_dv))
1179 regulator_disable(aic32x4->supply_dv);
1180
1181error_dv:
1182 if (!IS_ERR(aic32x4->supply_ldo))
1183 regulator_disable(aic32x4->supply_ldo);
1184
1185error_ldo:
1186 regulator_disable(aic32x4->supply_iov);
1187 return ret;
1188}
1189
3bcfd222 1190int aic32x4_probe(struct device *dev, struct regmap *regmap)
1d471cd1 1191{
1d471cd1 1192 struct aic32x4_priv *aic32x4;
3bcfd222
JM		 1193 struct aic32x4_pdata *pdata = dev->platform_data;
1194 struct device_node *np = dev->of_node;
1d471cd1
JM		 1195 int ret;
1196
3bcfd222
JM		 1197 if (IS_ERR(regmap))
1198 return PTR_ERR(regmap);
1199
1200 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
514b044c 1201 GFP_KERNEL);
1d471cd1
JM		 1202 if (aic32x4 == NULL)
1203 return -ENOMEM;
1204
b9045b9c 1205 aic32x4->dev = dev;
3bcfd222 1206 dev_set_drvdata(dev, aic32x4);
1d471cd1
JM		 1207
1208 if (pdata) {
1209 aic32x4->power_cfg = pdata->power_cfg;
1210 aic32x4->swapdacs = pdata->swapdacs;
1211 aic32x4->micpga_routing = pdata->micpga_routing;
1858fe97 1212 aic32x4->rstn_gpio = pdata->rstn_gpio;
514b044c 1213 aic32x4->mclk_name = "mclk";
4d16700d
MP		 1214 } else if (np) {
1215 ret = aic32x4_parse_dt(aic32x4, np);
1216 if (ret) {
3bcfd222 1217 dev_err(dev, "Failed to parse DT node\n");
4d16700d
MP		 1218 return ret;
1219 }
1d471cd1
JM		 1220 } else {
1221 aic32x4->power_cfg = 0;
1222 aic32x4->swapdacs = false;
1223 aic32x4->micpga_routing = 0;
1858fe97 1224 aic32x4->rstn_gpio = -1;
514b044c 1225 aic32x4->mclk_name = "mclk";
1d471cd1
JM		 1226 }
1227
3bcfd222 1228 aic32x4->mclk = devm_clk_get(dev, "mclk");
98b664e2 1229 if (IS_ERR(aic32x4->mclk)) {
3bcfd222 1230 dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
98b664e2
MP		 1231 return PTR_ERR(aic32x4->mclk);
1232 }
1233
514b044c
AM		 1234 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1235 if (ret)
1236 return ret;
1237
a74ab512 1238 if (gpio_is_valid(aic32x4->rstn_gpio)) {
3bcfd222 1239 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
752b7764
MB		 1240 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1241 if (ret != 0)
1242 return ret;
1243 }
1244
3bcfd222 1245 ret = aic32x4_setup_regulators(dev, aic32x4);
239b669b 1246 if (ret) {
3bcfd222 1247 dev_err(dev, "Failed to setup regulators\n");
239b669b
MP		 1248 return ret;
1249 }
1250
b154dc5d
KM		 1251 ret = devm_snd_soc_register_component(dev,
1252 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
239b669b 1253 if (ret) {
b154dc5d 1254 dev_err(dev, "Failed to register component\n");
239b669b
MP		 1255 aic32x4_disable_regulators(aic32x4);
1256 return ret;
1257 }
1258
239b669b 1259 return 0;
1d471cd1 1260}
3bcfd222 1261EXPORT_SYMBOL(aic32x4_probe);
1d471cd1 1262
3bcfd222 1263int aic32x4_remove(struct device *dev)
1d471cd1 1264{
3bcfd222 1265 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
239b669b
MP		 1266
1267 aic32x4_disable_regulators(aic32x4);
1268
1d471cd1
JM		 1269 return 0;
1270}
3bcfd222 1271EXPORT_SYMBOL(aic32x4_remove);
1d471cd1
JM		 1272
1273MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1274MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1275MODULE_LICENSE("GPL");
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