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Merge remote-tracking branch 'regulator/fix/fixed' into regulator-linus
[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
b3b70786 43#include <linux/of.h>
c24fdc88 44#include <linux/of_gpio.h>
5a0e3ad6 45#include <linux/slab.h>
44d0a879
VB		 46#include <sound/core.h>
47#include <sound/pcm.h>
48#include <sound/pcm_params.h>
49#include <sound/soc.h>
44d0a879 50#include <sound/initval.h>
7565fc38 51#include <sound/tlv.h>
5193d62f 52#include <sound/tlv320aic3x.h>
44d0a879
VB		 53
54#include "tlv320aic3x.h"
55
07779fdd
JN		 56#define AIC3X_NUM_SUPPLIES 4
57static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62};
44d0a879 63
414c73ab
JN		 64static LIST_HEAD(reset_list);
65
5a895f8a
JN		 66struct aic3x_priv;
67
68struct aic3x_disable_nb {
69 struct notifier_block nb;
70 struct aic3x_priv *aic3x;
71};
72
44d0a879
VB		 73/* codec private data */
74struct aic3x_priv {
5a895f8a 75 struct snd_soc_codec *codec;
2a6fedec 76 struct regmap *regmap;
07779fdd 77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad 79 struct aic3x_setup_data *setup;
44d0a879 80 unsigned int sysclk;
414c73ab 81 struct list_head list;
44d0a879 82 int master;
5193d62f 83 int gpio_reset;
6c1a7d40 84 int power;
6184f105
RC		 85#define AIC3X_MODEL_3X 0
86#define AIC3X_MODEL_33 1
87#define AIC3X_MODEL_3007 2
88 u16 model;
e2e8bfdf
HG		 89
90 /* Selects the micbias voltage */
91 enum aic3x_micbias_voltage micbias_vg;
44d0a879
VB		 92};
93
2a6fedec
MB		 94static const struct reg_default aic3x_reg[] = {
95 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
96 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
97 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
98 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
99 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
100 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
101 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
102 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
103 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
104 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
105 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
106 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
107 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
108 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
109 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
110 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
111 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
112 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
113 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
114 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
115 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
116 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
117 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
118 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
119 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
120 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
121 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
122 { 108, 0x00 }, { 109, 0x00 },
123};
124
125static const struct regmap_config aic3x_regmap = {
126 .reg_bits = 8,
127 .val_bits = 8,
128
129 .max_register = DAC_ICC_ADJ,
130 .reg_defaults = aic3x_reg,
131 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
132 .cache_type = REGCACHE_RBTREE,
44d0a879
VB		 133};
134
44d0a879 135#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
1476f66f
LPC		 136 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
137 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
44d0a879
VB		 138
139/*
140 * All input lines are connected when !0xf and disconnected with 0xf bit field,
141 * so we have to use specific dapm_put call for input mixer
142 */
143static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
144 struct snd_ctl_elem_value *ucontrol)
145{
eee5d7f9 146 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
4453dba5
EN		 147 struct soc_mixer_control *mc =
148 (struct soc_mixer_control *)kcontrol->private_value;
149 unsigned int reg = mc->reg;
150 unsigned int shift = mc->shift;
151 int max = mc->max;
152 unsigned int mask = (1 << fls(max)) - 1;
153 unsigned int invert = mc->invert;
5d99d778
LPC		 154 unsigned short val;
155 struct snd_soc_dapm_update update;
156 int connect, change;
44d0a879
VB		 157
158 val = (ucontrol->value.integer.value[0] & mask);
159
160 mask = 0xf;
161 if (val)
162 val = mask;
163
5d99d778
LPC		 164 connect = !!val;
165
44d0a879
VB		 166 if (invert)
167 val = mask - val;
44d0a879 168
5d99d778
LPC		 169 mask <<= shift;
170 val <<= shift;
2894770e 171
eee5d7f9 172 change = snd_soc_test_bits(codec, val, mask, reg);
5d99d778
LPC		 173 if (change) {
174 update.kcontrol = kcontrol;
175 update.reg = reg;
176 update.mask = mask;
177 update.val = val;
178
eee5d7f9 179 snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect,
5d99d778
LPC		 180 &update);
181 }
2894770e 182
5d99d778 183 return change;
44d0a879
VB		 184}
185
e2e8bfdf
HG		 186/*
187 * mic bias power on/off share the same register bits with
188 * output voltage of mic bias. when power on mic bias, we
189 * need reclaim it to voltage value.
190 * 0x0 = Powered off
191 * 0x1 = MICBIAS output is powered to 2.0V,
192 * 0x2 = MICBIAS output is powered to 2.5V
193 * 0x3 = MICBIAS output is connected to AVDD
194 */
195static int mic_bias_event(struct snd_soc_dapm_widget *w,
196 struct snd_kcontrol *kcontrol, int event)
197{
198 struct snd_soc_codec *codec = w->codec;
199 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
200
201 switch (event) {
202 case SND_SOC_DAPM_POST_PMU:
203 /* change mic bias voltage to user defined */
204 snd_soc_update_bits(codec, MICBIAS_CTRL,
205 MICBIAS_LEVEL_MASK,
206 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
207 break;
208
209 case SND_SOC_DAPM_PRE_PMD:
210 snd_soc_update_bits(codec, MICBIAS_CTRL,
211 MICBIAS_LEVEL_MASK, 0);
212 break;
213 }
214 return 0;
215}
216
44d0a879
VB		 217static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
218static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
219static const char *aic3x_left_hpcom_mux[] =
220 { "differential of HPLOUT", "constant VCM", "single-ended" };
221static const char *aic3x_right_hpcom_mux[] =
222 { "differential of HPROUT", "constant VCM", "single-ended",
223 "differential of HPLCOM", "external feedback" };
224static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 225static const char *aic3x_adc_hpf[] =
226 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 227
228#define LDAC_ENUM 0
229#define RDAC_ENUM 1
230#define LHPCOM_ENUM 2
231#define RHPCOM_ENUM 3
404b5665
JN		 232#define LINE1L_2_L_ENUM 4
233#define LINE1L_2_R_ENUM 5
234#define LINE1R_2_L_ENUM 6
235#define LINE1R_2_R_ENUM 7
236#define LINE2L_ENUM 8
237#define LINE2R_ENUM 9
238#define ADC_HPF_ENUM 10
44d0a879
VB		 239
240static const struct soc_enum aic3x_enum[] = {
241 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
242 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
243 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
244 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
245 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
404b5665
JN		 246 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
247 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
44d0a879
VB		 248 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
249 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
250 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 251 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 252};
253
bb1daa80
JP		 254static const char *aic3x_agc_level[] =
255 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" };
256static const struct soc_enum aic3x_agc_level_enum[] = {
257 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level),
258 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level),
259};
260
261static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" };
262static const struct soc_enum aic3x_agc_attack_enum[] = {
263 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack),
264 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack),
265};
266
267static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" };
268static const struct soc_enum aic3x_agc_decay_enum[] = {
269 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay),
270 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay),
271};
272
7565fc38
JN		 273/*
274 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
275 */
276static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
277/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
278static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
279/*
280 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
281 * Step size is approximately 0.5 dB over most of the scale but increasing
282 * near the very low levels.
283 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
284 * but having increasing dB difference below that (and where it doesn't count
285 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
286 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
287 */
288static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
289
44d0a879
VB		 290static const struct snd_kcontrol_new aic3x_snd_controls[] = {
291 /* Output */
7565fc38
JN		 292 SOC_DOUBLE_R_TLV("PCM Playback Volume",
293 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 294
098b1718
JN		 295 /*
296 * Output controls that map to output mixer switches. Note these are
297 * only for swapped L-to-R and R-to-L routes. See below stereo controls
298 * for direct L-to-L and R-to-R routes.
299 */
300 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
301 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
302 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
303 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
304 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
305 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
306
307 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
308 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
309 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
310 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
311 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
312 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
313
314 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
315 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
316 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
317 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
318 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
319 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
320
321 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
322 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
323 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
324 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
325 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
326 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
327
328 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
329 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
330 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
331 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
332 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
333 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
334
335 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
336 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
337 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
338 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
340 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
341
342 /* Stereo output controls for direct L-to-L and R-to-R routes */
343 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
344 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
345 0, 118, 1, output_stage_tlv),
346 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
347 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
348 0, 118, 1, output_stage_tlv),
7565fc38
JN		 349 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
350 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
351 0, 118, 1, output_stage_tlv),
098b1718
JN		 352
353 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
354 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 355 0, 118, 1, output_stage_tlv),
098b1718
JN		 356 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
357 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 358 0, 118, 1, output_stage_tlv),
7565fc38
JN		 359 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
360 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
361 0, 118, 1, output_stage_tlv),
098b1718
JN		 362
363 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
364 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 365 0, 118, 1, output_stage_tlv),
098b1718
JN		 366 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
367 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 368 0, 118, 1, output_stage_tlv),
7565fc38
JN		 369 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
370 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
371 0, 118, 1, output_stage_tlv),
098b1718
JN		 372
373 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
374 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 375 0, 118, 1, output_stage_tlv),
098b1718
JN		 376 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
377 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 378 0, 118, 1, output_stage_tlv),
7565fc38
JN		 379 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
380 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
381 0, 118, 1, output_stage_tlv),
098b1718
JN		 382
383 /* Output pin mute controls */
384 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
385 0x01, 0),
386 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
387 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
388 0x01, 0),
f9bc0297 389 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 390 0x01, 0),
44d0a879
VB		 391
392 /*
393 * Note: enable Automatic input Gain Controller with care. It can
394 * adjust PGA to max value when ADC is on and will never go back.
395 */
396 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
bb1daa80
JP		 397 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]),
398 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]),
399 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]),
400 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]),
401 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]),
402 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]),
44d0a879 403
77444191
JP		 404 /* De-emphasis */
405 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
44d0a879
VB		 406
407 /* Input */
7565fc38
JN		 408 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
409 0, 119, 0, adc_tlv),
44d0a879 410 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 411
412 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 413};
414
6184f105
RC		 415/*
416 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
417 */
418static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
419
420static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
14a95fe8 421 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
6184f105 422
44d0a879
VB		 423/* Left DAC Mux */
424static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
425SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
426
427/* Right DAC Mux */
428static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
429SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
430
431/* Left HPCOM Mux */
432static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
433SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
434
435/* Right HPCOM Mux */
436static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
437SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
438
c3b79e05
JN		 439/* Left Line Mixer */
440static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
441 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
442 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
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VB		 447};
448
c3b79e05
JN		 449/* Right Line Mixer */
450static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
451 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
457};
458
459/* Mono Mixer */
460static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
461 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
462 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
463 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
464 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
467};
468
469/* Left HP Mixer */
470static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
471 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
472 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
473 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
474 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
475 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
476 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
477};
478
479/* Right HP Mixer */
480static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
481 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
482 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
483 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
484 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
485 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
486 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
487};
488
489/* Left HPCOM Mixer */
490static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
491 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
492 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
493 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
494 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
495 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
496 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
497};
498
499/* Right HPCOM Mixer */
500static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
501 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
502 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
503 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
504 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
505 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
506 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
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VB		 507};
508
509/* Left PGA Mixer */
510static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
511 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 512 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
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VB		 513 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
514 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 515 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
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VB		 516};
517
518/* Right PGA Mixer */
519static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
520 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 521 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 522 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 523 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
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VB		 524 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
525};
526
527/* Left Line1 Mux */
404b5665
JN		 528static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
529SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
530static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
531SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
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VB		 532
533/* Right Line1 Mux */
404b5665
JN		 534static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
535SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
536static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
537SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
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VB		 538
539/* Left Line2 Mux */
540static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
541SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
542
543/* Right Line2 Mux */
544static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
545SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
546
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VB		 547static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
548 /* Left DAC to Left Outputs */
549 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
550 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
551 &aic3x_left_dac_mux_controls),
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VB		 552 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
553 &aic3x_left_hpcom_mux_controls),
554 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
555 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
556 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
557
558 /* Right DAC to Right Outputs */
559 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
560 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
561 &aic3x_right_dac_mux_controls),
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VB		 562 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
563 &aic3x_right_hpcom_mux_controls),
564 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
565 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
566 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
567
568 /* Mono Output */
569 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
570
54f01916 571 /* Inputs to Left ADC */
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VB		 572 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
573 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
574 &aic3x_left_pga_mixer_controls[0],
575 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
576 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 577 &aic3x_left_line1l_mux_controls),
54f01916 578 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 579 &aic3x_left_line1r_mux_controls),
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VB		 580 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
581 &aic3x_left_line2_mux_controls),
582
54f01916 583 /* Inputs to Right ADC */
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VB		 584 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
585 LINE1R_2_RADC_CTRL, 2, 0),
586 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
587 &aic3x_right_pga_mixer_controls[0],
588 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916 589 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 590 &aic3x_right_line1l_mux_controls),
44d0a879 591 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 592 &aic3x_right_line1r_mux_controls),
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VB		 593 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
594 &aic3x_right_line2_mux_controls),
595
ee15ffdb
JN		 596 /*
597 * Not a real mic bias widget but similar function. This is for dynamic
598 * control of GPIO1 digital mic modulator clock output function when
599 * using digital mic.
600 */
601 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
602 AIC3X_GPIO1_REG, 4, 0xf,
603 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
604 AIC3X_GPIO1_FUNC_DISABLED),
605
606 /*
607 * Also similar function like mic bias. Selects digital mic with
608 * configurable oversampling rate instead of ADC converter.
609 */
610 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
611 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
612 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
613 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
614 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
615 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
616
44d0a879 617 /* Mic Bias */
e2e8bfdf
HG		 618 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
619 mic_bias_event,
620 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
44d0a879 621
c3b79e05
JN		 622 /* Output mixers */
623 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
624 &aic3x_left_line_mixer_controls[0],
625 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
626 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
627 &aic3x_right_line_mixer_controls[0],
628 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
629 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
630 &aic3x_mono_mixer_controls[0],
631 ARRAY_SIZE(aic3x_mono_mixer_controls)),
632 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
633 &aic3x_left_hp_mixer_controls[0],
634 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
635 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
636 &aic3x_right_hp_mixer_controls[0],
637 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
638 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
639 &aic3x_left_hpcom_mixer_controls[0],
640 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
641 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
642 &aic3x_right_hpcom_mixer_controls[0],
643 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
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VB		 644
645 SND_SOC_DAPM_OUTPUT("LLOUT"),
646 SND_SOC_DAPM_OUTPUT("RLOUT"),
647 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
648 SND_SOC_DAPM_OUTPUT("HPLOUT"),
649 SND_SOC_DAPM_OUTPUT("HPROUT"),
650 SND_SOC_DAPM_OUTPUT("HPLCOM"),
651 SND_SOC_DAPM_OUTPUT("HPRCOM"),
652
653 SND_SOC_DAPM_INPUT("MIC3L"),
654 SND_SOC_DAPM_INPUT("MIC3R"),
655 SND_SOC_DAPM_INPUT("LINE1L"),
656 SND_SOC_DAPM_INPUT("LINE1R"),
657 SND_SOC_DAPM_INPUT("LINE2L"),
658 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 659
660 /*
661 * Virtual output pin to detection block inside codec. This can be
662 * used to keep codec bias on if gpio or detection features are needed.
663 * Force pin on or construct a path with an input jack and mic bias
664 * widgets.
665 */
666 SND_SOC_DAPM_OUTPUT("Detection"),
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VB		 667};
668
6184f105
RC		 669static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
670 /* Class-D outputs */
671 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
672 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
673
674 SND_SOC_DAPM_OUTPUT("SPOP"),
675 SND_SOC_DAPM_OUTPUT("SPOM"),
676};
677
d0cc0d3a 678static const struct snd_soc_dapm_route intercon[] = {
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VB		 679 /* Left Input */
680 {"Left Line1L Mux", "single-ended", "LINE1L"},
681 {"Left Line1L Mux", "differential", "LINE1L"},
6b2afee1
PU		 682 {"Left Line1R Mux", "single-ended", "LINE1R"},
683 {"Left Line1R Mux", "differential", "LINE1R"},
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VB		 684
685 {"Left Line2L Mux", "single-ended", "LINE2L"},
686 {"Left Line2L Mux", "differential", "LINE2L"},
687
688 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 689 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
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VB		 690 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
691 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 692 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
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VB		 693
694 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 695 {"Left ADC", NULL, "GPIO1 dmic modclk"},
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VB		 696
697 /* Right Input */
698 {"Right Line1R Mux", "single-ended", "LINE1R"},
699 {"Right Line1R Mux", "differential", "LINE1R"},
6b2afee1
PU		 700 {"Right Line1L Mux", "single-ended", "LINE1L"},
701 {"Right Line1L Mux", "differential", "LINE1L"},
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VB		 702
703 {"Right Line2R Mux", "single-ended", "LINE2R"},
704 {"Right Line2R Mux", "differential", "LINE2R"},
705
54f01916 706 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
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VB		 707 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
708 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 709 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
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VB		 710 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
711
712 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 713 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 714
ee15ffdb
JN		 715 /*
716 * Logical path between digital mic enable and GPIO1 modulator clock
717 * output function
718 */
719 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
720 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
721 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 722
723 /* Left DAC Output */
724 {"Left DAC Mux", "DAC_L1", "Left DAC"},
725 {"Left DAC Mux", "DAC_L2", "Left DAC"},
726 {"Left DAC Mux", "DAC_L3", "Left DAC"},
727
728 /* Right DAC Output */
729 {"Right DAC Mux", "DAC_R1", "Right DAC"},
730 {"Right DAC Mux", "DAC_R2", "Right DAC"},
731 {"Right DAC Mux", "DAC_R3", "Right DAC"},
732
733 /* Left Line Output */
734 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
735 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
736 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
737 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
738 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
739 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
740
741 {"Left Line Out", NULL, "Left Line Mixer"},
742 {"Left Line Out", NULL, "Left DAC Mux"},
743 {"LLOUT", NULL, "Left Line Out"},
744
745 /* Right Line Output */
746 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
747 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
748 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
749 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
750 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
751 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
752
753 {"Right Line Out", NULL, "Right Line Mixer"},
754 {"Right Line Out", NULL, "Right DAC Mux"},
755 {"RLOUT", NULL, "Right Line Out"},
756
757 /* Mono Output */
758 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
759 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
760 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
761 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
762 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
763 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
764
765 {"Mono Out", NULL, "Mono Mixer"},
766 {"MONO_LOUT", NULL, "Mono Out"},
767
768 /* Left HP Output */
769 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
770 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
771 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
772 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
773 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
774 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
775
776 {"Left HP Out", NULL, "Left HP Mixer"},
777 {"Left HP Out", NULL, "Left DAC Mux"},
778 {"HPLOUT", NULL, "Left HP Out"},
779
780 /* Right HP Output */
781 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
782 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
783 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
784 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
785 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
786 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
787
788 {"Right HP Out", NULL, "Right HP Mixer"},
789 {"Right HP Out", NULL, "Right DAC Mux"},
790 {"HPROUT", NULL, "Right HP Out"},
791
792 /* Left HPCOM Output */
793 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
794 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
795 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
796 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
797 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
798 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
799
800 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
801 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
802 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
803 {"Left HP Com", NULL, "Left HPCOM Mux"},
804 {"HPLCOM", NULL, "Left HP Com"},
805
806 /* Right HPCOM Output */
807 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
808 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
809 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
810 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
811 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
812 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
813
814 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
815 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
816 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
817 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
818 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
819 {"Right HP Com", NULL, "Right HPCOM Mux"},
820 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 821};
822
6184f105
RC		 823static const struct snd_soc_dapm_route intercon_3007[] = {
824 /* Class-D outputs */
825 {"Left Class-D Out", NULL, "Left Line Out"},
826 {"Right Class-D Out", NULL, "Left Line Out"},
827 {"SPOP", NULL, "Left Class-D Out"},
828 {"SPOM", NULL, "Right Class-D Out"},
829};
830
44d0a879
VB		 831static int aic3x_add_widgets(struct snd_soc_codec *codec)
832{
6184f105 833 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 834 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 835
6184f105 836 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 837 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 838 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 839 snd_soc_dapm_add_routes(dapm, intercon_3007,
840 ARRAY_SIZE(intercon_3007));
6184f105
RC		 841 }
842
44d0a879
VB		 843 return 0;
844}
845
44d0a879 846static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 847 struct snd_pcm_hw_params *params,
848 struct snd_soc_dai *dai)
44d0a879 849{
e6968a17 850 struct snd_soc_codec *codec = dai->codec;
b2c812e2 851 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 852 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 853 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
854 u16 d, pll_d = 1;
255173b4 855 int clk;
44d0a879 856
4f9c16cc 857 /* select data word length */
e18eca43 858 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 859 switch (params_format(params)) {
860 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 861 break;
4f9c16cc
DM		 862 case SNDRV_PCM_FORMAT_S20_3LE:
863 data |= (0x01 << 4);
44d0a879 864 break;
4f9c16cc
DM		 865 case SNDRV_PCM_FORMAT_S24_LE:
866 data |= (0x02 << 4);
44d0a879 867 break;
4f9c16cc
DM		 868 case SNDRV_PCM_FORMAT_S32_LE:
869 data |= (0x03 << 4);
44d0a879
VB		 870 break;
871 }
e18eca43 872 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 873
874 /* Fsref can be 44100 or 48000 */
875 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
876
877 /* Try to find a value for Q which allows us to bypass the PLL and
878 * generate CODEC_CLK directly. */
879 for (pll_q = 2; pll_q < 18; pll_q++)
880 if (aic3x->sysclk / (128 * pll_q) == fsref) {
881 bypass_pll = 1;
882 break;
883 }
884
885 if (bypass_pll) {
886 pll_q &= 0xf;
e18eca43
JN		 887 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
888 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 889 /* disable PLL if it is bypassed */
9c173d15 890 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
06c71282
C		 891
892 } else {
e18eca43 893 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 894 /* enable PLL when it is used */
9c173d15
AL		 895 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
896 PLL_ENABLE, PLL_ENABLE);
06c71282 897 }
4f9c16cc
DM		 898
899 /* Route Left DAC to left channel input and
900 * right DAC to right channel input */
901 data = (LDAC2LCH | RDAC2RCH);
902 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
903 if (params_rate(params) >= 64000)
904 data |= DUAL_RATE_MODE;
e18eca43 905 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 906
907 /* codec sample rate select */
4f9c16cc
DM		 908 data = (fsref * 20) / params_rate(params);
909 if (params_rate(params) < 64000)
910 data /= 2;
911 data /= 5;
912 data -= 2;
44d0a879 913 data |= (data << 4);
e18eca43 914 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 915
4f9c16cc
DM		 916 if (bypass_pll)
917 return 0;
918
25985edc 919 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 920 * one wins the game. Try with d==0 first, next with d!=0.
921 * Constraints for j are according to the datasheet.
4f9c16cc 922 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 923 */
255173b4 924
4f9c16cc
DM		 925 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
926
927 for (r = 1; r <= 16; r++)
928 for (p = 1; p <= 8; p++) {
255173b4
PM		 929 for (j = 4; j <= 55; j++) {
930 /* This is actually 1000*((j+(d/10000))*r)/p
931 * The term had to be converted to get
932 * rid of the division by 10000; d = 0 here
933 */
5baf8315 934 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 935
936 /* Check whether this values get closer than
937 * the best ones we had before
938 */
5baf8315 939 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 940 abs(codec_clk - last_clk)) {
941 pll_j = j; pll_d = 0;
942 pll_r = r; pll_p = p;
5baf8315 943 last_clk = tmp_clk;
255173b4
PM		 944 }
945
946 /* Early exit for exact matches */
5baf8315 947 if (tmp_clk == codec_clk)
255173b4
PM		 948 goto found;
949 }
950 }
4f9c16cc 951
255173b4
PM		 952 /* try with d != 0 */
953 for (p = 1; p <= 8; p++) {
954 j = codec_clk * p / 1000;
4f9c16cc 955
255173b4
PM		 956 if (j < 4 || j > 11)
957 continue;
4f9c16cc 958
255173b4
PM		 959 /* do not use codec_clk here since we'd loose precision */
960 d = ((2048 * p * fsref) - j * aic3x->sysclk)
961 * 100 / (aic3x->sysclk/100);
4f9c16cc 962
255173b4 963 clk = (10000 * j + d) / (10 * p);
4f9c16cc 964
255173b4
PM		 965 /* check whether this values get closer than the best
966 * ones we had before */
967 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
968 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
969 last_clk = clk;
4f9c16cc
DM		 970 }
971
255173b4
PM		 972 /* Early exit for exact matches */
973 if (clk == codec_clk)
974 goto found;
975 }
976
4f9c16cc
DM		 977 if (last_clk == 0) {
978 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
979 return -EINVAL;
980 }
44d0a879 981
255173b4 982found:
c9fe573a 983 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
e18eca43
JN		 984 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
985 pll_r << PLLR_SHIFT);
986 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
987 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
988 (pll_d >> 6) << PLLD_MSB_SHIFT);
989 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
990 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 991
44d0a879
VB		 992 return 0;
993}
994
e550e17f 995static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 996{
997 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 998 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
999 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 1000
1001 if (mute) {
e18eca43
JN		 1002 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1003 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 1004 } else {
e18eca43
JN		 1005 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1006 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 1007 }
1008
1009 return 0;
1010}
1011
e550e17f 1012static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1013 int clk_id, unsigned int freq, int dir)
1014{
1015 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1016 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1017
a1f34af0
JP		 1018 /* set clock on MCLK or GPIO2 or BCLK */
1019 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1020 clk_id << PLLCLK_IN_SHIFT);
1021 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1022 clk_id << CLKDIV_IN_SHIFT);
1023
4f9c16cc
DM		 1024 aic3x->sysclk = freq;
1025 return 0;
44d0a879
VB		 1026}
1027
e550e17f 1028static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1029 unsigned int fmt)
1030{
1031 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1032 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 1033 u8 iface_areg, iface_breg;
a24f4f68 1034 int delay = 0;
81971a14 1035
e18eca43
JN		 1036 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1037 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1038
1039 /* set master/slave audio interface */
1040 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1041 case SND_SOC_DAIFMT_CBM_CFM:
1042 aic3x->master = 1;
1043 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1044 break;
1045 case SND_SOC_DAIFMT_CBS_CFS:
1046 aic3x->master = 0;
68e47981 1047 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
44d0a879
VB		 1048 break;
1049 default:
1050 return -EINVAL;
1051 }
1052
4b7d2831
JN		 1053 /*
1054 * match both interface format and signal polarities since they
1055 * are fixed
1056 */
1057 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1058 SND_SOC_DAIFMT_INV_MASK)) {
1059 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1060 break;
a24f4f68
TK		 1061 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1062 delay = 1;
4b7d2831 1063 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1064 iface_breg |= (0x01 << 6);
1065 break;
4b7d2831 1066 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1067 iface_breg |= (0x02 << 6);
1068 break;
4b7d2831 1069 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1070 iface_breg |= (0x03 << 6);
1071 break;
1072 default:
1073 return -EINVAL;
1074 }
1075
1076 /* set iface */
e18eca43
JN		 1077 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1078 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1079 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1080
1081 return 0;
1082}
1083
5a895f8a
JN		 1084static int aic3x_regulator_event(struct notifier_block *nb,
1085 unsigned long event, void *data)
1086{
1087 struct aic3x_disable_nb *disable_nb =
1088 container_of(nb, struct aic3x_disable_nb, nb);
1089 struct aic3x_priv *aic3x = disable_nb->aic3x;
1090
1091 if (event & REGULATOR_EVENT_DISABLE) {
1092 /*
1093 * Put codec to reset and require cache sync as at least one
1094 * of the supplies was disabled
1095 */
79ee820d 1096 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a 1097 gpio_set_value(aic3x->gpio_reset, 0);
2a6fedec 1098 regcache_mark_dirty(aic3x->regmap);
5a895f8a
JN		 1099 }
1100
1101 return 0;
1102}
1103
6c1a7d40
JN		 1104static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1105{
1106 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2a6fedec 1107 int ret;
6c1a7d40
JN		 1108
1109 if (power) {
1110 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1111 aic3x->supplies);
1112 if (ret)
1113 goto out;
1114 aic3x->power = 1;
5a895f8a 1115
79ee820d 1116 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1117 udelay(1);
1118 gpio_set_value(aic3x->gpio_reset, 1);
1119 }
1120
1121 /* Sync reg_cache with the hardware */
2a6fedec
MB		 1122 regcache_cache_only(aic3x->regmap, false);
1123 regcache_sync(aic3x->regmap);
6c1a7d40 1124 } else {
9fb352b1
JN		 1125 /*
1126 * Do soft reset to this codec instance in order to clear
1127 * possible VDD leakage currents in case the supply regulators
1128 * remain on
1129 */
1130 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
2a6fedec 1131 regcache_mark_dirty(aic3x->regmap);
6c1a7d40 1132 aic3x->power = 0;
5a895f8a 1133 /* HW writes are needless when bias is off */
2a6fedec 1134 regcache_cache_only(aic3x->regmap, true);
6c1a7d40
JN		 1135 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1136 aic3x->supplies);
1137 }
1138out:
1139 return ret;
1140}
1141
0be9898a
MB		 1142static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1143 enum snd_soc_bias_level level)
44d0a879 1144{
b2c812e2 1145 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1146
0be9898a
MB		 1147 switch (level) {
1148 case SND_SOC_BIAS_ON:
db13802e
JN		 1149 break;
1150 case SND_SOC_BIAS_PREPARE:
ce6120cc 1151 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1152 aic3x->master) {
44d0a879 1153 /* enable pll */
9c173d15
AL		 1154 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1155 PLL_ENABLE, PLL_ENABLE);
44d0a879
VB		 1156 }
1157 break;
0be9898a 1158 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1159 if (!aic3x->power)
1160 aic3x_set_power(codec, 1);
ce6120cc 1161 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1162 aic3x->master) {
44d0a879 1163 /* disable pll */
9c173d15
AL		 1164 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1165 PLL_ENABLE, 0);
44d0a879
VB		 1166 }
1167 break;
c23fd751 1168 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1169 if (aic3x->power)
1170 aic3x_set_power(codec, 0);
c23fd751 1171 break;
44d0a879 1172 }
ce6120cc 1173 codec->dapm.bias_level = level;
44d0a879
VB		 1174
1175 return 0;
1176}
1177
1178#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1179#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1180 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1181
85e7652d 1182static const struct snd_soc_dai_ops aic3x_dai_ops = {
6335d055
EM		 1183 .hw_params = aic3x_hw_params,
1184 .digital_mute = aic3x_mute,
1185 .set_sysclk = aic3x_set_dai_sysclk,
1186 .set_fmt = aic3x_set_dai_fmt,
1187};
1188
f0fba2ad
LG		 1189static struct snd_soc_dai_driver aic3x_dai = {
1190 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1191 .playback = {
1192 .stream_name = "Playback",
06378da4 1193 .channels_min = 2,
44d0a879
VB		 1194 .channels_max = 2,
1195 .rates = AIC3X_RATES,
1196 .formats = AIC3X_FORMATS,},
1197 .capture = {
1198 .stream_name = "Capture",
06378da4 1199 .channels_min = 2,
44d0a879
VB		 1200 .channels_max = 2,
1201 .rates = AIC3X_RATES,
1202 .formats = AIC3X_FORMATS,},
6335d055 1203 .ops = &aic3x_dai_ops,
14017615 1204 .symmetric_rates = 1,
44d0a879 1205};
44d0a879 1206
84b315ee 1207static int aic3x_suspend(struct snd_soc_codec *codec)
44d0a879 1208{
0be9898a 1209 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1210
1211 return 0;
1212}
1213
f0fba2ad 1214static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1215{
29e189c2 1216 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1217
1218 return 0;
1219}
1220
1221/*
1222 * initialise the AIC3X driver
1223 * register the mixer and dsp interfaces with the kernel
1224 */
cb3826f5 1225static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1226{
6184f105 1227 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5 1228
e18eca43
JN		 1229 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1230 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1231
44d0a879 1232 /* DAC default volume and mute */
e18eca43
JN		 1233 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1234 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1235
1236 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1237 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1238 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1239 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1240 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1241 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1242 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1243 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1244 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1245 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1246 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1247
1248 /* unmute all outputs */
9c173d15
AL		 1249 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1250 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1251 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1252 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1253 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1254 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1255 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
44d0a879
VB		 1256
1257 /* ADC default volume and unmute */
e18eca43
JN		 1258 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1259 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1260 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1261 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1262 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1263
1264 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1265 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1266 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1267 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1268 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1269 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1270 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1271 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1272 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1273 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1274 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1275
1276 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1277 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1278 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1279 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1280 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1281 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1282 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1283 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1284 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1285 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1286 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1287
6184f105 1288 if (aic3x->model == AIC3X_MODEL_3007) {
e18eca43 1289 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1290 }
1291
cb3826f5
BD		 1292 return 0;
1293}
54e7e616 1294
414c73ab
JN		 1295static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1296{
1297 struct aic3x_priv *a;
1298
1299 list_for_each_entry(a, &reset_list, list) {
1300 if (gpio_is_valid(aic3x->gpio_reset) &&
1301 aic3x->gpio_reset == a->gpio_reset)
1302 return true;
1303 }
1304
1305 return false;
1306}
1307
f0fba2ad 1308static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1309{
f0fba2ad 1310 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1311 int ret, i;
f0fba2ad 1312
414c73ab 1313 INIT_LIST_HEAD(&aic3x->list);
5a895f8a 1314 aic3x->codec = codec;
cb3826f5 1315
2a6fedec 1316 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
a84a441b
JN		 1317 if (ret != 0) {
1318 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1319 return ret;
1320 }
1321
5a895f8a
JN		 1322 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1323 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1324 aic3x->disable_nb[i].aic3x = aic3x;
1325 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1326 &aic3x->disable_nb[i].nb);
1327 if (ret) {
1328 dev_err(codec->dev,
1329 "Failed to request regulator notifier: %d\n",
1330 ret);
1331 goto err_notif;
1332 }
1333 }
2f24111a 1334
2a6fedec 1335 regcache_mark_dirty(aic3x->regmap);
37b47656
JN		 1336 aic3x_init(codec);
1337
f0fba2ad
LG		 1338 if (aic3x->setup) {
1339 /* setup GPIO functions */
e18eca43
JN		 1340 snd_soc_write(codec, AIC3X_GPIO1_REG,
1341 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1342 snd_soc_write(codec, AIC3X_GPIO2_REG,
1343 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1344 }
1345
6184f105 1346 if (aic3x->model == AIC3X_MODEL_3007)
022658be 1347 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1348
e2e8bfdf
HG		 1349 /* set mic bias voltage */
1350 switch (aic3x->micbias_vg) {
1351 case AIC3X_MICBIAS_2_0V:
1352 case AIC3X_MICBIAS_2_5V:
1353 case AIC3X_MICBIAS_AVDDV:
1354 snd_soc_update_bits(codec, MICBIAS_CTRL,
1355 MICBIAS_LEVEL_MASK,
1356 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1357 break;
1358 case AIC3X_MICBIAS_OFF:
1359 /*
1360 * noting to do. target won't enter here. This is just to avoid
1361 * compile time warning "warning: enumeration value
1362 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1363 */
1364 break;
1365 }
1366
f0fba2ad 1367 aic3x_add_widgets(codec);
414c73ab 1368 list_add(&aic3x->list, &reset_list);
cb3826f5
BD		 1369
1370 return 0;
2f24111a 1371
5a895f8a
JN		 1372err_notif:
1373 while (i--)
1374 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1375 &aic3x->disable_nb[i].nb);
2f24111a 1376 return ret;
44d0a879
VB		 1377}
1378
f0fba2ad 1379static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1380{
2f24111a 1381 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1382 int i;
2f24111a 1383
f0fba2ad 1384 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
414c73ab 1385 list_del(&aic3x->list);
5a895f8a
JN		 1386 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1387 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1388 &aic3x->disable_nb[i].nb);
2f24111a 1389
cb3826f5
BD		 1390 return 0;
1391}
44d0a879 1392
f0fba2ad 1393static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad 1394 .set_bias_level = aic3x_set_bias_level,
eb3032f8 1395 .idle_bias_off = true,
f0fba2ad
LG		 1396 .probe = aic3x_probe,
1397 .remove = aic3x_remove,
1398 .suspend = aic3x_suspend,
1399 .resume = aic3x_resume,
f9df1ae6
MB		 1400 .controls = aic3x_snd_controls,
1401 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
58a63fbd
MB		 1402 .dapm_widgets = aic3x_dapm_widgets,
1403 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1404 .dapm_routes = intercon,
1405 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 1406};
1407
44d0a879
VB		 1408/*
1409 * AIC3X 2 wire address can be up to 4 devices with device addresses
1410 * 0x18, 0x19, 0x1A, 0x1B
1411 */
44d0a879 1412
6184f105 1413static const struct i2c_device_id aic3x_i2c_id[] = {
177fdd89
AL		 1414 { "tlv320aic3x", AIC3X_MODEL_3X },
1415 { "tlv320aic33", AIC3X_MODEL_33 },
1416 { "tlv320aic3007", AIC3X_MODEL_3007 },
cbaa5689 1417 { "tlv320aic3106", AIC3X_MODEL_3X },
6184f105
RC		 1418 { }
1419};
1420MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1421
2a6fedec
MB		 1422static const struct reg_default aic3007_class_d[] = {
1423 /* Class-D speaker driver init; datasheet p. 46 */
1424 { AIC3X_PAGE_SELECT, 0x0D },
1425 { 0xD, 0x0D },
1426 { 0x8, 0x5C },
1427 { 0x8, 0x5D },
1428 { 0x8, 0x5C },
1429 { AIC3X_PAGE_SELECT, 0x00 },
1430};
1431
44d0a879
VB		 1432/*
1433 * If the i2c layer weren't so broken, we could pass this kind of data
1434 * around
1435 */
ba8ed121
JD		 1436static int aic3x_i2c_probe(struct i2c_client *i2c,
1437 const struct i2c_device_id *id)
44d0a879 1438{
5193d62f 1439 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1440 struct aic3x_priv *aic3x;
c24fdc88
HG		 1441 struct aic3x_setup_data *ai3x_setup;
1442 struct device_node *np = i2c->dev.of_node;
6f818e04 1443 int ret, i;
e2e8bfdf 1444 u32 value;
44d0a879 1445
e2257db3 1446 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
cb3826f5
BD		 1447 if (aic3x == NULL) {
1448 dev_err(&i2c->dev, "failed to create private data\n");
1449 return -ENOMEM;
1450 }
1451
2a6fedec
MB		 1452 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1453 if (IS_ERR(aic3x->regmap)) {
1454 ret = PTR_ERR(aic3x->regmap);
1455 return ret;
1456 }
1457
1458 regcache_cache_only(aic3x->regmap, true);
a84a441b 1459
cb3826f5 1460 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1461 if (pdata) {
1462 aic3x->gpio_reset = pdata->gpio_reset;
1463 aic3x->setup = pdata->setup;
e2e8bfdf 1464 aic3x->micbias_vg = pdata->micbias_vg;
c24fdc88
HG		 1465 } else if (np) {
1466 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1467 GFP_KERNEL);
1468 if (ai3x_setup == NULL) {
1469 dev_err(&i2c->dev, "failed to create private data\n");
1470 return -ENOMEM;
1471 }
1472
1473 ret = of_get_named_gpio(np, "gpio-reset", 0);
1474 if (ret >= 0)
1475 aic3x->gpio_reset = ret;
1476 else
1477 aic3x->gpio_reset = -1;
1478
1479 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1480 ai3x_setup->gpio_func, 2) >= 0) {
1481 aic3x->setup = ai3x_setup;
1482 }
1483
e2e8bfdf
HG		 1484 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1485 switch (value) {
1486 case 1 :
1487 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1488 break;
1489 case 2 :
1490 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1491 break;
1492 case 3 :
1493 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1494 break;
1495 default :
1496 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1497 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1498 "found in DT\n");
1499 }
1500 } else {
1501 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1502 }
1503
c776357e
JN		 1504 } else {
1505 aic3x->gpio_reset = -1;
1506 }
cb3826f5 1507
177fdd89 1508 aic3x->model = id->driver_data;
6184f105 1509
6f818e04
MB		 1510 if (gpio_is_valid(aic3x->gpio_reset) &&
1511 !aic3x_is_shared_reset(aic3x)) {
1512 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1513 if (ret != 0)
1514 goto err;
1515 gpio_direction_output(aic3x->gpio_reset, 0);
1516 }
1517
1518 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1519 aic3x->supplies[i].supply = aic3x_supply_names[i];
1520
1521 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1522 aic3x->supplies);
1523 if (ret != 0) {
1524 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1525 goto err_gpio;
1526 }
1527
2a6fedec
MB		 1528 if (aic3x->model == AIC3X_MODEL_3007) {
1529 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1530 ARRAY_SIZE(aic3007_class_d));
1531 if (ret != 0)
1532 dev_err(&i2c->dev, "Failed to init class D: %d\n",
1533 ret);
1534 }
1535
f0fba2ad
LG		 1536 ret = snd_soc_register_codec(&i2c->dev,
1537 &soc_codec_dev_aic3x, &aic3x_dai, 1);
07779fdd 1538 return ret;
6f818e04
MB		 1539
1540err_gpio:
1541 if (gpio_is_valid(aic3x->gpio_reset) &&
1542 !aic3x_is_shared_reset(aic3x))
1543 gpio_free(aic3x->gpio_reset);
1544err:
1545 return ret;
44d0a879
VB		 1546}
1547
ba8ed121 1548static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1549{
6f818e04
MB		 1550 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1551
f0fba2ad 1552 snd_soc_unregister_codec(&client->dev);
6f818e04
MB		 1553 if (gpio_is_valid(aic3x->gpio_reset) &&
1554 !aic3x_is_shared_reset(aic3x)) {
1555 gpio_set_value(aic3x->gpio_reset, 0);
1556 gpio_free(aic3x->gpio_reset);
1557 }
f0fba2ad 1558 return 0;
44d0a879
VB		 1559}
1560
c24fdc88
HG		 1561#if defined(CONFIG_OF)
1562static const struct of_device_id tlv320aic3x_of_match[] = {
1563 { .compatible = "ti,tlv320aic3x", },
f2c4fa65
MB		 1564 { .compatible = "ti,tlv320aic33" },
1565 { .compatible = "ti,tlv320aic3007" },
cbaa5689 1566 { .compatible = "ti,tlv320aic3106" },
c24fdc88
HG		 1567 {},
1568};
1569MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1570#endif
1571
44d0a879
VB		 1572/* machine i2c codec control layer */
1573static struct i2c_driver aic3x_i2c_driver = {
1574 .driver = {
f0fba2ad 1575 .name = "tlv320aic3x-codec",
44d0a879 1576 .owner = THIS_MODULE,
c24fdc88 1577 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
44d0a879 1578 },
cb3826f5 1579 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1580 .remove = aic3x_i2c_remove,
1581 .id_table = aic3x_i2c_id,
44d0a879 1582};
44d0a879 1583
fd39d14b 1584module_i2c_driver(aic3x_i2c_driver);
64089b84 1585
44d0a879
VB		 1586MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1587MODULE_AUTHOR("Vladimir Barinov");
1588MODULE_LICENSE("GPL");
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