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ASoC: tlv320aic3x: Don't reference cache datastructure directly
[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
c24fdc88 43#include <linux/of_gpio.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
44d0a879 49#include <sound/initval.h>
7565fc38 50#include <sound/tlv.h>
5193d62f 51#include <sound/tlv320aic3x.h>
44d0a879
VB		 52
53#include "tlv320aic3x.h"
54
07779fdd
JN		 55#define AIC3X_NUM_SUPPLIES 4
56static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD", /* I/O Voltage */
58 "DVDD", /* Digital Core Voltage */
59 "AVDD", /* Analog DAC Voltage */
60 "DRVDD", /* ADC Analog and Output Driver Voltage */
61};
44d0a879 62
414c73ab
JN		 63static LIST_HEAD(reset_list);
64
5a895f8a
JN		 65struct aic3x_priv;
66
67struct aic3x_disable_nb {
68 struct notifier_block nb;
69 struct aic3x_priv *aic3x;
70};
71
44d0a879
VB		 72/* codec private data */
73struct aic3x_priv {
5a895f8a 74 struct snd_soc_codec *codec;
07779fdd 75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 77 enum snd_soc_control_type control_type;
78 struct aic3x_setup_data *setup;
44d0a879 79 unsigned int sysclk;
414c73ab 80 struct list_head list;
44d0a879 81 int master;
5193d62f 82 int gpio_reset;
6c1a7d40 83 int power;
6184f105
RC		 84#define AIC3X_MODEL_3X 0
85#define AIC3X_MODEL_33 1
86#define AIC3X_MODEL_3007 2
87 u16 model;
e2e8bfdf
HG		 88
89 /* Selects the micbias voltage */
90 enum aic3x_micbias_voltage micbias_vg;
44d0a879
VB		 91};
92
44d0a879
VB		 93static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
94 0x00, 0x00, 0x00, 0x10, /* 0 */
95 0x04, 0x00, 0x00, 0x00, /* 4 */
96 0x00, 0x00, 0x00, 0x01, /* 8 */
97 0x00, 0x00, 0x00, 0x80, /* 12 */
98 0x80, 0xff, 0xff, 0x78, /* 16 */
99 0x78, 0x78, 0x78, 0x78, /* 20 */
100 0x78, 0x00, 0x00, 0xfe, /* 24 */
101 0x00, 0x00, 0xfe, 0x00, /* 28 */
102 0x18, 0x18, 0x00, 0x00, /* 32 */
103 0x00, 0x00, 0x00, 0x00, /* 36 */
104 0x00, 0x00, 0x00, 0x80, /* 40 */
105 0x80, 0x00, 0x00, 0x00, /* 44 */
106 0x00, 0x00, 0x00, 0x04, /* 48 */
107 0x00, 0x00, 0x00, 0x00, /* 52 */
108 0x00, 0x00, 0x04, 0x00, /* 56 */
109 0x00, 0x00, 0x00, 0x00, /* 60 */
110 0x00, 0x04, 0x00, 0x00, /* 64 */
111 0x00, 0x00, 0x00, 0x00, /* 68 */
112 0x04, 0x00, 0x00, 0x00, /* 72 */
113 0x00, 0x00, 0x00, 0x00, /* 76 */
114 0x00, 0x00, 0x00, 0x00, /* 80 */
115 0x00, 0x00, 0x00, 0x00, /* 84 */
116 0x00, 0x00, 0x00, 0x00, /* 88 */
117 0x00, 0x00, 0x00, 0x00, /* 92 */
118 0x00, 0x00, 0x00, 0x00, /* 96 */
c9e8e8d2
JP		 119 0x00, 0x00, 0x02, 0x00, /* 100 */
120 0x00, 0x00, 0x00, 0x00, /* 104 */
121 0x00, 0x00, /* 108 */
44d0a879
VB		 122};
123
44d0a879 124#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
1476f66f
LPC		 125 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
126 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
44d0a879
VB		 127
128/*
129 * All input lines are connected when !0xf and disconnected with 0xf bit field,
130 * so we have to use specific dapm_put call for input mixer
131 */
132static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
133 struct snd_ctl_elem_value *ucontrol)
134{
eee5d7f9 135 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
4453dba5
EN		 136 struct soc_mixer_control *mc =
137 (struct soc_mixer_control *)kcontrol->private_value;
138 unsigned int reg = mc->reg;
139 unsigned int shift = mc->shift;
140 int max = mc->max;
141 unsigned int mask = (1 << fls(max)) - 1;
142 unsigned int invert = mc->invert;
5d99d778
LPC		 143 unsigned short val;
144 struct snd_soc_dapm_update update;
145 int connect, change;
44d0a879
VB		 146
147 val = (ucontrol->value.integer.value[0] & mask);
148
149 mask = 0xf;
150 if (val)
151 val = mask;
152
5d99d778
LPC		 153 connect = !!val;
154
44d0a879
VB		 155 if (invert)
156 val = mask - val;
44d0a879 157
5d99d778
LPC		 158 mask <<= shift;
159 val <<= shift;
2894770e 160
eee5d7f9 161 change = snd_soc_test_bits(codec, val, mask, reg);
5d99d778
LPC		 162 if (change) {
163 update.kcontrol = kcontrol;
164 update.reg = reg;
165 update.mask = mask;
166 update.val = val;
167
eee5d7f9 168 snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect,
5d99d778
LPC		 169 &update);
170 }
2894770e 171
5d99d778 172 return change;
44d0a879
VB		 173}
174
e2e8bfdf
HG		 175/*
176 * mic bias power on/off share the same register bits with
177 * output voltage of mic bias. when power on mic bias, we
178 * need reclaim it to voltage value.
179 * 0x0 = Powered off
180 * 0x1 = MICBIAS output is powered to 2.0V,
181 * 0x2 = MICBIAS output is powered to 2.5V
182 * 0x3 = MICBIAS output is connected to AVDD
183 */
184static int mic_bias_event(struct snd_soc_dapm_widget *w,
185 struct snd_kcontrol *kcontrol, int event)
186{
187 struct snd_soc_codec *codec = w->codec;
188 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
189
190 switch (event) {
191 case SND_SOC_DAPM_POST_PMU:
192 /* change mic bias voltage to user defined */
193 snd_soc_update_bits(codec, MICBIAS_CTRL,
194 MICBIAS_LEVEL_MASK,
195 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
196 break;
197
198 case SND_SOC_DAPM_PRE_PMD:
199 snd_soc_update_bits(codec, MICBIAS_CTRL,
200 MICBIAS_LEVEL_MASK, 0);
201 break;
202 }
203 return 0;
204}
205
44d0a879
VB		 206static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
207static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
208static const char *aic3x_left_hpcom_mux[] =
209 { "differential of HPLOUT", "constant VCM", "single-ended" };
210static const char *aic3x_right_hpcom_mux[] =
211 { "differential of HPROUT", "constant VCM", "single-ended",
212 "differential of HPLCOM", "external feedback" };
213static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 214static const char *aic3x_adc_hpf[] =
215 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 216
217#define LDAC_ENUM 0
218#define RDAC_ENUM 1
219#define LHPCOM_ENUM 2
220#define RHPCOM_ENUM 3
404b5665
JN		 221#define LINE1L_2_L_ENUM 4
222#define LINE1L_2_R_ENUM 5
223#define LINE1R_2_L_ENUM 6
224#define LINE1R_2_R_ENUM 7
225#define LINE2L_ENUM 8
226#define LINE2R_ENUM 9
227#define ADC_HPF_ENUM 10
44d0a879
VB		 228
229static const struct soc_enum aic3x_enum[] = {
230 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
231 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
232 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
233 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
234 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
404b5665
JN		 235 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
236 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
44d0a879
VB		 237 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
238 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
239 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 240 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 241};
242
bb1daa80
JP		 243static const char *aic3x_agc_level[] =
244 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" };
245static const struct soc_enum aic3x_agc_level_enum[] = {
246 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level),
247 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level),
248};
249
250static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" };
251static const struct soc_enum aic3x_agc_attack_enum[] = {
252 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack),
253 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack),
254};
255
256static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" };
257static const struct soc_enum aic3x_agc_decay_enum[] = {
258 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay),
259 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay),
260};
261
7565fc38
JN		 262/*
263 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
264 */
265static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
266/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
267static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
268/*
269 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
270 * Step size is approximately 0.5 dB over most of the scale but increasing
271 * near the very low levels.
272 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
273 * but having increasing dB difference below that (and where it doesn't count
274 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
275 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
276 */
277static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
278
44d0a879
VB		 279static const struct snd_kcontrol_new aic3x_snd_controls[] = {
280 /* Output */
7565fc38
JN		 281 SOC_DOUBLE_R_TLV("PCM Playback Volume",
282 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 283
098b1718
JN		 284 /*
285 * Output controls that map to output mixer switches. Note these are
286 * only for swapped L-to-R and R-to-L routes. See below stereo controls
287 * for direct L-to-L and R-to-R routes.
288 */
289 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
290 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
291 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
292 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
293 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
294 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
295
296 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
297 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
299 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
300 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
301 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
302
303 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
304 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
305 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
306 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
307 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
308 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
309
310 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
311 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
312 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
313 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
314 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
315 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
316
317 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
318 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
319 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
320 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
321 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
322 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
323
324 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
325 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
326 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
327 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
328 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
329 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
330
331 /* Stereo output controls for direct L-to-L and R-to-R routes */
332 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
333 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
334 0, 118, 1, output_stage_tlv),
335 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
336 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
337 0, 118, 1, output_stage_tlv),
7565fc38
JN		 338 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
339 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
340 0, 118, 1, output_stage_tlv),
098b1718
JN		 341
342 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
343 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 344 0, 118, 1, output_stage_tlv),
098b1718
JN		 345 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
346 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 347 0, 118, 1, output_stage_tlv),
7565fc38
JN		 348 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
349 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
350 0, 118, 1, output_stage_tlv),
098b1718
JN		 351
352 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
353 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 354 0, 118, 1, output_stage_tlv),
098b1718
JN		 355 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
356 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 357 0, 118, 1, output_stage_tlv),
7565fc38
JN		 358 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
359 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
360 0, 118, 1, output_stage_tlv),
098b1718
JN		 361
362 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
363 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 364 0, 118, 1, output_stage_tlv),
098b1718
JN		 365 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
366 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 367 0, 118, 1, output_stage_tlv),
7565fc38
JN		 368 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
369 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
370 0, 118, 1, output_stage_tlv),
098b1718
JN		 371
372 /* Output pin mute controls */
373 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
374 0x01, 0),
375 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
376 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
377 0x01, 0),
f9bc0297 378 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 379 0x01, 0),
44d0a879
VB		 380
381 /*
382 * Note: enable Automatic input Gain Controller with care. It can
383 * adjust PGA to max value when ADC is on and will never go back.
384 */
385 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
bb1daa80
JP		 386 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]),
387 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]),
388 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]),
389 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]),
390 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]),
391 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]),
44d0a879 392
77444191
JP		 393 /* De-emphasis */
394 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
44d0a879
VB		 395
396 /* Input */
7565fc38
JN		 397 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
398 0, 119, 0, adc_tlv),
44d0a879 399 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 400
401 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 402};
403
6184f105
RC		 404/*
405 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
406 */
407static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
408
409static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
14a95fe8 410 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
6184f105 411
44d0a879
VB		 412/* Left DAC Mux */
413static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
414SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
415
416/* Right DAC Mux */
417static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
418SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
419
420/* Left HPCOM Mux */
421static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
422SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
423
424/* Right HPCOM Mux */
425static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
426SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
427
c3b79e05
JN		 428/* Left Line Mixer */
429static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
430 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
431 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 436};
437
c3b79e05
JN		 438/* Right Line Mixer */
439static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
440 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
441 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
442 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
446};
447
448/* Mono Mixer */
449static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
450 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
456};
457
458/* Left HP Mixer */
459static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
460 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
462 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
463 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
464 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
466};
467
468/* Right HP Mixer */
469static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
470 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
472 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
473 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
474 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
475 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
476};
477
478/* Left HPCOM Mixer */
479static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
480 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
481 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
482 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
483 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
484 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
485 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
486};
487
488/* Right HPCOM Mixer */
489static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
490 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
491 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
492 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
493 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
494 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
495 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 496};
497
498/* Left PGA Mixer */
499static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
500 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 501 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 502 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
503 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 504 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 505};
506
507/* Right PGA Mixer */
508static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
509 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 510 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 511 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 512 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
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VB		 513 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
514};
515
516/* Left Line1 Mux */
404b5665
JN		 517static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
518SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
519static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
520SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
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VB		 521
522/* Right Line1 Mux */
404b5665
JN		 523static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
524SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
525static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
526SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
44d0a879
VB		 527
528/* Left Line2 Mux */
529static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
530SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
531
532/* Right Line2 Mux */
533static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
534SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
535
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VB		 536static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
537 /* Left DAC to Left Outputs */
538 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
539 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
540 &aic3x_left_dac_mux_controls),
44d0a879
VB		 541 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
542 &aic3x_left_hpcom_mux_controls),
543 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
544 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
545 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
546
547 /* Right DAC to Right Outputs */
548 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
549 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
550 &aic3x_right_dac_mux_controls),
44d0a879
VB		 551 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
552 &aic3x_right_hpcom_mux_controls),
553 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
554 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
555 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
556
557 /* Mono Output */
558 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
559
54f01916 560 /* Inputs to Left ADC */
44d0a879
VB		 561 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
562 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
563 &aic3x_left_pga_mixer_controls[0],
564 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
565 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 566 &aic3x_left_line1l_mux_controls),
54f01916 567 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 568 &aic3x_left_line1r_mux_controls),
44d0a879
VB		 569 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
570 &aic3x_left_line2_mux_controls),
571
54f01916 572 /* Inputs to Right ADC */
44d0a879
VB		 573 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
574 LINE1R_2_RADC_CTRL, 2, 0),
575 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
576 &aic3x_right_pga_mixer_controls[0],
577 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916 578 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 579 &aic3x_right_line1l_mux_controls),
44d0a879 580 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 581 &aic3x_right_line1r_mux_controls),
44d0a879
VB		 582 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
583 &aic3x_right_line2_mux_controls),
584
ee15ffdb
JN		 585 /*
586 * Not a real mic bias widget but similar function. This is for dynamic
587 * control of GPIO1 digital mic modulator clock output function when
588 * using digital mic.
589 */
590 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
591 AIC3X_GPIO1_REG, 4, 0xf,
592 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
593 AIC3X_GPIO1_FUNC_DISABLED),
594
595 /*
596 * Also similar function like mic bias. Selects digital mic with
597 * configurable oversampling rate instead of ADC converter.
598 */
599 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
600 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
601 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
602 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
603 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
604 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
605
44d0a879 606 /* Mic Bias */
e2e8bfdf
HG		 607 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
608 mic_bias_event,
609 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
44d0a879 610
c3b79e05
JN		 611 /* Output mixers */
612 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
613 &aic3x_left_line_mixer_controls[0],
614 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
615 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
616 &aic3x_right_line_mixer_controls[0],
617 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
618 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
619 &aic3x_mono_mixer_controls[0],
620 ARRAY_SIZE(aic3x_mono_mixer_controls)),
621 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
622 &aic3x_left_hp_mixer_controls[0],
623 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
624 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
625 &aic3x_right_hp_mixer_controls[0],
626 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
627 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
628 &aic3x_left_hpcom_mixer_controls[0],
629 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
630 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
631 &aic3x_right_hpcom_mixer_controls[0],
632 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 633
634 SND_SOC_DAPM_OUTPUT("LLOUT"),
635 SND_SOC_DAPM_OUTPUT("RLOUT"),
636 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
637 SND_SOC_DAPM_OUTPUT("HPLOUT"),
638 SND_SOC_DAPM_OUTPUT("HPROUT"),
639 SND_SOC_DAPM_OUTPUT("HPLCOM"),
640 SND_SOC_DAPM_OUTPUT("HPRCOM"),
641
642 SND_SOC_DAPM_INPUT("MIC3L"),
643 SND_SOC_DAPM_INPUT("MIC3R"),
644 SND_SOC_DAPM_INPUT("LINE1L"),
645 SND_SOC_DAPM_INPUT("LINE1R"),
646 SND_SOC_DAPM_INPUT("LINE2L"),
647 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 648
649 /*
650 * Virtual output pin to detection block inside codec. This can be
651 * used to keep codec bias on if gpio or detection features are needed.
652 * Force pin on or construct a path with an input jack and mic bias
653 * widgets.
654 */
655 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 656};
657
6184f105
RC		 658static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
659 /* Class-D outputs */
660 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
661 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
662
663 SND_SOC_DAPM_OUTPUT("SPOP"),
664 SND_SOC_DAPM_OUTPUT("SPOM"),
665};
666
d0cc0d3a 667static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 668 /* Left Input */
669 {"Left Line1L Mux", "single-ended", "LINE1L"},
670 {"Left Line1L Mux", "differential", "LINE1L"},
671
672 {"Left Line2L Mux", "single-ended", "LINE2L"},
673 {"Left Line2L Mux", "differential", "LINE2L"},
674
675 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 676 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 677 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
678 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 679 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 680
681 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 682 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 683
684 /* Right Input */
685 {"Right Line1R Mux", "single-ended", "LINE1R"},
686 {"Right Line1R Mux", "differential", "LINE1R"},
687
688 {"Right Line2R Mux", "single-ended", "LINE2R"},
689 {"Right Line2R Mux", "differential", "LINE2R"},
690
54f01916 691 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 692 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
693 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 694 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 695 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
696
697 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 698 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 699
ee15ffdb
JN		 700 /*
701 * Logical path between digital mic enable and GPIO1 modulator clock
702 * output function
703 */
704 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
705 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
706 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 707
708 /* Left DAC Output */
709 {"Left DAC Mux", "DAC_L1", "Left DAC"},
710 {"Left DAC Mux", "DAC_L2", "Left DAC"},
711 {"Left DAC Mux", "DAC_L3", "Left DAC"},
712
713 /* Right DAC Output */
714 {"Right DAC Mux", "DAC_R1", "Right DAC"},
715 {"Right DAC Mux", "DAC_R2", "Right DAC"},
716 {"Right DAC Mux", "DAC_R3", "Right DAC"},
717
718 /* Left Line Output */
719 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
720 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
721 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
722 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
723 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
724 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
725
726 {"Left Line Out", NULL, "Left Line Mixer"},
727 {"Left Line Out", NULL, "Left DAC Mux"},
728 {"LLOUT", NULL, "Left Line Out"},
729
730 /* Right Line Output */
731 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
732 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
733 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
734 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
735 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
736 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
737
738 {"Right Line Out", NULL, "Right Line Mixer"},
739 {"Right Line Out", NULL, "Right DAC Mux"},
740 {"RLOUT", NULL, "Right Line Out"},
741
742 /* Mono Output */
743 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
744 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
745 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
746 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
747 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
748 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
749
750 {"Mono Out", NULL, "Mono Mixer"},
751 {"MONO_LOUT", NULL, "Mono Out"},
752
753 /* Left HP Output */
754 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
755 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
756 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
757 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
758 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
759 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
760
761 {"Left HP Out", NULL, "Left HP Mixer"},
762 {"Left HP Out", NULL, "Left DAC Mux"},
763 {"HPLOUT", NULL, "Left HP Out"},
764
765 /* Right HP Output */
766 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
767 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
768 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
769 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
770 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
771 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
772
773 {"Right HP Out", NULL, "Right HP Mixer"},
774 {"Right HP Out", NULL, "Right DAC Mux"},
775 {"HPROUT", NULL, "Right HP Out"},
776
777 /* Left HPCOM Output */
778 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
779 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
780 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
781 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
782 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
783 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
784
785 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
786 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
787 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
788 {"Left HP Com", NULL, "Left HPCOM Mux"},
789 {"HPLCOM", NULL, "Left HP Com"},
790
791 /* Right HPCOM Output */
792 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
793 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
794 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
795 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
796 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
797 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
798
799 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
800 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
801 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
802 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
803 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
804 {"Right HP Com", NULL, "Right HPCOM Mux"},
805 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 806};
807
6184f105
RC		 808static const struct snd_soc_dapm_route intercon_3007[] = {
809 /* Class-D outputs */
810 {"Left Class-D Out", NULL, "Left Line Out"},
811 {"Right Class-D Out", NULL, "Left Line Out"},
812 {"SPOP", NULL, "Left Class-D Out"},
813 {"SPOM", NULL, "Right Class-D Out"},
814};
815
44d0a879
VB		 816static int aic3x_add_widgets(struct snd_soc_codec *codec)
817{
6184f105 818 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 819 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 820
6184f105 821 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 822 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 823 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 824 snd_soc_dapm_add_routes(dapm, intercon_3007,
825 ARRAY_SIZE(intercon_3007));
6184f105
RC		 826 }
827
44d0a879
VB		 828 return 0;
829}
830
44d0a879 831static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 832 struct snd_pcm_hw_params *params,
833 struct snd_soc_dai *dai)
44d0a879 834{
e6968a17 835 struct snd_soc_codec *codec = dai->codec;
b2c812e2 836 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 837 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 838 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
839 u16 d, pll_d = 1;
255173b4 840 int clk;
44d0a879 841
4f9c16cc 842 /* select data word length */
e18eca43 843 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 844 switch (params_format(params)) {
845 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 846 break;
4f9c16cc
DM		 847 case SNDRV_PCM_FORMAT_S20_3LE:
848 data |= (0x01 << 4);
44d0a879 849 break;
4f9c16cc
DM		 850 case SNDRV_PCM_FORMAT_S24_LE:
851 data |= (0x02 << 4);
44d0a879 852 break;
4f9c16cc
DM		 853 case SNDRV_PCM_FORMAT_S32_LE:
854 data |= (0x03 << 4);
44d0a879
VB		 855 break;
856 }
e18eca43 857 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 858
859 /* Fsref can be 44100 or 48000 */
860 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
861
862 /* Try to find a value for Q which allows us to bypass the PLL and
863 * generate CODEC_CLK directly. */
864 for (pll_q = 2; pll_q < 18; pll_q++)
865 if (aic3x->sysclk / (128 * pll_q) == fsref) {
866 bypass_pll = 1;
867 break;
868 }
869
870 if (bypass_pll) {
871 pll_q &= 0xf;
e18eca43
JN		 872 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
873 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 874 /* disable PLL if it is bypassed */
9c173d15 875 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
06c71282
C		 876
877 } else {
e18eca43 878 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 879 /* enable PLL when it is used */
9c173d15
AL		 880 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
881 PLL_ENABLE, PLL_ENABLE);
06c71282 882 }
4f9c16cc
DM		 883
884 /* Route Left DAC to left channel input and
885 * right DAC to right channel input */
886 data = (LDAC2LCH | RDAC2RCH);
887 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
888 if (params_rate(params) >= 64000)
889 data |= DUAL_RATE_MODE;
e18eca43 890 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 891
892 /* codec sample rate select */
4f9c16cc
DM		 893 data = (fsref * 20) / params_rate(params);
894 if (params_rate(params) < 64000)
895 data /= 2;
896 data /= 5;
897 data -= 2;
44d0a879 898 data |= (data << 4);
e18eca43 899 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 900
4f9c16cc
DM		 901 if (bypass_pll)
902 return 0;
903
25985edc 904 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 905 * one wins the game. Try with d==0 first, next with d!=0.
906 * Constraints for j are according to the datasheet.
4f9c16cc 907 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 908 */
255173b4 909
4f9c16cc
DM		 910 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
911
912 for (r = 1; r <= 16; r++)
913 for (p = 1; p <= 8; p++) {
255173b4
PM		 914 for (j = 4; j <= 55; j++) {
915 /* This is actually 1000*((j+(d/10000))*r)/p
916 * The term had to be converted to get
917 * rid of the division by 10000; d = 0 here
918 */
5baf8315 919 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 920
921 /* Check whether this values get closer than
922 * the best ones we had before
923 */
5baf8315 924 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 925 abs(codec_clk - last_clk)) {
926 pll_j = j; pll_d = 0;
927 pll_r = r; pll_p = p;
5baf8315 928 last_clk = tmp_clk;
255173b4
PM		 929 }
930
931 /* Early exit for exact matches */
5baf8315 932 if (tmp_clk == codec_clk)
255173b4
PM		 933 goto found;
934 }
935 }
4f9c16cc 936
255173b4
PM		 937 /* try with d != 0 */
938 for (p = 1; p <= 8; p++) {
939 j = codec_clk * p / 1000;
4f9c16cc 940
255173b4
PM		 941 if (j < 4 || j > 11)
942 continue;
4f9c16cc 943
255173b4
PM		 944 /* do not use codec_clk here since we'd loose precision */
945 d = ((2048 * p * fsref) - j * aic3x->sysclk)
946 * 100 / (aic3x->sysclk/100);
4f9c16cc 947
255173b4 948 clk = (10000 * j + d) / (10 * p);
4f9c16cc 949
255173b4
PM		 950 /* check whether this values get closer than the best
951 * ones we had before */
952 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
953 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
954 last_clk = clk;
4f9c16cc
DM		 955 }
956
255173b4
PM		 957 /* Early exit for exact matches */
958 if (clk == codec_clk)
959 goto found;
960 }
961
4f9c16cc
DM		 962 if (last_clk == 0) {
963 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
964 return -EINVAL;
965 }
44d0a879 966
255173b4 967found:
c9fe573a 968 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
e18eca43
JN		 969 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
970 pll_r << PLLR_SHIFT);
971 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
972 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
973 (pll_d >> 6) << PLLD_MSB_SHIFT);
974 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
975 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 976
44d0a879
VB		 977 return 0;
978}
979
e550e17f 980static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 981{
982 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 983 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
984 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 985
986 if (mute) {
e18eca43
JN		 987 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
988 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 989 } else {
e18eca43
JN		 990 snd_soc_write(codec, LDAC_VOL, ldac_reg);
991 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 992 }
993
994 return 0;
995}
996
e550e17f 997static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 998 int clk_id, unsigned int freq, int dir)
999{
1000 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1001 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1002
a1f34af0
JP		 1003 /* set clock on MCLK or GPIO2 or BCLK */
1004 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1005 clk_id << PLLCLK_IN_SHIFT);
1006 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1007 clk_id << CLKDIV_IN_SHIFT);
1008
4f9c16cc
DM		 1009 aic3x->sysclk = freq;
1010 return 0;
44d0a879
VB		 1011}
1012
e550e17f 1013static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1014 unsigned int fmt)
1015{
1016 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1017 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 1018 u8 iface_areg, iface_breg;
a24f4f68 1019 int delay = 0;
81971a14 1020
e18eca43
JN		 1021 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1022 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1023
1024 /* set master/slave audio interface */
1025 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1026 case SND_SOC_DAIFMT_CBM_CFM:
1027 aic3x->master = 1;
1028 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1029 break;
1030 case SND_SOC_DAIFMT_CBS_CFS:
1031 aic3x->master = 0;
68e47981 1032 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
44d0a879
VB		 1033 break;
1034 default:
1035 return -EINVAL;
1036 }
1037
4b7d2831
JN		 1038 /*
1039 * match both interface format and signal polarities since they
1040 * are fixed
1041 */
1042 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1043 SND_SOC_DAIFMT_INV_MASK)) {
1044 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1045 break;
a24f4f68
TK		 1046 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1047 delay = 1;
4b7d2831 1048 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1049 iface_breg |= (0x01 << 6);
1050 break;
4b7d2831 1051 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1052 iface_breg |= (0x02 << 6);
1053 break;
4b7d2831 1054 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1055 iface_breg |= (0x03 << 6);
1056 break;
1057 default:
1058 return -EINVAL;
1059 }
1060
1061 /* set iface */
e18eca43
JN		 1062 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1063 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1064 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1065
1066 return 0;
1067}
1068
6c1a7d40
JN		 1069static int aic3x_init_3007(struct snd_soc_codec *codec)
1070{
2677b4bb 1071 unsigned int tmp1, tmp2;
6c1a7d40
JN		 1072
1073 /*
1074 * There is no need to cache writes to undocumented page 0xD but
1075 * respective page 0 register cache entries must be preserved
1076 */
2677b4bb
MB		 1077 tmp1 = snd_soc_read(codec, 0xD);
1078 tmp2 = snd_soc_read(codec, 0x8);
6c1a7d40
JN		 1079 /* Class-D speaker driver init; datasheet p. 46 */
1080 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1081 snd_soc_write(codec, 0xD, 0x0D);
1082 snd_soc_write(codec, 0x8, 0x5C);
1083 snd_soc_write(codec, 0x8, 0x5D);
1084 snd_soc_write(codec, 0x8, 0x5C);
1085 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
2677b4bb
MB		 1086
1087 snd_soc_write(codec, 0xD, tmp1);
1088 snd_soc_write(codec, 0x8, tmp2);
6c1a7d40
JN		 1089
1090 return 0;
1091}
1092
5a895f8a
JN		 1093static int aic3x_regulator_event(struct notifier_block *nb,
1094 unsigned long event, void *data)
1095{
1096 struct aic3x_disable_nb *disable_nb =
1097 container_of(nb, struct aic3x_disable_nb, nb);
1098 struct aic3x_priv *aic3x = disable_nb->aic3x;
1099
1100 if (event & REGULATOR_EVENT_DISABLE) {
1101 /*
1102 * Put codec to reset and require cache sync as at least one
1103 * of the supplies was disabled
1104 */
79ee820d 1105 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a
JN		 1106 gpio_set_value(aic3x->gpio_reset, 0);
1107 aic3x->codec->cache_sync = 1;
1108 }
1109
1110 return 0;
1111}
1112
6c1a7d40
JN		 1113static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1114{
1115 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1116 int i, ret;
1117 u8 *cache = codec->reg_cache;
1118
1119 if (power) {
1120 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1121 aic3x->supplies);
1122 if (ret)
1123 goto out;
1124 aic3x->power = 1;
5a895f8a
JN		 1125 /*
1126 * Reset release and cache sync is necessary only if some
1127 * supply was off or if there were cached writes
1128 */
1129 if (!codec->cache_sync)
1130 goto out;
1131
79ee820d 1132 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1133 udelay(1);
1134 gpio_set_value(aic3x->gpio_reset, 1);
1135 }
1136
1137 /* Sync reg_cache with the hardware */
1138 codec->cache_only = 0;
508b7686 1139 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
6c1a7d40
JN		 1140 snd_soc_write(codec, i, cache[i]);
1141 if (aic3x->model == AIC3X_MODEL_3007)
1142 aic3x_init_3007(codec);
1143 codec->cache_sync = 0;
1144 } else {
9fb352b1
JN		 1145 /*
1146 * Do soft reset to this codec instance in order to clear
1147 * possible VDD leakage currents in case the supply regulators
1148 * remain on
1149 */
1150 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1151 codec->cache_sync = 1;
6c1a7d40 1152 aic3x->power = 0;
5a895f8a
JN		 1153 /* HW writes are needless when bias is off */
1154 codec->cache_only = 1;
6c1a7d40
JN		 1155 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1156 aic3x->supplies);
1157 }
1158out:
1159 return ret;
1160}
1161
0be9898a
MB		 1162static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1163 enum snd_soc_bias_level level)
44d0a879 1164{
b2c812e2 1165 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1166
0be9898a
MB		 1167 switch (level) {
1168 case SND_SOC_BIAS_ON:
db13802e
JN		 1169 break;
1170 case SND_SOC_BIAS_PREPARE:
ce6120cc 1171 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1172 aic3x->master) {
44d0a879 1173 /* enable pll */
9c173d15
AL		 1174 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1175 PLL_ENABLE, PLL_ENABLE);
44d0a879
VB		 1176 }
1177 break;
0be9898a 1178 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1179 if (!aic3x->power)
1180 aic3x_set_power(codec, 1);
ce6120cc 1181 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1182 aic3x->master) {
44d0a879 1183 /* disable pll */
9c173d15
AL		 1184 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1185 PLL_ENABLE, 0);
44d0a879
VB		 1186 }
1187 break;
c23fd751 1188 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1189 if (aic3x->power)
1190 aic3x_set_power(codec, 0);
c23fd751 1191 break;
44d0a879 1192 }
ce6120cc 1193 codec->dapm.bias_level = level;
44d0a879
VB		 1194
1195 return 0;
1196}
1197
1198#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1199#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1200 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1201
85e7652d 1202static const struct snd_soc_dai_ops aic3x_dai_ops = {
6335d055
EM		 1203 .hw_params = aic3x_hw_params,
1204 .digital_mute = aic3x_mute,
1205 .set_sysclk = aic3x_set_dai_sysclk,
1206 .set_fmt = aic3x_set_dai_fmt,
1207};
1208
f0fba2ad
LG		 1209static struct snd_soc_dai_driver aic3x_dai = {
1210 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1211 .playback = {
1212 .stream_name = "Playback",
06378da4 1213 .channels_min = 2,
44d0a879
VB		 1214 .channels_max = 2,
1215 .rates = AIC3X_RATES,
1216 .formats = AIC3X_FORMATS,},
1217 .capture = {
1218 .stream_name = "Capture",
06378da4 1219 .channels_min = 2,
44d0a879
VB		 1220 .channels_max = 2,
1221 .rates = AIC3X_RATES,
1222 .formats = AIC3X_FORMATS,},
6335d055 1223 .ops = &aic3x_dai_ops,
14017615 1224 .symmetric_rates = 1,
44d0a879 1225};
44d0a879 1226
84b315ee 1227static int aic3x_suspend(struct snd_soc_codec *codec)
44d0a879 1228{
0be9898a 1229 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1230
1231 return 0;
1232}
1233
f0fba2ad 1234static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1235{
29e189c2 1236 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1237
1238 return 0;
1239}
1240
1241/*
1242 * initialise the AIC3X driver
1243 * register the mixer and dsp interfaces with the kernel
1244 */
cb3826f5 1245static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1246{
6184f105 1247 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5 1248
e18eca43
JN		 1249 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1250 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1251
44d0a879 1252 /* DAC default volume and mute */
e18eca43
JN		 1253 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1254 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1255
1256 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1257 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1258 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1259 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1260 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1261 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1262 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1263 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1264 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1265 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1266 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1267
1268 /* unmute all outputs */
9c173d15
AL		 1269 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1270 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1271 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1272 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1273 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1274 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1275 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
44d0a879
VB		 1276
1277 /* ADC default volume and unmute */
e18eca43
JN		 1278 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1279 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1280 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1281 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1282 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1283
1284 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1285 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1286 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1287 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1288 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1289 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1290 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1291 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1292 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1293 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1294 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1295
1296 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1297 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1298 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1299 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1300 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1301 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1302 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1303 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1304 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1305 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1306 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1307
6184f105 1308 if (aic3x->model == AIC3X_MODEL_3007) {
6c1a7d40 1309 aic3x_init_3007(codec);
e18eca43 1310 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1311 }
1312
cb3826f5
BD		 1313 return 0;
1314}
54e7e616 1315
414c73ab
JN		 1316static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1317{
1318 struct aic3x_priv *a;
1319
1320 list_for_each_entry(a, &reset_list, list) {
1321 if (gpio_is_valid(aic3x->gpio_reset) &&
1322 aic3x->gpio_reset == a->gpio_reset)
1323 return true;
1324 }
1325
1326 return false;
1327}
1328
f0fba2ad 1329static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1330{
f0fba2ad 1331 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1332 int ret, i;
f0fba2ad 1333
414c73ab 1334 INIT_LIST_HEAD(&aic3x->list);
5a895f8a 1335 aic3x->codec = codec;
cb3826f5 1336
a84a441b
JN		 1337 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1338 if (ret != 0) {
1339 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1340 return ret;
1341 }
1342
5a895f8a
JN		 1343 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1344 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1345 aic3x->disable_nb[i].aic3x = aic3x;
1346 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1347 &aic3x->disable_nb[i].nb);
1348 if (ret) {
1349 dev_err(codec->dev,
1350 "Failed to request regulator notifier: %d\n",
1351 ret);
1352 goto err_notif;
1353 }
1354 }
2f24111a 1355
7d1be0a6 1356 codec->cache_only = 1;
37b47656
JN		 1357 aic3x_init(codec);
1358
f0fba2ad
LG		 1359 if (aic3x->setup) {
1360 /* setup GPIO functions */
e18eca43
JN		 1361 snd_soc_write(codec, AIC3X_GPIO1_REG,
1362 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1363 snd_soc_write(codec, AIC3X_GPIO2_REG,
1364 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1365 }
1366
6184f105 1367 if (aic3x->model == AIC3X_MODEL_3007)
022658be 1368 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1369
e2e8bfdf
HG		 1370 /* set mic bias voltage */
1371 switch (aic3x->micbias_vg) {
1372 case AIC3X_MICBIAS_2_0V:
1373 case AIC3X_MICBIAS_2_5V:
1374 case AIC3X_MICBIAS_AVDDV:
1375 snd_soc_update_bits(codec, MICBIAS_CTRL,
1376 MICBIAS_LEVEL_MASK,
1377 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1378 break;
1379 case AIC3X_MICBIAS_OFF:
1380 /*
1381 * noting to do. target won't enter here. This is just to avoid
1382 * compile time warning "warning: enumeration value
1383 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1384 */
1385 break;
1386 }
1387
f0fba2ad 1388 aic3x_add_widgets(codec);
414c73ab 1389 list_add(&aic3x->list, &reset_list);
cb3826f5
BD		 1390
1391 return 0;
2f24111a 1392
5a895f8a
JN		 1393err_notif:
1394 while (i--)
1395 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1396 &aic3x->disable_nb[i].nb);
2f24111a 1397 return ret;
44d0a879
VB		 1398}
1399
f0fba2ad 1400static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1401{
2f24111a 1402 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1403 int i;
2f24111a 1404
f0fba2ad 1405 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
414c73ab 1406 list_del(&aic3x->list);
5a895f8a
JN		 1407 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1408 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1409 &aic3x->disable_nb[i].nb);
2f24111a 1410
cb3826f5
BD		 1411 return 0;
1412}
44d0a879 1413
f0fba2ad 1414static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad 1415 .set_bias_level = aic3x_set_bias_level,
eb3032f8 1416 .idle_bias_off = true,
f0fba2ad
LG		 1417 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1418 .reg_word_size = sizeof(u8),
1419 .reg_cache_default = aic3x_reg,
1420 .probe = aic3x_probe,
1421 .remove = aic3x_remove,
1422 .suspend = aic3x_suspend,
1423 .resume = aic3x_resume,
f9df1ae6
MB		 1424 .controls = aic3x_snd_controls,
1425 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
58a63fbd
MB		 1426 .dapm_widgets = aic3x_dapm_widgets,
1427 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1428 .dapm_routes = intercon,
1429 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 1430};
1431
44d0a879
VB		 1432/*
1433 * AIC3X 2 wire address can be up to 4 devices with device addresses
1434 * 0x18, 0x19, 0x1A, 0x1B
1435 */
44d0a879 1436
6184f105 1437static const struct i2c_device_id aic3x_i2c_id[] = {
177fdd89
AL		 1438 { "tlv320aic3x", AIC3X_MODEL_3X },
1439 { "tlv320aic33", AIC3X_MODEL_33 },
1440 { "tlv320aic3007", AIC3X_MODEL_3007 },
cbaa5689 1441 { "tlv320aic3106", AIC3X_MODEL_3X },
6184f105
RC		 1442 { }
1443};
1444MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1445
44d0a879
VB		 1446/*
1447 * If the i2c layer weren't so broken, we could pass this kind of data
1448 * around
1449 */
ba8ed121
JD		 1450static int aic3x_i2c_probe(struct i2c_client *i2c,
1451 const struct i2c_device_id *id)
44d0a879 1452{
5193d62f 1453 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1454 struct aic3x_priv *aic3x;
c24fdc88
HG		 1455 struct aic3x_setup_data *ai3x_setup;
1456 struct device_node *np = i2c->dev.of_node;
6f818e04 1457 int ret, i;
e2e8bfdf 1458 u32 value;
44d0a879 1459
e2257db3 1460 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
cb3826f5
BD		 1461 if (aic3x == NULL) {
1462 dev_err(&i2c->dev, "failed to create private data\n");
1463 return -ENOMEM;
1464 }
1465
a84a441b
JN		 1466 aic3x->control_type = SND_SOC_I2C;
1467
cb3826f5 1468 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1469 if (pdata) {
1470 aic3x->gpio_reset = pdata->gpio_reset;
1471 aic3x->setup = pdata->setup;
e2e8bfdf 1472 aic3x->micbias_vg = pdata->micbias_vg;
c24fdc88
HG		 1473 } else if (np) {
1474 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1475 GFP_KERNEL);
1476 if (ai3x_setup == NULL) {
1477 dev_err(&i2c->dev, "failed to create private data\n");
1478 return -ENOMEM;
1479 }
1480
1481 ret = of_get_named_gpio(np, "gpio-reset", 0);
1482 if (ret >= 0)
1483 aic3x->gpio_reset = ret;
1484 else
1485 aic3x->gpio_reset = -1;
1486
1487 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1488 ai3x_setup->gpio_func, 2) >= 0) {
1489 aic3x->setup = ai3x_setup;
1490 }
1491
e2e8bfdf
HG		 1492 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1493 switch (value) {
1494 case 1 :
1495 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1496 break;
1497 case 2 :
1498 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1499 break;
1500 case 3 :
1501 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1502 break;
1503 default :
1504 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1505 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1506 "found in DT\n");
1507 }
1508 } else {
1509 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1510 }
1511
c776357e
JN		 1512 } else {
1513 aic3x->gpio_reset = -1;
1514 }
cb3826f5 1515
177fdd89 1516 aic3x->model = id->driver_data;
6184f105 1517
6f818e04
MB		 1518 if (gpio_is_valid(aic3x->gpio_reset) &&
1519 !aic3x_is_shared_reset(aic3x)) {
1520 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1521 if (ret != 0)
1522 goto err;
1523 gpio_direction_output(aic3x->gpio_reset, 0);
1524 }
1525
1526 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1527 aic3x->supplies[i].supply = aic3x_supply_names[i];
1528
1529 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1530 aic3x->supplies);
1531 if (ret != 0) {
1532 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1533 goto err_gpio;
1534 }
1535
f0fba2ad
LG		 1536 ret = snd_soc_register_codec(&i2c->dev,
1537 &soc_codec_dev_aic3x, &aic3x_dai, 1);
07779fdd 1538 return ret;
6f818e04
MB		 1539
1540err_gpio:
1541 if (gpio_is_valid(aic3x->gpio_reset) &&
1542 !aic3x_is_shared_reset(aic3x))
1543 gpio_free(aic3x->gpio_reset);
1544err:
1545 return ret;
44d0a879
VB		 1546}
1547
ba8ed121 1548static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1549{
6f818e04
MB		 1550 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1551
f0fba2ad 1552 snd_soc_unregister_codec(&client->dev);
6f818e04
MB		 1553 if (gpio_is_valid(aic3x->gpio_reset) &&
1554 !aic3x_is_shared_reset(aic3x)) {
1555 gpio_set_value(aic3x->gpio_reset, 0);
1556 gpio_free(aic3x->gpio_reset);
1557 }
f0fba2ad 1558 return 0;
44d0a879
VB		 1559}
1560
c24fdc88
HG		 1561#if defined(CONFIG_OF)
1562static const struct of_device_id tlv320aic3x_of_match[] = {
1563 { .compatible = "ti,tlv320aic3x", },
f2c4fa65
MB		 1564 { .compatible = "ti,tlv320aic33" },
1565 { .compatible = "ti,tlv320aic3007" },
cbaa5689 1566 { .compatible = "ti,tlv320aic3106" },
c24fdc88
HG		 1567 {},
1568};
1569MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1570#endif
1571
44d0a879
VB		 1572/* machine i2c codec control layer */
1573static struct i2c_driver aic3x_i2c_driver = {
1574 .driver = {
f0fba2ad 1575 .name = "tlv320aic3x-codec",
44d0a879 1576 .owner = THIS_MODULE,
c24fdc88 1577 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
44d0a879 1578 },
cb3826f5 1579 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1580 .remove = aic3x_i2c_remove,
1581 .id_table = aic3x_i2c_id,
44d0a879 1582};
44d0a879 1583
fd39d14b 1584module_i2c_driver(aic3x_i2c_driver);
64089b84 1585
44d0a879
VB		 1586MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1587MODULE_AUTHOR("Vladimir Barinov");
1588MODULE_LICENSE("GPL");
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