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ASoC: tlv320aic3x: Switch to soc-cache helpers
[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / tlv320aic3x.c
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44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
44d0a879 43#include <linux/platform_device.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
49#include <sound/soc-dapm.h>
50#include <sound/initval.h>
7565fc38 51#include <sound/tlv.h>
5193d62f 52#include <sound/tlv320aic3x.h>
44d0a879
VB		 53
54#include "tlv320aic3x.h"
55
07779fdd
JN		 56#define AIC3X_NUM_SUPPLIES 4
57static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62};
44d0a879
VB		 63
64/* codec private data */
65struct aic3x_priv {
07779fdd 66 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 67 enum snd_soc_control_type control_type;
68 struct aic3x_setup_data *setup;
69 void *control_data;
44d0a879
VB		 70 unsigned int sysclk;
71 int master;
5193d62f 72 int gpio_reset;
6184f105
RC		 73#define AIC3X_MODEL_3X 0
74#define AIC3X_MODEL_33 1
75#define AIC3X_MODEL_3007 2
76 u16 model;
44d0a879
VB		 77};
78
79/*
80 * AIC3X register cache
81 * We can't read the AIC3X register space when we are
82 * using 2 wire for device control, so we cache them instead.
83 * There is no point in caching the reset register
84 */
85static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
86 0x00, 0x00, 0x00, 0x10, /* 0 */
87 0x04, 0x00, 0x00, 0x00, /* 4 */
88 0x00, 0x00, 0x00, 0x01, /* 8 */
89 0x00, 0x00, 0x00, 0x80, /* 12 */
90 0x80, 0xff, 0xff, 0x78, /* 16 */
91 0x78, 0x78, 0x78, 0x78, /* 20 */
92 0x78, 0x00, 0x00, 0xfe, /* 24 */
93 0x00, 0x00, 0xfe, 0x00, /* 28 */
94 0x18, 0x18, 0x00, 0x00, /* 32 */
95 0x00, 0x00, 0x00, 0x00, /* 36 */
96 0x00, 0x00, 0x00, 0x80, /* 40 */
97 0x80, 0x00, 0x00, 0x00, /* 44 */
98 0x00, 0x00, 0x00, 0x04, /* 48 */
99 0x00, 0x00, 0x00, 0x00, /* 52 */
100 0x00, 0x00, 0x04, 0x00, /* 56 */
101 0x00, 0x00, 0x00, 0x00, /* 60 */
102 0x00, 0x04, 0x00, 0x00, /* 64 */
103 0x00, 0x00, 0x00, 0x00, /* 68 */
104 0x04, 0x00, 0x00, 0x00, /* 72 */
105 0x00, 0x00, 0x00, 0x00, /* 76 */
106 0x00, 0x00, 0x00, 0x00, /* 80 */
107 0x00, 0x00, 0x00, 0x00, /* 84 */
108 0x00, 0x00, 0x00, 0x00, /* 88 */
109 0x00, 0x00, 0x00, 0x00, /* 92 */
110 0x00, 0x00, 0x00, 0x00, /* 96 */
111 0x00, 0x00, 0x02, /* 100 */
112};
113
44d0a879
VB		 114/*
115 * write aic3x register cache
116 */
117static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
118 u8 reg, u8 value)
119{
120 u8 *cache = codec->reg_cache;
121 if (reg >= AIC3X_CACHEREGNUM)
122 return;
123 cache[reg] = value;
124}
125
54e7e616
DM		 126/*
127 * read from the aic3x register space
128 */
129static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
130 u8 *value)
131{
132 *value = reg & 0xff;
5f345346
MB		 133
134 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
54e7e616
DM		 135
136 aic3x_write_reg_cache(codec, reg, *value);
137 return 0;
138}
139
44d0a879
VB		 140#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
141{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
142 .info = snd_soc_info_volsw, \
143 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
144 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
145
146/*
147 * All input lines are connected when !0xf and disconnected with 0xf bit field,
148 * so we have to use specific dapm_put call for input mixer
149 */
150static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
151 struct snd_ctl_elem_value *ucontrol)
152{
153 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
4453dba5
EN		 154 struct soc_mixer_control *mc =
155 (struct soc_mixer_control *)kcontrol->private_value;
156 unsigned int reg = mc->reg;
157 unsigned int shift = mc->shift;
158 int max = mc->max;
159 unsigned int mask = (1 << fls(max)) - 1;
160 unsigned int invert = mc->invert;
44d0a879
VB		 161 unsigned short val, val_mask;
162 int ret;
163 struct snd_soc_dapm_path *path;
164 int found = 0;
165
166 val = (ucontrol->value.integer.value[0] & mask);
167
168 mask = 0xf;
169 if (val)
170 val = mask;
171
172 if (invert)
173 val = mask - val;
174 val_mask = mask << shift;
175 val = val << shift;
176
177 mutex_lock(&widget->codec->mutex);
178
179 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
180 /* find dapm widget path assoc with kcontrol */
181 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
182 if (path->kcontrol != kcontrol)
183 continue;
184
185 /* found, now check type */
186 found = 1;
187 if (val)
188 /* new connection */
189 path->connect = invert ? 0 : 1;
190 else
191 /* old connection must be powered down */
192 path->connect = invert ? 1 : 0;
193 break;
194 }
195
196 if (found)
a5302181 197 snd_soc_dapm_sync(widget->codec);
44d0a879
VB		 198 }
199
200 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
201
202 mutex_unlock(&widget->codec->mutex);
203 return ret;
204}
205
206static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
207static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
208static const char *aic3x_left_hpcom_mux[] =
209 { "differential of HPLOUT", "constant VCM", "single-ended" };
210static const char *aic3x_right_hpcom_mux[] =
211 { "differential of HPROUT", "constant VCM", "single-ended",
212 "differential of HPLCOM", "external feedback" };
213static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 214static const char *aic3x_adc_hpf[] =
215 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 216
217#define LDAC_ENUM 0
218#define RDAC_ENUM 1
219#define LHPCOM_ENUM 2
220#define RHPCOM_ENUM 3
221#define LINE1L_ENUM 4
222#define LINE1R_ENUM 5
223#define LINE2L_ENUM 6
224#define LINE2R_ENUM 7
4d20f70a 225#define ADC_HPF_ENUM 8
44d0a879
VB		 226
227static const struct soc_enum aic3x_enum[] = {
228 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
229 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
230 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
231 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
232 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
233 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
234 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
235 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 236 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 237};
238
7565fc38
JN		 239/*
240 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
241 */
242static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
243/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
244static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
245/*
246 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
247 * Step size is approximately 0.5 dB over most of the scale but increasing
248 * near the very low levels.
249 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
250 * but having increasing dB difference below that (and where it doesn't count
251 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
252 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
253 */
254static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
255
44d0a879
VB		 256static const struct snd_kcontrol_new aic3x_snd_controls[] = {
257 /* Output */
7565fc38
JN		 258 SOC_DOUBLE_R_TLV("PCM Playback Volume",
259 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 260
098b1718
JN		 261 /*
262 * Output controls that map to output mixer switches. Note these are
263 * only for swapped L-to-R and R-to-L routes. See below stereo controls
264 * for direct L-to-L and R-to-R routes.
265 */
266 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
267 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
268 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
269 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
270 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
271 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
272
273 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
274 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
275 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
276 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
277 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
278 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
279
280 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
281 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
282 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
283 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
284 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
285 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
286
287 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
288 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
289 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
290 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
291 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
292 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
293
294 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
295 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
296 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
297 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
299 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
300
301 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
302 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
303 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
304 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
305 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
306 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
307
308 /* Stereo output controls for direct L-to-L and R-to-R routes */
309 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
310 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
311 0, 118, 1, output_stage_tlv),
312 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
313 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
314 0, 118, 1, output_stage_tlv),
7565fc38
JN		 315 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
316 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
317 0, 118, 1, output_stage_tlv),
098b1718
JN		 318
319 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
320 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 321 0, 118, 1, output_stage_tlv),
098b1718
JN		 322 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
323 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 324 0, 118, 1, output_stage_tlv),
7565fc38
JN		 325 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
326 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
327 0, 118, 1, output_stage_tlv),
098b1718
JN		 328
329 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
330 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 331 0, 118, 1, output_stage_tlv),
098b1718
JN		 332 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
333 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 334 0, 118, 1, output_stage_tlv),
7565fc38
JN		 335 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
336 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
337 0, 118, 1, output_stage_tlv),
098b1718
JN		 338
339 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
340 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 341 0, 118, 1, output_stage_tlv),
098b1718
JN		 342 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
343 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 344 0, 118, 1, output_stage_tlv),
7565fc38
JN		 345 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
346 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
347 0, 118, 1, output_stage_tlv),
098b1718
JN		 348
349 /* Output pin mute controls */
350 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
351 0x01, 0),
352 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
353 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
354 0x01, 0),
f9bc0297 355 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 356 0x01, 0),
44d0a879
VB		 357
358 /*
359 * Note: enable Automatic input Gain Controller with care. It can
360 * adjust PGA to max value when ADC is on and will never go back.
361 */
362 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
363
364 /* Input */
7565fc38
JN		 365 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
366 0, 119, 0, adc_tlv),
44d0a879 367 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 368
369 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 370};
371
6184f105
RC		 372/*
373 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
374 */
375static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
376
377static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
378 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
379
44d0a879
VB		 380/* Left DAC Mux */
381static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
382SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
383
384/* Right DAC Mux */
385static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
386SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
387
388/* Left HPCOM Mux */
389static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
390SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
391
392/* Right HPCOM Mux */
393static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
394SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
395
c3b79e05
JN		 396/* Left Line Mixer */
397static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
398 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
399 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
400 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
401 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
402 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
403 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 404};
405
c3b79e05
JN		 406/* Right Line Mixer */
407static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
408 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
409 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
410 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
411 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
412 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
413 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
414};
415
416/* Mono Mixer */
417static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
418 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
419 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
420 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
421 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
422 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
423 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
424};
425
426/* Left HP Mixer */
427static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
428 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
429 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
430 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
431 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
434};
435
436/* Right HP Mixer */
437static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
438 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
439 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
440 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
441 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
442 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
444};
445
446/* Left HPCOM Mixer */
447static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
448 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
450 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
454};
455
456/* Right HPCOM Mixer */
457static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
458 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
462 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
463 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 464};
465
466/* Left PGA Mixer */
467static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
468 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 469 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 470 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
471 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 472 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 473};
474
475/* Right PGA Mixer */
476static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
477 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 478 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 479 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 480 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 481 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
482};
483
484/* Left Line1 Mux */
485static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
486SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
487
488/* Right Line1 Mux */
489static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
490SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
491
492/* Left Line2 Mux */
493static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
494SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
495
496/* Right Line2 Mux */
497static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
498SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
499
44d0a879
VB		 500static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
501 /* Left DAC to Left Outputs */
502 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
503 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
504 &aic3x_left_dac_mux_controls),
44d0a879
VB		 505 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
506 &aic3x_left_hpcom_mux_controls),
507 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
508 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
509 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
510
511 /* Right DAC to Right Outputs */
512 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
513 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
514 &aic3x_right_dac_mux_controls),
44d0a879
VB		 515 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
516 &aic3x_right_hpcom_mux_controls),
517 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
518 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
519 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
520
521 /* Mono Output */
522 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
523
54f01916 524 /* Inputs to Left ADC */
44d0a879
VB		 525 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
526 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
527 &aic3x_left_pga_mixer_controls[0],
528 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
529 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
530 &aic3x_left_line1_mux_controls),
54f01916
DM		 531 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
532 &aic3x_left_line1_mux_controls),
44d0a879
VB		 533 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
534 &aic3x_left_line2_mux_controls),
535
54f01916 536 /* Inputs to Right ADC */
44d0a879
VB		 537 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
538 LINE1R_2_RADC_CTRL, 2, 0),
539 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
540 &aic3x_right_pga_mixer_controls[0],
541 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 542 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
543 &aic3x_right_line1_mux_controls),
44d0a879
VB		 544 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
545 &aic3x_right_line1_mux_controls),
546 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
547 &aic3x_right_line2_mux_controls),
548
ee15ffdb
JN		 549 /*
550 * Not a real mic bias widget but similar function. This is for dynamic
551 * control of GPIO1 digital mic modulator clock output function when
552 * using digital mic.
553 */
554 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
555 AIC3X_GPIO1_REG, 4, 0xf,
556 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
557 AIC3X_GPIO1_FUNC_DISABLED),
558
559 /*
560 * Also similar function like mic bias. Selects digital mic with
561 * configurable oversampling rate instead of ADC converter.
562 */
563 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
564 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
565 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
566 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
567 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
568 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
569
44d0a879 570 /* Mic Bias */
0bd72a3d
JN		 571 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
572 MICBIAS_CTRL, 6, 3, 1, 0),
573 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
574 MICBIAS_CTRL, 6, 3, 2, 0),
575 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
576 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 577
c3b79e05
JN		 578 /* Output mixers */
579 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
580 &aic3x_left_line_mixer_controls[0],
581 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
582 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
583 &aic3x_right_line_mixer_controls[0],
584 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
585 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
586 &aic3x_mono_mixer_controls[0],
587 ARRAY_SIZE(aic3x_mono_mixer_controls)),
588 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
589 &aic3x_left_hp_mixer_controls[0],
590 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
591 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
592 &aic3x_right_hp_mixer_controls[0],
593 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
594 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
595 &aic3x_left_hpcom_mixer_controls[0],
596 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
597 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
598 &aic3x_right_hpcom_mixer_controls[0],
599 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 600
601 SND_SOC_DAPM_OUTPUT("LLOUT"),
602 SND_SOC_DAPM_OUTPUT("RLOUT"),
603 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
604 SND_SOC_DAPM_OUTPUT("HPLOUT"),
605 SND_SOC_DAPM_OUTPUT("HPROUT"),
606 SND_SOC_DAPM_OUTPUT("HPLCOM"),
607 SND_SOC_DAPM_OUTPUT("HPRCOM"),
608
609 SND_SOC_DAPM_INPUT("MIC3L"),
610 SND_SOC_DAPM_INPUT("MIC3R"),
611 SND_SOC_DAPM_INPUT("LINE1L"),
612 SND_SOC_DAPM_INPUT("LINE1R"),
613 SND_SOC_DAPM_INPUT("LINE2L"),
614 SND_SOC_DAPM_INPUT("LINE2R"),
615};
616
6184f105
RC		 617static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
618 /* Class-D outputs */
619 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
620 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
621
622 SND_SOC_DAPM_OUTPUT("SPOP"),
623 SND_SOC_DAPM_OUTPUT("SPOM"),
624};
625
d0cc0d3a 626static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 627 /* Left Input */
628 {"Left Line1L Mux", "single-ended", "LINE1L"},
629 {"Left Line1L Mux", "differential", "LINE1L"},
630
631 {"Left Line2L Mux", "single-ended", "LINE2L"},
632 {"Left Line2L Mux", "differential", "LINE2L"},
633
634 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 635 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 636 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
637 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 638 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 639
640 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 641 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 642
643 /* Right Input */
644 {"Right Line1R Mux", "single-ended", "LINE1R"},
645 {"Right Line1R Mux", "differential", "LINE1R"},
646
647 {"Right Line2R Mux", "single-ended", "LINE2R"},
648 {"Right Line2R Mux", "differential", "LINE2R"},
649
54f01916 650 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 651 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
652 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 653 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 654 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
655
656 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 657 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 658
ee15ffdb
JN		 659 /*
660 * Logical path between digital mic enable and GPIO1 modulator clock
661 * output function
662 */
663 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
664 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
665 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 666
667 /* Left DAC Output */
668 {"Left DAC Mux", "DAC_L1", "Left DAC"},
669 {"Left DAC Mux", "DAC_L2", "Left DAC"},
670 {"Left DAC Mux", "DAC_L3", "Left DAC"},
671
672 /* Right DAC Output */
673 {"Right DAC Mux", "DAC_R1", "Right DAC"},
674 {"Right DAC Mux", "DAC_R2", "Right DAC"},
675 {"Right DAC Mux", "DAC_R3", "Right DAC"},
676
677 /* Left Line Output */
678 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
679 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
680 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
681 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
682 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
683 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
684
685 {"Left Line Out", NULL, "Left Line Mixer"},
686 {"Left Line Out", NULL, "Left DAC Mux"},
687 {"LLOUT", NULL, "Left Line Out"},
688
689 /* Right Line Output */
690 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
691 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
692 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
693 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
694 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
695 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
696
697 {"Right Line Out", NULL, "Right Line Mixer"},
698 {"Right Line Out", NULL, "Right DAC Mux"},
699 {"RLOUT", NULL, "Right Line Out"},
700
701 /* Mono Output */
702 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
703 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
704 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
705 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
706 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
707 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
708
709 {"Mono Out", NULL, "Mono Mixer"},
710 {"MONO_LOUT", NULL, "Mono Out"},
711
712 /* Left HP Output */
713 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
714 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
715 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
716 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
717 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
718 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
719
720 {"Left HP Out", NULL, "Left HP Mixer"},
721 {"Left HP Out", NULL, "Left DAC Mux"},
722 {"HPLOUT", NULL, "Left HP Out"},
723
724 /* Right HP Output */
725 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
726 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
727 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
728 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
729 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
730 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
731
732 {"Right HP Out", NULL, "Right HP Mixer"},
733 {"Right HP Out", NULL, "Right DAC Mux"},
734 {"HPROUT", NULL, "Right HP Out"},
735
736 /* Left HPCOM Output */
737 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
738 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
739 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
740 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
741 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
742 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
743
744 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
745 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
746 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
747 {"Left HP Com", NULL, "Left HPCOM Mux"},
748 {"HPLCOM", NULL, "Left HP Com"},
749
750 /* Right HPCOM Output */
751 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
752 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
753 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
754 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
755 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
756 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
757
758 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
759 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
760 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
761 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
762 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
763 {"Right HP Com", NULL, "Right HPCOM Mux"},
764 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 765};
766
6184f105
RC		 767static const struct snd_soc_dapm_route intercon_3007[] = {
768 /* Class-D outputs */
769 {"Left Class-D Out", NULL, "Left Line Out"},
770 {"Right Class-D Out", NULL, "Left Line Out"},
771 {"SPOP", NULL, "Left Class-D Out"},
772 {"SPOM", NULL, "Right Class-D Out"},
773};
774
44d0a879
VB		 775static int aic3x_add_widgets(struct snd_soc_codec *codec)
776{
6184f105
RC		 777 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
778
d0cc0d3a
MB		 779 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
780 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 781
782 /* set up audio path interconnects */
d0cc0d3a 783 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
44d0a879 784
6184f105
RC		 785 if (aic3x->model == AIC3X_MODEL_3007) {
786 snd_soc_dapm_new_controls(codec, aic3007_dapm_widgets,
787 ARRAY_SIZE(aic3007_dapm_widgets));
788 snd_soc_dapm_add_routes(codec, intercon_3007, ARRAY_SIZE(intercon_3007));
789 }
790
44d0a879
VB		 791 return 0;
792}
793
44d0a879 794static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 795 struct snd_pcm_hw_params *params,
796 struct snd_soc_dai *dai)
44d0a879
VB		 797{
798 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 799 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 800 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 801 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 802 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
803 u16 d, pll_d = 1;
06c71282 804 u8 reg;
255173b4 805 int clk;
44d0a879 806
4f9c16cc 807 /* select data word length */
e18eca43 808 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 809 switch (params_format(params)) {
810 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 811 break;
4f9c16cc
DM		 812 case SNDRV_PCM_FORMAT_S20_3LE:
813 data |= (0x01 << 4);
44d0a879 814 break;
4f9c16cc
DM		 815 case SNDRV_PCM_FORMAT_S24_LE:
816 data |= (0x02 << 4);
44d0a879 817 break;
4f9c16cc
DM		 818 case SNDRV_PCM_FORMAT_S32_LE:
819 data |= (0x03 << 4);
44d0a879
VB		 820 break;
821 }
e18eca43 822 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 823
824 /* Fsref can be 44100 or 48000 */
825 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
826
827 /* Try to find a value for Q which allows us to bypass the PLL and
828 * generate CODEC_CLK directly. */
829 for (pll_q = 2; pll_q < 18; pll_q++)
830 if (aic3x->sysclk / (128 * pll_q) == fsref) {
831 bypass_pll = 1;
832 break;
833 }
834
835 if (bypass_pll) {
836 pll_q &= 0xf;
e18eca43
JN		 837 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
838 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 839 /* disable PLL if it is bypassed */
e18eca43
JN		 840 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
841 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
06c71282
C		 842
843 } else {
e18eca43 844 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 845 /* enable PLL when it is used */
e18eca43
JN		 846 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
847 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
06c71282 848 }
4f9c16cc
DM		 849
850 /* Route Left DAC to left channel input and
851 * right DAC to right channel input */
852 data = (LDAC2LCH | RDAC2RCH);
853 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
854 if (params_rate(params) >= 64000)
855 data |= DUAL_RATE_MODE;
e18eca43 856 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 857
858 /* codec sample rate select */
4f9c16cc
DM		 859 data = (fsref * 20) / params_rate(params);
860 if (params_rate(params) < 64000)
861 data /= 2;
862 data /= 5;
863 data -= 2;
44d0a879 864 data |= (data << 4);
e18eca43 865 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 866
4f9c16cc
DM		 867 if (bypass_pll)
868 return 0;
869
255173b4
PM		 870 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
871 * one wins the game. Try with d==0 first, next with d!=0.
872 * Constraints for j are according to the datasheet.
4f9c16cc 873 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 874 */
255173b4 875
4f9c16cc
DM		 876 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
877
878 for (r = 1; r <= 16; r++)
879 for (p = 1; p <= 8; p++) {
255173b4
PM		 880 for (j = 4; j <= 55; j++) {
881 /* This is actually 1000*((j+(d/10000))*r)/p
882 * The term had to be converted to get
883 * rid of the division by 10000; d = 0 here
884 */
5baf8315 885 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 886
887 /* Check whether this values get closer than
888 * the best ones we had before
889 */
5baf8315 890 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 891 abs(codec_clk - last_clk)) {
892 pll_j = j; pll_d = 0;
893 pll_r = r; pll_p = p;
5baf8315 894 last_clk = tmp_clk;
255173b4
PM		 895 }
896
897 /* Early exit for exact matches */
5baf8315 898 if (tmp_clk == codec_clk)
255173b4
PM		 899 goto found;
900 }
901 }
4f9c16cc 902
255173b4
PM		 903 /* try with d != 0 */
904 for (p = 1; p <= 8; p++) {
905 j = codec_clk * p / 1000;
4f9c16cc 906
255173b4
PM		 907 if (j < 4 || j > 11)
908 continue;
4f9c16cc 909
255173b4
PM		 910 /* do not use codec_clk here since we'd loose precision */
911 d = ((2048 * p * fsref) - j * aic3x->sysclk)
912 * 100 / (aic3x->sysclk/100);
4f9c16cc 913
255173b4 914 clk = (10000 * j + d) / (10 * p);
4f9c16cc 915
255173b4
PM		 916 /* check whether this values get closer than the best
917 * ones we had before */
918 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
919 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
920 last_clk = clk;
4f9c16cc
DM		 921 }
922
255173b4
PM		 923 /* Early exit for exact matches */
924 if (clk == codec_clk)
925 goto found;
926 }
927
4f9c16cc
DM		 928 if (last_clk == 0) {
929 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
930 return -EINVAL;
931 }
44d0a879 932
255173b4 933found:
e18eca43
JN		 934 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
935 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
936 data | (pll_p << PLLP_SHIFT));
937 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
938 pll_r << PLLR_SHIFT);
939 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
940 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
941 (pll_d >> 6) << PLLD_MSB_SHIFT);
942 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
943 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 944
44d0a879
VB		 945 return 0;
946}
947
e550e17f 948static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 949{
950 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 951 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
952 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 953
954 if (mute) {
e18eca43
JN		 955 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
956 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 957 } else {
e18eca43
JN		 958 snd_soc_write(codec, LDAC_VOL, ldac_reg);
959 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 960 }
961
962 return 0;
963}
964
e550e17f 965static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 966 int clk_id, unsigned int freq, int dir)
967{
968 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 969 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 970
4f9c16cc
DM		 971 aic3x->sysclk = freq;
972 return 0;
44d0a879
VB		 973}
974
e550e17f 975static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 976 unsigned int fmt)
977{
978 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 979 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 980 u8 iface_areg, iface_breg;
a24f4f68 981 int delay = 0;
81971a14 982
e18eca43
JN		 983 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
984 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 985
986 /* set master/slave audio interface */
987 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
988 case SND_SOC_DAIFMT_CBM_CFM:
989 aic3x->master = 1;
990 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
991 break;
992 case SND_SOC_DAIFMT_CBS_CFS:
993 aic3x->master = 0;
994 break;
995 default:
996 return -EINVAL;
997 }
998
4b7d2831
JN		 999 /*
1000 * match both interface format and signal polarities since they
1001 * are fixed
1002 */
1003 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1004 SND_SOC_DAIFMT_INV_MASK)) {
1005 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1006 break;
a24f4f68
TK		 1007 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1008 delay = 1;
4b7d2831 1009 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1010 iface_breg |= (0x01 << 6);
1011 break;
4b7d2831 1012 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1013 iface_breg |= (0x02 << 6);
1014 break;
4b7d2831 1015 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1016 iface_breg |= (0x03 << 6);
1017 break;
1018 default:
1019 return -EINVAL;
1020 }
1021
1022 /* set iface */
e18eca43
JN		 1023 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1024 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1025 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1026
1027 return 0;
1028}
1029
0be9898a
MB		 1030static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1031 enum snd_soc_bias_level level)
44d0a879 1032{
b2c812e2 1033 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 1034 u8 reg;
1035
0be9898a
MB		 1036 switch (level) {
1037 case SND_SOC_BIAS_ON:
db13802e
JN		 1038 break;
1039 case SND_SOC_BIAS_PREPARE:
c23fd751
JN		 1040 if (codec->bias_level == SND_SOC_BIAS_STANDBY &&
1041 aic3x->master) {
44d0a879 1042 /* enable pll */
e18eca43
JN		 1043 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1044 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1045 reg | PLL_ENABLE);
44d0a879
VB		 1046 }
1047 break;
0be9898a 1048 case SND_SOC_BIAS_STANDBY:
c23fd751
JN		 1049 if (codec->bias_level == SND_SOC_BIAS_PREPARE &&
1050 aic3x->master) {
44d0a879 1051 /* disable pll */
e18eca43
JN		 1052 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1053 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1054 reg & ~PLL_ENABLE);
44d0a879
VB		 1055 }
1056 break;
c23fd751
JN		 1057 case SND_SOC_BIAS_OFF:
1058 break;
44d0a879 1059 }
0be9898a 1060 codec->bias_level = level;
44d0a879
VB		 1061
1062 return 0;
1063}
1064
54e7e616
DM		 1065void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1066{
1067 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1068 u8 bit = gpio ? 3: 0;
e18eca43
JN		 1069 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1070 snd_soc_write(codec, reg, val | (!!state << bit));
54e7e616
DM		 1071}
1072EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1073
1074int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1075{
1076 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1077 u8 val, bit = gpio ? 2: 1;
1078
1079 aic3x_read(codec, reg, &val);
1080 return (val >> bit) & 1;
1081}
1082EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1083
6f2a974b
DM		 1084void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1085 int headset_debounce, int button_debounce)
1086{
1087 u8 val;
1088
1089 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1090 << AIC3X_HEADSET_DETECT_SHIFT) |
1091 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1092 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1093 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1094 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1095
1096 if (detect & AIC3X_HEADSET_DETECT_MASK)
1097 val |= AIC3X_HEADSET_DETECT_ENABLED;
1098
e18eca43 1099 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
6f2a974b
DM		 1100}
1101EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1102
54e7e616
DM		 1103int aic3x_headset_detected(struct snd_soc_codec *codec)
1104{
1105 u8 val;
6f2a974b
DM		 1106 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1107 return (val >> 4) & 1;
54e7e616
DM		 1108}
1109EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1110
6f2a974b
DM		 1111int aic3x_button_pressed(struct snd_soc_codec *codec)
1112{
1113 u8 val;
1114 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1115 return (val >> 5) & 1;
1116}
1117EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1118
44d0a879
VB		 1119#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1120#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1121 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1122
6335d055
EM		 1123static struct snd_soc_dai_ops aic3x_dai_ops = {
1124 .hw_params = aic3x_hw_params,
1125 .digital_mute = aic3x_mute,
1126 .set_sysclk = aic3x_set_dai_sysclk,
1127 .set_fmt = aic3x_set_dai_fmt,
1128};
1129
f0fba2ad
LG		 1130static struct snd_soc_dai_driver aic3x_dai = {
1131 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1132 .playback = {
1133 .stream_name = "Playback",
1134 .channels_min = 1,
1135 .channels_max = 2,
1136 .rates = AIC3X_RATES,
1137 .formats = AIC3X_FORMATS,},
1138 .capture = {
1139 .stream_name = "Capture",
1140 .channels_min = 1,
1141 .channels_max = 2,
1142 .rates = AIC3X_RATES,
1143 .formats = AIC3X_FORMATS,},
6335d055 1144 .ops = &aic3x_dai_ops,
14017615 1145 .symmetric_rates = 1,
44d0a879 1146};
44d0a879 1147
f0fba2ad 1148static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
44d0a879 1149{
0be9898a 1150 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1151
1152 return 0;
1153}
1154
f0fba2ad 1155static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1156{
44d0a879
VB		 1157 int i;
1158 u8 data[2];
1159 u8 *cache = codec->reg_cache;
1160
1161 /* Sync reg_cache with the hardware */
1162 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1163 data[0] = i;
1164 data[1] = cache[i];
1165 codec->hw_write(codec->control_data, data, 2);
1166 }
1167
29e189c2 1168 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1169
1170 return 0;
1171}
1172
1173/*
1174 * initialise the AIC3X driver
1175 * register the mixer and dsp interfaces with the kernel
1176 */
cb3826f5 1177static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1178{
6184f105 1179 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5
BD		 1180 int reg;
1181
e18eca43
JN		 1182 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1183 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1184
44d0a879 1185 /* DAC default volume and mute */
e18eca43
JN		 1186 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1187 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1188
1189 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1190 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1191 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1192 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1193 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1194 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1195 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1196 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1197 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1198 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1199 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1200
1201 /* unmute all outputs */
e18eca43
JN		 1202 reg = snd_soc_read(codec, LLOPM_CTRL);
1203 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
1204 reg = snd_soc_read(codec, RLOPM_CTRL);
1205 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
1206 reg = snd_soc_read(codec, MONOLOPM_CTRL);
1207 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1208 reg = snd_soc_read(codec, HPLOUT_CTRL);
1209 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1210 reg = snd_soc_read(codec, HPROUT_CTRL);
1211 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
1212 reg = snd_soc_read(codec, HPLCOM_CTRL);
1213 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1214 reg = snd_soc_read(codec, HPRCOM_CTRL);
1215 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
44d0a879
VB		 1216
1217 /* ADC default volume and unmute */
e18eca43
JN		 1218 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1219 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1220 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1221 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1222 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1223
1224 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1225 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1226 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1227 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1228 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1229 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1230 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1231 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1232 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1233 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1234 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1235
1236 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1237 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1238 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1239 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1240 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1241 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1242 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1243 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1244 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1245 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1246 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1247
6184f105
RC		 1248 if (aic3x->model == AIC3X_MODEL_3007) {
1249 /* Class-D speaker driver init; datasheet p. 46 */
e18eca43
JN		 1250 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1251 snd_soc_write(codec, 0xD, 0x0D);
1252 snd_soc_write(codec, 0x8, 0x5C);
1253 snd_soc_write(codec, 0x8, 0x5D);
1254 snd_soc_write(codec, 0x8, 0x5C);
1255 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1256 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1257 }
1258
44d0a879 1259 /* off, with power on */
0be9898a 1260 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879 1261
cb3826f5
BD		 1262 return 0;
1263}
54e7e616 1264
f0fba2ad 1265static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1266{
f0fba2ad 1267 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
a84a441b 1268 int ret;
f0fba2ad 1269
f0fba2ad 1270 codec->control_data = aic3x->control_data;
cb3826f5 1271
a84a441b
JN		 1272 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1273 if (ret != 0) {
1274 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1275 return ret;
1276 }
1277
37b47656
JN		 1278 aic3x_init(codec);
1279
f0fba2ad
LG		 1280 if (aic3x->setup) {
1281 /* setup GPIO functions */
e18eca43
JN		 1282 snd_soc_write(codec, AIC3X_GPIO1_REG,
1283 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1284 snd_soc_write(codec, AIC3X_GPIO2_REG,
1285 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1286 }
1287
f0fba2ad
LG		 1288 snd_soc_add_controls(codec, aic3x_snd_controls,
1289 ARRAY_SIZE(aic3x_snd_controls));
6184f105
RC		 1290 if (aic3x->model == AIC3X_MODEL_3007)
1291 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1292
f0fba2ad 1293 aic3x_add_widgets(codec);
cb3826f5
BD		 1294
1295 return 0;
44d0a879
VB		 1296}
1297
f0fba2ad 1298static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1299{
f0fba2ad 1300 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
cb3826f5
BD		 1301 return 0;
1302}
44d0a879 1303
f0fba2ad 1304static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad
LG		 1305 .set_bias_level = aic3x_set_bias_level,
1306 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1307 .reg_word_size = sizeof(u8),
1308 .reg_cache_default = aic3x_reg,
1309 .probe = aic3x_probe,
1310 .remove = aic3x_remove,
1311 .suspend = aic3x_suspend,
1312 .resume = aic3x_resume,
1313};
1314
44d0a879
VB		 1315#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1316/*
1317 * AIC3X 2 wire address can be up to 4 devices with device addresses
1318 * 0x18, 0x19, 0x1A, 0x1B
1319 */
44d0a879 1320
6184f105
RC		 1321static const struct i2c_device_id aic3x_i2c_id[] = {
1322 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1323 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1324 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1325 { }
1326};
1327MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1328
44d0a879
VB		 1329/*
1330 * If the i2c layer weren't so broken, we could pass this kind of data
1331 * around
1332 */
ba8ed121
JD		 1333static int aic3x_i2c_probe(struct i2c_client *i2c,
1334 const struct i2c_device_id *id)
44d0a879 1335{
5193d62f 1336 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1337 struct aic3x_priv *aic3x;
07779fdd 1338 int ret, i;
6184f105 1339 const struct i2c_device_id *tbl;
44d0a879 1340
cb3826f5
BD		 1341 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1342 if (aic3x == NULL) {
1343 dev_err(&i2c->dev, "failed to create private data\n");
1344 return -ENOMEM;
1345 }
1346
f0fba2ad 1347 aic3x->control_data = i2c;
a84a441b
JN		 1348 aic3x->control_type = SND_SOC_I2C;
1349
cb3826f5 1350 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1351 if (pdata) {
1352 aic3x->gpio_reset = pdata->gpio_reset;
1353 aic3x->setup = pdata->setup;
1354 } else {
1355 aic3x->gpio_reset = -1;
1356 }
cb3826f5 1357
c776357e
JN		 1358 if (aic3x->gpio_reset >= 0) {
1359 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
5193d62f
JN		 1360 if (ret != 0)
1361 goto err_gpio;
5193d62f
JN		 1362 gpio_direction_output(aic3x->gpio_reset, 0);
1363 }
1364
6184f105
RC		 1365 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1366 if (!strcmp(tbl->name, id->name))
1367 break;
1368 }
1369 aic3x->model = tbl - aic3x_i2c_id;
1370
07779fdd
JN		 1371 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1372 aic3x->supplies[i].supply = aic3x_supply_names[i];
1373
f0fba2ad 1374 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
07779fdd
JN		 1375 aic3x->supplies);
1376 if (ret != 0) {
f0fba2ad 1377 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
07779fdd
JN		 1378 goto err_get;
1379 }
1380
1381 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1382 aic3x->supplies);
1383 if (ret != 0) {
f0fba2ad 1384 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
07779fdd
JN		 1385 goto err_enable;
1386 }
1387
5193d62f
JN		 1388 if (aic3x->gpio_reset >= 0) {
1389 udelay(1);
1390 gpio_set_value(aic3x->gpio_reset, 1);
1391 }
1392
f0fba2ad
LG		 1393 ret = snd_soc_register_codec(&i2c->dev,
1394 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1395 if (ret < 0)
1396 goto err_enable;
1397 return ret;
07779fdd
JN		 1398
1399err_enable:
1400 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1401err_get:
5193d62f
JN		 1402 if (aic3x->gpio_reset >= 0)
1403 gpio_free(aic3x->gpio_reset);
1404err_gpio:
07779fdd
JN		 1405 kfree(aic3x);
1406 return ret;
44d0a879
VB		 1407}
1408
ba8ed121 1409static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1410{
cb3826f5
BD		 1411 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1412
f0fba2ad
LG		 1413 if (aic3x->gpio_reset >= 0) {
1414 gpio_set_value(aic3x->gpio_reset, 0);
1415 gpio_free(aic3x->gpio_reset);
1416 }
1417 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1418 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1419
1420 snd_soc_unregister_codec(&client->dev);
1421 kfree(i2c_get_clientdata(client));
1422 return 0;
44d0a879
VB		 1423}
1424
44d0a879
VB		 1425/* machine i2c codec control layer */
1426static struct i2c_driver aic3x_i2c_driver = {
1427 .driver = {
f0fba2ad 1428 .name = "tlv320aic3x-codec",
44d0a879
VB		 1429 .owner = THIS_MODULE,
1430 },
cb3826f5 1431 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1432 .remove = aic3x_i2c_remove,
1433 .id_table = aic3x_i2c_id,
44d0a879 1434};
54e7e616 1435
cb3826f5 1436static inline void aic3x_i2c_init(void)
ba8ed121 1437{
ba8ed121
JD		 1438 int ret;
1439
1440 ret = i2c_add_driver(&aic3x_i2c_driver);
cb3826f5
BD		 1441 if (ret)
1442 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1443 __func__, ret);
1444}
ba8ed121 1445
cb3826f5
BD		 1446static inline void aic3x_i2c_exit(void)
1447{
ba8ed121 1448 i2c_del_driver(&aic3x_i2c_driver);
ba8ed121 1449}
44d0a879
VB		 1450#endif
1451
f0fba2ad 1452static int __init aic3x_modinit(void)
44d0a879 1453{
44d0a879 1454 int ret = 0;
f0fba2ad
LG		 1455#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1456 ret = i2c_add_driver(&aic3x_i2c_driver);
1457 if (ret != 0) {
1458 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1459 ret);
44d0a879 1460 }
f0fba2ad 1461#endif
44d0a879
VB		 1462 return ret;
1463}
64089b84
MB		 1464module_init(aic3x_modinit);
1465
1466static void __exit aic3x_exit(void)
1467{
f0fba2ad
LG		 1468#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1469 i2c_del_driver(&aic3x_i2c_driver);
1470#endif
64089b84
MB		 1471}
1472module_exit(aic3x_exit);
1473
44d0a879
VB		 1474MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1475MODULE_AUTHOR("Vladimir Barinov");
1476MODULE_LICENSE("GPL");
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