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ASoC: wm2200: Add missing BCLK rate
[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / tlv320aic3x.c
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44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
5a0e3ad6 43#include <linux/slab.h>
44d0a879
VB		 44#include <sound/core.h>
45#include <sound/pcm.h>
46#include <sound/pcm_params.h>
47#include <sound/soc.h>
44d0a879 48#include <sound/initval.h>
7565fc38 49#include <sound/tlv.h>
5193d62f 50#include <sound/tlv320aic3x.h>
44d0a879
VB		 51
52#include "tlv320aic3x.h"
53
07779fdd
JN		 54#define AIC3X_NUM_SUPPLIES 4
55static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
56 "IOVDD", /* I/O Voltage */
57 "DVDD", /* Digital Core Voltage */
58 "AVDD", /* Analog DAC Voltage */
59 "DRVDD", /* ADC Analog and Output Driver Voltage */
60};
44d0a879 61
414c73ab
JN		 62static LIST_HEAD(reset_list);
63
5a895f8a
JN		 64struct aic3x_priv;
65
66struct aic3x_disable_nb {
67 struct notifier_block nb;
68 struct aic3x_priv *aic3x;
69};
70
44d0a879
VB		 71/* codec private data */
72struct aic3x_priv {
5a895f8a 73 struct snd_soc_codec *codec;
07779fdd 74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 76 enum snd_soc_control_type control_type;
77 struct aic3x_setup_data *setup;
44d0a879 78 unsigned int sysclk;
414c73ab 79 struct list_head list;
44d0a879 80 int master;
5193d62f 81 int gpio_reset;
6c1a7d40 82 int power;
6184f105
RC		 83#define AIC3X_MODEL_3X 0
84#define AIC3X_MODEL_33 1
85#define AIC3X_MODEL_3007 2
86 u16 model;
44d0a879
VB		 87};
88
89/*
90 * AIC3X register cache
91 * We can't read the AIC3X register space when we are
92 * using 2 wire for device control, so we cache them instead.
93 * There is no point in caching the reset register
94 */
95static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
96 0x00, 0x00, 0x00, 0x10, /* 0 */
97 0x04, 0x00, 0x00, 0x00, /* 4 */
98 0x00, 0x00, 0x00, 0x01, /* 8 */
99 0x00, 0x00, 0x00, 0x80, /* 12 */
100 0x80, 0xff, 0xff, 0x78, /* 16 */
101 0x78, 0x78, 0x78, 0x78, /* 20 */
102 0x78, 0x00, 0x00, 0xfe, /* 24 */
103 0x00, 0x00, 0xfe, 0x00, /* 28 */
104 0x18, 0x18, 0x00, 0x00, /* 32 */
105 0x00, 0x00, 0x00, 0x00, /* 36 */
106 0x00, 0x00, 0x00, 0x80, /* 40 */
107 0x80, 0x00, 0x00, 0x00, /* 44 */
108 0x00, 0x00, 0x00, 0x04, /* 48 */
109 0x00, 0x00, 0x00, 0x00, /* 52 */
110 0x00, 0x00, 0x04, 0x00, /* 56 */
111 0x00, 0x00, 0x00, 0x00, /* 60 */
112 0x00, 0x04, 0x00, 0x00, /* 64 */
113 0x00, 0x00, 0x00, 0x00, /* 68 */
114 0x04, 0x00, 0x00, 0x00, /* 72 */
115 0x00, 0x00, 0x00, 0x00, /* 76 */
116 0x00, 0x00, 0x00, 0x00, /* 80 */
117 0x00, 0x00, 0x00, 0x00, /* 84 */
118 0x00, 0x00, 0x00, 0x00, /* 88 */
119 0x00, 0x00, 0x00, 0x00, /* 92 */
120 0x00, 0x00, 0x00, 0x00, /* 96 */
121 0x00, 0x00, 0x02, /* 100 */
122};
123
44d0a879
VB		 124#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
125{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
126 .info = snd_soc_info_volsw, \
127 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
128 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
129
130/*
131 * All input lines are connected when !0xf and disconnected with 0xf bit field,
132 * so we have to use specific dapm_put call for input mixer
133 */
134static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
135 struct snd_ctl_elem_value *ucontrol)
136{
9d03545d
JN		 137 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
138 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
4453dba5
EN		 139 struct soc_mixer_control *mc =
140 (struct soc_mixer_control *)kcontrol->private_value;
141 unsigned int reg = mc->reg;
142 unsigned int shift = mc->shift;
143 int max = mc->max;
144 unsigned int mask = (1 << fls(max)) - 1;
145 unsigned int invert = mc->invert;
44d0a879
VB		 146 unsigned short val, val_mask;
147 int ret;
148 struct snd_soc_dapm_path *path;
149 int found = 0;
150
151 val = (ucontrol->value.integer.value[0] & mask);
152
153 mask = 0xf;
154 if (val)
155 val = mask;
156
157 if (invert)
158 val = mask - val;
159 val_mask = mask << shift;
160 val = val << shift;
161
162 mutex_lock(&widget->codec->mutex);
163
164 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
165 /* find dapm widget path assoc with kcontrol */
8ddab3f5 166 list_for_each_entry(path, &widget->dapm->card->paths, list) {
44d0a879
VB		 167 if (path->kcontrol != kcontrol)
168 continue;
169
170 /* found, now check type */
171 found = 1;
172 if (val)
173 /* new connection */
174 path->connect = invert ? 0 : 1;
175 else
176 /* old connection must be powered down */
177 path->connect = invert ? 1 : 0;
25c77c5f
MB		 178
179 dapm_mark_dirty(path->source, "tlv320aic3x source");
180 dapm_mark_dirty(path->sink, "tlv320aic3x sink");
181
44d0a879
VB		 182 break;
183 }
184
185 if (found)
ce6120cc 186 snd_soc_dapm_sync(widget->dapm);
44d0a879
VB		 187 }
188
189 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
190
191 mutex_unlock(&widget->codec->mutex);
192 return ret;
193}
194
195static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
196static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
197static const char *aic3x_left_hpcom_mux[] =
198 { "differential of HPLOUT", "constant VCM", "single-ended" };
199static const char *aic3x_right_hpcom_mux[] =
200 { "differential of HPROUT", "constant VCM", "single-ended",
201 "differential of HPLCOM", "external feedback" };
202static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 203static const char *aic3x_adc_hpf[] =
204 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 205
206#define LDAC_ENUM 0
207#define RDAC_ENUM 1
208#define LHPCOM_ENUM 2
209#define RHPCOM_ENUM 3
404b5665
JN		 210#define LINE1L_2_L_ENUM 4
211#define LINE1L_2_R_ENUM 5
212#define LINE1R_2_L_ENUM 6
213#define LINE1R_2_R_ENUM 7
214#define LINE2L_ENUM 8
215#define LINE2R_ENUM 9
216#define ADC_HPF_ENUM 10
44d0a879
VB		 217
218static const struct soc_enum aic3x_enum[] = {
219 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
220 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
221 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
222 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
223 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
404b5665
JN		 224 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
225 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
44d0a879
VB		 226 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
227 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
228 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 229 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 230};
231
7565fc38
JN		 232/*
233 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
234 */
235static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
236/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
237static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
238/*
239 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
240 * Step size is approximately 0.5 dB over most of the scale but increasing
241 * near the very low levels.
242 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
243 * but having increasing dB difference below that (and where it doesn't count
244 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
245 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
246 */
247static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
248
44d0a879
VB		 249static const struct snd_kcontrol_new aic3x_snd_controls[] = {
250 /* Output */
7565fc38
JN		 251 SOC_DOUBLE_R_TLV("PCM Playback Volume",
252 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 253
098b1718
JN		 254 /*
255 * Output controls that map to output mixer switches. Note these are
256 * only for swapped L-to-R and R-to-L routes. See below stereo controls
257 * for direct L-to-L and R-to-R routes.
258 */
259 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
260 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
261 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
262 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
263 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
264 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
265
266 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
267 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
268 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
269 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
270 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
271 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
272
273 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
274 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
275 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
276 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
277 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
278 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
279
280 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
281 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
282 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
283 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
284 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
285 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
286
287 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
288 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
289 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
290 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
291 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
292 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
293
294 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
295 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
296 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
297 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
299 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
300
301 /* Stereo output controls for direct L-to-L and R-to-R routes */
302 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
303 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
304 0, 118, 1, output_stage_tlv),
305 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
306 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
307 0, 118, 1, output_stage_tlv),
7565fc38
JN		 308 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
309 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
310 0, 118, 1, output_stage_tlv),
098b1718
JN		 311
312 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
313 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 314 0, 118, 1, output_stage_tlv),
098b1718
JN		 315 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
316 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 317 0, 118, 1, output_stage_tlv),
7565fc38
JN		 318 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
319 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
320 0, 118, 1, output_stage_tlv),
098b1718
JN		 321
322 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
323 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 324 0, 118, 1, output_stage_tlv),
098b1718
JN		 325 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
326 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 327 0, 118, 1, output_stage_tlv),
7565fc38
JN		 328 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
329 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
330 0, 118, 1, output_stage_tlv),
098b1718
JN		 331
332 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
333 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 334 0, 118, 1, output_stage_tlv),
098b1718
JN		 335 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
336 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 337 0, 118, 1, output_stage_tlv),
7565fc38
JN		 338 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
339 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
340 0, 118, 1, output_stage_tlv),
098b1718
JN		 341
342 /* Output pin mute controls */
343 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
344 0x01, 0),
345 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
346 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
347 0x01, 0),
f9bc0297 348 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 349 0x01, 0),
44d0a879
VB		 350
351 /*
352 * Note: enable Automatic input Gain Controller with care. It can
353 * adjust PGA to max value when ADC is on and will never go back.
354 */
355 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
356
357 /* Input */
7565fc38
JN		 358 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
359 0, 119, 0, adc_tlv),
44d0a879 360 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 361
362 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 363};
364
6184f105
RC		 365/*
366 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
367 */
368static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
369
370static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
371 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
372
44d0a879
VB		 373/* Left DAC Mux */
374static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
375SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
376
377/* Right DAC Mux */
378static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
379SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
380
381/* Left HPCOM Mux */
382static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
383SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
384
385/* Right HPCOM Mux */
386static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
387SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
388
c3b79e05
JN		 389/* Left Line Mixer */
390static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
391 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
392 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
393 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
394 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
395 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
396 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 397};
398
c3b79e05
JN		 399/* Right Line Mixer */
400static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
401 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
402 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
403 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
407};
408
409/* Mono Mixer */
410static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
411 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
412 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
413 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
414 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
417};
418
419/* Left HP Mixer */
420static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
421 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
422 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
423 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
427};
428
429/* Right HP Mixer */
430static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
431 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
437};
438
439/* Left HPCOM Mixer */
440static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
441 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
442 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
447};
448
449/* Right HPCOM Mixer */
450static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
451 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 457};
458
459/* Left PGA Mixer */
460static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
461 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 462 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 463 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
464 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 465 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 466};
467
468/* Right PGA Mixer */
469static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
470 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 471 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 472 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 473 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 474 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
475};
476
477/* Left Line1 Mux */
404b5665
JN		 478static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
479SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
480static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
481SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
44d0a879
VB		 482
483/* Right Line1 Mux */
404b5665
JN		 484static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
485SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
486static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
487SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
44d0a879
VB		 488
489/* Left Line2 Mux */
490static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
491SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
492
493/* Right Line2 Mux */
494static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
495SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
496
44d0a879
VB		 497static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
498 /* Left DAC to Left Outputs */
499 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
500 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
501 &aic3x_left_dac_mux_controls),
44d0a879
VB		 502 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
503 &aic3x_left_hpcom_mux_controls),
504 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
505 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
506 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
507
508 /* Right DAC to Right Outputs */
509 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
510 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
511 &aic3x_right_dac_mux_controls),
44d0a879
VB		 512 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
513 &aic3x_right_hpcom_mux_controls),
514 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
515 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
516 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
517
518 /* Mono Output */
519 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
520
54f01916 521 /* Inputs to Left ADC */
44d0a879
VB		 522 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
523 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
524 &aic3x_left_pga_mixer_controls[0],
525 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
526 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 527 &aic3x_left_line1l_mux_controls),
54f01916 528 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 529 &aic3x_left_line1r_mux_controls),
44d0a879
VB		 530 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
531 &aic3x_left_line2_mux_controls),
532
54f01916 533 /* Inputs to Right ADC */
44d0a879
VB		 534 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
535 LINE1R_2_RADC_CTRL, 2, 0),
536 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
537 &aic3x_right_pga_mixer_controls[0],
538 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916 539 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 540 &aic3x_right_line1l_mux_controls),
44d0a879 541 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 542 &aic3x_right_line1r_mux_controls),
44d0a879
VB		 543 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
544 &aic3x_right_line2_mux_controls),
545
ee15ffdb
JN		 546 /*
547 * Not a real mic bias widget but similar function. This is for dynamic
548 * control of GPIO1 digital mic modulator clock output function when
549 * using digital mic.
550 */
551 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
552 AIC3X_GPIO1_REG, 4, 0xf,
553 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
554 AIC3X_GPIO1_FUNC_DISABLED),
555
556 /*
557 * Also similar function like mic bias. Selects digital mic with
558 * configurable oversampling rate instead of ADC converter.
559 */
560 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
561 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
562 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
563 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
564 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
565 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
566
44d0a879 567 /* Mic Bias */
0bd72a3d
JN		 568 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
569 MICBIAS_CTRL, 6, 3, 1, 0),
570 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
571 MICBIAS_CTRL, 6, 3, 2, 0),
572 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
573 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 574
c3b79e05
JN		 575 /* Output mixers */
576 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
577 &aic3x_left_line_mixer_controls[0],
578 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
579 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
580 &aic3x_right_line_mixer_controls[0],
581 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
582 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
583 &aic3x_mono_mixer_controls[0],
584 ARRAY_SIZE(aic3x_mono_mixer_controls)),
585 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
586 &aic3x_left_hp_mixer_controls[0],
587 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
588 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
589 &aic3x_right_hp_mixer_controls[0],
590 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
591 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
592 &aic3x_left_hpcom_mixer_controls[0],
593 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
594 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
595 &aic3x_right_hpcom_mixer_controls[0],
596 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 597
598 SND_SOC_DAPM_OUTPUT("LLOUT"),
599 SND_SOC_DAPM_OUTPUT("RLOUT"),
600 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
601 SND_SOC_DAPM_OUTPUT("HPLOUT"),
602 SND_SOC_DAPM_OUTPUT("HPROUT"),
603 SND_SOC_DAPM_OUTPUT("HPLCOM"),
604 SND_SOC_DAPM_OUTPUT("HPRCOM"),
605
606 SND_SOC_DAPM_INPUT("MIC3L"),
607 SND_SOC_DAPM_INPUT("MIC3R"),
608 SND_SOC_DAPM_INPUT("LINE1L"),
609 SND_SOC_DAPM_INPUT("LINE1R"),
610 SND_SOC_DAPM_INPUT("LINE2L"),
611 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 612
613 /*
614 * Virtual output pin to detection block inside codec. This can be
615 * used to keep codec bias on if gpio or detection features are needed.
616 * Force pin on or construct a path with an input jack and mic bias
617 * widgets.
618 */
619 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 620};
621
6184f105
RC		 622static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
623 /* Class-D outputs */
624 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
625 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
626
627 SND_SOC_DAPM_OUTPUT("SPOP"),
628 SND_SOC_DAPM_OUTPUT("SPOM"),
629};
630
d0cc0d3a 631static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 632 /* Left Input */
633 {"Left Line1L Mux", "single-ended", "LINE1L"},
634 {"Left Line1L Mux", "differential", "LINE1L"},
635
636 {"Left Line2L Mux", "single-ended", "LINE2L"},
637 {"Left Line2L Mux", "differential", "LINE2L"},
638
639 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 640 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 641 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
642 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 643 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 644
645 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 646 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 647
648 /* Right Input */
649 {"Right Line1R Mux", "single-ended", "LINE1R"},
650 {"Right Line1R Mux", "differential", "LINE1R"},
651
652 {"Right Line2R Mux", "single-ended", "LINE2R"},
653 {"Right Line2R Mux", "differential", "LINE2R"},
654
54f01916 655 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 656 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
657 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 658 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 659 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
660
661 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 662 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 663
ee15ffdb
JN		 664 /*
665 * Logical path between digital mic enable and GPIO1 modulator clock
666 * output function
667 */
668 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
669 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
670 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 671
672 /* Left DAC Output */
673 {"Left DAC Mux", "DAC_L1", "Left DAC"},
674 {"Left DAC Mux", "DAC_L2", "Left DAC"},
675 {"Left DAC Mux", "DAC_L3", "Left DAC"},
676
677 /* Right DAC Output */
678 {"Right DAC Mux", "DAC_R1", "Right DAC"},
679 {"Right DAC Mux", "DAC_R2", "Right DAC"},
680 {"Right DAC Mux", "DAC_R3", "Right DAC"},
681
682 /* Left Line Output */
683 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
684 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
685 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
686 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
687 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
688 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
689
690 {"Left Line Out", NULL, "Left Line Mixer"},
691 {"Left Line Out", NULL, "Left DAC Mux"},
692 {"LLOUT", NULL, "Left Line Out"},
693
694 /* Right Line Output */
695 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
696 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
697 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
698 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
699 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
700 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
701
702 {"Right Line Out", NULL, "Right Line Mixer"},
703 {"Right Line Out", NULL, "Right DAC Mux"},
704 {"RLOUT", NULL, "Right Line Out"},
705
706 /* Mono Output */
707 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
708 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
709 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
710 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
711 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
712 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
713
714 {"Mono Out", NULL, "Mono Mixer"},
715 {"MONO_LOUT", NULL, "Mono Out"},
716
717 /* Left HP Output */
718 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
719 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
720 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
721 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
722 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
723 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
724
725 {"Left HP Out", NULL, "Left HP Mixer"},
726 {"Left HP Out", NULL, "Left DAC Mux"},
727 {"HPLOUT", NULL, "Left HP Out"},
728
729 /* Right HP Output */
730 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
731 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
732 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
733 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
734 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
735 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
736
737 {"Right HP Out", NULL, "Right HP Mixer"},
738 {"Right HP Out", NULL, "Right DAC Mux"},
739 {"HPROUT", NULL, "Right HP Out"},
740
741 /* Left HPCOM Output */
742 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
743 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
744 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
745 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
746 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
747 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
748
749 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
750 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
751 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
752 {"Left HP Com", NULL, "Left HPCOM Mux"},
753 {"HPLCOM", NULL, "Left HP Com"},
754
755 /* Right HPCOM Output */
756 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
757 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
758 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
759 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
760 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
761 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
762
763 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
764 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
765 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
766 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
767 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
768 {"Right HP Com", NULL, "Right HPCOM Mux"},
769 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 770};
771
6184f105
RC		 772static const struct snd_soc_dapm_route intercon_3007[] = {
773 /* Class-D outputs */
774 {"Left Class-D Out", NULL, "Left Line Out"},
775 {"Right Class-D Out", NULL, "Left Line Out"},
776 {"SPOP", NULL, "Left Class-D Out"},
777 {"SPOM", NULL, "Right Class-D Out"},
778};
779
44d0a879
VB		 780static int aic3x_add_widgets(struct snd_soc_codec *codec)
781{
6184f105 782 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 783 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 784
ce6120cc 785 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
d0cc0d3a 786 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 787
788 /* set up audio path interconnects */
ce6120cc 789 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
44d0a879 790
6184f105 791 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 792 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 793 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 794 snd_soc_dapm_add_routes(dapm, intercon_3007,
795 ARRAY_SIZE(intercon_3007));
6184f105
RC		 796 }
797
44d0a879
VB		 798 return 0;
799}
800
44d0a879 801static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 802 struct snd_pcm_hw_params *params,
803 struct snd_soc_dai *dai)
44d0a879 804{
e6968a17 805 struct snd_soc_codec *codec = dai->codec;
b2c812e2 806 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 807 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 808 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
809 u16 d, pll_d = 1;
255173b4 810 int clk;
44d0a879 811
4f9c16cc 812 /* select data word length */
e18eca43 813 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 814 switch (params_format(params)) {
815 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 816 break;
4f9c16cc
DM		 817 case SNDRV_PCM_FORMAT_S20_3LE:
818 data |= (0x01 << 4);
44d0a879 819 break;
4f9c16cc
DM		 820 case SNDRV_PCM_FORMAT_S24_LE:
821 data |= (0x02 << 4);
44d0a879 822 break;
4f9c16cc
DM		 823 case SNDRV_PCM_FORMAT_S32_LE:
824 data |= (0x03 << 4);
44d0a879
VB		 825 break;
826 }
e18eca43 827 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 828
829 /* Fsref can be 44100 or 48000 */
830 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
831
832 /* Try to find a value for Q which allows us to bypass the PLL and
833 * generate CODEC_CLK directly. */
834 for (pll_q = 2; pll_q < 18; pll_q++)
835 if (aic3x->sysclk / (128 * pll_q) == fsref) {
836 bypass_pll = 1;
837 break;
838 }
839
840 if (bypass_pll) {
841 pll_q &= 0xf;
e18eca43
JN		 842 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
843 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 844 /* disable PLL if it is bypassed */
9c173d15 845 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
06c71282
C		 846
847 } else {
e18eca43 848 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 849 /* enable PLL when it is used */
9c173d15
AL		 850 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
851 PLL_ENABLE, PLL_ENABLE);
06c71282 852 }
4f9c16cc
DM		 853
854 /* Route Left DAC to left channel input and
855 * right DAC to right channel input */
856 data = (LDAC2LCH | RDAC2RCH);
857 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
858 if (params_rate(params) >= 64000)
859 data |= DUAL_RATE_MODE;
e18eca43 860 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 861
862 /* codec sample rate select */
4f9c16cc
DM		 863 data = (fsref * 20) / params_rate(params);
864 if (params_rate(params) < 64000)
865 data /= 2;
866 data /= 5;
867 data -= 2;
44d0a879 868 data |= (data << 4);
e18eca43 869 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 870
4f9c16cc
DM		 871 if (bypass_pll)
872 return 0;
873
25985edc 874 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 875 * one wins the game. Try with d==0 first, next with d!=0.
876 * Constraints for j are according to the datasheet.
4f9c16cc 877 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 878 */
255173b4 879
4f9c16cc
DM		 880 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
881
882 for (r = 1; r <= 16; r++)
883 for (p = 1; p <= 8; p++) {
255173b4
PM		 884 for (j = 4; j <= 55; j++) {
885 /* This is actually 1000*((j+(d/10000))*r)/p
886 * The term had to be converted to get
887 * rid of the division by 10000; d = 0 here
888 */
5baf8315 889 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 890
891 /* Check whether this values get closer than
892 * the best ones we had before
893 */
5baf8315 894 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 895 abs(codec_clk - last_clk)) {
896 pll_j = j; pll_d = 0;
897 pll_r = r; pll_p = p;
5baf8315 898 last_clk = tmp_clk;
255173b4
PM		 899 }
900
901 /* Early exit for exact matches */
5baf8315 902 if (tmp_clk == codec_clk)
255173b4
PM		 903 goto found;
904 }
905 }
4f9c16cc 906
255173b4
PM		 907 /* try with d != 0 */
908 for (p = 1; p <= 8; p++) {
909 j = codec_clk * p / 1000;
4f9c16cc 910
255173b4
PM		 911 if (j < 4 || j > 11)
912 continue;
4f9c16cc 913
255173b4
PM		 914 /* do not use codec_clk here since we'd loose precision */
915 d = ((2048 * p * fsref) - j * aic3x->sysclk)
916 * 100 / (aic3x->sysclk/100);
4f9c16cc 917
255173b4 918 clk = (10000 * j + d) / (10 * p);
4f9c16cc 919
255173b4
PM		 920 /* check whether this values get closer than the best
921 * ones we had before */
922 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
923 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
924 last_clk = clk;
4f9c16cc
DM		 925 }
926
255173b4
PM		 927 /* Early exit for exact matches */
928 if (clk == codec_clk)
929 goto found;
930 }
931
4f9c16cc
DM		 932 if (last_clk == 0) {
933 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
934 return -EINVAL;
935 }
44d0a879 936
255173b4 937found:
e18eca43
JN		 938 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
939 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
940 data | (pll_p << PLLP_SHIFT));
941 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
942 pll_r << PLLR_SHIFT);
943 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
944 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
945 (pll_d >> 6) << PLLD_MSB_SHIFT);
946 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
947 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 948
44d0a879
VB		 949 return 0;
950}
951
e550e17f 952static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 953{
954 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 955 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
956 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 957
958 if (mute) {
e18eca43
JN		 959 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
960 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 961 } else {
e18eca43
JN		 962 snd_soc_write(codec, LDAC_VOL, ldac_reg);
963 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 964 }
965
966 return 0;
967}
968
e550e17f 969static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 970 int clk_id, unsigned int freq, int dir)
971{
972 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 973 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 974
4f9c16cc
DM		 975 aic3x->sysclk = freq;
976 return 0;
44d0a879
VB		 977}
978
e550e17f 979static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 980 unsigned int fmt)
981{
982 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 983 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 984 u8 iface_areg, iface_breg;
a24f4f68 985 int delay = 0;
81971a14 986
e18eca43
JN		 987 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
988 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 989
990 /* set master/slave audio interface */
991 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
992 case SND_SOC_DAIFMT_CBM_CFM:
993 aic3x->master = 1;
994 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
995 break;
996 case SND_SOC_DAIFMT_CBS_CFS:
997 aic3x->master = 0;
68e47981 998 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
44d0a879
VB		 999 break;
1000 default:
1001 return -EINVAL;
1002 }
1003
4b7d2831
JN		 1004 /*
1005 * match both interface format and signal polarities since they
1006 * are fixed
1007 */
1008 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1009 SND_SOC_DAIFMT_INV_MASK)) {
1010 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1011 break;
a24f4f68
TK		 1012 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1013 delay = 1;
4b7d2831 1014 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1015 iface_breg |= (0x01 << 6);
1016 break;
4b7d2831 1017 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1018 iface_breg |= (0x02 << 6);
1019 break;
4b7d2831 1020 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1021 iface_breg |= (0x03 << 6);
1022 break;
1023 default:
1024 return -EINVAL;
1025 }
1026
1027 /* set iface */
e18eca43
JN		 1028 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1029 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1030 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1031
1032 return 0;
1033}
1034
6c1a7d40
JN		 1035static int aic3x_init_3007(struct snd_soc_codec *codec)
1036{
1037 u8 tmp1, tmp2, *cache = codec->reg_cache;
1038
1039 /*
1040 * There is no need to cache writes to undocumented page 0xD but
1041 * respective page 0 register cache entries must be preserved
1042 */
1043 tmp1 = cache[0xD];
1044 tmp2 = cache[0x8];
1045 /* Class-D speaker driver init; datasheet p. 46 */
1046 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1047 snd_soc_write(codec, 0xD, 0x0D);
1048 snd_soc_write(codec, 0x8, 0x5C);
1049 snd_soc_write(codec, 0x8, 0x5D);
1050 snd_soc_write(codec, 0x8, 0x5C);
1051 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1052 cache[0xD] = tmp1;
1053 cache[0x8] = tmp2;
1054
1055 return 0;
1056}
1057
5a895f8a
JN		 1058static int aic3x_regulator_event(struct notifier_block *nb,
1059 unsigned long event, void *data)
1060{
1061 struct aic3x_disable_nb *disable_nb =
1062 container_of(nb, struct aic3x_disable_nb, nb);
1063 struct aic3x_priv *aic3x = disable_nb->aic3x;
1064
1065 if (event & REGULATOR_EVENT_DISABLE) {
1066 /*
1067 * Put codec to reset and require cache sync as at least one
1068 * of the supplies was disabled
1069 */
79ee820d 1070 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a
JN		 1071 gpio_set_value(aic3x->gpio_reset, 0);
1072 aic3x->codec->cache_sync = 1;
1073 }
1074
1075 return 0;
1076}
1077
6c1a7d40
JN		 1078static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1079{
1080 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1081 int i, ret;
1082 u8 *cache = codec->reg_cache;
1083
1084 if (power) {
1085 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1086 aic3x->supplies);
1087 if (ret)
1088 goto out;
1089 aic3x->power = 1;
5a895f8a
JN		 1090 /*
1091 * Reset release and cache sync is necessary only if some
1092 * supply was off or if there were cached writes
1093 */
1094 if (!codec->cache_sync)
1095 goto out;
1096
79ee820d 1097 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1098 udelay(1);
1099 gpio_set_value(aic3x->gpio_reset, 1);
1100 }
1101
1102 /* Sync reg_cache with the hardware */
1103 codec->cache_only = 0;
508b7686 1104 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
6c1a7d40
JN		 1105 snd_soc_write(codec, i, cache[i]);
1106 if (aic3x->model == AIC3X_MODEL_3007)
1107 aic3x_init_3007(codec);
1108 codec->cache_sync = 0;
1109 } else {
9fb352b1
JN		 1110 /*
1111 * Do soft reset to this codec instance in order to clear
1112 * possible VDD leakage currents in case the supply regulators
1113 * remain on
1114 */
1115 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1116 codec->cache_sync = 1;
6c1a7d40 1117 aic3x->power = 0;
5a895f8a
JN		 1118 /* HW writes are needless when bias is off */
1119 codec->cache_only = 1;
6c1a7d40
JN		 1120 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1121 aic3x->supplies);
1122 }
1123out:
1124 return ret;
1125}
1126
0be9898a
MB		 1127static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1128 enum snd_soc_bias_level level)
44d0a879 1129{
b2c812e2 1130 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1131
0be9898a
MB		 1132 switch (level) {
1133 case SND_SOC_BIAS_ON:
db13802e
JN		 1134 break;
1135 case SND_SOC_BIAS_PREPARE:
ce6120cc 1136 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1137 aic3x->master) {
44d0a879 1138 /* enable pll */
9c173d15
AL		 1139 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1140 PLL_ENABLE, PLL_ENABLE);
44d0a879
VB		 1141 }
1142 break;
0be9898a 1143 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1144 if (!aic3x->power)
1145 aic3x_set_power(codec, 1);
ce6120cc 1146 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1147 aic3x->master) {
44d0a879 1148 /* disable pll */
9c173d15
AL		 1149 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1150 PLL_ENABLE, 0);
44d0a879
VB		 1151 }
1152 break;
c23fd751 1153 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1154 if (aic3x->power)
1155 aic3x_set_power(codec, 0);
c23fd751 1156 break;
44d0a879 1157 }
ce6120cc 1158 codec->dapm.bias_level = level;
44d0a879
VB		 1159
1160 return 0;
1161}
1162
1163#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1164#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1165 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1166
85e7652d 1167static const struct snd_soc_dai_ops aic3x_dai_ops = {
6335d055
EM		 1168 .hw_params = aic3x_hw_params,
1169 .digital_mute = aic3x_mute,
1170 .set_sysclk = aic3x_set_dai_sysclk,
1171 .set_fmt = aic3x_set_dai_fmt,
1172};
1173
f0fba2ad
LG		 1174static struct snd_soc_dai_driver aic3x_dai = {
1175 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1176 .playback = {
1177 .stream_name = "Playback",
1178 .channels_min = 1,
1179 .channels_max = 2,
1180 .rates = AIC3X_RATES,
1181 .formats = AIC3X_FORMATS,},
1182 .capture = {
1183 .stream_name = "Capture",
1184 .channels_min = 1,
1185 .channels_max = 2,
1186 .rates = AIC3X_RATES,
1187 .formats = AIC3X_FORMATS,},
6335d055 1188 .ops = &aic3x_dai_ops,
14017615 1189 .symmetric_rates = 1,
44d0a879 1190};
44d0a879 1191
84b315ee 1192static int aic3x_suspend(struct snd_soc_codec *codec)
44d0a879 1193{
0be9898a 1194 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1195
1196 return 0;
1197}
1198
f0fba2ad 1199static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1200{
29e189c2 1201 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1202
1203 return 0;
1204}
1205
1206/*
1207 * initialise the AIC3X driver
1208 * register the mixer and dsp interfaces with the kernel
1209 */
cb3826f5 1210static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1211{
6184f105 1212 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5 1213
e18eca43
JN		 1214 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1215 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1216
44d0a879 1217 /* DAC default volume and mute */
e18eca43
JN		 1218 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1219 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1220
1221 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1222 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1223 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1224 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1225 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1226 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1227 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1228 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1229 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1230 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1231 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1232
1233 /* unmute all outputs */
9c173d15
AL		 1234 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1235 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1236 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1237 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1238 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1239 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1240 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
44d0a879
VB		 1241
1242 /* ADC default volume and unmute */
e18eca43
JN		 1243 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1244 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1245 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1246 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1247 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1248
1249 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1250 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1251 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1252 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1253 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1254 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1255 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1256 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1257 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1258 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1259 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1260
1261 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1262 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1263 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1264 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1265 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1266 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1267 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1268 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1269 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1270 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1271 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1272
6184f105 1273 if (aic3x->model == AIC3X_MODEL_3007) {
6c1a7d40 1274 aic3x_init_3007(codec);
e18eca43 1275 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1276 }
1277
cb3826f5
BD		 1278 return 0;
1279}
54e7e616 1280
414c73ab
JN		 1281static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1282{
1283 struct aic3x_priv *a;
1284
1285 list_for_each_entry(a, &reset_list, list) {
1286 if (gpio_is_valid(aic3x->gpio_reset) &&
1287 aic3x->gpio_reset == a->gpio_reset)
1288 return true;
1289 }
1290
1291 return false;
1292}
1293
f0fba2ad 1294static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1295{
f0fba2ad 1296 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1297 int ret, i;
f0fba2ad 1298
414c73ab 1299 INIT_LIST_HEAD(&aic3x->list);
5a895f8a 1300 aic3x->codec = codec;
cb3826f5 1301
a84a441b
JN		 1302 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1303 if (ret != 0) {
1304 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1305 return ret;
1306 }
1307
414c73ab
JN		 1308 if (gpio_is_valid(aic3x->gpio_reset) &&
1309 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1310 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1311 if (ret != 0)
1312 goto err_gpio;
1313 gpio_direction_output(aic3x->gpio_reset, 0);
1314 }
1315
1316 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1317 aic3x->supplies[i].supply = aic3x_supply_names[i];
1318
1319 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1320 aic3x->supplies);
1321 if (ret != 0) {
1322 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1323 goto err_get;
1324 }
5a895f8a
JN		 1325 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1326 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1327 aic3x->disable_nb[i].aic3x = aic3x;
1328 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1329 &aic3x->disable_nb[i].nb);
1330 if (ret) {
1331 dev_err(codec->dev,
1332 "Failed to request regulator notifier: %d\n",
1333 ret);
1334 goto err_notif;
1335 }
1336 }
2f24111a 1337
7d1be0a6 1338 codec->cache_only = 1;
37b47656
JN		 1339 aic3x_init(codec);
1340
f0fba2ad
LG		 1341 if (aic3x->setup) {
1342 /* setup GPIO functions */
e18eca43
JN		 1343 snd_soc_write(codec, AIC3X_GPIO1_REG,
1344 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1345 snd_soc_write(codec, AIC3X_GPIO2_REG,
1346 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1347 }
1348
022658be 1349 snd_soc_add_codec_controls(codec, aic3x_snd_controls,
f0fba2ad 1350 ARRAY_SIZE(aic3x_snd_controls));
6184f105 1351 if (aic3x->model == AIC3X_MODEL_3007)
022658be 1352 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1353
f0fba2ad 1354 aic3x_add_widgets(codec);
414c73ab 1355 list_add(&aic3x->list, &reset_list);
cb3826f5
BD		 1356
1357 return 0;
2f24111a 1358
5a895f8a
JN		 1359err_notif:
1360 while (i--)
1361 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1362 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1363 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1364err_get:
414c73ab
JN		 1365 if (gpio_is_valid(aic3x->gpio_reset) &&
1366 !aic3x_is_shared_reset(aic3x))
2f24111a
JN		 1367 gpio_free(aic3x->gpio_reset);
1368err_gpio:
2f24111a 1369 return ret;
44d0a879
VB		 1370}
1371
f0fba2ad 1372static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1373{
2f24111a 1374 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1375 int i;
2f24111a 1376
f0fba2ad 1377 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
414c73ab
JN		 1378 list_del(&aic3x->list);
1379 if (gpio_is_valid(aic3x->gpio_reset) &&
1380 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1381 gpio_set_value(aic3x->gpio_reset, 0);
1382 gpio_free(aic3x->gpio_reset);
1383 }
5a895f8a
JN		 1384 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1385 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1386 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1387 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1388
cb3826f5
BD		 1389 return 0;
1390}
44d0a879 1391
f0fba2ad 1392static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad 1393 .set_bias_level = aic3x_set_bias_level,
eb3032f8 1394 .idle_bias_off = true,
f0fba2ad
LG		 1395 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1396 .reg_word_size = sizeof(u8),
1397 .reg_cache_default = aic3x_reg,
1398 .probe = aic3x_probe,
1399 .remove = aic3x_remove,
1400 .suspend = aic3x_suspend,
1401 .resume = aic3x_resume,
1402};
1403
44d0a879
VB		 1404/*
1405 * AIC3X 2 wire address can be up to 4 devices with device addresses
1406 * 0x18, 0x19, 0x1A, 0x1B
1407 */
44d0a879 1408
6184f105 1409static const struct i2c_device_id aic3x_i2c_id[] = {
177fdd89
AL		 1410 { "tlv320aic3x", AIC3X_MODEL_3X },
1411 { "tlv320aic33", AIC3X_MODEL_33 },
1412 { "tlv320aic3007", AIC3X_MODEL_3007 },
6184f105
RC		 1413 { }
1414};
1415MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1416
44d0a879
VB		 1417/*
1418 * If the i2c layer weren't so broken, we could pass this kind of data
1419 * around
1420 */
ba8ed121
JD		 1421static int aic3x_i2c_probe(struct i2c_client *i2c,
1422 const struct i2c_device_id *id)
44d0a879 1423{
5193d62f 1424 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1425 struct aic3x_priv *aic3x;
2f24111a 1426 int ret;
44d0a879 1427
e2257db3 1428 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
cb3826f5
BD		 1429 if (aic3x == NULL) {
1430 dev_err(&i2c->dev, "failed to create private data\n");
1431 return -ENOMEM;
1432 }
1433
a84a441b
JN		 1434 aic3x->control_type = SND_SOC_I2C;
1435
cb3826f5 1436 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1437 if (pdata) {
1438 aic3x->gpio_reset = pdata->gpio_reset;
1439 aic3x->setup = pdata->setup;
1440 } else {
1441 aic3x->gpio_reset = -1;
1442 }
cb3826f5 1443
177fdd89 1444 aic3x->model = id->driver_data;
6184f105 1445
f0fba2ad
LG		 1446 ret = snd_soc_register_codec(&i2c->dev,
1447 &soc_codec_dev_aic3x, &aic3x_dai, 1);
07779fdd 1448 return ret;
44d0a879
VB		 1449}
1450
ba8ed121 1451static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1452{
f0fba2ad 1453 snd_soc_unregister_codec(&client->dev);
f0fba2ad 1454 return 0;
44d0a879
VB		 1455}
1456
44d0a879
VB		 1457/* machine i2c codec control layer */
1458static struct i2c_driver aic3x_i2c_driver = {
1459 .driver = {
f0fba2ad 1460 .name = "tlv320aic3x-codec",
44d0a879
VB		 1461 .owner = THIS_MODULE,
1462 },
cb3826f5 1463 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1464 .remove = aic3x_i2c_remove,
1465 .id_table = aic3x_i2c_id,
44d0a879 1466};
44d0a879 1467
f0fba2ad 1468static int __init aic3x_modinit(void)
44d0a879 1469{
44d0a879 1470 int ret = 0;
f0fba2ad
LG		 1471 ret = i2c_add_driver(&aic3x_i2c_driver);
1472 if (ret != 0) {
1473 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1474 ret);
44d0a879 1475 }
44d0a879
VB		 1476 return ret;
1477}
64089b84
MB		 1478module_init(aic3x_modinit);
1479
1480static void __exit aic3x_exit(void)
1481{
f0fba2ad 1482 i2c_del_driver(&aic3x_i2c_driver);
64089b84
MB		 1483}
1484module_exit(aic3x_exit);
1485
44d0a879
VB		 1486MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1487MODULE_AUTHOR("Vladimir Barinov");
1488MODULE_LICENSE("GPL");
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