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44d0a879 VB |
1 | /* |
2 | * ALSA SoC TLV320AIC3X codec driver | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
44d0a879 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef _AIC3X_H | |
13 | #define _AIC3X_H | |
14 | ||
15 | /* AIC3X register space */ | |
784a897e | 16 | #define AIC3X_CACHEREGNUM 110 |
44d0a879 VB |
17 | |
18 | /* Page select register */ | |
19 | #define AIC3X_PAGE_SELECT 0 | |
20 | /* Software reset register */ | |
21 | #define AIC3X_RESET 1 | |
22 | /* Codec Sample rate select register */ | |
23 | #define AIC3X_SAMPLE_RATE_SEL_REG 2 | |
24 | /* PLL progrramming register A */ | |
25 | #define AIC3X_PLL_PROGA_REG 3 | |
26 | /* PLL progrramming register B */ | |
27 | #define AIC3X_PLL_PROGB_REG 4 | |
28 | /* PLL progrramming register C */ | |
29 | #define AIC3X_PLL_PROGC_REG 5 | |
30 | /* PLL progrramming register D */ | |
31 | #define AIC3X_PLL_PROGD_REG 6 | |
32 | /* Codec datapath setup register */ | |
33 | #define AIC3X_CODEC_DATAPATH_REG 7 | |
34 | /* Audio serial data interface control register A */ | |
35 | #define AIC3X_ASD_INTF_CTRLA 8 | |
36 | /* Audio serial data interface control register B */ | |
37 | #define AIC3X_ASD_INTF_CTRLB 9 | |
a24f4f68 TK |
38 | /* Audio serial data interface control register C */ |
39 | #define AIC3X_ASD_INTF_CTRLC 10 | |
44d0a879 VB |
40 | /* Audio overflow status and PLL R value programming register */ |
41 | #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 | |
4d20f70a JN |
42 | /* Audio codec digital filter control register */ |
43 | #define AIC3X_CODEC_DFILT_CTRL 12 | |
6f2a974b DM |
44 | /* Headset/button press detection register */ |
45 | #define AIC3X_HEADSET_DETECT_CTRL_A 13 | |
46 | #define AIC3X_HEADSET_DETECT_CTRL_B 14 | |
44d0a879 VB |
47 | /* ADC PGA Gain control registers */ |
48 | #define LADC_VOL 15 | |
49 | #define RADC_VOL 16 | |
50 | /* MIC3 control registers */ | |
51 | #define MIC3LR_2_LADC_CTRL 17 | |
52 | #define MIC3LR_2_RADC_CTRL 18 | |
53 | /* Line1 Input control registers */ | |
54 | #define LINE1L_2_LADC_CTRL 19 | |
54f01916 | 55 | #define LINE1R_2_LADC_CTRL 21 |
44d0a879 | 56 | #define LINE1R_2_RADC_CTRL 22 |
54f01916 | 57 | #define LINE1L_2_RADC_CTRL 24 |
44d0a879 VB |
58 | /* Line2 Input control registers */ |
59 | #define LINE2L_2_LADC_CTRL 20 | |
60 | #define LINE2R_2_RADC_CTRL 23 | |
61 | /* MICBIAS Control Register */ | |
62 | #define MICBIAS_CTRL 25 | |
63 | ||
64 | /* AGC Control Registers A, B, C */ | |
65 | #define LAGC_CTRL_A 26 | |
66 | #define LAGC_CTRL_B 27 | |
67 | #define LAGC_CTRL_C 28 | |
68 | #define RAGC_CTRL_A 29 | |
69 | #define RAGC_CTRL_B 30 | |
70 | #define RAGC_CTRL_C 31 | |
71 | ||
72 | /* DAC Power and Left High Power Output control registers */ | |
73 | #define DAC_PWR 37 | |
74 | #define HPLCOM_CFG 37 | |
75 | /* Right High Power Output control registers */ | |
76 | #define HPRCOM_CFG 38 | |
784a897e JP |
77 | /* High Power Output Stage Control Register */ |
78 | #define HPOUT_SC 40 | |
44d0a879 VB |
79 | /* DAC Output Switching control registers */ |
80 | #define DAC_LINE_MUX 41 | |
81 | /* High Power Output Driver Pop Reduction registers */ | |
82 | #define HPOUT_POP_REDUCTION 42 | |
83 | /* DAC Digital control registers */ | |
84 | #define LDAC_VOL 43 | |
85 | #define RDAC_VOL 44 | |
b2eaac20 | 86 | /* Left High Power Output control registers */ |
44d0a879 | 87 | #define LINE2L_2_HPLOUT_VOL 45 |
44d0a879 | 88 | #define PGAL_2_HPLOUT_VOL 46 |
44d0a879 | 89 | #define DACL1_2_HPLOUT_VOL 47 |
c3b79e05 | 90 | #define LINE2R_2_HPLOUT_VOL 48 |
b2eaac20 | 91 | #define PGAR_2_HPLOUT_VOL 49 |
c3b79e05 | 92 | #define DACR1_2_HPLOUT_VOL 50 |
44d0a879 | 93 | #define HPLOUT_CTRL 51 |
b2eaac20 | 94 | /* Left High Power COM control registers */ |
44d0a879 | 95 | #define LINE2L_2_HPLCOM_VOL 52 |
44d0a879 | 96 | #define PGAL_2_HPLCOM_VOL 53 |
b2eaac20 | 97 | #define DACL1_2_HPLCOM_VOL 54 |
c3b79e05 | 98 | #define LINE2R_2_HPLCOM_VOL 55 |
54f01916 | 99 | #define PGAR_2_HPLCOM_VOL 56 |
c3b79e05 | 100 | #define DACR1_2_HPLCOM_VOL 57 |
b2eaac20 JN |
101 | #define HPLCOM_CTRL 58 |
102 | /* Right High Power Output control registers */ | |
c3b79e05 | 103 | #define LINE2L_2_HPROUT_VOL 59 |
b2eaac20 | 104 | #define PGAL_2_HPROUT_VOL 60 |
c3b79e05 | 105 | #define DACL1_2_HPROUT_VOL 61 |
b2eaac20 JN |
106 | #define LINE2R_2_HPROUT_VOL 62 |
107 | #define PGAR_2_HPROUT_VOL 63 | |
108 | #define DACR1_2_HPROUT_VOL 64 | |
109 | #define HPROUT_CTRL 65 | |
110 | /* Right High Power COM control registers */ | |
c3b79e05 | 111 | #define LINE2L_2_HPRCOM_VOL 66 |
54f01916 | 112 | #define PGAL_2_HPRCOM_VOL 67 |
c3b79e05 | 113 | #define DACL1_2_HPRCOM_VOL 68 |
b2eaac20 | 114 | #define LINE2R_2_HPRCOM_VOL 69 |
44d0a879 | 115 | #define PGAR_2_HPRCOM_VOL 70 |
44d0a879 | 116 | #define DACR1_2_HPRCOM_VOL 71 |
44d0a879 VB |
117 | #define HPRCOM_CTRL 72 |
118 | /* Mono Line Output Plus/Minus control registers */ | |
119 | #define LINE2L_2_MONOLOPM_VOL 73 | |
44d0a879 | 120 | #define PGAL_2_MONOLOPM_VOL 74 |
44d0a879 | 121 | #define DACL1_2_MONOLOPM_VOL 75 |
b2eaac20 JN |
122 | #define LINE2R_2_MONOLOPM_VOL 76 |
123 | #define PGAR_2_MONOLOPM_VOL 77 | |
44d0a879 VB |
124 | #define DACR1_2_MONOLOPM_VOL 78 |
125 | #define MONOLOPM_CTRL 79 | |
6184f105 RC |
126 | /* Class-D speaker driver on tlv320aic3007 */ |
127 | #define CLASSD_CTRL 73 | |
b2eaac20 | 128 | /* Left Line Output Plus/Minus control registers */ |
44d0a879 | 129 | #define LINE2L_2_LLOPM_VOL 80 |
44d0a879 | 130 | #define PGAL_2_LLOPM_VOL 81 |
44d0a879 | 131 | #define DACL1_2_LLOPM_VOL 82 |
b2eaac20 JN |
132 | #define LINE2R_2_LLOPM_VOL 83 |
133 | #define PGAR_2_LLOPM_VOL 84 | |
54f01916 | 134 | #define DACR1_2_LLOPM_VOL 85 |
44d0a879 | 135 | #define LLOPM_CTRL 86 |
b2eaac20 JN |
136 | /* Right Line Output Plus/Minus control registers */ |
137 | #define LINE2L_2_RLOPM_VOL 87 | |
138 | #define PGAL_2_RLOPM_VOL 88 | |
139 | #define DACL1_2_RLOPM_VOL 89 | |
140 | #define LINE2R_2_RLOPM_VOL 90 | |
141 | #define PGAR_2_RLOPM_VOL 91 | |
142 | #define DACR1_2_RLOPM_VOL 92 | |
44d0a879 | 143 | #define RLOPM_CTRL 93 |
54e7e616 DM |
144 | /* GPIO/IRQ registers */ |
145 | #define AIC3X_STICKY_IRQ_FLAGS_REG 96 | |
146 | #define AIC3X_RT_IRQ_FLAGS_REG 97 | |
147 | #define AIC3X_GPIO1_REG 98 | |
148 | #define AIC3X_GPIO2_REG 99 | |
149 | #define AIC3X_GPIOA_REG 100 | |
4f9c16cc | 150 | #define AIC3X_GPIOB_REG 101 |
54e7e616 | 151 | /* Clock generation control register */ |
44d0a879 | 152 | #define AIC3X_CLKGEN_CTRL_REG 102 |
784a897e JP |
153 | /* New AGC registers */ |
154 | #define LAGCN_ATTACK 103 | |
155 | #define LAGCN_DECAY 104 | |
156 | #define RAGCN_ATTACK 105 | |
157 | #define RAGCN_DECAY 106 | |
158 | /* New Programmable ADC Digital Path and I2C Bus Condition Register */ | |
159 | #define NEW_ADC_DIGITALPATH 107 | |
160 | /* Passive Analog Signal Bypass Selection During Powerdown Register */ | |
161 | #define PASSIVE_BYPASS 108 | |
162 | /* DAC Quiescent Current Adjustment Register */ | |
163 | #define DAC_ICC_ADJ 109 | |
44d0a879 VB |
164 | |
165 | /* Page select register bits */ | |
166 | #define PAGE0_SELECT 0 | |
167 | #define PAGE1_SELECT 1 | |
168 | ||
169 | /* Audio serial data interface control register A bits */ | |
170 | #define BIT_CLK_MASTER 0x80 | |
171 | #define WORD_CLK_MASTER 0x40 | |
36849409 | 172 | #define DOUT_TRISTATE 0x20 |
44d0a879 VB |
173 | |
174 | /* Codec Datapath setup register 7 */ | |
175 | #define FSREF_44100 (1 << 7) | |
176 | #define FSREF_48000 (0 << 7) | |
177 | #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) | |
178 | #define LDAC2LCH (0x1 << 3) | |
179 | #define RDAC2RCH (0x1 << 1) | |
784a897e JP |
180 | #define LDAC2RCH (0x2 << 3) |
181 | #define RDAC2LCH (0x2 << 1) | |
182 | #define LDAC2MONOMIX (0x3 << 3) | |
183 | #define RDAC2MONOMIX (0x3 << 1) | |
44d0a879 VB |
184 | |
185 | /* PLL registers bitfields */ | |
186 | #define PLLP_SHIFT 0 | |
c9fe573a | 187 | #define PLLP_MASK 7 |
4f9c16cc | 188 | #define PLLQ_SHIFT 3 |
44d0a879 VB |
189 | #define PLLR_SHIFT 0 |
190 | #define PLLJ_SHIFT 2 | |
191 | #define PLLD_MSB_SHIFT 0 | |
192 | #define PLLD_LSB_SHIFT 2 | |
193 | ||
194 | /* Clock generation register bits */ | |
4f9c16cc DM |
195 | #define CODEC_CLKIN_PLLDIV 0 |
196 | #define CODEC_CLKIN_CLKDIV 1 | |
44d0a879 VB |
197 | #define PLL_CLKIN_SHIFT 4 |
198 | #define MCLK_SOURCE 0x0 | |
199 | #define PLL_CLKDIV_SHIFT 0 | |
a1f34af0 JP |
200 | #define PLLCLK_IN_MASK 0x30 |
201 | #define PLLCLK_IN_SHIFT 4 | |
202 | #define CLKDIV_IN_MASK 0xc0 | |
203 | #define CLKDIV_IN_SHIFT 6 | |
204 | /* clock in source */ | |
205 | #define CLKIN_MCLK 0 | |
206 | #define CLKIN_GPIO2 1 | |
207 | #define CLKIN_BCLK 2 | |
44d0a879 VB |
208 | |
209 | /* Software reset register bits */ | |
210 | #define SOFT_RESET 0x80 | |
211 | ||
212 | /* PLL progrramming register A bits */ | |
213 | #define PLL_ENABLE 0x80 | |
214 | ||
215 | /* Route bits */ | |
216 | #define ROUTE_ON 0x80 | |
217 | ||
218 | /* Mute bits */ | |
219 | #define UNMUTE 0x08 | |
220 | #define MUTE_ON 0x80 | |
221 | ||
222 | /* Power bits */ | |
223 | #define LADC_PWR_ON 0x04 | |
224 | #define RADC_PWR_ON 0x04 | |
225 | #define LDAC_PWR_ON 0x80 | |
226 | #define RDAC_PWR_ON 0x40 | |
227 | #define HPLOUT_PWR_ON 0x01 | |
228 | #define HPROUT_PWR_ON 0x01 | |
229 | #define HPLCOM_PWR_ON 0x01 | |
230 | #define HPRCOM_PWR_ON 0x01 | |
231 | #define MONOLOPM_PWR_ON 0x01 | |
232 | #define LLOPM_PWR_ON 0x01 | |
233 | #define RLOPM_PWR_ON 0x01 | |
234 | ||
235 | #define INVERT_VOL(val) (0x7f - val) | |
236 | ||
237 | /* Default output volume (inverted) */ | |
238 | #define DEFAULT_VOL INVERT_VOL(0x50) | |
239 | /* Default input volume */ | |
240 | #define DEFAULT_GAIN 0x20 | |
241 | ||
e2e8bfdf HG |
242 | /* MICBIAS Control Register */ |
243 | #define MICBIAS_LEVEL_SHIFT (6) | |
244 | #define MICBIAS_LEVEL_MASK (3 << 6) | |
245 | ||
6f2a974b DM |
246 | /* headset detection / button API */ |
247 | ||
248 | /* The AIC3x supports detection of stereo headsets (GND + left + right signal) | |
249 | * and cellular headsets (GND + speaker output + microphone input). | |
250 | * It is recommended to enable MIC bias for this function to work properly. | |
251 | * For more information, please refer to the datasheet. */ | |
252 | enum { | |
253 | AIC3X_HEADSET_DETECT_OFF = 0, | |
254 | AIC3X_HEADSET_DETECT_STEREO = 1, | |
255 | AIC3X_HEADSET_DETECT_CELLULAR = 2, | |
256 | AIC3X_HEADSET_DETECT_BOTH = 3 | |
257 | }; | |
258 | ||
259 | enum { | |
260 | AIC3X_HEADSET_DEBOUNCE_16MS = 0, | |
261 | AIC3X_HEADSET_DEBOUNCE_32MS = 1, | |
262 | AIC3X_HEADSET_DEBOUNCE_64MS = 2, | |
263 | AIC3X_HEADSET_DEBOUNCE_128MS = 3, | |
264 | AIC3X_HEADSET_DEBOUNCE_256MS = 4, | |
265 | AIC3X_HEADSET_DEBOUNCE_512MS = 5 | |
266 | }; | |
267 | ||
268 | enum { | |
269 | AIC3X_BUTTON_DEBOUNCE_0MS = 0, | |
270 | AIC3X_BUTTON_DEBOUNCE_8MS = 1, | |
271 | AIC3X_BUTTON_DEBOUNCE_16MS = 2, | |
272 | AIC3X_BUTTON_DEBOUNCE_32MS = 3 | |
273 | }; | |
274 | ||
275 | #define AIC3X_HEADSET_DETECT_ENABLED 0x80 | |
276 | #define AIC3X_HEADSET_DETECT_SHIFT 5 | |
277 | #define AIC3X_HEADSET_DETECT_MASK 3 | |
278 | #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2 | |
279 | #define AIC3X_HEADSET_DEBOUNCE_MASK 7 | |
280 | #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0 | |
281 | #define AIC3X_BUTTON_DEBOUNCE_MASK 3 | |
282 | ||
44d0a879 | 283 | #endif /* _AIC3X_H */ |