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c8bf93f0 PU |
1 | /* |
2 | * ALSA SoC Texas Instruments TLV320DAC33 codec driver | |
3 | * | |
4 | * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com> | |
5 | * | |
6 | * Copyright: (C) 2009 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/moduleparam.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/pm.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/gpio.h> | |
3a7aaed7 | 33 | #include <linux/regulator/consumer.h> |
c8bf93f0 PU |
34 | #include <sound/core.h> |
35 | #include <sound/pcm.h> | |
36 | #include <sound/pcm_params.h> | |
37 | #include <sound/soc.h> | |
38 | #include <sound/soc-dapm.h> | |
39 | #include <sound/initval.h> | |
40 | #include <sound/tlv.h> | |
41 | ||
42 | #include <sound/tlv320dac33-plat.h> | |
43 | #include "tlv320dac33.h" | |
44 | ||
45 | #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words, | |
46 | * 6144 stereo */ | |
47 | #define DAC33_BUFFER_SIZE_SAMPLES 6144 | |
48 | ||
49 | #define NSAMPLE_MAX 5700 | |
50 | ||
51 | #define LATENCY_TIME_MS 20 | |
52 | ||
4260393e PU |
53 | #define MODE7_LTHR 10 |
54 | #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10) | |
55 | ||
76f47127 PU |
56 | #define BURST_BASEFREQ_HZ 49152000 |
57 | ||
f57d2cfa PU |
58 | #define SAMPLES_TO_US(rate, samples) \ |
59 | (1000000000 / ((rate * 1000) / samples)) | |
60 | ||
61 | #define US_TO_SAMPLES(rate, us) \ | |
62 | (rate / (1000000 / us)) | |
63 | ||
64 | ||
c8bf93f0 PU |
65 | static struct snd_soc_codec *tlv320dac33_codec; |
66 | ||
67 | enum dac33_state { | |
68 | DAC33_IDLE = 0, | |
69 | DAC33_PREFILL, | |
70 | DAC33_PLAYBACK, | |
71 | DAC33_FLUSH, | |
72 | }; | |
73 | ||
7427b4b9 PU |
74 | enum dac33_fifo_modes { |
75 | DAC33_FIFO_BYPASS = 0, | |
76 | DAC33_FIFO_MODE1, | |
28e05d98 | 77 | DAC33_FIFO_MODE7, |
7427b4b9 PU |
78 | DAC33_FIFO_LAST_MODE, |
79 | }; | |
80 | ||
3a7aaed7 IK |
81 | #define DAC33_NUM_SUPPLIES 3 |
82 | static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { | |
83 | "AVDD", | |
84 | "DVDD", | |
85 | "IOVDD", | |
86 | }; | |
87 | ||
c8bf93f0 PU |
88 | struct tlv320dac33_priv { |
89 | struct mutex mutex; | |
90 | struct workqueue_struct *dac33_wq; | |
91 | struct work_struct work; | |
92 | struct snd_soc_codec codec; | |
3a7aaed7 | 93 | struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; |
0b61d2b9 | 94 | struct snd_pcm_substream *substream; |
c8bf93f0 PU |
95 | int power_gpio; |
96 | int chip_power; | |
97 | int irq; | |
98 | unsigned int refclk; | |
99 | ||
100 | unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ | |
101 | unsigned int nsample_min; /* nsample should not be lower than | |
102 | * this */ | |
103 | unsigned int nsample_max; /* nsample should not be higher than | |
104 | * this */ | |
7427b4b9 | 105 | enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ |
c8bf93f0 | 106 | unsigned int nsample; /* burst read amount from host */ |
6aceabb4 | 107 | u8 burst_bclkdiv; /* BCLK divider value in burst mode */ |
76f47127 | 108 | unsigned int burst_rate; /* Interface speed in Burst modes */ |
c8bf93f0 | 109 | |
eeb309a8 PU |
110 | int keep_bclk; /* Keep the BCLK continuously running |
111 | * in FIFO modes */ | |
f57d2cfa PU |
112 | spinlock_t lock; |
113 | unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ | |
114 | unsigned long long t_stamp2; /* calculate the FIFO caused delay */ | |
115 | ||
116 | unsigned int mode1_us_burst; /* Time to burst read n number of | |
117 | * samples */ | |
118 | unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ | |
119 | ||
c8bf93f0 PU |
120 | enum dac33_state state; |
121 | }; | |
122 | ||
123 | static const u8 dac33_reg[DAC33_CACHEREGNUM] = { | |
124 | 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ | |
125 | 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ | |
126 | 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ | |
127 | 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ | |
128 | 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ | |
129 | 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ | |
130 | 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ | |
131 | 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ | |
132 | 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ | |
133 | 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ | |
134 | 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ | |
135 | 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ | |
136 | 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ | |
137 | 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ | |
138 | 0x00, 0x00, /* 0x38 - 0x39 */ | |
139 | /* Registers 0x3a - 0x3f are reserved */ | |
140 | 0x00, 0x00, /* 0x3a - 0x3b */ | |
141 | 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ | |
142 | ||
143 | 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ | |
144 | 0x00, 0x80, /* 0x44 - 0x45 */ | |
145 | /* Registers 0x46 - 0x47 are reserved */ | |
146 | 0x80, 0x80, /* 0x46 - 0x47 */ | |
147 | ||
148 | 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ | |
149 | /* Registers 0x4b - 0x7c are reserved */ | |
150 | 0x00, /* 0x4b */ | |
151 | 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ | |
152 | 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ | |
153 | 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ | |
154 | 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ | |
155 | 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ | |
156 | 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ | |
157 | 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ | |
158 | 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ | |
159 | 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ | |
160 | 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ | |
161 | 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ | |
162 | 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ | |
163 | 0x00, /* 0x7c */ | |
164 | ||
165 | 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ | |
166 | }; | |
167 | ||
168 | /* Register read and write */ | |
169 | static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec, | |
170 | unsigned reg) | |
171 | { | |
172 | u8 *cache = codec->reg_cache; | |
173 | if (reg >= DAC33_CACHEREGNUM) | |
174 | return 0; | |
175 | ||
176 | return cache[reg]; | |
177 | } | |
178 | ||
179 | static inline void dac33_write_reg_cache(struct snd_soc_codec *codec, | |
180 | u8 reg, u8 value) | |
181 | { | |
182 | u8 *cache = codec->reg_cache; | |
183 | if (reg >= DAC33_CACHEREGNUM) | |
184 | return; | |
185 | ||
186 | cache[reg] = value; | |
187 | } | |
188 | ||
189 | static int dac33_read(struct snd_soc_codec *codec, unsigned int reg, | |
190 | u8 *value) | |
191 | { | |
b2c812e2 | 192 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
193 | int val; |
194 | ||
195 | *value = reg & 0xff; | |
196 | ||
197 | /* If powered off, return the cached value */ | |
198 | if (dac33->chip_power) { | |
199 | val = i2c_smbus_read_byte_data(codec->control_data, value[0]); | |
200 | if (val < 0) { | |
201 | dev_err(codec->dev, "Read failed (%d)\n", val); | |
202 | value[0] = dac33_read_reg_cache(codec, reg); | |
203 | } else { | |
204 | value[0] = val; | |
205 | dac33_write_reg_cache(codec, reg, val); | |
206 | } | |
207 | } else { | |
208 | value[0] = dac33_read_reg_cache(codec, reg); | |
209 | } | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | static int dac33_write(struct snd_soc_codec *codec, unsigned int reg, | |
215 | unsigned int value) | |
216 | { | |
b2c812e2 | 217 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
218 | u8 data[2]; |
219 | int ret = 0; | |
220 | ||
221 | /* | |
222 | * data is | |
223 | * D15..D8 dac33 register offset | |
224 | * D7...D0 register data | |
225 | */ | |
226 | data[0] = reg & 0xff; | |
227 | data[1] = value & 0xff; | |
228 | ||
229 | dac33_write_reg_cache(codec, data[0], data[1]); | |
230 | if (dac33->chip_power) { | |
231 | ret = codec->hw_write(codec->control_data, data, 2); | |
232 | if (ret != 2) | |
233 | dev_err(codec->dev, "Write failed (%d)\n", ret); | |
234 | else | |
235 | ret = 0; | |
236 | } | |
237 | ||
238 | return ret; | |
239 | } | |
240 | ||
241 | static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg, | |
242 | unsigned int value) | |
243 | { | |
b2c812e2 | 244 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
245 | int ret; |
246 | ||
247 | mutex_lock(&dac33->mutex); | |
248 | ret = dac33_write(codec, reg, value); | |
249 | mutex_unlock(&dac33->mutex); | |
250 | ||
251 | return ret; | |
252 | } | |
253 | ||
254 | #define DAC33_I2C_ADDR_AUTOINC 0x80 | |
255 | static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg, | |
256 | unsigned int value) | |
257 | { | |
b2c812e2 | 258 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
259 | u8 data[3]; |
260 | int ret = 0; | |
261 | ||
262 | /* | |
263 | * data is | |
264 | * D23..D16 dac33 register offset | |
265 | * D15..D8 register data MSB | |
266 | * D7...D0 register data LSB | |
267 | */ | |
268 | data[0] = reg & 0xff; | |
269 | data[1] = (value >> 8) & 0xff; | |
270 | data[2] = value & 0xff; | |
271 | ||
272 | dac33_write_reg_cache(codec, data[0], data[1]); | |
273 | dac33_write_reg_cache(codec, data[0] + 1, data[2]); | |
274 | ||
275 | if (dac33->chip_power) { | |
276 | /* We need to set autoincrement mode for 16 bit writes */ | |
277 | data[0] |= DAC33_I2C_ADDR_AUTOINC; | |
278 | ret = codec->hw_write(codec->control_data, data, 3); | |
279 | if (ret != 3) | |
280 | dev_err(codec->dev, "Write failed (%d)\n", ret); | |
281 | else | |
282 | ret = 0; | |
283 | } | |
284 | ||
285 | return ret; | |
286 | } | |
287 | ||
ef909d67 | 288 | static void dac33_init_chip(struct snd_soc_codec *codec) |
c8bf93f0 | 289 | { |
b2c812e2 | 290 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 291 | |
ef909d67 | 292 | if (unlikely(!dac33->chip_power)) |
c8bf93f0 PU |
293 | return; |
294 | ||
ef909d67 PU |
295 | /* 44-46: DAC Control Registers */ |
296 | /* A : DAC sample rate Fsref/1.5 */ | |
297 | dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); | |
298 | /* B : DAC src=normal, not muted */ | |
299 | dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | | |
300 | DAC33_DACSRCL_LEFT); | |
301 | /* C : (defaults) */ | |
302 | dac33_write(codec, DAC33_DAC_CTRL_C, 0x00); | |
303 | ||
304 | /* 64-65 : L&R DAC power control | |
305 | Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/ | |
306 | dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2)); | |
307 | dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2)); | |
308 | ||
309 | /* 73 : volume soft stepping control, | |
310 | clock source = internal osc (?) */ | |
311 | dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); | |
312 | ||
313 | /* 66 : LOP/LOM Modes */ | |
314 | dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff); | |
315 | ||
316 | /* 68 : LOM inverted from LOP */ | |
317 | dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2)); | |
318 | ||
319 | dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB); | |
320 | ||
321 | /* Restore only selected registers (gains mostly) */ | |
322 | dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, | |
323 | dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); | |
324 | dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL, | |
325 | dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL)); | |
326 | ||
327 | dac33_write(codec, DAC33_LINEL_TO_LLO_VOL, | |
328 | dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); | |
329 | dac33_write(codec, DAC33_LINER_TO_RLO_VOL, | |
330 | dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); | |
c8bf93f0 PU |
331 | } |
332 | ||
239fe55c PU |
333 | static inline void dac33_read_id(struct snd_soc_codec *codec) |
334 | { | |
335 | u8 reg; | |
336 | ||
337 | dac33_read(codec, DAC33_DEVICE_ID_MSB, ®); | |
338 | dac33_read(codec, DAC33_DEVICE_ID_LSB, ®); | |
339 | dac33_read(codec, DAC33_DEVICE_REV_ID, ®); | |
340 | } | |
341 | ||
c8bf93f0 PU |
342 | static inline void dac33_soft_power(struct snd_soc_codec *codec, int power) |
343 | { | |
344 | u8 reg; | |
345 | ||
346 | reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
347 | if (power) | |
348 | reg |= DAC33_PDNALLB; | |
349 | else | |
c3746a07 PU |
350 | reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | |
351 | DAC33_DACRPDNB | DAC33_DACLPDNB); | |
c8bf93f0 PU |
352 | dac33_write(codec, DAC33_PWR_CTRL, reg); |
353 | } | |
354 | ||
3a7aaed7 | 355 | static int dac33_hard_power(struct snd_soc_codec *codec, int power) |
c8bf93f0 | 356 | { |
b2c812e2 | 357 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
3a7aaed7 | 358 | int ret; |
c8bf93f0 PU |
359 | |
360 | mutex_lock(&dac33->mutex); | |
361 | if (power) { | |
3a7aaed7 IK |
362 | ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), |
363 | dac33->supplies); | |
364 | if (ret != 0) { | |
365 | dev_err(codec->dev, | |
366 | "Failed to enable supplies: %d\n", ret); | |
367 | goto exit; | |
c8bf93f0 | 368 | } |
3a7aaed7 IK |
369 | |
370 | if (dac33->power_gpio >= 0) | |
371 | gpio_set_value(dac33->power_gpio, 1); | |
372 | ||
373 | dac33->chip_power = 1; | |
374 | ||
ef909d67 | 375 | dac33_init_chip(codec); |
3a7aaed7 | 376 | |
c8bf93f0 PU |
377 | dac33_soft_power(codec, 1); |
378 | } else { | |
379 | dac33_soft_power(codec, 0); | |
3a7aaed7 | 380 | if (dac33->power_gpio >= 0) |
c8bf93f0 | 381 | gpio_set_value(dac33->power_gpio, 0); |
3a7aaed7 IK |
382 | |
383 | ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), | |
384 | dac33->supplies); | |
385 | if (ret != 0) { | |
386 | dev_err(codec->dev, | |
387 | "Failed to disable supplies: %d\n", ret); | |
388 | goto exit; | |
c8bf93f0 | 389 | } |
3a7aaed7 IK |
390 | |
391 | dac33->chip_power = 0; | |
c8bf93f0 | 392 | } |
c8bf93f0 | 393 | |
3a7aaed7 IK |
394 | exit: |
395 | mutex_unlock(&dac33->mutex); | |
396 | return ret; | |
c8bf93f0 PU |
397 | } |
398 | ||
399 | static int dac33_get_nsample(struct snd_kcontrol *kcontrol, | |
400 | struct snd_ctl_elem_value *ucontrol) | |
401 | { | |
402 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 403 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
404 | |
405 | ucontrol->value.integer.value[0] = dac33->nsample; | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
410 | static int dac33_set_nsample(struct snd_kcontrol *kcontrol, | |
411 | struct snd_ctl_elem_value *ucontrol) | |
412 | { | |
413 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 414 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
415 | int ret = 0; |
416 | ||
417 | if (dac33->nsample == ucontrol->value.integer.value[0]) | |
418 | return 0; | |
419 | ||
420 | if (ucontrol->value.integer.value[0] < dac33->nsample_min || | |
f57d2cfa | 421 | ucontrol->value.integer.value[0] > dac33->nsample_max) { |
c8bf93f0 | 422 | ret = -EINVAL; |
f57d2cfa | 423 | } else { |
c8bf93f0 | 424 | dac33->nsample = ucontrol->value.integer.value[0]; |
f57d2cfa PU |
425 | /* Re calculate the burst time */ |
426 | dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, | |
427 | dac33->nsample); | |
428 | } | |
c8bf93f0 PU |
429 | |
430 | return ret; | |
431 | } | |
432 | ||
7427b4b9 | 433 | static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, |
c8bf93f0 PU |
434 | struct snd_ctl_elem_value *ucontrol) |
435 | { | |
436 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 437 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 438 | |
7427b4b9 | 439 | ucontrol->value.integer.value[0] = dac33->fifo_mode; |
c8bf93f0 PU |
440 | |
441 | return 0; | |
442 | } | |
443 | ||
7427b4b9 | 444 | static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, |
c8bf93f0 PU |
445 | struct snd_ctl_elem_value *ucontrol) |
446 | { | |
447 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 448 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
449 | int ret = 0; |
450 | ||
7427b4b9 | 451 | if (dac33->fifo_mode == ucontrol->value.integer.value[0]) |
c8bf93f0 PU |
452 | return 0; |
453 | /* Do not allow changes while stream is running*/ | |
454 | if (codec->active) | |
455 | return -EPERM; | |
456 | ||
457 | if (ucontrol->value.integer.value[0] < 0 || | |
7427b4b9 | 458 | ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE) |
c8bf93f0 PU |
459 | ret = -EINVAL; |
460 | else | |
7427b4b9 | 461 | dac33->fifo_mode = ucontrol->value.integer.value[0]; |
c8bf93f0 PU |
462 | |
463 | return ret; | |
464 | } | |
465 | ||
7427b4b9 PU |
466 | /* Codec operation modes */ |
467 | static const char *dac33_fifo_mode_texts[] = { | |
28e05d98 | 468 | "Bypass", "Mode 1", "Mode 7" |
7427b4b9 PU |
469 | }; |
470 | ||
471 | static const struct soc_enum dac33_fifo_mode_enum = | |
472 | SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts), | |
473 | dac33_fifo_mode_texts); | |
474 | ||
c8bf93f0 PU |
475 | /* |
476 | * DACL/R digital volume control: | |
477 | * from 0 dB to -63.5 in 0.5 dB steps | |
478 | * Need to be inverted later on: | |
479 | * 0x00 == 0 dB | |
480 | * 0x7f == -63.5 dB | |
481 | */ | |
482 | static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); | |
483 | ||
484 | static const struct snd_kcontrol_new dac33_snd_controls[] = { | |
485 | SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", | |
486 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, | |
487 | 0, 0x7f, 1, dac_digivol_tlv), | |
488 | SOC_DOUBLE_R("DAC Digital Playback Switch", | |
489 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), | |
490 | SOC_DOUBLE_R("Line to Line Out Volume", | |
491 | DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), | |
492 | }; | |
493 | ||
494 | static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = { | |
495 | SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0, | |
496 | dac33_get_nsample, dac33_set_nsample), | |
7427b4b9 PU |
497 | SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, |
498 | dac33_get_fifo_mode, dac33_set_fifo_mode), | |
c8bf93f0 PU |
499 | }; |
500 | ||
501 | /* Analog bypass */ | |
502 | static const struct snd_kcontrol_new dac33_dapm_abypassl_control = | |
503 | SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); | |
504 | ||
505 | static const struct snd_kcontrol_new dac33_dapm_abypassr_control = | |
506 | SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); | |
507 | ||
508 | static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { | |
509 | SND_SOC_DAPM_OUTPUT("LEFT_LO"), | |
510 | SND_SOC_DAPM_OUTPUT("RIGHT_LO"), | |
511 | ||
512 | SND_SOC_DAPM_INPUT("LINEL"), | |
513 | SND_SOC_DAPM_INPUT("LINER"), | |
514 | ||
515 | SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0), | |
516 | SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0), | |
517 | ||
518 | /* Analog bypass */ | |
519 | SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, | |
520 | &dac33_dapm_abypassl_control), | |
521 | SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, | |
522 | &dac33_dapm_abypassr_control), | |
523 | ||
524 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power", | |
525 | DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), | |
526 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power", | |
527 | DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), | |
528 | }; | |
529 | ||
530 | static const struct snd_soc_dapm_route audio_map[] = { | |
531 | /* Analog bypass */ | |
532 | {"Analog Left Bypass", "Switch", "LINEL"}, | |
533 | {"Analog Right Bypass", "Switch", "LINER"}, | |
534 | ||
535 | {"Output Left Amp Power", NULL, "DACL"}, | |
536 | {"Output Right Amp Power", NULL, "DACR"}, | |
537 | ||
538 | {"Output Left Amp Power", NULL, "Analog Left Bypass"}, | |
539 | {"Output Right Amp Power", NULL, "Analog Right Bypass"}, | |
540 | ||
541 | /* output */ | |
542 | {"LEFT_LO", NULL, "Output Left Amp Power"}, | |
543 | {"RIGHT_LO", NULL, "Output Right Amp Power"}, | |
544 | }; | |
545 | ||
546 | static int dac33_add_widgets(struct snd_soc_codec *codec) | |
547 | { | |
548 | snd_soc_dapm_new_controls(codec, dac33_dapm_widgets, | |
549 | ARRAY_SIZE(dac33_dapm_widgets)); | |
550 | ||
551 | /* set up audio path interconnects */ | |
552 | snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); | |
c8bf93f0 PU |
553 | |
554 | return 0; | |
555 | } | |
556 | ||
557 | static int dac33_set_bias_level(struct snd_soc_codec *codec, | |
558 | enum snd_soc_bias_level level) | |
559 | { | |
3a7aaed7 IK |
560 | int ret; |
561 | ||
c8bf93f0 PU |
562 | switch (level) { |
563 | case SND_SOC_BIAS_ON: | |
564 | dac33_soft_power(codec, 1); | |
565 | break; | |
566 | case SND_SOC_BIAS_PREPARE: | |
567 | break; | |
568 | case SND_SOC_BIAS_STANDBY: | |
3a7aaed7 IK |
569 | if (codec->bias_level == SND_SOC_BIAS_OFF) { |
570 | ret = dac33_hard_power(codec, 1); | |
571 | if (ret != 0) | |
572 | return ret; | |
573 | } | |
574 | ||
c8bf93f0 PU |
575 | dac33_soft_power(codec, 0); |
576 | break; | |
577 | case SND_SOC_BIAS_OFF: | |
3a7aaed7 IK |
578 | ret = dac33_hard_power(codec, 0); |
579 | if (ret != 0) | |
580 | return ret; | |
581 | ||
c8bf93f0 PU |
582 | break; |
583 | } | |
584 | codec->bias_level = level; | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
d4f102d4 PU |
589 | static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) |
590 | { | |
591 | struct snd_soc_codec *codec; | |
592 | ||
593 | codec = &dac33->codec; | |
594 | ||
595 | switch (dac33->fifo_mode) { | |
596 | case DAC33_FIFO_MODE1: | |
597 | dac33_write16(codec, DAC33_NSAMPLE_MSB, | |
f4d59328 | 598 | DAC33_THRREG(dac33->nsample + dac33->alarm_threshold)); |
f57d2cfa PU |
599 | |
600 | /* Take the timestamps */ | |
601 | spin_lock_irq(&dac33->lock); | |
602 | dac33->t_stamp2 = ktime_to_us(ktime_get()); | |
603 | dac33->t_stamp1 = dac33->t_stamp2; | |
604 | spin_unlock_irq(&dac33->lock); | |
605 | ||
d4f102d4 PU |
606 | dac33_write16(codec, DAC33_PREFILL_MSB, |
607 | DAC33_THRREG(dac33->alarm_threshold)); | |
f4d59328 PU |
608 | /* Enable Alarm Threshold IRQ with a delay */ |
609 | udelay(SAMPLES_TO_US(dac33->burst_rate, | |
610 | dac33->alarm_threshold)); | |
611 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT); | |
d4f102d4 | 612 | break; |
28e05d98 | 613 | case DAC33_FIFO_MODE7: |
f57d2cfa PU |
614 | /* Take the timestamp */ |
615 | spin_lock_irq(&dac33->lock); | |
616 | dac33->t_stamp1 = ktime_to_us(ktime_get()); | |
617 | /* Move back the timestamp with drain time */ | |
618 | dac33->t_stamp1 -= dac33->mode7_us_to_lthr; | |
619 | spin_unlock_irq(&dac33->lock); | |
620 | ||
28e05d98 | 621 | dac33_write16(codec, DAC33_PREFILL_MSB, |
4260393e | 622 | DAC33_THRREG(MODE7_LTHR)); |
f57d2cfa PU |
623 | |
624 | /* Enable Upper Threshold IRQ */ | |
625 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); | |
28e05d98 | 626 | break; |
d4f102d4 PU |
627 | default: |
628 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
629 | dac33->fifo_mode); | |
630 | break; | |
631 | } | |
632 | } | |
633 | ||
634 | static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) | |
635 | { | |
636 | struct snd_soc_codec *codec; | |
637 | ||
638 | codec = &dac33->codec; | |
639 | ||
640 | switch (dac33->fifo_mode) { | |
641 | case DAC33_FIFO_MODE1: | |
f57d2cfa PU |
642 | /* Take the timestamp */ |
643 | spin_lock_irq(&dac33->lock); | |
644 | dac33->t_stamp2 = ktime_to_us(ktime_get()); | |
645 | spin_unlock_irq(&dac33->lock); | |
646 | ||
d4f102d4 PU |
647 | dac33_write16(codec, DAC33_NSAMPLE_MSB, |
648 | DAC33_THRREG(dac33->nsample)); | |
649 | break; | |
28e05d98 PU |
650 | case DAC33_FIFO_MODE7: |
651 | /* At the moment we are not using interrupts in mode7 */ | |
652 | break; | |
d4f102d4 PU |
653 | default: |
654 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
655 | dac33->fifo_mode); | |
656 | break; | |
657 | } | |
658 | } | |
659 | ||
c8bf93f0 PU |
660 | static void dac33_work(struct work_struct *work) |
661 | { | |
662 | struct snd_soc_codec *codec; | |
663 | struct tlv320dac33_priv *dac33; | |
664 | u8 reg; | |
665 | ||
666 | dac33 = container_of(work, struct tlv320dac33_priv, work); | |
667 | codec = &dac33->codec; | |
668 | ||
669 | mutex_lock(&dac33->mutex); | |
670 | switch (dac33->state) { | |
671 | case DAC33_PREFILL: | |
672 | dac33->state = DAC33_PLAYBACK; | |
d4f102d4 | 673 | dac33_prefill_handler(dac33); |
c8bf93f0 PU |
674 | break; |
675 | case DAC33_PLAYBACK: | |
d4f102d4 | 676 | dac33_playback_handler(dac33); |
c8bf93f0 PU |
677 | break; |
678 | case DAC33_IDLE: | |
679 | break; | |
680 | case DAC33_FLUSH: | |
681 | dac33->state = DAC33_IDLE; | |
682 | /* Mask all interrupts from dac33 */ | |
683 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); | |
684 | ||
685 | /* flush fifo */ | |
686 | reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); | |
687 | reg |= DAC33_FIFOFLUSH; | |
688 | dac33_write(codec, DAC33_FIFO_CTRL_A, reg); | |
689 | break; | |
690 | } | |
691 | mutex_unlock(&dac33->mutex); | |
692 | } | |
693 | ||
694 | static irqreturn_t dac33_interrupt_handler(int irq, void *dev) | |
695 | { | |
696 | struct snd_soc_codec *codec = dev; | |
b2c812e2 | 697 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 698 | |
f57d2cfa PU |
699 | spin_lock(&dac33->lock); |
700 | dac33->t_stamp1 = ktime_to_us(ktime_get()); | |
701 | spin_unlock(&dac33->lock); | |
702 | ||
703 | /* Do not schedule the workqueue in Mode7 */ | |
704 | if (dac33->fifo_mode != DAC33_FIFO_MODE7) | |
705 | queue_work(dac33->dac33_wq, &dac33->work); | |
c8bf93f0 PU |
706 | |
707 | return IRQ_HANDLED; | |
708 | } | |
709 | ||
c8bf93f0 PU |
710 | static void dac33_oscwait(struct snd_soc_codec *codec) |
711 | { | |
712 | int timeout = 20; | |
713 | u8 reg; | |
714 | ||
715 | do { | |
716 | msleep(1); | |
717 | dac33_read(codec, DAC33_INT_OSC_STATUS, ®); | |
718 | } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); | |
719 | if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) | |
720 | dev_err(codec->dev, | |
721 | "internal oscillator calibration failed\n"); | |
722 | } | |
723 | ||
0b61d2b9 PU |
724 | static int dac33_startup(struct snd_pcm_substream *substream, |
725 | struct snd_soc_dai *dai) | |
726 | { | |
727 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
728 | struct snd_soc_device *socdev = rtd->socdev; | |
729 | struct snd_soc_codec *codec = socdev->card->codec; | |
730 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); | |
731 | ||
732 | /* Stream started, save the substream pointer */ | |
733 | dac33->substream = substream; | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
738 | static void dac33_shutdown(struct snd_pcm_substream *substream, | |
739 | struct snd_soc_dai *dai) | |
740 | { | |
741 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
742 | struct snd_soc_device *socdev = rtd->socdev; | |
743 | struct snd_soc_codec *codec = socdev->card->codec; | |
744 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); | |
745 | ||
746 | dac33->substream = NULL; | |
747 | } | |
748 | ||
c8bf93f0 PU |
749 | static int dac33_hw_params(struct snd_pcm_substream *substream, |
750 | struct snd_pcm_hw_params *params, | |
751 | struct snd_soc_dai *dai) | |
752 | { | |
753 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
754 | struct snd_soc_device *socdev = rtd->socdev; | |
755 | struct snd_soc_codec *codec = socdev->card->codec; | |
756 | ||
757 | /* Check parameters for validity */ | |
758 | switch (params_rate(params)) { | |
759 | case 44100: | |
760 | case 48000: | |
761 | break; | |
762 | default: | |
763 | dev_err(codec->dev, "unsupported rate %d\n", | |
764 | params_rate(params)); | |
765 | return -EINVAL; | |
766 | } | |
767 | ||
768 | switch (params_format(params)) { | |
769 | case SNDRV_PCM_FORMAT_S16_LE: | |
770 | break; | |
771 | default: | |
772 | dev_err(codec->dev, "unsupported format %d\n", | |
773 | params_format(params)); | |
774 | return -EINVAL; | |
775 | } | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
780 | #define CALC_OSCSET(rate, refclk) ( \ | |
7833ae0e | 781 | ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) |
c8bf93f0 PU |
782 | #define CALC_RATIOSET(rate, refclk) ( \ |
783 | ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) | |
784 | ||
785 | /* | |
786 | * tlv320dac33 is strict on the sequence of the register writes, if the register | |
787 | * writes happens in different order, than dac33 might end up in unknown state. | |
788 | * Use the known, working sequence of register writes to initialize the dac33. | |
789 | */ | |
790 | static int dac33_prepare_chip(struct snd_pcm_substream *substream) | |
791 | { | |
792 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
793 | struct snd_soc_device *socdev = rtd->socdev; | |
794 | struct snd_soc_codec *codec = socdev->card->codec; | |
b2c812e2 | 795 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 796 | unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; |
aec242dc | 797 | u8 aictrl_a, aictrl_b, fifoctrl_a; |
c8bf93f0 PU |
798 | |
799 | switch (substream->runtime->rate) { | |
800 | case 44100: | |
801 | case 48000: | |
802 | oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); | |
803 | ratioset = CALC_RATIOSET(substream->runtime->rate, | |
804 | dac33->refclk); | |
805 | break; | |
806 | default: | |
807 | dev_err(codec->dev, "unsupported rate %d\n", | |
808 | substream->runtime->rate); | |
809 | return -EINVAL; | |
810 | } | |
811 | ||
812 | ||
813 | aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); | |
814 | aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); | |
e5e878c1 | 815 | /* Read FIFO control A, and clear FIFO flush bit */ |
c8bf93f0 | 816 | fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); |
e5e878c1 PU |
817 | fifoctrl_a &= ~DAC33_FIFOFLUSH; |
818 | ||
c8bf93f0 PU |
819 | fifoctrl_a &= ~DAC33_WIDTH; |
820 | switch (substream->runtime->format) { | |
821 | case SNDRV_PCM_FORMAT_S16_LE: | |
822 | aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); | |
823 | fifoctrl_a |= DAC33_WIDTH; | |
824 | break; | |
825 | default: | |
826 | dev_err(codec->dev, "unsupported format %d\n", | |
827 | substream->runtime->format); | |
828 | return -EINVAL; | |
829 | } | |
830 | ||
831 | mutex_lock(&dac33->mutex); | |
c3746a07 | 832 | dac33_soft_power(codec, 0); |
c8bf93f0 PU |
833 | dac33_soft_power(codec, 1); |
834 | ||
835 | reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); | |
836 | dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp); | |
837 | ||
838 | /* Write registers 0x08 and 0x09 (MSB, LSB) */ | |
839 | dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset); | |
840 | ||
841 | /* calib time: 128 is a nice number ;) */ | |
842 | dac33_write(codec, DAC33_CALIB_TIME, 128); | |
843 | ||
844 | /* adjustment treshold & step */ | |
845 | dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | | |
846 | DAC33_ADJSTEP(1)); | |
847 | ||
848 | /* div=4 / gain=1 / div */ | |
849 | dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); | |
850 | ||
851 | pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
852 | pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; | |
853 | dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl); | |
854 | ||
855 | dac33_oscwait(codec); | |
856 | ||
7427b4b9 | 857 | if (dac33->fifo_mode) { |
aec242dc | 858 | /* Generic for all FIFO modes */ |
c8bf93f0 | 859 | /* 50-51 : ASRC Control registers */ |
fdb6b1e1 | 860 | dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); |
c8bf93f0 PU |
861 | dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */ |
862 | ||
863 | /* Write registers 0x34 and 0x35 (MSB, LSB) */ | |
864 | dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset); | |
865 | ||
866 | /* Set interrupts to high active */ | |
867 | dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); | |
c8bf93f0 | 868 | } else { |
aec242dc | 869 | /* FIFO bypass mode */ |
c8bf93f0 PU |
870 | /* 50-51 : ASRC Control registers */ |
871 | dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); | |
872 | dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */ | |
873 | } | |
874 | ||
aec242dc PU |
875 | /* Interrupt behaviour configuration */ |
876 | switch (dac33->fifo_mode) { | |
877 | case DAC33_FIFO_MODE1: | |
878 | dac33_write(codec, DAC33_FIFO_IRQ_MODE_B, | |
879 | DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); | |
aec242dc | 880 | break; |
28e05d98 | 881 | case DAC33_FIFO_MODE7: |
f57d2cfa PU |
882 | dac33_write(codec, DAC33_FIFO_IRQ_MODE_A, |
883 | DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); | |
28e05d98 | 884 | break; |
aec242dc PU |
885 | default: |
886 | /* in FIFO bypass mode, the interrupts are not used */ | |
887 | break; | |
888 | } | |
889 | ||
890 | aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
891 | ||
892 | switch (dac33->fifo_mode) { | |
893 | case DAC33_FIFO_MODE1: | |
894 | /* | |
895 | * For mode1: | |
896 | * Disable the FIFO bypass (Enable the use of FIFO) | |
897 | * Select nSample mode | |
898 | * BCLK is only running when data is needed by DAC33 | |
899 | */ | |
c8bf93f0 | 900 | fifoctrl_a &= ~DAC33_FBYPAS; |
aec242dc | 901 | fifoctrl_a &= ~DAC33_FAUTO; |
eeb309a8 PU |
902 | if (dac33->keep_bclk) |
903 | aictrl_b |= DAC33_BCLKON; | |
904 | else | |
905 | aictrl_b &= ~DAC33_BCLKON; | |
aec242dc | 906 | break; |
28e05d98 PU |
907 | case DAC33_FIFO_MODE7: |
908 | /* | |
909 | * For mode1: | |
910 | * Disable the FIFO bypass (Enable the use of FIFO) | |
911 | * Select Threshold mode | |
912 | * BCLK is only running when data is needed by DAC33 | |
913 | */ | |
914 | fifoctrl_a &= ~DAC33_FBYPAS; | |
915 | fifoctrl_a |= DAC33_FAUTO; | |
eeb309a8 PU |
916 | if (dac33->keep_bclk) |
917 | aictrl_b |= DAC33_BCLKON; | |
918 | else | |
919 | aictrl_b &= ~DAC33_BCLKON; | |
28e05d98 | 920 | break; |
aec242dc PU |
921 | default: |
922 | /* | |
923 | * For FIFO bypass mode: | |
924 | * Enable the FIFO bypass (Disable the FIFO use) | |
925 | * Set the BCLK as continous | |
926 | */ | |
c8bf93f0 | 927 | fifoctrl_a |= DAC33_FBYPAS; |
aec242dc PU |
928 | aictrl_b |= DAC33_BCLKON; |
929 | break; | |
930 | } | |
c8bf93f0 | 931 | |
aec242dc | 932 | dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a); |
c8bf93f0 | 933 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); |
aec242dc | 934 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); |
c8bf93f0 | 935 | |
6aceabb4 PU |
936 | /* |
937 | * BCLK divide ratio | |
938 | * 0: 1.5 | |
939 | * 1: 1 | |
940 | * 2: 2 | |
941 | * ... | |
942 | * 254: 254 | |
943 | * 255: 255 | |
944 | */ | |
6cd6cede | 945 | if (dac33->fifo_mode) |
6aceabb4 PU |
946 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, |
947 | dac33->burst_bclkdiv); | |
6cd6cede PU |
948 | else |
949 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); | |
c8bf93f0 | 950 | |
6cd6cede PU |
951 | switch (dac33->fifo_mode) { |
952 | case DAC33_FIFO_MODE1: | |
c8bf93f0 PU |
953 | dac33_write16(codec, DAC33_ATHR_MSB, |
954 | DAC33_THRREG(dac33->alarm_threshold)); | |
aec242dc | 955 | break; |
28e05d98 PU |
956 | case DAC33_FIFO_MODE7: |
957 | /* | |
958 | * Configure the threshold levels, and leave 10 sample space | |
959 | * at the bottom, and also at the top of the FIFO | |
960 | */ | |
4260393e PU |
961 | dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR)); |
962 | dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR)); | |
28e05d98 | 963 | break; |
aec242dc | 964 | default: |
aec242dc | 965 | break; |
c8bf93f0 PU |
966 | } |
967 | ||
968 | mutex_unlock(&dac33->mutex); | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
973 | static void dac33_calculate_times(struct snd_pcm_substream *substream) | |
974 | { | |
975 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
976 | struct snd_soc_device *socdev = rtd->socdev; | |
977 | struct snd_soc_codec *codec = socdev->card->codec; | |
b2c812e2 | 978 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
979 | unsigned int nsample_limit; |
980 | ||
55abb59c PU |
981 | /* In bypass mode we don't need to calculate */ |
982 | if (!dac33->fifo_mode) | |
983 | return; | |
984 | ||
c8bf93f0 PU |
985 | /* Number of samples (16bit, stereo) in one period */ |
986 | dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4; | |
987 | ||
988 | /* Number of samples (16bit, stereo) in ALSA buffer */ | |
989 | dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4; | |
990 | /* Subtract one period from the total */ | |
991 | dac33->nsample_max -= dac33->nsample_min; | |
992 | ||
993 | /* Number of samples for LATENCY_TIME_MS / 2 */ | |
994 | dac33->alarm_threshold = substream->runtime->rate / | |
995 | (1000 / (LATENCY_TIME_MS / 2)); | |
996 | ||
997 | /* Find and fix up the lowest nsmaple limit */ | |
998 | nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS); | |
999 | ||
1000 | if (dac33->nsample_min < nsample_limit) | |
1001 | dac33->nsample_min = nsample_limit; | |
1002 | ||
1003 | if (dac33->nsample < dac33->nsample_min) | |
1004 | dac33->nsample = dac33->nsample_min; | |
1005 | ||
1006 | /* | |
1007 | * Find and fix up the highest nsmaple limit | |
1008 | * In order to not overflow the DAC33 buffer substract the | |
1009 | * alarm_threshold value from the size of the DAC33 buffer | |
1010 | */ | |
1011 | nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold; | |
1012 | ||
1013 | if (dac33->nsample_max > nsample_limit) | |
1014 | dac33->nsample_max = nsample_limit; | |
1015 | ||
1016 | if (dac33->nsample > dac33->nsample_max) | |
1017 | dac33->nsample = dac33->nsample_max; | |
f57d2cfa PU |
1018 | |
1019 | switch (dac33->fifo_mode) { | |
1020 | case DAC33_FIFO_MODE1: | |
1021 | dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, | |
1022 | dac33->nsample); | |
1023 | dac33->t_stamp1 = 0; | |
1024 | dac33->t_stamp2 = 0; | |
1025 | break; | |
1026 | case DAC33_FIFO_MODE7: | |
1027 | dac33->mode7_us_to_lthr = | |
1028 | SAMPLES_TO_US(substream->runtime->rate, | |
1029 | MODE7_UTHR - MODE7_LTHR + 1); | |
1030 | dac33->t_stamp1 = 0; | |
1031 | break; | |
1032 | default: | |
1033 | break; | |
1034 | } | |
1035 | ||
c8bf93f0 PU |
1036 | } |
1037 | ||
1038 | static int dac33_pcm_prepare(struct snd_pcm_substream *substream, | |
1039 | struct snd_soc_dai *dai) | |
1040 | { | |
1041 | dac33_calculate_times(substream); | |
1042 | dac33_prepare_chip(substream); | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, | |
1048 | struct snd_soc_dai *dai) | |
1049 | { | |
1050 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1051 | struct snd_soc_device *socdev = rtd->socdev; | |
1052 | struct snd_soc_codec *codec = socdev->card->codec; | |
b2c812e2 | 1053 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1054 | int ret = 0; |
1055 | ||
1056 | switch (cmd) { | |
1057 | case SNDRV_PCM_TRIGGER_START: | |
1058 | case SNDRV_PCM_TRIGGER_RESUME: | |
1059 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
7427b4b9 | 1060 | if (dac33->fifo_mode) { |
c8bf93f0 PU |
1061 | dac33->state = DAC33_PREFILL; |
1062 | queue_work(dac33->dac33_wq, &dac33->work); | |
1063 | } | |
1064 | break; | |
1065 | case SNDRV_PCM_TRIGGER_STOP: | |
1066 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
1067 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
7427b4b9 | 1068 | if (dac33->fifo_mode) { |
c8bf93f0 PU |
1069 | dac33->state = DAC33_FLUSH; |
1070 | queue_work(dac33->dac33_wq, &dac33->work); | |
1071 | } | |
1072 | break; | |
1073 | default: | |
1074 | ret = -EINVAL; | |
1075 | } | |
1076 | ||
1077 | return ret; | |
1078 | } | |
1079 | ||
f57d2cfa PU |
1080 | static snd_pcm_sframes_t dac33_dai_delay( |
1081 | struct snd_pcm_substream *substream, | |
1082 | struct snd_soc_dai *dai) | |
1083 | { | |
1084 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1085 | struct snd_soc_device *socdev = rtd->socdev; | |
1086 | struct snd_soc_codec *codec = socdev->card->codec; | |
1087 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); | |
1088 | unsigned long long t0, t1, t_now; | |
1089 | unsigned int time_delta; | |
1090 | int samples_out, samples_in, samples; | |
1091 | snd_pcm_sframes_t delay = 0; | |
1092 | ||
1093 | switch (dac33->fifo_mode) { | |
1094 | case DAC33_FIFO_BYPASS: | |
1095 | break; | |
1096 | case DAC33_FIFO_MODE1: | |
1097 | spin_lock(&dac33->lock); | |
1098 | t0 = dac33->t_stamp1; | |
1099 | t1 = dac33->t_stamp2; | |
1100 | spin_unlock(&dac33->lock); | |
1101 | t_now = ktime_to_us(ktime_get()); | |
1102 | ||
1103 | /* We have not started to fill the FIFO yet, delay is 0 */ | |
1104 | if (!t1) | |
1105 | goto out; | |
1106 | ||
1107 | if (t0 > t1) { | |
1108 | /* | |
1109 | * Phase 1: | |
1110 | * After Alarm threshold, and before nSample write | |
1111 | */ | |
1112 | time_delta = t_now - t0; | |
1113 | samples_out = time_delta ? US_TO_SAMPLES( | |
1114 | substream->runtime->rate, | |
1115 | time_delta) : 0; | |
1116 | ||
1117 | if (likely(dac33->alarm_threshold > samples_out)) | |
1118 | delay = dac33->alarm_threshold - samples_out; | |
1119 | else | |
1120 | delay = 0; | |
1121 | } else if ((t_now - t1) <= dac33->mode1_us_burst) { | |
1122 | /* | |
1123 | * Phase 2: | |
1124 | * After nSample write (during burst operation) | |
1125 | */ | |
1126 | time_delta = t_now - t0; | |
1127 | samples_out = time_delta ? US_TO_SAMPLES( | |
1128 | substream->runtime->rate, | |
1129 | time_delta) : 0; | |
1130 | ||
1131 | time_delta = t_now - t1; | |
1132 | samples_in = time_delta ? US_TO_SAMPLES( | |
1133 | dac33->burst_rate, | |
1134 | time_delta) : 0; | |
1135 | ||
1136 | samples = dac33->alarm_threshold; | |
1137 | samples += (samples_in - samples_out); | |
1138 | ||
1139 | if (likely(samples > 0)) | |
1140 | delay = samples; | |
1141 | else | |
1142 | delay = 0; | |
1143 | } else { | |
1144 | /* | |
1145 | * Phase 3: | |
1146 | * After burst operation, before next alarm threshold | |
1147 | */ | |
1148 | time_delta = t_now - t0; | |
1149 | samples_out = time_delta ? US_TO_SAMPLES( | |
1150 | substream->runtime->rate, | |
1151 | time_delta) : 0; | |
1152 | ||
1153 | samples_in = dac33->nsample; | |
1154 | samples = dac33->alarm_threshold; | |
1155 | samples += (samples_in - samples_out); | |
1156 | ||
1157 | if (likely(samples > 0)) | |
1158 | delay = samples > DAC33_BUFFER_SIZE_SAMPLES ? | |
1159 | DAC33_BUFFER_SIZE_SAMPLES : samples; | |
1160 | else | |
1161 | delay = 0; | |
1162 | } | |
1163 | break; | |
1164 | case DAC33_FIFO_MODE7: | |
1165 | spin_lock(&dac33->lock); | |
1166 | t0 = dac33->t_stamp1; | |
1167 | spin_unlock(&dac33->lock); | |
1168 | t_now = ktime_to_us(ktime_get()); | |
1169 | ||
1170 | /* We have not started to fill the FIFO yet, delay is 0 */ | |
1171 | if (!t0) | |
1172 | goto out; | |
1173 | ||
1174 | if (t_now <= t0) { | |
1175 | /* | |
1176 | * Either the timestamps are messed or equal. Report | |
1177 | * maximum delay | |
1178 | */ | |
1179 | delay = MODE7_UTHR; | |
1180 | goto out; | |
1181 | } | |
1182 | ||
1183 | time_delta = t_now - t0; | |
1184 | if (time_delta <= dac33->mode7_us_to_lthr) { | |
1185 | /* | |
1186 | * Phase 1: | |
1187 | * After burst (draining phase) | |
1188 | */ | |
1189 | samples_out = US_TO_SAMPLES( | |
1190 | substream->runtime->rate, | |
1191 | time_delta); | |
1192 | ||
1193 | if (likely(MODE7_UTHR > samples_out)) | |
1194 | delay = MODE7_UTHR - samples_out; | |
1195 | else | |
1196 | delay = 0; | |
1197 | } else { | |
1198 | /* | |
1199 | * Phase 2: | |
1200 | * During burst operation | |
1201 | */ | |
1202 | time_delta = time_delta - dac33->mode7_us_to_lthr; | |
1203 | ||
1204 | samples_out = US_TO_SAMPLES( | |
1205 | substream->runtime->rate, | |
1206 | time_delta); | |
1207 | samples_in = US_TO_SAMPLES( | |
1208 | dac33->burst_rate, | |
1209 | time_delta); | |
1210 | delay = MODE7_LTHR + samples_in - samples_out; | |
1211 | ||
1212 | if (unlikely(delay > MODE7_UTHR)) | |
1213 | delay = MODE7_UTHR; | |
1214 | } | |
1215 | break; | |
1216 | default: | |
1217 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
1218 | dac33->fifo_mode); | |
1219 | break; | |
1220 | } | |
1221 | out: | |
1222 | return delay; | |
1223 | } | |
1224 | ||
c8bf93f0 PU |
1225 | static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
1226 | int clk_id, unsigned int freq, int dir) | |
1227 | { | |
1228 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1229 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1230 | u8 ioc_reg, asrcb_reg; |
1231 | ||
1232 | ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); | |
1233 | asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B); | |
1234 | switch (clk_id) { | |
1235 | case TLV320DAC33_MCLK: | |
1236 | ioc_reg |= DAC33_REFSEL; | |
1237 | asrcb_reg |= DAC33_SRCREFSEL; | |
1238 | break; | |
1239 | case TLV320DAC33_SLEEPCLK: | |
1240 | ioc_reg &= ~DAC33_REFSEL; | |
1241 | asrcb_reg &= ~DAC33_SRCREFSEL; | |
1242 | break; | |
1243 | default: | |
1244 | dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id); | |
1245 | break; | |
1246 | } | |
1247 | dac33->refclk = freq; | |
1248 | ||
1249 | dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg); | |
1250 | dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg); | |
1251 | ||
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1256 | unsigned int fmt) | |
1257 | { | |
1258 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1259 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1260 | u8 aictrl_a, aictrl_b; |
1261 | ||
1262 | aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); | |
1263 | aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
1264 | /* set master/slave audio interface */ | |
1265 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1266 | case SND_SOC_DAIFMT_CBM_CFM: | |
1267 | /* Codec Master */ | |
1268 | aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); | |
1269 | break; | |
1270 | case SND_SOC_DAIFMT_CBS_CFS: | |
1271 | /* Codec Slave */ | |
adcb8bc0 PU |
1272 | if (dac33->fifo_mode) { |
1273 | dev_err(codec->dev, "FIFO mode requires master mode\n"); | |
1274 | return -EINVAL; | |
1275 | } else | |
1276 | aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); | |
c8bf93f0 PU |
1277 | break; |
1278 | default: | |
1279 | return -EINVAL; | |
1280 | } | |
1281 | ||
1282 | aictrl_a &= ~DAC33_AFMT_MASK; | |
1283 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1284 | case SND_SOC_DAIFMT_I2S: | |
1285 | aictrl_a |= DAC33_AFMT_I2S; | |
1286 | break; | |
1287 | case SND_SOC_DAIFMT_DSP_A: | |
1288 | aictrl_a |= DAC33_AFMT_DSP; | |
1289 | aictrl_b &= ~DAC33_DATA_DELAY_MASK; | |
44f497b4 | 1290 | aictrl_b |= DAC33_DATA_DELAY(0); |
c8bf93f0 PU |
1291 | break; |
1292 | case SND_SOC_DAIFMT_RIGHT_J: | |
1293 | aictrl_a |= DAC33_AFMT_RIGHT_J; | |
1294 | break; | |
1295 | case SND_SOC_DAIFMT_LEFT_J: | |
1296 | aictrl_a |= DAC33_AFMT_LEFT_J; | |
1297 | break; | |
1298 | default: | |
1299 | dev_err(codec->dev, "Unsupported format (%u)\n", | |
1300 | fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1301 | return -EINVAL; | |
1302 | } | |
1303 | ||
1304 | dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); | |
1305 | dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
c8bf93f0 PU |
1310 | static int dac33_soc_probe(struct platform_device *pdev) |
1311 | { | |
1312 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1313 | struct snd_soc_codec *codec; | |
1314 | struct tlv320dac33_priv *dac33; | |
1315 | int ret = 0; | |
1316 | ||
1317 | BUG_ON(!tlv320dac33_codec); | |
1318 | ||
1319 | codec = tlv320dac33_codec; | |
1320 | socdev->card->codec = codec; | |
b2c812e2 | 1321 | dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 1322 | |
c8bf93f0 PU |
1323 | /* register pcms */ |
1324 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
1325 | if (ret < 0) { | |
1326 | dev_err(codec->dev, "failed to create pcms\n"); | |
1327 | goto pcm_err; | |
1328 | } | |
1329 | ||
1330 | snd_soc_add_controls(codec, dac33_snd_controls, | |
1331 | ARRAY_SIZE(dac33_snd_controls)); | |
1332 | /* Only add the nSample controls, if we have valid IRQ number */ | |
1333 | if (dac33->irq >= 0) | |
1334 | snd_soc_add_controls(codec, dac33_nsample_snd_controls, | |
1335 | ARRAY_SIZE(dac33_nsample_snd_controls)); | |
1336 | ||
1337 | dac33_add_widgets(codec); | |
1338 | ||
1339 | /* power on device */ | |
1340 | dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1341 | ||
c8bf93f0 | 1342 | return 0; |
fe3e78e0 | 1343 | |
c8bf93f0 PU |
1344 | pcm_err: |
1345 | dac33_hard_power(codec, 0); | |
1346 | return ret; | |
1347 | } | |
1348 | ||
1349 | static int dac33_soc_remove(struct platform_device *pdev) | |
1350 | { | |
1351 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1352 | struct snd_soc_codec *codec = socdev->card->codec; | |
1353 | ||
1354 | dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1355 | ||
1356 | snd_soc_free_pcms(socdev); | |
1357 | snd_soc_dapm_free(socdev); | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state) | |
1363 | { | |
1364 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1365 | struct snd_soc_codec *codec = socdev->card->codec; | |
1366 | ||
1367 | dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1368 | ||
1369 | return 0; | |
1370 | } | |
1371 | ||
1372 | static int dac33_soc_resume(struct platform_device *pdev) | |
1373 | { | |
1374 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1375 | struct snd_soc_codec *codec = socdev->card->codec; | |
1376 | ||
1377 | dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1378 | dac33_set_bias_level(codec, codec->suspend_bias_level); | |
1379 | ||
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = { | |
1384 | .probe = dac33_soc_probe, | |
1385 | .remove = dac33_soc_remove, | |
1386 | .suspend = dac33_soc_suspend, | |
1387 | .resume = dac33_soc_resume, | |
1388 | }; | |
1389 | EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33); | |
1390 | ||
1391 | #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ | |
1392 | SNDRV_PCM_RATE_48000) | |
1393 | #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE | |
1394 | ||
1395 | static struct snd_soc_dai_ops dac33_dai_ops = { | |
0b61d2b9 PU |
1396 | .startup = dac33_startup, |
1397 | .shutdown = dac33_shutdown, | |
c8bf93f0 PU |
1398 | .hw_params = dac33_hw_params, |
1399 | .prepare = dac33_pcm_prepare, | |
1400 | .trigger = dac33_pcm_trigger, | |
f57d2cfa | 1401 | .delay = dac33_dai_delay, |
c8bf93f0 PU |
1402 | .set_sysclk = dac33_set_dai_sysclk, |
1403 | .set_fmt = dac33_set_dai_fmt, | |
1404 | }; | |
1405 | ||
1406 | struct snd_soc_dai dac33_dai = { | |
1407 | .name = "tlv320dac33", | |
1408 | .playback = { | |
1409 | .stream_name = "Playback", | |
1410 | .channels_min = 2, | |
1411 | .channels_max = 2, | |
1412 | .rates = DAC33_RATES, | |
1413 | .formats = DAC33_FORMATS,}, | |
1414 | .ops = &dac33_dai_ops, | |
1415 | }; | |
1416 | EXPORT_SYMBOL_GPL(dac33_dai); | |
1417 | ||
735fe4cf MB |
1418 | static int __devinit dac33_i2c_probe(struct i2c_client *client, |
1419 | const struct i2c_device_id *id) | |
c8bf93f0 PU |
1420 | { |
1421 | struct tlv320dac33_platform_data *pdata; | |
1422 | struct tlv320dac33_priv *dac33; | |
1423 | struct snd_soc_codec *codec; | |
3a7aaed7 | 1424 | int ret, i; |
c8bf93f0 PU |
1425 | |
1426 | if (client->dev.platform_data == NULL) { | |
1427 | dev_err(&client->dev, "Platform data not set\n"); | |
1428 | return -ENODEV; | |
1429 | } | |
1430 | pdata = client->dev.platform_data; | |
1431 | ||
1432 | dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL); | |
1433 | if (dac33 == NULL) | |
1434 | return -ENOMEM; | |
1435 | ||
1436 | codec = &dac33->codec; | |
b2c812e2 | 1437 | snd_soc_codec_set_drvdata(codec, dac33); |
c8bf93f0 PU |
1438 | codec->control_data = client; |
1439 | ||
1440 | mutex_init(&codec->mutex); | |
1441 | mutex_init(&dac33->mutex); | |
f57d2cfa | 1442 | spin_lock_init(&dac33->lock); |
c8bf93f0 PU |
1443 | INIT_LIST_HEAD(&codec->dapm_widgets); |
1444 | INIT_LIST_HEAD(&codec->dapm_paths); | |
1445 | ||
1446 | codec->name = "tlv320dac33"; | |
1447 | codec->owner = THIS_MODULE; | |
1448 | codec->read = dac33_read_reg_cache; | |
1449 | codec->write = dac33_write_locked; | |
1450 | codec->hw_write = (hw_write_t) i2c_master_send; | |
1451 | codec->bias_level = SND_SOC_BIAS_OFF; | |
1452 | codec->set_bias_level = dac33_set_bias_level; | |
1453 | codec->dai = &dac33_dai; | |
1454 | codec->num_dai = 1; | |
1455 | codec->reg_cache_size = ARRAY_SIZE(dac33_reg); | |
1456 | codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg), | |
1457 | GFP_KERNEL); | |
1458 | if (codec->reg_cache == NULL) { | |
1459 | ret = -ENOMEM; | |
1460 | goto error_reg; | |
1461 | } | |
1462 | ||
1463 | i2c_set_clientdata(client, dac33); | |
1464 | ||
1465 | dac33->power_gpio = pdata->power_gpio; | |
6aceabb4 | 1466 | dac33->burst_bclkdiv = pdata->burst_bclkdiv; |
76f47127 PU |
1467 | /* Pre calculate the burst rate */ |
1468 | dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32; | |
eeb309a8 | 1469 | dac33->keep_bclk = pdata->keep_bclk; |
c8bf93f0 PU |
1470 | dac33->irq = client->irq; |
1471 | dac33->nsample = NSAMPLE_MAX; | |
55abb59c | 1472 | dac33->nsample_max = NSAMPLE_MAX; |
c8bf93f0 | 1473 | /* Disable FIFO use by default */ |
7427b4b9 | 1474 | dac33->fifo_mode = DAC33_FIFO_BYPASS; |
c8bf93f0 PU |
1475 | |
1476 | tlv320dac33_codec = codec; | |
1477 | ||
1478 | codec->dev = &client->dev; | |
1479 | dac33_dai.dev = codec->dev; | |
1480 | ||
1481 | /* Check if the reset GPIO number is valid and request it */ | |
1482 | if (dac33->power_gpio >= 0) { | |
1483 | ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset"); | |
1484 | if (ret < 0) { | |
1485 | dev_err(codec->dev, | |
1486 | "Failed to request reset GPIO (%d)\n", | |
1487 | dac33->power_gpio); | |
1488 | snd_soc_unregister_dai(&dac33_dai); | |
1489 | snd_soc_unregister_codec(codec); | |
1490 | goto error_gpio; | |
1491 | } | |
1492 | gpio_direction_output(dac33->power_gpio, 0); | |
c8bf93f0 PU |
1493 | } |
1494 | ||
1495 | /* Check if the IRQ number is valid and request it */ | |
1496 | if (dac33->irq >= 0) { | |
1497 | ret = request_irq(dac33->irq, dac33_interrupt_handler, | |
1498 | IRQF_TRIGGER_RISING | IRQF_DISABLED, | |
1499 | codec->name, codec); | |
1500 | if (ret < 0) { | |
1501 | dev_err(codec->dev, "Could not request IRQ%d (%d)\n", | |
1502 | dac33->irq, ret); | |
1503 | dac33->irq = -1; | |
1504 | } | |
1505 | if (dac33->irq != -1) { | |
1506 | /* Setup work queue */ | |
74ea23aa PU |
1507 | dac33->dac33_wq = |
1508 | create_singlethread_workqueue("tlv320dac33"); | |
c8bf93f0 PU |
1509 | if (dac33->dac33_wq == NULL) { |
1510 | free_irq(dac33->irq, &dac33->codec); | |
1511 | ret = -ENOMEM; | |
1512 | goto error_wq; | |
1513 | } | |
1514 | ||
1515 | INIT_WORK(&dac33->work, dac33_work); | |
1516 | } | |
1517 | } | |
1518 | ||
3a7aaed7 IK |
1519 | for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) |
1520 | dac33->supplies[i].supply = dac33_supply_names[i]; | |
1521 | ||
1522 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies), | |
1523 | dac33->supplies); | |
1524 | ||
1525 | if (ret != 0) { | |
1526 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
1527 | goto err_get; | |
1528 | } | |
1529 | ||
239fe55c PU |
1530 | /* Read the tlv320dac33 ID registers */ |
1531 | ret = dac33_hard_power(codec, 1); | |
3a7aaed7 | 1532 | if (ret != 0) { |
239fe55c PU |
1533 | dev_err(codec->dev, "Failed to power up codec: %d\n", ret); |
1534 | goto error_codec; | |
3a7aaed7 | 1535 | } |
239fe55c PU |
1536 | dac33_read_id(codec); |
1537 | dac33_hard_power(codec, 0); | |
3a7aaed7 | 1538 | |
c8bf93f0 PU |
1539 | ret = snd_soc_register_codec(codec); |
1540 | if (ret != 0) { | |
1541 | dev_err(codec->dev, "Failed to register codec: %d\n", ret); | |
1542 | goto error_codec; | |
1543 | } | |
1544 | ||
1545 | ret = snd_soc_register_dai(&dac33_dai); | |
1546 | if (ret != 0) { | |
1547 | dev_err(codec->dev, "Failed to register DAI: %d\n", ret); | |
1548 | snd_soc_unregister_codec(codec); | |
1549 | goto error_codec; | |
1550 | } | |
1551 | ||
c8bf93f0 PU |
1552 | return ret; |
1553 | ||
1554 | error_codec: | |
3a7aaed7 IK |
1555 | regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); |
1556 | err_get: | |
c8bf93f0 PU |
1557 | if (dac33->irq >= 0) { |
1558 | free_irq(dac33->irq, &dac33->codec); | |
1559 | destroy_workqueue(dac33->dac33_wq); | |
1560 | } | |
1561 | error_wq: | |
1562 | if (dac33->power_gpio >= 0) | |
1563 | gpio_free(dac33->power_gpio); | |
1564 | error_gpio: | |
1565 | kfree(codec->reg_cache); | |
1566 | error_reg: | |
1567 | tlv320dac33_codec = NULL; | |
1568 | kfree(dac33); | |
1569 | ||
1570 | return ret; | |
1571 | } | |
1572 | ||
735fe4cf | 1573 | static int __devexit dac33_i2c_remove(struct i2c_client *client) |
c8bf93f0 PU |
1574 | { |
1575 | struct tlv320dac33_priv *dac33; | |
1576 | ||
1577 | dac33 = i2c_get_clientdata(client); | |
239fe55c PU |
1578 | |
1579 | if (unlikely(dac33->chip_power)) | |
1580 | dac33_hard_power(&dac33->codec, 0); | |
c8bf93f0 PU |
1581 | |
1582 | if (dac33->power_gpio >= 0) | |
1583 | gpio_free(dac33->power_gpio); | |
1584 | if (dac33->irq >= 0) | |
1585 | free_irq(dac33->irq, &dac33->codec); | |
1586 | ||
3a7aaed7 IK |
1587 | regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); |
1588 | ||
c8bf93f0 PU |
1589 | destroy_workqueue(dac33->dac33_wq); |
1590 | snd_soc_unregister_dai(&dac33_dai); | |
1591 | snd_soc_unregister_codec(&dac33->codec); | |
1592 | kfree(dac33->codec.reg_cache); | |
1593 | kfree(dac33); | |
1594 | tlv320dac33_codec = NULL; | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | static const struct i2c_device_id tlv320dac33_i2c_id[] = { | |
1600 | { | |
1601 | .name = "tlv320dac33", | |
1602 | .driver_data = 0, | |
1603 | }, | |
1604 | { }, | |
1605 | }; | |
1606 | ||
1607 | static struct i2c_driver tlv320dac33_i2c_driver = { | |
1608 | .driver = { | |
1609 | .name = "tlv320dac33", | |
1610 | .owner = THIS_MODULE, | |
1611 | }, | |
1612 | .probe = dac33_i2c_probe, | |
1613 | .remove = __devexit_p(dac33_i2c_remove), | |
1614 | .id_table = tlv320dac33_i2c_id, | |
1615 | }; | |
1616 | ||
1617 | static int __init dac33_module_init(void) | |
1618 | { | |
1619 | int r; | |
1620 | r = i2c_add_driver(&tlv320dac33_i2c_driver); | |
1621 | if (r < 0) { | |
1622 | printk(KERN_ERR "DAC33: driver registration failed\n"); | |
1623 | return r; | |
1624 | } | |
1625 | return 0; | |
1626 | } | |
1627 | module_init(dac33_module_init); | |
1628 | ||
1629 | static void __exit dac33_module_exit(void) | |
1630 | { | |
1631 | i2c_del_driver(&tlv320dac33_i2c_driver); | |
1632 | } | |
1633 | module_exit(dac33_module_exit); | |
1634 | ||
1635 | ||
1636 | MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); | |
1637 | MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>"); | |
1638 | MODULE_LICENSE("GPL"); |