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ASoC: Implement WM8994 OPCLK support
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
b07682b6 29#include <linux/i2c/twl.h>
5a0e3ad6 30#include <linux/slab.h>
cc17557e
SS		 31#include <sound/core.h>
32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/soc.h>
35#include <sound/soc-dapm.h>
36#include <sound/initval.h>
c10b82cf 37#include <sound/tlv.h>
cc17557e
SS		 38
39#include "twl4030.h"
40
41/*
42 * twl4030 register cache & default register settings
43 */
44static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
45 0x00, /* this register not used */
33f92ed4 46 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 47 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 48 0x00, /* REG_UNKNOWN (0x3) */
49 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 50 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 51 0x00, /* REG_ANAMICR (0x6) */
52 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 53 0x00, /* REG_ADCMICSEL (0x8) */
54 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 55 0x0f, /* REG_ATXL1PGA (0xA) */
56 0x0f, /* REG_ATXR1PGA (0xB) */
57 0x0f, /* REG_AVTXL2PGA (0xC) */
58 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 59 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 60 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 61 0x3f, /* REG_ARXR1PGA (0x10) */
62 0x3f, /* REG_ARXL1PGA (0x11) */
63 0x3f, /* REG_ARXR2PGA (0x12) */
64 0x3f, /* REG_ARXL2PGA (0x13) */
65 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 66 0x00, /* REG_VSTPGA (0x15) */
67 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 68 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 69 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 70 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
71 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
72 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
73 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 74 0x00, /* REG_ATX2ARXPGA (0x1D) */
75 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 76 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 77 0x00, /* REG_BTSTPGA (0x20) */
78 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 79 0x00, /* REG_HS_SEL (0x22) */
80 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 81 0x00, /* REG_HS_POPN_SET (0x24) */
82 0x00, /* REG_PREDL_CTL (0x25) */
83 0x00, /* REG_PREDR_CTL (0x26) */
84 0x00, /* REG_PRECKL_CTL (0x27) */
85 0x00, /* REG_PRECKR_CTL (0x28) */
86 0x00, /* REG_HFL_CTL (0x29) */
87 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 88 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 89 0x00, /* REG_ALC_SET1 (0x2C) */
90 0x00, /* REG_ALC_SET2 (0x2D) */
91 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 92 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 93 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 94 0x00, /* REG_DTMF_TONEXT1H (0x31) */
95 0x00, /* REG_DTMF_TONEXT1L (0x32) */
96 0x00, /* REG_DTMF_TONEXT2H (0x33) */
97 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 98 0x79, /* REG_DTMF_TONOFF (0x35) */
99 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 100 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
102 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 103 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 104 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 105 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
106 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 107 0x00, /* REG_MISC_SET_1 (0x3E) */
108 0x00, /* REG_PCMBTMUX (0x3F) */
109 0x00, /* not used (0x40) */
110 0x00, /* not used (0x41) */
111 0x00, /* not used (0x42) */
112 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 113 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 114 0x00, /* REG_VIBRA_CTL (0x45) */
115 0x00, /* REG_VIBRA_SET (0x46) */
116 0x00, /* REG_VIBRA_PWM_SET (0x47) */
117 0x00, /* REG_ANAMIC_GAIN (0x48) */
118 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 119 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 120};
121
7393958f
PU		 122/* codec private data */
123struct twl4030_priv {
7a1fecf5
PU		 124 struct snd_soc_codec codec;
125
7393958f 126 unsigned int codec_powered;
7b4c734e
PU		 127
128 /* reference counts of AIF/APLL users */
2845fa13 129 unsigned int apll_enabled;
7220b9f4
PU		 130
131 struct snd_pcm_substream *master_substream;
132 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 133
134 unsigned int configured;
135 unsigned int rate;
136 unsigned int sample_bits;
137 unsigned int channels;
6943c92e
PU		 138
139 unsigned int sysclk;
140
c96907f2
PU		 141 /* Output (with associated amp) states */
142 u8 hsl_enabled, hsr_enabled;
143 u8 earpiece_enabled;
144 u8 predrivel_enabled, predriver_enabled;
145 u8 carkitl_enabled, carkitr_enabled;
7393958f
PU		 146};
147
cc17557e
SS		 148/*
149 * read twl4030 register cache
150 */
151static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
152 unsigned int reg)
153{
d08664fd 154 u8 *cache = codec->reg_cache;
cc17557e 155
91432e97
IM		 156 if (reg >= TWL4030_CACHEREGNUM)
157 return -EIO;
158
cc17557e
SS		 159 return cache[reg];
160}
161
162/*
163 * write twl4030 register cache
164 */
165static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
166 u8 reg, u8 value)
167{
168 u8 *cache = codec->reg_cache;
169
170 if (reg >= TWL4030_CACHEREGNUM)
171 return;
172 cache[reg] = value;
173}
174
175/*
176 * write to the twl4030 register space
177 */
178static int twl4030_write(struct snd_soc_codec *codec,
179 unsigned int reg, unsigned int value)
180{
b2c812e2 181 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
c96907f2
PU		 182 int write_to_reg = 0;
183
cc17557e 184 twl4030_write_reg_cache(codec, reg, value);
c96907f2
PU		 185 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
186 /* Decide if the given register can be written */
187 switch (reg) {
188 case TWL4030_REG_EAR_CTL:
189 if (twl4030->earpiece_enabled)
190 write_to_reg = 1;
191 break;
192 case TWL4030_REG_PREDL_CTL:
193 if (twl4030->predrivel_enabled)
194 write_to_reg = 1;
195 break;
196 case TWL4030_REG_PREDR_CTL:
197 if (twl4030->predriver_enabled)
198 write_to_reg = 1;
199 break;
200 case TWL4030_REG_PRECKL_CTL:
201 if (twl4030->carkitl_enabled)
202 write_to_reg = 1;
203 break;
204 case TWL4030_REG_PRECKR_CTL:
205 if (twl4030->carkitr_enabled)
206 write_to_reg = 1;
207 break;
208 case TWL4030_REG_HS_GAIN_SET:
209 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
210 write_to_reg = 1;
211 break;
212 default:
213 /* All other register can be written */
214 write_to_reg = 1;
215 break;
216 }
217 if (write_to_reg)
218 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
219 value, reg);
220 }
221 return 0;
cc17557e
SS		 222}
223
db04e2c5 224static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 225{
b2c812e2 226 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 227 int mode;
cc17557e 228
7393958f
PU		 229 if (enable == twl4030->codec_powered)
230 return;
231
db04e2c5 232 if (enable)
7a1fecf5 233 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 234 else
7a1fecf5 235 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 236
7a1fecf5
PU		 237 if (mode >= 0) {
238 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
239 twl4030->codec_powered = enable;
240 }
cc17557e
SS		 241
242 /* REVISIT: this delay is present in TI sample drivers */
243 /* but there seems to be no TRM requirement for it */
244 udelay(10);
245}
246
9fdcc0f7 247static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
cc17557e 248{
9fdcc0f7
PU		 249 int i, difference = 0;
250 u8 val;
251
252 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
253 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
254 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
255 if (val != twl4030_reg[i]) {
256 difference++;
257 dev_dbg(codec->dev,
258 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
259 i, val, twl4030_reg[i]);
260 }
261 }
262 dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
263 difference, difference ? "Not OK" : "OK");
264}
cc17557e 265
a3a29b55
PU		 266static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
267{
268 int i;
cc17557e
SS		 269
270 /* set all audio section registers to reasonable defaults */
271 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955 272 if (i != TWL4030_REG_APLL_CTL)
a3a29b55 273 twl4030_write(codec, i, twl4030_reg[i]);
cc17557e
SS		 274
275}
276
ee4ccac7 277static void twl4030_init_chip(struct platform_device *pdev)
7393958f 278{
ee4ccac7
PU		 279 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
280 struct twl4030_setup_data *setup = socdev->codec_data;
281 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 282 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 283 u8 reg, byte;
284 int i = 0;
7393958f 285
9fdcc0f7
PU		 286 /* Check defaults, if instructed before anything else */
287 if (setup && setup->check_defaults)
288 twl4030_check_defaults(codec);
7a1fecf5 289
a3a29b55
PU		 290 /* Reset registers, if no setup data or if instructed to do so */
291 if (!setup || (setup && setup->reset_registers))
292 twl4030_reset_registers(codec);
7393958f 293
ee4ccac7 294 /* Refresh APLL_CTL register from HW */
9fdcc0f7 295 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 296 TWL4030_REG_APLL_CTL);
297 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
006f367e 298
ee4ccac7
PU		 299 /* anti-pop when changing analog gain */
300 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
301 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
302 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 303
ee4ccac7
PU		 304 twl4030_write(codec, TWL4030_REG_OPTION,
305 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
306 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 307
3c36cc68
PU		 308 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
309 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
310
ee4ccac7
PU		 311 /* Machine dependent setup */
312 if (!setup)
7393958f
PU		 313 return;
314
ee4ccac7
PU		 315 /* Configuration for headset ramp delay from setup data */
316 if (setup->sysclk != twl4030->sysclk)
317 dev_warn(codec->dev,
318 "Mismatch in APLL mclk: %u (configured: %u)\n",
319 setup->sysclk, twl4030->sysclk);
320
321 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
322 reg &= ~TWL4030_RAMP_DELAY;
323 reg |= (setup->ramp_delay_value << 2);
324 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 325
326 /* initiate offset cancellation */
ee4ccac7
PU		 327 twl4030_codec_enable(codec, 1);
328
329 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
330 reg &= ~TWL4030_OFFSET_CNCL_SEL;
331 reg |= setup->offset_cncl_path;
006f367e 332 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 333 reg | TWL4030_CNCL_OFFSET_START);
006f367e
PU		 334
335 /* wait for offset cancellation to complete */
336 do {
337 /* this takes a little while, so don't slam i2c */
338 udelay(2000);
fc7b92fc 339 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 340 TWL4030_REG_ANAMICL);
341 } while ((i++ < 100) &&
342 ((byte & TWL4030_CNCL_OFFSET_START) ==
343 TWL4030_CNCL_OFFSET_START));
344
345 /* Make sure that the reg_cache has the same value as the HW */
346 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
347
006f367e 348 twl4030_codec_enable(codec, 0);
006f367e
PU		 349}
350
ee4ccac7 351static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 352{
ee4ccac7
PU		 353 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
354 int status = -1;
355
356 if (enable) {
357 twl4030->apll_enabled++;
358 if (twl4030->apll_enabled == 1)
359 status = twl4030_codec_enable_resource(
360 TWL4030_CODEC_RES_APLL);
361 } else {
362 twl4030->apll_enabled--;
363 if (!twl4030->apll_enabled)
364 status = twl4030_codec_disable_resource(
365 TWL4030_CODEC_RES_APLL);
366 }
367
368 if (status >= 0)
369 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 370}
371
5e98a464 372/* Earpiece */
1a787e7a
JS		 373static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
374 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
375 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
376 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
377 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
378};
5e98a464 379
2a6f5c58 380/* PreDrive Left */
1a787e7a
JS		 381static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
382 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
383 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
384 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
385 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
386};
2a6f5c58
PU		 387
388/* PreDrive Right */
1a787e7a
JS		 389static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
390 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
391 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
392 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
393 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
394};
2a6f5c58 395
dfad21a2 396/* Headset Left */
1a787e7a
JS		 397static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
398 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
399 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
400 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
401};
dfad21a2
PU		 402
403/* Headset Right */
1a787e7a
JS		 404static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
405 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
406 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
407 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
408};
dfad21a2 409
5152d8c2 410/* Carkit Left */
1a787e7a
JS		 411static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
412 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
413 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
414 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
415};
5152d8c2
PU		 416
417/* Carkit Right */
1a787e7a
JS		 418static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
419 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
420 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
421 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
422};
5152d8c2 423
df339804
PU		 424/* Handsfree Left */
425static const char *twl4030_handsfreel_texts[] =
1a787e7a 426 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 427
428static const struct soc_enum twl4030_handsfreel_enum =
429 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
430 ARRAY_SIZE(twl4030_handsfreel_texts),
431 twl4030_handsfreel_texts);
432
433static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
434SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
435
0f89bdca
PU		 436/* Handsfree Left virtual mute */
437static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
438 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
439
df339804
PU		 440/* Handsfree Right */
441static const char *twl4030_handsfreer_texts[] =
1a787e7a 442 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 443
444static const struct soc_enum twl4030_handsfreer_enum =
445 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
446 ARRAY_SIZE(twl4030_handsfreer_texts),
447 twl4030_handsfreer_texts);
448
449static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
450SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
451
0f89bdca
PU		 452/* Handsfree Right virtual mute */
453static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
454 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
455
376f7839
PU		 456/* Vibra */
457/* Vibra audio path selection */
458static const char *twl4030_vibra_texts[] =
459 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
460
461static const struct soc_enum twl4030_vibra_enum =
462 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
463 ARRAY_SIZE(twl4030_vibra_texts),
464 twl4030_vibra_texts);
465
466static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
467SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
468
469/* Vibra path selection: local vibrator (PWM) or audio driven */
470static const char *twl4030_vibrapath_texts[] =
471 {"Local vibrator", "Audio"};
472
473static const struct soc_enum twl4030_vibrapath_enum =
474 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
475 ARRAY_SIZE(twl4030_vibrapath_texts),
476 twl4030_vibrapath_texts);
477
478static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
479SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
480
276c6222 481/* Left analog microphone selection */
97b8096d 482static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 483 SOC_DAPM_SINGLE("Main Mic Capture Switch",
484 TWL4030_REG_ANAMICL, 0, 1, 0),
485 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
486 TWL4030_REG_ANAMICL, 1, 1, 0),
487 SOC_DAPM_SINGLE("AUXL Capture Switch",
488 TWL4030_REG_ANAMICL, 2, 1, 0),
489 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
490 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 491};
276c6222
PU		 492
493/* Right analog microphone selection */
97b8096d 494static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 495 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
496 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 497};
276c6222
PU		 498
499/* TX1 L/R Analog/Digital microphone selection */
500static const char *twl4030_micpathtx1_texts[] =
501 {"Analog", "Digimic0"};
502
503static const struct soc_enum twl4030_micpathtx1_enum =
504 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
505 ARRAY_SIZE(twl4030_micpathtx1_texts),
506 twl4030_micpathtx1_texts);
507
508static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
509SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
510
511/* TX2 L/R Analog/Digital microphone selection */
512static const char *twl4030_micpathtx2_texts[] =
513 {"Analog", "Digimic1"};
514
515static const struct soc_enum twl4030_micpathtx2_enum =
516 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
517 ARRAY_SIZE(twl4030_micpathtx2_texts),
518 twl4030_micpathtx2_texts);
519
520static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
521SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
522
7393958f
PU		 523/* Analog bypass for AudioR1 */
524static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
525 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
526
527/* Analog bypass for AudioL1 */
528static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
529 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
530
531/* Analog bypass for AudioR2 */
532static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
533 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
534
535/* Analog bypass for AudioL2 */
536static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
537 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
538
fcd274a3
LCM		 539/* Analog bypass for Voice */
540static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
541 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
542
6bab83fd
PU		 543/* Digital bypass gain, 0 mutes the bypass */
544static const unsigned int twl4030_dapm_dbypass_tlv[] = {
545 TLV_DB_RANGE_HEAD(2),
546 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
547 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
548};
549
550/* Digital bypass left (TX1L -> RX2L) */
551static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
552 SOC_DAPM_SINGLE_TLV("Volume",
553 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
554 twl4030_dapm_dbypass_tlv);
555
556/* Digital bypass right (TX1R -> RX2R) */
557static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
558 SOC_DAPM_SINGLE_TLV("Volume",
559 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
560 twl4030_dapm_dbypass_tlv);
561
ee8f6894
LCM		 562/*
563 * Voice Sidetone GAIN volume control:
564 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
565 */
566static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
567
568/* Digital bypass voice: sidetone (VUL -> VDL)*/
569static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
570 SOC_DAPM_SINGLE_TLV("Volume",
571 TWL4030_REG_VSTPGA, 0, 0x29, 0,
572 twl4030_dapm_dbypassv_tlv);
573
276c6222
PU		 574static int micpath_event(struct snd_soc_dapm_widget *w,
575 struct snd_kcontrol *kcontrol, int event)
576{
577 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
578 unsigned char adcmicsel, micbias_ctl;
579
580 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
581 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
582 /* Prepare the bits for the given TX path:
583 * shift_l == 0: TX1 microphone path
584 * shift_l == 2: TX2 microphone path */
585 if (e->shift_l) {
586 /* TX2 microphone path */
587 if (adcmicsel & TWL4030_TX2IN_SEL)
588 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
589 else
590 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
591 } else {
592 /* TX1 microphone path */
593 if (adcmicsel & TWL4030_TX1IN_SEL)
594 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
595 else
596 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
597 }
598
599 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
600
601 return 0;
602}
603
9008adf9
PU		 604/*
605 * Output PGA builder:
606 * Handle the muting and unmuting of the given output (turning off the
607 * amplifier associated with the output pin)
c96907f2
PU		 608 * On mute bypass the reg_cache and write 0 to the register
609 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 610 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
611 */
612#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
613static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
614 struct snd_kcontrol *kcontrol, int event) \
615{ \
b2c812e2 616 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 617 \
618 switch (event) { \
619 case SND_SOC_DAPM_POST_PMU: \
c96907f2 620 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 621 twl4030_write(w->codec, reg, \
622 twl4030_read_reg_cache(w->codec, reg)); \
623 break; \
624 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 625 twl4030->pin_name##_enabled = 0; \
626 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
627 0, reg); \
9008adf9
PU		 628 break; \
629 } \
630 return 0; \
631}
632
633TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
634TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
635TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
636TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
637TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
638
5a2e9a48 639static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 640{
49d92c7d
SM		 641 unsigned char hs_ctl;
642
5a2e9a48 643 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 644
5a2e9a48
PU		 645 if (ramp) {
646 /* HF ramp-up */
647 hs_ctl |= TWL4030_HF_CTL_REF_EN;
648 twl4030_write(codec, reg, hs_ctl);
649 udelay(10);
49d92c7d 650 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 651 twl4030_write(codec, reg, hs_ctl);
652 udelay(40);
49d92c7d 653 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 654 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 655 twl4030_write(codec, reg, hs_ctl);
49d92c7d 656 } else {
5a2e9a48
PU		 657 /* HF ramp-down */
658 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
659 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
660 twl4030_write(codec, reg, hs_ctl);
661 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
662 twl4030_write(codec, reg, hs_ctl);
663 udelay(40);
664 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
665 twl4030_write(codec, reg, hs_ctl);
49d92c7d 666 }
5a2e9a48 667}
49d92c7d 668
5a2e9a48
PU		 669static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
670 struct snd_kcontrol *kcontrol, int event)
671{
672 switch (event) {
673 case SND_SOC_DAPM_POST_PMU:
674 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
675 break;
676 case SND_SOC_DAPM_POST_PMD:
677 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
678 break;
679 }
680 return 0;
681}
682
683static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
684 struct snd_kcontrol *kcontrol, int event)
685{
686 switch (event) {
687 case SND_SOC_DAPM_POST_PMU:
688 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
689 break;
690 case SND_SOC_DAPM_POST_PMD:
691 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
692 break;
693 }
49d92c7d
SM		 694 return 0;
695}
696
86139a13
JV		 697static int vibramux_event(struct snd_soc_dapm_widget *w,
698 struct snd_kcontrol *kcontrol, int event)
699{
700 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
701 return 0;
702}
703
7729cf74
PU		 704static int apll_event(struct snd_soc_dapm_widget *w,
705 struct snd_kcontrol *kcontrol, int event)
706{
707 switch (event) {
708 case SND_SOC_DAPM_PRE_PMU:
709 twl4030_apll_enable(w->codec, 1);
710 break;
711 case SND_SOC_DAPM_POST_PMD:
712 twl4030_apll_enable(w->codec, 0);
713 break;
714 }
715 return 0;
716}
717
7b4c734e
PU		 718static int aif_event(struct snd_soc_dapm_widget *w,
719 struct snd_kcontrol *kcontrol, int event)
720{
721 u8 audio_if;
722
723 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
724 switch (event) {
725 case SND_SOC_DAPM_PRE_PMU:
726 /* Enable AIF */
727 /* enable the PLL before we use it to clock the DAI */
728 twl4030_apll_enable(w->codec, 1);
729
730 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
731 audio_if | TWL4030_AIF_EN);
732 break;
733 case SND_SOC_DAPM_POST_PMD:
734 /* disable the DAI before we stop it's source PLL */
735 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
736 audio_if & ~TWL4030_AIF_EN);
737 twl4030_apll_enable(w->codec, 0);
738 break;
739 }
740 return 0;
741}
742
6943c92e 743static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 744{
4e49ffd1
CVJ		 745 struct snd_soc_device *socdev = codec->socdev;
746 struct twl4030_setup_data *setup = socdev->codec_data;
747
aad749e5 748 unsigned char hs_gain, hs_pop;
b2c812e2 749 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 750 /* Base values for ramp delay calculation: 2^19 - 2^26 */
751 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
752 8388608, 16777216, 33554432, 67108864};
aad749e5 753
6943c92e
PU		 754 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
755 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 756
4e49ffd1
CVJ		 757 /* Enable external mute control, this dramatically reduces
758 * the pop-noise */
759 if (setup && setup->hs_extmute) {
760 if (setup->set_hs_extmute) {
761 setup->set_hs_extmute(1);
762 } else {
763 hs_pop |= TWL4030_EXTMUTE;
764 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
765 }
766 }
767
6943c92e
PU		 768 if (ramp) {
769 /* Headset ramp-up according to the TRM */
aad749e5 770 hs_pop |= TWL4030_VMID_EN;
6943c92e 771 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 772 /* Actually write to the register */
773 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
774 hs_gain,
775 TWL4030_REG_HS_GAIN_SET);
aad749e5 776 hs_pop |= TWL4030_RAMP_EN;
6943c92e 777 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 778 /* Wait ramp delay time + 1, so the VMID can settle */
779 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
780 twl4030->sysclk) + 1);
6943c92e
PU		 781 } else {
782 /* Headset ramp-down _not_ according to
783 * the TRM, but in a way that it is working */
aad749e5 784 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 785 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
786 /* Wait ramp delay time + 1, so the VMID can settle */
787 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
788 twl4030->sysclk) + 1);
aad749e5 789 /* Bypass the reg_cache to mute the headset */
fc7b92fc 790 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 791 hs_gain & (~0x0f),
792 TWL4030_REG_HS_GAIN_SET);
6943c92e 793
aad749e5 794 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 795 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
796 }
4e49ffd1
CVJ		 797
798 /* Disable external mute */
799 if (setup && setup->hs_extmute) {
800 if (setup->set_hs_extmute) {
801 setup->set_hs_extmute(0);
802 } else {
803 hs_pop &= ~TWL4030_EXTMUTE;
804 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
805 }
806 }
6943c92e
PU		 807}
808
809static int headsetlpga_event(struct snd_soc_dapm_widget *w,
810 struct snd_kcontrol *kcontrol, int event)
811{
b2c812e2 812 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 813
814 switch (event) {
815 case SND_SOC_DAPM_POST_PMU:
816 /* Do the ramp-up only once */
817 if (!twl4030->hsr_enabled)
818 headset_ramp(w->codec, 1);
819
820 twl4030->hsl_enabled = 1;
821 break;
822 case SND_SOC_DAPM_POST_PMD:
823 /* Do the ramp-down only if both headsetL/R is disabled */
824 if (!twl4030->hsr_enabled)
825 headset_ramp(w->codec, 0);
826
827 twl4030->hsl_enabled = 0;
828 break;
829 }
830 return 0;
831}
832
833static int headsetrpga_event(struct snd_soc_dapm_widget *w,
834 struct snd_kcontrol *kcontrol, int event)
835{
b2c812e2 836 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 837
838 switch (event) {
839 case SND_SOC_DAPM_POST_PMU:
840 /* Do the ramp-up only once */
841 if (!twl4030->hsl_enabled)
842 headset_ramp(w->codec, 1);
843
844 twl4030->hsr_enabled = 1;
845 break;
846 case SND_SOC_DAPM_POST_PMD:
847 /* Do the ramp-down only if both headsetL/R is disabled */
848 if (!twl4030->hsl_enabled)
849 headset_ramp(w->codec, 0);
850
851 twl4030->hsr_enabled = 0;
aad749e5
PU		 852 break;
853 }
854 return 0;
855}
856
b0bd53a7
PU		 857/*
858 * Some of the gain controls in TWL (mostly those which are associated with
859 * the outputs) are implemented in an interesting way:
860 * 0x0 : Power down (mute)
861 * 0x1 : 6dB
862 * 0x2 : 0 dB
863 * 0x3 : -6 dB
864 * Inverting not going to help with these.
865 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
866 */
867#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
868 xinvert, tlv_array) \
869{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
870 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
871 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
872 .tlv.p = (tlv_array), \
873 .info = snd_soc_info_volsw, \
874 .get = snd_soc_get_volsw_twl4030, \
875 .put = snd_soc_put_volsw_twl4030, \
876 .private_value = (unsigned long)&(struct soc_mixer_control) \
877 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
878 .max = xmax, .invert = xinvert} }
879#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
880 xinvert, tlv_array) \
881{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
882 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
883 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
884 .tlv.p = (tlv_array), \
885 .info = snd_soc_info_volsw_2r, \
886 .get = snd_soc_get_volsw_r2_twl4030,\
887 .put = snd_soc_put_volsw_r2_twl4030, \
888 .private_value = (unsigned long)&(struct soc_mixer_control) \
889 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 890 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 891#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
892 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
893 xinvert, tlv_array)
894
895static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
896 struct snd_ctl_elem_value *ucontrol)
897{
898 struct soc_mixer_control *mc =
899 (struct soc_mixer_control *)kcontrol->private_value;
900 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
901 unsigned int reg = mc->reg;
902 unsigned int shift = mc->shift;
903 unsigned int rshift = mc->rshift;
904 int max = mc->max;
905 int mask = (1 << fls(max)) - 1;
906
907 ucontrol->value.integer.value[0] =
908 (snd_soc_read(codec, reg) >> shift) & mask;
909 if (ucontrol->value.integer.value[0])
910 ucontrol->value.integer.value[0] =
911 max + 1 - ucontrol->value.integer.value[0];
912
913 if (shift != rshift) {
914 ucontrol->value.integer.value[1] =
915 (snd_soc_read(codec, reg) >> rshift) & mask;
916 if (ucontrol->value.integer.value[1])
917 ucontrol->value.integer.value[1] =
918 max + 1 - ucontrol->value.integer.value[1];
919 }
920
921 return 0;
922}
923
924static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
925 struct snd_ctl_elem_value *ucontrol)
926{
927 struct soc_mixer_control *mc =
928 (struct soc_mixer_control *)kcontrol->private_value;
929 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
930 unsigned int reg = mc->reg;
931 unsigned int shift = mc->shift;
932 unsigned int rshift = mc->rshift;
933 int max = mc->max;
934 int mask = (1 << fls(max)) - 1;
935 unsigned short val, val2, val_mask;
936
937 val = (ucontrol->value.integer.value[0] & mask);
938
939 val_mask = mask << shift;
940 if (val)
941 val = max + 1 - val;
942 val = val << shift;
943 if (shift != rshift) {
944 val2 = (ucontrol->value.integer.value[1] & mask);
945 val_mask |= mask << rshift;
946 if (val2)
947 val2 = max + 1 - val2;
948 val |= val2 << rshift;
949 }
950 return snd_soc_update_bits(codec, reg, val_mask, val);
951}
952
953static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
954 struct snd_ctl_elem_value *ucontrol)
955{
956 struct soc_mixer_control *mc =
957 (struct soc_mixer_control *)kcontrol->private_value;
958 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
959 unsigned int reg = mc->reg;
960 unsigned int reg2 = mc->rreg;
961 unsigned int shift = mc->shift;
962 int max = mc->max;
963 int mask = (1<<fls(max))-1;
964
965 ucontrol->value.integer.value[0] =
966 (snd_soc_read(codec, reg) >> shift) & mask;
967 ucontrol->value.integer.value[1] =
968 (snd_soc_read(codec, reg2) >> shift) & mask;
969
970 if (ucontrol->value.integer.value[0])
971 ucontrol->value.integer.value[0] =
972 max + 1 - ucontrol->value.integer.value[0];
973 if (ucontrol->value.integer.value[1])
974 ucontrol->value.integer.value[1] =
975 max + 1 - ucontrol->value.integer.value[1];
976
977 return 0;
978}
979
980static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
981 struct snd_ctl_elem_value *ucontrol)
982{
983 struct soc_mixer_control *mc =
984 (struct soc_mixer_control *)kcontrol->private_value;
985 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
986 unsigned int reg = mc->reg;
987 unsigned int reg2 = mc->rreg;
988 unsigned int shift = mc->shift;
989 int max = mc->max;
990 int mask = (1 << fls(max)) - 1;
991 int err;
992 unsigned short val, val2, val_mask;
993
994 val_mask = mask << shift;
995 val = (ucontrol->value.integer.value[0] & mask);
996 val2 = (ucontrol->value.integer.value[1] & mask);
997
998 if (val)
999 val = max + 1 - val;
1000 if (val2)
1001 val2 = max + 1 - val2;
1002
1003 val = val << shift;
1004 val2 = val2 << shift;
1005
1006 err = snd_soc_update_bits(codec, reg, val_mask, val);
1007 if (err < 0)
1008 return err;
1009
1010 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1011 return err;
1012}
1013
b74bd40f
LCM		 1014/* Codec operation modes */
1015static const char *twl4030_op_modes_texts[] = {
1016 "Option 2 (voice/audio)", "Option 1 (audio)"
1017};
1018
1019static const struct soc_enum twl4030_op_modes_enum =
1020 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1021 ARRAY_SIZE(twl4030_op_modes_texts),
1022 twl4030_op_modes_texts);
1023
423c238d 1024static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 1025 struct snd_ctl_elem_value *ucontrol)
1026{
1027 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 1028 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1029 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1030 unsigned short val;
1031 unsigned short mask, bitmask;
1032
1033 if (twl4030->configured) {
1034 printk(KERN_ERR "twl4030 operation mode cannot be "
1035 "changed on-the-fly\n");
1036 return -EBUSY;
1037 }
1038
1039 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
1040 ;
1041 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1042 return -EINVAL;
1043
1044 val = ucontrol->value.enumerated.item[0] << e->shift_l;
1045 mask = (bitmask - 1) << e->shift_l;
1046 if (e->shift_l != e->shift_r) {
1047 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1048 return -EINVAL;
1049 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1050 mask |= (bitmask - 1) << e->shift_r;
1051 }
1052
1053 return snd_soc_update_bits(codec, e->reg, mask, val);
1054}
1055
c10b82cf
PU		 1056/*
1057 * FGAIN volume control:
1058 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1059 */
d889a72c 1060static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1061
0d33ea0b
PU		 1062/*
1063 * CGAIN volume control:
1064 * 0 dB to 12 dB in 6 dB steps
1065 * value 2 and 3 means 12 dB
1066 */
d889a72c
PU		 1067static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1068
1a787e7a
JS		 1069/*
1070 * Voice Downlink GAIN volume control:
1071 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1072 */
1073static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1074
d889a72c
PU		 1075/*
1076 * Analog playback gain
1077 * -24 dB to 12 dB in 2 dB steps
1078 */
1079static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1080
4290239c
PU		 1081/*
1082 * Gain controls tied to outputs
1083 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1084 */
1085static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1086
18cc8d8d
JS		 1087/*
1088 * Gain control for earpiece amplifier
1089 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1090 */
1091static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1092
381a22b5
PU		 1093/*
1094 * Capture gain after the ADCs
1095 * from 0 dB to 31 dB in 1 dB steps
1096 */
1097static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1098
5920b453
GI		 1099/*
1100 * Gain control for input amplifiers
1101 * 0 dB to 30 dB in 6 dB steps
1102 */
1103static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1104
328d0a13
LCM		 1105/* AVADC clock priority */
1106static const char *twl4030_avadc_clk_priority_texts[] = {
1107 "Voice high priority", "HiFi high priority"
1108};
1109
1110static const struct soc_enum twl4030_avadc_clk_priority_enum =
1111 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1112 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1113 twl4030_avadc_clk_priority_texts);
1114
89492be8
PU		 1115static const char *twl4030_rampdelay_texts[] = {
1116 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1117 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1118 "3495/2581/1748 ms"
1119};
1120
1121static const struct soc_enum twl4030_rampdelay_enum =
1122 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1123 ARRAY_SIZE(twl4030_rampdelay_texts),
1124 twl4030_rampdelay_texts);
1125
376f7839
PU		 1126/* Vibra H-bridge direction mode */
1127static const char *twl4030_vibradirmode_texts[] = {
1128 "Vibra H-bridge direction", "Audio data MSB",
1129};
1130
1131static const struct soc_enum twl4030_vibradirmode_enum =
1132 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1133 ARRAY_SIZE(twl4030_vibradirmode_texts),
1134 twl4030_vibradirmode_texts);
1135
1136/* Vibra H-bridge direction */
1137static const char *twl4030_vibradir_texts[] = {
1138 "Positive polarity", "Negative polarity",
1139};
1140
1141static const struct soc_enum twl4030_vibradir_enum =
1142 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1143 ARRAY_SIZE(twl4030_vibradir_texts),
1144 twl4030_vibradir_texts);
1145
36aeff61
PU		 1146/* Digimic Left and right swapping */
1147static const char *twl4030_digimicswap_texts[] = {
1148 "Not swapped", "Swapped",
1149};
1150
1151static const struct soc_enum twl4030_digimicswap_enum =
1152 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1153 ARRAY_SIZE(twl4030_digimicswap_texts),
1154 twl4030_digimicswap_texts);
1155
cc17557e 1156static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1157 /* Codec operation mode control */
1158 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1159 snd_soc_get_enum_double,
1160 snd_soc_put_twl4030_opmode_enum_double),
1161
d889a72c
PU		 1162 /* Common playback gain controls */
1163 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1164 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1165 0, 0x3f, 0, digital_fine_tlv),
1166 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1167 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1168 0, 0x3f, 0, digital_fine_tlv),
1169
1170 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1171 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1172 6, 0x2, 0, digital_coarse_tlv),
1173 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1174 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1175 6, 0x2, 0, digital_coarse_tlv),
1176
1177 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1178 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1179 3, 0x12, 1, analog_tlv),
1180 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1181 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1182 3, 0x12, 1, analog_tlv),
44c55870
PU		 1183 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1184 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1185 1, 1, 0),
1186 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1187 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1188 1, 1, 0),
381a22b5 1189
1a787e7a
JS		 1190 /* Common voice downlink gain controls */
1191 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1192 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1193
1194 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1195 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1196
1197 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1198 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1199
4290239c
PU		 1200 /* Separate output gain controls */
1201 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1202 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1203 4, 3, 0, output_tvl),
1204
1205 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1206 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1207
1208 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1209 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1210 4, 3, 0, output_tvl),
1211
1212 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1213 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1214
381a22b5 1215 /* Common capture gain controls */
276c6222 1216 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1217 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1218 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1219 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1220 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1221 0, 0x1f, 0, digital_capture_tlv),
5920b453 1222
276c6222 1223 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1224 0, 3, 5, 0, input_gain_tlv),
89492be8 1225
328d0a13
LCM		 1226 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1227
89492be8 1228 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1229
1230 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1231 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1232
1233 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1234};
1235
cc17557e 1236static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1237 /* Left channel inputs */
1238 SND_SOC_DAPM_INPUT("MAINMIC"),
1239 SND_SOC_DAPM_INPUT("HSMIC"),
1240 SND_SOC_DAPM_INPUT("AUXL"),
1241 SND_SOC_DAPM_INPUT("CARKITMIC"),
1242 /* Right channel inputs */
1243 SND_SOC_DAPM_INPUT("SUBMIC"),
1244 SND_SOC_DAPM_INPUT("AUXR"),
1245 /* Digital microphones (Stereo) */
1246 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1247 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1248
1249 /* Outputs */
5e98a464 1250 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1251 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1252 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1253 SND_SOC_DAPM_OUTPUT("HSOL"),
1254 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1255 SND_SOC_DAPM_OUTPUT("CARKITL"),
1256 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1257 SND_SOC_DAPM_OUTPUT("HFL"),
1258 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1259 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1260
7b4c734e
PU		 1261 /* AIF and APLL clocks for running DAIs (including loopback) */
1262 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1263 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1264 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1265
53b5047d 1266 /* DACs */
b4852b79 1267 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1268 SND_SOC_NOPM, 0, 0),
b4852b79 1269 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1270 SND_SOC_NOPM, 0, 0),
b4852b79 1271 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1272 SND_SOC_NOPM, 0, 0),
b4852b79 1273 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1274 SND_SOC_NOPM, 0, 0),
1a787e7a 1275 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1276 SND_SOC_NOPM, 0, 0),
cc17557e 1277
7393958f 1278 /* Analog bypasses */
78e08e2f
PU		 1279 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1280 &twl4030_dapm_abypassr1_control),
1281 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1282 &twl4030_dapm_abypassl1_control),
1283 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1284 &twl4030_dapm_abypassr2_control),
1285 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1286 &twl4030_dapm_abypassl2_control),
1287 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1288 &twl4030_dapm_abypassv_control),
1289
1290 /* Master analog loopback switch */
1291 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1292 NULL, 0),
7393958f 1293
6bab83fd 1294 /* Digital bypasses */
78e08e2f
PU		 1295 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1296 &twl4030_dapm_dbypassl_control),
1297 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1298 &twl4030_dapm_dbypassr_control),
1299 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1300 &twl4030_dapm_dbypassv_control),
6bab83fd 1301
4005d39a
PU		 1302 /* Digital mixers, power control for the physical DACs */
1303 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1304 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1305 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1306 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1307 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1308 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1309 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1310 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1311 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1312 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1313
1314 /* Analog mixers, power control for the physical PGAs */
1315 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1316 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1317 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1318 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1319 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1320 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1321 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1322 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1323 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1324 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1325
7729cf74
PU		 1326 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1327 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1328
7b4c734e
PU		 1329 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1330 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1331
1a787e7a 1332 /* Output MIXER controls */
5e98a464 1333 /* Earpiece */
1a787e7a
JS		 1334 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1335 &twl4030_dapm_earpiece_controls[0],
1336 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1337 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1338 0, 0, NULL, 0, earpiecepga_event,
1339 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1340 /* PreDrivL/R */
1a787e7a
JS		 1341 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1342 &twl4030_dapm_predrivel_controls[0],
1343 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1344 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1345 0, 0, NULL, 0, predrivelpga_event,
1346 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1347 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1348 &twl4030_dapm_predriver_controls[0],
1349 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1350 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1351 0, 0, NULL, 0, predriverpga_event,
1352 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1353 /* HeadsetL/R */
6943c92e 1354 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1355 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1356 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1357 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1358 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1359 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1360 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1361 &twl4030_dapm_hsor_controls[0],
1362 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1363 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1364 0, 0, NULL, 0, headsetrpga_event,
1365 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1366 /* CarkitL/R */
1a787e7a
JS		 1367 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1368 &twl4030_dapm_carkitl_controls[0],
1369 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1370 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1371 0, 0, NULL, 0, carkitlpga_event,
1372 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1373 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1374 &twl4030_dapm_carkitr_controls[0],
1375 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1376 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1377 0, 0, NULL, 0, carkitrpga_event,
1378 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1379
1380 /* Output MUX controls */
df339804 1381 /* HandsfreeL/R */
5a2e9a48
PU		 1382 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1383 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1384 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1385 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1386 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1387 0, 0, NULL, 0, handsfreelpga_event,
1388 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1389 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1390 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1391 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1392 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1393 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1394 0, 0, NULL, 0, handsfreerpga_event,
1395 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1396 /* Vibra */
86139a13
JV		 1397 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1398 &twl4030_dapm_vibra_control, vibramux_event,
1399 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1400 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1401 &twl4030_dapm_vibrapath_control),
5e98a464 1402
276c6222
PU		 1403 /* Introducing four virtual ADC, since TWL4030 have four channel for
1404 capture */
1405 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1406 SND_SOC_NOPM, 0, 0),
1407 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1408 SND_SOC_NOPM, 0, 0),
1409 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1410 SND_SOC_NOPM, 0, 0),
1411 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1412 SND_SOC_NOPM, 0, 0),
1413
1414 /* Analog/Digital mic path selection.
1415 TX1 Left/Right: either analog Left/Right or Digimic0
1416 TX2 Left/Right: either analog Left/Right or Digimic1 */
1417 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1418 &twl4030_dapm_micpathtx1_control, micpath_event,
1419 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1420 SND_SOC_DAPM_POST_REG),
1421 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1422 &twl4030_dapm_micpathtx2_control, micpath_event,
1423 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1424 SND_SOC_DAPM_POST_REG),
1425
97b8096d 1426 /* Analog input mixers for the capture amplifiers */
9028935d 1427 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1428 TWL4030_REG_ANAMICL, 4, 0,
1429 &twl4030_dapm_analoglmic_controls[0],
1430 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1431 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1432 TWL4030_REG_ANAMICR, 4, 0,
1433 &twl4030_dapm_analogrmic_controls[0],
1434 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1435
fb2a2f84
PU		 1436 SND_SOC_DAPM_PGA("ADC Physical Left",
1437 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1438 SND_SOC_DAPM_PGA("ADC Physical Right",
1439 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1440
1441 SND_SOC_DAPM_PGA("Digimic0 Enable",
1442 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1443 SND_SOC_DAPM_PGA("Digimic1 Enable",
1444 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1445
1446 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1447 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1448 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1449
cc17557e
SS		 1450};
1451
1452static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1453 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1454 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1455 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1456 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1457 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1458
7729cf74 1459 /* Supply for the digital part (APLL) */
7729cf74
PU		 1460 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1461
c42a59ea
PU		 1462 {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
1463 {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
1464 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1465 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1466
4005d39a
PU		 1467 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1468 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1469 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1470 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1471 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1472
5e98a464
PU		 1473 /* Internal playback routings */
1474 /* Earpiece */
4005d39a
PU		 1475 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1476 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1477 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1478 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1479 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1480 /* PreDrivL */
4005d39a
PU		 1481 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1482 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1483 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1484 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1485 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1486 /* PreDrivR */
4005d39a
PU		 1487 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1488 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1489 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1490 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1491 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1492 /* HeadsetL */
4005d39a
PU		 1493 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1494 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1495 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1496 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1497 /* HeadsetR */
4005d39a
PU		 1498 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1499 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1500 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1501 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1502 /* CarkitL */
4005d39a
PU		 1503 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1504 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1505 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1506 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1507 /* CarkitR */
4005d39a
PU		 1508 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1509 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1510 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1511 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1512 /* HandsfreeL */
4005d39a
PU		 1513 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1514 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1515 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1516 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1517 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1518 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1519 /* HandsfreeR */
4005d39a
PU		 1520 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1521 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1522 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1523 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1524 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1525 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1526 /* Vibra */
1527 {"Vibra Mux", "AudioL1", "DAC Left1"},
1528 {"Vibra Mux", "AudioR1", "DAC Right1"},
1529 {"Vibra Mux", "AudioL2", "DAC Left2"},
1530 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1531
cc17557e 1532 /* outputs */
7b4c734e
PU		 1533 /* Must be always connected (for AIF and APLL) */
1534 {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
1535 {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
1536 {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
1537 {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
1538 /* Must be always connected (for APLL) */
1539 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1540 /* Physical outputs */
9008adf9
PU		 1541 {"EARPIECE", NULL, "Earpiece PGA"},
1542 {"PREDRIVEL", NULL, "PredriveL PGA"},
1543 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1544 {"HSOL", NULL, "HeadsetL PGA"},
1545 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1546 {"CARKITL", NULL, "CarkitL PGA"},
1547 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1548 {"HFL", NULL, "HandsfreeL PGA"},
1549 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1550 {"Vibra Route", "Audio", "Vibra Mux"},
1551 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1552
276c6222 1553 /* Capture path */
7b4c734e
PU		 1554 /* Must be always connected (for AIF and APLL) */
1555 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1556 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1557 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1558 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1559 /* Physical inputs */
9028935d
PU		 1560 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1561 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1562 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1563 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1564
9028935d
PU		 1565 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1566 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1567
9028935d
PU		 1568 {"ADC Physical Left", NULL, "Analog Left"},
1569 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1570
1571 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1572 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1573
1574 /* TX1 Left capture path */
fb2a2f84 1575 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1576 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1577 /* TX1 Right capture path */
fb2a2f84 1578 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1579 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1580 /* TX2 Left capture path */
fb2a2f84 1581 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1582 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1583 /* TX2 Right capture path */
fb2a2f84 1584 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1585 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1586
1587 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1588 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1589 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1590 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1591
c42a59ea
PU		 1592 {"ADC Virtual Left1", NULL, "AIF Enable"},
1593 {"ADC Virtual Right1", NULL, "AIF Enable"},
1594 {"ADC Virtual Left2", NULL, "AIF Enable"},
1595 {"ADC Virtual Right2", NULL, "AIF Enable"},
1596
7393958f 1597 /* Analog bypass routes */
9028935d
PU		 1598 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1599 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1600 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1601 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1602 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1603
78e08e2f
PU		 1604 /* Supply for the Analog loopbacks */
1605 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1606 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1607 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1608 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1609 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1610
7393958f
PU		 1611 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1612 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1613 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1614 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1615 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1616
6bab83fd
PU		 1617 /* Digital bypass routes */
1618 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1619 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1620 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1621
4005d39a
PU		 1622 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1623 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1624 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1625
cc17557e
SS		 1626};
1627
1628static int twl4030_add_widgets(struct snd_soc_codec *codec)
1629{
1630 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1631 ARRAY_SIZE(twl4030_dapm_widgets));
1632
1633 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1634
cc17557e
SS		 1635 return 0;
1636}
1637
cc17557e
SS		 1638static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1639 enum snd_soc_bias_level level)
1640{
1641 switch (level) {
1642 case SND_SOC_BIAS_ON:
cc17557e
SS		 1643 break;
1644 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1645 break;
1646 case SND_SOC_BIAS_STANDBY:
78e08e2f 1647 if (codec->bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1648 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1649 break;
1650 case SND_SOC_BIAS_OFF:
cbd2db12 1651 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1652 break;
1653 }
1654 codec->bias_level = level;
1655
1656 return 0;
1657}
1658
6b87a91f
PU		 1659static void twl4030_constraints(struct twl4030_priv *twl4030,
1660 struct snd_pcm_substream *mst_substream)
1661{
1662 struct snd_pcm_substream *slv_substream;
1663
1664 /* Pick the stream, which need to be constrained */
1665 if (mst_substream == twl4030->master_substream)
1666 slv_substream = twl4030->slave_substream;
1667 else if (mst_substream == twl4030->slave_substream)
1668 slv_substream = twl4030->master_substream;
1669 else /* This should not happen.. */
1670 return;
1671
1672 /* Set the constraints according to the already configured stream */
1673 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1674 SNDRV_PCM_HW_PARAM_RATE,
1675 twl4030->rate,
1676 twl4030->rate);
1677
1678 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1679 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1680 twl4030->sample_bits,
1681 twl4030->sample_bits);
1682
1683 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1684 SNDRV_PCM_HW_PARAM_CHANNELS,
1685 twl4030->channels,
1686 twl4030->channels);
1687}
1688
8a1f936a
PU		 1689/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1690 * capture has to be enabled/disabled. */
1691static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1692 int enable)
1693{
1694 u8 reg, mask;
1695
1696 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1697
1698 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1699 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1700 else
1701 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1702
1703 if (enable)
1704 reg |= mask;
1705 else
1706 reg &= ~mask;
1707
1708 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1709}
1710
d6648da1
PU		 1711static int twl4030_startup(struct snd_pcm_substream *substream,
1712 struct snd_soc_dai *dai)
7220b9f4
PU		 1713{
1714 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1715 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1716 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1717 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1718
7220b9f4 1719 if (twl4030->master_substream) {
7220b9f4 1720 twl4030->slave_substream = substream;
6b87a91f
PU		 1721 /* The DAI has one configuration for playback and capture, so
1722 * if the DAI has been already configured then constrain this
1723 * substream to match it. */
1724 if (twl4030->configured)
1725 twl4030_constraints(twl4030, twl4030->master_substream);
1726 } else {
8a1f936a
PU		 1727 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1728 TWL4030_OPTION_1)) {
1729 /* In option2 4 channel is not supported, set the
1730 * constraint for the first stream for channels, the
1731 * second stream will 'inherit' this cosntraint */
1732 snd_pcm_hw_constraint_minmax(substream->runtime,
1733 SNDRV_PCM_HW_PARAM_CHANNELS,
1734 2, 2);
1735 }
7220b9f4 1736 twl4030->master_substream = substream;
6b87a91f 1737 }
7220b9f4
PU		 1738
1739 return 0;
1740}
1741
d6648da1
PU		 1742static void twl4030_shutdown(struct snd_pcm_substream *substream,
1743 struct snd_soc_dai *dai)
7220b9f4
PU		 1744{
1745 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1746 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1747 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1748 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1749
1750 if (twl4030->master_substream == substream)
1751 twl4030->master_substream = twl4030->slave_substream;
1752
1753 twl4030->slave_substream = NULL;
6b87a91f
PU		 1754
1755 /* If all streams are closed, or the remaining stream has not yet
1756 * been configured than set the DAI as not configured. */
1757 if (!twl4030->master_substream)
1758 twl4030->configured = 0;
1759 else if (!twl4030->master_substream->runtime->channels)
1760 twl4030->configured = 0;
8a1f936a
PU		 1761
1762 /* If the closing substream had 4 channel, do the necessary cleanup */
1763 if (substream->runtime->channels == 4)
1764 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1765}
1766
cc17557e 1767static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1768 struct snd_pcm_hw_params *params,
1769 struct snd_soc_dai *dai)
cc17557e
SS		 1770{
1771 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1772 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1773 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1774 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1775 u8 mode, old_mode, format, old_format;
1776
8a1f936a
PU		 1777 /* If the substream has 4 channel, do the necessary setup */
1778 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1779 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1780 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1781
1782 /* Safety check: are we in the correct operating mode and
1783 * the interface is in TDM mode? */
1784 if ((mode & TWL4030_OPTION_1) &&
1785 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1786 twl4030_tdm_enable(codec, substream->stream, 1);
1787 else
1788 return -EINVAL;
1789 }
1790
6b87a91f
PU		 1791 if (twl4030->configured)
1792 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1793 return 0;
1794
cc17557e
SS		 1795 /* bit rate */
1796 old_mode = twl4030_read_reg_cache(codec,
1797 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1798 mode = old_mode & ~TWL4030_APLL_RATE;
1799
1800 switch (params_rate(params)) {
1801 case 8000:
1802 mode |= TWL4030_APLL_RATE_8000;
1803 break;
1804 case 11025:
1805 mode |= TWL4030_APLL_RATE_11025;
1806 break;
1807 case 12000:
1808 mode |= TWL4030_APLL_RATE_12000;
1809 break;
1810 case 16000:
1811 mode |= TWL4030_APLL_RATE_16000;
1812 break;
1813 case 22050:
1814 mode |= TWL4030_APLL_RATE_22050;
1815 break;
1816 case 24000:
1817 mode |= TWL4030_APLL_RATE_24000;
1818 break;
1819 case 32000:
1820 mode |= TWL4030_APLL_RATE_32000;
1821 break;
1822 case 44100:
1823 mode |= TWL4030_APLL_RATE_44100;
1824 break;
1825 case 48000:
1826 mode |= TWL4030_APLL_RATE_48000;
1827 break;
103f211d
PU		 1828 case 96000:
1829 mode |= TWL4030_APLL_RATE_96000;
1830 break;
cc17557e
SS		 1831 default:
1832 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1833 params_rate(params));
1834 return -EINVAL;
1835 }
1836
cc17557e
SS		 1837 /* sample size */
1838 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1839 format = old_format;
1840 format &= ~TWL4030_DATA_WIDTH;
1841 switch (params_format(params)) {
1842 case SNDRV_PCM_FORMAT_S16_LE:
1843 format |= TWL4030_DATA_WIDTH_16S_16W;
1844 break;
1845 case SNDRV_PCM_FORMAT_S24_LE:
1846 format |= TWL4030_DATA_WIDTH_32S_24W;
1847 break;
1848 default:
1849 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1850 params_format(params));
1851 return -EINVAL;
1852 }
1853
2046f175
PU		 1854 if (format != old_format || mode != old_mode) {
1855 if (twl4030->codec_powered) {
1856 /*
1857 * If the codec is powered, than we need to toggle the
1858 * codec power.
1859 */
1860 twl4030_codec_enable(codec, 0);
1861 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1862 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1863 twl4030_codec_enable(codec, 1);
1864 } else {
1865 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1866 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1867 }
cc17557e 1868 }
6b87a91f
PU		 1869
1870 /* Store the important parameters for the DAI configuration and set
1871 * the DAI as configured */
1872 twl4030->configured = 1;
1873 twl4030->rate = params_rate(params);
1874 twl4030->sample_bits = hw_param_interval(params,
1875 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1876 twl4030->channels = params_channels(params);
1877
1878 /* If both playback and capture streams are open, and one of them
1879 * is setting the hw parameters right now (since we are here), set
1880 * constraints to the other stream to match the current one. */
1881 if (twl4030->slave_substream)
1882 twl4030_constraints(twl4030, substream);
1883
cc17557e
SS		 1884 return 0;
1885}
1886
1887static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1888 int clk_id, unsigned int freq, int dir)
1889{
1890 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1891 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1892
1893 switch (freq) {
1894 case 19200000:
cc17557e 1895 case 26000000:
cc17557e 1896 case 38400000:
cc17557e
SS		 1897 break;
1898 default:
68d01955 1899 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
cc17557e
SS		 1900 return -EINVAL;
1901 }
1902
68d01955
PU		 1903 if ((freq / 1000) != twl4030->sysclk) {
1904 dev_err(codec->dev,
1905 "Mismatch in APLL mclk: %u (configured: %u)\n",
1906 freq, twl4030->sysclk * 1000);
1907 return -EINVAL;
1908 }
cc17557e
SS		 1909
1910 return 0;
1911}
1912
1913static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1914 unsigned int fmt)
1915{
1916 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1917 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1918 u8 old_format, format;
1919
1920 /* get format */
1921 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1922 format = old_format;
1923
1924 /* set master/slave audio interface */
1925 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1926 case SND_SOC_DAIFMT_CBM_CFM:
1927 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1928 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1929 break;
1930 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1931 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1932 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1933 break;
1934 default:
1935 return -EINVAL;
1936 }
1937
1938 /* interface format */
1939 format &= ~TWL4030_AIF_FORMAT;
1940 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1941 case SND_SOC_DAIFMT_I2S:
1942 format |= TWL4030_AIF_FORMAT_CODEC;
1943 break;
8a1f936a
PU		 1944 case SND_SOC_DAIFMT_DSP_A:
1945 format |= TWL4030_AIF_FORMAT_TDM;
1946 break;
cc17557e
SS		 1947 default:
1948 return -EINVAL;
1949 }
1950
1951 if (format != old_format) {
2046f175
PU		 1952 if (twl4030->codec_powered) {
1953 /*
1954 * If the codec is powered, than we need to toggle the
1955 * codec power.
1956 */
1957 twl4030_codec_enable(codec, 0);
1958 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1959 twl4030_codec_enable(codec, 1);
1960 } else {
1961 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1962 }
cc17557e
SS		 1963 }
1964
1965 return 0;
1966}
1967
68140443
LCM		 1968static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1969{
1970 struct snd_soc_codec *codec = dai->codec;
1971 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1972
1973 if (tristate)
1974 reg |= TWL4030_AIF_TRI_EN;
1975 else
1976 reg &= ~TWL4030_AIF_TRI_EN;
1977
1978 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1979}
1980
b7a755a8
MLC		 1981/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1982 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1983static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1984 int enable)
1985{
1986 u8 reg, mask;
1987
1988 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1989
1990 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1991 mask = TWL4030_ARXL1_VRX_EN;
1992 else
1993 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1994
1995 if (enable)
1996 reg |= mask;
1997 else
1998 reg &= ~mask;
1999
2000 twl4030_write(codec, TWL4030_REG_OPTION, reg);
2001}
2002
7154b3e8
JS		 2003static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2004 struct snd_soc_dai *dai)
2005{
2006 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2007 struct snd_soc_device *socdev = rtd->socdev;
2008 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 2009 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2010 u8 mode;
2011
2012 /* If the system master clock is not 26MHz, the voice PCM interface is
2013 * not avilable.
2014 */
68d01955
PU		 2015 if (twl4030->sysclk != 26000) {
2016 dev_err(codec->dev, "The board is configured for %u Hz, while"
2017 "the Voice interface needs 26MHz APLL mclk\n",
2018 twl4030->sysclk * 1000);
7154b3e8
JS		 2019 return -EINVAL;
2020 }
2021
2022 /* If the codec mode is not option2, the voice PCM interface is not
2023 * avilable.
2024 */
2025 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2026 & TWL4030_OPT_MODE;
2027
2028 if (mode != TWL4030_OPTION_2) {
2029 printk(KERN_ERR "TWL4030 voice startup: "
2030 "the codec mode is not option2\n");
2031 return -EINVAL;
2032 }
2033
2034 return 0;
2035}
2036
b7a755a8
MLC		 2037static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2038 struct snd_soc_dai *dai)
2039{
2040 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2041 struct snd_soc_device *socdev = rtd->socdev;
2042 struct snd_soc_codec *codec = socdev->card->codec;
2043
2044 /* Enable voice digital filters */
2045 twl4030_voice_enable(codec, substream->stream, 0);
2046}
2047
7154b3e8
JS		 2048static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2049 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2050{
2051 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2052 struct snd_soc_device *socdev = rtd->socdev;
2053 struct snd_soc_codec *codec = socdev->card->codec;
2046f175 2054 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2055 u8 old_mode, mode;
2056
b7a755a8
MLC		 2057 /* Enable voice digital filters */
2058 twl4030_voice_enable(codec, substream->stream, 1);
2059
7154b3e8
JS		 2060 /* bit rate */
2061 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2062 & ~(TWL4030_CODECPDZ);
2063 mode = old_mode;
2064
2065 switch (params_rate(params)) {
2066 case 8000:
2067 mode &= ~(TWL4030_SEL_16K);
2068 break;
2069 case 16000:
2070 mode |= TWL4030_SEL_16K;
2071 break;
2072 default:
2073 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
2074 params_rate(params));
2075 return -EINVAL;
2076 }
2077
2078 if (mode != old_mode) {
2046f175
PU		 2079 if (twl4030->codec_powered) {
2080 /*
2081 * If the codec is powered, than we need to toggle the
2082 * codec power.
2083 */
2084 twl4030_codec_enable(codec, 0);
2085 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2086 twl4030_codec_enable(codec, 1);
2087 } else {
2088 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2089 }
7154b3e8
JS		 2090 }
2091
2092 return 0;
2093}
2094
2095static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2096 int clk_id, unsigned int freq, int dir)
2097{
2098 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2099 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2100
68d01955
PU		 2101 if (freq != 26000000) {
2102 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
2103 "interface needs 26MHz APLL mclk\n", freq);
2104 return -EINVAL;
2105 }
2106 if ((freq / 1000) != twl4030->sysclk) {
2107 dev_err(codec->dev,
2108 "Mismatch in APLL mclk: %u (configured: %u)\n",
2109 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2110 return -EINVAL;
2111 }
7154b3e8
JS		 2112 return 0;
2113}
2114
2115static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2116 unsigned int fmt)
2117{
2118 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2119 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2120 u8 old_format, format;
2121
2122 /* get format */
2123 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2124 format = old_format;
2125
2126 /* set master/slave audio interface */
2127 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2128 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2129 format &= ~(TWL4030_VIF_SLAVE_EN);
2130 break;
2131 case SND_SOC_DAIFMT_CBS_CFS:
2132 format |= TWL4030_VIF_SLAVE_EN;
2133 break;
2134 default:
2135 return -EINVAL;
2136 }
2137
2138 /* clock inversion */
2139 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2140 case SND_SOC_DAIFMT_IB_NF:
2141 format &= ~(TWL4030_VIF_FORMAT);
2142 break;
2143 case SND_SOC_DAIFMT_NB_IF:
2144 format |= TWL4030_VIF_FORMAT;
2145 break;
2146 default:
2147 return -EINVAL;
2148 }
2149
2150 if (format != old_format) {
2046f175
PU		 2151 if (twl4030->codec_powered) {
2152 /*
2153 * If the codec is powered, than we need to toggle the
2154 * codec power.
2155 */
2156 twl4030_codec_enable(codec, 0);
2157 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2158 twl4030_codec_enable(codec, 1);
2159 } else {
2160 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2161 }
7154b3e8
JS		 2162 }
2163
2164 return 0;
2165}
2166
68140443
LCM		 2167static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2168{
2169 struct snd_soc_codec *codec = dai->codec;
2170 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2171
2172 if (tristate)
2173 reg |= TWL4030_VIF_TRI_EN;
2174 else
2175 reg &= ~TWL4030_VIF_TRI_EN;
2176
2177 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2178}
2179
bbba9444 2180#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2181#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2182
10d9e3d9 2183static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 2184 .startup = twl4030_startup,
2185 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2186 .hw_params = twl4030_hw_params,
2187 .set_sysclk = twl4030_set_dai_sysclk,
2188 .set_fmt = twl4030_set_dai_fmt,
68140443 2189 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2190};
2191
7154b3e8
JS		 2192static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2193 .startup = twl4030_voice_startup,
b7a755a8 2194 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2195 .hw_params = twl4030_voice_hw_params,
2196 .set_sysclk = twl4030_voice_set_dai_sysclk,
2197 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2198 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2199};
2200
2201struct snd_soc_dai twl4030_dai[] = {
2202{
cc17557e
SS		 2203 .name = "twl4030",
2204 .playback = {
b4852b79 2205 .stream_name = "HiFi Playback",
cc17557e 2206 .channels_min = 2,
8a1f936a 2207 .channels_max = 4,
31ad0f31 2208 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2209 .formats = TWL4030_FORMATS,},
2210 .capture = {
2211 .stream_name = "Capture",
2212 .channels_min = 2,
8a1f936a 2213 .channels_max = 4,
cc17557e
SS		 2214 .rates = TWL4030_RATES,
2215 .formats = TWL4030_FORMATS,},
10d9e3d9 2216 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2217},
2218{
2219 .name = "twl4030 Voice",
2220 .playback = {
b4852b79 2221 .stream_name = "Voice Playback",
7154b3e8
JS		 2222 .channels_min = 1,
2223 .channels_max = 1,
2224 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2225 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2226 .capture = {
2227 .stream_name = "Capture",
2228 .channels_min = 1,
2229 .channels_max = 2,
2230 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2231 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2232 .ops = &twl4030_dai_voice_ops,
2233},
cc17557e
SS		 2234};
2235EXPORT_SYMBOL_GPL(twl4030_dai);
2236
7a1fecf5 2237static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
cc17557e
SS		 2238{
2239 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2240 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2241
2242 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2243
2244 return 0;
2245}
2246
7a1fecf5 2247static int twl4030_soc_resume(struct platform_device *pdev)
cc17557e
SS		 2248{
2249 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2250 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2251
2252 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
cc17557e
SS		 2253 return 0;
2254}
2255
7a1fecf5 2256static struct snd_soc_codec *twl4030_codec;
cc17557e 2257
7a1fecf5 2258static int twl4030_soc_probe(struct platform_device *pdev)
cc17557e 2259{
7a1fecf5 2260 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5 2261 struct snd_soc_codec *codec;
7a1fecf5 2262 int ret;
cc17557e 2263
7a1fecf5 2264 BUG_ON(!twl4030_codec);
cc17557e 2265
7a1fecf5 2266 codec = twl4030_codec;
7a1fecf5 2267 socdev->card->codec = codec;
cc17557e 2268
ee4ccac7 2269 twl4030_init_chip(pdev);
9da28c7b 2270
cc17557e
SS		 2271 /* register pcms */
2272 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2273 if (ret < 0) {
7a1fecf5
PU		 2274 dev_err(&pdev->dev, "failed to create pcms\n");
2275 return ret;
cc17557e
SS		 2276 }
2277
3e8e1952
IM		 2278 snd_soc_add_controls(codec, twl4030_snd_controls,
2279 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2280 twl4030_add_widgets(codec);
2281
7a1fecf5 2282 return 0;
cc17557e
SS		 2283}
2284
7a1fecf5 2285static int twl4030_soc_remove(struct platform_device *pdev)
cc17557e
SS		 2286{
2287 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
7a1fecf5
PU		 2288 struct snd_soc_codec *codec = socdev->card->codec;
2289
a3a29b55
PU		 2290 /* Reset registers to their chip default before leaving */
2291 twl4030_reset_registers(codec);
7a1fecf5
PU		 2292 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2293 snd_soc_free_pcms(socdev);
2294 snd_soc_dapm_free(socdev);
7a1fecf5
PU		 2295
2296 return 0;
2297}
2298
2299static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2300{
2301 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2302 struct snd_soc_codec *codec;
7393958f 2303 struct twl4030_priv *twl4030;
7a1fecf5 2304 int ret;
cc17557e 2305
68d01955
PU		 2306 if (!pdata) {
2307 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2308 return -EINVAL;
2309 }
cc17557e 2310
7393958f
PU		 2311 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2312 if (twl4030 == NULL) {
7a1fecf5 2313 dev_err(&pdev->dev, "Can not allocate memroy\n");
7393958f
PU		 2314 return -ENOMEM;
2315 }
2316
7a1fecf5 2317 codec = &twl4030->codec;
b2c812e2 2318 snd_soc_codec_set_drvdata(codec, twl4030);
7a1fecf5
PU		 2319 codec->dev = &pdev->dev;
2320 twl4030_dai[0].dev = &pdev->dev;
2321 twl4030_dai[1].dev = &pdev->dev;
2322
cc17557e
SS		 2323 mutex_init(&codec->mutex);
2324 INIT_LIST_HEAD(&codec->dapm_widgets);
2325 INIT_LIST_HEAD(&codec->dapm_paths);
2326
7a1fecf5
PU		 2327 codec->name = "twl4030";
2328 codec->owner = THIS_MODULE;
2329 codec->read = twl4030_read_reg_cache;
2330 codec->write = twl4030_write;
2331 codec->set_bias_level = twl4030_set_bias_level;
2046f175 2332 codec->idle_bias_off = 1;
7a1fecf5 2333 codec->dai = twl4030_dai;
fd63df22 2334 codec->num_dai = ARRAY_SIZE(twl4030_dai);
7a1fecf5
PU		 2335 codec->reg_cache_size = sizeof(twl4030_reg);
2336 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2337 GFP_KERNEL);
2338 if (codec->reg_cache == NULL) {
2339 ret = -ENOMEM;
2340 goto error_cache;
2341 }
2342
2343 platform_set_drvdata(pdev, twl4030);
2344 twl4030_codec = codec;
2345
2346 /* Set the defaults, and power up the codec */
68d01955 2347 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
b3f5a272 2348 codec->bias_level = SND_SOC_BIAS_OFF;
7a1fecf5
PU		 2349
2350 ret = snd_soc_register_codec(codec);
2351 if (ret != 0) {
2352 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2353 goto error_codec;
2354 }
2355
2356 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2357 if (ret != 0) {
2358 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2359 snd_soc_unregister_codec(codec);
2360 goto error_codec;
2361 }
cc17557e
SS		 2362
2363 return 0;
7a1fecf5
PU		 2364
2365error_codec:
cbd2db12 2366 twl4030_codec_enable(codec, 0);
7a1fecf5
PU		 2367 kfree(codec->reg_cache);
2368error_cache:
2369 kfree(twl4030);
2370 return ret;
cc17557e
SS		 2371}
2372
7a1fecf5 2373static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2374{
7a1fecf5 2375 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
cc17557e 2376
cb67286d
PU		 2377 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2378 snd_soc_unregister_codec(&twl4030->codec);
2379 kfree(twl4030->codec.reg_cache);
7a1fecf5 2380 kfree(twl4030);
cc17557e 2381
7a1fecf5 2382 twl4030_codec = NULL;
cc17557e
SS		 2383 return 0;
2384}
2385
7a1fecf5
PU		 2386MODULE_ALIAS("platform:twl4030_codec_audio");
2387
2388static struct platform_driver twl4030_codec_driver = {
2389 .probe = twl4030_codec_probe,
2390 .remove = __devexit_p(twl4030_codec_remove),
2391 .driver = {
2392 .name = "twl4030_codec_audio",
2393 .owner = THIS_MODULE,
2394 },
cc17557e 2395};
cc17557e 2396
24e07db8 2397static int __init twl4030_modinit(void)
64089b84 2398{
7a1fecf5 2399 return platform_driver_register(&twl4030_codec_driver);
64089b84 2400}
24e07db8 2401module_init(twl4030_modinit);
64089b84
MB		 2402
2403static void __exit twl4030_exit(void)
2404{
7a1fecf5 2405 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2406}
2407module_exit(twl4030_exit);
2408
7a1fecf5
PU		 2409struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2410 .probe = twl4030_soc_probe,
2411 .remove = twl4030_soc_remove,
2412 .suspend = twl4030_soc_suspend,
2413 .resume = twl4030_soc_resume,
2414};
2415EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2416
cc17557e
SS		 2417MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2418MODULE_AUTHOR("Steve Sakoman");
2419MODULE_LICENSE("GPL");
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