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ASoC: twl4030: Parameter alignment fixes (for code consistency)
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
2d6d649a
PU		 29#include <linux/of.h>
30#include <linux/of_gpio.h>
b07682b6 31#include <linux/i2c/twl.h>
5a0e3ad6 32#include <linux/slab.h>
281ecd16 33#include <linux/gpio.h>
cc17557e
SS		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
cc17557e 38#include <sound/initval.h>
c10b82cf 39#include <sound/tlv.h>
cc17557e 40
f0fba2ad 41/* Register descriptions are here */
57fe7251 42#include <linux/mfd/twl4030-audio.h>
f0fba2ad 43
5712ded9
PU		 44/* TWL4030 PMBR1 Register */
45#define TWL4030_PMBR1_REG 0x0D
46/* TWL4030 PMBR1 Register GPIO6 mux bits */
47#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
48
052901f4 49#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1)
cc17557e 50
7393958f
PU		 51/* codec private data */
52struct twl4030_priv {
7393958f 53 unsigned int codec_powered;
7b4c734e
PU		 54
55 /* reference counts of AIF/APLL users */
2845fa13 56 unsigned int apll_enabled;
7220b9f4
PU		 57
58 struct snd_pcm_substream *master_substream;
59 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 60
61 unsigned int configured;
62 unsigned int rate;
63 unsigned int sample_bits;
64 unsigned int channels;
6943c92e
PU		 65
66 unsigned int sysclk;
67
c96907f2
PU		 68 /* Output (with associated amp) states */
69 u8 hsl_enabled, hsr_enabled;
70 u8 earpiece_enabled;
71 u8 predrivel_enabled, predriver_enabled;
72 u8 carkitl_enabled, carkitr_enabled;
8b3bca29 73 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
01ea6ba2 74
182f73f6 75 struct twl4030_codec_data *pdata;
7393958f
PU		 76};
77
8b3bca29
PU		 78static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030)
79{
80 int i;
81 u8 byte;
82
83 for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) {
84 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i);
85 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte;
86 }
87}
88
efc8acff
PU		 89static void twl4030_update_ctl_cache(struct snd_soc_codec *codec,
90 unsigned int reg, unsigned int value)
cc17557e 91{
efc8acff 92 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
91432e97 93
efc8acff
PU		 94 switch (reg) {
95 case TWL4030_REG_EAR_CTL:
96 case TWL4030_REG_PREDL_CTL:
97 case TWL4030_REG_PREDR_CTL:
98 case TWL4030_REG_PRECKL_CTL:
99 case TWL4030_REG_PRECKR_CTL:
100 case TWL4030_REG_HS_GAIN_SET:
101 twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value;
102 break;
103 default:
104 break;
105 }
cc17557e
SS		 106}
107
efc8acff 108static unsigned int twl4030_read(struct snd_soc_codec *codec, unsigned int reg)
cc17557e 109{
efc8acff
PU		 110 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
111 u8 value = 0;
cc17557e
SS		 112
113 if (reg >= TWL4030_CACHEREGNUM)
efc8acff
PU		 114 return -EIO;
115
116 switch (reg) {
117 case TWL4030_REG_EAR_CTL:
118 case TWL4030_REG_PREDL_CTL:
119 case TWL4030_REG_PREDR_CTL:
120 case TWL4030_REG_PRECKL_CTL:
121 case TWL4030_REG_PRECKR_CTL:
122 case TWL4030_REG_HS_GAIN_SET:
123 value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL];
124 break;
125 default:
126 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg);
127 break;
128 }
129
130 return value;
cc17557e
SS		 131}
132
a8fc415c
PU		 133static bool twl4030_can_write_to_chip(struct snd_soc_codec *codec,
134 unsigned int reg)
cc17557e 135{
b2c812e2 136 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
a8fc415c 137 bool write_to_reg = false;
c96907f2 138
052901f4
LPC		 139 /* Decide if the given register can be written */
140 switch (reg) {
141 case TWL4030_REG_EAR_CTL:
142 if (twl4030->earpiece_enabled)
a8fc415c 143 write_to_reg = true;
052901f4
LPC		 144 break;
145 case TWL4030_REG_PREDL_CTL:
146 if (twl4030->predrivel_enabled)
a8fc415c 147 write_to_reg = true;
052901f4
LPC		 148 break;
149 case TWL4030_REG_PREDR_CTL:
150 if (twl4030->predriver_enabled)
a8fc415c 151 write_to_reg = true;
052901f4
LPC		 152 break;
153 case TWL4030_REG_PRECKL_CTL:
154 if (twl4030->carkitl_enabled)
a8fc415c 155 write_to_reg = true;
052901f4
LPC		 156 break;
157 case TWL4030_REG_PRECKR_CTL:
158 if (twl4030->carkitr_enabled)
a8fc415c 159 write_to_reg = true;
052901f4
LPC		 160 break;
161 case TWL4030_REG_HS_GAIN_SET:
162 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
a8fc415c 163 write_to_reg = true;
052901f4
LPC		 164 break;
165 default:
166 /* All other register can be written */
a8fc415c 167 write_to_reg = true;
052901f4 168 break;
c96907f2 169 }
a8fc415c
PU		 170
171 return write_to_reg;
172}
173
7ded5fe0
PU		 174static int twl4030_write(struct snd_soc_codec *codec, unsigned int reg,
175 unsigned int value)
a8fc415c 176{
efc8acff 177 twl4030_update_ctl_cache(codec, reg, value);
a8fc415c
PU		 178 if (twl4030_can_write_to_chip(codec, reg))
179 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
052901f4 180
c96907f2 181 return 0;
cc17557e
SS		 182}
183
7e6120c5
PU		 184static inline void twl4030_wait_ms(int time)
185{
186 if (time < 60) {
187 time *= 1000;
188 usleep_range(time, time + 500);
189 } else {
190 msleep(time);
191 }
192}
193
db04e2c5 194static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 195{
b2c812e2 196 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 197 int mode;
cc17557e 198
7393958f
PU		 199 if (enable == twl4030->codec_powered)
200 return;
201
db04e2c5 202 if (enable)
57fe7251 203 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
db04e2c5 204 else
57fe7251 205 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
cc17557e 206
efc8acff 207 if (mode >= 0)
7a1fecf5 208 twl4030->codec_powered = enable;
cc17557e
SS		 209
210 /* REVISIT: this delay is present in TI sample drivers */
211 /* but there seems to be no TRM requirement for it */
212 udelay(10);
213}
214
2d6d649a
PU		 215static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
216 struct device_node *node)
217{
218 int value;
219
220 of_property_read_u32(node, "ti,digimic_delay",
221 &pdata->digimic_delay);
222 of_property_read_u32(node, "ti,ramp_delay_value",
223 &pdata->ramp_delay_value);
224 of_property_read_u32(node, "ti,offset_cncl_path",
225 &pdata->offset_cncl_path);
226 if (!of_property_read_u32(node, "ti,hs_extmute", &value))
227 pdata->hs_extmute = value;
228
229 pdata->hs_extmute_gpio = of_get_named_gpio(node,
230 "ti,hs_extmute_gpio", 0);
231 if (gpio_is_valid(pdata->hs_extmute_gpio))
232 pdata->hs_extmute = 1;
233}
234
235static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
7393958f 236{
4ae6df5e 237 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
2d6d649a
PU		 238 struct device_node *twl4030_codec_node = NULL;
239
240 twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
241 "codec");
242
243 if (!pdata && twl4030_codec_node) {
244 pdata = devm_kzalloc(codec->dev,
245 sizeof(struct twl4030_codec_data),
246 GFP_KERNEL);
247 if (!pdata) {
248 dev_err(codec->dev, "Can not allocate memory\n");
249 return NULL;
250 }
251 twl4030_setup_pdata_of(pdata, twl4030_codec_node);
252 }
253
254 return pdata;
255}
256
257static void twl4030_init_chip(struct snd_soc_codec *codec)
258{
259 struct twl4030_codec_data *pdata;
b2c812e2 260 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 261 u8 reg, byte;
262 int i = 0;
7393958f 263
2d6d649a
PU		 264 pdata = twl4030_get_pdata(codec);
265
5712ded9
PU		 266 if (pdata && pdata->hs_extmute) {
267 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
268 int ret;
269
270 if (!pdata->hs_extmute_gpio)
271 dev_warn(codec->dev,
272 "Extmute GPIO is 0 is this correct?\n");
273
274 ret = gpio_request_one(pdata->hs_extmute_gpio,
275 GPIOF_OUT_INIT_LOW,
276 "hs_extmute");
277 if (ret) {
278 dev_err(codec->dev,
279 "Failed to get hs_extmute GPIO\n");
280 pdata->hs_extmute_gpio = -1;
281 }
282 } else {
283 u8 pin_mux;
284
285 /* Set TWL4030 GPIO6 as EXTMUTE signal */
286 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
287 TWL4030_PMBR1_REG);
288 pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
289 pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
290 twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
291 TWL4030_PMBR1_REG);
281ecd16
PU		 292 }
293 }
294
8b3bca29
PU		 295 /* Initialize the local ctl register cache */
296 tw4030_init_ctl_cache(twl4030);
297
ee4ccac7 298 /* anti-pop when changing analog gain */
efc8acff 299 reg = twl4030_read(codec, TWL4030_REG_MISC_SET_1);
ee4ccac7 300 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
7ded5fe0 301 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 302
ee4ccac7 303 twl4030_write(codec, TWL4030_REG_OPTION,
7ded5fe0
PU		 304 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
305 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 306
3c36cc68
PU		 307 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
308 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
309
ee4ccac7 310 /* Machine dependent setup */
f0fba2ad 311 if (!pdata)
7393958f
PU		 312 return;
313
182f73f6 314 twl4030->pdata = pdata;
ee4ccac7 315
efc8acff 316 reg = twl4030_read(codec, TWL4030_REG_HS_POPN_SET);
ee4ccac7 317 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 318 reg |= (pdata->ramp_delay_value << 2);
efc8acff 319 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 320
321 /* initiate offset cancellation */
ee4ccac7
PU		 322 twl4030_codec_enable(codec, 1);
323
efc8acff 324 reg = twl4030_read(codec, TWL4030_REG_ANAMICL);
ee4ccac7 325 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 326 reg |= pdata->offset_cncl_path;
006f367e 327 twl4030_write(codec, TWL4030_REG_ANAMICL,
7ded5fe0 328 reg | TWL4030_CNCL_OFFSET_START);
006f367e 329
7e6120c5
PU		 330 /*
331 * Wait for offset cancellation to complete.
332 * Since this takes a while, do not slam the i2c.
333 * Start polling the status after ~20ms.
334 */
335 msleep(20);
006f367e 336 do {
7e6120c5 337 usleep_range(1000, 2000);
efc8acff 338 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, true);
fc7b92fc 339 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
7ded5fe0 340 TWL4030_REG_ANAMICL);
efc8acff 341 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, false);
006f367e
PU		 342 } while ((i++ < 100) &&
343 ((byte & TWL4030_CNCL_OFFSET_START) ==
344 TWL4030_CNCL_OFFSET_START));
345
006f367e 346 twl4030_codec_enable(codec, 0);
006f367e
PU		 347}
348
ee4ccac7 349static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 350{
ee4ccac7
PU		 351 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
352 int status = -1;
353
354 if (enable) {
355 twl4030->apll_enabled++;
356 if (twl4030->apll_enabled == 1)
57fe7251
PU		 357 status = twl4030_audio_enable_resource(
358 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 359 } else {
360 twl4030->apll_enabled--;
361 if (!twl4030->apll_enabled)
57fe7251
PU		 362 status = twl4030_audio_disable_resource(
363 TWL4030_AUDIO_RES_APLL);
ee4ccac7 364 }
006f367e
PU		 365}
366
5e98a464 367/* Earpiece */
1a787e7a
JS		 368static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
369 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
370 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
371 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
372 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
373};
5e98a464 374
2a6f5c58 375/* PreDrive Left */
1a787e7a
JS		 376static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
377 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
378 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
379 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
380 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
381};
2a6f5c58
PU		 382
383/* PreDrive Right */
1a787e7a
JS		 384static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
385 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
386 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
387 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
388 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
389};
2a6f5c58 390
dfad21a2 391/* Headset Left */
1a787e7a
JS		 392static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
393 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
394 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
395 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
396};
dfad21a2
PU		 397
398/* Headset Right */
1a787e7a
JS		 399static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
400 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
401 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
402 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
403};
dfad21a2 404
5152d8c2 405/* Carkit Left */
1a787e7a
JS		 406static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
407 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
408 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
409 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
410};
5152d8c2
PU		 411
412/* Carkit Right */
1a787e7a
JS		 413static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
414 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
415 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
416 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
417};
5152d8c2 418
df339804
PU		 419/* Handsfree Left */
420static const char *twl4030_handsfreel_texts[] =
1a787e7a 421 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 422
423static const struct soc_enum twl4030_handsfreel_enum =
424 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
425 ARRAY_SIZE(twl4030_handsfreel_texts),
426 twl4030_handsfreel_texts);
427
428static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
429SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
430
0f89bdca
PU		 431/* Handsfree Left virtual mute */
432static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
052901f4 433 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 434
df339804
PU		 435/* Handsfree Right */
436static const char *twl4030_handsfreer_texts[] =
1a787e7a 437 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 438
439static const struct soc_enum twl4030_handsfreer_enum =
440 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
441 ARRAY_SIZE(twl4030_handsfreer_texts),
442 twl4030_handsfreer_texts);
443
444static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
445SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
446
0f89bdca
PU		 447/* Handsfree Right virtual mute */
448static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
052901f4 449 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 450
376f7839
PU		 451/* Vibra */
452/* Vibra audio path selection */
453static const char *twl4030_vibra_texts[] =
454 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
455
456static const struct soc_enum twl4030_vibra_enum =
457 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
458 ARRAY_SIZE(twl4030_vibra_texts),
459 twl4030_vibra_texts);
460
461static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
462SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
463
464/* Vibra path selection: local vibrator (PWM) or audio driven */
465static const char *twl4030_vibrapath_texts[] =
466 {"Local vibrator", "Audio"};
467
468static const struct soc_enum twl4030_vibrapath_enum =
469 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
470 ARRAY_SIZE(twl4030_vibrapath_texts),
471 twl4030_vibrapath_texts);
472
473static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
474SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
475
276c6222 476/* Left analog microphone selection */
97b8096d 477static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 478 SOC_DAPM_SINGLE("Main Mic Capture Switch",
479 TWL4030_REG_ANAMICL, 0, 1, 0),
480 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
481 TWL4030_REG_ANAMICL, 1, 1, 0),
482 SOC_DAPM_SINGLE("AUXL Capture Switch",
483 TWL4030_REG_ANAMICL, 2, 1, 0),
484 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
485 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 486};
276c6222
PU		 487
488/* Right analog microphone selection */
97b8096d 489static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 490 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
491 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 492};
276c6222
PU		 493
494/* TX1 L/R Analog/Digital microphone selection */
495static const char *twl4030_micpathtx1_texts[] =
496 {"Analog", "Digimic0"};
497
498static const struct soc_enum twl4030_micpathtx1_enum =
499 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
500 ARRAY_SIZE(twl4030_micpathtx1_texts),
501 twl4030_micpathtx1_texts);
502
503static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
504SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
505
506/* TX2 L/R Analog/Digital microphone selection */
507static const char *twl4030_micpathtx2_texts[] =
508 {"Analog", "Digimic1"};
509
510static const struct soc_enum twl4030_micpathtx2_enum =
511 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
512 ARRAY_SIZE(twl4030_micpathtx2_texts),
513 twl4030_micpathtx2_texts);
514
515static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
516SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
517
7393958f
PU		 518/* Analog bypass for AudioR1 */
519static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
520 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
521
522/* Analog bypass for AudioL1 */
523static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
524 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
525
526/* Analog bypass for AudioR2 */
527static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
528 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
529
530/* Analog bypass for AudioL2 */
531static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
532 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
533
fcd274a3
LCM		 534/* Analog bypass for Voice */
535static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
536 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
537
8b0d3153 538/* Digital bypass gain, mute instead of -30dB */
6bab83fd 539static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 540 TLV_DB_RANGE_HEAD(3),
541 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
542 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 543 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
544};
545
546/* Digital bypass left (TX1L -> RX2L) */
547static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
548 SOC_DAPM_SINGLE_TLV("Volume",
549 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
550 twl4030_dapm_dbypass_tlv);
551
552/* Digital bypass right (TX1R -> RX2R) */
553static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
554 SOC_DAPM_SINGLE_TLV("Volume",
555 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
556 twl4030_dapm_dbypass_tlv);
557
ee8f6894
LCM		 558/*
559 * Voice Sidetone GAIN volume control:
560 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
561 */
562static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
563
564/* Digital bypass voice: sidetone (VUL -> VDL)*/
565static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
566 SOC_DAPM_SINGLE_TLV("Volume",
567 TWL4030_REG_VSTPGA, 0, 0x29, 0,
568 twl4030_dapm_dbypassv_tlv);
569
9008adf9
PU		 570/*
571 * Output PGA builder:
572 * Handle the muting and unmuting of the given output (turning off the
573 * amplifier associated with the output pin)
c96907f2
PU		 574 * On mute bypass the reg_cache and write 0 to the register
575 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 576 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
577 */
578#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
579static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
7ded5fe0 580 struct snd_kcontrol *kcontrol, int event) \
9008adf9 581{ \
b2c812e2 582 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 583 \
584 switch (event) { \
585 case SND_SOC_DAPM_POST_PMU: \
c96907f2 586 twl4030->pin_name##_enabled = 1; \
efc8acff 587 twl4030_write(w->codec, reg, twl4030_read(w->codec, reg)); \
9008adf9
PU		 588 break; \
589 case SND_SOC_DAPM_POST_PMD: \
c96907f2 590 twl4030->pin_name##_enabled = 0; \
7ded5fe0 591 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg); \
9008adf9
PU		 592 break; \
593 } \
594 return 0; \
595}
596
597TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
598TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
599TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
600TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
601TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
602
5a2e9a48 603static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 604{
49d92c7d
SM		 605 unsigned char hs_ctl;
606
efc8acff 607 hs_ctl = twl4030_read(codec, reg);
49d92c7d 608
5a2e9a48
PU		 609 if (ramp) {
610 /* HF ramp-up */
611 hs_ctl |= TWL4030_HF_CTL_REF_EN;
612 twl4030_write(codec, reg, hs_ctl);
613 udelay(10);
49d92c7d 614 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 615 twl4030_write(codec, reg, hs_ctl);
616 udelay(40);
49d92c7d 617 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 618 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 619 twl4030_write(codec, reg, hs_ctl);
49d92c7d 620 } else {
5a2e9a48
PU		 621 /* HF ramp-down */
622 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
623 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
624 twl4030_write(codec, reg, hs_ctl);
625 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
626 twl4030_write(codec, reg, hs_ctl);
627 udelay(40);
628 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
629 twl4030_write(codec, reg, hs_ctl);
49d92c7d 630 }
5a2e9a48 631}
49d92c7d 632
5a2e9a48 633static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 634 struct snd_kcontrol *kcontrol, int event)
5a2e9a48
PU		 635{
636 switch (event) {
637 case SND_SOC_DAPM_POST_PMU:
638 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
639 break;
640 case SND_SOC_DAPM_POST_PMD:
641 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
642 break;
643 }
644 return 0;
645}
646
647static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 648 struct snd_kcontrol *kcontrol, int event)
5a2e9a48
PU		 649{
650 switch (event) {
651 case SND_SOC_DAPM_POST_PMU:
652 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
653 break;
654 case SND_SOC_DAPM_POST_PMD:
655 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
656 break;
657 }
49d92c7d
SM		 658 return 0;
659}
660
86139a13 661static int vibramux_event(struct snd_soc_dapm_widget *w,
7ded5fe0 662 struct snd_kcontrol *kcontrol, int event)
86139a13
JV		 663{
664 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
665 return 0;
666}
667
7729cf74 668static int apll_event(struct snd_soc_dapm_widget *w,
7ded5fe0 669 struct snd_kcontrol *kcontrol, int event)
7729cf74
PU		 670{
671 switch (event) {
672 case SND_SOC_DAPM_PRE_PMU:
673 twl4030_apll_enable(w->codec, 1);
674 break;
675 case SND_SOC_DAPM_POST_PMD:
676 twl4030_apll_enable(w->codec, 0);
677 break;
678 }
679 return 0;
680}
681
7b4c734e 682static int aif_event(struct snd_soc_dapm_widget *w,
7ded5fe0 683 struct snd_kcontrol *kcontrol, int event)
7b4c734e
PU		 684{
685 u8 audio_if;
686
efc8acff 687 audio_if = twl4030_read(w->codec, TWL4030_REG_AUDIO_IF);
7b4c734e
PU		 688 switch (event) {
689 case SND_SOC_DAPM_PRE_PMU:
690 /* Enable AIF */
691 /* enable the PLL before we use it to clock the DAI */
692 twl4030_apll_enable(w->codec, 1);
693
694 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
7ded5fe0 695 audio_if | TWL4030_AIF_EN);
7b4c734e
PU		 696 break;
697 case SND_SOC_DAPM_POST_PMD:
698 /* disable the DAI before we stop it's source PLL */
699 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
7ded5fe0 700 audio_if & ~TWL4030_AIF_EN);
7b4c734e
PU		 701 twl4030_apll_enable(w->codec, 0);
702 break;
703 }
704 return 0;
705}
706
6943c92e 707static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 708{
709 unsigned char hs_gain, hs_pop;
b2c812e2 710 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 711 struct twl4030_codec_data *pdata = twl4030->pdata;
6943c92e
PU		 712 /* Base values for ramp delay calculation: 2^19 - 2^26 */
713 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
714 8388608, 16777216, 33554432, 67108864};
7e6120c5 715 unsigned int delay;
aad749e5 716
efc8acff
PU		 717 hs_gain = twl4030_read(codec, TWL4030_REG_HS_GAIN_SET);
718 hs_pop = twl4030_read(codec, TWL4030_REG_HS_POPN_SET);
7e6120c5
PU		 719 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
720 twl4030->sysclk) + 1;
aad749e5 721
4e49ffd1
CVJ		 722 /* Enable external mute control, this dramatically reduces
723 * the pop-noise */
f0fba2ad 724 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 725 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
726 gpio_set_value(pdata->hs_extmute_gpio, 1);
4e49ffd1
CVJ		 727 } else {
728 hs_pop |= TWL4030_EXTMUTE;
729 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
730 }
731 }
732
6943c92e
PU		 733 if (ramp) {
734 /* Headset ramp-up according to the TRM */
aad749e5 735 hs_pop |= TWL4030_VMID_EN;
6943c92e 736 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2 737 /* Actually write to the register */
7ded5fe0
PU		 738 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain,
739 TWL4030_REG_HS_GAIN_SET);
aad749e5 740 hs_pop |= TWL4030_RAMP_EN;
6943c92e 741 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1 742 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 743 twl4030_wait_ms(delay);
6943c92e
PU		 744 } else {
745 /* Headset ramp-down _not_ according to
746 * the TRM, but in a way that it is working */
aad749e5 747 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 748 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
749 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 750 twl4030_wait_ms(delay);
aad749e5 751 /* Bypass the reg_cache to mute the headset */
7ded5fe0
PU		 752 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f),
753 TWL4030_REG_HS_GAIN_SET);
6943c92e 754
aad749e5 755 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 756 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
757 }
4e49ffd1
CVJ		 758
759 /* Disable external mute */
f0fba2ad 760 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 761 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
762 gpio_set_value(pdata->hs_extmute_gpio, 0);
4e49ffd1
CVJ		 763 } else {
764 hs_pop &= ~TWL4030_EXTMUTE;
765 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
766 }
767 }
6943c92e
PU		 768}
769
770static int headsetlpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 771 struct snd_kcontrol *kcontrol, int event)
6943c92e 772{
b2c812e2 773 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 774
775 switch (event) {
776 case SND_SOC_DAPM_POST_PMU:
777 /* Do the ramp-up only once */
778 if (!twl4030->hsr_enabled)
779 headset_ramp(w->codec, 1);
780
781 twl4030->hsl_enabled = 1;
782 break;
783 case SND_SOC_DAPM_POST_PMD:
784 /* Do the ramp-down only if both headsetL/R is disabled */
785 if (!twl4030->hsr_enabled)
786 headset_ramp(w->codec, 0);
787
788 twl4030->hsl_enabled = 0;
789 break;
790 }
791 return 0;
792}
793
794static int headsetrpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 795 struct snd_kcontrol *kcontrol, int event)
6943c92e 796{
b2c812e2 797 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 798
799 switch (event) {
800 case SND_SOC_DAPM_POST_PMU:
801 /* Do the ramp-up only once */
802 if (!twl4030->hsl_enabled)
803 headset_ramp(w->codec, 1);
804
805 twl4030->hsr_enabled = 1;
806 break;
807 case SND_SOC_DAPM_POST_PMD:
808 /* Do the ramp-down only if both headsetL/R is disabled */
809 if (!twl4030->hsl_enabled)
810 headset_ramp(w->codec, 0);
811
812 twl4030->hsr_enabled = 0;
aad749e5
PU		 813 break;
814 }
815 return 0;
816}
817
01ea6ba2 818static int digimic_event(struct snd_soc_dapm_widget *w,
7ded5fe0 819 struct snd_kcontrol *kcontrol, int event)
01ea6ba2
PU		 820{
821 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
182f73f6 822 struct twl4030_codec_data *pdata = twl4030->pdata;
01ea6ba2 823
182f73f6
PU		 824 if (pdata && pdata->digimic_delay)
825 twl4030_wait_ms(pdata->digimic_delay);
01ea6ba2
PU		 826 return 0;
827}
828
b0bd53a7
PU		 829/*
830 * Some of the gain controls in TWL (mostly those which are associated with
831 * the outputs) are implemented in an interesting way:
832 * 0x0 : Power down (mute)
833 * 0x1 : 6dB
834 * 0x2 : 0 dB
835 * 0x3 : -6 dB
836 * Inverting not going to help with these.
837 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
838 */
b0bd53a7 839static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 840 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 841{
842 struct soc_mixer_control *mc =
843 (struct soc_mixer_control *)kcontrol->private_value;
844 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
845 unsigned int reg = mc->reg;
846 unsigned int shift = mc->shift;
847 unsigned int rshift = mc->rshift;
848 int max = mc->max;
849 int mask = (1 << fls(max)) - 1;
850
851 ucontrol->value.integer.value[0] =
852 (snd_soc_read(codec, reg) >> shift) & mask;
853 if (ucontrol->value.integer.value[0])
854 ucontrol->value.integer.value[0] =
855 max + 1 - ucontrol->value.integer.value[0];
856
857 if (shift != rshift) {
858 ucontrol->value.integer.value[1] =
859 (snd_soc_read(codec, reg) >> rshift) & mask;
860 if (ucontrol->value.integer.value[1])
861 ucontrol->value.integer.value[1] =
862 max + 1 - ucontrol->value.integer.value[1];
863 }
864
865 return 0;
866}
867
868static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 869 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 870{
871 struct soc_mixer_control *mc =
872 (struct soc_mixer_control *)kcontrol->private_value;
873 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
874 unsigned int reg = mc->reg;
875 unsigned int shift = mc->shift;
876 unsigned int rshift = mc->rshift;
877 int max = mc->max;
878 int mask = (1 << fls(max)) - 1;
879 unsigned short val, val2, val_mask;
880
881 val = (ucontrol->value.integer.value[0] & mask);
882
883 val_mask = mask << shift;
884 if (val)
885 val = max + 1 - val;
886 val = val << shift;
887 if (shift != rshift) {
888 val2 = (ucontrol->value.integer.value[1] & mask);
889 val_mask |= mask << rshift;
890 if (val2)
891 val2 = max + 1 - val2;
892 val |= val2 << rshift;
893 }
894 return snd_soc_update_bits(codec, reg, val_mask, val);
895}
896
897static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 898 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 899{
900 struct soc_mixer_control *mc =
901 (struct soc_mixer_control *)kcontrol->private_value;
902 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
903 unsigned int reg = mc->reg;
904 unsigned int reg2 = mc->rreg;
905 unsigned int shift = mc->shift;
906 int max = mc->max;
907 int mask = (1<<fls(max))-1;
908
909 ucontrol->value.integer.value[0] =
910 (snd_soc_read(codec, reg) >> shift) & mask;
911 ucontrol->value.integer.value[1] =
912 (snd_soc_read(codec, reg2) >> shift) & mask;
913
914 if (ucontrol->value.integer.value[0])
915 ucontrol->value.integer.value[0] =
916 max + 1 - ucontrol->value.integer.value[0];
917 if (ucontrol->value.integer.value[1])
918 ucontrol->value.integer.value[1] =
919 max + 1 - ucontrol->value.integer.value[1];
920
921 return 0;
922}
923
924static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 925 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 926{
927 struct soc_mixer_control *mc =
928 (struct soc_mixer_control *)kcontrol->private_value;
929 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
930 unsigned int reg = mc->reg;
931 unsigned int reg2 = mc->rreg;
932 unsigned int shift = mc->shift;
933 int max = mc->max;
934 int mask = (1 << fls(max)) - 1;
935 int err;
936 unsigned short val, val2, val_mask;
937
938 val_mask = mask << shift;
939 val = (ucontrol->value.integer.value[0] & mask);
940 val2 = (ucontrol->value.integer.value[1] & mask);
941
942 if (val)
943 val = max + 1 - val;
944 if (val2)
945 val2 = max + 1 - val2;
946
947 val = val << shift;
948 val2 = val2 << shift;
949
950 err = snd_soc_update_bits(codec, reg, val_mask, val);
951 if (err < 0)
952 return err;
953
954 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
955 return err;
956}
957
b74bd40f
LCM		 958/* Codec operation modes */
959static const char *twl4030_op_modes_texts[] = {
960 "Option 2 (voice/audio)", "Option 1 (audio)"
961};
962
963static const struct soc_enum twl4030_op_modes_enum =
964 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
965 ARRAY_SIZE(twl4030_op_modes_texts),
966 twl4030_op_modes_texts);
967
423c238d 968static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 969 struct snd_ctl_elem_value *ucontrol)
970{
971 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 972 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 973 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
974 unsigned short val;
86767b7d 975 unsigned short mask;
b74bd40f
LCM		 976
977 if (twl4030->configured) {
3b8a0795
PU		 978 dev_err(codec->dev,
979 "operation mode cannot be changed on-the-fly\n");
b74bd40f
LCM		 980 return -EBUSY;
981 }
982
b74bd40f
LCM		 983 if (ucontrol->value.enumerated.item[0] > e->max - 1)
984 return -EINVAL;
985
986 val = ucontrol->value.enumerated.item[0] << e->shift_l;
86767b7d 987 mask = e->mask << e->shift_l;
b74bd40f
LCM		 988 if (e->shift_l != e->shift_r) {
989 if (ucontrol->value.enumerated.item[1] > e->max - 1)
990 return -EINVAL;
991 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
86767b7d 992 mask |= e->mask << e->shift_r;
b74bd40f
LCM		 993 }
994
995 return snd_soc_update_bits(codec, e->reg, mask, val);
996}
997
c10b82cf
PU		 998/*
999 * FGAIN volume control:
1000 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1001 */
d889a72c 1002static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1003
0d33ea0b
PU		 1004/*
1005 * CGAIN volume control:
1006 * 0 dB to 12 dB in 6 dB steps
1007 * value 2 and 3 means 12 dB
1008 */
d889a72c
PU		 1009static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1010
1a787e7a
JS		 1011/*
1012 * Voice Downlink GAIN volume control:
1013 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1014 */
1015static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1016
d889a72c
PU		 1017/*
1018 * Analog playback gain
1019 * -24 dB to 12 dB in 2 dB steps
1020 */
1021static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1022
4290239c
PU		 1023/*
1024 * Gain controls tied to outputs
1025 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1026 */
1027static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1028
18cc8d8d
JS		 1029/*
1030 * Gain control for earpiece amplifier
1031 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1032 */
1033static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1034
381a22b5
PU		 1035/*
1036 * Capture gain after the ADCs
1037 * from 0 dB to 31 dB in 1 dB steps
1038 */
1039static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1040
5920b453
GI		 1041/*
1042 * Gain control for input amplifiers
1043 * 0 dB to 30 dB in 6 dB steps
1044 */
1045static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1046
328d0a13
LCM		 1047/* AVADC clock priority */
1048static const char *twl4030_avadc_clk_priority_texts[] = {
1049 "Voice high priority", "HiFi high priority"
1050};
1051
1052static const struct soc_enum twl4030_avadc_clk_priority_enum =
1053 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1054 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1055 twl4030_avadc_clk_priority_texts);
1056
89492be8
PU		 1057static const char *twl4030_rampdelay_texts[] = {
1058 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1059 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1060 "3495/2581/1748 ms"
1061};
1062
1063static const struct soc_enum twl4030_rampdelay_enum =
1064 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1065 ARRAY_SIZE(twl4030_rampdelay_texts),
1066 twl4030_rampdelay_texts);
1067
376f7839
PU		 1068/* Vibra H-bridge direction mode */
1069static const char *twl4030_vibradirmode_texts[] = {
1070 "Vibra H-bridge direction", "Audio data MSB",
1071};
1072
1073static const struct soc_enum twl4030_vibradirmode_enum =
1074 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1075 ARRAY_SIZE(twl4030_vibradirmode_texts),
1076 twl4030_vibradirmode_texts);
1077
1078/* Vibra H-bridge direction */
1079static const char *twl4030_vibradir_texts[] = {
1080 "Positive polarity", "Negative polarity",
1081};
1082
1083static const struct soc_enum twl4030_vibradir_enum =
1084 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1085 ARRAY_SIZE(twl4030_vibradir_texts),
1086 twl4030_vibradir_texts);
1087
36aeff61
PU		 1088/* Digimic Left and right swapping */
1089static const char *twl4030_digimicswap_texts[] = {
1090 "Not swapped", "Swapped",
1091};
1092
1093static const struct soc_enum twl4030_digimicswap_enum =
1094 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1095 ARRAY_SIZE(twl4030_digimicswap_texts),
1096 twl4030_digimicswap_texts);
1097
cc17557e 1098static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1099 /* Codec operation mode control */
1100 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1101 snd_soc_get_enum_double,
1102 snd_soc_put_twl4030_opmode_enum_double),
1103
d889a72c
PU		 1104 /* Common playback gain controls */
1105 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1106 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1107 0, 0x3f, 0, digital_fine_tlv),
1108 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1109 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1110 0, 0x3f, 0, digital_fine_tlv),
1111
1112 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1113 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1114 6, 0x2, 0, digital_coarse_tlv),
1115 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1116 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1117 6, 0x2, 0, digital_coarse_tlv),
1118
1119 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1120 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1121 3, 0x12, 1, analog_tlv),
1122 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1123 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1124 3, 0x12, 1, analog_tlv),
44c55870
PU		 1125 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1126 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1127 1, 1, 0),
1128 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1129 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1130 1, 1, 0),
381a22b5 1131
1a787e7a
JS		 1132 /* Common voice downlink gain controls */
1133 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1134 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1135
1136 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1137 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1138
1139 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1140 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1141
4290239c 1142 /* Separate output gain controls */
0f9887d1 1143 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
4290239c 1144 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
0f9887d1
PU		 1145 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1146 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1147
0f9887d1
PU		 1148 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1149 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1150 snd_soc_put_volsw_twl4030, output_tvl),
4290239c 1151
0f9887d1 1152 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
4290239c 1153 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
0f9887d1
PU		 1154 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1155 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1156
0f9887d1
PU		 1157 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1158 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1159 snd_soc_put_volsw_twl4030, output_ear_tvl),
4290239c 1160
381a22b5 1161 /* Common capture gain controls */
276c6222 1162 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1163 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1164 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1165 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1166 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1167 0, 0x1f, 0, digital_capture_tlv),
5920b453 1168
276c6222 1169 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1170 0, 3, 5, 0, input_gain_tlv),
89492be8 1171
328d0a13
LCM		 1172 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1173
89492be8 1174 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1175
1176 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1177 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1178
1179 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1180};
1181
cc17557e 1182static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1183 /* Left channel inputs */
1184 SND_SOC_DAPM_INPUT("MAINMIC"),
1185 SND_SOC_DAPM_INPUT("HSMIC"),
1186 SND_SOC_DAPM_INPUT("AUXL"),
1187 SND_SOC_DAPM_INPUT("CARKITMIC"),
1188 /* Right channel inputs */
1189 SND_SOC_DAPM_INPUT("SUBMIC"),
1190 SND_SOC_DAPM_INPUT("AUXR"),
1191 /* Digital microphones (Stereo) */
1192 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1193 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1194
1195 /* Outputs */
5e98a464 1196 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1197 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1198 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1199 SND_SOC_DAPM_OUTPUT("HSOL"),
1200 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1201 SND_SOC_DAPM_OUTPUT("CARKITL"),
1202 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1203 SND_SOC_DAPM_OUTPUT("HFL"),
1204 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1205 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1206
7b4c734e
PU		 1207 /* AIF and APLL clocks for running DAIs (including loopback) */
1208 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1209 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1210 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1211
53b5047d 1212 /* DACs */
7f51e7d3
PU		 1213 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1214 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1215 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1216 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1217 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
cc17557e 1218
927a7747
PU		 1219 SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1220 TWL4030_REG_VOICE_IF, 6, 0),
1221
7393958f 1222 /* Analog bypasses */
78e08e2f
PU		 1223 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1224 &twl4030_dapm_abypassr1_control),
1225 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1226 &twl4030_dapm_abypassl1_control),
1227 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1228 &twl4030_dapm_abypassr2_control),
1229 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1230 &twl4030_dapm_abypassl2_control),
1231 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1232 &twl4030_dapm_abypassv_control),
1233
1234 /* Master analog loopback switch */
1235 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1236 NULL, 0),
7393958f 1237
6bab83fd 1238 /* Digital bypasses */
78e08e2f
PU		 1239 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1240 &twl4030_dapm_dbypassl_control),
1241 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1242 &twl4030_dapm_dbypassr_control),
1243 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1244 &twl4030_dapm_dbypassv_control),
6bab83fd 1245
4005d39a
PU		 1246 /* Digital mixers, power control for the physical DACs */
1247 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1248 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1249 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1250 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1251 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1252 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1253 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1254 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1255 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1256 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1257
1258 /* Analog mixers, power control for the physical PGAs */
1259 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1260 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1261 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1262 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1263 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1264 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1265 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1266 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1267 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1268 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1269
7729cf74
PU		 1270 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1271 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1272
7b4c734e
PU		 1273 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1274 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1275
1a787e7a 1276 /* Output MIXER controls */
5e98a464 1277 /* Earpiece */
1a787e7a
JS		 1278 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1279 &twl4030_dapm_earpiece_controls[0],
1280 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1281 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1282 0, 0, NULL, 0, earpiecepga_event,
1283 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1284 /* PreDrivL/R */
1a787e7a
JS		 1285 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1286 &twl4030_dapm_predrivel_controls[0],
1287 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1288 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1289 0, 0, NULL, 0, predrivelpga_event,
1290 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1291 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1292 &twl4030_dapm_predriver_controls[0],
1293 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1294 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1295 0, 0, NULL, 0, predriverpga_event,
1296 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1297 /* HeadsetL/R */
6943c92e 1298 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1299 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1300 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1301 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1302 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1303 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1304 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1305 &twl4030_dapm_hsor_controls[0],
1306 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1307 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1308 0, 0, NULL, 0, headsetrpga_event,
1309 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1310 /* CarkitL/R */
1a787e7a
JS		 1311 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1312 &twl4030_dapm_carkitl_controls[0],
1313 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1314 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1315 0, 0, NULL, 0, carkitlpga_event,
1316 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1317 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1318 &twl4030_dapm_carkitr_controls[0],
1319 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1320 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1321 0, 0, NULL, 0, carkitrpga_event,
1322 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1323
1324 /* Output MUX controls */
df339804 1325 /* HandsfreeL/R */
5a2e9a48
PU		 1326 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1327 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1328 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1329 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1330 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1331 0, 0, NULL, 0, handsfreelpga_event,
1332 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1333 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1334 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1335 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1336 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1337 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1338 0, 0, NULL, 0, handsfreerpga_event,
1339 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1340 /* Vibra */
86139a13
JV		 1341 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1342 &twl4030_dapm_vibra_control, vibramux_event,
1343 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1344 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1345 &twl4030_dapm_vibrapath_control),
5e98a464 1346
276c6222
PU		 1347 /* Introducing four virtual ADC, since TWL4030 have four channel for
1348 capture */
7f51e7d3
PU		 1349 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1350 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1351 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1352 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
276c6222 1353
927a7747
PU		 1354 SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1355 TWL4030_REG_VOICE_IF, 5, 0),
1356
276c6222
PU		 1357 /* Analog/Digital mic path selection.
1358 TX1 Left/Right: either analog Left/Right or Digimic0
1359 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1360 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1361 &twl4030_dapm_micpathtx1_control),
1362 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1363 &twl4030_dapm_micpathtx2_control),
276c6222 1364
97b8096d 1365 /* Analog input mixers for the capture amplifiers */
9028935d 1366 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1367 TWL4030_REG_ANAMICL, 4, 0,
1368 &twl4030_dapm_analoglmic_controls[0],
1369 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1370 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1371 TWL4030_REG_ANAMICR, 4, 0,
1372 &twl4030_dapm_analogrmic_controls[0],
1373 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1374
fb2a2f84
PU		 1375 SND_SOC_DAPM_PGA("ADC Physical Left",
1376 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1377 SND_SOC_DAPM_PGA("ADC Physical Right",
1378 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1379
01ea6ba2
PU		 1380 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1381 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1382 digimic_event, SND_SOC_DAPM_POST_PMU),
1383 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1384 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1385 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1386
bda7d2a8
PU		 1387 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1388 NULL, 0),
1389 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1390 NULL, 0),
1391
e04d6e55
PU		 1392 /* Microphone bias */
1393 SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1394 TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1395 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1396 TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1397 SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1398 TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
7393958f 1399
927a7747 1400 SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
cc17557e
SS		 1401};
1402
1403static const struct snd_soc_dapm_route intercon[] = {
7f51e7d3
PU		 1404 /* Stream -> DAC mapping */
1405 {"DAC Right1", NULL, "HiFi Playback"},
1406 {"DAC Left1", NULL, "HiFi Playback"},
1407 {"DAC Right2", NULL, "HiFi Playback"},
1408 {"DAC Left2", NULL, "HiFi Playback"},
927a7747 1409 {"DAC Voice", NULL, "VAIFIN"},
7f51e7d3
PU		 1410
1411 /* ADC -> Stream mapping */
1412 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1413 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1414 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1415 {"HiFi Capture", NULL, "ADC Virtual Right2"},
927a7747
PU		 1416 {"VAIFOUT", NULL, "ADC Virtual Left2"},
1417 {"VAIFOUT", NULL, "ADC Virtual Right2"},
1418 {"VAIFOUT", NULL, "VIF Enable"},
7f51e7d3 1419
4005d39a
PU		 1420 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1421 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1422 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1423 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1424 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1425
7729cf74 1426 /* Supply for the digital part (APLL) */
7729cf74
PU		 1427 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1428
27eeb1fe
PU		 1429 {"DAC Left1", NULL, "AIF Enable"},
1430 {"DAC Right1", NULL, "AIF Enable"},
1431 {"DAC Left2", NULL, "AIF Enable"},
1432 {"DAC Right1", NULL, "AIF Enable"},
927a7747 1433 {"DAC Voice", NULL, "VIF Enable"},
27eeb1fe 1434
c42a59ea
PU		 1435 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1436 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1437
4005d39a
PU		 1438 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1439 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1440 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1441 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1442 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1443
5e98a464
PU		 1444 /* Internal playback routings */
1445 /* Earpiece */
4005d39a
PU		 1446 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1447 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1448 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1449 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1450 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1451 /* PreDrivL */
4005d39a
PU		 1452 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1453 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1454 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1455 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1456 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1457 /* PreDrivR */
4005d39a
PU		 1458 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1459 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1460 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1461 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1462 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1463 /* HeadsetL */
4005d39a
PU		 1464 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1465 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1466 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1467 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1468 /* HeadsetR */
4005d39a
PU		 1469 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1470 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1471 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1472 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1473 /* CarkitL */
4005d39a
PU		 1474 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1475 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1476 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1477 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1478 /* CarkitR */
4005d39a
PU		 1479 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1480 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1481 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1482 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1483 /* HandsfreeL */
4005d39a
PU		 1484 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1485 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1486 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1487 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1488 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1489 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1490 /* HandsfreeR */
4005d39a
PU		 1491 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1492 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1493 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1494 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1495 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1496 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1497 /* Vibra */
1498 {"Vibra Mux", "AudioL1", "DAC Left1"},
1499 {"Vibra Mux", "AudioR1", "DAC Right1"},
1500 {"Vibra Mux", "AudioL2", "DAC Left2"},
1501 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1502
cc17557e 1503 /* outputs */
7b4c734e 1504 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1505 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1506 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1507 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1508 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1509 /* Must be always connected (for APLL) */
1510 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1511 /* Physical outputs */
9008adf9
PU		 1512 {"EARPIECE", NULL, "Earpiece PGA"},
1513 {"PREDRIVEL", NULL, "PredriveL PGA"},
1514 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1515 {"HSOL", NULL, "HeadsetL PGA"},
1516 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1517 {"CARKITL", NULL, "CarkitL PGA"},
1518 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1519 {"HFL", NULL, "HandsfreeL PGA"},
1520 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1521 {"Vibra Route", "Audio", "Vibra Mux"},
1522 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1523
276c6222 1524 /* Capture path */
7b4c734e
PU		 1525 /* Must be always connected (for AIF and APLL) */
1526 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1527 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1528 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1529 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1530 /* Physical inputs */
9028935d
PU		 1531 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1532 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1533 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1534 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1535
9028935d
PU		 1536 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1537 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1538
9028935d
PU		 1539 {"ADC Physical Left", NULL, "Analog Left"},
1540 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1541
1542 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1543 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1544
bda7d2a8
PU		 1545 {"DIGIMIC0", NULL, "micbias1 select"},
1546 {"DIGIMIC1", NULL, "micbias2 select"},
1547
276c6222 1548 /* TX1 Left capture path */
fb2a2f84 1549 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1550 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1551 /* TX1 Right capture path */
fb2a2f84 1552 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1553 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1554 /* TX2 Left capture path */
fb2a2f84 1555 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1556 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1557 /* TX2 Right capture path */
fb2a2f84 1558 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1559 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1560
1561 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1562 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1563 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1564 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1565
c42a59ea
PU		 1566 {"ADC Virtual Left1", NULL, "AIF Enable"},
1567 {"ADC Virtual Right1", NULL, "AIF Enable"},
1568 {"ADC Virtual Left2", NULL, "AIF Enable"},
1569 {"ADC Virtual Right2", NULL, "AIF Enable"},
1570
7393958f 1571 /* Analog bypass routes */
9028935d
PU		 1572 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1573 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1574 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1575 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1576 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1577
78e08e2f
PU		 1578 /* Supply for the Analog loopbacks */
1579 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1580 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1581 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1582 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1583 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1584
7393958f
PU		 1585 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1586 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1587 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1588 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1589 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1590
6bab83fd
PU		 1591 /* Digital bypass routes */
1592 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1593 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1594 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1595
4005d39a
PU		 1596 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1597 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1598 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1599
cc17557e
SS		 1600};
1601
cc17557e
SS		 1602static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1603 enum snd_soc_bias_level level)
1604{
1605 switch (level) {
1606 case SND_SOC_BIAS_ON:
cc17557e
SS		 1607 break;
1608 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1609 break;
1610 case SND_SOC_BIAS_STANDBY:
ce6120cc 1611 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1612 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1613 break;
1614 case SND_SOC_BIAS_OFF:
cbd2db12 1615 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1616 break;
1617 }
ce6120cc 1618 codec->dapm.bias_level = level;
cc17557e
SS		 1619
1620 return 0;
1621}
1622
6b87a91f
PU		 1623static void twl4030_constraints(struct twl4030_priv *twl4030,
1624 struct snd_pcm_substream *mst_substream)
1625{
1626 struct snd_pcm_substream *slv_substream;
1627
1628 /* Pick the stream, which need to be constrained */
1629 if (mst_substream == twl4030->master_substream)
1630 slv_substream = twl4030->slave_substream;
1631 else if (mst_substream == twl4030->slave_substream)
1632 slv_substream = twl4030->master_substream;
1633 else /* This should not happen.. */
1634 return;
1635
1636 /* Set the constraints according to the already configured stream */
1637 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1638 SNDRV_PCM_HW_PARAM_RATE,
1639 twl4030->rate,
1640 twl4030->rate);
1641
1642 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1643 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1644 twl4030->sample_bits,
1645 twl4030->sample_bits);
1646
1647 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1648 SNDRV_PCM_HW_PARAM_CHANNELS,
1649 twl4030->channels,
1650 twl4030->channels);
1651}
1652
8a1f936a
PU		 1653/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1654 * capture has to be enabled/disabled. */
1655static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
7ded5fe0 1656 int enable)
8a1f936a
PU		 1657{
1658 u8 reg, mask;
1659
efc8acff 1660 reg = twl4030_read(codec, TWL4030_REG_OPTION);
8a1f936a
PU		 1661
1662 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1663 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1664 else
1665 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1666
1667 if (enable)
1668 reg |= mask;
1669 else
1670 reg &= ~mask;
1671
1672 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1673}
1674
d6648da1
PU		 1675static int twl4030_startup(struct snd_pcm_substream *substream,
1676 struct snd_soc_dai *dai)
7220b9f4 1677{
e6968a17 1678 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1679 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1680
7220b9f4 1681 if (twl4030->master_substream) {
7220b9f4 1682 twl4030->slave_substream = substream;
6b87a91f
PU		 1683 /* The DAI has one configuration for playback and capture, so
1684 * if the DAI has been already configured then constrain this
1685 * substream to match it. */
1686 if (twl4030->configured)
1687 twl4030_constraints(twl4030, twl4030->master_substream);
1688 } else {
efc8acff 1689 if (!(twl4030_read(codec, TWL4030_REG_CODEC_MODE) &
8a1f936a
PU		 1690 TWL4030_OPTION_1)) {
1691 /* In option2 4 channel is not supported, set the
1692 * constraint for the first stream for channels, the
1693 * second stream will 'inherit' this cosntraint */
1694 snd_pcm_hw_constraint_minmax(substream->runtime,
7ded5fe0
PU		 1695 SNDRV_PCM_HW_PARAM_CHANNELS,
1696 2, 2);
8a1f936a 1697 }
7220b9f4 1698 twl4030->master_substream = substream;
6b87a91f 1699 }
7220b9f4
PU		 1700
1701 return 0;
1702}
1703
d6648da1
PU		 1704static void twl4030_shutdown(struct snd_pcm_substream *substream,
1705 struct snd_soc_dai *dai)
7220b9f4 1706{
e6968a17 1707 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1708 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1709
1710 if (twl4030->master_substream == substream)
1711 twl4030->master_substream = twl4030->slave_substream;
1712
1713 twl4030->slave_substream = NULL;
6b87a91f
PU		 1714
1715 /* If all streams are closed, or the remaining stream has not yet
1716 * been configured than set the DAI as not configured. */
1717 if (!twl4030->master_substream)
1718 twl4030->configured = 0;
1719 else if (!twl4030->master_substream->runtime->channels)
1720 twl4030->configured = 0;
8a1f936a
PU		 1721
1722 /* If the closing substream had 4 channel, do the necessary cleanup */
1723 if (substream->runtime->channels == 4)
1724 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1725}
1726
cc17557e 1727static int twl4030_hw_params(struct snd_pcm_substream *substream,
7ded5fe0
PU		 1728 struct snd_pcm_hw_params *params,
1729 struct snd_soc_dai *dai)
cc17557e 1730{
e6968a17 1731 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1732 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1733 u8 mode, old_mode, format, old_format;
1734
8a1f936a
PU		 1735 /* If the substream has 4 channel, do the necessary setup */
1736 if (params_channels(params) == 4) {
efc8acff
PU		 1737 format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
1738 mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE);
eaf1ac8b
PU		 1739
1740 /* Safety check: are we in the correct operating mode and
1741 * the interface is in TDM mode? */
1742 if ((mode & TWL4030_OPTION_1) &&
1743 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1744 twl4030_tdm_enable(codec, substream->stream, 1);
1745 else
1746 return -EINVAL;
1747 }
1748
6b87a91f
PU		 1749 if (twl4030->configured)
1750 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1751 return 0;
1752
cc17557e 1753 /* bit rate */
efc8acff
PU		 1754 old_mode = twl4030_read(codec,
1755 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
cc17557e
SS		 1756 mode = old_mode & ~TWL4030_APLL_RATE;
1757
1758 switch (params_rate(params)) {
1759 case 8000:
1760 mode |= TWL4030_APLL_RATE_8000;
1761 break;
1762 case 11025:
1763 mode |= TWL4030_APLL_RATE_11025;
1764 break;
1765 case 12000:
1766 mode |= TWL4030_APLL_RATE_12000;
1767 break;
1768 case 16000:
1769 mode |= TWL4030_APLL_RATE_16000;
1770 break;
1771 case 22050:
1772 mode |= TWL4030_APLL_RATE_22050;
1773 break;
1774 case 24000:
1775 mode |= TWL4030_APLL_RATE_24000;
1776 break;
1777 case 32000:
1778 mode |= TWL4030_APLL_RATE_32000;
1779 break;
1780 case 44100:
1781 mode |= TWL4030_APLL_RATE_44100;
1782 break;
1783 case 48000:
1784 mode |= TWL4030_APLL_RATE_48000;
1785 break;
103f211d
PU		 1786 case 96000:
1787 mode |= TWL4030_APLL_RATE_96000;
1788 break;
cc17557e 1789 default:
3b8a0795 1790 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
cc17557e
SS		 1791 params_rate(params));
1792 return -EINVAL;
1793 }
1794
cc17557e 1795 /* sample size */
efc8acff 1796 old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
cc17557e
SS		 1797 format = old_format;
1798 format &= ~TWL4030_DATA_WIDTH;
1799 switch (params_format(params)) {
1800 case SNDRV_PCM_FORMAT_S16_LE:
1801 format |= TWL4030_DATA_WIDTH_16S_16W;
1802 break;
dcdeda4a 1803 case SNDRV_PCM_FORMAT_S32_LE:
cc17557e
SS		 1804 format |= TWL4030_DATA_WIDTH_32S_24W;
1805 break;
1806 default:
3b8a0795 1807 dev_err(codec->dev, "%s: unknown format %d\n", __func__,
cc17557e
SS		 1808 params_format(params));
1809 return -EINVAL;
1810 }
1811
2046f175
PU		 1812 if (format != old_format || mode != old_mode) {
1813 if (twl4030->codec_powered) {
1814 /*
1815 * If the codec is powered, than we need to toggle the
1816 * codec power.
1817 */
1818 twl4030_codec_enable(codec, 0);
1819 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1820 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1821 twl4030_codec_enable(codec, 1);
1822 } else {
1823 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1824 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1825 }
cc17557e 1826 }
6b87a91f
PU		 1827
1828 /* Store the important parameters for the DAI configuration and set
1829 * the DAI as configured */
1830 twl4030->configured = 1;
1831 twl4030->rate = params_rate(params);
1832 twl4030->sample_bits = hw_param_interval(params,
1833 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1834 twl4030->channels = params_channels(params);
1835
1836 /* If both playback and capture streams are open, and one of them
1837 * is setting the hw parameters right now (since we are here), set
1838 * constraints to the other stream to match the current one. */
1839 if (twl4030->slave_substream)
1840 twl4030_constraints(twl4030, substream);
1841
cc17557e
SS		 1842 return 0;
1843}
1844
7ded5fe0
PU		 1845static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
1846 unsigned int freq, int dir)
cc17557e
SS		 1847{
1848 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1849 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1850
1851 switch (freq) {
1852 case 19200000:
cc17557e 1853 case 26000000:
cc17557e 1854 case 38400000:
cc17557e
SS		 1855 break;
1856 default:
3b8a0795 1857 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
cc17557e
SS		 1858 return -EINVAL;
1859 }
1860
68d01955
PU		 1861 if ((freq / 1000) != twl4030->sysclk) {
1862 dev_err(codec->dev,
3b8a0795 1863 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955
PU		 1864 freq, twl4030->sysclk * 1000);
1865 return -EINVAL;
1866 }
cc17557e
SS		 1867
1868 return 0;
1869}
1870
7ded5fe0 1871static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
cc17557e
SS		 1872{
1873 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1874 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1875 u8 old_format, format;
1876
1877 /* get format */
efc8acff 1878 old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
cc17557e
SS		 1879 format = old_format;
1880
1881 /* set master/slave audio interface */
1882 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1883 case SND_SOC_DAIFMT_CBM_CFM:
1884 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1885 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1886 break;
1887 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1888 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1889 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1890 break;
1891 default:
1892 return -EINVAL;
1893 }
1894
1895 /* interface format */
1896 format &= ~TWL4030_AIF_FORMAT;
1897 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1898 case SND_SOC_DAIFMT_I2S:
1899 format |= TWL4030_AIF_FORMAT_CODEC;
1900 break;
8a1f936a
PU		 1901 case SND_SOC_DAIFMT_DSP_A:
1902 format |= TWL4030_AIF_FORMAT_TDM;
1903 break;
cc17557e
SS		 1904 default:
1905 return -EINVAL;
1906 }
1907
1908 if (format != old_format) {
2046f175
PU		 1909 if (twl4030->codec_powered) {
1910 /*
1911 * If the codec is powered, than we need to toggle the
1912 * codec power.
1913 */
1914 twl4030_codec_enable(codec, 0);
1915 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1916 twl4030_codec_enable(codec, 1);
1917 } else {
1918 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1919 }
cc17557e
SS		 1920 }
1921
1922 return 0;
1923}
1924
68140443
LCM		 1925static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1926{
1927 struct snd_soc_codec *codec = dai->codec;
efc8acff 1928 u8 reg = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
68140443
LCM		 1929
1930 if (tristate)
1931 reg |= TWL4030_AIF_TRI_EN;
1932 else
1933 reg &= ~TWL4030_AIF_TRI_EN;
1934
1935 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1936}
1937
b7a755a8
MLC		 1938/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1939 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1940static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
7ded5fe0 1941 int enable)
b7a755a8
MLC		 1942{
1943 u8 reg, mask;
1944
efc8acff 1945 reg = twl4030_read(codec, TWL4030_REG_OPTION);
b7a755a8
MLC		 1946
1947 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1948 mask = TWL4030_ARXL1_VRX_EN;
1949 else
1950 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1951
1952 if (enable)
1953 reg |= mask;
1954 else
1955 reg &= ~mask;
1956
1957 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1958}
1959
7154b3e8 1960static int twl4030_voice_startup(struct snd_pcm_substream *substream,
7ded5fe0 1961 struct snd_soc_dai *dai)
7154b3e8 1962{
e6968a17 1963 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1964 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1965 u8 mode;
1966
1967 /* If the system master clock is not 26MHz, the voice PCM interface is
25985edc 1968 * not available.
7154b3e8 1969 */
68d01955 1970 if (twl4030->sysclk != 26000) {
3b8a0795
PU		 1971 dev_err(codec->dev,
1972 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
1973 __func__, twl4030->sysclk);
7154b3e8
JS		 1974 return -EINVAL;
1975 }
1976
1977 /* If the codec mode is not option2, the voice PCM interface is not
25985edc 1978 * available.
7154b3e8 1979 */
efc8acff 1980 mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE)
7154b3e8
JS		 1981 & TWL4030_OPT_MODE;
1982
1983 if (mode != TWL4030_OPTION_2) {
3b8a0795
PU		 1984 dev_err(codec->dev, "%s: the codec mode is not option2\n",
1985 __func__);
7154b3e8
JS		 1986 return -EINVAL;
1987 }
1988
1989 return 0;
1990}
1991
b7a755a8 1992static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
7ded5fe0 1993 struct snd_soc_dai *dai)
b7a755a8 1994{
e6968a17 1995 struct snd_soc_codec *codec = dai->codec;
b7a755a8
MLC		 1996
1997 /* Enable voice digital filters */
1998 twl4030_voice_enable(codec, substream->stream, 0);
1999}
2000
7154b3e8 2001static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
7ded5fe0
PU		 2002 struct snd_pcm_hw_params *params,
2003 struct snd_soc_dai *dai)
7154b3e8 2004{
e6968a17 2005 struct snd_soc_codec *codec = dai->codec;
2046f175 2006 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2007 u8 old_mode, mode;
2008
b7a755a8
MLC		 2009 /* Enable voice digital filters */
2010 twl4030_voice_enable(codec, substream->stream, 1);
2011
7154b3e8 2012 /* bit rate */
7ded5fe0
PU		 2013 old_mode = twl4030_read(codec,
2014 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
7154b3e8
JS		 2015 mode = old_mode;
2016
2017 switch (params_rate(params)) {
2018 case 8000:
2019 mode &= ~(TWL4030_SEL_16K);
2020 break;
2021 case 16000:
2022 mode |= TWL4030_SEL_16K;
2023 break;
2024 default:
3b8a0795 2025 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
7154b3e8
JS		 2026 params_rate(params));
2027 return -EINVAL;
2028 }
2029
2030 if (mode != old_mode) {
2046f175
PU		 2031 if (twl4030->codec_powered) {
2032 /*
2033 * If the codec is powered, than we need to toggle the
2034 * codec power.
2035 */
2036 twl4030_codec_enable(codec, 0);
2037 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2038 twl4030_codec_enable(codec, 1);
2039 } else {
2040 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2041 }
7154b3e8
JS		 2042 }
2043
2044 return 0;
2045}
2046
2047static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
7ded5fe0 2048 int clk_id, unsigned int freq, int dir)
7154b3e8
JS		 2049{
2050 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2051 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2052
68d01955 2053 if (freq != 26000000) {
3b8a0795
PU		 2054 dev_err(codec->dev,
2055 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2056 __func__, freq / 1000);
68d01955
PU		 2057 return -EINVAL;
2058 }
2059 if ((freq / 1000) != twl4030->sysclk) {
2060 dev_err(codec->dev,
3b8a0795 2061 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955 2062 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2063 return -EINVAL;
2064 }
7154b3e8
JS		 2065 return 0;
2066}
2067
2068static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
7ded5fe0 2069 unsigned int fmt)
7154b3e8
JS		 2070{
2071 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2072 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2073 u8 old_format, format;
2074
2075 /* get format */
efc8acff 2076 old_format = twl4030_read(codec, TWL4030_REG_VOICE_IF);
7154b3e8
JS		 2077 format = old_format;
2078
2079 /* set master/slave audio interface */
2080 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2081 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2082 format &= ~(TWL4030_VIF_SLAVE_EN);
2083 break;
2084 case SND_SOC_DAIFMT_CBS_CFS:
2085 format |= TWL4030_VIF_SLAVE_EN;
2086 break;
2087 default:
2088 return -EINVAL;
2089 }
2090
2091 /* clock inversion */
2092 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2093 case SND_SOC_DAIFMT_IB_NF:
2094 format &= ~(TWL4030_VIF_FORMAT);
2095 break;
2096 case SND_SOC_DAIFMT_NB_IF:
2097 format |= TWL4030_VIF_FORMAT;
2098 break;
2099 default:
2100 return -EINVAL;
2101 }
2102
2103 if (format != old_format) {
2046f175
PU		 2104 if (twl4030->codec_powered) {
2105 /*
2106 * If the codec is powered, than we need to toggle the
2107 * codec power.
2108 */
2109 twl4030_codec_enable(codec, 0);
2110 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2111 twl4030_codec_enable(codec, 1);
2112 } else {
2113 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2114 }
7154b3e8
JS		 2115 }
2116
2117 return 0;
2118}
2119
68140443
LCM		 2120static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2121{
2122 struct snd_soc_codec *codec = dai->codec;
efc8acff 2123 u8 reg = twl4030_read(codec, TWL4030_REG_VOICE_IF);
68140443
LCM		 2124
2125 if (tristate)
2126 reg |= TWL4030_VIF_TRI_EN;
2127 else
2128 reg &= ~TWL4030_VIF_TRI_EN;
2129
2130 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2131}
2132
bbba9444 2133#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
dcdeda4a 2134#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
cc17557e 2135
85e7652d 2136static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2137 .startup = twl4030_startup,
2138 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2139 .hw_params = twl4030_hw_params,
2140 .set_sysclk = twl4030_set_dai_sysclk,
2141 .set_fmt = twl4030_set_dai_fmt,
68140443 2142 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2143};
2144
85e7652d 2145static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
7154b3e8 2146 .startup = twl4030_voice_startup,
b7a755a8 2147 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2148 .hw_params = twl4030_voice_hw_params,
2149 .set_sysclk = twl4030_voice_set_dai_sysclk,
2150 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2151 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2152};
2153
f0fba2ad 2154static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2155{
f0fba2ad 2156 .name = "twl4030-hifi",
cc17557e 2157 .playback = {
b4852b79 2158 .stream_name = "HiFi Playback",
cc17557e 2159 .channels_min = 2,
8a1f936a 2160 .channels_max = 4,
31ad0f31 2161 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
8819f65c
PU		 2162 .formats = TWL4030_FORMATS,
2163 .sig_bits = 24,},
cc17557e 2164 .capture = {
7f51e7d3 2165 .stream_name = "HiFi Capture",
cc17557e 2166 .channels_min = 2,
8a1f936a 2167 .channels_max = 4,
cc17557e 2168 .rates = TWL4030_RATES,
8819f65c
PU		 2169 .formats = TWL4030_FORMATS,
2170 .sig_bits = 24,},
f0fba2ad 2171 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2172},
2173{
f0fba2ad 2174 .name = "twl4030-voice",
7154b3e8 2175 .playback = {
b4852b79 2176 .stream_name = "Voice Playback",
7154b3e8
JS		 2177 .channels_min = 1,
2178 .channels_max = 1,
2179 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2180 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2181 .capture = {
7f51e7d3 2182 .stream_name = "Voice Capture",
7154b3e8
JS		 2183 .channels_min = 1,
2184 .channels_max = 2,
2185 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2186 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2187 .ops = &twl4030_dai_voice_ops,
2188},
cc17557e 2189};
cc17557e 2190
f0fba2ad 2191static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2192{
f0fba2ad 2193 struct twl4030_priv *twl4030;
9da28c7b 2194
f2b1ce49
PU		 2195 twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2196 GFP_KERNEL);
f0fba2ad 2197 if (twl4030 == NULL) {
3b8a0795 2198 dev_err(codec->dev, "Can not allocate memory\n");
f0fba2ad 2199 return -ENOMEM;
cc17557e 2200 }
f0fba2ad
LG		 2201 snd_soc_codec_set_drvdata(codec, twl4030);
2202 /* Set the defaults, and power up the codec */
57fe7251 2203 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
f0fba2ad
LG		 2204
2205 twl4030_init_chip(codec);
cc17557e 2206
7a1fecf5 2207 return 0;
cc17557e
SS		 2208}
2209
f0fba2ad 2210static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2211{
5b3b0fa8 2212 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 2213 struct twl4030_codec_data *pdata = twl4030->pdata;
5b3b0fa8 2214
7a1fecf5 2215 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
281ecd16
PU		 2216
2217 if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2218 gpio_free(pdata->hs_extmute_gpio);
2219
7a1fecf5
PU		 2220 return 0;
2221}
2222
f0fba2ad
LG		 2223static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2224 .probe = twl4030_soc_probe,
2225 .remove = twl4030_soc_remove,
efc8acff 2226 .read = twl4030_read,
f0fba2ad
LG		 2227 .write = twl4030_write,
2228 .set_bias_level = twl4030_set_bias_level,
eb3032f8 2229 .idle_bias_off = true,
f7c93f01
PU		 2230
2231 .controls = twl4030_snd_controls,
2232 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2233 .dapm_widgets = twl4030_dapm_widgets,
2234 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2235 .dapm_routes = intercon,
2236 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 2237};
2238
05c4c6f7 2239static int twl4030_codec_probe(struct platform_device *pdev)
7a1fecf5 2240{
f0fba2ad 2241 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
7ded5fe0 2242 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2243}
2244
05c4c6f7 2245static int twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2246{
f0fba2ad 2247 snd_soc_unregister_codec(&pdev->dev);
cc17557e
SS		 2248 return 0;
2249}
2250
f0fba2ad 2251MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2252
2253static struct platform_driver twl4030_codec_driver = {
2254 .probe = twl4030_codec_probe,
05c4c6f7 2255 .remove = twl4030_codec_remove,
7a1fecf5 2256 .driver = {
f0fba2ad 2257 .name = "twl4030-codec",
7a1fecf5
PU		 2258 .owner = THIS_MODULE,
2259 },
cc17557e 2260};
cc17557e 2261
5bbcc3c0 2262module_platform_driver(twl4030_codec_driver);
64089b84 2263
cc17557e
SS		 2264MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2265MODULE_AUTHOR("Steve Sakoman");
2266MODULE_LICENSE("GPL");
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