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ASoC: Register platform drivers
[mirror_ubuntu-zesty-kernel.git] / sound / soc / codecs / twl4030.c
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cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129}
130
131/*
132 * write twl4030 register cache
133 */
134static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136{
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142}
143
144/*
145 * write to the twl4030 register space
146 */
147static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149{
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152}
153
154static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155{
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165}
166
167static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168{
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178}
179
180static void twl4030_init_chip(struct snd_soc_codec *codec)
181{
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191}
192
5e98a464
PU		 193/* Earpiece */
194static const char *twl4030_earpiece_texts[] =
195 {"Off", "DACL1", "DACL2", "Invalid",
196 "DACR1"};
197
198static const struct soc_enum twl4030_earpiece_enum =
199 SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1,
200 ARRAY_SIZE(twl4030_earpiece_texts),
201 twl4030_earpiece_texts);
202
203static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
204SOC_DAPM_ENUM("Route", twl4030_earpiece_enum);
205
2a6f5c58
PU		 206/* PreDrive Left */
207static const char *twl4030_predrivel_texts[] =
208 {"Off", "DACL1", "DACL2", "Invalid",
209 "DACR2"};
210
211static const struct soc_enum twl4030_predrivel_enum =
212 SOC_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1,
213 ARRAY_SIZE(twl4030_predrivel_texts),
214 twl4030_predrivel_texts);
215
216static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
217SOC_DAPM_ENUM("Route", twl4030_predrivel_enum);
218
219/* PreDrive Right */
220static const char *twl4030_predriver_texts[] =
221 {"Off", "DACR1", "DACR2", "Invalid",
222 "DACL2"};
223
224static const struct soc_enum twl4030_predriver_enum =
225 SOC_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1,
226 ARRAY_SIZE(twl4030_predriver_texts),
227 twl4030_predriver_texts);
228
229static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
230SOC_DAPM_ENUM("Route", twl4030_predriver_enum);
231
dfad21a2
PU		 232/* Headset Left */
233static const char *twl4030_hsol_texts[] =
234 {"Off", "DACL1", "DACL2"};
235
236static const struct soc_enum twl4030_hsol_enum =
237 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
238 ARRAY_SIZE(twl4030_hsol_texts),
239 twl4030_hsol_texts);
240
241static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
242SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
243
244/* Headset Right */
245static const char *twl4030_hsor_texts[] =
246 {"Off", "DACR1", "DACR2"};
247
248static const struct soc_enum twl4030_hsor_enum =
249 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
250 ARRAY_SIZE(twl4030_hsor_texts),
251 twl4030_hsor_texts);
252
253static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
254SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
255
5152d8c2
PU		 256/* Carkit Left */
257static const char *twl4030_carkitl_texts[] =
258 {"Off", "DACL1", "DACL2"};
259
260static const struct soc_enum twl4030_carkitl_enum =
261 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
262 ARRAY_SIZE(twl4030_carkitl_texts),
263 twl4030_carkitl_texts);
264
265static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
266SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
267
268/* Carkit Right */
269static const char *twl4030_carkitr_texts[] =
270 {"Off", "DACR1", "DACR2"};
271
272static const struct soc_enum twl4030_carkitr_enum =
273 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
274 ARRAY_SIZE(twl4030_carkitr_texts),
275 twl4030_carkitr_texts);
276
277static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
278SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
279
df339804
PU		 280/* Handsfree Left */
281static const char *twl4030_handsfreel_texts[] =
282 {"Voice", "DACL1", "DACL2", "DACR2"};
283
284static const struct soc_enum twl4030_handsfreel_enum =
285 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
286 ARRAY_SIZE(twl4030_handsfreel_texts),
287 twl4030_handsfreel_texts);
288
289static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
290SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
291
292/* Handsfree Right */
293static const char *twl4030_handsfreer_texts[] =
294 {"Voice", "DACR1", "DACR2", "DACL2"};
295
296static const struct soc_enum twl4030_handsfreer_enum =
297 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
298 ARRAY_SIZE(twl4030_handsfreer_texts),
299 twl4030_handsfreer_texts);
300
301static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
302SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
303
e8ff9c41
PU		 304static int outmixer_event(struct snd_soc_dapm_widget *w,
305 struct snd_kcontrol *kcontrol, int event)
306{
307 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
308 int ret = 0;
309 int val;
310
311 switch (e->reg) {
312 case TWL4030_REG_PREDL_CTL:
313 case TWL4030_REG_PREDR_CTL:
314 case TWL4030_REG_EAR_CTL:
315 val = w->value >> e->shift_l;
316 if (val == 3) {
317 printk(KERN_WARNING
318 "Invalid MUX setting for register 0x%02x (%d)\n",
319 e->reg, val);
320 ret = -1;
321 }
322 break;
323 }
324
325 return ret;
326}
327
b0bd53a7
PU		 328/*
329 * Some of the gain controls in TWL (mostly those which are associated with
330 * the outputs) are implemented in an interesting way:
331 * 0x0 : Power down (mute)
332 * 0x1 : 6dB
333 * 0x2 : 0 dB
334 * 0x3 : -6 dB
335 * Inverting not going to help with these.
336 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
337 */
338#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
339 xinvert, tlv_array) \
340{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
341 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
342 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
343 .tlv.p = (tlv_array), \
344 .info = snd_soc_info_volsw, \
345 .get = snd_soc_get_volsw_twl4030, \
346 .put = snd_soc_put_volsw_twl4030, \
347 .private_value = (unsigned long)&(struct soc_mixer_control) \
348 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
349 .max = xmax, .invert = xinvert} }
350#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
351 xinvert, tlv_array) \
352{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
353 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
354 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
355 .tlv.p = (tlv_array), \
356 .info = snd_soc_info_volsw_2r, \
357 .get = snd_soc_get_volsw_r2_twl4030,\
358 .put = snd_soc_put_volsw_r2_twl4030, \
359 .private_value = (unsigned long)&(struct soc_mixer_control) \
360 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
361 .max = xmax, .invert = xinvert} }
362#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
363 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
364 xinvert, tlv_array)
365
366static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
367 struct snd_ctl_elem_value *ucontrol)
368{
369 struct soc_mixer_control *mc =
370 (struct soc_mixer_control *)kcontrol->private_value;
371 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
372 unsigned int reg = mc->reg;
373 unsigned int shift = mc->shift;
374 unsigned int rshift = mc->rshift;
375 int max = mc->max;
376 int mask = (1 << fls(max)) - 1;
377
378 ucontrol->value.integer.value[0] =
379 (snd_soc_read(codec, reg) >> shift) & mask;
380 if (ucontrol->value.integer.value[0])
381 ucontrol->value.integer.value[0] =
382 max + 1 - ucontrol->value.integer.value[0];
383
384 if (shift != rshift) {
385 ucontrol->value.integer.value[1] =
386 (snd_soc_read(codec, reg) >> rshift) & mask;
387 if (ucontrol->value.integer.value[1])
388 ucontrol->value.integer.value[1] =
389 max + 1 - ucontrol->value.integer.value[1];
390 }
391
392 return 0;
393}
394
395static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
396 struct snd_ctl_elem_value *ucontrol)
397{
398 struct soc_mixer_control *mc =
399 (struct soc_mixer_control *)kcontrol->private_value;
400 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
401 unsigned int reg = mc->reg;
402 unsigned int shift = mc->shift;
403 unsigned int rshift = mc->rshift;
404 int max = mc->max;
405 int mask = (1 << fls(max)) - 1;
406 unsigned short val, val2, val_mask;
407
408 val = (ucontrol->value.integer.value[0] & mask);
409
410 val_mask = mask << shift;
411 if (val)
412 val = max + 1 - val;
413 val = val << shift;
414 if (shift != rshift) {
415 val2 = (ucontrol->value.integer.value[1] & mask);
416 val_mask |= mask << rshift;
417 if (val2)
418 val2 = max + 1 - val2;
419 val |= val2 << rshift;
420 }
421 return snd_soc_update_bits(codec, reg, val_mask, val);
422}
423
424static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
425 struct snd_ctl_elem_value *ucontrol)
426{
427 struct soc_mixer_control *mc =
428 (struct soc_mixer_control *)kcontrol->private_value;
429 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
430 unsigned int reg = mc->reg;
431 unsigned int reg2 = mc->rreg;
432 unsigned int shift = mc->shift;
433 int max = mc->max;
434 int mask = (1<<fls(max))-1;
435
436 ucontrol->value.integer.value[0] =
437 (snd_soc_read(codec, reg) >> shift) & mask;
438 ucontrol->value.integer.value[1] =
439 (snd_soc_read(codec, reg2) >> shift) & mask;
440
441 if (ucontrol->value.integer.value[0])
442 ucontrol->value.integer.value[0] =
443 max + 1 - ucontrol->value.integer.value[0];
444 if (ucontrol->value.integer.value[1])
445 ucontrol->value.integer.value[1] =
446 max + 1 - ucontrol->value.integer.value[1];
447
448 return 0;
449}
450
451static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
452 struct snd_ctl_elem_value *ucontrol)
453{
454 struct soc_mixer_control *mc =
455 (struct soc_mixer_control *)kcontrol->private_value;
456 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
457 unsigned int reg = mc->reg;
458 unsigned int reg2 = mc->rreg;
459 unsigned int shift = mc->shift;
460 int max = mc->max;
461 int mask = (1 << fls(max)) - 1;
462 int err;
463 unsigned short val, val2, val_mask;
464
465 val_mask = mask << shift;
466 val = (ucontrol->value.integer.value[0] & mask);
467 val2 = (ucontrol->value.integer.value[1] & mask);
468
469 if (val)
470 val = max + 1 - val;
471 if (val2)
472 val2 = max + 1 - val2;
473
474 val = val << shift;
475 val2 = val2 << shift;
476
477 err = snd_soc_update_bits(codec, reg, val_mask, val);
478 if (err < 0)
479 return err;
480
481 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
482 return err;
483}
484
5920b453
GI		 485static int twl4030_get_left_input(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = kcontrol->private_data;
489 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
490 int result = 0;
491
492 /* one bit must be set a time */
493 reg &= TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
494 | TWL4030_MAINMIC_EN;
495 if (reg != 0) {
496 result++;
497 while ((reg & 1) == 0) {
498 result++;
499 reg >>= 1;
500 }
501 }
502
503 ucontrol->value.integer.value[0] = result;
504 return 0;
505}
506
507static int twl4030_put_left_input(struct snd_kcontrol *kcontrol,
508 struct snd_ctl_elem_value *ucontrol)
509{
510 struct snd_soc_codec *codec = kcontrol->private_data;
511 int value = ucontrol->value.integer.value[0];
512 u8 anamicl, micbias, avadc_ctl;
513
514 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
515 anamicl &= ~(TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
516 | TWL4030_MAINMIC_EN);
517 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
518 micbias &= ~(TWL4030_HSMICBIAS_EN | TWL4030_MICBIAS1_EN);
519 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
520
521 switch (value) {
522 case 1:
523 anamicl |= TWL4030_MAINMIC_EN;
524 micbias |= TWL4030_MICBIAS1_EN;
525 break;
526 case 2:
527 anamicl |= TWL4030_HSMIC_EN;
528 micbias |= TWL4030_HSMICBIAS_EN;
529 break;
530 case 3:
531 anamicl |= TWL4030_AUXL_EN;
532 break;
533 case 4:
534 anamicl |= TWL4030_CKMIC_EN;
535 break;
536 default:
537 break;
538 }
539
540 /* If some input is selected, enable amp and ADC */
541 if (value != 0) {
542 anamicl |= TWL4030_MICAMPL_EN;
543 avadc_ctl |= TWL4030_ADCL_EN;
544 } else {
545 anamicl &= ~TWL4030_MICAMPL_EN;
546 avadc_ctl &= ~TWL4030_ADCL_EN;
547 }
548
549 twl4030_write(codec, TWL4030_REG_ANAMICL, anamicl);
550 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
551 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
552
553 return 1;
554}
555
556static int twl4030_get_right_input(struct snd_kcontrol *kcontrol,
557 struct snd_ctl_elem_value *ucontrol)
558{
559 struct snd_soc_codec *codec = kcontrol->private_data;
560 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
561 int value = 0;
562
563 reg &= TWL4030_SUBMIC_EN|TWL4030_AUXR_EN;
564 switch (reg) {
565 case TWL4030_SUBMIC_EN:
566 value = 1;
567 break;
568 case TWL4030_AUXR_EN:
569 value = 2;
570 break;
571 default:
572 break;
573 }
574
575 ucontrol->value.integer.value[0] = value;
576 return 0;
577}
578
579static int twl4030_put_right_input(struct snd_kcontrol *kcontrol,
580 struct snd_ctl_elem_value *ucontrol)
581{
582 struct snd_soc_codec *codec = kcontrol->private_data;
583 int value = ucontrol->value.integer.value[0];
584 u8 anamicr, micbias, avadc_ctl;
585
586 anamicr = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
587 anamicr &= ~(TWL4030_SUBMIC_EN|TWL4030_AUXR_EN);
588 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
589 micbias &= ~TWL4030_MICBIAS2_EN;
590 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
591
592 switch (value) {
593 case 1:
594 anamicr |= TWL4030_SUBMIC_EN;
595 micbias |= TWL4030_MICBIAS2_EN;
596 break;
597 case 2:
598 anamicr |= TWL4030_AUXR_EN;
599 break;
600 default:
601 break;
602 }
603
604 if (value != 0) {
605 anamicr |= TWL4030_MICAMPR_EN;
606 avadc_ctl |= TWL4030_ADCR_EN;
607 } else {
608 anamicr &= ~TWL4030_MICAMPR_EN;
609 avadc_ctl &= ~TWL4030_ADCR_EN;
610 }
611
612 twl4030_write(codec, TWL4030_REG_ANAMICR, anamicr);
613 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
614 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
615
616 return 1;
617}
618
619static const char *twl4030_left_in_sel[] = {
620 "None",
621 "Main Mic",
622 "Headset Mic",
623 "Line In",
624 "Carkit Mic",
625};
626
627static const char *twl4030_right_in_sel[] = {
628 "None",
629 "Sub Mic",
630 "Line In",
631};
632
633static const struct soc_enum twl4030_left_input_mux =
634 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel),
635 twl4030_left_in_sel);
636
637static const struct soc_enum twl4030_right_input_mux =
638 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel),
639 twl4030_right_in_sel);
640
c10b82cf
PU		 641/*
642 * FGAIN volume control:
643 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
644 */
d889a72c 645static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 646
0d33ea0b
PU		 647/*
648 * CGAIN volume control:
649 * 0 dB to 12 dB in 6 dB steps
650 * value 2 and 3 means 12 dB
651 */
d889a72c
PU		 652static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
653
654/*
655 * Analog playback gain
656 * -24 dB to 12 dB in 2 dB steps
657 */
658static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 659
4290239c
PU		 660/*
661 * Gain controls tied to outputs
662 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
663 */
664static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
665
381a22b5
PU		 666/*
667 * Capture gain after the ADCs
668 * from 0 dB to 31 dB in 1 dB steps
669 */
670static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
671
5920b453
GI		 672/*
673 * Gain control for input amplifiers
674 * 0 dB to 30 dB in 6 dB steps
675 */
676static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
677
cc17557e 678static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 679 /* Common playback gain controls */
680 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
681 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
682 0, 0x3f, 0, digital_fine_tlv),
683 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
684 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
685 0, 0x3f, 0, digital_fine_tlv),
686
687 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
688 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
689 6, 0x2, 0, digital_coarse_tlv),
690 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
691 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
692 6, 0x2, 0, digital_coarse_tlv),
693
694 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
695 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
696 3, 0x12, 1, analog_tlv),
697 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
698 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
699 3, 0x12, 1, analog_tlv),
44c55870
PU		 700 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
701 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
702 1, 1, 0),
703 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
704 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
705 1, 1, 0),
381a22b5 706
4290239c
PU		 707 /* Separate output gain controls */
708 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
709 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
710 4, 3, 0, output_tvl),
711
712 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
713 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
714
715 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
716 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
717 4, 3, 0, output_tvl),
718
719 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
720 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
721
381a22b5
PU		 722 /* Common capture gain controls */
723 SOC_DOUBLE_R_TLV("Capture Volume",
724 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
725 0, 0x1f, 0, digital_capture_tlv),
5920b453
GI		 726
727 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN,
728 0, 3, 5, 0, input_gain_tlv),
729
730 /* Input source controls */
731 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux,
732 twl4030_get_left_input, twl4030_put_left_input),
733 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux,
734 twl4030_get_right_input, twl4030_put_right_input),
cc17557e
SS		 735};
736
737/* add non dapm controls */
738static int twl4030_add_controls(struct snd_soc_codec *codec)
739{
740 int err, i;
741
742 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
743 err = snd_ctl_add(codec->card,
744 snd_soc_cnew(&twl4030_snd_controls[i],
745 codec, NULL));
746 if (err < 0)
747 return err;
748 }
749
750 return 0;
751}
752
753static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
754 SND_SOC_DAPM_INPUT("INL"),
755 SND_SOC_DAPM_INPUT("INR"),
756
757 SND_SOC_DAPM_OUTPUT("OUTL"),
758 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 759 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 760 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
761 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 762 SND_SOC_DAPM_OUTPUT("HSOL"),
763 SND_SOC_DAPM_OUTPUT("HSOR"),
df339804
PU		 764 SND_SOC_DAPM_OUTPUT("HFL"),
765 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 766
53b5047d
PU		 767 /* DACs */
768 SND_SOC_DAPM_DAC("DACR1", "Right Front Playback",
769 TWL4030_REG_AVDAC_CTL, 0, 0),
770 SND_SOC_DAPM_DAC("DACL1", "Left Front Playback",
771 TWL4030_REG_AVDAC_CTL, 1, 0),
772 SND_SOC_DAPM_DAC("DACR2", "Right Rear Playback",
773 TWL4030_REG_AVDAC_CTL, 2, 0),
774 SND_SOC_DAPM_DAC("DACL2", "Left Rear Playback",
775 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e 776
44c55870
PU		 777 /* Analog PGAs */
778 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
779 0, 0, NULL, 0),
780 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
781 0, 0, NULL, 0),
782 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
783 0, 0, NULL, 0),
784 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
785 0, 0, NULL, 0),
786
5e98a464
PU		 787 /* Output MUX controls */
788 /* Earpiece */
789 SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM, 0, 0,
790 &twl4030_dapm_earpiece_control, outmixer_event,
791 SND_SOC_DAPM_PRE_REG),
2a6f5c58
PU		 792 /* PreDrivL/R */
793 SND_SOC_DAPM_MUX_E("PredriveL Mux", SND_SOC_NOPM, 0, 0,
794 &twl4030_dapm_predrivel_control, outmixer_event,
795 SND_SOC_DAPM_PRE_REG),
796 SND_SOC_DAPM_MUX_E("PredriveR Mux", SND_SOC_NOPM, 0, 0,
797 &twl4030_dapm_predriver_control, outmixer_event,
798 SND_SOC_DAPM_PRE_REG),
dfad21a2
PU		 799 /* HeadsetL/R */
800 SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
801 &twl4030_dapm_hsol_control),
802 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
803 &twl4030_dapm_hsor_control),
5152d8c2
PU		 804 /* CarkitL/R */
805 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
806 &twl4030_dapm_carkitl_control),
807 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
808 &twl4030_dapm_carkitr_control),
df339804
PU		 809 /* HandsfreeL/R */
810 SND_SOC_DAPM_MUX("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
811 &twl4030_dapm_handsfreel_control),
812 SND_SOC_DAPM_MUX("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
813 &twl4030_dapm_handsfreer_control),
5e98a464 814
cc17557e
SS		 815 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
816 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
817};
818
819static const struct snd_soc_dapm_route intercon[] = {
44c55870
PU		 820 {"ARXL1_APGA", NULL, "DACL1"},
821 {"ARXR1_APGA", NULL, "DACR1"},
822 {"ARXL2_APGA", NULL, "DACL2"},
823 {"ARXR2_APGA", NULL, "DACR2"},
824
5e98a464
PU		 825 /* Internal playback routings */
826 /* Earpiece */
827 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
828 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
829 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 830 /* PreDrivL */
831 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
832 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
833 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
834 /* PreDrivR */
835 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
836 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
837 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 838 /* HeadsetL */
839 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
840 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
841 /* HeadsetR */
842 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
843 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 844 /* CarkitL */
845 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
846 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
847 /* CarkitR */
848 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
849 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 850 /* HandsfreeL */
851 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
852 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
853 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
854 /* HandsfreeR */
855 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
856 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
857 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 858
cc17557e 859 /* outputs */
44c55870
PU		 860 {"OUTL", NULL, "ARXL2_APGA"},
861 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 862 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 863 {"PREDRIVEL", NULL, "PredriveL Mux"},
864 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 865 {"HSOL", NULL, "HeadsetL Mux"},
866 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 867 {"CARKITL", NULL, "CarkitL Mux"},
868 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 869 {"HFL", NULL, "HandsfreeL Mux"},
870 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e
SS		 871
872 /* inputs */
873 {"ADCL", NULL, "INL"},
874 {"ADCR", NULL, "INR"},
875};
876
877static int twl4030_add_widgets(struct snd_soc_codec *codec)
878{
879 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
880 ARRAY_SIZE(twl4030_dapm_widgets));
881
882 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
883
884 snd_soc_dapm_new_widgets(codec);
885 return 0;
886}
887
888static void twl4030_power_up(struct snd_soc_codec *codec)
889{
ca4513fe 890 u8 anamicl, regmisc1, byte, popn;
cc17557e
SS		 891 int i = 0;
892
893 /* set CODECPDZ to turn on codec */
894 twl4030_set_codecpdz(codec);
895
896 /* initiate offset cancellation */
897 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
898 twl4030_write(codec, TWL4030_REG_ANAMICL,
899 anamicl | TWL4030_CNCL_OFFSET_START);
900
901 /* wait for offset cancellation to complete */
902 do {
903 /* this takes a little while, so don't slam i2c */
904 udelay(2000);
905 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
906 TWL4030_REG_ANAMICL);
907 } while ((i++ < 100) &&
908 ((byte & TWL4030_CNCL_OFFSET_START) ==
909 TWL4030_CNCL_OFFSET_START));
910
911 /* anti-pop when changing analog gain */
912 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
913 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
914 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
915
916 /* toggle CODECPDZ as per TRM */
917 twl4030_clear_codecpdz(codec);
918 twl4030_set_codecpdz(codec);
919
920 /* program anti-pop with bias ramp delay */
921 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
922 popn &= TWL4030_RAMP_DELAY;
923 popn |= TWL4030_RAMP_DELAY_645MS;
924 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
925 popn |= TWL4030_VMID_EN;
926 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
927
cc17557e
SS		 928 /* enable anti-pop ramp */
929 popn |= TWL4030_RAMP_EN;
930 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
931}
932
933static void twl4030_power_down(struct snd_soc_codec *codec)
934{
ca4513fe 935 u8 popn;
cc17557e
SS		 936
937 /* disable anti-pop ramp */
938 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
939 popn &= ~TWL4030_RAMP_EN;
940 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
941
cc17557e
SS		 942 /* disable bias out */
943 popn &= ~TWL4030_VMID_EN;
944 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
945
946 /* power down */
947 twl4030_clear_codecpdz(codec);
948}
949
950static int twl4030_set_bias_level(struct snd_soc_codec *codec,
951 enum snd_soc_bias_level level)
952{
953 switch (level) {
954 case SND_SOC_BIAS_ON:
955 twl4030_power_up(codec);
956 break;
957 case SND_SOC_BIAS_PREPARE:
958 /* TODO: develop a twl4030_prepare function */
959 break;
960 case SND_SOC_BIAS_STANDBY:
961 /* TODO: develop a twl4030_standby function */
962 twl4030_power_down(codec);
963 break;
964 case SND_SOC_BIAS_OFF:
965 twl4030_power_down(codec);
966 break;
967 }
968 codec->bias_level = level;
969
970 return 0;
971}
972
973static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 974 struct snd_pcm_hw_params *params,
975 struct snd_soc_dai *dai)
cc17557e
SS		 976{
977 struct snd_soc_pcm_runtime *rtd = substream->private_data;
978 struct snd_soc_device *socdev = rtd->socdev;
979 struct snd_soc_codec *codec = socdev->codec;
980 u8 mode, old_mode, format, old_format;
981
982
983 /* bit rate */
984 old_mode = twl4030_read_reg_cache(codec,
985 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
986 mode = old_mode & ~TWL4030_APLL_RATE;
987
988 switch (params_rate(params)) {
989 case 8000:
990 mode |= TWL4030_APLL_RATE_8000;
991 break;
992 case 11025:
993 mode |= TWL4030_APLL_RATE_11025;
994 break;
995 case 12000:
996 mode |= TWL4030_APLL_RATE_12000;
997 break;
998 case 16000:
999 mode |= TWL4030_APLL_RATE_16000;
1000 break;
1001 case 22050:
1002 mode |= TWL4030_APLL_RATE_22050;
1003 break;
1004 case 24000:
1005 mode |= TWL4030_APLL_RATE_24000;
1006 break;
1007 case 32000:
1008 mode |= TWL4030_APLL_RATE_32000;
1009 break;
1010 case 44100:
1011 mode |= TWL4030_APLL_RATE_44100;
1012 break;
1013 case 48000:
1014 mode |= TWL4030_APLL_RATE_48000;
1015 break;
1016 default:
1017 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1018 params_rate(params));
1019 return -EINVAL;
1020 }
1021
1022 if (mode != old_mode) {
1023 /* change rate and set CODECPDZ */
1024 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1025 twl4030_set_codecpdz(codec);
1026 }
1027
1028 /* sample size */
1029 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1030 format = old_format;
1031 format &= ~TWL4030_DATA_WIDTH;
1032 switch (params_format(params)) {
1033 case SNDRV_PCM_FORMAT_S16_LE:
1034 format |= TWL4030_DATA_WIDTH_16S_16W;
1035 break;
1036 case SNDRV_PCM_FORMAT_S24_LE:
1037 format |= TWL4030_DATA_WIDTH_32S_24W;
1038 break;
1039 default:
1040 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1041 params_format(params));
1042 return -EINVAL;
1043 }
1044
1045 if (format != old_format) {
1046
1047 /* clear CODECPDZ before changing format (codec requirement) */
1048 twl4030_clear_codecpdz(codec);
1049
1050 /* change format */
1051 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1052
1053 /* set CODECPDZ afterwards */
1054 twl4030_set_codecpdz(codec);
1055 }
1056 return 0;
1057}
1058
1059static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1060 int clk_id, unsigned int freq, int dir)
1061{
1062 struct snd_soc_codec *codec = codec_dai->codec;
1063 u8 infreq;
1064
1065 switch (freq) {
1066 case 19200000:
1067 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1068 break;
1069 case 26000000:
1070 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1071 break;
1072 case 38400000:
1073 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1074 break;
1075 default:
1076 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1077 freq);
1078 return -EINVAL;
1079 }
1080
1081 infreq |= TWL4030_APLL_EN;
1082 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1083
1084 return 0;
1085}
1086
1087static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1088 unsigned int fmt)
1089{
1090 struct snd_soc_codec *codec = codec_dai->codec;
1091 u8 old_format, format;
1092
1093 /* get format */
1094 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1095 format = old_format;
1096
1097 /* set master/slave audio interface */
1098 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1099 case SND_SOC_DAIFMT_CBM_CFM:
1100 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1101 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1102 break;
1103 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1104 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1105 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1106 break;
1107 default:
1108 return -EINVAL;
1109 }
1110
1111 /* interface format */
1112 format &= ~TWL4030_AIF_FORMAT;
1113 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1114 case SND_SOC_DAIFMT_I2S:
1115 format |= TWL4030_AIF_FORMAT_CODEC;
1116 break;
1117 default:
1118 return -EINVAL;
1119 }
1120
1121 if (format != old_format) {
1122
1123 /* clear CODECPDZ before changing format (codec requirement) */
1124 twl4030_clear_codecpdz(codec);
1125
1126 /* change format */
1127 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1128
1129 /* set CODECPDZ afterwards */
1130 twl4030_set_codecpdz(codec);
1131 }
1132
1133 return 0;
1134}
1135
bbba9444 1136#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1137#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1138
1139struct snd_soc_dai twl4030_dai = {
1140 .name = "twl4030",
1141 .playback = {
1142 .stream_name = "Playback",
1143 .channels_min = 2,
1144 .channels_max = 2,
1145 .rates = TWL4030_RATES,
1146 .formats = TWL4030_FORMATS,},
1147 .capture = {
1148 .stream_name = "Capture",
1149 .channels_min = 2,
1150 .channels_max = 2,
1151 .rates = TWL4030_RATES,
1152 .formats = TWL4030_FORMATS,},
1153 .ops = {
1154 .hw_params = twl4030_hw_params,
cc17557e
SS		 1155 .set_sysclk = twl4030_set_dai_sysclk,
1156 .set_fmt = twl4030_set_dai_fmt,
1157 }
1158};
1159EXPORT_SYMBOL_GPL(twl4030_dai);
1160
1161static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1162{
1163 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1164 struct snd_soc_codec *codec = socdev->codec;
1165
1166 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1167
1168 return 0;
1169}
1170
1171static int twl4030_resume(struct platform_device *pdev)
1172{
1173 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1174 struct snd_soc_codec *codec = socdev->codec;
1175
1176 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1177 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1178 return 0;
1179}
1180
1181/*
1182 * initialize the driver
1183 * register the mixer and dsp interfaces with the kernel
1184 */
1185
1186static int twl4030_init(struct snd_soc_device *socdev)
1187{
1188 struct snd_soc_codec *codec = socdev->codec;
1189 int ret = 0;
1190
1191 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1192
1193 codec->name = "twl4030";
1194 codec->owner = THIS_MODULE;
1195 codec->read = twl4030_read_reg_cache;
1196 codec->write = twl4030_write;
1197 codec->set_bias_level = twl4030_set_bias_level;
1198 codec->dai = &twl4030_dai;
1199 codec->num_dai = 1;
1200 codec->reg_cache_size = sizeof(twl4030_reg);
1201 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1202 GFP_KERNEL);
1203 if (codec->reg_cache == NULL)
1204 return -ENOMEM;
1205
1206 /* register pcms */
1207 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1208 if (ret < 0) {
1209 printk(KERN_ERR "twl4030: failed to create pcms\n");
1210 goto pcm_err;
1211 }
1212
1213 twl4030_init_chip(codec);
1214
1215 /* power on device */
1216 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1217
1218 twl4030_add_controls(codec);
1219 twl4030_add_widgets(codec);
1220
968a6025 1221 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1222 if (ret < 0) {
1223 printk(KERN_ERR "twl4030: failed to register card\n");
1224 goto card_err;
1225 }
1226
1227 return ret;
1228
1229card_err:
1230 snd_soc_free_pcms(socdev);
1231 snd_soc_dapm_free(socdev);
1232pcm_err:
1233 kfree(codec->reg_cache);
1234 return ret;
1235}
1236
1237static struct snd_soc_device *twl4030_socdev;
1238
1239static int twl4030_probe(struct platform_device *pdev)
1240{
1241 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1242 struct snd_soc_codec *codec;
1243
1244 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1245 if (codec == NULL)
1246 return -ENOMEM;
1247
1248 socdev->codec = codec;
1249 mutex_init(&codec->mutex);
1250 INIT_LIST_HEAD(&codec->dapm_widgets);
1251 INIT_LIST_HEAD(&codec->dapm_paths);
1252
1253 twl4030_socdev = socdev;
1254 twl4030_init(socdev);
1255
1256 return 0;
1257}
1258
1259static int twl4030_remove(struct platform_device *pdev)
1260{
1261 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1262 struct snd_soc_codec *codec = socdev->codec;
1263
1264 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1265 kfree(codec);
1266
1267 return 0;
1268}
1269
1270struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1271 .probe = twl4030_probe,
1272 .remove = twl4030_remove,
1273 .suspend = twl4030_suspend,
1274 .resume = twl4030_resume,
1275};
1276EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1277
1278MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1279MODULE_AUTHOR("Steve Sakoman");
1280MODULE_LICENSE("GPL");
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