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cc17557e SS |
1 | /* |
2 | * ALSA SoC TWL4030 codec driver | |
3 | * | |
4 | * Author: Steve Sakoman, <steve@sakoman.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/i2c.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/i2c/twl4030.h> | |
30 | #include <sound/core.h> | |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/soc-dapm.h> | |
35 | #include <sound/initval.h> | |
c10b82cf | 36 | #include <sound/tlv.h> |
cc17557e SS |
37 | |
38 | #include "twl4030.h" | |
39 | ||
40 | /* | |
41 | * twl4030 register cache & default register settings | |
42 | */ | |
43 | static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { | |
44 | 0x00, /* this register not used */ | |
db04e2c5 | 45 | 0x91, /* REG_CODEC_MODE (0x1) */ |
cc17557e SS |
46 | 0xc3, /* REG_OPTION (0x2) */ |
47 | 0x00, /* REG_UNKNOWN (0x3) */ | |
48 | 0x00, /* REG_MICBIAS_CTL (0x4) */ | |
5920b453 GI |
49 | 0x20, /* REG_ANAMICL (0x5) */ |
50 | 0x00, /* REG_ANAMICR (0x6) */ | |
51 | 0x00, /* REG_AVADC_CTL (0x7) */ | |
cc17557e SS |
52 | 0x00, /* REG_ADCMICSEL (0x8) */ |
53 | 0x00, /* REG_DIGMIXING (0x9) */ | |
54 | 0x0c, /* REG_ATXL1PGA (0xA) */ | |
55 | 0x0c, /* REG_ATXR1PGA (0xB) */ | |
56 | 0x00, /* REG_AVTXL2PGA (0xC) */ | |
57 | 0x00, /* REG_AVTXR2PGA (0xD) */ | |
58 | 0x01, /* REG_AUDIO_IF (0xE) */ | |
59 | 0x00, /* REG_VOICE_IF (0xF) */ | |
60 | 0x00, /* REG_ARXR1PGA (0x10) */ | |
61 | 0x00, /* REG_ARXL1PGA (0x11) */ | |
62 | 0x6c, /* REG_ARXR2PGA (0x12) */ | |
63 | 0x6c, /* REG_ARXL2PGA (0x13) */ | |
64 | 0x00, /* REG_VRXPGA (0x14) */ | |
65 | 0x00, /* REG_VSTPGA (0x15) */ | |
66 | 0x00, /* REG_VRX2ARXPGA (0x16) */ | |
67 | 0x0c, /* REG_AVDAC_CTL (0x17) */ | |
68 | 0x00, /* REG_ARX2VTXPGA (0x18) */ | |
69 | 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ | |
70 | 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ | |
71 | 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */ | |
72 | 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */ | |
73 | 0x00, /* REG_ATX2ARXPGA (0x1D) */ | |
74 | 0x00, /* REG_BT_IF (0x1E) */ | |
75 | 0x00, /* REG_BTPGA (0x1F) */ | |
76 | 0x00, /* REG_BTSTPGA (0x20) */ | |
77 | 0x00, /* REG_EAR_CTL (0x21) */ | |
78 | 0x24, /* REG_HS_SEL (0x22) */ | |
79 | 0x0a, /* REG_HS_GAIN_SET (0x23) */ | |
80 | 0x00, /* REG_HS_POPN_SET (0x24) */ | |
81 | 0x00, /* REG_PREDL_CTL (0x25) */ | |
82 | 0x00, /* REG_PREDR_CTL (0x26) */ | |
83 | 0x00, /* REG_PRECKL_CTL (0x27) */ | |
84 | 0x00, /* REG_PRECKR_CTL (0x28) */ | |
85 | 0x00, /* REG_HFL_CTL (0x29) */ | |
86 | 0x00, /* REG_HFR_CTL (0x2A) */ | |
87 | 0x00, /* REG_ALC_CTL (0x2B) */ | |
88 | 0x00, /* REG_ALC_SET1 (0x2C) */ | |
89 | 0x00, /* REG_ALC_SET2 (0x2D) */ | |
90 | 0x00, /* REG_BOOST_CTL (0x2E) */ | |
f8d05bdb | 91 | 0x00, /* REG_SOFTVOL_CTL (0x2F) */ |
cc17557e SS |
92 | 0x00, /* REG_DTMF_FREQSEL (0x30) */ |
93 | 0x00, /* REG_DTMF_TONEXT1H (0x31) */ | |
94 | 0x00, /* REG_DTMF_TONEXT1L (0x32) */ | |
95 | 0x00, /* REG_DTMF_TONEXT2H (0x33) */ | |
96 | 0x00, /* REG_DTMF_TONEXT2L (0x34) */ | |
97 | 0x00, /* REG_DTMF_TONOFF (0x35) */ | |
98 | 0x00, /* REG_DTMF_WANONOFF (0x36) */ | |
99 | 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ | |
100 | 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ | |
101 | 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ | |
102 | 0x16, /* REG_APLL_CTL (0x3A) */ | |
103 | 0x00, /* REG_DTMF_CTL (0x3B) */ | |
104 | 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ | |
105 | 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ | |
106 | 0x00, /* REG_MISC_SET_1 (0x3E) */ | |
107 | 0x00, /* REG_PCMBTMUX (0x3F) */ | |
108 | 0x00, /* not used (0x40) */ | |
109 | 0x00, /* not used (0x41) */ | |
110 | 0x00, /* not used (0x42) */ | |
111 | 0x00, /* REG_RX_PATH_SEL (0x43) */ | |
112 | 0x00, /* REG_VDL_APGA_CTL (0x44) */ | |
113 | 0x00, /* REG_VIBRA_CTL (0x45) */ | |
114 | 0x00, /* REG_VIBRA_SET (0x46) */ | |
115 | 0x00, /* REG_VIBRA_PWM_SET (0x47) */ | |
116 | 0x00, /* REG_ANAMIC_GAIN (0x48) */ | |
117 | 0x00, /* REG_MISC_SET_2 (0x49) */ | |
118 | }; | |
119 | ||
120 | /* | |
121 | * read twl4030 register cache | |
122 | */ | |
123 | static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, | |
124 | unsigned int reg) | |
125 | { | |
126 | u8 *cache = codec->reg_cache; | |
127 | ||
91432e97 IM |
128 | if (reg >= TWL4030_CACHEREGNUM) |
129 | return -EIO; | |
130 | ||
cc17557e SS |
131 | return cache[reg]; |
132 | } | |
133 | ||
134 | /* | |
135 | * write twl4030 register cache | |
136 | */ | |
137 | static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, | |
138 | u8 reg, u8 value) | |
139 | { | |
140 | u8 *cache = codec->reg_cache; | |
141 | ||
142 | if (reg >= TWL4030_CACHEREGNUM) | |
143 | return; | |
144 | cache[reg] = value; | |
145 | } | |
146 | ||
147 | /* | |
148 | * write to the twl4030 register space | |
149 | */ | |
150 | static int twl4030_write(struct snd_soc_codec *codec, | |
151 | unsigned int reg, unsigned int value) | |
152 | { | |
153 | twl4030_write_reg_cache(codec, reg, value); | |
154 | return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); | |
155 | } | |
156 | ||
db04e2c5 | 157 | static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) |
cc17557e SS |
158 | { |
159 | u8 mode; | |
160 | ||
161 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); | |
db04e2c5 PU |
162 | if (enable) |
163 | mode |= TWL4030_CODECPDZ; | |
164 | else | |
165 | mode &= ~TWL4030_CODECPDZ; | |
cc17557e | 166 | |
db04e2c5 | 167 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); |
cc17557e SS |
168 | |
169 | /* REVISIT: this delay is present in TI sample drivers */ | |
170 | /* but there seems to be no TRM requirement for it */ | |
171 | udelay(10); | |
172 | } | |
173 | ||
174 | static void twl4030_init_chip(struct snd_soc_codec *codec) | |
175 | { | |
176 | int i; | |
177 | ||
178 | /* clear CODECPDZ prior to setting register defaults */ | |
db04e2c5 | 179 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
180 | |
181 | /* set all audio section registers to reasonable defaults */ | |
182 | for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) | |
183 | twl4030_write(codec, i, twl4030_reg[i]); | |
184 | ||
185 | } | |
186 | ||
5e98a464 PU |
187 | /* Earpiece */ |
188 | static const char *twl4030_earpiece_texts[] = | |
2f423577 | 189 | {"Off", "DACL1", "DACL2", "DACR1"}; |
5e98a464 | 190 | |
2f423577 PU |
191 | static const unsigned int twl4030_earpiece_values[] = |
192 | {0x0, 0x1, 0x2, 0x4}; | |
193 | ||
cb1ace04 | 194 | static const struct soc_enum twl4030_earpiece_enum = |
2f423577 | 195 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7, |
5e98a464 | 196 | ARRAY_SIZE(twl4030_earpiece_texts), |
2f423577 PU |
197 | twl4030_earpiece_texts, |
198 | twl4030_earpiece_values); | |
5e98a464 PU |
199 | |
200 | static const struct snd_kcontrol_new twl4030_dapm_earpiece_control = | |
2f423577 | 201 | SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum); |
5e98a464 | 202 | |
2a6f5c58 PU |
203 | /* PreDrive Left */ |
204 | static const char *twl4030_predrivel_texts[] = | |
2f423577 PU |
205 | {"Off", "DACL1", "DACL2", "DACR2"}; |
206 | ||
207 | static const unsigned int twl4030_predrivel_values[] = | |
208 | {0x0, 0x1, 0x2, 0x4}; | |
2a6f5c58 | 209 | |
cb1ace04 | 210 | static const struct soc_enum twl4030_predrivel_enum = |
2f423577 | 211 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7, |
2a6f5c58 | 212 | ARRAY_SIZE(twl4030_predrivel_texts), |
2f423577 PU |
213 | twl4030_predrivel_texts, |
214 | twl4030_predrivel_values); | |
2a6f5c58 PU |
215 | |
216 | static const struct snd_kcontrol_new twl4030_dapm_predrivel_control = | |
2f423577 | 217 | SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum); |
2a6f5c58 PU |
218 | |
219 | /* PreDrive Right */ | |
220 | static const char *twl4030_predriver_texts[] = | |
2f423577 | 221 | {"Off", "DACR1", "DACR2", "DACL2"}; |
2a6f5c58 | 222 | |
2f423577 PU |
223 | static const unsigned int twl4030_predriver_values[] = |
224 | {0x0, 0x1, 0x2, 0x4}; | |
225 | ||
cb1ace04 | 226 | static const struct soc_enum twl4030_predriver_enum = |
2f423577 | 227 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7, |
2a6f5c58 | 228 | ARRAY_SIZE(twl4030_predriver_texts), |
2f423577 PU |
229 | twl4030_predriver_texts, |
230 | twl4030_predriver_values); | |
2a6f5c58 PU |
231 | |
232 | static const struct snd_kcontrol_new twl4030_dapm_predriver_control = | |
2f423577 | 233 | SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum); |
2a6f5c58 | 234 | |
dfad21a2 PU |
235 | /* Headset Left */ |
236 | static const char *twl4030_hsol_texts[] = | |
237 | {"Off", "DACL1", "DACL2"}; | |
238 | ||
239 | static const struct soc_enum twl4030_hsol_enum = | |
240 | SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1, | |
241 | ARRAY_SIZE(twl4030_hsol_texts), | |
242 | twl4030_hsol_texts); | |
243 | ||
244 | static const struct snd_kcontrol_new twl4030_dapm_hsol_control = | |
245 | SOC_DAPM_ENUM("Route", twl4030_hsol_enum); | |
246 | ||
247 | /* Headset Right */ | |
248 | static const char *twl4030_hsor_texts[] = | |
249 | {"Off", "DACR1", "DACR2"}; | |
250 | ||
251 | static const struct soc_enum twl4030_hsor_enum = | |
252 | SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4, | |
253 | ARRAY_SIZE(twl4030_hsor_texts), | |
254 | twl4030_hsor_texts); | |
255 | ||
256 | static const struct snd_kcontrol_new twl4030_dapm_hsor_control = | |
257 | SOC_DAPM_ENUM("Route", twl4030_hsor_enum); | |
258 | ||
5152d8c2 PU |
259 | /* Carkit Left */ |
260 | static const char *twl4030_carkitl_texts[] = | |
261 | {"Off", "DACL1", "DACL2"}; | |
262 | ||
263 | static const struct soc_enum twl4030_carkitl_enum = | |
264 | SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1, | |
265 | ARRAY_SIZE(twl4030_carkitl_texts), | |
266 | twl4030_carkitl_texts); | |
267 | ||
268 | static const struct snd_kcontrol_new twl4030_dapm_carkitl_control = | |
269 | SOC_DAPM_ENUM("Route", twl4030_carkitl_enum); | |
270 | ||
271 | /* Carkit Right */ | |
272 | static const char *twl4030_carkitr_texts[] = | |
273 | {"Off", "DACR1", "DACR2"}; | |
274 | ||
275 | static const struct soc_enum twl4030_carkitr_enum = | |
276 | SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1, | |
277 | ARRAY_SIZE(twl4030_carkitr_texts), | |
278 | twl4030_carkitr_texts); | |
279 | ||
280 | static const struct snd_kcontrol_new twl4030_dapm_carkitr_control = | |
281 | SOC_DAPM_ENUM("Route", twl4030_carkitr_enum); | |
282 | ||
df339804 PU |
283 | /* Handsfree Left */ |
284 | static const char *twl4030_handsfreel_texts[] = | |
285 | {"Voice", "DACL1", "DACL2", "DACR2"}; | |
286 | ||
287 | static const struct soc_enum twl4030_handsfreel_enum = | |
288 | SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0, | |
289 | ARRAY_SIZE(twl4030_handsfreel_texts), | |
290 | twl4030_handsfreel_texts); | |
291 | ||
292 | static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = | |
293 | SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); | |
294 | ||
295 | /* Handsfree Right */ | |
296 | static const char *twl4030_handsfreer_texts[] = | |
297 | {"Voice", "DACR1", "DACR2", "DACL2"}; | |
298 | ||
299 | static const struct soc_enum twl4030_handsfreer_enum = | |
300 | SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0, | |
301 | ARRAY_SIZE(twl4030_handsfreer_texts), | |
302 | twl4030_handsfreer_texts); | |
303 | ||
304 | static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = | |
305 | SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); | |
306 | ||
276c6222 PU |
307 | /* Left analog microphone selection */ |
308 | static const char *twl4030_analoglmic_texts[] = | |
2f423577 PU |
309 | {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"}; |
310 | ||
311 | static const unsigned int twl4030_analoglmic_values[] = | |
312 | {0x0, 0x1, 0x2, 0x4, 0x8}; | |
276c6222 | 313 | |
cb1ace04 | 314 | static const struct soc_enum twl4030_analoglmic_enum = |
2f423577 | 315 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf, |
276c6222 | 316 | ARRAY_SIZE(twl4030_analoglmic_texts), |
2f423577 PU |
317 | twl4030_analoglmic_texts, |
318 | twl4030_analoglmic_values); | |
276c6222 PU |
319 | |
320 | static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control = | |
2f423577 | 321 | SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum); |
276c6222 PU |
322 | |
323 | /* Right analog microphone selection */ | |
324 | static const char *twl4030_analogrmic_texts[] = | |
2f423577 | 325 | {"Off", "Sub mic", "AUXR"}; |
276c6222 | 326 | |
2f423577 PU |
327 | static const unsigned int twl4030_analogrmic_values[] = |
328 | {0x0, 0x1, 0x4}; | |
329 | ||
cb1ace04 | 330 | static const struct soc_enum twl4030_analogrmic_enum = |
2f423577 | 331 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5, |
276c6222 | 332 | ARRAY_SIZE(twl4030_analogrmic_texts), |
2f423577 PU |
333 | twl4030_analogrmic_texts, |
334 | twl4030_analogrmic_values); | |
276c6222 PU |
335 | |
336 | static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control = | |
2f423577 | 337 | SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum); |
276c6222 PU |
338 | |
339 | /* TX1 L/R Analog/Digital microphone selection */ | |
340 | static const char *twl4030_micpathtx1_texts[] = | |
341 | {"Analog", "Digimic0"}; | |
342 | ||
343 | static const struct soc_enum twl4030_micpathtx1_enum = | |
344 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0, | |
345 | ARRAY_SIZE(twl4030_micpathtx1_texts), | |
346 | twl4030_micpathtx1_texts); | |
347 | ||
348 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control = | |
349 | SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum); | |
350 | ||
351 | /* TX2 L/R Analog/Digital microphone selection */ | |
352 | static const char *twl4030_micpathtx2_texts[] = | |
353 | {"Analog", "Digimic1"}; | |
354 | ||
355 | static const struct soc_enum twl4030_micpathtx2_enum = | |
356 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2, | |
357 | ARRAY_SIZE(twl4030_micpathtx2_texts), | |
358 | twl4030_micpathtx2_texts); | |
359 | ||
360 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control = | |
361 | SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum); | |
362 | ||
276c6222 PU |
363 | static int micpath_event(struct snd_soc_dapm_widget *w, |
364 | struct snd_kcontrol *kcontrol, int event) | |
365 | { | |
366 | struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value; | |
367 | unsigned char adcmicsel, micbias_ctl; | |
368 | ||
369 | adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL); | |
370 | micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL); | |
371 | /* Prepare the bits for the given TX path: | |
372 | * shift_l == 0: TX1 microphone path | |
373 | * shift_l == 2: TX2 microphone path */ | |
374 | if (e->shift_l) { | |
375 | /* TX2 microphone path */ | |
376 | if (adcmicsel & TWL4030_TX2IN_SEL) | |
377 | micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */ | |
378 | else | |
379 | micbias_ctl &= ~TWL4030_MICBIAS2_CTL; | |
380 | } else { | |
381 | /* TX1 microphone path */ | |
382 | if (adcmicsel & TWL4030_TX1IN_SEL) | |
383 | micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */ | |
384 | else | |
385 | micbias_ctl &= ~TWL4030_MICBIAS1_CTL; | |
386 | } | |
387 | ||
388 | twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl); | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
49d92c7d SM |
393 | static int handsfree_event(struct snd_soc_dapm_widget *w, |
394 | struct snd_kcontrol *kcontrol, int event) | |
395 | { | |
396 | struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value; | |
397 | unsigned char hs_ctl; | |
398 | ||
399 | hs_ctl = twl4030_read_reg_cache(w->codec, e->reg); | |
400 | ||
401 | if (hs_ctl & TWL4030_HF_CTL_REF_EN) { | |
402 | hs_ctl |= TWL4030_HF_CTL_RAMP_EN; | |
403 | twl4030_write(w->codec, e->reg, hs_ctl); | |
404 | hs_ctl |= TWL4030_HF_CTL_LOOP_EN; | |
405 | twl4030_write(w->codec, e->reg, hs_ctl); | |
406 | hs_ctl |= TWL4030_HF_CTL_HB_EN; | |
407 | twl4030_write(w->codec, e->reg, hs_ctl); | |
408 | } else { | |
409 | hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN | |
410 | | TWL4030_HF_CTL_HB_EN); | |
411 | twl4030_write(w->codec, e->reg, hs_ctl); | |
412 | } | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
aad749e5 PU |
417 | static int headsetl_event(struct snd_soc_dapm_widget *w, |
418 | struct snd_kcontrol *kcontrol, int event) | |
419 | { | |
420 | unsigned char hs_gain, hs_pop; | |
421 | ||
422 | /* Save the current volume */ | |
423 | hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET); | |
424 | ||
425 | switch (event) { | |
426 | case SND_SOC_DAPM_POST_PMU: | |
427 | /* Do the anti-pop/bias ramp enable according to the TRM */ | |
428 | hs_pop = TWL4030_RAMP_DELAY_645MS; | |
429 | twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
430 | hs_pop |= TWL4030_VMID_EN; | |
431 | twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
432 | /* Is this needed? Can we just use whatever gain here? */ | |
433 | twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, | |
434 | (hs_gain & (~0x0f)) | 0x0a); | |
435 | hs_pop |= TWL4030_RAMP_EN; | |
436 | twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
437 | ||
438 | /* Restore the original volume */ | |
439 | twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain); | |
440 | break; | |
441 | case SND_SOC_DAPM_POST_PMD: | |
442 | /* Do the anti-pop/bias ramp disable according to the TRM */ | |
443 | hs_pop = twl4030_read_reg_cache(w->codec, | |
444 | TWL4030_REG_HS_POPN_SET); | |
445 | hs_pop &= ~TWL4030_RAMP_EN; | |
446 | twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
447 | /* Bypass the reg_cache to mute the headset */ | |
448 | twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
449 | hs_gain & (~0x0f), | |
450 | TWL4030_REG_HS_GAIN_SET); | |
451 | hs_pop &= ~TWL4030_VMID_EN; | |
452 | twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
453 | break; | |
454 | } | |
455 | return 0; | |
456 | } | |
457 | ||
b0bd53a7 PU |
458 | /* |
459 | * Some of the gain controls in TWL (mostly those which are associated with | |
460 | * the outputs) are implemented in an interesting way: | |
461 | * 0x0 : Power down (mute) | |
462 | * 0x1 : 6dB | |
463 | * 0x2 : 0 dB | |
464 | * 0x3 : -6 dB | |
465 | * Inverting not going to help with these. | |
466 | * Custom volsw and volsw_2r get/put functions to handle these gain bits. | |
467 | */ | |
468 | #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\ | |
469 | xinvert, tlv_array) \ | |
470 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
471 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
472 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
473 | .tlv.p = (tlv_array), \ | |
474 | .info = snd_soc_info_volsw, \ | |
475 | .get = snd_soc_get_volsw_twl4030, \ | |
476 | .put = snd_soc_put_volsw_twl4030, \ | |
477 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
478 | {.reg = xreg, .shift = shift_left, .rshift = shift_right,\ | |
479 | .max = xmax, .invert = xinvert} } | |
480 | #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\ | |
481 | xinvert, tlv_array) \ | |
482 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
483 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
484 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
485 | .tlv.p = (tlv_array), \ | |
486 | .info = snd_soc_info_volsw_2r, \ | |
487 | .get = snd_soc_get_volsw_r2_twl4030,\ | |
488 | .put = snd_soc_put_volsw_r2_twl4030, \ | |
489 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
490 | {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ | |
64089b84 | 491 | .rshift = xshift, .max = xmax, .invert = xinvert} } |
b0bd53a7 PU |
492 | #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \ |
493 | SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \ | |
494 | xinvert, tlv_array) | |
495 | ||
496 | static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
497 | struct snd_ctl_elem_value *ucontrol) | |
498 | { | |
499 | struct soc_mixer_control *mc = | |
500 | (struct soc_mixer_control *)kcontrol->private_value; | |
501 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
502 | unsigned int reg = mc->reg; | |
503 | unsigned int shift = mc->shift; | |
504 | unsigned int rshift = mc->rshift; | |
505 | int max = mc->max; | |
506 | int mask = (1 << fls(max)) - 1; | |
507 | ||
508 | ucontrol->value.integer.value[0] = | |
509 | (snd_soc_read(codec, reg) >> shift) & mask; | |
510 | if (ucontrol->value.integer.value[0]) | |
511 | ucontrol->value.integer.value[0] = | |
512 | max + 1 - ucontrol->value.integer.value[0]; | |
513 | ||
514 | if (shift != rshift) { | |
515 | ucontrol->value.integer.value[1] = | |
516 | (snd_soc_read(codec, reg) >> rshift) & mask; | |
517 | if (ucontrol->value.integer.value[1]) | |
518 | ucontrol->value.integer.value[1] = | |
519 | max + 1 - ucontrol->value.integer.value[1]; | |
520 | } | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
526 | struct snd_ctl_elem_value *ucontrol) | |
527 | { | |
528 | struct soc_mixer_control *mc = | |
529 | (struct soc_mixer_control *)kcontrol->private_value; | |
530 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
531 | unsigned int reg = mc->reg; | |
532 | unsigned int shift = mc->shift; | |
533 | unsigned int rshift = mc->rshift; | |
534 | int max = mc->max; | |
535 | int mask = (1 << fls(max)) - 1; | |
536 | unsigned short val, val2, val_mask; | |
537 | ||
538 | val = (ucontrol->value.integer.value[0] & mask); | |
539 | ||
540 | val_mask = mask << shift; | |
541 | if (val) | |
542 | val = max + 1 - val; | |
543 | val = val << shift; | |
544 | if (shift != rshift) { | |
545 | val2 = (ucontrol->value.integer.value[1] & mask); | |
546 | val_mask |= mask << rshift; | |
547 | if (val2) | |
548 | val2 = max + 1 - val2; | |
549 | val |= val2 << rshift; | |
550 | } | |
551 | return snd_soc_update_bits(codec, reg, val_mask, val); | |
552 | } | |
553 | ||
554 | static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
555 | struct snd_ctl_elem_value *ucontrol) | |
556 | { | |
557 | struct soc_mixer_control *mc = | |
558 | (struct soc_mixer_control *)kcontrol->private_value; | |
559 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
560 | unsigned int reg = mc->reg; | |
561 | unsigned int reg2 = mc->rreg; | |
562 | unsigned int shift = mc->shift; | |
563 | int max = mc->max; | |
564 | int mask = (1<<fls(max))-1; | |
565 | ||
566 | ucontrol->value.integer.value[0] = | |
567 | (snd_soc_read(codec, reg) >> shift) & mask; | |
568 | ucontrol->value.integer.value[1] = | |
569 | (snd_soc_read(codec, reg2) >> shift) & mask; | |
570 | ||
571 | if (ucontrol->value.integer.value[0]) | |
572 | ucontrol->value.integer.value[0] = | |
573 | max + 1 - ucontrol->value.integer.value[0]; | |
574 | if (ucontrol->value.integer.value[1]) | |
575 | ucontrol->value.integer.value[1] = | |
576 | max + 1 - ucontrol->value.integer.value[1]; | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
581 | static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
582 | struct snd_ctl_elem_value *ucontrol) | |
583 | { | |
584 | struct soc_mixer_control *mc = | |
585 | (struct soc_mixer_control *)kcontrol->private_value; | |
586 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
587 | unsigned int reg = mc->reg; | |
588 | unsigned int reg2 = mc->rreg; | |
589 | unsigned int shift = mc->shift; | |
590 | int max = mc->max; | |
591 | int mask = (1 << fls(max)) - 1; | |
592 | int err; | |
593 | unsigned short val, val2, val_mask; | |
594 | ||
595 | val_mask = mask << shift; | |
596 | val = (ucontrol->value.integer.value[0] & mask); | |
597 | val2 = (ucontrol->value.integer.value[1] & mask); | |
598 | ||
599 | if (val) | |
600 | val = max + 1 - val; | |
601 | if (val2) | |
602 | val2 = max + 1 - val2; | |
603 | ||
604 | val = val << shift; | |
605 | val2 = val2 << shift; | |
606 | ||
607 | err = snd_soc_update_bits(codec, reg, val_mask, val); | |
608 | if (err < 0) | |
609 | return err; | |
610 | ||
611 | err = snd_soc_update_bits(codec, reg2, val_mask, val2); | |
612 | return err; | |
613 | } | |
614 | ||
c10b82cf PU |
615 | /* |
616 | * FGAIN volume control: | |
617 | * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) | |
618 | */ | |
d889a72c | 619 | static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1); |
c10b82cf | 620 | |
0d33ea0b PU |
621 | /* |
622 | * CGAIN volume control: | |
623 | * 0 dB to 12 dB in 6 dB steps | |
624 | * value 2 and 3 means 12 dB | |
625 | */ | |
d889a72c PU |
626 | static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); |
627 | ||
628 | /* | |
629 | * Analog playback gain | |
630 | * -24 dB to 12 dB in 2 dB steps | |
631 | */ | |
632 | static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0); | |
0d33ea0b | 633 | |
4290239c PU |
634 | /* |
635 | * Gain controls tied to outputs | |
636 | * -6 dB to 6 dB in 6 dB steps (mute instead of -12) | |
637 | */ | |
638 | static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1); | |
639 | ||
381a22b5 PU |
640 | /* |
641 | * Capture gain after the ADCs | |
642 | * from 0 dB to 31 dB in 1 dB steps | |
643 | */ | |
644 | static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0); | |
645 | ||
5920b453 GI |
646 | /* |
647 | * Gain control for input amplifiers | |
648 | * 0 dB to 30 dB in 6 dB steps | |
649 | */ | |
650 | static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0); | |
651 | ||
cc17557e | 652 | static const struct snd_kcontrol_new twl4030_snd_controls[] = { |
d889a72c PU |
653 | /* Common playback gain controls */ |
654 | SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", | |
655 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
656 | 0, 0x3f, 0, digital_fine_tlv), | |
657 | SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume", | |
658 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
659 | 0, 0x3f, 0, digital_fine_tlv), | |
660 | ||
661 | SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume", | |
662 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
663 | 6, 0x2, 0, digital_coarse_tlv), | |
664 | SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume", | |
665 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
666 | 6, 0x2, 0, digital_coarse_tlv), | |
667 | ||
668 | SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume", | |
669 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
670 | 3, 0x12, 1, analog_tlv), | |
671 | SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume", | |
672 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
673 | 3, 0x12, 1, analog_tlv), | |
44c55870 PU |
674 | SOC_DOUBLE_R("DAC1 Analog Playback Switch", |
675 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
676 | 1, 1, 0), | |
677 | SOC_DOUBLE_R("DAC2 Analog Playback Switch", | |
678 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
679 | 1, 1, 0), | |
381a22b5 | 680 | |
4290239c PU |
681 | /* Separate output gain controls */ |
682 | SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume", | |
683 | TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, | |
684 | 4, 3, 0, output_tvl), | |
685 | ||
686 | SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume", | |
687 | TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl), | |
688 | ||
689 | SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume", | |
690 | TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL, | |
691 | 4, 3, 0, output_tvl), | |
692 | ||
693 | SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume", | |
694 | TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl), | |
695 | ||
381a22b5 | 696 | /* Common capture gain controls */ |
276c6222 | 697 | SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume", |
381a22b5 PU |
698 | TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, |
699 | 0, 0x1f, 0, digital_capture_tlv), | |
276c6222 PU |
700 | SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume", |
701 | TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA, | |
702 | 0, 0x1f, 0, digital_capture_tlv), | |
5920b453 | 703 | |
276c6222 | 704 | SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN, |
5920b453 | 705 | 0, 3, 5, 0, input_gain_tlv), |
cc17557e SS |
706 | }; |
707 | ||
cc17557e | 708 | static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { |
276c6222 PU |
709 | /* Left channel inputs */ |
710 | SND_SOC_DAPM_INPUT("MAINMIC"), | |
711 | SND_SOC_DAPM_INPUT("HSMIC"), | |
712 | SND_SOC_DAPM_INPUT("AUXL"), | |
713 | SND_SOC_DAPM_INPUT("CARKITMIC"), | |
714 | /* Right channel inputs */ | |
715 | SND_SOC_DAPM_INPUT("SUBMIC"), | |
716 | SND_SOC_DAPM_INPUT("AUXR"), | |
717 | /* Digital microphones (Stereo) */ | |
718 | SND_SOC_DAPM_INPUT("DIGIMIC0"), | |
719 | SND_SOC_DAPM_INPUT("DIGIMIC1"), | |
720 | ||
721 | /* Outputs */ | |
cc17557e SS |
722 | SND_SOC_DAPM_OUTPUT("OUTL"), |
723 | SND_SOC_DAPM_OUTPUT("OUTR"), | |
5e98a464 | 724 | SND_SOC_DAPM_OUTPUT("EARPIECE"), |
2a6f5c58 PU |
725 | SND_SOC_DAPM_OUTPUT("PREDRIVEL"), |
726 | SND_SOC_DAPM_OUTPUT("PREDRIVER"), | |
dfad21a2 PU |
727 | SND_SOC_DAPM_OUTPUT("HSOL"), |
728 | SND_SOC_DAPM_OUTPUT("HSOR"), | |
6a1bee4a PU |
729 | SND_SOC_DAPM_OUTPUT("CARKITL"), |
730 | SND_SOC_DAPM_OUTPUT("CARKITR"), | |
df339804 PU |
731 | SND_SOC_DAPM_OUTPUT("HFL"), |
732 | SND_SOC_DAPM_OUTPUT("HFR"), | |
cc17557e | 733 | |
53b5047d | 734 | /* DACs */ |
1e5fa31f | 735 | SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback", |
53b5047d | 736 | TWL4030_REG_AVDAC_CTL, 0, 0), |
1e5fa31f | 737 | SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback", |
53b5047d | 738 | TWL4030_REG_AVDAC_CTL, 1, 0), |
1e5fa31f | 739 | SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback", |
53b5047d | 740 | TWL4030_REG_AVDAC_CTL, 2, 0), |
1e5fa31f | 741 | SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback", |
53b5047d | 742 | TWL4030_REG_AVDAC_CTL, 3, 0), |
cc17557e | 743 | |
44c55870 PU |
744 | /* Analog PGAs */ |
745 | SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL, | |
746 | 0, 0, NULL, 0), | |
747 | SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL, | |
748 | 0, 0, NULL, 0), | |
749 | SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL, | |
750 | 0, 0, NULL, 0), | |
751 | SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL, | |
752 | 0, 0, NULL, 0), | |
753 | ||
5e98a464 PU |
754 | /* Output MUX controls */ |
755 | /* Earpiece */ | |
2f423577 PU |
756 | SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0, |
757 | &twl4030_dapm_earpiece_control), | |
2a6f5c58 | 758 | /* PreDrivL/R */ |
2f423577 PU |
759 | SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0, |
760 | &twl4030_dapm_predrivel_control), | |
761 | SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0, | |
762 | &twl4030_dapm_predriver_control), | |
dfad21a2 | 763 | /* HeadsetL/R */ |
aad749e5 PU |
764 | SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0, |
765 | &twl4030_dapm_hsol_control, headsetl_event, | |
766 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
dfad21a2 PU |
767 | SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0, |
768 | &twl4030_dapm_hsor_control), | |
5152d8c2 PU |
769 | /* CarkitL/R */ |
770 | SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0, | |
771 | &twl4030_dapm_carkitl_control), | |
772 | SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0, | |
773 | &twl4030_dapm_carkitr_control), | |
df339804 | 774 | /* HandsfreeL/R */ |
49d92c7d SM |
775 | SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0, |
776 | &twl4030_dapm_handsfreel_control, handsfree_event, | |
777 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
778 | SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0, | |
779 | &twl4030_dapm_handsfreer_control, handsfree_event, | |
780 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
5e98a464 | 781 | |
276c6222 PU |
782 | /* Introducing four virtual ADC, since TWL4030 have four channel for |
783 | capture */ | |
784 | SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture", | |
785 | SND_SOC_NOPM, 0, 0), | |
786 | SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture", | |
787 | SND_SOC_NOPM, 0, 0), | |
788 | SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture", | |
789 | SND_SOC_NOPM, 0, 0), | |
790 | SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture", | |
791 | SND_SOC_NOPM, 0, 0), | |
792 | ||
793 | /* Analog/Digital mic path selection. | |
794 | TX1 Left/Right: either analog Left/Right or Digimic0 | |
795 | TX2 Left/Right: either analog Left/Right or Digimic1 */ | |
796 | SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0, | |
797 | &twl4030_dapm_micpathtx1_control, micpath_event, | |
798 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
799 | SND_SOC_DAPM_POST_REG), | |
800 | SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0, | |
801 | &twl4030_dapm_micpathtx2_control, micpath_event, | |
802 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
803 | SND_SOC_DAPM_POST_REG), | |
804 | ||
805 | /* Analog input muxes with power switch for the physical ADCL/R */ | |
2f423577 PU |
806 | SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route", |
807 | TWL4030_REG_AVADC_CTL, 3, 0, &twl4030_dapm_analoglmic_control), | |
808 | SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route", | |
809 | TWL4030_REG_AVADC_CTL, 1, 0, &twl4030_dapm_analogrmic_control), | |
276c6222 PU |
810 | |
811 | SND_SOC_DAPM_PGA("Analog Left Amplifier", | |
812 | TWL4030_REG_ANAMICL, 4, 0, NULL, 0), | |
813 | SND_SOC_DAPM_PGA("Analog Right Amplifier", | |
814 | TWL4030_REG_ANAMICR, 4, 0, NULL, 0), | |
815 | ||
816 | SND_SOC_DAPM_PGA("Digimic0 Enable", | |
817 | TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0), | |
818 | SND_SOC_DAPM_PGA("Digimic1 Enable", | |
819 | TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0), | |
820 | ||
821 | SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0), | |
822 | SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0), | |
823 | SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0), | |
cc17557e SS |
824 | }; |
825 | ||
826 | static const struct snd_soc_dapm_route intercon[] = { | |
1e5fa31f PU |
827 | {"ARXL1_APGA", NULL, "DAC Left1"}, |
828 | {"ARXR1_APGA", NULL, "DAC Right1"}, | |
829 | {"ARXL2_APGA", NULL, "DAC Left2"}, | |
830 | {"ARXR2_APGA", NULL, "DAC Right2"}, | |
44c55870 | 831 | |
5e98a464 PU |
832 | /* Internal playback routings */ |
833 | /* Earpiece */ | |
834 | {"Earpiece Mux", "DACL1", "ARXL1_APGA"}, | |
835 | {"Earpiece Mux", "DACL2", "ARXL2_APGA"}, | |
836 | {"Earpiece Mux", "DACR1", "ARXR1_APGA"}, | |
2a6f5c58 PU |
837 | /* PreDrivL */ |
838 | {"PredriveL Mux", "DACL1", "ARXL1_APGA"}, | |
839 | {"PredriveL Mux", "DACL2", "ARXL2_APGA"}, | |
840 | {"PredriveL Mux", "DACR2", "ARXR2_APGA"}, | |
841 | /* PreDrivR */ | |
842 | {"PredriveR Mux", "DACR1", "ARXR1_APGA"}, | |
843 | {"PredriveR Mux", "DACR2", "ARXR2_APGA"}, | |
844 | {"PredriveR Mux", "DACL2", "ARXL2_APGA"}, | |
dfad21a2 PU |
845 | /* HeadsetL */ |
846 | {"HeadsetL Mux", "DACL1", "ARXL1_APGA"}, | |
847 | {"HeadsetL Mux", "DACL2", "ARXL2_APGA"}, | |
848 | /* HeadsetR */ | |
849 | {"HeadsetR Mux", "DACR1", "ARXR1_APGA"}, | |
850 | {"HeadsetR Mux", "DACR2", "ARXR2_APGA"}, | |
5152d8c2 PU |
851 | /* CarkitL */ |
852 | {"CarkitL Mux", "DACL1", "ARXL1_APGA"}, | |
853 | {"CarkitL Mux", "DACL2", "ARXL2_APGA"}, | |
854 | /* CarkitR */ | |
855 | {"CarkitR Mux", "DACR1", "ARXR1_APGA"}, | |
856 | {"CarkitR Mux", "DACR2", "ARXR2_APGA"}, | |
df339804 PU |
857 | /* HandsfreeL */ |
858 | {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"}, | |
859 | {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"}, | |
860 | {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"}, | |
861 | /* HandsfreeR */ | |
862 | {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"}, | |
863 | {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"}, | |
864 | {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"}, | |
5e98a464 | 865 | |
cc17557e | 866 | /* outputs */ |
44c55870 PU |
867 | {"OUTL", NULL, "ARXL2_APGA"}, |
868 | {"OUTR", NULL, "ARXR2_APGA"}, | |
5e98a464 | 869 | {"EARPIECE", NULL, "Earpiece Mux"}, |
2a6f5c58 PU |
870 | {"PREDRIVEL", NULL, "PredriveL Mux"}, |
871 | {"PREDRIVER", NULL, "PredriveR Mux"}, | |
dfad21a2 PU |
872 | {"HSOL", NULL, "HeadsetL Mux"}, |
873 | {"HSOR", NULL, "HeadsetR Mux"}, | |
5152d8c2 PU |
874 | {"CARKITL", NULL, "CarkitL Mux"}, |
875 | {"CARKITR", NULL, "CarkitR Mux"}, | |
df339804 PU |
876 | {"HFL", NULL, "HandsfreeL Mux"}, |
877 | {"HFR", NULL, "HandsfreeR Mux"}, | |
cc17557e | 878 | |
276c6222 PU |
879 | /* Capture path */ |
880 | {"Analog Left Capture Route", "Main mic", "MAINMIC"}, | |
881 | {"Analog Left Capture Route", "Headset mic", "HSMIC"}, | |
882 | {"Analog Left Capture Route", "AUXL", "AUXL"}, | |
883 | {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"}, | |
884 | ||
885 | {"Analog Right Capture Route", "Sub mic", "SUBMIC"}, | |
886 | {"Analog Right Capture Route", "AUXR", "AUXR"}, | |
887 | ||
888 | {"Analog Left Amplifier", NULL, "Analog Left Capture Route"}, | |
889 | {"Analog Right Amplifier", NULL, "Analog Right Capture Route"}, | |
890 | ||
891 | {"Digimic0 Enable", NULL, "DIGIMIC0"}, | |
892 | {"Digimic1 Enable", NULL, "DIGIMIC1"}, | |
893 | ||
894 | /* TX1 Left capture path */ | |
895 | {"TX1 Capture Route", "Analog", "Analog Left Amplifier"}, | |
896 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, | |
897 | /* TX1 Right capture path */ | |
898 | {"TX1 Capture Route", "Analog", "Analog Right Amplifier"}, | |
899 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, | |
900 | /* TX2 Left capture path */ | |
901 | {"TX2 Capture Route", "Analog", "Analog Left Amplifier"}, | |
902 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, | |
903 | /* TX2 Right capture path */ | |
904 | {"TX2 Capture Route", "Analog", "Analog Right Amplifier"}, | |
905 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, | |
906 | ||
907 | {"ADC Virtual Left1", NULL, "TX1 Capture Route"}, | |
908 | {"ADC Virtual Right1", NULL, "TX1 Capture Route"}, | |
909 | {"ADC Virtual Left2", NULL, "TX2 Capture Route"}, | |
910 | {"ADC Virtual Right2", NULL, "TX2 Capture Route"}, | |
911 | ||
cc17557e SS |
912 | }; |
913 | ||
914 | static int twl4030_add_widgets(struct snd_soc_codec *codec) | |
915 | { | |
916 | snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, | |
917 | ARRAY_SIZE(twl4030_dapm_widgets)); | |
918 | ||
919 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); | |
920 | ||
921 | snd_soc_dapm_new_widgets(codec); | |
922 | return 0; | |
923 | } | |
924 | ||
925 | static void twl4030_power_up(struct snd_soc_codec *codec) | |
926 | { | |
aad749e5 | 927 | u8 anamicl, regmisc1, byte; |
cc17557e SS |
928 | int i = 0; |
929 | ||
930 | /* set CODECPDZ to turn on codec */ | |
db04e2c5 | 931 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
932 | |
933 | /* initiate offset cancellation */ | |
934 | anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL); | |
935 | twl4030_write(codec, TWL4030_REG_ANAMICL, | |
936 | anamicl | TWL4030_CNCL_OFFSET_START); | |
937 | ||
276c6222 | 938 | |
cc17557e SS |
939 | /* wait for offset cancellation to complete */ |
940 | do { | |
941 | /* this takes a little while, so don't slam i2c */ | |
942 | udelay(2000); | |
943 | twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, | |
944 | TWL4030_REG_ANAMICL); | |
945 | } while ((i++ < 100) && | |
946 | ((byte & TWL4030_CNCL_OFFSET_START) == | |
947 | TWL4030_CNCL_OFFSET_START)); | |
948 | ||
3fc93030 PU |
949 | /* Make sure that the reg_cache has the same value as the HW */ |
950 | twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte); | |
951 | ||
cc17557e SS |
952 | /* anti-pop when changing analog gain */ |
953 | regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); | |
954 | twl4030_write(codec, TWL4030_REG_MISC_SET_1, | |
955 | regmisc1 | TWL4030_SMOOTH_ANAVOL_EN); | |
956 | ||
957 | /* toggle CODECPDZ as per TRM */ | |
db04e2c5 PU |
958 | twl4030_codec_enable(codec, 0); |
959 | twl4030_codec_enable(codec, 1); | |
cc17557e SS |
960 | } |
961 | ||
962 | static void twl4030_power_down(struct snd_soc_codec *codec) | |
963 | { | |
cc17557e | 964 | /* power down */ |
db04e2c5 | 965 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
966 | } |
967 | ||
968 | static int twl4030_set_bias_level(struct snd_soc_codec *codec, | |
969 | enum snd_soc_bias_level level) | |
970 | { | |
971 | switch (level) { | |
972 | case SND_SOC_BIAS_ON: | |
973 | twl4030_power_up(codec); | |
974 | break; | |
975 | case SND_SOC_BIAS_PREPARE: | |
976 | /* TODO: develop a twl4030_prepare function */ | |
977 | break; | |
978 | case SND_SOC_BIAS_STANDBY: | |
979 | /* TODO: develop a twl4030_standby function */ | |
980 | twl4030_power_down(codec); | |
981 | break; | |
982 | case SND_SOC_BIAS_OFF: | |
983 | twl4030_power_down(codec); | |
984 | break; | |
985 | } | |
986 | codec->bias_level = level; | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | static int twl4030_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
992 | struct snd_pcm_hw_params *params, |
993 | struct snd_soc_dai *dai) | |
cc17557e SS |
994 | { |
995 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
996 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 997 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
998 | u8 mode, old_mode, format, old_format; |
999 | ||
1000 | ||
1001 | /* bit rate */ | |
1002 | old_mode = twl4030_read_reg_cache(codec, | |
1003 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
1004 | mode = old_mode & ~TWL4030_APLL_RATE; | |
1005 | ||
1006 | switch (params_rate(params)) { | |
1007 | case 8000: | |
1008 | mode |= TWL4030_APLL_RATE_8000; | |
1009 | break; | |
1010 | case 11025: | |
1011 | mode |= TWL4030_APLL_RATE_11025; | |
1012 | break; | |
1013 | case 12000: | |
1014 | mode |= TWL4030_APLL_RATE_12000; | |
1015 | break; | |
1016 | case 16000: | |
1017 | mode |= TWL4030_APLL_RATE_16000; | |
1018 | break; | |
1019 | case 22050: | |
1020 | mode |= TWL4030_APLL_RATE_22050; | |
1021 | break; | |
1022 | case 24000: | |
1023 | mode |= TWL4030_APLL_RATE_24000; | |
1024 | break; | |
1025 | case 32000: | |
1026 | mode |= TWL4030_APLL_RATE_32000; | |
1027 | break; | |
1028 | case 44100: | |
1029 | mode |= TWL4030_APLL_RATE_44100; | |
1030 | break; | |
1031 | case 48000: | |
1032 | mode |= TWL4030_APLL_RATE_48000; | |
1033 | break; | |
1034 | default: | |
1035 | printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", | |
1036 | params_rate(params)); | |
1037 | return -EINVAL; | |
1038 | } | |
1039 | ||
1040 | if (mode != old_mode) { | |
1041 | /* change rate and set CODECPDZ */ | |
1042 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
db04e2c5 | 1043 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1044 | } |
1045 | ||
1046 | /* sample size */ | |
1047 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1048 | format = old_format; | |
1049 | format &= ~TWL4030_DATA_WIDTH; | |
1050 | switch (params_format(params)) { | |
1051 | case SNDRV_PCM_FORMAT_S16_LE: | |
1052 | format |= TWL4030_DATA_WIDTH_16S_16W; | |
1053 | break; | |
1054 | case SNDRV_PCM_FORMAT_S24_LE: | |
1055 | format |= TWL4030_DATA_WIDTH_32S_24W; | |
1056 | break; | |
1057 | default: | |
1058 | printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", | |
1059 | params_format(params)); | |
1060 | return -EINVAL; | |
1061 | } | |
1062 | ||
1063 | if (format != old_format) { | |
1064 | ||
1065 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1066 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1067 | |
1068 | /* change format */ | |
1069 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1070 | ||
1071 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1072 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1073 | } |
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1078 | int clk_id, unsigned int freq, int dir) | |
1079 | { | |
1080 | struct snd_soc_codec *codec = codec_dai->codec; | |
1081 | u8 infreq; | |
1082 | ||
1083 | switch (freq) { | |
1084 | case 19200000: | |
1085 | infreq = TWL4030_APLL_INFREQ_19200KHZ; | |
1086 | break; | |
1087 | case 26000000: | |
1088 | infreq = TWL4030_APLL_INFREQ_26000KHZ; | |
1089 | break; | |
1090 | case 38400000: | |
1091 | infreq = TWL4030_APLL_INFREQ_38400KHZ; | |
1092 | break; | |
1093 | default: | |
1094 | printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n", | |
1095 | freq); | |
1096 | return -EINVAL; | |
1097 | } | |
1098 | ||
1099 | infreq |= TWL4030_APLL_EN; | |
1100 | twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq); | |
1101 | ||
1102 | return 0; | |
1103 | } | |
1104 | ||
1105 | static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1106 | unsigned int fmt) | |
1107 | { | |
1108 | struct snd_soc_codec *codec = codec_dai->codec; | |
1109 | u8 old_format, format; | |
1110 | ||
1111 | /* get format */ | |
1112 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1113 | format = old_format; | |
1114 | ||
1115 | /* set master/slave audio interface */ | |
1116 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1117 | case SND_SOC_DAIFMT_CBM_CFM: | |
1118 | format &= ~(TWL4030_AIF_SLAVE_EN); | |
e18c94d2 | 1119 | format &= ~(TWL4030_CLK256FS_EN); |
cc17557e SS |
1120 | break; |
1121 | case SND_SOC_DAIFMT_CBS_CFS: | |
cc17557e | 1122 | format |= TWL4030_AIF_SLAVE_EN; |
e18c94d2 | 1123 | format |= TWL4030_CLK256FS_EN; |
cc17557e SS |
1124 | break; |
1125 | default: | |
1126 | return -EINVAL; | |
1127 | } | |
1128 | ||
1129 | /* interface format */ | |
1130 | format &= ~TWL4030_AIF_FORMAT; | |
1131 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1132 | case SND_SOC_DAIFMT_I2S: | |
1133 | format |= TWL4030_AIF_FORMAT_CODEC; | |
1134 | break; | |
1135 | default: | |
1136 | return -EINVAL; | |
1137 | } | |
1138 | ||
1139 | if (format != old_format) { | |
1140 | ||
1141 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1142 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1143 | |
1144 | /* change format */ | |
1145 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1146 | ||
1147 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1148 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1149 | } |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
bbba9444 | 1154 | #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) |
cc17557e SS |
1155 | #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) |
1156 | ||
1157 | struct snd_soc_dai twl4030_dai = { | |
1158 | .name = "twl4030", | |
1159 | .playback = { | |
1160 | .stream_name = "Playback", | |
1161 | .channels_min = 2, | |
1162 | .channels_max = 2, | |
1163 | .rates = TWL4030_RATES, | |
1164 | .formats = TWL4030_FORMATS,}, | |
1165 | .capture = { | |
1166 | .stream_name = "Capture", | |
1167 | .channels_min = 2, | |
1168 | .channels_max = 2, | |
1169 | .rates = TWL4030_RATES, | |
1170 | .formats = TWL4030_FORMATS,}, | |
1171 | .ops = { | |
1172 | .hw_params = twl4030_hw_params, | |
cc17557e SS |
1173 | .set_sysclk = twl4030_set_dai_sysclk, |
1174 | .set_fmt = twl4030_set_dai_fmt, | |
1175 | } | |
1176 | }; | |
1177 | EXPORT_SYMBOL_GPL(twl4030_dai); | |
1178 | ||
1179 | static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) | |
1180 | { | |
1181 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1182 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
1183 | |
1184 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | static int twl4030_resume(struct platform_device *pdev) | |
1190 | { | |
1191 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1192 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
1193 | |
1194 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1195 | twl4030_set_bias_level(codec, codec->suspend_bias_level); | |
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | /* | |
1200 | * initialize the driver | |
1201 | * register the mixer and dsp interfaces with the kernel | |
1202 | */ | |
1203 | ||
1204 | static int twl4030_init(struct snd_soc_device *socdev) | |
1205 | { | |
6627a653 | 1206 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
1207 | int ret = 0; |
1208 | ||
1209 | printk(KERN_INFO "TWL4030 Audio Codec init \n"); | |
1210 | ||
1211 | codec->name = "twl4030"; | |
1212 | codec->owner = THIS_MODULE; | |
1213 | codec->read = twl4030_read_reg_cache; | |
1214 | codec->write = twl4030_write; | |
1215 | codec->set_bias_level = twl4030_set_bias_level; | |
1216 | codec->dai = &twl4030_dai; | |
1217 | codec->num_dai = 1; | |
1218 | codec->reg_cache_size = sizeof(twl4030_reg); | |
1219 | codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), | |
1220 | GFP_KERNEL); | |
1221 | if (codec->reg_cache == NULL) | |
1222 | return -ENOMEM; | |
1223 | ||
1224 | /* register pcms */ | |
1225 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
1226 | if (ret < 0) { | |
1227 | printk(KERN_ERR "twl4030: failed to create pcms\n"); | |
1228 | goto pcm_err; | |
1229 | } | |
1230 | ||
1231 | twl4030_init_chip(codec); | |
1232 | ||
1233 | /* power on device */ | |
1234 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1235 | ||
3e8e1952 IM |
1236 | snd_soc_add_controls(codec, twl4030_snd_controls, |
1237 | ARRAY_SIZE(twl4030_snd_controls)); | |
cc17557e SS |
1238 | twl4030_add_widgets(codec); |
1239 | ||
968a6025 | 1240 | ret = snd_soc_init_card(socdev); |
cc17557e SS |
1241 | if (ret < 0) { |
1242 | printk(KERN_ERR "twl4030: failed to register card\n"); | |
1243 | goto card_err; | |
1244 | } | |
1245 | ||
1246 | return ret; | |
1247 | ||
1248 | card_err: | |
1249 | snd_soc_free_pcms(socdev); | |
1250 | snd_soc_dapm_free(socdev); | |
1251 | pcm_err: | |
1252 | kfree(codec->reg_cache); | |
1253 | return ret; | |
1254 | } | |
1255 | ||
1256 | static struct snd_soc_device *twl4030_socdev; | |
1257 | ||
1258 | static int twl4030_probe(struct platform_device *pdev) | |
1259 | { | |
1260 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1261 | struct snd_soc_codec *codec; | |
1262 | ||
1263 | codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); | |
1264 | if (codec == NULL) | |
1265 | return -ENOMEM; | |
1266 | ||
6627a653 | 1267 | socdev->card->codec = codec; |
cc17557e SS |
1268 | mutex_init(&codec->mutex); |
1269 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
1270 | INIT_LIST_HEAD(&codec->dapm_paths); | |
1271 | ||
1272 | twl4030_socdev = socdev; | |
1273 | twl4030_init(socdev); | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | static int twl4030_remove(struct platform_device *pdev) | |
1279 | { | |
1280 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1281 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
1282 | |
1283 | printk(KERN_INFO "TWL4030 Audio Codec remove\n"); | |
c6d1662b PU |
1284 | snd_soc_free_pcms(socdev); |
1285 | snd_soc_dapm_free(socdev); | |
cc17557e SS |
1286 | kfree(codec); |
1287 | ||
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | struct snd_soc_codec_device soc_codec_dev_twl4030 = { | |
1292 | .probe = twl4030_probe, | |
1293 | .remove = twl4030_remove, | |
1294 | .suspend = twl4030_suspend, | |
1295 | .resume = twl4030_resume, | |
1296 | }; | |
1297 | EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); | |
1298 | ||
24e07db8 | 1299 | static int __init twl4030_modinit(void) |
64089b84 MB |
1300 | { |
1301 | return snd_soc_register_dai(&twl4030_dai); | |
1302 | } | |
24e07db8 | 1303 | module_init(twl4030_modinit); |
64089b84 MB |
1304 | |
1305 | static void __exit twl4030_exit(void) | |
1306 | { | |
1307 | snd_soc_unregister_dai(&twl4030_dai); | |
1308 | } | |
1309 | module_exit(twl4030_exit); | |
1310 | ||
cc17557e SS |
1311 | MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); |
1312 | MODULE_AUTHOR("Steve Sakoman"); | |
1313 | MODULE_LICENSE("GPL"); |