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ASoC: TWL4030: Add shadow register
[mirror_ubuntu-jammy-kernel.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
123 unsigned int bypass_state;
124 unsigned int codec_powered;
125 unsigned int codec_muted;
7220b9f4
PU		 126
127 struct snd_pcm_substream *master_substream;
128 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 129
130 unsigned int configured;
131 unsigned int rate;
132 unsigned int sample_bits;
133 unsigned int channels;
6943c92e
PU		 134
135 unsigned int sysclk;
136
137 /* Headset output state handling */
138 unsigned int hsl_enabled;
139 unsigned int hsr_enabled;
7393958f
PU		 140};
141
cc17557e
SS		 142/*
143 * read twl4030 register cache
144 */
145static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
146 unsigned int reg)
147{
148 u8 *cache = codec->reg_cache;
149
91432e97
IM		 150 if (reg >= TWL4030_CACHEREGNUM)
151 return -EIO;
152
cc17557e
SS		 153 return cache[reg];
154}
155
156/*
157 * write twl4030 register cache
158 */
159static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
160 u8 reg, u8 value)
161{
162 u8 *cache = codec->reg_cache;
163
164 if (reg >= TWL4030_CACHEREGNUM)
165 return;
166 cache[reg] = value;
167}
168
169/*
170 * write to the twl4030 register space
171 */
172static int twl4030_write(struct snd_soc_codec *codec,
173 unsigned int reg, unsigned int value)
174{
175 twl4030_write_reg_cache(codec, reg, value);
f3b5d300
PU		 176 if (likely(reg < TWL4030_REG_SW_SHADOW))
177 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
178 reg);
179 else
180 return 0;
cc17557e
SS		 181}
182
db04e2c5 183static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 184{
7393958f 185 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 186 u8 mode;
187
7393958f
PU		 188 if (enable == twl4030->codec_powered)
189 return;
190
cc17557e 191 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 192 if (enable)
193 mode |= TWL4030_CODECPDZ;
194 else
195 mode &= ~TWL4030_CODECPDZ;
cc17557e 196
db04e2c5 197 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 198 twl4030->codec_powered = enable;
cc17557e
SS		 199
200 /* REVISIT: this delay is present in TI sample drivers */
201 /* but there seems to be no TRM requirement for it */
202 udelay(10);
203}
204
205static void twl4030_init_chip(struct snd_soc_codec *codec)
206{
207 int i;
208
209 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 210 twl4030_codec_enable(codec, 0);
cc17557e
SS		 211
212 /* set all audio section registers to reasonable defaults */
213 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
214 twl4030_write(codec, i, twl4030_reg[i]);
215
216}
217
7393958f
PU		 218static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
219{
220 struct twl4030_priv *twl4030 = codec->private_data;
221 u8 reg_val;
222
223 if (mute == twl4030->codec_muted)
224 return;
225
226 if (mute) {
227 /* Bypass the reg_cache and mute the volumes
228 * Headset mute is done in it's own event handler
229 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
230 */
231 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
232 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
233 reg_val & (~TWL4030_EAR_GAIN),
234 TWL4030_REG_EAR_CTL);
235
236 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
237 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
238 reg_val & (~TWL4030_PREDL_GAIN),
239 TWL4030_REG_PREDL_CTL);
240 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
241 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
242 reg_val & (~TWL4030_PREDR_GAIN),
243 TWL4030_REG_PREDL_CTL);
244
245 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
246 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
247 reg_val & (~TWL4030_PRECKL_GAIN),
248 TWL4030_REG_PRECKL_CTL);
249 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
250 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
c198d811 251 reg_val & (~TWL4030_PRECKR_GAIN),
7393958f
PU		 252 TWL4030_REG_PRECKR_CTL);
253
254 /* Disable PLL */
255 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
256 reg_val &= ~TWL4030_APLL_EN;
257 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
258 } else {
259 /* Restore the volumes
260 * Headset mute is done in it's own event handler
261 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
262 */
263 twl4030_write(codec, TWL4030_REG_EAR_CTL,
264 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
265
266 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
267 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
268 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
269 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
270
271 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
272 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
273 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
274 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
275
276 /* Enable PLL */
277 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
278 reg_val |= TWL4030_APLL_EN;
279 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
280 }
281
282 twl4030->codec_muted = mute;
283}
284
006f367e
PU		 285static void twl4030_power_up(struct snd_soc_codec *codec)
286{
7393958f 287 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 288 u8 anamicl, regmisc1, byte;
289 int i = 0;
290
7393958f
PU		 291 if (twl4030->codec_powered)
292 return;
293
006f367e
PU		 294 /* set CODECPDZ to turn on codec */
295 twl4030_codec_enable(codec, 1);
296
297 /* initiate offset cancellation */
298 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
299 twl4030_write(codec, TWL4030_REG_ANAMICL,
300 anamicl | TWL4030_CNCL_OFFSET_START);
301
302 /* wait for offset cancellation to complete */
303 do {
304 /* this takes a little while, so don't slam i2c */
305 udelay(2000);
306 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
307 TWL4030_REG_ANAMICL);
308 } while ((i++ < 100) &&
309 ((byte & TWL4030_CNCL_OFFSET_START) ==
310 TWL4030_CNCL_OFFSET_START));
311
312 /* Make sure that the reg_cache has the same value as the HW */
313 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
314
315 /* anti-pop when changing analog gain */
316 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
317 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
318 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
319
320 /* toggle CODECPDZ as per TRM */
321 twl4030_codec_enable(codec, 0);
322 twl4030_codec_enable(codec, 1);
323}
324
7393958f
PU		 325/*
326 * Unconditional power down
327 */
006f367e
PU		 328static void twl4030_power_down(struct snd_soc_codec *codec)
329{
330 /* power down */
331 twl4030_codec_enable(codec, 0);
332}
333
5e98a464 334/* Earpiece */
1a787e7a
JS		 335static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
336 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
337 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
338 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
339 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
340};
5e98a464 341
2a6f5c58 342/* PreDrive Left */
1a787e7a
JS		 343static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
344 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
345 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
346 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
347 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
348};
2a6f5c58
PU		 349
350/* PreDrive Right */
1a787e7a
JS		 351static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
352 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
353 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
354 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
355 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
356};
2a6f5c58 357
dfad21a2 358/* Headset Left */
1a787e7a
JS		 359static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
360 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
361 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
362 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
363};
dfad21a2
PU		 364
365/* Headset Right */
1a787e7a
JS		 366static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
367 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
368 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
369 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
370};
dfad21a2 371
5152d8c2 372/* Carkit Left */
1a787e7a
JS		 373static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
374 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
375 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
376 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
377};
5152d8c2
PU		 378
379/* Carkit Right */
1a787e7a
JS		 380static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
381 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
382 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
383 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
384};
5152d8c2 385
df339804
PU		 386/* Handsfree Left */
387static const char *twl4030_handsfreel_texts[] =
1a787e7a 388 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 389
390static const struct soc_enum twl4030_handsfreel_enum =
391 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
392 ARRAY_SIZE(twl4030_handsfreel_texts),
393 twl4030_handsfreel_texts);
394
395static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
396SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
397
398/* Handsfree Right */
399static const char *twl4030_handsfreer_texts[] =
1a787e7a 400 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 401
402static const struct soc_enum twl4030_handsfreer_enum =
403 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
404 ARRAY_SIZE(twl4030_handsfreer_texts),
405 twl4030_handsfreer_texts);
406
407static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
408SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
409
376f7839
PU		 410/* Vibra */
411/* Vibra audio path selection */
412static const char *twl4030_vibra_texts[] =
413 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
414
415static const struct soc_enum twl4030_vibra_enum =
416 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
417 ARRAY_SIZE(twl4030_vibra_texts),
418 twl4030_vibra_texts);
419
420static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
421SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
422
423/* Vibra path selection: local vibrator (PWM) or audio driven */
424static const char *twl4030_vibrapath_texts[] =
425 {"Local vibrator", "Audio"};
426
427static const struct soc_enum twl4030_vibrapath_enum =
428 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
429 ARRAY_SIZE(twl4030_vibrapath_texts),
430 twl4030_vibrapath_texts);
431
432static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
433SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
434
276c6222 435/* Left analog microphone selection */
97b8096d
JS		 436static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
437 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
438 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
439 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
440 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
441};
276c6222
PU		 442
443/* Right analog microphone selection */
97b8096d
JS		 444static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
445 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
181da78c 446 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 447};
276c6222
PU		 448
449/* TX1 L/R Analog/Digital microphone selection */
450static const char *twl4030_micpathtx1_texts[] =
451 {"Analog", "Digimic0"};
452
453static const struct soc_enum twl4030_micpathtx1_enum =
454 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
455 ARRAY_SIZE(twl4030_micpathtx1_texts),
456 twl4030_micpathtx1_texts);
457
458static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
459SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
460
461/* TX2 L/R Analog/Digital microphone selection */
462static const char *twl4030_micpathtx2_texts[] =
463 {"Analog", "Digimic1"};
464
465static const struct soc_enum twl4030_micpathtx2_enum =
466 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
467 ARRAY_SIZE(twl4030_micpathtx2_texts),
468 twl4030_micpathtx2_texts);
469
470static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
471SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
472
7393958f
PU		 473/* Analog bypass for AudioR1 */
474static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
475 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
476
477/* Analog bypass for AudioL1 */
478static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
479 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
480
481/* Analog bypass for AudioR2 */
482static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
483 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
484
485/* Analog bypass for AudioL2 */
486static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
487 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
488
fcd274a3
LCM		 489/* Analog bypass for Voice */
490static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
491 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
492
6bab83fd
PU		 493/* Digital bypass gain, 0 mutes the bypass */
494static const unsigned int twl4030_dapm_dbypass_tlv[] = {
495 TLV_DB_RANGE_HEAD(2),
496 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
497 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
498};
499
500/* Digital bypass left (TX1L -> RX2L) */
501static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
502 SOC_DAPM_SINGLE_TLV("Volume",
503 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
504 twl4030_dapm_dbypass_tlv);
505
506/* Digital bypass right (TX1R -> RX2R) */
507static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
508 SOC_DAPM_SINGLE_TLV("Volume",
509 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
510 twl4030_dapm_dbypass_tlv);
511
ee8f6894
LCM		 512/*
513 * Voice Sidetone GAIN volume control:
514 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
515 */
516static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
517
518/* Digital bypass voice: sidetone (VUL -> VDL)*/
519static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
520 SOC_DAPM_SINGLE_TLV("Volume",
521 TWL4030_REG_VSTPGA, 0, 0x29, 0,
522 twl4030_dapm_dbypassv_tlv);
523
276c6222
PU		 524static int micpath_event(struct snd_soc_dapm_widget *w,
525 struct snd_kcontrol *kcontrol, int event)
526{
527 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
528 unsigned char adcmicsel, micbias_ctl;
529
530 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
531 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
532 /* Prepare the bits for the given TX path:
533 * shift_l == 0: TX1 microphone path
534 * shift_l == 2: TX2 microphone path */
535 if (e->shift_l) {
536 /* TX2 microphone path */
537 if (adcmicsel & TWL4030_TX2IN_SEL)
538 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
539 else
540 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
541 } else {
542 /* TX1 microphone path */
543 if (adcmicsel & TWL4030_TX1IN_SEL)
544 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
545 else
546 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
547 }
548
549 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
550
551 return 0;
552}
553
5a2e9a48 554static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 555{
49d92c7d
SM		 556 unsigned char hs_ctl;
557
5a2e9a48 558 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 559
5a2e9a48
PU		 560 if (ramp) {
561 /* HF ramp-up */
562 hs_ctl |= TWL4030_HF_CTL_REF_EN;
563 twl4030_write(codec, reg, hs_ctl);
564 udelay(10);
49d92c7d 565 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 566 twl4030_write(codec, reg, hs_ctl);
567 udelay(40);
49d92c7d 568 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 569 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 570 twl4030_write(codec, reg, hs_ctl);
49d92c7d 571 } else {
5a2e9a48
PU		 572 /* HF ramp-down */
573 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
574 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
575 twl4030_write(codec, reg, hs_ctl);
576 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
577 twl4030_write(codec, reg, hs_ctl);
578 udelay(40);
579 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
580 twl4030_write(codec, reg, hs_ctl);
49d92c7d 581 }
5a2e9a48 582}
49d92c7d 583
5a2e9a48
PU		 584static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
585 struct snd_kcontrol *kcontrol, int event)
586{
587 switch (event) {
588 case SND_SOC_DAPM_POST_PMU:
589 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
590 break;
591 case SND_SOC_DAPM_POST_PMD:
592 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
593 break;
594 }
595 return 0;
596}
597
598static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
599 struct snd_kcontrol *kcontrol, int event)
600{
601 switch (event) {
602 case SND_SOC_DAPM_POST_PMU:
603 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
604 break;
605 case SND_SOC_DAPM_POST_PMD:
606 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
607 break;
608 }
49d92c7d
SM		 609 return 0;
610}
611
6943c92e 612static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 613{
614 unsigned char hs_gain, hs_pop;
6943c92e
PU		 615 struct twl4030_priv *twl4030 = codec->private_data;
616 /* Base values for ramp delay calculation: 2^19 - 2^26 */
617 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
618 8388608, 16777216, 33554432, 67108864};
aad749e5 619
6943c92e
PU		 620 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
621 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 622
6943c92e
PU		 623 if (ramp) {
624 /* Headset ramp-up according to the TRM */
aad749e5 625 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 626 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
627 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 628 hs_pop |= TWL4030_RAMP_EN;
6943c92e
PU		 629 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
630 } else {
631 /* Headset ramp-down _not_ according to
632 * the TRM, but in a way that it is working */
aad749e5 633 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 634 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
635 /* Wait ramp delay time + 1, so the VMID can settle */
636 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
637 twl4030->sysclk) + 1);
aad749e5
PU		 638 /* Bypass the reg_cache to mute the headset */
639 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
640 hs_gain & (~0x0f),
641 TWL4030_REG_HS_GAIN_SET);
6943c92e 642
aad749e5 643 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 644 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
645 }
646}
647
648static int headsetlpga_event(struct snd_soc_dapm_widget *w,
649 struct snd_kcontrol *kcontrol, int event)
650{
651 struct twl4030_priv *twl4030 = w->codec->private_data;
652
653 switch (event) {
654 case SND_SOC_DAPM_POST_PMU:
655 /* Do the ramp-up only once */
656 if (!twl4030->hsr_enabled)
657 headset_ramp(w->codec, 1);
658
659 twl4030->hsl_enabled = 1;
660 break;
661 case SND_SOC_DAPM_POST_PMD:
662 /* Do the ramp-down only if both headsetL/R is disabled */
663 if (!twl4030->hsr_enabled)
664 headset_ramp(w->codec, 0);
665
666 twl4030->hsl_enabled = 0;
667 break;
668 }
669 return 0;
670}
671
672static int headsetrpga_event(struct snd_soc_dapm_widget *w,
673 struct snd_kcontrol *kcontrol, int event)
674{
675 struct twl4030_priv *twl4030 = w->codec->private_data;
676
677 switch (event) {
678 case SND_SOC_DAPM_POST_PMU:
679 /* Do the ramp-up only once */
680 if (!twl4030->hsl_enabled)
681 headset_ramp(w->codec, 1);
682
683 twl4030->hsr_enabled = 1;
684 break;
685 case SND_SOC_DAPM_POST_PMD:
686 /* Do the ramp-down only if both headsetL/R is disabled */
687 if (!twl4030->hsl_enabled)
688 headset_ramp(w->codec, 0);
689
690 twl4030->hsr_enabled = 0;
aad749e5
PU		 691 break;
692 }
693 return 0;
694}
695
7393958f
PU		 696static int bypass_event(struct snd_soc_dapm_widget *w,
697 struct snd_kcontrol *kcontrol, int event)
698{
699 struct soc_mixer_control *m =
700 (struct soc_mixer_control *)w->kcontrols->private_value;
701 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 702 unsigned char reg, misc;
7393958f
PU		 703
704 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 705
706 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
707 /* Analog bypass */
708 if (reg & (1 << m->shift))
709 twl4030->bypass_state |=
710 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
711 else
712 twl4030->bypass_state &=
713 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 714 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
715 /* Analog voice bypass */
716 if (reg & (1 << m->shift))
717 twl4030->bypass_state |= (1 << 4);
718 else
719 twl4030->bypass_state &= ~(1 << 4);
ee8f6894
LCM		 720 } else if (m->reg == TWL4030_REG_VSTPGA) {
721 /* Voice digital bypass */
722 if (reg)
723 twl4030->bypass_state |= (1 << 5);
724 else
725 twl4030->bypass_state &= ~(1 << 5);
6bab83fd
PU		 726 } else {
727 /* Digital bypass */
728 if (reg & (0x7 << m->shift))
ee8f6894 729 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 730 else
ee8f6894 731 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 732 }
7393958f 733
fcd274a3
LCM		 734 /* Enable master analog loopback mode if any analog switch is enabled*/
735 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
736 if (twl4030->bypass_state & 0x1F)
737 misc |= TWL4030_FMLOOP_EN;
738 else
739 misc &= ~TWL4030_FMLOOP_EN;
740 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
741
7393958f
PU		 742 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
743 if (twl4030->bypass_state)
744 twl4030_codec_mute(w->codec, 0);
745 else
746 twl4030_codec_mute(w->codec, 1);
747 }
748 return 0;
749}
750
b0bd53a7
PU		 751/*
752 * Some of the gain controls in TWL (mostly those which are associated with
753 * the outputs) are implemented in an interesting way:
754 * 0x0 : Power down (mute)
755 * 0x1 : 6dB
756 * 0x2 : 0 dB
757 * 0x3 : -6 dB
758 * Inverting not going to help with these.
759 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
760 */
761#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
762 xinvert, tlv_array) \
763{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
764 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
765 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
766 .tlv.p = (tlv_array), \
767 .info = snd_soc_info_volsw, \
768 .get = snd_soc_get_volsw_twl4030, \
769 .put = snd_soc_put_volsw_twl4030, \
770 .private_value = (unsigned long)&(struct soc_mixer_control) \
771 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
772 .max = xmax, .invert = xinvert} }
773#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
774 xinvert, tlv_array) \
775{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
776 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
777 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
778 .tlv.p = (tlv_array), \
779 .info = snd_soc_info_volsw_2r, \
780 .get = snd_soc_get_volsw_r2_twl4030,\
781 .put = snd_soc_put_volsw_r2_twl4030, \
782 .private_value = (unsigned long)&(struct soc_mixer_control) \
783 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 784 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 785#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
786 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
787 xinvert, tlv_array)
788
789static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
790 struct snd_ctl_elem_value *ucontrol)
791{
792 struct soc_mixer_control *mc =
793 (struct soc_mixer_control *)kcontrol->private_value;
794 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
795 unsigned int reg = mc->reg;
796 unsigned int shift = mc->shift;
797 unsigned int rshift = mc->rshift;
798 int max = mc->max;
799 int mask = (1 << fls(max)) - 1;
800
801 ucontrol->value.integer.value[0] =
802 (snd_soc_read(codec, reg) >> shift) & mask;
803 if (ucontrol->value.integer.value[0])
804 ucontrol->value.integer.value[0] =
805 max + 1 - ucontrol->value.integer.value[0];
806
807 if (shift != rshift) {
808 ucontrol->value.integer.value[1] =
809 (snd_soc_read(codec, reg) >> rshift) & mask;
810 if (ucontrol->value.integer.value[1])
811 ucontrol->value.integer.value[1] =
812 max + 1 - ucontrol->value.integer.value[1];
813 }
814
815 return 0;
816}
817
818static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
819 struct snd_ctl_elem_value *ucontrol)
820{
821 struct soc_mixer_control *mc =
822 (struct soc_mixer_control *)kcontrol->private_value;
823 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
824 unsigned int reg = mc->reg;
825 unsigned int shift = mc->shift;
826 unsigned int rshift = mc->rshift;
827 int max = mc->max;
828 int mask = (1 << fls(max)) - 1;
829 unsigned short val, val2, val_mask;
830
831 val = (ucontrol->value.integer.value[0] & mask);
832
833 val_mask = mask << shift;
834 if (val)
835 val = max + 1 - val;
836 val = val << shift;
837 if (shift != rshift) {
838 val2 = (ucontrol->value.integer.value[1] & mask);
839 val_mask |= mask << rshift;
840 if (val2)
841 val2 = max + 1 - val2;
842 val |= val2 << rshift;
843 }
844 return snd_soc_update_bits(codec, reg, val_mask, val);
845}
846
847static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
848 struct snd_ctl_elem_value *ucontrol)
849{
850 struct soc_mixer_control *mc =
851 (struct soc_mixer_control *)kcontrol->private_value;
852 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
853 unsigned int reg = mc->reg;
854 unsigned int reg2 = mc->rreg;
855 unsigned int shift = mc->shift;
856 int max = mc->max;
857 int mask = (1<<fls(max))-1;
858
859 ucontrol->value.integer.value[0] =
860 (snd_soc_read(codec, reg) >> shift) & mask;
861 ucontrol->value.integer.value[1] =
862 (snd_soc_read(codec, reg2) >> shift) & mask;
863
864 if (ucontrol->value.integer.value[0])
865 ucontrol->value.integer.value[0] =
866 max + 1 - ucontrol->value.integer.value[0];
867 if (ucontrol->value.integer.value[1])
868 ucontrol->value.integer.value[1] =
869 max + 1 - ucontrol->value.integer.value[1];
870
871 return 0;
872}
873
874static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
875 struct snd_ctl_elem_value *ucontrol)
876{
877 struct soc_mixer_control *mc =
878 (struct soc_mixer_control *)kcontrol->private_value;
879 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
880 unsigned int reg = mc->reg;
881 unsigned int reg2 = mc->rreg;
882 unsigned int shift = mc->shift;
883 int max = mc->max;
884 int mask = (1 << fls(max)) - 1;
885 int err;
886 unsigned short val, val2, val_mask;
887
888 val_mask = mask << shift;
889 val = (ucontrol->value.integer.value[0] & mask);
890 val2 = (ucontrol->value.integer.value[1] & mask);
891
892 if (val)
893 val = max + 1 - val;
894 if (val2)
895 val2 = max + 1 - val2;
896
897 val = val << shift;
898 val2 = val2 << shift;
899
900 err = snd_soc_update_bits(codec, reg, val_mask, val);
901 if (err < 0)
902 return err;
903
904 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
905 return err;
906}
907
b74bd40f
LCM		 908/* Codec operation modes */
909static const char *twl4030_op_modes_texts[] = {
910 "Option 2 (voice/audio)", "Option 1 (audio)"
911};
912
913static const struct soc_enum twl4030_op_modes_enum =
914 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
915 ARRAY_SIZE(twl4030_op_modes_texts),
916 twl4030_op_modes_texts);
917
918int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
919 struct snd_ctl_elem_value *ucontrol)
920{
921 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
922 struct twl4030_priv *twl4030 = codec->private_data;
923 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
924 unsigned short val;
925 unsigned short mask, bitmask;
926
927 if (twl4030->configured) {
928 printk(KERN_ERR "twl4030 operation mode cannot be "
929 "changed on-the-fly\n");
930 return -EBUSY;
931 }
932
933 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
934 ;
935 if (ucontrol->value.enumerated.item[0] > e->max - 1)
936 return -EINVAL;
937
938 val = ucontrol->value.enumerated.item[0] << e->shift_l;
939 mask = (bitmask - 1) << e->shift_l;
940 if (e->shift_l != e->shift_r) {
941 if (ucontrol->value.enumerated.item[1] > e->max - 1)
942 return -EINVAL;
943 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
944 mask |= (bitmask - 1) << e->shift_r;
945 }
946
947 return snd_soc_update_bits(codec, e->reg, mask, val);
948}
949
c10b82cf
PU		 950/*
951 * FGAIN volume control:
952 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
953 */
d889a72c 954static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 955
0d33ea0b
PU		 956/*
957 * CGAIN volume control:
958 * 0 dB to 12 dB in 6 dB steps
959 * value 2 and 3 means 12 dB
960 */
d889a72c
PU		 961static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
962
1a787e7a
JS		 963/*
964 * Voice Downlink GAIN volume control:
965 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
966 */
967static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
968
d889a72c
PU		 969/*
970 * Analog playback gain
971 * -24 dB to 12 dB in 2 dB steps
972 */
973static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 974
4290239c
PU		 975/*
976 * Gain controls tied to outputs
977 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
978 */
979static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
980
18cc8d8d
JS		 981/*
982 * Gain control for earpiece amplifier
983 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
984 */
985static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
986
381a22b5
PU		 987/*
988 * Capture gain after the ADCs
989 * from 0 dB to 31 dB in 1 dB steps
990 */
991static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
992
5920b453
GI		 993/*
994 * Gain control for input amplifiers
995 * 0 dB to 30 dB in 6 dB steps
996 */
997static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
998
89492be8
PU		 999static const char *twl4030_rampdelay_texts[] = {
1000 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1001 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1002 "3495/2581/1748 ms"
1003};
1004
1005static const struct soc_enum twl4030_rampdelay_enum =
1006 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1007 ARRAY_SIZE(twl4030_rampdelay_texts),
1008 twl4030_rampdelay_texts);
1009
376f7839
PU		 1010/* Vibra H-bridge direction mode */
1011static const char *twl4030_vibradirmode_texts[] = {
1012 "Vibra H-bridge direction", "Audio data MSB",
1013};
1014
1015static const struct soc_enum twl4030_vibradirmode_enum =
1016 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1017 ARRAY_SIZE(twl4030_vibradirmode_texts),
1018 twl4030_vibradirmode_texts);
1019
1020/* Vibra H-bridge direction */
1021static const char *twl4030_vibradir_texts[] = {
1022 "Positive polarity", "Negative polarity",
1023};
1024
1025static const struct soc_enum twl4030_vibradir_enum =
1026 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1027 ARRAY_SIZE(twl4030_vibradir_texts),
1028 twl4030_vibradir_texts);
1029
cc17557e 1030static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1031 /* Codec operation mode control */
1032 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1033 snd_soc_get_enum_double,
1034 snd_soc_put_twl4030_opmode_enum_double),
1035
d889a72c
PU		 1036 /* Common playback gain controls */
1037 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1038 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1039 0, 0x3f, 0, digital_fine_tlv),
1040 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1041 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1042 0, 0x3f, 0, digital_fine_tlv),
1043
1044 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1045 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1046 6, 0x2, 0, digital_coarse_tlv),
1047 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1048 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1049 6, 0x2, 0, digital_coarse_tlv),
1050
1051 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1052 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1053 3, 0x12, 1, analog_tlv),
1054 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1055 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1056 3, 0x12, 1, analog_tlv),
44c55870
PU		 1057 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1058 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1059 1, 1, 0),
1060 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1061 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1062 1, 1, 0),
381a22b5 1063
1a787e7a
JS		 1064 /* Common voice downlink gain controls */
1065 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1066 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1067
1068 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1069 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1070
1071 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1072 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1073
4290239c
PU		 1074 /* Separate output gain controls */
1075 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1076 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1077 4, 3, 0, output_tvl),
1078
1079 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1080 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1081
1082 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1083 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1084 4, 3, 0, output_tvl),
1085
1086 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1087 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1088
381a22b5 1089 /* Common capture gain controls */
276c6222 1090 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1091 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1092 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1093 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1094 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1095 0, 0x1f, 0, digital_capture_tlv),
5920b453 1096
276c6222 1097 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1098 0, 3, 5, 0, input_gain_tlv),
89492be8
PU		 1099
1100 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1101
1102 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1103 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1104};
1105
cc17557e 1106static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1107 /* Left channel inputs */
1108 SND_SOC_DAPM_INPUT("MAINMIC"),
1109 SND_SOC_DAPM_INPUT("HSMIC"),
1110 SND_SOC_DAPM_INPUT("AUXL"),
1111 SND_SOC_DAPM_INPUT("CARKITMIC"),
1112 /* Right channel inputs */
1113 SND_SOC_DAPM_INPUT("SUBMIC"),
1114 SND_SOC_DAPM_INPUT("AUXR"),
1115 /* Digital microphones (Stereo) */
1116 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1117 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1118
1119 /* Outputs */
cc17557e
SS		 1120 SND_SOC_DAPM_OUTPUT("OUTL"),
1121 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1122 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1123 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1124 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1125 SND_SOC_DAPM_OUTPUT("HSOL"),
1126 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1127 SND_SOC_DAPM_OUTPUT("CARKITL"),
1128 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1129 SND_SOC_DAPM_OUTPUT("HFL"),
1130 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1131 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1132
53b5047d 1133 /* DACs */
b4852b79 1134 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1135 SND_SOC_NOPM, 0, 0),
b4852b79 1136 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1137 SND_SOC_NOPM, 0, 0),
b4852b79 1138 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1139 SND_SOC_NOPM, 0, 0),
b4852b79 1140 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1141 SND_SOC_NOPM, 0, 0),
1a787e7a 1142 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1143 SND_SOC_NOPM, 0, 0),
cc17557e 1144
7393958f
PU		 1145 /* Analog bypasses */
1146 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1147 &twl4030_dapm_abypassr1_control, bypass_event,
1148 SND_SOC_DAPM_POST_REG),
1149 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1150 &twl4030_dapm_abypassl1_control,
1151 bypass_event, SND_SOC_DAPM_POST_REG),
1152 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1153 &twl4030_dapm_abypassr2_control,
1154 bypass_event, SND_SOC_DAPM_POST_REG),
1155 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1156 &twl4030_dapm_abypassl2_control,
1157 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1158 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1159 &twl4030_dapm_abypassv_control,
1160 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1161
6bab83fd
PU		 1162 /* Digital bypasses */
1163 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1164 &twl4030_dapm_dbypassl_control, bypass_event,
1165 SND_SOC_DAPM_POST_REG),
1166 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1167 &twl4030_dapm_dbypassr_control, bypass_event,
1168 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1169 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1170 &twl4030_dapm_dbypassv_control, bypass_event,
1171 SND_SOC_DAPM_POST_REG),
6bab83fd 1172
4005d39a
PU		 1173 /* Digital mixers, power control for the physical DACs */
1174 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1175 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1176 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1177 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1178 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1179 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1180 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1181 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1182 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1183 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1184
1185 /* Analog mixers, power control for the physical PGAs */
1186 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1187 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1188 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1189 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1190 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1191 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1192 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1193 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1194 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1195 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1196
1a787e7a 1197 /* Output MIXER controls */
5e98a464 1198 /* Earpiece */
1a787e7a
JS		 1199 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1200 &twl4030_dapm_earpiece_controls[0],
1201 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
2a6f5c58 1202 /* PreDrivL/R */
1a787e7a
JS		 1203 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1204 &twl4030_dapm_predrivel_controls[0],
1205 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1206 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1207 &twl4030_dapm_predriver_controls[0],
1208 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
dfad21a2 1209 /* HeadsetL/R */
6943c92e 1210 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1211 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1212 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1213 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1214 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1215 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1216 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1217 &twl4030_dapm_hsor_controls[0],
1218 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1219 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1220 0, 0, NULL, 0, headsetrpga_event,
1221 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1222 /* CarkitL/R */
1a787e7a
JS		 1223 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1224 &twl4030_dapm_carkitl_controls[0],
1225 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1226 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1227 &twl4030_dapm_carkitr_controls[0],
1228 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1229
1230 /* Output MUX controls */
df339804 1231 /* HandsfreeL/R */
5a2e9a48
PU		 1232 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1233 &twl4030_dapm_handsfreel_control),
1234 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1235 0, 0, NULL, 0, handsfreelpga_event,
1236 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1237 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1238 &twl4030_dapm_handsfreer_control),
1239 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1240 0, 0, NULL, 0, handsfreerpga_event,
1241 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1242 /* Vibra */
1243 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1244 &twl4030_dapm_vibra_control),
1245 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1246 &twl4030_dapm_vibrapath_control),
5e98a464 1247
276c6222
PU		 1248 /* Introducing four virtual ADC, since TWL4030 have four channel for
1249 capture */
1250 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1251 SND_SOC_NOPM, 0, 0),
1252 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1253 SND_SOC_NOPM, 0, 0),
1254 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1255 SND_SOC_NOPM, 0, 0),
1256 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1257 SND_SOC_NOPM, 0, 0),
1258
1259 /* Analog/Digital mic path selection.
1260 TX1 Left/Right: either analog Left/Right or Digimic0
1261 TX2 Left/Right: either analog Left/Right or Digimic1 */
1262 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1263 &twl4030_dapm_micpathtx1_control, micpath_event,
1264 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1265 SND_SOC_DAPM_POST_REG),
1266 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1267 &twl4030_dapm_micpathtx2_control, micpath_event,
1268 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1269 SND_SOC_DAPM_POST_REG),
1270
97b8096d
JS		 1271 /* Analog input mixers for the capture amplifiers */
1272 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1273 TWL4030_REG_ANAMICL, 4, 0,
1274 &twl4030_dapm_analoglmic_controls[0],
1275 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1276 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1277 TWL4030_REG_ANAMICR, 4, 0,
1278 &twl4030_dapm_analogrmic_controls[0],
1279 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1280
fb2a2f84
PU		 1281 SND_SOC_DAPM_PGA("ADC Physical Left",
1282 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1283 SND_SOC_DAPM_PGA("ADC Physical Right",
1284 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1285
1286 SND_SOC_DAPM_PGA("Digimic0 Enable",
1287 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1288 SND_SOC_DAPM_PGA("Digimic1 Enable",
1289 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1290
1291 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1292 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1293 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1294
cc17557e
SS		 1295};
1296
1297static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1298 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1299 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1300 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1301 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1302 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1303
1304 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1305 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1306 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1307 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1308 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1309
5e98a464
PU		 1310 /* Internal playback routings */
1311 /* Earpiece */
4005d39a
PU		 1312 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1313 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1314 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1315 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
2a6f5c58 1316 /* PreDrivL */
4005d39a
PU		 1317 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1318 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1319 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1320 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
2a6f5c58 1321 /* PreDrivR */
4005d39a
PU		 1322 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1323 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1324 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1325 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
dfad21a2 1326 /* HeadsetL */
4005d39a
PU		 1327 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1328 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1329 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1330 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1331 /* HeadsetR */
4005d39a
PU		 1332 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1333 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1334 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1335 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1336 /* CarkitL */
4005d39a
PU		 1337 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1338 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1339 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
5152d8c2 1340 /* CarkitR */
4005d39a
PU		 1341 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1342 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1343 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
df339804 1344 /* HandsfreeL */
4005d39a
PU		 1345 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1346 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1347 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1348 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
5a2e9a48 1349 {"HandsfreeL PGA", NULL, "HandsfreeL Mux"},
df339804 1350 /* HandsfreeR */
4005d39a
PU		 1351 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1352 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1353 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1354 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
5a2e9a48 1355 {"HandsfreeR PGA", NULL, "HandsfreeR Mux"},
376f7839
PU		 1356 /* Vibra */
1357 {"Vibra Mux", "AudioL1", "DAC Left1"},
1358 {"Vibra Mux", "AudioR1", "DAC Right1"},
1359 {"Vibra Mux", "AudioL2", "DAC Left2"},
1360 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1361
cc17557e 1362 /* outputs */
4005d39a
PU		 1363 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1364 {"OUTR", NULL, "Analog R2 Playback Mixer"},
1a787e7a
JS		 1365 {"EARPIECE", NULL, "Earpiece Mixer"},
1366 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1367 {"PREDRIVER", NULL, "PredriveR Mixer"},
6943c92e
PU		 1368 {"HSOL", NULL, "HeadsetL PGA"},
1369 {"HSOR", NULL, "HeadsetR PGA"},
1a787e7a
JS		 1370 {"CARKITL", NULL, "CarkitL Mixer"},
1371 {"CARKITR", NULL, "CarkitR Mixer"},
5a2e9a48
PU		 1372 {"HFL", NULL, "HandsfreeL PGA"},
1373 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1374 {"Vibra Route", "Audio", "Vibra Mux"},
1375 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1376
276c6222
PU		 1377 /* Capture path */
1378 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1379 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1380 {"Analog Left Capture Route", "AUXL", "AUXL"},
1381 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1382
1383 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1384 {"Analog Right Capture Route", "AUXR", "AUXR"},
1385
fb2a2f84
PU		 1386 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1387 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1388
1389 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1390 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1391
1392 /* TX1 Left capture path */
fb2a2f84 1393 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1394 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1395 /* TX1 Right capture path */
fb2a2f84 1396 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1397 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1398 /* TX2 Left capture path */
fb2a2f84 1399 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1400 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1401 /* TX2 Right capture path */
fb2a2f84 1402 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1403 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1404
1405 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1406 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1407 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1408 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1409
7393958f
PU		 1410 /* Analog bypass routes */
1411 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1412 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1413 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1414 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
fcd274a3 1415 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
7393958f
PU		 1416
1417 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1418 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1419 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1420 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1421 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1422
6bab83fd
PU		 1423 /* Digital bypass routes */
1424 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1425 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1426 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1427
4005d39a
PU		 1428 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1429 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1430 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1431
cc17557e
SS		 1432};
1433
1434static int twl4030_add_widgets(struct snd_soc_codec *codec)
1435{
1436 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1437 ARRAY_SIZE(twl4030_dapm_widgets));
1438
1439 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1440
1441 snd_soc_dapm_new_widgets(codec);
1442 return 0;
1443}
1444
cc17557e
SS		 1445static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1446 enum snd_soc_bias_level level)
1447{
7393958f
PU		 1448 struct twl4030_priv *twl4030 = codec->private_data;
1449
cc17557e
SS		 1450 switch (level) {
1451 case SND_SOC_BIAS_ON:
7393958f 1452 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1453 break;
1454 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1455 twl4030_power_up(codec);
1456 if (twl4030->bypass_state)
1457 twl4030_codec_mute(codec, 0);
1458 else
1459 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1460 break;
1461 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1462 twl4030_power_up(codec);
1463 if (twl4030->bypass_state)
1464 twl4030_codec_mute(codec, 0);
1465 else
1466 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1467 break;
1468 case SND_SOC_BIAS_OFF:
1469 twl4030_power_down(codec);
1470 break;
1471 }
1472 codec->bias_level = level;
1473
1474 return 0;
1475}
1476
6b87a91f
PU		 1477static void twl4030_constraints(struct twl4030_priv *twl4030,
1478 struct snd_pcm_substream *mst_substream)
1479{
1480 struct snd_pcm_substream *slv_substream;
1481
1482 /* Pick the stream, which need to be constrained */
1483 if (mst_substream == twl4030->master_substream)
1484 slv_substream = twl4030->slave_substream;
1485 else if (mst_substream == twl4030->slave_substream)
1486 slv_substream = twl4030->master_substream;
1487 else /* This should not happen.. */
1488 return;
1489
1490 /* Set the constraints according to the already configured stream */
1491 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1492 SNDRV_PCM_HW_PARAM_RATE,
1493 twl4030->rate,
1494 twl4030->rate);
1495
1496 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1497 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1498 twl4030->sample_bits,
1499 twl4030->sample_bits);
1500
1501 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1502 SNDRV_PCM_HW_PARAM_CHANNELS,
1503 twl4030->channels,
1504 twl4030->channels);
1505}
1506
8a1f936a
PU		 1507/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1508 * capture has to be enabled/disabled. */
1509static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1510 int enable)
1511{
1512 u8 reg, mask;
1513
1514 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1515
1516 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1517 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1518 else
1519 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1520
1521 if (enable)
1522 reg |= mask;
1523 else
1524 reg &= ~mask;
1525
1526 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1527}
1528
d6648da1
PU		 1529static int twl4030_startup(struct snd_pcm_substream *substream,
1530 struct snd_soc_dai *dai)
7220b9f4
PU		 1531{
1532 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1533 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1534 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1535 struct twl4030_priv *twl4030 = codec->private_data;
1536
7220b9f4 1537 if (twl4030->master_substream) {
7220b9f4 1538 twl4030->slave_substream = substream;
6b87a91f
PU		 1539 /* The DAI has one configuration for playback and capture, so
1540 * if the DAI has been already configured then constrain this
1541 * substream to match it. */
1542 if (twl4030->configured)
1543 twl4030_constraints(twl4030, twl4030->master_substream);
1544 } else {
8a1f936a
PU		 1545 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1546 TWL4030_OPTION_1)) {
1547 /* In option2 4 channel is not supported, set the
1548 * constraint for the first stream for channels, the
1549 * second stream will 'inherit' this cosntraint */
1550 snd_pcm_hw_constraint_minmax(substream->runtime,
1551 SNDRV_PCM_HW_PARAM_CHANNELS,
1552 2, 2);
1553 }
7220b9f4 1554 twl4030->master_substream = substream;
6b87a91f 1555 }
7220b9f4
PU		 1556
1557 return 0;
1558}
1559
d6648da1
PU		 1560static void twl4030_shutdown(struct snd_pcm_substream *substream,
1561 struct snd_soc_dai *dai)
7220b9f4
PU		 1562{
1563 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1564 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1565 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1566 struct twl4030_priv *twl4030 = codec->private_data;
1567
1568 if (twl4030->master_substream == substream)
1569 twl4030->master_substream = twl4030->slave_substream;
1570
1571 twl4030->slave_substream = NULL;
6b87a91f
PU		 1572
1573 /* If all streams are closed, or the remaining stream has not yet
1574 * been configured than set the DAI as not configured. */
1575 if (!twl4030->master_substream)
1576 twl4030->configured = 0;
1577 else if (!twl4030->master_substream->runtime->channels)
1578 twl4030->configured = 0;
8a1f936a
PU		 1579
1580 /* If the closing substream had 4 channel, do the necessary cleanup */
1581 if (substream->runtime->channels == 4)
1582 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1583}
1584
cc17557e 1585static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1586 struct snd_pcm_hw_params *params,
1587 struct snd_soc_dai *dai)
cc17557e
SS		 1588{
1589 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1590 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1591 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1592 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1593 u8 mode, old_mode, format, old_format;
1594
8a1f936a
PU		 1595 /* If the substream has 4 channel, do the necessary setup */
1596 if (params_channels(params) == 4) {
1597 /* Safety check: are we in the correct operating mode? */
1598 if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1599 TWL4030_OPTION_1))
1600 twl4030_tdm_enable(codec, substream->stream, 1);
1601 else
1602 return -EINVAL;
1603 }
1604
6b87a91f
PU		 1605 if (twl4030->configured)
1606 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1607 return 0;
1608
cc17557e
SS		 1609 /* bit rate */
1610 old_mode = twl4030_read_reg_cache(codec,
1611 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1612 mode = old_mode & ~TWL4030_APLL_RATE;
1613
1614 switch (params_rate(params)) {
1615 case 8000:
1616 mode |= TWL4030_APLL_RATE_8000;
1617 break;
1618 case 11025:
1619 mode |= TWL4030_APLL_RATE_11025;
1620 break;
1621 case 12000:
1622 mode |= TWL4030_APLL_RATE_12000;
1623 break;
1624 case 16000:
1625 mode |= TWL4030_APLL_RATE_16000;
1626 break;
1627 case 22050:
1628 mode |= TWL4030_APLL_RATE_22050;
1629 break;
1630 case 24000:
1631 mode |= TWL4030_APLL_RATE_24000;
1632 break;
1633 case 32000:
1634 mode |= TWL4030_APLL_RATE_32000;
1635 break;
1636 case 44100:
1637 mode |= TWL4030_APLL_RATE_44100;
1638 break;
1639 case 48000:
1640 mode |= TWL4030_APLL_RATE_48000;
1641 break;
103f211d
PU		 1642 case 96000:
1643 mode |= TWL4030_APLL_RATE_96000;
1644 break;
cc17557e
SS		 1645 default:
1646 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1647 params_rate(params));
1648 return -EINVAL;
1649 }
1650
1651 if (mode != old_mode) {
1652 /* change rate and set CODECPDZ */
7393958f 1653 twl4030_codec_enable(codec, 0);
cc17557e 1654 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1655 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1656 }
1657
1658 /* sample size */
1659 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1660 format = old_format;
1661 format &= ~TWL4030_DATA_WIDTH;
1662 switch (params_format(params)) {
1663 case SNDRV_PCM_FORMAT_S16_LE:
1664 format |= TWL4030_DATA_WIDTH_16S_16W;
1665 break;
1666 case SNDRV_PCM_FORMAT_S24_LE:
1667 format |= TWL4030_DATA_WIDTH_32S_24W;
1668 break;
1669 default:
1670 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1671 params_format(params));
1672 return -EINVAL;
1673 }
1674
1675 if (format != old_format) {
1676
1677 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1678 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1679
1680 /* change format */
1681 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1682
1683 /* set CODECPDZ afterwards */
db04e2c5 1684 twl4030_codec_enable(codec, 1);
cc17557e 1685 }
6b87a91f
PU		 1686
1687 /* Store the important parameters for the DAI configuration and set
1688 * the DAI as configured */
1689 twl4030->configured = 1;
1690 twl4030->rate = params_rate(params);
1691 twl4030->sample_bits = hw_param_interval(params,
1692 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1693 twl4030->channels = params_channels(params);
1694
1695 /* If both playback and capture streams are open, and one of them
1696 * is setting the hw parameters right now (since we are here), set
1697 * constraints to the other stream to match the current one. */
1698 if (twl4030->slave_substream)
1699 twl4030_constraints(twl4030, substream);
1700
cc17557e
SS		 1701 return 0;
1702}
1703
1704static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1705 int clk_id, unsigned int freq, int dir)
1706{
1707 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1708 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1709 u8 infreq;
1710
1711 switch (freq) {
1712 case 19200000:
1713 infreq = TWL4030_APLL_INFREQ_19200KHZ;
6943c92e 1714 twl4030->sysclk = 19200;
cc17557e
SS		 1715 break;
1716 case 26000000:
1717 infreq = TWL4030_APLL_INFREQ_26000KHZ;
6943c92e 1718 twl4030->sysclk = 26000;
cc17557e
SS		 1719 break;
1720 case 38400000:
1721 infreq = TWL4030_APLL_INFREQ_38400KHZ;
6943c92e 1722 twl4030->sysclk = 38400;
cc17557e
SS		 1723 break;
1724 default:
1725 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1726 freq);
1727 return -EINVAL;
1728 }
1729
1730 infreq |= TWL4030_APLL_EN;
1731 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1732
1733 return 0;
1734}
1735
1736static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1737 unsigned int fmt)
1738{
1739 struct snd_soc_codec *codec = codec_dai->codec;
1740 u8 old_format, format;
1741
1742 /* get format */
1743 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1744 format = old_format;
1745
1746 /* set master/slave audio interface */
1747 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1748 case SND_SOC_DAIFMT_CBM_CFM:
1749 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1750 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1751 break;
1752 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1753 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1754 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1755 break;
1756 default:
1757 return -EINVAL;
1758 }
1759
1760 /* interface format */
1761 format &= ~TWL4030_AIF_FORMAT;
1762 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1763 case SND_SOC_DAIFMT_I2S:
1764 format |= TWL4030_AIF_FORMAT_CODEC;
1765 break;
8a1f936a
PU		 1766 case SND_SOC_DAIFMT_DSP_A:
1767 format |= TWL4030_AIF_FORMAT_TDM;
1768 break;
cc17557e
SS		 1769 default:
1770 return -EINVAL;
1771 }
1772
1773 if (format != old_format) {
1774
1775 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1776 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1777
1778 /* change format */
1779 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1780
1781 /* set CODECPDZ afterwards */
db04e2c5 1782 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1783 }
1784
1785 return 0;
1786}
1787
b7a755a8
MLC		 1788/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1789 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1790static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1791 int enable)
1792{
1793 u8 reg, mask;
1794
1795 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1796
1797 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1798 mask = TWL4030_ARXL1_VRX_EN;
1799 else
1800 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1801
1802 if (enable)
1803 reg |= mask;
1804 else
1805 reg &= ~mask;
1806
1807 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1808}
1809
7154b3e8
JS		 1810static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1811 struct snd_soc_dai *dai)
1812{
1813 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1814 struct snd_soc_device *socdev = rtd->socdev;
1815 struct snd_soc_codec *codec = socdev->card->codec;
1816 u8 infreq;
1817 u8 mode;
1818
1819 /* If the system master clock is not 26MHz, the voice PCM interface is
1820 * not avilable.
1821 */
1822 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1823 & TWL4030_APLL_INFREQ;
1824
1825 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1826 printk(KERN_ERR "TWL4030 voice startup: "
1827 "MCLK is not 26MHz, call set_sysclk() on init\n");
1828 return -EINVAL;
1829 }
1830
1831 /* If the codec mode is not option2, the voice PCM interface is not
1832 * avilable.
1833 */
1834 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1835 & TWL4030_OPT_MODE;
1836
1837 if (mode != TWL4030_OPTION_2) {
1838 printk(KERN_ERR "TWL4030 voice startup: "
1839 "the codec mode is not option2\n");
1840 return -EINVAL;
1841 }
1842
1843 return 0;
1844}
1845
b7a755a8
MLC		 1846static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1847 struct snd_soc_dai *dai)
1848{
1849 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1850 struct snd_soc_device *socdev = rtd->socdev;
1851 struct snd_soc_codec *codec = socdev->card->codec;
1852
1853 /* Enable voice digital filters */
1854 twl4030_voice_enable(codec, substream->stream, 0);
1855}
1856
7154b3e8
JS		 1857static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1858 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1859{
1860 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1861 struct snd_soc_device *socdev = rtd->socdev;
1862 struct snd_soc_codec *codec = socdev->card->codec;
1863 u8 old_mode, mode;
1864
b7a755a8
MLC		 1865 /* Enable voice digital filters */
1866 twl4030_voice_enable(codec, substream->stream, 1);
1867
7154b3e8
JS		 1868 /* bit rate */
1869 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1870 & ~(TWL4030_CODECPDZ);
1871 mode = old_mode;
1872
1873 switch (params_rate(params)) {
1874 case 8000:
1875 mode &= ~(TWL4030_SEL_16K);
1876 break;
1877 case 16000:
1878 mode |= TWL4030_SEL_16K;
1879 break;
1880 default:
1881 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1882 params_rate(params));
1883 return -EINVAL;
1884 }
1885
1886 if (mode != old_mode) {
1887 /* change rate and set CODECPDZ */
1888 twl4030_codec_enable(codec, 0);
1889 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1890 twl4030_codec_enable(codec, 1);
1891 }
1892
1893 return 0;
1894}
1895
1896static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1897 int clk_id, unsigned int freq, int dir)
1898{
1899 struct snd_soc_codec *codec = codec_dai->codec;
1900 u8 infreq;
1901
1902 switch (freq) {
1903 case 26000000:
1904 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1905 break;
1906 default:
1907 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1908 freq);
1909 return -EINVAL;
1910 }
1911
1912 infreq |= TWL4030_APLL_EN;
1913 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1914
1915 return 0;
1916}
1917
1918static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1919 unsigned int fmt)
1920{
1921 struct snd_soc_codec *codec = codec_dai->codec;
1922 u8 old_format, format;
1923
1924 /* get format */
1925 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1926 format = old_format;
1927
1928 /* set master/slave audio interface */
1929 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1930 case SND_SOC_DAIFMT_CBS_CFM:
1931 format &= ~(TWL4030_VIF_SLAVE_EN);
1932 break;
1933 case SND_SOC_DAIFMT_CBS_CFS:
1934 format |= TWL4030_VIF_SLAVE_EN;
1935 break;
1936 default:
1937 return -EINVAL;
1938 }
1939
1940 /* clock inversion */
1941 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1942 case SND_SOC_DAIFMT_IB_NF:
1943 format &= ~(TWL4030_VIF_FORMAT);
1944 break;
1945 case SND_SOC_DAIFMT_NB_IF:
1946 format |= TWL4030_VIF_FORMAT;
1947 break;
1948 default:
1949 return -EINVAL;
1950 }
1951
1952 if (format != old_format) {
1953 /* change format and set CODECPDZ */
1954 twl4030_codec_enable(codec, 0);
1955 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1956 twl4030_codec_enable(codec, 1);
1957 }
1958
1959 return 0;
1960}
1961
bbba9444 1962#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1963#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1964
10d9e3d9 1965static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 1966 .startup = twl4030_startup,
1967 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 1968 .hw_params = twl4030_hw_params,
1969 .set_sysclk = twl4030_set_dai_sysclk,
1970 .set_fmt = twl4030_set_dai_fmt,
1971};
1972
7154b3e8
JS		 1973static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1974 .startup = twl4030_voice_startup,
b7a755a8 1975 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 1976 .hw_params = twl4030_voice_hw_params,
1977 .set_sysclk = twl4030_voice_set_dai_sysclk,
1978 .set_fmt = twl4030_voice_set_dai_fmt,
1979};
1980
1981struct snd_soc_dai twl4030_dai[] = {
1982{
cc17557e
SS		 1983 .name = "twl4030",
1984 .playback = {
b4852b79 1985 .stream_name = "HiFi Playback",
cc17557e 1986 .channels_min = 2,
8a1f936a 1987 .channels_max = 4,
31ad0f31 1988 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 1989 .formats = TWL4030_FORMATS,},
1990 .capture = {
1991 .stream_name = "Capture",
1992 .channels_min = 2,
8a1f936a 1993 .channels_max = 4,
cc17557e
SS		 1994 .rates = TWL4030_RATES,
1995 .formats = TWL4030_FORMATS,},
10d9e3d9 1996 .ops = &twl4030_dai_ops,
7154b3e8
JS		 1997},
1998{
1999 .name = "twl4030 Voice",
2000 .playback = {
b4852b79 2001 .stream_name = "Voice Playback",
7154b3e8
JS		 2002 .channels_min = 1,
2003 .channels_max = 1,
2004 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2005 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2006 .capture = {
2007 .stream_name = "Capture",
2008 .channels_min = 1,
2009 .channels_max = 2,
2010 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2011 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2012 .ops = &twl4030_dai_voice_ops,
2013},
cc17557e
SS		 2014};
2015EXPORT_SYMBOL_GPL(twl4030_dai);
2016
2017static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
2018{
2019 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2020 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2021
2022 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2023
2024 return 0;
2025}
2026
2027static int twl4030_resume(struct platform_device *pdev)
2028{
2029 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2030 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2031
2032 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2033 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2034 return 0;
2035}
2036
2037/*
2038 * initialize the driver
2039 * register the mixer and dsp interfaces with the kernel
2040 */
2041
2042static int twl4030_init(struct snd_soc_device *socdev)
2043{
6627a653 2044 struct snd_soc_codec *codec = socdev->card->codec;
9da28c7b
PU		 2045 struct twl4030_setup_data *setup = socdev->codec_data;
2046 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 2047 int ret = 0;
2048
2049 printk(KERN_INFO "TWL4030 Audio Codec init \n");
2050
2051 codec->name = "twl4030";
2052 codec->owner = THIS_MODULE;
2053 codec->read = twl4030_read_reg_cache;
2054 codec->write = twl4030_write;
2055 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 2056 codec->dai = twl4030_dai;
2057 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 2058 codec->reg_cache_size = sizeof(twl4030_reg);
2059 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2060 GFP_KERNEL);
2061 if (codec->reg_cache == NULL)
2062 return -ENOMEM;
2063
9da28c7b
PU		 2064 /* Configuration for headset ramp delay from setup data */
2065 if (setup) {
2066 unsigned char hs_pop;
2067
2068 if (setup->sysclk)
2069 twl4030->sysclk = setup->sysclk;
2070 else
2071 twl4030->sysclk = 26000;
2072
2073 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2074 hs_pop &= ~TWL4030_RAMP_DELAY;
2075 hs_pop |= (setup->ramp_delay_value << 2);
2076 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2077 } else {
2078 twl4030->sysclk = 26000;
2079 }
2080
cc17557e
SS		 2081 /* register pcms */
2082 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2083 if (ret < 0) {
2084 printk(KERN_ERR "twl4030: failed to create pcms\n");
2085 goto pcm_err;
2086 }
2087
2088 twl4030_init_chip(codec);
2089
2090 /* power on device */
2091 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2092
3e8e1952
IM		 2093 snd_soc_add_controls(codec, twl4030_snd_controls,
2094 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2095 twl4030_add_widgets(codec);
2096
968a6025 2097 ret = snd_soc_init_card(socdev);
cc17557e
SS		 2098 if (ret < 0) {
2099 printk(KERN_ERR "twl4030: failed to register card\n");
2100 goto card_err;
2101 }
2102
2103 return ret;
2104
2105card_err:
2106 snd_soc_free_pcms(socdev);
2107 snd_soc_dapm_free(socdev);
2108pcm_err:
2109 kfree(codec->reg_cache);
2110 return ret;
2111}
2112
2113static struct snd_soc_device *twl4030_socdev;
2114
2115static int twl4030_probe(struct platform_device *pdev)
2116{
2117 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2118 struct snd_soc_codec *codec;
7393958f 2119 struct twl4030_priv *twl4030;
cc17557e
SS		 2120
2121 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
2122 if (codec == NULL)
2123 return -ENOMEM;
2124
7393958f
PU		 2125 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2126 if (twl4030 == NULL) {
2127 kfree(codec);
2128 return -ENOMEM;
2129 }
2130
2131 codec->private_data = twl4030;
6627a653 2132 socdev->card->codec = codec;
cc17557e
SS		 2133 mutex_init(&codec->mutex);
2134 INIT_LIST_HEAD(&codec->dapm_widgets);
2135 INIT_LIST_HEAD(&codec->dapm_paths);
2136
2137 twl4030_socdev = socdev;
2138 twl4030_init(socdev);
2139
2140 return 0;
2141}
2142
2143static int twl4030_remove(struct platform_device *pdev)
2144{
2145 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2146 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2147
2148 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 2149 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 2150 snd_soc_free_pcms(socdev);
2151 snd_soc_dapm_free(socdev);
7393958f 2152 kfree(codec->private_data);
cc17557e
SS		 2153 kfree(codec);
2154
2155 return 0;
2156}
2157
2158struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2159 .probe = twl4030_probe,
2160 .remove = twl4030_remove,
2161 .suspend = twl4030_suspend,
2162 .resume = twl4030_resume,
2163};
2164EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2165
24e07db8 2166static int __init twl4030_modinit(void)
64089b84 2167{
7154b3e8 2168 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 2169}
24e07db8 2170module_init(twl4030_modinit);
64089b84
MB		 2171
2172static void __exit twl4030_exit(void)
2173{
7154b3e8 2174 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 2175}
2176module_exit(twl4030_exit);
2177
cc17557e
SS		 2178MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2179MODULE_AUTHOR("Steve Sakoman");
2180MODULE_LICENSE("GPL");
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