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1 | /* |
2 | * wm8350.c -- WM8350 ALSA SoC audio driver | |
3 | * | |
4 | * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC. | |
5 | * | |
64ca0404 | 6 | * Author: Liam Girdwood <lrg@slimlogic.co.uk> |
40aa4a30 MB |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
40aa4a30 MB |
17 | #include <linux/delay.h> |
18 | #include <linux/pm.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/mfd/wm8350/audio.h> | |
21 | #include <linux/mfd/wm8350/core.h> | |
22 | #include <linux/regulator/consumer.h> | |
23 | #include <sound/core.h> | |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
27 | #include <sound/soc-dapm.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/tlv.h> | |
30 | ||
31 | #include "wm8350.h" | |
32 | ||
33 | #define WM8350_OUTn_0dB 0x39 | |
34 | ||
35 | #define WM8350_RAMP_NONE 0 | |
36 | #define WM8350_RAMP_UP 1 | |
37 | #define WM8350_RAMP_DOWN 2 | |
38 | ||
39 | /* We only include the analogue supplies here; the digital supplies | |
40 | * need to be available well before this driver can be probed. | |
41 | */ | |
42 | static const char *supply_names[] = { | |
43 | "AVDD", | |
44 | "HPVDD", | |
45 | }; | |
46 | ||
47 | struct wm8350_output { | |
48 | u16 active; | |
49 | u16 left_vol; | |
50 | u16 right_vol; | |
51 | u16 ramp; | |
52 | u16 mute; | |
53 | }; | |
54 | ||
a6ba2b2d MB |
55 | struct wm8350_jack_data { |
56 | struct snd_soc_jack *jack; | |
57 | int report; | |
2a0761a3 | 58 | int short_report; |
a6ba2b2d MB |
59 | }; |
60 | ||
40aa4a30 MB |
61 | struct wm8350_data { |
62 | struct snd_soc_codec codec; | |
63 | struct wm8350_output out1; | |
64 | struct wm8350_output out2; | |
a6ba2b2d MB |
65 | struct wm8350_jack_data hpl; |
66 | struct wm8350_jack_data hpr; | |
2a0761a3 | 67 | struct wm8350_jack_data mic; |
40aa4a30 | 68 | struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; |
f1e887de MB |
69 | int fll_freq_out; |
70 | int fll_freq_in; | |
40aa4a30 MB |
71 | }; |
72 | ||
73 | static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec, | |
74 | unsigned int reg) | |
75 | { | |
76 | struct wm8350 *wm8350 = codec->control_data; | |
77 | return wm8350->reg_cache[reg]; | |
78 | } | |
79 | ||
80 | static unsigned int wm8350_codec_read(struct snd_soc_codec *codec, | |
81 | unsigned int reg) | |
82 | { | |
83 | struct wm8350 *wm8350 = codec->control_data; | |
84 | return wm8350_reg_read(wm8350, reg); | |
85 | } | |
86 | ||
87 | static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg, | |
88 | unsigned int value) | |
89 | { | |
90 | struct wm8350 *wm8350 = codec->control_data; | |
91 | return wm8350_reg_write(wm8350, reg, value); | |
92 | } | |
93 | ||
94 | /* | |
95 | * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown. | |
96 | */ | |
97 | static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec) | |
98 | { | |
b2c812e2 | 99 | struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); |
40aa4a30 MB |
100 | struct wm8350_output *out1 = &wm8350_data->out1; |
101 | struct wm8350 *wm8350 = codec->control_data; | |
102 | int left_complete = 0, right_complete = 0; | |
103 | u16 reg, val; | |
104 | ||
105 | /* left channel */ | |
106 | reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME); | |
107 | val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; | |
108 | ||
109 | if (out1->ramp == WM8350_RAMP_UP) { | |
110 | /* ramp step up */ | |
111 | if (val < out1->left_vol) { | |
112 | val++; | |
113 | reg &= ~WM8350_OUT1L_VOL_MASK; | |
114 | wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, | |
115 | reg | (val << WM8350_OUT1L_VOL_SHIFT)); | |
116 | } else | |
117 | left_complete = 1; | |
118 | } else if (out1->ramp == WM8350_RAMP_DOWN) { | |
119 | /* ramp step down */ | |
120 | if (val > 0) { | |
121 | val--; | |
122 | reg &= ~WM8350_OUT1L_VOL_MASK; | |
123 | wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, | |
124 | reg | (val << WM8350_OUT1L_VOL_SHIFT)); | |
125 | } else | |
126 | left_complete = 1; | |
127 | } else | |
128 | return 1; | |
129 | ||
130 | /* right channel */ | |
131 | reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME); | |
132 | val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; | |
133 | if (out1->ramp == WM8350_RAMP_UP) { | |
134 | /* ramp step up */ | |
135 | if (val < out1->right_vol) { | |
136 | val++; | |
137 | reg &= ~WM8350_OUT1R_VOL_MASK; | |
138 | wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, | |
139 | reg | (val << WM8350_OUT1R_VOL_SHIFT)); | |
140 | } else | |
141 | right_complete = 1; | |
142 | } else if (out1->ramp == WM8350_RAMP_DOWN) { | |
143 | /* ramp step down */ | |
144 | if (val > 0) { | |
145 | val--; | |
146 | reg &= ~WM8350_OUT1R_VOL_MASK; | |
147 | wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, | |
148 | reg | (val << WM8350_OUT1R_VOL_SHIFT)); | |
149 | } else | |
150 | right_complete = 1; | |
151 | } | |
152 | ||
153 | /* only hit the update bit if either volume has changed this step */ | |
154 | if (!left_complete || !right_complete) | |
155 | wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU); | |
156 | ||
157 | return left_complete & right_complete; | |
158 | } | |
159 | ||
160 | /* | |
161 | * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown. | |
162 | */ | |
163 | static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec) | |
164 | { | |
b2c812e2 | 165 | struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); |
40aa4a30 MB |
166 | struct wm8350_output *out2 = &wm8350_data->out2; |
167 | struct wm8350 *wm8350 = codec->control_data; | |
168 | int left_complete = 0, right_complete = 0; | |
169 | u16 reg, val; | |
170 | ||
171 | /* left channel */ | |
172 | reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME); | |
173 | val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; | |
174 | if (out2->ramp == WM8350_RAMP_UP) { | |
175 | /* ramp step up */ | |
176 | if (val < out2->left_vol) { | |
177 | val++; | |
178 | reg &= ~WM8350_OUT2L_VOL_MASK; | |
179 | wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, | |
180 | reg | (val << WM8350_OUT1L_VOL_SHIFT)); | |
181 | } else | |
182 | left_complete = 1; | |
183 | } else if (out2->ramp == WM8350_RAMP_DOWN) { | |
184 | /* ramp step down */ | |
185 | if (val > 0) { | |
186 | val--; | |
187 | reg &= ~WM8350_OUT2L_VOL_MASK; | |
188 | wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, | |
189 | reg | (val << WM8350_OUT1L_VOL_SHIFT)); | |
190 | } else | |
191 | left_complete = 1; | |
192 | } else | |
193 | return 1; | |
194 | ||
195 | /* right channel */ | |
196 | reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME); | |
197 | val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; | |
198 | if (out2->ramp == WM8350_RAMP_UP) { | |
199 | /* ramp step up */ | |
200 | if (val < out2->right_vol) { | |
201 | val++; | |
202 | reg &= ~WM8350_OUT2R_VOL_MASK; | |
203 | wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, | |
204 | reg | (val << WM8350_OUT1R_VOL_SHIFT)); | |
205 | } else | |
206 | right_complete = 1; | |
207 | } else if (out2->ramp == WM8350_RAMP_DOWN) { | |
208 | /* ramp step down */ | |
209 | if (val > 0) { | |
210 | val--; | |
211 | reg &= ~WM8350_OUT2R_VOL_MASK; | |
212 | wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, | |
213 | reg | (val << WM8350_OUT1R_VOL_SHIFT)); | |
214 | } else | |
215 | right_complete = 1; | |
216 | } | |
217 | ||
218 | /* only hit the update bit if either volume has changed this step */ | |
219 | if (!left_complete || !right_complete) | |
220 | wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU); | |
221 | ||
222 | return left_complete & right_complete; | |
223 | } | |
224 | ||
225 | /* | |
226 | * This work ramps both output PGAs at stream start/stop time to | |
227 | * minimise pop associated with DAPM power switching. | |
228 | * It's best to enable Zero Cross when ramping occurs to minimise any | |
229 | * zipper noises. | |
230 | */ | |
231 | static void wm8350_pga_work(struct work_struct *work) | |
232 | { | |
ce6120cc LG |
233 | struct snd_soc_dapm_context *dapm = |
234 | container_of(work, struct snd_soc_dapm_context, delayed_work.work); | |
235 | struct snd_soc_codec *codec = dapm->codec; | |
b2c812e2 | 236 | struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); |
40aa4a30 MB |
237 | struct wm8350_output *out1 = &wm8350_data->out1, |
238 | *out2 = &wm8350_data->out2; | |
239 | int i, out1_complete, out2_complete; | |
240 | ||
241 | /* do we need to ramp at all ? */ | |
242 | if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE) | |
243 | return; | |
244 | ||
245 | /* PGA volumes have 6 bits of resolution to ramp */ | |
246 | for (i = 0; i <= 63; i++) { | |
247 | out1_complete = 1, out2_complete = 1; | |
248 | if (out1->ramp != WM8350_RAMP_NONE) | |
249 | out1_complete = wm8350_out1_ramp_step(codec); | |
250 | if (out2->ramp != WM8350_RAMP_NONE) | |
251 | out2_complete = wm8350_out2_ramp_step(codec); | |
252 | ||
253 | /* ramp finished ? */ | |
254 | if (out1_complete && out2_complete) | |
255 | break; | |
256 | ||
257 | /* we need to delay longer on the up ramp */ | |
258 | if (out1->ramp == WM8350_RAMP_UP || | |
259 | out2->ramp == WM8350_RAMP_UP) { | |
260 | /* delay is longer over 0dB as increases are larger */ | |
261 | if (i >= WM8350_OUTn_0dB) | |
262 | schedule_timeout_interruptible(msecs_to_jiffies | |
263 | (2)); | |
264 | else | |
265 | schedule_timeout_interruptible(msecs_to_jiffies | |
266 | (1)); | |
267 | } else | |
268 | udelay(50); /* doesn't matter if we delay longer */ | |
269 | } | |
270 | ||
271 | out1->ramp = WM8350_RAMP_NONE; | |
272 | out2->ramp = WM8350_RAMP_NONE; | |
273 | } | |
274 | ||
275 | /* | |
276 | * WM8350 Controls | |
277 | */ | |
278 | ||
279 | static int pga_event(struct snd_soc_dapm_widget *w, | |
280 | struct snd_kcontrol *kcontrol, int event) | |
281 | { | |
282 | struct snd_soc_codec *codec = w->codec; | |
b2c812e2 | 283 | struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); |
40aa4a30 MB |
284 | struct wm8350_output *out; |
285 | ||
286 | switch (w->shift) { | |
287 | case 0: | |
288 | case 1: | |
289 | out = &wm8350_data->out1; | |
290 | break; | |
291 | case 2: | |
292 | case 3: | |
293 | out = &wm8350_data->out2; | |
294 | break; | |
295 | ||
296 | default: | |
297 | BUG(); | |
298 | return -1; | |
299 | } | |
300 | ||
301 | switch (event) { | |
302 | case SND_SOC_DAPM_POST_PMU: | |
303 | out->ramp = WM8350_RAMP_UP; | |
304 | out->active = 1; | |
305 | ||
ce6120cc LG |
306 | if (!delayed_work_pending(&codec->dapm.delayed_work)) |
307 | schedule_delayed_work(&codec->dapm.delayed_work, | |
40aa4a30 MB |
308 | msecs_to_jiffies(1)); |
309 | break; | |
310 | ||
311 | case SND_SOC_DAPM_PRE_PMD: | |
312 | out->ramp = WM8350_RAMP_DOWN; | |
313 | out->active = 0; | |
314 | ||
ce6120cc LG |
315 | if (!delayed_work_pending(&codec->dapm.delayed_work)) |
316 | schedule_delayed_work(&codec->dapm.delayed_work, | |
40aa4a30 MB |
317 | msecs_to_jiffies(1)); |
318 | break; | |
319 | } | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol, | |
325 | struct snd_ctl_elem_value *ucontrol) | |
326 | { | |
327 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 328 | struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); |
40aa4a30 MB |
329 | struct wm8350_output *out = NULL; |
330 | struct soc_mixer_control *mc = | |
331 | (struct soc_mixer_control *)kcontrol->private_value; | |
332 | int ret; | |
333 | unsigned int reg = mc->reg; | |
334 | u16 val; | |
335 | ||
336 | /* For OUT1 and OUT2 we shadow the values and only actually write | |
337 | * them out when active in order to ensure the amplifier comes on | |
338 | * as quietly as possible. */ | |
339 | switch (reg) { | |
340 | case WM8350_LOUT1_VOLUME: | |
341 | out = &wm8350_priv->out1; | |
342 | break; | |
343 | case WM8350_LOUT2_VOLUME: | |
344 | out = &wm8350_priv->out2; | |
345 | break; | |
346 | default: | |
347 | break; | |
348 | } | |
349 | ||
350 | if (out) { | |
351 | out->left_vol = ucontrol->value.integer.value[0]; | |
352 | out->right_vol = ucontrol->value.integer.value[1]; | |
353 | if (!out->active) | |
354 | return 1; | |
355 | } | |
356 | ||
357 | ret = snd_soc_put_volsw_2r(kcontrol, ucontrol); | |
358 | if (ret < 0) | |
359 | return ret; | |
360 | ||
361 | /* now hit the volume update bits (always bit 8) */ | |
362 | val = wm8350_codec_read(codec, reg); | |
363 | wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU); | |
364 | return 1; | |
365 | } | |
366 | ||
367 | static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol, | |
368 | struct snd_ctl_elem_value *ucontrol) | |
369 | { | |
370 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 371 | struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); |
40aa4a30 MB |
372 | struct wm8350_output *out1 = &wm8350_priv->out1; |
373 | struct wm8350_output *out2 = &wm8350_priv->out2; | |
374 | struct soc_mixer_control *mc = | |
375 | (struct soc_mixer_control *)kcontrol->private_value; | |
376 | unsigned int reg = mc->reg; | |
377 | ||
378 | /* If these are cached registers use the cache */ | |
379 | switch (reg) { | |
380 | case WM8350_LOUT1_VOLUME: | |
381 | ucontrol->value.integer.value[0] = out1->left_vol; | |
382 | ucontrol->value.integer.value[1] = out1->right_vol; | |
383 | return 0; | |
384 | ||
385 | case WM8350_LOUT2_VOLUME: | |
386 | ucontrol->value.integer.value[0] = out2->left_vol; | |
387 | ucontrol->value.integer.value[1] = out2->right_vol; | |
388 | return 0; | |
389 | ||
390 | default: | |
391 | break; | |
392 | } | |
393 | ||
394 | return snd_soc_get_volsw_2r(kcontrol, ucontrol); | |
395 | } | |
396 | ||
397 | /* double control with volume update */ | |
398 | #define SOC_WM8350_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \ | |
399 | xinvert, tlv_array) \ | |
400 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ | |
401 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ | |
402 | SNDRV_CTL_ELEM_ACCESS_READWRITE | \ | |
403 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
404 | .tlv.p = (tlv_array), \ | |
405 | .info = snd_soc_info_volsw_2r, \ | |
406 | .get = wm8350_get_volsw_2r, .put = wm8350_put_volsw_2r_vu, \ | |
407 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
408 | {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ | |
409 | .rshift = xshift, .max = xmax, .invert = xinvert}, } | |
410 | ||
411 | static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" }; | |
412 | static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" }; | |
413 | static const char *wm8350_dacmutem[] = { "Normal", "Soft" }; | |
414 | static const char *wm8350_dacmutes[] = { "Fast", "Slow" }; | |
40aa4a30 MB |
415 | static const char *wm8350_adcfilter[] = { "None", "High Pass" }; |
416 | static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" }; | |
417 | static const char *wm8350_lr[] = { "Left", "Right" }; | |
418 | ||
419 | static const struct soc_enum wm8350_enum[] = { | |
420 | SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp), | |
421 | SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol), | |
422 | SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem), | |
423 | SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes), | |
40aa4a30 MB |
424 | SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter), |
425 | SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp), | |
426 | SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol), | |
427 | SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr), | |
428 | }; | |
429 | ||
e6a08c5a MB |
430 | static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0); |
431 | static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0); | |
40aa4a30 MB |
432 | static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1); |
433 | static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1); | |
434 | static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1); | |
435 | ||
436 | static const unsigned int capture_sd_tlv[] = { | |
437 | TLV_DB_RANGE_HEAD(2), | |
438 | 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1), | |
439 | 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0), | |
440 | }; | |
441 | ||
442 | static const struct snd_kcontrol_new wm8350_snd_controls[] = { | |
443 | SOC_ENUM("Playback Deemphasis", wm8350_enum[0]), | |
444 | SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]), | |
445 | SOC_WM8350_DOUBLE_R_TLV("Playback PCM Volume", | |
446 | WM8350_DAC_DIGITAL_VOLUME_L, | |
447 | WM8350_DAC_DIGITAL_VOLUME_R, | |
448 | 0, 255, 0, dac_pcm_tlv), | |
449 | SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]), | |
450 | SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]), | |
61943999 MB |
451 | SOC_ENUM("Capture PCM Filter", wm8350_enum[4]), |
452 | SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]), | |
453 | SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]), | |
40aa4a30 MB |
454 | SOC_WM8350_DOUBLE_R_TLV("Capture PCM Volume", |
455 | WM8350_ADC_DIGITAL_VOLUME_L, | |
456 | WM8350_ADC_DIGITAL_VOLUME_R, | |
457 | 0, 255, 0, adc_pcm_tlv), | |
458 | SOC_DOUBLE_TLV("Capture Sidetone Volume", | |
459 | WM8350_ADC_DIVIDER, | |
460 | 8, 4, 15, 1, capture_sd_tlv), | |
461 | SOC_WM8350_DOUBLE_R_TLV("Capture Volume", | |
462 | WM8350_LEFT_INPUT_VOLUME, | |
463 | WM8350_RIGHT_INPUT_VOLUME, | |
464 | 2, 63, 0, pre_amp_tlv), | |
465 | SOC_DOUBLE_R("Capture ZC Switch", | |
466 | WM8350_LEFT_INPUT_VOLUME, | |
467 | WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0), | |
468 | SOC_SINGLE_TLV("Left Input Left Sidetone Volume", | |
469 | WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv), | |
470 | SOC_SINGLE_TLV("Left Input Right Sidetone Volume", | |
471 | WM8350_OUTPUT_LEFT_MIXER_VOLUME, | |
472 | 5, 7, 0, out_mix_tlv), | |
473 | SOC_SINGLE_TLV("Left Input Bypass Volume", | |
474 | WM8350_OUTPUT_LEFT_MIXER_VOLUME, | |
475 | 9, 7, 0, out_mix_tlv), | |
476 | SOC_SINGLE_TLV("Right Input Left Sidetone Volume", | |
477 | WM8350_OUTPUT_RIGHT_MIXER_VOLUME, | |
478 | 1, 7, 0, out_mix_tlv), | |
479 | SOC_SINGLE_TLV("Right Input Right Sidetone Volume", | |
480 | WM8350_OUTPUT_RIGHT_MIXER_VOLUME, | |
481 | 5, 7, 0, out_mix_tlv), | |
482 | SOC_SINGLE_TLV("Right Input Bypass Volume", | |
483 | WM8350_OUTPUT_RIGHT_MIXER_VOLUME, | |
484 | 13, 7, 0, out_mix_tlv), | |
485 | SOC_SINGLE("Left Input Mixer +20dB Switch", | |
486 | WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0), | |
487 | SOC_SINGLE("Right Input Mixer +20dB Switch", | |
488 | WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0), | |
489 | SOC_SINGLE_TLV("Out4 Capture Volume", | |
490 | WM8350_INPUT_MIXER_VOLUME, | |
491 | 1, 7, 0, out_mix_tlv), | |
492 | SOC_WM8350_DOUBLE_R_TLV("Out1 Playback Volume", | |
493 | WM8350_LOUT1_VOLUME, | |
494 | WM8350_ROUT1_VOLUME, | |
495 | 2, 63, 0, out_pga_tlv), | |
496 | SOC_DOUBLE_R("Out1 Playback ZC Switch", | |
497 | WM8350_LOUT1_VOLUME, | |
498 | WM8350_ROUT1_VOLUME, 13, 1, 0), | |
499 | SOC_WM8350_DOUBLE_R_TLV("Out2 Playback Volume", | |
500 | WM8350_LOUT2_VOLUME, | |
501 | WM8350_ROUT2_VOLUME, | |
502 | 2, 63, 0, out_pga_tlv), | |
503 | SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME, | |
504 | WM8350_ROUT2_VOLUME, 13, 1, 0), | |
505 | SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0), | |
506 | SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME, | |
507 | 5, 7, 0, out_mix_tlv), | |
508 | ||
509 | SOC_DOUBLE_R("Out1 Playback Switch", | |
510 | WM8350_LOUT1_VOLUME, | |
511 | WM8350_ROUT1_VOLUME, | |
512 | 14, 1, 1), | |
513 | SOC_DOUBLE_R("Out2 Playback Switch", | |
514 | WM8350_LOUT2_VOLUME, | |
515 | WM8350_ROUT2_VOLUME, | |
516 | 14, 1, 1), | |
517 | }; | |
518 | ||
519 | /* | |
520 | * DAPM Controls | |
521 | */ | |
522 | ||
523 | /* Left Playback Mixer */ | |
524 | static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = { | |
525 | SOC_DAPM_SINGLE("Playback Switch", | |
526 | WM8350_LEFT_MIXER_CONTROL, 11, 1, 0), | |
527 | SOC_DAPM_SINGLE("Left Bypass Switch", | |
528 | WM8350_LEFT_MIXER_CONTROL, 2, 1, 0), | |
529 | SOC_DAPM_SINGLE("Right Playback Switch", | |
530 | WM8350_LEFT_MIXER_CONTROL, 12, 1, 0), | |
531 | SOC_DAPM_SINGLE("Left Sidetone Switch", | |
532 | WM8350_LEFT_MIXER_CONTROL, 0, 1, 0), | |
533 | SOC_DAPM_SINGLE("Right Sidetone Switch", | |
534 | WM8350_LEFT_MIXER_CONTROL, 1, 1, 0), | |
535 | }; | |
536 | ||
537 | /* Right Playback Mixer */ | |
538 | static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = { | |
539 | SOC_DAPM_SINGLE("Playback Switch", | |
540 | WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0), | |
541 | SOC_DAPM_SINGLE("Right Bypass Switch", | |
542 | WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0), | |
543 | SOC_DAPM_SINGLE("Left Playback Switch", | |
544 | WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0), | |
545 | SOC_DAPM_SINGLE("Left Sidetone Switch", | |
546 | WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0), | |
547 | SOC_DAPM_SINGLE("Right Sidetone Switch", | |
548 | WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0), | |
549 | }; | |
550 | ||
551 | /* Out4 Mixer */ | |
552 | static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = { | |
553 | SOC_DAPM_SINGLE("Right Playback Switch", | |
554 | WM8350_OUT4_MIXER_CONTROL, 12, 1, 0), | |
555 | SOC_DAPM_SINGLE("Left Playback Switch", | |
556 | WM8350_OUT4_MIXER_CONTROL, 11, 1, 0), | |
557 | SOC_DAPM_SINGLE("Right Capture Switch", | |
558 | WM8350_OUT4_MIXER_CONTROL, 9, 1, 0), | |
559 | SOC_DAPM_SINGLE("Out3 Playback Switch", | |
560 | WM8350_OUT4_MIXER_CONTROL, 2, 1, 0), | |
561 | SOC_DAPM_SINGLE("Right Mixer Switch", | |
562 | WM8350_OUT4_MIXER_CONTROL, 1, 1, 0), | |
563 | SOC_DAPM_SINGLE("Left Mixer Switch", | |
564 | WM8350_OUT4_MIXER_CONTROL, 0, 1, 0), | |
565 | }; | |
566 | ||
567 | /* Out3 Mixer */ | |
568 | static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = { | |
569 | SOC_DAPM_SINGLE("Left Playback Switch", | |
570 | WM8350_OUT3_MIXER_CONTROL, 11, 1, 0), | |
571 | SOC_DAPM_SINGLE("Left Capture Switch", | |
572 | WM8350_OUT3_MIXER_CONTROL, 8, 1, 0), | |
573 | SOC_DAPM_SINGLE("Out4 Playback Switch", | |
574 | WM8350_OUT3_MIXER_CONTROL, 3, 1, 0), | |
575 | SOC_DAPM_SINGLE("Left Mixer Switch", | |
576 | WM8350_OUT3_MIXER_CONTROL, 0, 1, 0), | |
577 | }; | |
578 | ||
579 | /* Left Input Mixer */ | |
580 | static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = { | |
581 | SOC_DAPM_SINGLE_TLV("L2 Capture Volume", | |
582 | WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv), | |
583 | SOC_DAPM_SINGLE_TLV("L3 Capture Volume", | |
584 | WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv), | |
585 | SOC_DAPM_SINGLE("PGA Capture Switch", | |
5b7dde34 | 586 | WM8350_LEFT_INPUT_VOLUME, 14, 1, 1), |
40aa4a30 MB |
587 | }; |
588 | ||
589 | /* Right Input Mixer */ | |
590 | static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = { | |
591 | SOC_DAPM_SINGLE_TLV("L2 Capture Volume", | |
592 | WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv), | |
593 | SOC_DAPM_SINGLE_TLV("L3 Capture Volume", | |
594 | WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv), | |
595 | SOC_DAPM_SINGLE("PGA Capture Switch", | |
5b7dde34 | 596 | WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1), |
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597 | }; |
598 | ||
599 | /* Left Mic Mixer */ | |
600 | static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = { | |
601 | SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0), | |
602 | SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0), | |
603 | SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0), | |
604 | }; | |
605 | ||
606 | /* Right Mic Mixer */ | |
607 | static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = { | |
608 | SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0), | |
609 | SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0), | |
610 | SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0), | |
611 | }; | |
612 | ||
613 | /* Beep Switch */ | |
614 | static const struct snd_kcontrol_new wm8350_beep_switch_controls = | |
615 | SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1); | |
616 | ||
617 | /* Out4 Capture Mux */ | |
618 | static const struct snd_kcontrol_new wm8350_out4_capture_controls = | |
87831cb6 | 619 | SOC_DAPM_ENUM("Route", wm8350_enum[7]); |
40aa4a30 MB |
620 | |
621 | static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = { | |
622 | ||
623 | SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0), | |
624 | SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0), | |
625 | SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL, | |
626 | 0, pga_event, | |
627 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
628 | SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0, | |
629 | pga_event, | |
630 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
631 | SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL, | |
632 | 0, pga_event, | |
633 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
634 | SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0, | |
635 | pga_event, | |
636 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
637 | ||
638 | SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2, | |
639 | 7, 0, &wm8350_right_capt_mixer_controls[0], | |
640 | ARRAY_SIZE(wm8350_right_capt_mixer_controls)), | |
641 | ||
642 | SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2, | |
643 | 6, 0, &wm8350_left_capt_mixer_controls[0], | |
644 | ARRAY_SIZE(wm8350_left_capt_mixer_controls)), | |
645 | ||
646 | SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0, | |
647 | &wm8350_out4_mixer_controls[0], | |
648 | ARRAY_SIZE(wm8350_out4_mixer_controls)), | |
649 | ||
650 | SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0, | |
651 | &wm8350_out3_mixer_controls[0], | |
652 | ARRAY_SIZE(wm8350_out3_mixer_controls)), | |
653 | ||
654 | SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0, | |
655 | &wm8350_right_play_mixer_controls[0], | |
656 | ARRAY_SIZE(wm8350_right_play_mixer_controls)), | |
657 | ||
658 | SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0, | |
659 | &wm8350_left_play_mixer_controls[0], | |
660 | ARRAY_SIZE(wm8350_left_play_mixer_controls)), | |
661 | ||
662 | SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0, | |
663 | &wm8350_left_mic_mixer_controls[0], | |
664 | ARRAY_SIZE(wm8350_left_mic_mixer_controls)), | |
665 | ||
666 | SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0, | |
667 | &wm8350_right_mic_mixer_controls[0], | |
668 | ARRAY_SIZE(wm8350_right_mic_mixer_controls)), | |
669 | ||
670 | /* virtual mixer for Beep and Out2R */ | |
671 | SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), | |
672 | ||
673 | SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0, | |
674 | &wm8350_beep_switch_controls), | |
675 | ||
676 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", | |
677 | WM8350_POWER_MGMT_4, 3, 0), | |
678 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", | |
679 | WM8350_POWER_MGMT_4, 2, 0), | |
680 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", | |
681 | WM8350_POWER_MGMT_4, 5, 0), | |
682 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", | |
683 | WM8350_POWER_MGMT_4, 4, 0), | |
684 | ||
685 | SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0), | |
686 | ||
687 | SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0, | |
688 | &wm8350_out4_capture_controls), | |
689 | ||
690 | SND_SOC_DAPM_OUTPUT("OUT1R"), | |
691 | SND_SOC_DAPM_OUTPUT("OUT1L"), | |
692 | SND_SOC_DAPM_OUTPUT("OUT2R"), | |
693 | SND_SOC_DAPM_OUTPUT("OUT2L"), | |
694 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
695 | SND_SOC_DAPM_OUTPUT("OUT4"), | |
696 | ||
697 | SND_SOC_DAPM_INPUT("IN1RN"), | |
698 | SND_SOC_DAPM_INPUT("IN1RP"), | |
699 | SND_SOC_DAPM_INPUT("IN2R"), | |
700 | SND_SOC_DAPM_INPUT("IN1LP"), | |
701 | SND_SOC_DAPM_INPUT("IN1LN"), | |
702 | SND_SOC_DAPM_INPUT("IN2L"), | |
703 | SND_SOC_DAPM_INPUT("IN3R"), | |
704 | SND_SOC_DAPM_INPUT("IN3L"), | |
705 | }; | |
706 | ||
707 | static const struct snd_soc_dapm_route audio_map[] = { | |
708 | ||
709 | /* left playback mixer */ | |
710 | {"Left Playback Mixer", "Playback Switch", "Left DAC"}, | |
711 | {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"}, | |
712 | {"Left Playback Mixer", "Right Playback Switch", "Right DAC"}, | |
713 | {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, | |
714 | {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, | |
715 | ||
716 | /* right playback mixer */ | |
717 | {"Right Playback Mixer", "Playback Switch", "Right DAC"}, | |
718 | {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"}, | |
719 | {"Right Playback Mixer", "Left Playback Switch", "Left DAC"}, | |
720 | {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, | |
721 | {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, | |
722 | ||
723 | /* out4 playback mixer */ | |
724 | {"Out4 Mixer", "Right Playback Switch", "Right DAC"}, | |
725 | {"Out4 Mixer", "Left Playback Switch", "Left DAC"}, | |
726 | {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"}, | |
727 | {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"}, | |
728 | {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"}, | |
729 | {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, | |
730 | {"OUT4", NULL, "Out4 Mixer"}, | |
731 | ||
732 | /* out3 playback mixer */ | |
733 | {"Out3 Mixer", "Left Playback Switch", "Left DAC"}, | |
734 | {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"}, | |
735 | {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, | |
736 | {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"}, | |
737 | {"OUT3", NULL, "Out3 Mixer"}, | |
738 | ||
739 | /* out2 */ | |
740 | {"Right Out2 PGA", NULL, "Right Playback Mixer"}, | |
741 | {"Left Out2 PGA", NULL, "Left Playback Mixer"}, | |
742 | {"OUT2L", NULL, "Left Out2 PGA"}, | |
743 | {"OUT2R", NULL, "Right Out2 PGA"}, | |
744 | ||
745 | /* out1 */ | |
746 | {"Right Out1 PGA", NULL, "Right Playback Mixer"}, | |
747 | {"Left Out1 PGA", NULL, "Left Playback Mixer"}, | |
748 | {"OUT1L", NULL, "Left Out1 PGA"}, | |
749 | {"OUT1R", NULL, "Right Out1 PGA"}, | |
750 | ||
751 | /* ADCs */ | |
752 | {"Left ADC", NULL, "Left Capture Mixer"}, | |
753 | {"Right ADC", NULL, "Right Capture Mixer"}, | |
754 | ||
755 | /* Left capture mixer */ | |
756 | {"Left Capture Mixer", "L2 Capture Volume", "IN2L"}, | |
757 | {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"}, | |
758 | {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"}, | |
759 | {"Left Capture Mixer", NULL, "Out4 Capture Channel"}, | |
760 | ||
761 | /* Right capture mixer */ | |
762 | {"Right Capture Mixer", "L2 Capture Volume", "IN2R"}, | |
763 | {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"}, | |
764 | {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"}, | |
765 | {"Right Capture Mixer", NULL, "Out4 Capture Channel"}, | |
766 | ||
767 | /* L3 Inputs */ | |
768 | {"IN3L PGA", NULL, "IN3L"}, | |
769 | {"IN3R PGA", NULL, "IN3R"}, | |
770 | ||
771 | /* Left Mic mixer */ | |
772 | {"Left Mic Mixer", "INN Capture Switch", "IN1LN"}, | |
773 | {"Left Mic Mixer", "INP Capture Switch", "IN1LP"}, | |
774 | {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"}, | |
775 | ||
776 | /* Right Mic mixer */ | |
777 | {"Right Mic Mixer", "INN Capture Switch", "IN1RN"}, | |
778 | {"Right Mic Mixer", "INP Capture Switch", "IN1RP"}, | |
779 | {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"}, | |
780 | ||
781 | /* out 4 capture */ | |
782 | {"Out4 Capture Channel", NULL, "Out4 Mixer"}, | |
783 | ||
784 | /* Beep */ | |
785 | {"Beep", NULL, "IN3R PGA"}, | |
786 | }; | |
787 | ||
40aa4a30 MB |
788 | static int wm8350_add_widgets(struct snd_soc_codec *codec) |
789 | { | |
ce6120cc | 790 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
40aa4a30 MB |
791 | int ret; |
792 | ||
ce6120cc | 793 | ret = snd_soc_dapm_new_controls(dapm, |
40aa4a30 MB |
794 | wm8350_dapm_widgets, |
795 | ARRAY_SIZE(wm8350_dapm_widgets)); | |
796 | if (ret != 0) { | |
797 | dev_err(codec->dev, "dapm control register failed\n"); | |
798 | return ret; | |
799 | } | |
800 | ||
801 | /* set up audio paths */ | |
ce6120cc | 802 | ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); |
40aa4a30 MB |
803 | if (ret != 0) { |
804 | dev_err(codec->dev, "DAPM route register failed\n"); | |
805 | return ret; | |
806 | } | |
807 | ||
0a3f5e35 | 808 | return 0; |
40aa4a30 MB |
809 | } |
810 | ||
811 | static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
812 | int clk_id, unsigned int freq, int dir) | |
813 | { | |
814 | struct snd_soc_codec *codec = codec_dai->codec; | |
815 | struct wm8350 *wm8350 = codec->control_data; | |
816 | u16 fll_4; | |
817 | ||
818 | switch (clk_id) { | |
819 | case WM8350_MCLK_SEL_MCLK: | |
820 | wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1, | |
821 | WM8350_MCLK_SEL); | |
822 | break; | |
823 | case WM8350_MCLK_SEL_PLL_MCLK: | |
824 | case WM8350_MCLK_SEL_PLL_DAC: | |
825 | case WM8350_MCLK_SEL_PLL_ADC: | |
826 | case WM8350_MCLK_SEL_PLL_32K: | |
827 | wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1, | |
828 | WM8350_MCLK_SEL); | |
829 | fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & | |
830 | ~WM8350_FLL_CLK_SRC_MASK; | |
831 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id); | |
832 | break; | |
833 | } | |
834 | ||
835 | /* MCLK direction */ | |
836 | if (dir == WM8350_MCLK_DIR_OUT) | |
837 | wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2, | |
838 | WM8350_MCLK_DIR); | |
839 | else | |
840 | wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2, | |
841 | WM8350_MCLK_DIR); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) | |
847 | { | |
848 | struct snd_soc_codec *codec = codec_dai->codec; | |
849 | u16 val; | |
850 | ||
851 | switch (div_id) { | |
852 | case WM8350_ADC_CLKDIV: | |
853 | val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) & | |
854 | ~WM8350_ADC_CLKDIV_MASK; | |
855 | wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div); | |
856 | break; | |
857 | case WM8350_DAC_CLKDIV: | |
858 | val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) & | |
859 | ~WM8350_DAC_CLKDIV_MASK; | |
860 | wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div); | |
861 | break; | |
862 | case WM8350_BCLK_CLKDIV: | |
863 | val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & | |
864 | ~WM8350_BCLK_DIV_MASK; | |
865 | wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); | |
866 | break; | |
867 | case WM8350_OPCLK_CLKDIV: | |
868 | val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & | |
869 | ~WM8350_OPCLK_DIV_MASK; | |
870 | wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); | |
871 | break; | |
872 | case WM8350_SYS_CLKDIV: | |
873 | val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & | |
874 | ~WM8350_MCLK_DIV_MASK; | |
875 | wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); | |
876 | break; | |
877 | case WM8350_DACLR_CLKDIV: | |
878 | val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & | |
879 | ~WM8350_DACLRC_RATE_MASK; | |
880 | wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div); | |
881 | break; | |
882 | case WM8350_ADCLR_CLKDIV: | |
883 | val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & | |
884 | ~WM8350_ADCLRC_RATE_MASK; | |
885 | wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div); | |
886 | break; | |
887 | default: | |
888 | return -EINVAL; | |
889 | } | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
894 | static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
895 | { | |
896 | struct snd_soc_codec *codec = codec_dai->codec; | |
897 | u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & | |
898 | ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK); | |
899 | u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) & | |
900 | ~WM8350_BCLK_MSTR; | |
901 | u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & | |
902 | ~WM8350_DACLRC_ENA; | |
903 | u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & | |
904 | ~WM8350_ADCLRC_ENA; | |
905 | ||
906 | /* set master/slave audio interface */ | |
907 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
908 | case SND_SOC_DAIFMT_CBM_CFM: | |
909 | master |= WM8350_BCLK_MSTR; | |
910 | dac_lrc |= WM8350_DACLRC_ENA; | |
911 | adc_lrc |= WM8350_ADCLRC_ENA; | |
912 | break; | |
913 | case SND_SOC_DAIFMT_CBS_CFS: | |
914 | break; | |
915 | default: | |
916 | return -EINVAL; | |
917 | } | |
918 | ||
919 | /* interface format */ | |
920 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
921 | case SND_SOC_DAIFMT_I2S: | |
922 | iface |= 0x2 << 8; | |
923 | break; | |
924 | case SND_SOC_DAIFMT_RIGHT_J: | |
925 | break; | |
926 | case SND_SOC_DAIFMT_LEFT_J: | |
927 | iface |= 0x1 << 8; | |
928 | break; | |
929 | case SND_SOC_DAIFMT_DSP_A: | |
930 | iface |= 0x3 << 8; | |
931 | break; | |
932 | case SND_SOC_DAIFMT_DSP_B: | |
5ee518ec | 933 | iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV; |
40aa4a30 MB |
934 | break; |
935 | default: | |
936 | return -EINVAL; | |
937 | } | |
938 | ||
939 | /* clock inversion */ | |
940 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
941 | case SND_SOC_DAIFMT_NB_NF: | |
942 | break; | |
943 | case SND_SOC_DAIFMT_IB_IF: | |
944 | iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV; | |
945 | break; | |
946 | case SND_SOC_DAIFMT_IB_NF: | |
947 | iface |= WM8350_AIF_BCLK_INV; | |
948 | break; | |
949 | case SND_SOC_DAIFMT_NB_IF: | |
950 | iface |= WM8350_AIF_LRCLK_INV; | |
951 | break; | |
952 | default: | |
953 | return -EINVAL; | |
954 | } | |
955 | ||
956 | wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); | |
957 | wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master); | |
958 | wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc); | |
959 | wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc); | |
960 | return 0; | |
961 | } | |
962 | ||
963 | static int wm8350_pcm_trigger(struct snd_pcm_substream *substream, | |
964 | int cmd, struct snd_soc_dai *codec_dai) | |
965 | { | |
966 | struct snd_soc_codec *codec = codec_dai->codec; | |
967 | int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) & | |
968 | WM8350_BCLK_MSTR; | |
969 | int enabled = 0; | |
970 | ||
971 | /* Check that the DACs or ADCs are enabled since they are | |
972 | * required for LRC in master mode. The DACs or ADCs need a | |
973 | * valid audio path i.e. pin -> ADC or DAC -> pin before | |
974 | * the LRC will be enabled in master mode. */ | |
5e42336a | 975 | if (!master || cmd != SNDRV_PCM_TRIGGER_START) |
40aa4a30 MB |
976 | return 0; |
977 | ||
978 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { | |
979 | enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) & | |
980 | (WM8350_ADCR_ENA | WM8350_ADCL_ENA); | |
981 | } else { | |
982 | enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) & | |
983 | (WM8350_DACR_ENA | WM8350_DACL_ENA); | |
984 | } | |
985 | ||
986 | if (!enabled) { | |
987 | dev_err(codec->dev, | |
988 | "%s: invalid audio path - no clocks available\n", | |
989 | __func__); | |
990 | return -EINVAL; | |
991 | } | |
992 | return 0; | |
993 | } | |
994 | ||
995 | static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream, | |
996 | struct snd_pcm_hw_params *params, | |
997 | struct snd_soc_dai *codec_dai) | |
998 | { | |
999 | struct snd_soc_codec *codec = codec_dai->codec; | |
61943999 | 1000 | struct wm8350 *wm8350 = codec->control_data; |
40aa4a30 MB |
1001 | u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & |
1002 | ~WM8350_AIF_WL_MASK; | |
1003 | ||
1004 | /* bit size */ | |
1005 | switch (params_format(params)) { | |
1006 | case SNDRV_PCM_FORMAT_S16_LE: | |
1007 | break; | |
1008 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1009 | iface |= 0x1 << 10; | |
1010 | break; | |
1011 | case SNDRV_PCM_FORMAT_S24_LE: | |
1012 | iface |= 0x2 << 10; | |
1013 | break; | |
1014 | case SNDRV_PCM_FORMAT_S32_LE: | |
1015 | iface |= 0x3 << 10; | |
1016 | break; | |
1017 | } | |
1018 | ||
1019 | wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); | |
61943999 MB |
1020 | |
1021 | /* The sloping stopband filter is recommended for use with | |
1022 | * lower sample rates to improve performance. | |
1023 | */ | |
1024 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1025 | if (params_rate(params) < 24000) | |
1026 | wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME, | |
1027 | WM8350_DAC_SB_FILT); | |
1028 | else | |
1029 | wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME, | |
1030 | WM8350_DAC_SB_FILT); | |
1031 | } | |
1032 | ||
40aa4a30 MB |
1033 | return 0; |
1034 | } | |
1035 | ||
1036 | static int wm8350_mute(struct snd_soc_dai *dai, int mute) | |
1037 | { | |
1038 | struct snd_soc_codec *codec = dai->codec; | |
1039 | struct wm8350 *wm8350 = codec->control_data; | |
1040 | ||
1041 | if (mute) | |
1042 | wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); | |
1043 | else | |
1044 | wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); | |
1045 | return 0; | |
1046 | } | |
1047 | ||
1048 | /* FLL divisors */ | |
1049 | struct _fll_div { | |
1050 | int div; /* FLL_OUTDIV */ | |
1051 | int n; | |
1052 | int k; | |
1053 | int ratio; /* FLL_FRATIO */ | |
1054 | }; | |
1055 | ||
1056 | /* The size in bits of the fll divide multiplied by 10 | |
1057 | * to allow rounding later */ | |
1058 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1059 | ||
1060 | static inline int fll_factors(struct _fll_div *fll_div, unsigned int input, | |
1061 | unsigned int output) | |
1062 | { | |
1063 | u64 Kpart; | |
1064 | unsigned int t1, t2, K, Nmod; | |
1065 | ||
1066 | if (output >= 2815250 && output <= 3125000) | |
1067 | fll_div->div = 0x4; | |
1068 | else if (output >= 5625000 && output <= 6250000) | |
1069 | fll_div->div = 0x3; | |
1070 | else if (output >= 11250000 && output <= 12500000) | |
1071 | fll_div->div = 0x2; | |
1072 | else if (output >= 22500000 && output <= 25000000) | |
1073 | fll_div->div = 0x1; | |
1074 | else { | |
1075 | printk(KERN_ERR "wm8350: fll freq %d out of range\n", output); | |
1076 | return -EINVAL; | |
1077 | } | |
1078 | ||
1079 | if (input > 48000) | |
1080 | fll_div->ratio = 1; | |
1081 | else | |
1082 | fll_div->ratio = 8; | |
1083 | ||
1084 | t1 = output * (1 << (fll_div->div + 1)); | |
1085 | t2 = input * fll_div->ratio; | |
1086 | ||
1087 | fll_div->n = t1 / t2; | |
1088 | Nmod = t1 % t2; | |
1089 | ||
1090 | if (Nmod) { | |
1091 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1092 | do_div(Kpart, t2); | |
1093 | K = Kpart & 0xFFFFFFFF; | |
1094 | ||
1095 | /* Check if we need to round */ | |
1096 | if ((K % 10) >= 5) | |
1097 | K += 5; | |
1098 | ||
1099 | /* Move down to proper range now rounding is done */ | |
1100 | K /= 10; | |
1101 | fll_div->k = K; | |
1102 | } else | |
1103 | fll_div->k = 0; | |
1104 | ||
1105 | return 0; | |
1106 | } | |
1107 | ||
1108 | static int wm8350_set_fll(struct snd_soc_dai *codec_dai, | |
85488037 | 1109 | int pll_id, int source, unsigned int freq_in, |
40aa4a30 MB |
1110 | unsigned int freq_out) |
1111 | { | |
1112 | struct snd_soc_codec *codec = codec_dai->codec; | |
1113 | struct wm8350 *wm8350 = codec->control_data; | |
b2c812e2 | 1114 | struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); |
40aa4a30 MB |
1115 | struct _fll_div fll_div; |
1116 | int ret = 0; | |
1117 | u16 fll_1, fll_4; | |
1118 | ||
f1e887de MB |
1119 | if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out) |
1120 | return 0; | |
1121 | ||
40aa4a30 MB |
1122 | /* power down FLL - we need to do this for reconfiguration */ |
1123 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, | |
1124 | WM8350_FLL_ENA | WM8350_FLL_OSC_ENA); | |
1125 | ||
1126 | if (freq_out == 0 || freq_in == 0) | |
1127 | return ret; | |
1128 | ||
1129 | ret = fll_factors(&fll_div, freq_in, freq_out); | |
1130 | if (ret < 0) | |
1131 | return ret; | |
1132 | dev_dbg(wm8350->dev, | |
449bd54d | 1133 | "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d", |
40aa4a30 MB |
1134 | freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div, |
1135 | fll_div.ratio); | |
1136 | ||
1137 | /* set up N.K & dividers */ | |
1138 | fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) & | |
1139 | ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000); | |
1140 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_1, | |
1141 | fll_1 | (fll_div.div << 8) | 0x50); | |
1142 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_2, | |
1143 | (fll_div.ratio << 11) | (fll_div. | |
1144 | n & WM8350_FLL_N_MASK)); | |
1145 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k); | |
1146 | fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & | |
1147 | ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF); | |
1148 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, | |
1149 | fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) | | |
1150 | (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0)); | |
1151 | ||
1152 | /* power FLL on */ | |
1153 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA); | |
1154 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA); | |
1155 | ||
f1e887de MB |
1156 | priv->fll_freq_out = freq_out; |
1157 | priv->fll_freq_in = freq_in; | |
1158 | ||
40aa4a30 MB |
1159 | return 0; |
1160 | } | |
1161 | ||
1162 | static int wm8350_set_bias_level(struct snd_soc_codec *codec, | |
1163 | enum snd_soc_bias_level level) | |
1164 | { | |
1165 | struct wm8350 *wm8350 = codec->control_data; | |
b2c812e2 | 1166 | struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); |
40aa4a30 MB |
1167 | struct wm8350_audio_platform_data *platform = |
1168 | wm8350->codec.platform_data; | |
1169 | u16 pm1; | |
1170 | int ret; | |
1171 | ||
1172 | switch (level) { | |
1173 | case SND_SOC_BIAS_ON: | |
1174 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1175 | ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); | |
1176 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1177 | pm1 | WM8350_VMID_50K | | |
1178 | platform->codec_current_on << 14); | |
1179 | break; | |
1180 | ||
1181 | case SND_SOC_BIAS_PREPARE: | |
1182 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1); | |
1183 | pm1 &= ~WM8350_VMID_MASK; | |
1184 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1185 | pm1 | WM8350_VMID_50K); | |
1186 | break; | |
1187 | ||
1188 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 1189 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
40aa4a30 MB |
1190 | ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), |
1191 | priv->supplies); | |
1192 | if (ret != 0) | |
1193 | return ret; | |
1194 | ||
1195 | /* Enable the system clock */ | |
1196 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, | |
1197 | WM8350_SYSCLK_ENA); | |
1198 | ||
1199 | /* mute DAC & outputs */ | |
1200 | wm8350_set_bits(wm8350, WM8350_DAC_MUTE, | |
1201 | WM8350_DAC_MUTE_ENA); | |
1202 | ||
1203 | /* discharge cap memory */ | |
1204 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, | |
1205 | platform->dis_out1 | | |
1206 | (platform->dis_out2 << 2) | | |
1207 | (platform->dis_out3 << 4) | | |
1208 | (platform->dis_out4 << 6)); | |
1209 | ||
1210 | /* wait for discharge */ | |
1211 | schedule_timeout_interruptible(msecs_to_jiffies | |
1212 | (platform-> | |
1213 | cap_discharge_msecs)); | |
1214 | ||
1215 | /* enable antipop */ | |
1216 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, | |
1217 | (platform->vmid_s_curve << 8)); | |
1218 | ||
1219 | /* ramp up vmid */ | |
1220 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1221 | (platform-> | |
1222 | codec_current_charge << 14) | | |
1223 | WM8350_VMID_5K | WM8350_VMIDEN | | |
1224 | WM8350_VBUFEN); | |
1225 | ||
1226 | /* wait for vmid */ | |
1227 | schedule_timeout_interruptible(msecs_to_jiffies | |
1228 | (platform-> | |
1229 | vmid_charge_msecs)); | |
1230 | ||
1231 | /* turn on vmid 300k */ | |
1232 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1233 | ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); | |
1234 | pm1 |= WM8350_VMID_300K | | |
1235 | (platform->codec_current_standby << 14); | |
1236 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1237 | pm1); | |
1238 | ||
1239 | ||
1240 | /* enable analogue bias */ | |
1241 | pm1 |= WM8350_BIASEN; | |
1242 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); | |
1243 | ||
1244 | /* disable antipop */ | |
1245 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); | |
1246 | ||
1247 | } else { | |
1248 | /* turn on vmid 300k and reduce current */ | |
1249 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1250 | ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); | |
1251 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1252 | pm1 | WM8350_VMID_300K | | |
1253 | (platform-> | |
1254 | codec_current_standby << 14)); | |
1255 | ||
1256 | } | |
1257 | break; | |
1258 | ||
1259 | case SND_SOC_BIAS_OFF: | |
1260 | ||
1261 | /* mute DAC & enable outputs */ | |
1262 | wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); | |
1263 | ||
1264 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3, | |
1265 | WM8350_OUT1L_ENA | WM8350_OUT1R_ENA | | |
1266 | WM8350_OUT2L_ENA | WM8350_OUT2R_ENA); | |
1267 | ||
1268 | /* enable anti pop S curve */ | |
1269 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, | |
1270 | (platform->vmid_s_curve << 8)); | |
1271 | ||
1272 | /* turn off vmid */ | |
1273 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1274 | ~WM8350_VMIDEN; | |
1275 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); | |
1276 | ||
1277 | /* wait */ | |
1278 | schedule_timeout_interruptible(msecs_to_jiffies | |
1279 | (platform-> | |
1280 | vmid_discharge_msecs)); | |
1281 | ||
1282 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, | |
1283 | (platform->vmid_s_curve << 8) | | |
1284 | platform->dis_out1 | | |
1285 | (platform->dis_out2 << 2) | | |
1286 | (platform->dis_out3 << 4) | | |
1287 | (platform->dis_out4 << 6)); | |
1288 | ||
1289 | /* turn off VBuf and drain */ | |
1290 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1291 | ~(WM8350_VBUFEN | WM8350_VMID_MASK); | |
1292 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1293 | pm1 | WM8350_OUTPUT_DRAIN_EN); | |
1294 | ||
1295 | /* wait */ | |
1296 | schedule_timeout_interruptible(msecs_to_jiffies | |
1297 | (platform->drain_msecs)); | |
1298 | ||
1299 | pm1 &= ~WM8350_BIASEN; | |
1300 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); | |
1301 | ||
1302 | /* disable anti-pop */ | |
1303 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); | |
1304 | ||
1305 | wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME, | |
1306 | WM8350_OUT1L_ENA); | |
1307 | wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME, | |
1308 | WM8350_OUT1R_ENA); | |
1309 | wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME, | |
1310 | WM8350_OUT2L_ENA); | |
1311 | wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME, | |
1312 | WM8350_OUT2R_ENA); | |
1313 | ||
1314 | /* disable clock gen */ | |
1315 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, | |
1316 | WM8350_SYSCLK_ENA); | |
1317 | ||
1318 | regulator_bulk_disable(ARRAY_SIZE(priv->supplies), | |
1319 | priv->supplies); | |
1320 | break; | |
1321 | } | |
ce6120cc | 1322 | codec->dapm.bias_level = level; |
40aa4a30 MB |
1323 | return 0; |
1324 | } | |
1325 | ||
f0fba2ad | 1326 | static int wm8350_suspend(struct snd_soc_codec *codec, pm_message_t state) |
40aa4a30 | 1327 | { |
40aa4a30 MB |
1328 | wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); |
1329 | return 0; | |
1330 | } | |
1331 | ||
f0fba2ad | 1332 | static int wm8350_resume(struct snd_soc_codec *codec) |
40aa4a30 | 1333 | { |
40aa4a30 MB |
1334 | wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
1335 | ||
40aa4a30 MB |
1336 | return 0; |
1337 | } | |
1338 | ||
5a65edbc | 1339 | static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) |
a6ba2b2d MB |
1340 | { |
1341 | struct wm8350_data *priv = data; | |
5a65edbc | 1342 | struct wm8350 *wm8350 = priv->codec.control_data; |
a6ba2b2d MB |
1343 | u16 reg; |
1344 | int report; | |
1345 | int mask; | |
1346 | struct wm8350_jack_data *jack = NULL; | |
1347 | ||
59f25070 | 1348 | switch (irq - wm8350->irq_base) { |
a6ba2b2d MB |
1349 | case WM8350_IRQ_CODEC_JCK_DET_L: |
1350 | jack = &priv->hpl; | |
1351 | mask = WM8350_JACK_L_LVL; | |
1352 | break; | |
1353 | ||
1354 | case WM8350_IRQ_CODEC_JCK_DET_R: | |
1355 | jack = &priv->hpr; | |
1356 | mask = WM8350_JACK_R_LVL; | |
1357 | break; | |
1358 | ||
1359 | default: | |
1360 | BUG(); | |
1361 | } | |
1362 | ||
1363 | if (!jack->jack) { | |
1364 | dev_warn(wm8350->dev, "Jack interrupt called with no jack\n"); | |
5a65edbc | 1365 | return IRQ_NONE; |
a6ba2b2d MB |
1366 | } |
1367 | ||
1368 | /* Debounce */ | |
1369 | msleep(200); | |
1370 | ||
1371 | reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); | |
1372 | if (reg & mask) | |
1373 | report = jack->report; | |
1374 | else | |
1375 | report = 0; | |
1376 | ||
1377 | snd_soc_jack_report(jack->jack, report, jack->report); | |
5a65edbc MB |
1378 | |
1379 | return IRQ_HANDLED; | |
a6ba2b2d MB |
1380 | } |
1381 | ||
1382 | /** | |
1383 | * wm8350_hp_jack_detect - Enable headphone jack detection. | |
1384 | * | |
1385 | * @codec: WM8350 codec | |
1386 | * @which: left or right jack detect signal | |
1387 | * @jack: jack to report detection events on | |
1388 | * @report: value to report | |
1389 | * | |
f06bce9c MB |
1390 | * Enables the headphone jack detection of the WM8350. If no report |
1391 | * is specified then detection is disabled. | |
a6ba2b2d MB |
1392 | */ |
1393 | int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which, | |
1394 | struct snd_soc_jack *jack, int report) | |
1395 | { | |
b2c812e2 | 1396 | struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); |
a6ba2b2d MB |
1397 | struct wm8350 *wm8350 = codec->control_data; |
1398 | int irq; | |
1399 | int ena; | |
1400 | ||
1401 | switch (which) { | |
1402 | case WM8350_JDL: | |
1403 | priv->hpl.jack = jack; | |
1404 | priv->hpl.report = report; | |
1405 | irq = WM8350_IRQ_CODEC_JCK_DET_L; | |
1406 | ena = WM8350_JDL_ENA; | |
1407 | break; | |
1408 | ||
1409 | case WM8350_JDR: | |
1410 | priv->hpr.jack = jack; | |
1411 | priv->hpr.report = report; | |
1412 | irq = WM8350_IRQ_CODEC_JCK_DET_R; | |
1413 | ena = WM8350_JDR_ENA; | |
1414 | break; | |
1415 | ||
1416 | default: | |
1417 | return -EINVAL; | |
1418 | } | |
1419 | ||
f06bce9c MB |
1420 | if (report) { |
1421 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); | |
1422 | wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena); | |
1423 | } else { | |
1424 | wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena); | |
1425 | } | |
a6ba2b2d MB |
1426 | |
1427 | /* Sync status */ | |
59f25070 | 1428 | wm8350_hp_jack_handler(irq + wm8350->irq_base, priv); |
a6ba2b2d | 1429 | |
a6ba2b2d MB |
1430 | return 0; |
1431 | } | |
1432 | EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect); | |
1433 | ||
2a0761a3 MB |
1434 | static irqreturn_t wm8350_mic_handler(int irq, void *data) |
1435 | { | |
1436 | struct wm8350_data *priv = data; | |
1437 | struct wm8350 *wm8350 = priv->codec.control_data; | |
1438 | u16 reg; | |
1439 | int report = 0; | |
1440 | ||
1441 | reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); | |
1442 | if (reg & WM8350_JACK_MICSCD_LVL) | |
1443 | report |= priv->mic.short_report; | |
1444 | if (reg & WM8350_JACK_MICSD_LVL) | |
1445 | report |= priv->mic.report; | |
1446 | ||
1447 | snd_soc_jack_report(priv->mic.jack, report, | |
1448 | priv->mic.report | priv->mic.short_report); | |
1449 | ||
1450 | return IRQ_HANDLED; | |
1451 | } | |
1452 | ||
1453 | /** | |
1454 | * wm8350_mic_jack_detect - Enable microphone jack detection. | |
1455 | * | |
1456 | * @codec: WM8350 codec | |
1457 | * @jack: jack to report detection events on | |
1458 | * @detect_report: value to report when presence detected | |
1459 | * @short_report: value to report when microphone short detected | |
1460 | * | |
f06bce9c MB |
1461 | * Enables the microphone jack detection of the WM8350. If both reports |
1462 | * are specified as zero then detection is disabled. | |
2a0761a3 MB |
1463 | */ |
1464 | int wm8350_mic_jack_detect(struct snd_soc_codec *codec, | |
1465 | struct snd_soc_jack *jack, | |
1466 | int detect_report, int short_report) | |
1467 | { | |
b2c812e2 | 1468 | struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); |
2a0761a3 MB |
1469 | struct wm8350 *wm8350 = codec->control_data; |
1470 | ||
1471 | priv->mic.jack = jack; | |
1472 | priv->mic.report = detect_report; | |
1473 | priv->mic.short_report = short_report; | |
1474 | ||
f06bce9c MB |
1475 | if (detect_report || short_report) { |
1476 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); | |
1477 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1, | |
1478 | WM8350_MIC_DET_ENA); | |
1479 | } else { | |
1480 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1, | |
1481 | WM8350_MIC_DET_ENA); | |
1482 | } | |
2a0761a3 | 1483 | |
2a0761a3 MB |
1484 | return 0; |
1485 | } | |
1486 | EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect); | |
1487 | ||
f0fba2ad LG |
1488 | #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000) |
1489 | ||
1490 | #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
1491 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1492 | SNDRV_PCM_FMTBIT_S24_LE) | |
1493 | ||
1494 | static struct snd_soc_dai_ops wm8350_dai_ops = { | |
1495 | .hw_params = wm8350_pcm_hw_params, | |
1496 | .digital_mute = wm8350_mute, | |
1497 | .trigger = wm8350_pcm_trigger, | |
1498 | .set_fmt = wm8350_set_dai_fmt, | |
1499 | .set_sysclk = wm8350_set_dai_sysclk, | |
1500 | .set_pll = wm8350_set_fll, | |
1501 | .set_clkdiv = wm8350_set_clkdiv, | |
1502 | }; | |
1503 | ||
1504 | static struct snd_soc_dai_driver wm8350_dai = { | |
1505 | .name = "wm8350-hifi", | |
1506 | .playback = { | |
1507 | .stream_name = "Playback", | |
1508 | .channels_min = 1, | |
1509 | .channels_max = 2, | |
1510 | .rates = WM8350_RATES, | |
1511 | .formats = WM8350_FORMATS, | |
1512 | }, | |
1513 | .capture = { | |
1514 | .stream_name = "Capture", | |
1515 | .channels_min = 1, | |
1516 | .channels_max = 2, | |
1517 | .rates = WM8350_RATES, | |
1518 | .formats = WM8350_FORMATS, | |
1519 | }, | |
1520 | .ops = &wm8350_dai_ops, | |
1521 | }; | |
40aa4a30 | 1522 | |
f0fba2ad | 1523 | static int wm8350_codec_probe(struct snd_soc_codec *codec) |
40aa4a30 | 1524 | { |
f0fba2ad | 1525 | struct wm8350 *wm8350 = dev_get_platdata(codec->dev); |
40aa4a30 | 1526 | struct wm8350_data *priv; |
40aa4a30 MB |
1527 | struct wm8350_output *out1; |
1528 | struct wm8350_output *out2; | |
f0fba2ad | 1529 | int ret, i; |
40aa4a30 | 1530 | |
f0fba2ad LG |
1531 | if (wm8350->codec.platform_data == NULL) { |
1532 | dev_err(codec->dev, "No audio platform data supplied\n"); | |
1533 | return -EINVAL; | |
1534 | } | |
1535 | ||
1536 | priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL); | |
1537 | if (priv == NULL) | |
1538 | return -ENOMEM; | |
1539 | snd_soc_codec_set_drvdata(codec, priv); | |
1540 | ||
1541 | for (i = 0; i < ARRAY_SIZE(supply_names); i++) | |
1542 | priv->supplies[i].supply = supply_names[i]; | |
1543 | ||
1544 | ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies), | |
1545 | priv->supplies); | |
1546 | if (ret != 0) | |
1547 | goto err_priv; | |
1548 | ||
1549 | wm8350->codec.codec = codec; | |
1550 | codec->control_data = wm8350; | |
40aa4a30 | 1551 | |
f0fba2ad LG |
1552 | /* Put the codec into reset if it wasn't already */ |
1553 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); | |
1554 | ||
ce6120cc | 1555 | INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work); |
40aa4a30 MB |
1556 | |
1557 | /* Enable the codec */ | |
1558 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); | |
1559 | ||
1560 | /* Enable robust clocking mode in ADC */ | |
1561 | wm8350_codec_write(codec, WM8350_SECURITY, 0xa7); | |
1562 | wm8350_codec_write(codec, 0xde, 0x13); | |
1563 | wm8350_codec_write(codec, WM8350_SECURITY, 0); | |
1564 | ||
1565 | /* read OUT1 & OUT2 volumes */ | |
1566 | out1 = &priv->out1; | |
1567 | out2 = &priv->out2; | |
1568 | out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) & | |
1569 | WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; | |
1570 | out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) & | |
1571 | WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; | |
1572 | out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) & | |
1573 | WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; | |
1574 | out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) & | |
1575 | WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; | |
1576 | wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0); | |
1577 | wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0); | |
1578 | wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0); | |
1579 | wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0); | |
1580 | ||
1581 | /* Latch VU bits & mute */ | |
1582 | wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, | |
1583 | WM8350_OUT1_VU | WM8350_OUT1L_MUTE); | |
1584 | wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, | |
1585 | WM8350_OUT2_VU | WM8350_OUT2L_MUTE); | |
1586 | wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME, | |
1587 | WM8350_OUT1_VU | WM8350_OUT1R_MUTE); | |
1588 | wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME, | |
1589 | WM8350_OUT2_VU | WM8350_OUT2R_MUTE); | |
1590 | ||
6a612746 MB |
1591 | /* Make sure jack detect is disabled to start off with */ |
1592 | wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, | |
1593 | WM8350_JDL_ENA | WM8350_JDR_ENA); | |
1594 | ||
a6ba2b2d | 1595 | wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, |
5a65edbc MB |
1596 | wm8350_hp_jack_handler, 0, "Left jack detect", |
1597 | priv); | |
a6ba2b2d | 1598 | wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, |
5a65edbc MB |
1599 | wm8350_hp_jack_handler, 0, "Right jack detect", |
1600 | priv); | |
2a0761a3 MB |
1601 | wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, |
1602 | wm8350_mic_handler, 0, "Microphone short", priv); | |
1603 | wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD, | |
1604 | wm8350_mic_handler, 0, "Microphone detect", priv); | |
a6ba2b2d | 1605 | |
40aa4a30 | 1606 | |
3e8e1952 IM |
1607 | snd_soc_add_controls(codec, wm8350_snd_controls, |
1608 | ARRAY_SIZE(wm8350_snd_controls)); | |
40aa4a30 MB |
1609 | wm8350_add_widgets(codec); |
1610 | ||
1611 | wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1612 | ||
40aa4a30 | 1613 | return 0; |
f0fba2ad LG |
1614 | |
1615 | err_priv: | |
1616 | kfree(priv); | |
1617 | return ret; | |
40aa4a30 MB |
1618 | } |
1619 | ||
f0fba2ad | 1620 | static int wm8350_codec_remove(struct snd_soc_codec *codec) |
40aa4a30 | 1621 | { |
b2c812e2 | 1622 | struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); |
f0fba2ad | 1623 | struct wm8350 *wm8350 = dev_get_platdata(codec->dev); |
40aa4a30 MB |
1624 | int ret; |
1625 | ||
a6ba2b2d MB |
1626 | wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, |
1627 | WM8350_JDL_ENA | WM8350_JDR_ENA); | |
1628 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); | |
1629 | ||
2a0761a3 MB |
1630 | wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv); |
1631 | wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv); | |
f99344fc MB |
1632 | wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv); |
1633 | wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv); | |
a6ba2b2d MB |
1634 | |
1635 | priv->hpl.jack = NULL; | |
1636 | priv->hpr.jack = NULL; | |
2a0761a3 | 1637 | priv->mic.jack = NULL; |
a6ba2b2d | 1638 | |
40aa4a30 | 1639 | /* cancel any work waiting to be queued. */ |
ce6120cc | 1640 | ret = cancel_delayed_work(&codec->dapm.delayed_work); |
40aa4a30 MB |
1641 | |
1642 | /* if there was any work waiting then we run it now and | |
1643 | * wait for its completion */ | |
1644 | if (ret) { | |
ce6120cc | 1645 | schedule_delayed_work(&codec->dapm.delayed_work, 0); |
40aa4a30 MB |
1646 | flush_scheduled_work(); |
1647 | } | |
1648 | ||
1649 | wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1650 | ||
1651 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); | |
1652 | ||
f0fba2ad LG |
1653 | regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies); |
1654 | kfree(priv); | |
40aa4a30 MB |
1655 | return 0; |
1656 | } | |
1657 | ||
f0fba2ad LG |
1658 | static struct snd_soc_codec_driver soc_codec_dev_wm8350 = { |
1659 | .probe = wm8350_codec_probe, | |
1660 | .remove = wm8350_codec_remove, | |
40aa4a30 MB |
1661 | .suspend = wm8350_suspend, |
1662 | .resume = wm8350_resume, | |
f0fba2ad LG |
1663 | .read = wm8350_codec_read, |
1664 | .write = wm8350_codec_write, | |
1665 | .set_bias_level = wm8350_set_bias_level, | |
40aa4a30 | 1666 | }; |
40aa4a30 | 1667 | |
f0fba2ad | 1668 | static int __devinit wm8350_probe(struct platform_device *pdev) |
40aa4a30 | 1669 | { |
f0fba2ad LG |
1670 | return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350, |
1671 | &wm8350_dai, 1); | |
40aa4a30 MB |
1672 | } |
1673 | ||
f0fba2ad | 1674 | static int __devexit wm8350_remove(struct platform_device *pdev) |
40aa4a30 | 1675 | { |
f0fba2ad | 1676 | snd_soc_unregister_codec(&pdev->dev); |
40aa4a30 MB |
1677 | return 0; |
1678 | } | |
1679 | ||
1680 | static struct platform_driver wm8350_codec_driver = { | |
1681 | .driver = { | |
1682 | .name = "wm8350-codec", | |
1683 | .owner = THIS_MODULE, | |
1684 | }, | |
f0fba2ad LG |
1685 | .probe = wm8350_probe, |
1686 | .remove = __devexit_p(wm8350_remove), | |
40aa4a30 MB |
1687 | }; |
1688 | ||
1689 | static __init int wm8350_init(void) | |
1690 | { | |
1691 | return platform_driver_register(&wm8350_codec_driver); | |
1692 | } | |
1693 | module_init(wm8350_init); | |
1694 | ||
1695 | static __exit void wm8350_exit(void) | |
1696 | { | |
1697 | platform_driver_unregister(&wm8350_codec_driver); | |
1698 | } | |
1699 | module_exit(wm8350_exit); | |
1700 | ||
1701 | MODULE_DESCRIPTION("ASoC WM8350 driver"); | |
1702 | MODULE_AUTHOR("Liam Girdwood"); | |
1703 | MODULE_LICENSE("GPL"); | |
1704 | MODULE_ALIAS("platform:wm8350-codec"); |