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e88ba015 MB |
1 | /* |
2 | * wm8580.c -- WM8580 ALSA Soc Audio driver | |
3 | * | |
6f7cb44b | 4 | * Copyright 2008, 2009 Wolfson Microelectronics PLC. |
e88ba015 MB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * Notes: | |
12 | * The WM8580 is a multichannel codec with S/PDIF support, featuring six | |
13 | * DAC channels and two ADC channels. | |
14 | * | |
15 | * Currently only the primary audio interface is supported - S/PDIF and | |
16 | * the secondary audio interfaces are not. | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
e88ba015 MB |
21 | #include <linux/kernel.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/pm.h> | |
25 | #include <linux/i2c.h> | |
26 | #include <linux/platform_device.h> | |
a583cd53 | 27 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
733eef3e | 29 | #include <linux/of_device.h> |
a583cd53 | 30 | |
e88ba015 MB |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/soc.h> | |
e88ba015 MB |
35 | #include <sound/tlv.h> |
36 | #include <sound/initval.h> | |
37 | #include <asm/div64.h> | |
38 | ||
39 | #include "wm8580.h" | |
40 | ||
e88ba015 MB |
41 | /* WM8580 register space */ |
42 | #define WM8580_PLLA1 0x00 | |
43 | #define WM8580_PLLA2 0x01 | |
44 | #define WM8580_PLLA3 0x02 | |
45 | #define WM8580_PLLA4 0x03 | |
46 | #define WM8580_PLLB1 0x04 | |
47 | #define WM8580_PLLB2 0x05 | |
48 | #define WM8580_PLLB3 0x06 | |
49 | #define WM8580_PLLB4 0x07 | |
50 | #define WM8580_CLKSEL 0x08 | |
51 | #define WM8580_PAIF1 0x09 | |
52 | #define WM8580_PAIF2 0x0A | |
53 | #define WM8580_SAIF1 0x0B | |
54 | #define WM8580_PAIF3 0x0C | |
55 | #define WM8580_PAIF4 0x0D | |
56 | #define WM8580_SAIF2 0x0E | |
57 | #define WM8580_DAC_CONTROL1 0x0F | |
58 | #define WM8580_DAC_CONTROL2 0x10 | |
59 | #define WM8580_DAC_CONTROL3 0x11 | |
60 | #define WM8580_DAC_CONTROL4 0x12 | |
61 | #define WM8580_DAC_CONTROL5 0x13 | |
62 | #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14 | |
63 | #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15 | |
64 | #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16 | |
65 | #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17 | |
66 | #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18 | |
67 | #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19 | |
68 | #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C | |
69 | #define WM8580_ADC_CONTROL1 0x1D | |
70 | #define WM8580_SPDTXCHAN0 0x1E | |
71 | #define WM8580_SPDTXCHAN1 0x1F | |
72 | #define WM8580_SPDTXCHAN2 0x20 | |
73 | #define WM8580_SPDTXCHAN3 0x21 | |
74 | #define WM8580_SPDTXCHAN4 0x22 | |
75 | #define WM8580_SPDTXCHAN5 0x23 | |
76 | #define WM8580_SPDMODE 0x24 | |
77 | #define WM8580_INTMASK 0x25 | |
78 | #define WM8580_GPO1 0x26 | |
79 | #define WM8580_GPO2 0x27 | |
80 | #define WM8580_GPO3 0x28 | |
81 | #define WM8580_GPO4 0x29 | |
82 | #define WM8580_GPO5 0x2A | |
83 | #define WM8580_INTSTAT 0x2B | |
84 | #define WM8580_SPDRXCHAN1 0x2C | |
85 | #define WM8580_SPDRXCHAN2 0x2D | |
86 | #define WM8580_SPDRXCHAN3 0x2E | |
87 | #define WM8580_SPDRXCHAN4 0x2F | |
88 | #define WM8580_SPDRXCHAN5 0x30 | |
89 | #define WM8580_SPDSTAT 0x31 | |
90 | #define WM8580_PWRDN1 0x32 | |
91 | #define WM8580_PWRDN2 0x33 | |
92 | #define WM8580_READBACK 0x34 | |
93 | #define WM8580_RESET 0x35 | |
94 | ||
6f7cb44b MB |
95 | #define WM8580_MAX_REGISTER 0x35 |
96 | ||
6bfb6aa9 MB |
97 | #define WM8580_DACOSR 0x40 |
98 | ||
e88ba015 MB |
99 | /* PLLB4 (register 7h) */ |
100 | #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60 | |
101 | #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20 | |
102 | #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40 | |
103 | #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60 | |
104 | ||
105 | #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180 | |
106 | #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080 | |
107 | #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100 | |
108 | #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180 | |
109 | ||
110 | /* CLKSEL (register 8h) */ | |
111 | #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03 | |
112 | #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01 | |
113 | #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02 | |
114 | ||
115 | /* AIF control 1 (registers 9h-bh) */ | |
116 | #define WM8580_AIF_RATE_MASK 0x7 | |
e88ba015 | 117 | #define WM8580_AIF_BCLKSEL_MASK 0x18 |
e88ba015 MB |
118 | |
119 | #define WM8580_AIF_MS 0x20 | |
120 | ||
121 | #define WM8580_AIF_CLKSRC_MASK 0xc0 | |
122 | #define WM8580_AIF_CLKSRC_PLLA 0x40 | |
123 | #define WM8580_AIF_CLKSRC_PLLB 0x40 | |
124 | #define WM8580_AIF_CLKSRC_MCLK 0xc0 | |
125 | ||
126 | /* AIF control 2 (registers ch-eh) */ | |
127 | #define WM8580_AIF_FMT_MASK 0x03 | |
128 | #define WM8580_AIF_FMT_RIGHTJ 0x00 | |
129 | #define WM8580_AIF_FMT_LEFTJ 0x01 | |
130 | #define WM8580_AIF_FMT_I2S 0x02 | |
131 | #define WM8580_AIF_FMT_DSP 0x03 | |
132 | ||
133 | #define WM8580_AIF_LENGTH_MASK 0x0c | |
134 | #define WM8580_AIF_LENGTH_16 0x00 | |
135 | #define WM8580_AIF_LENGTH_20 0x04 | |
136 | #define WM8580_AIF_LENGTH_24 0x08 | |
137 | #define WM8580_AIF_LENGTH_32 0x0c | |
138 | ||
139 | #define WM8580_AIF_LRP 0x10 | |
140 | #define WM8580_AIF_BCP 0x20 | |
141 | ||
142 | /* Powerdown Register 1 (register 32h) */ | |
143 | #define WM8580_PWRDN1_PWDN 0x001 | |
144 | #define WM8580_PWRDN1_ALLDACPD 0x040 | |
145 | ||
146 | /* Powerdown Register 2 (register 33h) */ | |
147 | #define WM8580_PWRDN2_OSSCPD 0x001 | |
148 | #define WM8580_PWRDN2_PLLAPD 0x002 | |
149 | #define WM8580_PWRDN2_PLLBPD 0x004 | |
150 | #define WM8580_PWRDN2_SPDIFPD 0x008 | |
151 | #define WM8580_PWRDN2_SPDIFTXD 0x010 | |
152 | #define WM8580_PWRDN2_SPDIFRXD 0x020 | |
153 | ||
154 | #define WM8580_DAC_CONTROL5_MUTEALL 0x10 | |
155 | ||
156 | /* | |
157 | * wm8580 register cache | |
158 | * We can't read the WM8580 register space when we | |
159 | * are using 2 wire for device control, so we cache them instead. | |
160 | */ | |
161 | static const u16 wm8580_reg[] = { | |
162 | 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/ | |
163 | 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/ | |
a0968628 | 164 | 0x0010, 0x0002, 0x0002, 0x00c2, /*R11*/ |
e88ba015 MB |
165 | 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/ |
166 | 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/ | |
167 | 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/ | |
168 | 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/ | |
169 | 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/ | |
170 | 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/ | |
171 | 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/ | |
172 | 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/ | |
173 | 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/ | |
174 | 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/ | |
175 | 0x0000, 0x0000 /*R53*/ | |
176 | }; | |
177 | ||
6f7cb44b MB |
178 | struct pll_state { |
179 | unsigned int in; | |
180 | unsigned int out; | |
181 | }; | |
182 | ||
a583cd53 MB |
183 | #define WM8580_NUM_SUPPLIES 3 |
184 | static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = { | |
185 | "AVDD", | |
186 | "DVDD", | |
187 | "PVDD", | |
188 | }; | |
189 | ||
6f7cb44b MB |
190 | /* codec private data */ |
191 | struct wm8580_priv { | |
f0fba2ad | 192 | enum snd_soc_control_type control_type; |
a583cd53 | 193 | struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES]; |
6f7cb44b MB |
194 | struct pll_state a; |
195 | struct pll_state b; | |
c5607d8e | 196 | int sysclk[2]; |
6f7cb44b MB |
197 | }; |
198 | ||
e88ba015 MB |
199 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); |
200 | ||
201 | static int wm8580_out_vu(struct snd_kcontrol *kcontrol, | |
202 | struct snd_ctl_elem_value *ucontrol) | |
203 | { | |
ccb077fd MB |
204 | struct soc_mixer_control *mc = |
205 | (struct soc_mixer_control *)kcontrol->private_value; | |
e88ba015 | 206 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
f6f1eb10 | 207 | u16 *reg_cache = codec->reg_cache; |
ccb077fd MB |
208 | unsigned int reg = mc->reg; |
209 | unsigned int reg2 = mc->rreg; | |
e88ba015 | 210 | int ret; |
e88ba015 MB |
211 | |
212 | /* Clear the register cache so we write without VU set */ | |
f6f1eb10 MB |
213 | reg_cache[reg] = 0; |
214 | reg_cache[reg2] = 0; | |
e88ba015 MB |
215 | |
216 | ret = snd_soc_put_volsw_2r(kcontrol, ucontrol); | |
217 | if (ret < 0) | |
218 | return ret; | |
219 | ||
220 | /* Now write again with the volume update bit set */ | |
f6f1eb10 MB |
221 | snd_soc_update_bits(codec, reg, 0x100, 0x100); |
222 | snd_soc_update_bits(codec, reg2, 0x100, 0x100); | |
e88ba015 MB |
223 | |
224 | return 0; | |
225 | } | |
226 | ||
e88ba015 | 227 | static const struct snd_kcontrol_new wm8580_snd_controls[] = { |
0f9887d1 PU |
228 | SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume", |
229 | WM8580_DIGITAL_ATTENUATION_DACL1, | |
230 | WM8580_DIGITAL_ATTENUATION_DACR1, | |
231 | 0, 0xff, 0, snd_soc_get_volsw_2r, wm8580_out_vu, dac_tlv), | |
232 | SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume", | |
233 | WM8580_DIGITAL_ATTENUATION_DACL2, | |
234 | WM8580_DIGITAL_ATTENUATION_DACR2, | |
235 | 0, 0xff, 0, snd_soc_get_volsw_2r, wm8580_out_vu, dac_tlv), | |
236 | SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume", | |
237 | WM8580_DIGITAL_ATTENUATION_DACL3, | |
238 | WM8580_DIGITAL_ATTENUATION_DACR3, | |
239 | 0, 0xff, 0, snd_soc_get_volsw_2r, wm8580_out_vu, dac_tlv), | |
e88ba015 MB |
240 | |
241 | SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0), | |
242 | SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0), | |
243 | SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0), | |
244 | ||
245 | SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0), | |
246 | SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0), | |
247 | SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0), | |
248 | ||
249 | SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0), | |
4f0ed9a5 MB |
250 | SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1), |
251 | SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1), | |
252 | SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1), | |
e88ba015 | 253 | |
dacfe9f2 | 254 | SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1), |
6f341d14 | 255 | SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0), |
e88ba015 MB |
256 | }; |
257 | ||
e88ba015 MB |
258 | static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = { |
259 | SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1), | |
260 | SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1), | |
261 | SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1), | |
262 | ||
263 | SND_SOC_DAPM_OUTPUT("VOUT1L"), | |
264 | SND_SOC_DAPM_OUTPUT("VOUT1R"), | |
265 | SND_SOC_DAPM_OUTPUT("VOUT2L"), | |
266 | SND_SOC_DAPM_OUTPUT("VOUT2R"), | |
267 | SND_SOC_DAPM_OUTPUT("VOUT3L"), | |
268 | SND_SOC_DAPM_OUTPUT("VOUT3R"), | |
269 | ||
270 | SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1), | |
271 | ||
272 | SND_SOC_DAPM_INPUT("AINL"), | |
273 | SND_SOC_DAPM_INPUT("AINR"), | |
274 | }; | |
275 | ||
276 | static const struct snd_soc_dapm_route audio_map[] = { | |
277 | { "VOUT1L", NULL, "DAC1" }, | |
278 | { "VOUT1R", NULL, "DAC1" }, | |
279 | ||
280 | { "VOUT2L", NULL, "DAC2" }, | |
281 | { "VOUT2R", NULL, "DAC2" }, | |
282 | ||
283 | { "VOUT3L", NULL, "DAC3" }, | |
284 | { "VOUT3R", NULL, "DAC3" }, | |
285 | ||
286 | { "ADC", NULL, "AINL" }, | |
287 | { "ADC", NULL, "AINR" }, | |
288 | }; | |
289 | ||
290 | static int wm8580_add_widgets(struct snd_soc_codec *codec) | |
291 | { | |
ce6120cc | 292 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
e88ba015 | 293 | |
ce6120cc LG |
294 | snd_soc_dapm_new_controls(dapm, wm8580_dapm_widgets, |
295 | ARRAY_SIZE(wm8580_dapm_widgets)); | |
296 | snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); | |
e88ba015 | 297 | |
e88ba015 MB |
298 | return 0; |
299 | } | |
300 | ||
301 | /* PLL divisors */ | |
302 | struct _pll_div { | |
303 | u32 prescale:1; | |
304 | u32 postscale:1; | |
305 | u32 freqmode:2; | |
306 | u32 n:4; | |
307 | u32 k:24; | |
308 | }; | |
309 | ||
310 | /* The size in bits of the pll divide */ | |
311 | #define FIXED_PLL_SIZE (1 << 22) | |
312 | ||
313 | /* PLL rate to output rate divisions */ | |
314 | static struct { | |
315 | unsigned int div; | |
316 | unsigned int freqmode; | |
317 | unsigned int postscale; | |
318 | } post_table[] = { | |
319 | { 2, 0, 0 }, | |
320 | { 4, 0, 1 }, | |
321 | { 4, 1, 0 }, | |
322 | { 8, 1, 1 }, | |
323 | { 8, 2, 0 }, | |
324 | { 16, 2, 1 }, | |
325 | { 12, 3, 0 }, | |
326 | { 24, 3, 1 } | |
327 | }; | |
328 | ||
329 | static int pll_factors(struct _pll_div *pll_div, unsigned int target, | |
330 | unsigned int source) | |
331 | { | |
332 | u64 Kpart; | |
333 | unsigned int K, Ndiv, Nmod; | |
334 | int i; | |
335 | ||
449bd54d | 336 | pr_debug("wm8580: PLL %uHz->%uHz\n", source, target); |
e88ba015 MB |
337 | |
338 | /* Scale the output frequency up; the PLL should run in the | |
339 | * region of 90-100MHz. | |
340 | */ | |
341 | for (i = 0; i < ARRAY_SIZE(post_table); i++) { | |
342 | if (target * post_table[i].div >= 90000000 && | |
343 | target * post_table[i].div <= 100000000) { | |
344 | pll_div->freqmode = post_table[i].freqmode; | |
345 | pll_div->postscale = post_table[i].postscale; | |
346 | target *= post_table[i].div; | |
347 | break; | |
348 | } | |
349 | } | |
350 | ||
351 | if (i == ARRAY_SIZE(post_table)) { | |
352 | printk(KERN_ERR "wm8580: Unable to scale output frequency " | |
353 | "%u\n", target); | |
354 | return -EINVAL; | |
355 | } | |
356 | ||
357 | Ndiv = target / source; | |
358 | ||
359 | if (Ndiv < 5) { | |
360 | source /= 2; | |
361 | pll_div->prescale = 1; | |
362 | Ndiv = target / source; | |
363 | } else | |
364 | pll_div->prescale = 0; | |
365 | ||
366 | if ((Ndiv < 5) || (Ndiv > 13)) { | |
367 | printk(KERN_ERR | |
449bd54d | 368 | "WM8580 N=%u outside supported range\n", Ndiv); |
e88ba015 MB |
369 | return -EINVAL; |
370 | } | |
371 | ||
372 | pll_div->n = Ndiv; | |
373 | Nmod = target % source; | |
374 | Kpart = FIXED_PLL_SIZE * (long long)Nmod; | |
375 | ||
376 | do_div(Kpart, source); | |
377 | ||
378 | K = Kpart & 0xFFFFFFFF; | |
379 | ||
380 | pll_div->k = K; | |
381 | ||
382 | pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n", | |
383 | pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode, | |
384 | pll_div->postscale); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
85488037 MB |
389 | static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
390 | int source, unsigned int freq_in, unsigned int freq_out) | |
e88ba015 MB |
391 | { |
392 | int offset; | |
393 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 394 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
e88ba015 MB |
395 | struct pll_state *state; |
396 | struct _pll_div pll_div; | |
397 | unsigned int reg; | |
398 | unsigned int pwr_mask; | |
399 | int ret; | |
400 | ||
401 | /* GCC isn't able to work out the ifs below for initialising/using | |
402 | * pll_div so suppress warnings. | |
403 | */ | |
404 | memset(&pll_div, 0, sizeof(pll_div)); | |
405 | ||
406 | switch (pll_id) { | |
407 | case WM8580_PLLA: | |
408 | state = &wm8580->a; | |
409 | offset = 0; | |
410 | pwr_mask = WM8580_PWRDN2_PLLAPD; | |
411 | break; | |
412 | case WM8580_PLLB: | |
413 | state = &wm8580->b; | |
414 | offset = 4; | |
415 | pwr_mask = WM8580_PWRDN2_PLLBPD; | |
416 | break; | |
417 | default: | |
418 | return -ENODEV; | |
419 | } | |
420 | ||
421 | if (freq_in && freq_out) { | |
422 | ret = pll_factors(&pll_div, freq_out, freq_in); | |
423 | if (ret != 0) | |
424 | return ret; | |
425 | } | |
426 | ||
427 | state->in = freq_in; | |
428 | state->out = freq_out; | |
429 | ||
430 | /* Always disable the PLL - it is not safe to leave it running | |
431 | * while reprogramming it. | |
432 | */ | |
f6f1eb10 MB |
433 | reg = snd_soc_read(codec, WM8580_PWRDN2); |
434 | snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask); | |
e88ba015 MB |
435 | |
436 | if (!freq_in || !freq_out) | |
437 | return 0; | |
438 | ||
f6f1eb10 | 439 | snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff); |
5c0d38c9 | 440 | snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff); |
f6f1eb10 | 441 | snd_soc_write(codec, WM8580_PLLA3 + offset, |
e88ba015 MB |
442 | (pll_div.k >> 18 & 0xf) | (pll_div.n << 4)); |
443 | ||
f6f1eb10 | 444 | reg = snd_soc_read(codec, WM8580_PLLA4 + offset); |
5c0d38c9 | 445 | reg &= ~0x1b; |
e88ba015 | 446 | reg |= pll_div.prescale | pll_div.postscale << 1 | |
ce88168f | 447 | pll_div.freqmode << 3; |
e88ba015 | 448 | |
f6f1eb10 | 449 | snd_soc_write(codec, WM8580_PLLA4 + offset, reg); |
e88ba015 MB |
450 | |
451 | /* All done, turn it on */ | |
f6f1eb10 MB |
452 | reg = snd_soc_read(codec, WM8580_PWRDN2); |
453 | snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask); | |
e88ba015 MB |
454 | |
455 | return 0; | |
456 | } | |
457 | ||
c5607d8e MB |
458 | static const int wm8580_sysclk_ratios[] = { |
459 | 128, 192, 256, 384, 512, 768, 1152, | |
460 | }; | |
461 | ||
e88ba015 MB |
462 | /* |
463 | * Set PCM DAI bit size and sample rate. | |
464 | */ | |
465 | static int wm8580_paif_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
466 | struct snd_pcm_hw_params *params, |
467 | struct snd_soc_dai *dai) | |
e88ba015 MB |
468 | { |
469 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 470 | struct snd_soc_codec *codec = rtd->codec; |
c5607d8e MB |
471 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
472 | u16 paifa = 0; | |
e231cab0 | 473 | u16 paifb = 0; |
6bfb6aa9 | 474 | int i, ratio, osr; |
e88ba015 | 475 | |
e88ba015 MB |
476 | /* bit size */ |
477 | switch (params_format(params)) { | |
478 | case SNDRV_PCM_FORMAT_S16_LE: | |
ba2772ed | 479 | paifa |= 0x8; |
e88ba015 MB |
480 | break; |
481 | case SNDRV_PCM_FORMAT_S20_3LE: | |
6b464321 | 482 | paifa |= 0x0; |
e88ba015 MB |
483 | paifb |= WM8580_AIF_LENGTH_20; |
484 | break; | |
485 | case SNDRV_PCM_FORMAT_S24_LE: | |
6b464321 | 486 | paifa |= 0x0; |
e88ba015 MB |
487 | paifb |= WM8580_AIF_LENGTH_24; |
488 | break; | |
489 | case SNDRV_PCM_FORMAT_S32_LE: | |
6b464321 JB |
490 | paifa |= 0x0; |
491 | paifb |= WM8580_AIF_LENGTH_32; | |
e88ba015 MB |
492 | break; |
493 | default: | |
494 | return -EINVAL; | |
495 | } | |
496 | ||
c5607d8e | 497 | /* Look up the SYSCLK ratio; accept only exact matches */ |
06286938 | 498 | ratio = wm8580->sysclk[dai->driver->id] / params_rate(params); |
c5607d8e MB |
499 | for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++) |
500 | if (ratio == wm8580_sysclk_ratios[i]) | |
501 | break; | |
502 | if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) { | |
503 | dev_err(codec->dev, "Invalid clock ratio %d/%d\n", | |
06286938 | 504 | wm8580->sysclk[dai->driver->id], params_rate(params)); |
c5607d8e MB |
505 | return -EINVAL; |
506 | } | |
507 | paifa |= i; | |
508 | dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n", | |
509 | wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]); | |
510 | ||
6bfb6aa9 MB |
511 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
512 | switch (ratio) { | |
513 | case 128: | |
514 | case 192: | |
515 | osr = WM8580_DACOSR; | |
516 | dev_dbg(codec->dev, "Selecting 64x OSR\n"); | |
517 | break; | |
518 | default: | |
519 | osr = 0; | |
520 | dev_dbg(codec->dev, "Selecting 128x OSR\n"); | |
521 | break; | |
522 | } | |
523 | ||
524 | snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr); | |
525 | } | |
526 | ||
c5607d8e | 527 | snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id, |
ba2772ed MB |
528 | WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK, |
529 | paifa); | |
e231cab0 MB |
530 | snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id, |
531 | WM8580_AIF_LENGTH_MASK, paifb); | |
e88ba015 MB |
532 | return 0; |
533 | } | |
534 | ||
535 | static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai, | |
536 | unsigned int fmt) | |
537 | { | |
538 | struct snd_soc_codec *codec = codec_dai->codec; | |
539 | unsigned int aifa; | |
540 | unsigned int aifb; | |
541 | int can_invert_lrclk; | |
542 | ||
f0fba2ad LG |
543 | aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id); |
544 | aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id); | |
e88ba015 MB |
545 | |
546 | aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP); | |
547 | ||
548 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
549 | case SND_SOC_DAIFMT_CBS_CFS: | |
550 | aifa &= ~WM8580_AIF_MS; | |
551 | break; | |
552 | case SND_SOC_DAIFMT_CBM_CFM: | |
553 | aifa |= WM8580_AIF_MS; | |
554 | break; | |
555 | default: | |
556 | return -EINVAL; | |
557 | } | |
558 | ||
559 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
560 | case SND_SOC_DAIFMT_I2S: | |
561 | can_invert_lrclk = 1; | |
562 | aifb |= WM8580_AIF_FMT_I2S; | |
563 | break; | |
564 | case SND_SOC_DAIFMT_RIGHT_J: | |
565 | can_invert_lrclk = 1; | |
566 | aifb |= WM8580_AIF_FMT_RIGHTJ; | |
567 | break; | |
568 | case SND_SOC_DAIFMT_LEFT_J: | |
569 | can_invert_lrclk = 1; | |
570 | aifb |= WM8580_AIF_FMT_LEFTJ; | |
571 | break; | |
572 | case SND_SOC_DAIFMT_DSP_A: | |
573 | can_invert_lrclk = 0; | |
574 | aifb |= WM8580_AIF_FMT_DSP; | |
575 | break; | |
576 | case SND_SOC_DAIFMT_DSP_B: | |
577 | can_invert_lrclk = 0; | |
578 | aifb |= WM8580_AIF_FMT_DSP; | |
579 | aifb |= WM8580_AIF_LRP; | |
580 | break; | |
581 | default: | |
582 | return -EINVAL; | |
583 | } | |
584 | ||
585 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
586 | case SND_SOC_DAIFMT_NB_NF: | |
587 | break; | |
588 | ||
589 | case SND_SOC_DAIFMT_IB_IF: | |
590 | if (!can_invert_lrclk) | |
591 | return -EINVAL; | |
592 | aifb |= WM8580_AIF_BCP; | |
593 | aifb |= WM8580_AIF_LRP; | |
594 | break; | |
595 | ||
596 | case SND_SOC_DAIFMT_IB_NF: | |
597 | aifb |= WM8580_AIF_BCP; | |
598 | break; | |
599 | ||
600 | case SND_SOC_DAIFMT_NB_IF: | |
601 | if (!can_invert_lrclk) | |
602 | return -EINVAL; | |
603 | aifb |= WM8580_AIF_LRP; | |
604 | break; | |
605 | ||
606 | default: | |
607 | return -EINVAL; | |
608 | } | |
609 | ||
f0fba2ad LG |
610 | snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa); |
611 | snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb); | |
e88ba015 MB |
612 | |
613 | return 0; | |
614 | } | |
615 | ||
616 | static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai, | |
617 | int div_id, int div) | |
618 | { | |
619 | struct snd_soc_codec *codec = codec_dai->codec; | |
620 | unsigned int reg; | |
621 | ||
622 | switch (div_id) { | |
623 | case WM8580_MCLK: | |
f6f1eb10 | 624 | reg = snd_soc_read(codec, WM8580_PLLB4); |
e88ba015 MB |
625 | reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK; |
626 | ||
627 | switch (div) { | |
628 | case WM8580_CLKSRC_MCLK: | |
629 | /* Input */ | |
630 | break; | |
631 | ||
632 | case WM8580_CLKSRC_PLLA: | |
633 | reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA; | |
634 | break; | |
635 | case WM8580_CLKSRC_PLLB: | |
636 | reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB; | |
637 | break; | |
638 | ||
639 | case WM8580_CLKSRC_OSC: | |
640 | reg |= WM8580_PLLB4_MCLKOUTSRC_OSC; | |
641 | break; | |
642 | ||
643 | default: | |
644 | return -EINVAL; | |
645 | } | |
f6f1eb10 | 646 | snd_soc_write(codec, WM8580_PLLB4, reg); |
e88ba015 MB |
647 | break; |
648 | ||
e88ba015 | 649 | case WM8580_CLKOUTSRC: |
f6f1eb10 | 650 | reg = snd_soc_read(codec, WM8580_PLLB4); |
e88ba015 MB |
651 | reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK; |
652 | ||
653 | switch (div) { | |
654 | case WM8580_CLKSRC_NONE: | |
655 | break; | |
656 | ||
657 | case WM8580_CLKSRC_PLLA: | |
658 | reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK; | |
659 | break; | |
660 | ||
661 | case WM8580_CLKSRC_PLLB: | |
662 | reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK; | |
663 | break; | |
664 | ||
665 | case WM8580_CLKSRC_OSC: | |
666 | reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK; | |
667 | break; | |
668 | ||
669 | default: | |
670 | return -EINVAL; | |
671 | } | |
f6f1eb10 | 672 | snd_soc_write(codec, WM8580_PLLB4, reg); |
e88ba015 MB |
673 | break; |
674 | ||
675 | default: | |
676 | return -EINVAL; | |
677 | } | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
c5607d8e MB |
682 | static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
683 | unsigned int freq, int dir) | |
684 | { | |
685 | struct snd_soc_codec *codec = dai->codec; | |
686 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); | |
687 | int sel, sel_mask, sel_shift; | |
688 | ||
689 | switch (dai->driver->id) { | |
c25edef8 | 690 | case WM8580_DAI_PAIFRX: |
c5607d8e MB |
691 | sel_mask = 0x3; |
692 | sel_shift = 0; | |
693 | break; | |
694 | ||
c25edef8 | 695 | case WM8580_DAI_PAIFTX: |
c5607d8e MB |
696 | sel_mask = 0xc; |
697 | sel_shift = 2; | |
698 | break; | |
699 | ||
700 | default: | |
701 | BUG_ON("Unknown DAI driver ID\n"); | |
702 | return -EINVAL; | |
703 | } | |
704 | ||
705 | switch (clk_id) { | |
706 | case WM8580_CLKSRC_ADCMCLK: | |
06286938 | 707 | if (dai->driver->id != WM8580_DAI_PAIFTX) |
c5607d8e MB |
708 | return -EINVAL; |
709 | sel = 0 << sel_shift; | |
710 | break; | |
711 | case WM8580_CLKSRC_PLLA: | |
712 | sel = 1 << sel_shift; | |
713 | break; | |
714 | case WM8580_CLKSRC_PLLB: | |
715 | sel = 2 << sel_shift; | |
716 | break; | |
717 | case WM8580_CLKSRC_MCLK: | |
718 | sel = 3 << sel_shift; | |
719 | break; | |
720 | default: | |
721 | dev_err(codec->dev, "Unknown clock %d\n", clk_id); | |
722 | return -EINVAL; | |
723 | } | |
724 | ||
725 | /* We really should validate PLL settings but not yet */ | |
06286938 | 726 | wm8580->sysclk[dai->driver->id] = freq; |
c5607d8e | 727 | |
f538281c | 728 | return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel); |
c5607d8e MB |
729 | } |
730 | ||
e88ba015 MB |
731 | static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute) |
732 | { | |
733 | struct snd_soc_codec *codec = codec_dai->codec; | |
734 | unsigned int reg; | |
735 | ||
f6f1eb10 | 736 | reg = snd_soc_read(codec, WM8580_DAC_CONTROL5); |
e88ba015 MB |
737 | |
738 | if (mute) | |
739 | reg |= WM8580_DAC_CONTROL5_MUTEALL; | |
740 | else | |
741 | reg &= ~WM8580_DAC_CONTROL5_MUTEALL; | |
742 | ||
f6f1eb10 | 743 | snd_soc_write(codec, WM8580_DAC_CONTROL5, reg); |
e88ba015 MB |
744 | |
745 | return 0; | |
746 | } | |
747 | ||
748 | static int wm8580_set_bias_level(struct snd_soc_codec *codec, | |
749 | enum snd_soc_bias_level level) | |
750 | { | |
751 | u16 reg; | |
752 | switch (level) { | |
753 | case SND_SOC_BIAS_ON: | |
754 | case SND_SOC_BIAS_PREPARE: | |
6f7cb44b MB |
755 | break; |
756 | ||
e88ba015 | 757 | case SND_SOC_BIAS_STANDBY: |
ce6120cc | 758 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
6f7cb44b | 759 | /* Power up and get individual control of the DACs */ |
f6f1eb10 | 760 | reg = snd_soc_read(codec, WM8580_PWRDN1); |
6f7cb44b | 761 | reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD); |
f6f1eb10 | 762 | snd_soc_write(codec, WM8580_PWRDN1, reg); |
6f7cb44b | 763 | |
25985edc | 764 | /* Make VMID high impedance */ |
f6f1eb10 | 765 | reg = snd_soc_read(codec, WM8580_ADC_CONTROL1); |
6f7cb44b | 766 | reg &= ~0x100; |
f6f1eb10 | 767 | snd_soc_write(codec, WM8580_ADC_CONTROL1, reg); |
6f7cb44b | 768 | } |
e88ba015 | 769 | break; |
6f7cb44b | 770 | |
e88ba015 | 771 | case SND_SOC_BIAS_OFF: |
f6f1eb10 MB |
772 | reg = snd_soc_read(codec, WM8580_PWRDN1); |
773 | snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN); | |
e88ba015 MB |
774 | break; |
775 | } | |
ce6120cc | 776 | codec->dapm.bias_level = level; |
e88ba015 MB |
777 | return 0; |
778 | } | |
779 | ||
780 | #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
781 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
782 | ||
6335d055 | 783 | static struct snd_soc_dai_ops wm8580_dai_ops_playback = { |
c5607d8e | 784 | .set_sysclk = wm8580_set_sysclk, |
6335d055 EM |
785 | .hw_params = wm8580_paif_hw_params, |
786 | .set_fmt = wm8580_set_paif_dai_fmt, | |
787 | .set_clkdiv = wm8580_set_dai_clkdiv, | |
788 | .set_pll = wm8580_set_dai_pll, | |
789 | .digital_mute = wm8580_digital_mute, | |
790 | }; | |
791 | ||
792 | static struct snd_soc_dai_ops wm8580_dai_ops_capture = { | |
c5607d8e | 793 | .set_sysclk = wm8580_set_sysclk, |
6335d055 EM |
794 | .hw_params = wm8580_paif_hw_params, |
795 | .set_fmt = wm8580_set_paif_dai_fmt, | |
796 | .set_clkdiv = wm8580_set_dai_clkdiv, | |
797 | .set_pll = wm8580_set_dai_pll, | |
798 | }; | |
799 | ||
f0fba2ad | 800 | static struct snd_soc_dai_driver wm8580_dai[] = { |
e88ba015 | 801 | { |
f0fba2ad LG |
802 | .name = "wm8580-hifi-playback", |
803 | .id = WM8580_DAI_PAIFRX, | |
e88ba015 MB |
804 | .playback = { |
805 | .stream_name = "Playback", | |
806 | .channels_min = 1, | |
807 | .channels_max = 6, | |
808 | .rates = SNDRV_PCM_RATE_8000_192000, | |
809 | .formats = WM8580_FORMATS, | |
810 | }, | |
6335d055 | 811 | .ops = &wm8580_dai_ops_playback, |
e88ba015 MB |
812 | }, |
813 | { | |
f0fba2ad LG |
814 | .name = "wm8580-hifi-capture", |
815 | .id = WM8580_DAI_PAIFTX, | |
e88ba015 MB |
816 | .capture = { |
817 | .stream_name = "Capture", | |
818 | .channels_min = 2, | |
819 | .channels_max = 2, | |
820 | .rates = SNDRV_PCM_RATE_8000_192000, | |
821 | .formats = WM8580_FORMATS, | |
822 | }, | |
6335d055 | 823 | .ops = &wm8580_dai_ops_capture, |
e88ba015 MB |
824 | }, |
825 | }; | |
e88ba015 | 826 | |
f0fba2ad | 827 | static int wm8580_probe(struct snd_soc_codec *codec) |
e88ba015 | 828 | { |
f0fba2ad LG |
829 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
830 | int ret = 0,i; | |
6f7cb44b | 831 | |
f0fba2ad | 832 | ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type); |
f6f1eb10 MB |
833 | if (ret < 0) { |
834 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
f0fba2ad | 835 | return ret; |
f6f1eb10 MB |
836 | } |
837 | ||
a583cd53 MB |
838 | for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++) |
839 | wm8580->supplies[i].supply = wm8580_supply_names[i]; | |
840 | ||
841 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies), | |
842 | wm8580->supplies); | |
843 | if (ret != 0) { | |
844 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
f0fba2ad | 845 | return ret; |
a583cd53 MB |
846 | } |
847 | ||
848 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies), | |
849 | wm8580->supplies); | |
850 | if (ret != 0) { | |
851 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
852 | goto err_regulator_get; | |
853 | } | |
854 | ||
6f7cb44b | 855 | /* Get the codec into a known state */ |
f6f1eb10 | 856 | ret = snd_soc_write(codec, WM8580_RESET, 0); |
6f7cb44b MB |
857 | if (ret != 0) { |
858 | dev_err(codec->dev, "Failed to reset codec: %d\n", ret); | |
a583cd53 | 859 | goto err_regulator_enable; |
6f7cb44b MB |
860 | } |
861 | ||
6f7cb44b | 862 | wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
e88ba015 | 863 | |
f0fba2ad LG |
864 | snd_soc_add_controls(codec, wm8580_snd_controls, |
865 | ARRAY_SIZE(wm8580_snd_controls)); | |
866 | wm8580_add_widgets(codec); | |
6f7cb44b MB |
867 | |
868 | return 0; | |
869 | ||
a583cd53 MB |
870 | err_regulator_enable: |
871 | regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies); | |
872 | err_regulator_get: | |
873 | regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies); | |
6f7cb44b MB |
874 | return ret; |
875 | } | |
876 | ||
f0fba2ad LG |
877 | /* power down chip */ |
878 | static int wm8580_remove(struct snd_soc_codec *codec) | |
6f7cb44b | 879 | { |
f0fba2ad LG |
880 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
881 | ||
882 | wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
883 | ||
a583cd53 MB |
884 | regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies); |
885 | regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies); | |
f0fba2ad LG |
886 | |
887 | return 0; | |
6f7cb44b MB |
888 | } |
889 | ||
f0fba2ad LG |
890 | static struct snd_soc_codec_driver soc_codec_dev_wm8580 = { |
891 | .probe = wm8580_probe, | |
892 | .remove = wm8580_remove, | |
893 | .set_bias_level = wm8580_set_bias_level, | |
e5eec34c | 894 | .reg_cache_size = ARRAY_SIZE(wm8580_reg), |
f0fba2ad | 895 | .reg_word_size = sizeof(u16), |
0aa34b16 | 896 | .reg_cache_default = wm8580_reg, |
f0fba2ad LG |
897 | }; |
898 | ||
733eef3e MB |
899 | static const struct of_device_id wm8580_of_match[] = { |
900 | { .compatible = "wlf,wm8580" }, | |
901 | { }, | |
902 | }; | |
903 | ||
6f7cb44b | 904 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
17be5522 JD |
905 | static int wm8580_i2c_probe(struct i2c_client *i2c, |
906 | const struct i2c_device_id *id) | |
e88ba015 | 907 | { |
6f7cb44b | 908 | struct wm8580_priv *wm8580; |
f0fba2ad | 909 | int ret; |
6f7cb44b MB |
910 | |
911 | wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL); | |
912 | if (wm8580 == NULL) | |
913 | return -ENOMEM; | |
914 | ||
6f7cb44b | 915 | i2c_set_clientdata(i2c, wm8580); |
f0fba2ad | 916 | wm8580->control_type = SND_SOC_I2C; |
6f7cb44b | 917 | |
f0fba2ad LG |
918 | ret = snd_soc_register_codec(&i2c->dev, |
919 | &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai)); | |
920 | if (ret < 0) | |
921 | kfree(wm8580); | |
922 | return ret; | |
e88ba015 MB |
923 | } |
924 | ||
17be5522 | 925 | static int wm8580_i2c_remove(struct i2c_client *client) |
e88ba015 | 926 | { |
f0fba2ad LG |
927 | snd_soc_unregister_codec(&client->dev); |
928 | kfree(i2c_get_clientdata(client)); | |
e88ba015 MB |
929 | return 0; |
930 | } | |
931 | ||
17be5522 JD |
932 | static const struct i2c_device_id wm8580_i2c_id[] = { |
933 | { "wm8580", 0 }, | |
934 | { } | |
935 | }; | |
936 | MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id); | |
e88ba015 | 937 | |
e88ba015 MB |
938 | static struct i2c_driver wm8580_i2c_driver = { |
939 | .driver = { | |
722d0daf | 940 | .name = "wm8580", |
e88ba015 | 941 | .owner = THIS_MODULE, |
733eef3e | 942 | .of_match_table = wm8580_of_match, |
e88ba015 | 943 | }, |
17be5522 JD |
944 | .probe = wm8580_i2c_probe, |
945 | .remove = wm8580_i2c_remove, | |
946 | .id_table = wm8580_i2c_id, | |
e88ba015 | 947 | }; |
6f7cb44b | 948 | #endif |
e88ba015 | 949 | |
6f7cb44b | 950 | static int __init wm8580_modinit(void) |
17be5522 | 951 | { |
f0fba2ad | 952 | int ret = 0; |
17be5522 | 953 | |
6f7cb44b | 954 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
17be5522 JD |
955 | ret = i2c_add_driver(&wm8580_i2c_driver); |
956 | if (ret != 0) { | |
6f7cb44b | 957 | pr_err("Failed to register WM8580 I2C driver: %d\n", ret); |
e88ba015 | 958 | } |
e88ba015 | 959 | #endif |
e88ba015 | 960 | |
f0fba2ad | 961 | return ret; |
e88ba015 | 962 | } |
64089b84 MB |
963 | module_init(wm8580_modinit); |
964 | ||
965 | static void __exit wm8580_exit(void) | |
966 | { | |
6f7cb44b MB |
967 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
968 | i2c_del_driver(&wm8580_i2c_driver); | |
969 | #endif | |
64089b84 MB |
970 | } |
971 | module_exit(wm8580_exit); | |
972 | ||
e88ba015 MB |
973 | MODULE_DESCRIPTION("ASoC WM8580 driver"); |
974 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
975 | MODULE_LICENSE("GPL"); |