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ASoC: Add a bit of resource unwinding in the S3C IISv4 driver
[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / wm8580.c
CommitLineData
e88ba015
MB		 1/*
2 * wm8580.c -- WM8580 ALSA Soc Audio driver
3 *
6f7cb44b 4 * Copyright 2008, 2009 Wolfson Microelectronics PLC.
e88ba015
MB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Notes:
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
14 *
15 * Currently only the primary audio interface is supported - S/PDIF and
16 * the secondary audio interfaces are not.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
e88ba015
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
a583cd53 27#include <linux/regulator/consumer.h>
5a0e3ad6 28#include <linux/slab.h>
a583cd53 29
e88ba015
MB		 30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/tlv.h>
36#include <sound/initval.h>
37#include <asm/div64.h>
38
39#include "wm8580.h"
40
e88ba015
MB		 41/* WM8580 register space */
42#define WM8580_PLLA1 0x00
43#define WM8580_PLLA2 0x01
44#define WM8580_PLLA3 0x02
45#define WM8580_PLLA4 0x03
46#define WM8580_PLLB1 0x04
47#define WM8580_PLLB2 0x05
48#define WM8580_PLLB3 0x06
49#define WM8580_PLLB4 0x07
50#define WM8580_CLKSEL 0x08
51#define WM8580_PAIF1 0x09
52#define WM8580_PAIF2 0x0A
53#define WM8580_SAIF1 0x0B
54#define WM8580_PAIF3 0x0C
55#define WM8580_PAIF4 0x0D
56#define WM8580_SAIF2 0x0E
57#define WM8580_DAC_CONTROL1 0x0F
58#define WM8580_DAC_CONTROL2 0x10
59#define WM8580_DAC_CONTROL3 0x11
60#define WM8580_DAC_CONTROL4 0x12
61#define WM8580_DAC_CONTROL5 0x13
62#define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
63#define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
64#define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
65#define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
66#define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
67#define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
68#define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
69#define WM8580_ADC_CONTROL1 0x1D
70#define WM8580_SPDTXCHAN0 0x1E
71#define WM8580_SPDTXCHAN1 0x1F
72#define WM8580_SPDTXCHAN2 0x20
73#define WM8580_SPDTXCHAN3 0x21
74#define WM8580_SPDTXCHAN4 0x22
75#define WM8580_SPDTXCHAN5 0x23
76#define WM8580_SPDMODE 0x24
77#define WM8580_INTMASK 0x25
78#define WM8580_GPO1 0x26
79#define WM8580_GPO2 0x27
80#define WM8580_GPO3 0x28
81#define WM8580_GPO4 0x29
82#define WM8580_GPO5 0x2A
83#define WM8580_INTSTAT 0x2B
84#define WM8580_SPDRXCHAN1 0x2C
85#define WM8580_SPDRXCHAN2 0x2D
86#define WM8580_SPDRXCHAN3 0x2E
87#define WM8580_SPDRXCHAN4 0x2F
88#define WM8580_SPDRXCHAN5 0x30
89#define WM8580_SPDSTAT 0x31
90#define WM8580_PWRDN1 0x32
91#define WM8580_PWRDN2 0x33
92#define WM8580_READBACK 0x34
93#define WM8580_RESET 0x35
94
6f7cb44b
MB		 95#define WM8580_MAX_REGISTER 0x35
96
e88ba015
MB		 97/* PLLB4 (register 7h) */
98#define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
99#define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
100#define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
101#define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
102
103#define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
104#define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
105#define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
106#define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
107
108/* CLKSEL (register 8h) */
109#define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
110#define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
111#define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
112
113/* AIF control 1 (registers 9h-bh) */
114#define WM8580_AIF_RATE_MASK 0x7
115#define WM8580_AIF_RATE_128 0x0
116#define WM8580_AIF_RATE_192 0x1
117#define WM8580_AIF_RATE_256 0x2
118#define WM8580_AIF_RATE_384 0x3
119#define WM8580_AIF_RATE_512 0x4
120#define WM8580_AIF_RATE_768 0x5
121#define WM8580_AIF_RATE_1152 0x6
122
123#define WM8580_AIF_BCLKSEL_MASK 0x18
124#define WM8580_AIF_BCLKSEL_64 0x00
125#define WM8580_AIF_BCLKSEL_128 0x08
126#define WM8580_AIF_BCLKSEL_256 0x10
127#define WM8580_AIF_BCLKSEL_SYSCLK 0x18
128
129#define WM8580_AIF_MS 0x20
130
131#define WM8580_AIF_CLKSRC_MASK 0xc0
132#define WM8580_AIF_CLKSRC_PLLA 0x40
133#define WM8580_AIF_CLKSRC_PLLB 0x40
134#define WM8580_AIF_CLKSRC_MCLK 0xc0
135
136/* AIF control 2 (registers ch-eh) */
137#define WM8580_AIF_FMT_MASK 0x03
138#define WM8580_AIF_FMT_RIGHTJ 0x00
139#define WM8580_AIF_FMT_LEFTJ 0x01
140#define WM8580_AIF_FMT_I2S 0x02
141#define WM8580_AIF_FMT_DSP 0x03
142
143#define WM8580_AIF_LENGTH_MASK 0x0c
144#define WM8580_AIF_LENGTH_16 0x00
145#define WM8580_AIF_LENGTH_20 0x04
146#define WM8580_AIF_LENGTH_24 0x08
147#define WM8580_AIF_LENGTH_32 0x0c
148
149#define WM8580_AIF_LRP 0x10
150#define WM8580_AIF_BCP 0x20
151
152/* Powerdown Register 1 (register 32h) */
153#define WM8580_PWRDN1_PWDN 0x001
154#define WM8580_PWRDN1_ALLDACPD 0x040
155
156/* Powerdown Register 2 (register 33h) */
157#define WM8580_PWRDN2_OSSCPD 0x001
158#define WM8580_PWRDN2_PLLAPD 0x002
159#define WM8580_PWRDN2_PLLBPD 0x004
160#define WM8580_PWRDN2_SPDIFPD 0x008
161#define WM8580_PWRDN2_SPDIFTXD 0x010
162#define WM8580_PWRDN2_SPDIFRXD 0x020
163
164#define WM8580_DAC_CONTROL5_MUTEALL 0x10
165
166/*
167 * wm8580 register cache
168 * We can't read the WM8580 register space when we
169 * are using 2 wire for device control, so we cache them instead.
170 */
171static const u16 wm8580_reg[] = {
172 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
173 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
174 0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
175 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
176 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
177 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
178 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
179 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
180 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
181 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
182 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
183 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
184 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
185 0x0000, 0x0000 /*R53*/
186};
187
6f7cb44b
MB		 188struct pll_state {
189 unsigned int in;
190 unsigned int out;
191};
192
a583cd53
MB		 193#define WM8580_NUM_SUPPLIES 3
194static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
195 "AVDD",
196 "DVDD",
197 "PVDD",
198};
199
6f7cb44b
MB		 200/* codec private data */
201struct wm8580_priv {
f0fba2ad 202 enum snd_soc_control_type control_type;
a583cd53 203 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
6f7cb44b
MB		 204 u16 reg_cache[WM8580_MAX_REGISTER + 1];
205 struct pll_state a;
206 struct pll_state b;
207};
208
e88ba015
MB		 209static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
210
211static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
212 struct snd_ctl_elem_value *ucontrol)
213{
ccb077fd
MB		 214 struct soc_mixer_control *mc =
215 (struct soc_mixer_control *)kcontrol->private_value;
e88ba015 216 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f6f1eb10 217 u16 *reg_cache = codec->reg_cache;
ccb077fd
MB		 218 unsigned int reg = mc->reg;
219 unsigned int reg2 = mc->rreg;
e88ba015 220 int ret;
e88ba015
MB		 221
222 /* Clear the register cache so we write without VU set */
f6f1eb10
MB		 223 reg_cache[reg] = 0;
224 reg_cache[reg2] = 0;
e88ba015
MB		 225
226 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
227 if (ret < 0)
228 return ret;
229
230 /* Now write again with the volume update bit set */
f6f1eb10
MB		 231 snd_soc_update_bits(codec, reg, 0x100, 0x100);
232 snd_soc_update_bits(codec, reg2, 0x100, 0x100);
e88ba015
MB		 233
234 return 0;
235}
236
ccb077fd
MB		 237#define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
238 xinvert, tlv_array) \
e88ba015
MB		 239{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
240 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
241 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
242 .tlv.p = (tlv_array), \
243 .info = snd_soc_info_volsw_2r, \
244 .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
ccb077fd
MB		 245 .private_value = (unsigned long)&(struct soc_mixer_control) \
246 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
247 .max = xmax, .invert = xinvert} }
e88ba015
MB		 248
249static const struct snd_kcontrol_new wm8580_snd_controls[] = {
250SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
251 WM8580_DIGITAL_ATTENUATION_DACL1,
252 WM8580_DIGITAL_ATTENUATION_DACR1,
253 0, 0xff, 0, dac_tlv),
254SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
255 WM8580_DIGITAL_ATTENUATION_DACL2,
256 WM8580_DIGITAL_ATTENUATION_DACR2,
257 0, 0xff, 0, dac_tlv),
258SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
259 WM8580_DIGITAL_ATTENUATION_DACL3,
260 WM8580_DIGITAL_ATTENUATION_DACR3,
261 0, 0xff, 0, dac_tlv),
262
263SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
264SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
265SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
266
267SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
268SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
269SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
270
271SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
272SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
273SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
274SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
275
6f341d14
MB		 276SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
277SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
e88ba015
MB		 278};
279
e88ba015
MB		 280static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
281SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
282SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
283SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
284
285SND_SOC_DAPM_OUTPUT("VOUT1L"),
286SND_SOC_DAPM_OUTPUT("VOUT1R"),
287SND_SOC_DAPM_OUTPUT("VOUT2L"),
288SND_SOC_DAPM_OUTPUT("VOUT2R"),
289SND_SOC_DAPM_OUTPUT("VOUT3L"),
290SND_SOC_DAPM_OUTPUT("VOUT3R"),
291
292SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
293
294SND_SOC_DAPM_INPUT("AINL"),
295SND_SOC_DAPM_INPUT("AINR"),
296};
297
298static const struct snd_soc_dapm_route audio_map[] = {
299 { "VOUT1L", NULL, "DAC1" },
300 { "VOUT1R", NULL, "DAC1" },
301
302 { "VOUT2L", NULL, "DAC2" },
303 { "VOUT2R", NULL, "DAC2" },
304
305 { "VOUT3L", NULL, "DAC3" },
306 { "VOUT3R", NULL, "DAC3" },
307
308 { "ADC", NULL, "AINL" },
309 { "ADC", NULL, "AINR" },
310};
311
312static int wm8580_add_widgets(struct snd_soc_codec *codec)
313{
314 snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
315 ARRAY_SIZE(wm8580_dapm_widgets));
316
317 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
318
e88ba015
MB		 319 return 0;
320}
321
322/* PLL divisors */
323struct _pll_div {
324 u32 prescale:1;
325 u32 postscale:1;
326 u32 freqmode:2;
327 u32 n:4;
328 u32 k:24;
329};
330
331/* The size in bits of the pll divide */
332#define FIXED_PLL_SIZE (1 << 22)
333
334/* PLL rate to output rate divisions */
335static struct {
336 unsigned int div;
337 unsigned int freqmode;
338 unsigned int postscale;
339} post_table[] = {
340 { 2, 0, 0 },
341 { 4, 0, 1 },
342 { 4, 1, 0 },
343 { 8, 1, 1 },
344 { 8, 2, 0 },
345 { 16, 2, 1 },
346 { 12, 3, 0 },
347 { 24, 3, 1 }
348};
349
350static int pll_factors(struct _pll_div *pll_div, unsigned int target,
351 unsigned int source)
352{
353 u64 Kpart;
354 unsigned int K, Ndiv, Nmod;
355 int i;
356
449bd54d 357 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
e88ba015
MB		 358
359 /* Scale the output frequency up; the PLL should run in the
360 * region of 90-100MHz.
361 */
362 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
363 if (target * post_table[i].div >= 90000000 &&
364 target * post_table[i].div <= 100000000) {
365 pll_div->freqmode = post_table[i].freqmode;
366 pll_div->postscale = post_table[i].postscale;
367 target *= post_table[i].div;
368 break;
369 }
370 }
371
372 if (i == ARRAY_SIZE(post_table)) {
373 printk(KERN_ERR "wm8580: Unable to scale output frequency "
374 "%u\n", target);
375 return -EINVAL;
376 }
377
378 Ndiv = target / source;
379
380 if (Ndiv < 5) {
381 source /= 2;
382 pll_div->prescale = 1;
383 Ndiv = target / source;
384 } else
385 pll_div->prescale = 0;
386
387 if ((Ndiv < 5) || (Ndiv > 13)) {
388 printk(KERN_ERR
449bd54d 389 "WM8580 N=%u outside supported range\n", Ndiv);
e88ba015
MB		 390 return -EINVAL;
391 }
392
393 pll_div->n = Ndiv;
394 Nmod = target % source;
395 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
396
397 do_div(Kpart, source);
398
399 K = Kpart & 0xFFFFFFFF;
400
401 pll_div->k = K;
402
403 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
404 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
405 pll_div->postscale);
406
407 return 0;
408}
409
85488037
MB		 410static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
411 int source, unsigned int freq_in, unsigned int freq_out)
e88ba015
MB		 412{
413 int offset;
414 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 415 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
e88ba015
MB		 416 struct pll_state *state;
417 struct _pll_div pll_div;
418 unsigned int reg;
419 unsigned int pwr_mask;
420 int ret;
421
422 /* GCC isn't able to work out the ifs below for initialising/using
423 * pll_div so suppress warnings.
424 */
425 memset(&pll_div, 0, sizeof(pll_div));
426
427 switch (pll_id) {
428 case WM8580_PLLA:
429 state = &wm8580->a;
430 offset = 0;
431 pwr_mask = WM8580_PWRDN2_PLLAPD;
432 break;
433 case WM8580_PLLB:
434 state = &wm8580->b;
435 offset = 4;
436 pwr_mask = WM8580_PWRDN2_PLLBPD;
437 break;
438 default:
439 return -ENODEV;
440 }
441
442 if (freq_in && freq_out) {
443 ret = pll_factors(&pll_div, freq_out, freq_in);
444 if (ret != 0)
445 return ret;
446 }
447
448 state->in = freq_in;
449 state->out = freq_out;
450
451 /* Always disable the PLL - it is not safe to leave it running
452 * while reprogramming it.
453 */
f6f1eb10
MB		 454 reg = snd_soc_read(codec, WM8580_PWRDN2);
455 snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
e88ba015
MB		 456
457 if (!freq_in || !freq_out)
458 return 0;
459
f6f1eb10 460 snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
5c0d38c9 461 snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
f6f1eb10 462 snd_soc_write(codec, WM8580_PLLA3 + offset,
e88ba015
MB		 463 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
464
f6f1eb10 465 reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
5c0d38c9 466 reg &= ~0x1b;
e88ba015 467 reg |= pll_div.prescale | pll_div.postscale << 1 |
ce88168f 468 pll_div.freqmode << 3;
e88ba015 469
f6f1eb10 470 snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
e88ba015
MB		 471
472 /* All done, turn it on */
f6f1eb10
MB		 473 reg = snd_soc_read(codec, WM8580_PWRDN2);
474 snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
e88ba015
MB		 475
476 return 0;
477}
478
479/*
480 * Set PCM DAI bit size and sample rate.
481 */
482static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 483 struct snd_pcm_hw_params *params,
484 struct snd_soc_dai *dai)
e88ba015
MB		 485{
486 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad
LG		 487 struct snd_soc_codec *codec = rtd->codec;
488 u16 paifb = snd_soc_read(codec, WM8580_PAIF3 + dai->driver->id);
e88ba015
MB		 489
490 paifb &= ~WM8580_AIF_LENGTH_MASK;
491 /* bit size */
492 switch (params_format(params)) {
493 case SNDRV_PCM_FORMAT_S16_LE:
494 break;
495 case SNDRV_PCM_FORMAT_S20_3LE:
496 paifb |= WM8580_AIF_LENGTH_20;
497 break;
498 case SNDRV_PCM_FORMAT_S24_LE:
499 paifb |= WM8580_AIF_LENGTH_24;
500 break;
501 case SNDRV_PCM_FORMAT_S32_LE:
502 paifb |= WM8580_AIF_LENGTH_24;
503 break;
504 default:
505 return -EINVAL;
506 }
507
f0fba2ad 508 snd_soc_write(codec, WM8580_PAIF3 + dai->driver->id, paifb);
e88ba015
MB		 509 return 0;
510}
511
512static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
513 unsigned int fmt)
514{
515 struct snd_soc_codec *codec = codec_dai->codec;
516 unsigned int aifa;
517 unsigned int aifb;
518 int can_invert_lrclk;
519
f0fba2ad
LG		 520 aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
521 aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
e88ba015
MB		 522
523 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
524
525 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
526 case SND_SOC_DAIFMT_CBS_CFS:
527 aifa &= ~WM8580_AIF_MS;
528 break;
529 case SND_SOC_DAIFMT_CBM_CFM:
530 aifa |= WM8580_AIF_MS;
531 break;
532 default:
533 return -EINVAL;
534 }
535
536 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
537 case SND_SOC_DAIFMT_I2S:
538 can_invert_lrclk = 1;
539 aifb |= WM8580_AIF_FMT_I2S;
540 break;
541 case SND_SOC_DAIFMT_RIGHT_J:
542 can_invert_lrclk = 1;
543 aifb |= WM8580_AIF_FMT_RIGHTJ;
544 break;
545 case SND_SOC_DAIFMT_LEFT_J:
546 can_invert_lrclk = 1;
547 aifb |= WM8580_AIF_FMT_LEFTJ;
548 break;
549 case SND_SOC_DAIFMT_DSP_A:
550 can_invert_lrclk = 0;
551 aifb |= WM8580_AIF_FMT_DSP;
552 break;
553 case SND_SOC_DAIFMT_DSP_B:
554 can_invert_lrclk = 0;
555 aifb |= WM8580_AIF_FMT_DSP;
556 aifb |= WM8580_AIF_LRP;
557 break;
558 default:
559 return -EINVAL;
560 }
561
562 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
563 case SND_SOC_DAIFMT_NB_NF:
564 break;
565
566 case SND_SOC_DAIFMT_IB_IF:
567 if (!can_invert_lrclk)
568 return -EINVAL;
569 aifb |= WM8580_AIF_BCP;
570 aifb |= WM8580_AIF_LRP;
571 break;
572
573 case SND_SOC_DAIFMT_IB_NF:
574 aifb |= WM8580_AIF_BCP;
575 break;
576
577 case SND_SOC_DAIFMT_NB_IF:
578 if (!can_invert_lrclk)
579 return -EINVAL;
580 aifb |= WM8580_AIF_LRP;
581 break;
582
583 default:
584 return -EINVAL;
585 }
586
f0fba2ad
LG		 587 snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
588 snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
e88ba015
MB		 589
590 return 0;
591}
592
593static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
594 int div_id, int div)
595{
596 struct snd_soc_codec *codec = codec_dai->codec;
597 unsigned int reg;
598
599 switch (div_id) {
600 case WM8580_MCLK:
f6f1eb10 601 reg = snd_soc_read(codec, WM8580_PLLB4);
e88ba015
MB		 602 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
603
604 switch (div) {
605 case WM8580_CLKSRC_MCLK:
606 /* Input */
607 break;
608
609 case WM8580_CLKSRC_PLLA:
610 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
611 break;
612 case WM8580_CLKSRC_PLLB:
613 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
614 break;
615
616 case WM8580_CLKSRC_OSC:
617 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
618 break;
619
620 default:
621 return -EINVAL;
622 }
f6f1eb10 623 snd_soc_write(codec, WM8580_PLLB4, reg);
e88ba015
MB		 624 break;
625
626 case WM8580_DAC_CLKSEL:
f6f1eb10 627 reg = snd_soc_read(codec, WM8580_CLKSEL);
e88ba015
MB		 628 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
629
630 switch (div) {
631 case WM8580_CLKSRC_MCLK:
632 break;
633
634 case WM8580_CLKSRC_PLLA:
635 reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
636 break;
637
638 case WM8580_CLKSRC_PLLB:
639 reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
640 break;
641
642 default:
643 return -EINVAL;
644 }
f6f1eb10 645 snd_soc_write(codec, WM8580_CLKSEL, reg);
e88ba015
MB		 646 break;
647
648 case WM8580_CLKOUTSRC:
f6f1eb10 649 reg = snd_soc_read(codec, WM8580_PLLB4);
e88ba015
MB		 650 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
651
652 switch (div) {
653 case WM8580_CLKSRC_NONE:
654 break;
655
656 case WM8580_CLKSRC_PLLA:
657 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
658 break;
659
660 case WM8580_CLKSRC_PLLB:
661 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
662 break;
663
664 case WM8580_CLKSRC_OSC:
665 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
666 break;
667
668 default:
669 return -EINVAL;
670 }
f6f1eb10 671 snd_soc_write(codec, WM8580_PLLB4, reg);
e88ba015
MB		 672 break;
673
674 default:
675 return -EINVAL;
676 }
677
678 return 0;
679}
680
681static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
682{
683 struct snd_soc_codec *codec = codec_dai->codec;
684 unsigned int reg;
685
f6f1eb10 686 reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
e88ba015
MB		 687
688 if (mute)
689 reg |= WM8580_DAC_CONTROL5_MUTEALL;
690 else
691 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
692
f6f1eb10 693 snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
e88ba015
MB		 694
695 return 0;
696}
697
698static int wm8580_set_bias_level(struct snd_soc_codec *codec,
699 enum snd_soc_bias_level level)
700{
701 u16 reg;
702 switch (level) {
703 case SND_SOC_BIAS_ON:
704 case SND_SOC_BIAS_PREPARE:
6f7cb44b
MB		 705 break;
706
e88ba015 707 case SND_SOC_BIAS_STANDBY:
6f7cb44b
MB		 708 if (codec->bias_level == SND_SOC_BIAS_OFF) {
709 /* Power up and get individual control of the DACs */
f6f1eb10 710 reg = snd_soc_read(codec, WM8580_PWRDN1);
6f7cb44b 711 reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
f6f1eb10 712 snd_soc_write(codec, WM8580_PWRDN1, reg);
6f7cb44b
MB		 713
714 /* Make VMID high impedence */
f6f1eb10 715 reg = snd_soc_read(codec, WM8580_ADC_CONTROL1);
6f7cb44b 716 reg &= ~0x100;
f6f1eb10 717 snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
6f7cb44b 718 }
e88ba015 719 break;
6f7cb44b 720
e88ba015 721 case SND_SOC_BIAS_OFF:
f6f1eb10
MB		 722 reg = snd_soc_read(codec, WM8580_PWRDN1);
723 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
e88ba015
MB		 724 break;
725 }
726 codec->bias_level = level;
727 return 0;
728}
729
730#define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
731 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
732
6335d055
EM		 733static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
734 .hw_params = wm8580_paif_hw_params,
735 .set_fmt = wm8580_set_paif_dai_fmt,
736 .set_clkdiv = wm8580_set_dai_clkdiv,
737 .set_pll = wm8580_set_dai_pll,
738 .digital_mute = wm8580_digital_mute,
739};
740
741static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
742 .hw_params = wm8580_paif_hw_params,
743 .set_fmt = wm8580_set_paif_dai_fmt,
744 .set_clkdiv = wm8580_set_dai_clkdiv,
745 .set_pll = wm8580_set_dai_pll,
746};
747
f0fba2ad 748static struct snd_soc_dai_driver wm8580_dai[] = {
e88ba015 749 {
f0fba2ad
LG		 750 .name = "wm8580-hifi-playback",
751 .id = WM8580_DAI_PAIFRX,
e88ba015
MB		 752 .playback = {
753 .stream_name = "Playback",
754 .channels_min = 1,
755 .channels_max = 6,
756 .rates = SNDRV_PCM_RATE_8000_192000,
757 .formats = WM8580_FORMATS,
758 },
6335d055 759 .ops = &wm8580_dai_ops_playback,
e88ba015
MB		 760 },
761 {
f0fba2ad
LG		 762 .name = "wm8580-hifi-capture",
763 .id = WM8580_DAI_PAIFTX,
e88ba015
MB		 764 .capture = {
765 .stream_name = "Capture",
766 .channels_min = 2,
767 .channels_max = 2,
768 .rates = SNDRV_PCM_RATE_8000_192000,
769 .formats = WM8580_FORMATS,
770 },
6335d055 771 .ops = &wm8580_dai_ops_capture,
e88ba015
MB		 772 },
773};
e88ba015 774
f0fba2ad 775static int wm8580_probe(struct snd_soc_codec *codec)
e88ba015 776{
f0fba2ad
LG		 777 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
778 int ret = 0,i;
6f7cb44b 779
f0fba2ad 780 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
f6f1eb10
MB		 781 if (ret < 0) {
782 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 783 return ret;
f6f1eb10
MB		 784 }
785
a583cd53
MB		 786 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
787 wm8580->supplies[i].supply = wm8580_supply_names[i];
788
789 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
790 wm8580->supplies);
791 if (ret != 0) {
792 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
f0fba2ad 793 return ret;
a583cd53
MB		 794 }
795
796 ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
797 wm8580->supplies);
798 if (ret != 0) {
799 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
800 goto err_regulator_get;
801 }
802
6f7cb44b 803 /* Get the codec into a known state */
f6f1eb10 804 ret = snd_soc_write(codec, WM8580_RESET, 0);
6f7cb44b
MB		 805 if (ret != 0) {
806 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
a583cd53 807 goto err_regulator_enable;
6f7cb44b
MB		 808 }
809
6f7cb44b 810 wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
e88ba015 811
f0fba2ad
LG		 812 snd_soc_add_controls(codec, wm8580_snd_controls,
813 ARRAY_SIZE(wm8580_snd_controls));
814 wm8580_add_widgets(codec);
6f7cb44b
MB		 815
816 return 0;
817
a583cd53
MB		 818err_regulator_enable:
819 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
820err_regulator_get:
821 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
6f7cb44b
MB		 822 return ret;
823}
824
f0fba2ad
LG		 825/* power down chip */
826static int wm8580_remove(struct snd_soc_codec *codec)
6f7cb44b 827{
f0fba2ad
LG		 828 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
829
830 wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
831
a583cd53
MB		 832 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
833 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
f0fba2ad
LG		 834
835 return 0;
6f7cb44b
MB		 836}
837
f0fba2ad
LG		 838static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
839 .probe = wm8580_probe,
840 .remove = wm8580_remove,
841 .set_bias_level = wm8580_set_bias_level,
842 .reg_cache_size = sizeof(wm8580_reg),
843 .reg_word_size = sizeof(u16),
844 .reg_cache_default = &wm8580_reg,
845};
846
6f7cb44b 847#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
17be5522
JD		 848static int wm8580_i2c_probe(struct i2c_client *i2c,
849 const struct i2c_device_id *id)
e88ba015 850{
6f7cb44b 851 struct wm8580_priv *wm8580;
f0fba2ad 852 int ret;
6f7cb44b
MB		 853
854 wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
855 if (wm8580 == NULL)
856 return -ENOMEM;
857
6f7cb44b 858 i2c_set_clientdata(i2c, wm8580);
f0fba2ad 859 wm8580->control_type = SND_SOC_I2C;
6f7cb44b 860
f0fba2ad
LG		 861 ret = snd_soc_register_codec(&i2c->dev,
862 &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
863 if (ret < 0)
864 kfree(wm8580);
865 return ret;
e88ba015
MB		 866}
867
17be5522 868static int wm8580_i2c_remove(struct i2c_client *client)
e88ba015 869{
f0fba2ad
LG		 870 snd_soc_unregister_codec(&client->dev);
871 kfree(i2c_get_clientdata(client));
e88ba015
MB		 872 return 0;
873}
874
17be5522
JD		 875static const struct i2c_device_id wm8580_i2c_id[] = {
876 { "wm8580", 0 },
877 { }
878};
879MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
e88ba015 880
e88ba015
MB		 881static struct i2c_driver wm8580_i2c_driver = {
882 .driver = {
f0fba2ad 883 .name = "wm8580-codec",
e88ba015
MB		 884 .owner = THIS_MODULE,
885 },
17be5522
JD		 886 .probe = wm8580_i2c_probe,
887 .remove = wm8580_i2c_remove,
888 .id_table = wm8580_i2c_id,
e88ba015 889};
6f7cb44b 890#endif
e88ba015 891
6f7cb44b 892static int __init wm8580_modinit(void)
17be5522 893{
f0fba2ad 894 int ret = 0;
17be5522 895
6f7cb44b 896#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
17be5522
JD		 897 ret = i2c_add_driver(&wm8580_i2c_driver);
898 if (ret != 0) {
6f7cb44b 899 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
e88ba015 900 }
e88ba015 901#endif
e88ba015 902
f0fba2ad 903 return ret;
e88ba015 904}
64089b84
MB		 905module_init(wm8580_modinit);
906
907static void __exit wm8580_exit(void)
908{
6f7cb44b
MB		 909#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
910 i2c_del_driver(&wm8580_i2c_driver);
911#endif
64089b84
MB		 912}
913module_exit(wm8580_exit);
914
e88ba015
MB		 915MODULE_DESCRIPTION("ASoC WM8580 driver");
916MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
917MODULE_LICENSE("GPL");
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