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[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / wm8580.c
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2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
e88ba015 2/*
028f5a5b 3 * wm8580.c -- WM8580 and WM8581 ALSA Soc Audio driver
e88ba015 4 *
b689d9f9 5 * Copyright 2008-12 Wolfson Microelectronics PLC.
e88ba015 6 *
e88ba015
MB		 7 * Notes:
8 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
9 * DAC channels and two ADC channels.
10 *
028f5a5b
MF		 11 * The WM8581 is a multichannel codec with S/PDIF support, featuring eight
12 * DAC channels and two ADC channels.
13 *
e88ba015
MB		 14 * Currently only the primary audio interface is supported - S/PDIF and
15 * the secondary audio interfaces are not.
16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
e88ba015
MB		 20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/pm.h>
24#include <linux/i2c.h>
b689d9f9 25#include <linux/regmap.h>
a583cd53 26#include <linux/regulator/consumer.h>
5a0e3ad6 27#include <linux/slab.h>
733eef3e 28#include <linux/of_device.h>
a583cd53 29
e88ba015
MB		 30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
e88ba015
MB		 34#include <sound/tlv.h>
35#include <sound/initval.h>
36#include <asm/div64.h>
37
38#include "wm8580.h"
39
e88ba015
MB		 40/* WM8580 register space */
41#define WM8580_PLLA1 0x00
42#define WM8580_PLLA2 0x01
43#define WM8580_PLLA3 0x02
44#define WM8580_PLLA4 0x03
45#define WM8580_PLLB1 0x04
46#define WM8580_PLLB2 0x05
47#define WM8580_PLLB3 0x06
48#define WM8580_PLLB4 0x07
49#define WM8580_CLKSEL 0x08
50#define WM8580_PAIF1 0x09
51#define WM8580_PAIF2 0x0A
52#define WM8580_SAIF1 0x0B
53#define WM8580_PAIF3 0x0C
54#define WM8580_PAIF4 0x0D
55#define WM8580_SAIF2 0x0E
56#define WM8580_DAC_CONTROL1 0x0F
57#define WM8580_DAC_CONTROL2 0x10
58#define WM8580_DAC_CONTROL3 0x11
59#define WM8580_DAC_CONTROL4 0x12
60#define WM8580_DAC_CONTROL5 0x13
61#define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
62#define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
63#define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
64#define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
65#define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
66#define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
028f5a5b
MF		 67#define WM8581_DIGITAL_ATTENUATION_DACL4 0x1A
68#define WM8581_DIGITAL_ATTENUATION_DACR4 0x1B
e88ba015
MB		 69#define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
70#define WM8580_ADC_CONTROL1 0x1D
71#define WM8580_SPDTXCHAN0 0x1E
72#define WM8580_SPDTXCHAN1 0x1F
73#define WM8580_SPDTXCHAN2 0x20
74#define WM8580_SPDTXCHAN3 0x21
75#define WM8580_SPDTXCHAN4 0x22
76#define WM8580_SPDTXCHAN5 0x23
77#define WM8580_SPDMODE 0x24
78#define WM8580_INTMASK 0x25
79#define WM8580_GPO1 0x26
80#define WM8580_GPO2 0x27
81#define WM8580_GPO3 0x28
82#define WM8580_GPO4 0x29
83#define WM8580_GPO5 0x2A
84#define WM8580_INTSTAT 0x2B
85#define WM8580_SPDRXCHAN1 0x2C
86#define WM8580_SPDRXCHAN2 0x2D
87#define WM8580_SPDRXCHAN3 0x2E
88#define WM8580_SPDRXCHAN4 0x2F
89#define WM8580_SPDRXCHAN5 0x30
90#define WM8580_SPDSTAT 0x31
91#define WM8580_PWRDN1 0x32
92#define WM8580_PWRDN2 0x33
93#define WM8580_READBACK 0x34
94#define WM8580_RESET 0x35
95
6f7cb44b
MB		 96#define WM8580_MAX_REGISTER 0x35
97
6bfb6aa9
MB		 98#define WM8580_DACOSR 0x40
99
e88ba015
MB		 100/* PLLB4 (register 7h) */
101#define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
102#define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
103#define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
104#define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
105
106#define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
107#define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
108#define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
109#define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
110
111/* CLKSEL (register 8h) */
112#define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
113#define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
114#define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
115
116/* AIF control 1 (registers 9h-bh) */
117#define WM8580_AIF_RATE_MASK 0x7
e88ba015 118#define WM8580_AIF_BCLKSEL_MASK 0x18
e88ba015
MB		 119
120#define WM8580_AIF_MS 0x20
121
122#define WM8580_AIF_CLKSRC_MASK 0xc0
123#define WM8580_AIF_CLKSRC_PLLA 0x40
124#define WM8580_AIF_CLKSRC_PLLB 0x40
125#define WM8580_AIF_CLKSRC_MCLK 0xc0
126
127/* AIF control 2 (registers ch-eh) */
128#define WM8580_AIF_FMT_MASK 0x03
129#define WM8580_AIF_FMT_RIGHTJ 0x00
130#define WM8580_AIF_FMT_LEFTJ 0x01
131#define WM8580_AIF_FMT_I2S 0x02
132#define WM8580_AIF_FMT_DSP 0x03
133
134#define WM8580_AIF_LENGTH_MASK 0x0c
135#define WM8580_AIF_LENGTH_16 0x00
136#define WM8580_AIF_LENGTH_20 0x04
137#define WM8580_AIF_LENGTH_24 0x08
138#define WM8580_AIF_LENGTH_32 0x0c
139
140#define WM8580_AIF_LRP 0x10
141#define WM8580_AIF_BCP 0x20
142
143/* Powerdown Register 1 (register 32h) */
144#define WM8580_PWRDN1_PWDN 0x001
145#define WM8580_PWRDN1_ALLDACPD 0x040
146
147/* Powerdown Register 2 (register 33h) */
148#define WM8580_PWRDN2_OSSCPD 0x001
149#define WM8580_PWRDN2_PLLAPD 0x002
150#define WM8580_PWRDN2_PLLBPD 0x004
151#define WM8580_PWRDN2_SPDIFPD 0x008
152#define WM8580_PWRDN2_SPDIFTXD 0x010
153#define WM8580_PWRDN2_SPDIFRXD 0x020
154
155#define WM8580_DAC_CONTROL5_MUTEALL 0x10
156
157/*
158 * wm8580 register cache
159 * We can't read the WM8580 register space when we
160 * are using 2 wire for device control, so we cache them instead.
161 */
b689d9f9
MB		 162static const struct reg_default wm8580_reg_defaults[] = {
163 { 0, 0x0121 },
164 { 1, 0x017e },
165 { 2, 0x007d },
166 { 3, 0x0014 },
167 { 4, 0x0121 },
168 { 5, 0x017e },
169 { 6, 0x007d },
170 { 7, 0x0194 },
171 { 8, 0x0010 },
172 { 9, 0x0002 },
173 { 10, 0x0002 },
174 { 11, 0x00c2 },
175 { 12, 0x0182 },
176 { 13, 0x0082 },
177 { 14, 0x000a },
178 { 15, 0x0024 },
179 { 16, 0x0009 },
180 { 17, 0x0000 },
181 { 18, 0x00ff },
182 { 19, 0x0000 },
183 { 20, 0x00ff },
184 { 21, 0x00ff },
185 { 22, 0x00ff },
186 { 23, 0x00ff },
187 { 24, 0x00ff },
188 { 25, 0x00ff },
189 { 26, 0x00ff },
190 { 27, 0x00ff },
191 { 28, 0x01f0 },
192 { 29, 0x0040 },
193 { 30, 0x0000 },
194 { 31, 0x0000 },
195 { 32, 0x0000 },
196 { 33, 0x0000 },
197 { 34, 0x0031 },
198 { 35, 0x000b },
199 { 36, 0x0039 },
200 { 37, 0x0000 },
201 { 38, 0x0010 },
202 { 39, 0x0032 },
203 { 40, 0x0054 },
204 { 41, 0x0076 },
205 { 42, 0x0098 },
206 { 43, 0x0000 },
207 { 44, 0x0000 },
208 { 45, 0x0000 },
209 { 46, 0x0000 },
210 { 47, 0x0000 },
211 { 48, 0x0000 },
212 { 49, 0x0000 },
213 { 50, 0x005e },
214 { 51, 0x003e },
215 { 52, 0x0000 },
e88ba015
MB		 216};
217
b689d9f9
MB		 218static bool wm8580_volatile(struct device *dev, unsigned int reg)
219{
220 switch (reg) {
221 case WM8580_RESET:
222 return true;
223 default:
224 return false;
225 }
226}
227
6f7cb44b
MB		 228struct pll_state {
229 unsigned int in;
230 unsigned int out;
231};
232
a583cd53
MB		 233#define WM8580_NUM_SUPPLIES 3
234static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
235 "AVDD",
236 "DVDD",
237 "PVDD",
238};
239
028f5a5b
MF		 240struct wm8580_driver_data {
241 int num_dacs;
242};
243
6f7cb44b
MB		 244/* codec private data */
245struct wm8580_priv {
b689d9f9 246 struct regmap *regmap;
a583cd53 247 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
6f7cb44b
MB		 248 struct pll_state a;
249 struct pll_state b;
028f5a5b 250 const struct wm8580_driver_data *drvdata;
c5607d8e 251 int sysclk[2];
6f7cb44b
MB		 252};
253
e88ba015
MB		 254static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
255
256static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
257 struct snd_ctl_elem_value *ucontrol)
258{
ccb077fd
MB		 259 struct soc_mixer_control *mc =
260 (struct soc_mixer_control *)kcontrol->private_value;
8f5a5935
KM		 261 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
262 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
ccb077fd
MB		 263 unsigned int reg = mc->reg;
264 unsigned int reg2 = mc->rreg;
e88ba015 265 int ret;
e88ba015 266
b689d9f9
MB		 267 /* Clear the register cache VU so we write without VU set */
268 regcache_cache_only(wm8580->regmap, true);
269 regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000);
270 regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000);
271 regcache_cache_only(wm8580->regmap, false);
e88ba015 272
c4671a95 273 ret = snd_soc_put_volsw(kcontrol, ucontrol);
e88ba015
MB		 274 if (ret < 0)
275 return ret;
276
277 /* Now write again with the volume update bit set */
8f5a5935
KM		 278 snd_soc_component_update_bits(component, reg, 0x100, 0x100);
279 snd_soc_component_update_bits(component, reg2, 0x100, 0x100);
e88ba015
MB		 280
281 return 0;
282}
283
e88ba015 284static const struct snd_kcontrol_new wm8580_snd_controls[] = {
0f9887d1
PU		 285SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
286 WM8580_DIGITAL_ATTENUATION_DACL1,
287 WM8580_DIGITAL_ATTENUATION_DACR1,
c4671a95 288 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
0f9887d1
PU		 289SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
290 WM8580_DIGITAL_ATTENUATION_DACL2,
291 WM8580_DIGITAL_ATTENUATION_DACR2,
c4671a95 292 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
0f9887d1
PU		 293SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
294 WM8580_DIGITAL_ATTENUATION_DACL3,
295 WM8580_DIGITAL_ATTENUATION_DACR3,
c4671a95 296 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
e88ba015
MB		 297
298SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
299SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
300SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
301
302SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
303SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
304SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
305
306SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
4f0ed9a5
MB		 307SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
308SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
309SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
e88ba015 310
dacfe9f2 311SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
6f341d14 312SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
e88ba015
MB		 313};
314
028f5a5b
MF		 315static const struct snd_kcontrol_new wm8581_snd_controls[] = {
316SOC_DOUBLE_R_EXT_TLV("DAC4 Playback Volume",
317 WM8581_DIGITAL_ATTENUATION_DACL4,
318 WM8581_DIGITAL_ATTENUATION_DACR4,
319 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
320
321SOC_SINGLE("DAC4 Deemphasis Switch", WM8580_DAC_CONTROL3, 3, 1, 0),
322
323SOC_DOUBLE("DAC4 Invert Switch", WM8580_DAC_CONTROL4, 8, 7, 1, 0),
324
325SOC_SINGLE("DAC4 Switch", WM8580_DAC_CONTROL5, 3, 1, 1),
326};
327
e88ba015
MB		 328static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
329SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
330SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
331SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
332
333SND_SOC_DAPM_OUTPUT("VOUT1L"),
334SND_SOC_DAPM_OUTPUT("VOUT1R"),
335SND_SOC_DAPM_OUTPUT("VOUT2L"),
336SND_SOC_DAPM_OUTPUT("VOUT2R"),
337SND_SOC_DAPM_OUTPUT("VOUT3L"),
338SND_SOC_DAPM_OUTPUT("VOUT3R"),
339
340SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
341
342SND_SOC_DAPM_INPUT("AINL"),
343SND_SOC_DAPM_INPUT("AINR"),
344};
345
028f5a5b
MF		 346static const struct snd_soc_dapm_widget wm8581_dapm_widgets[] = {
347SND_SOC_DAPM_DAC("DAC4", "Playback", WM8580_PWRDN1, 5, 1),
348
349SND_SOC_DAPM_OUTPUT("VOUT4L"),
350SND_SOC_DAPM_OUTPUT("VOUT4R"),
351};
352
f235c649 353static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
e88ba015
MB		 354 { "VOUT1L", NULL, "DAC1" },
355 { "VOUT1R", NULL, "DAC1" },
356
357 { "VOUT2L", NULL, "DAC2" },
358 { "VOUT2R", NULL, "DAC2" },
359
360 { "VOUT3L", NULL, "DAC3" },
361 { "VOUT3R", NULL, "DAC3" },
362
363 { "ADC", NULL, "AINL" },
364 { "ADC", NULL, "AINR" },
365};
366
028f5a5b
MF		 367static const struct snd_soc_dapm_route wm8581_dapm_routes[] = {
368 { "VOUT4L", NULL, "DAC4" },
369 { "VOUT4R", NULL, "DAC4" },
370};
371
e88ba015
MB		 372/* PLL divisors */
373struct _pll_div {
374 u32 prescale:1;
375 u32 postscale:1;
376 u32 freqmode:2;
377 u32 n:4;
378 u32 k:24;
379};
380
381/* The size in bits of the pll divide */
382#define FIXED_PLL_SIZE (1 << 22)
383
384/* PLL rate to output rate divisions */
385static struct {
386 unsigned int div;
387 unsigned int freqmode;
388 unsigned int postscale;
389} post_table[] = {
390 { 2, 0, 0 },
391 { 4, 0, 1 },
392 { 4, 1, 0 },
393 { 8, 1, 1 },
394 { 8, 2, 0 },
395 { 16, 2, 1 },
396 { 12, 3, 0 },
397 { 24, 3, 1 }
398};
399
400static int pll_factors(struct _pll_div *pll_div, unsigned int target,
401 unsigned int source)
402{
403 u64 Kpart;
404 unsigned int K, Ndiv, Nmod;
405 int i;
406
449bd54d 407 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
e88ba015
MB		 408
409 /* Scale the output frequency up; the PLL should run in the
410 * region of 90-100MHz.
411 */
412 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
413 if (target * post_table[i].div >= 90000000 &&
414 target * post_table[i].div <= 100000000) {
415 pll_div->freqmode = post_table[i].freqmode;
416 pll_div->postscale = post_table[i].postscale;
417 target *= post_table[i].div;
418 break;
419 }
420 }
421
422 if (i == ARRAY_SIZE(post_table)) {
423 printk(KERN_ERR "wm8580: Unable to scale output frequency "
424 "%u\n", target);
425 return -EINVAL;
426 }
427
428 Ndiv = target / source;
429
430 if (Ndiv < 5) {
431 source /= 2;
432 pll_div->prescale = 1;
433 Ndiv = target / source;
434 } else
435 pll_div->prescale = 0;
436
437 if ((Ndiv < 5) || (Ndiv > 13)) {
438 printk(KERN_ERR
449bd54d 439 "WM8580 N=%u outside supported range\n", Ndiv);
e88ba015
MB		 440 return -EINVAL;
441 }
442
443 pll_div->n = Ndiv;
444 Nmod = target % source;
445 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
446
447 do_div(Kpart, source);
448
449 K = Kpart & 0xFFFFFFFF;
450
451 pll_div->k = K;
452
453 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
454 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
455 pll_div->postscale);
456
457 return 0;
458}
459
85488037
MB		 460static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
461 int source, unsigned int freq_in, unsigned int freq_out)
e88ba015
MB		 462{
463 int offset;
8f5a5935
KM		 464 struct snd_soc_component *component = codec_dai->component;
465 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
e88ba015
MB		 466 struct pll_state *state;
467 struct _pll_div pll_div;
468 unsigned int reg;
469 unsigned int pwr_mask;
470 int ret;
471
472 /* GCC isn't able to work out the ifs below for initialising/using
473 * pll_div so suppress warnings.
474 */
475 memset(&pll_div, 0, sizeof(pll_div));
476
477 switch (pll_id) {
478 case WM8580_PLLA:
479 state = &wm8580->a;
480 offset = 0;
481 pwr_mask = WM8580_PWRDN2_PLLAPD;
482 break;
483 case WM8580_PLLB:
484 state = &wm8580->b;
485 offset = 4;
486 pwr_mask = WM8580_PWRDN2_PLLBPD;
487 break;
488 default:
489 return -ENODEV;
490 }
491
492 if (freq_in && freq_out) {
493 ret = pll_factors(&pll_div, freq_out, freq_in);
494 if (ret != 0)
495 return ret;
496 }
497
498 state->in = freq_in;
499 state->out = freq_out;
500
501 /* Always disable the PLL - it is not safe to leave it running
502 * while reprogramming it.
503 */
8f5a5935 504 snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, pwr_mask);
e88ba015
MB		 505
506 if (!freq_in || !freq_out)
507 return 0;
508
8f5a5935
KM		 509 snd_soc_component_write(component, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
510 snd_soc_component_write(component, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
511 snd_soc_component_write(component, WM8580_PLLA3 + offset,
e88ba015
MB		 512 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
513
6d75dfc3 514 reg = snd_soc_component_read(component, WM8580_PLLA4 + offset);
5c0d38c9 515 reg &= ~0x1b;
e88ba015 516 reg |= pll_div.prescale | pll_div.postscale << 1 |
ce88168f 517 pll_div.freqmode << 3;
e88ba015 518
8f5a5935 519 snd_soc_component_write(component, WM8580_PLLA4 + offset, reg);
e88ba015
MB		 520
521 /* All done, turn it on */
8f5a5935 522 snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, 0);
e88ba015
MB		 523
524 return 0;
525}
526
c5607d8e
MB		 527static const int wm8580_sysclk_ratios[] = {
528 128, 192, 256, 384, 512, 768, 1152,
529};
530
e88ba015
MB		 531/*
532 * Set PCM DAI bit size and sample rate.
533 */
534static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 535 struct snd_pcm_hw_params *params,
536 struct snd_soc_dai *dai)
e88ba015 537{
8f5a5935
KM		 538 struct snd_soc_component *component = dai->component;
539 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
c5607d8e 540 u16 paifa = 0;
e231cab0 541 u16 paifb = 0;
6bfb6aa9 542 int i, ratio, osr;
e88ba015 543
e88ba015 544 /* bit size */
993ba8e5
MB		 545 switch (params_width(params)) {
546 case 16:
ba2772ed 547 paifa |= 0x8;
e88ba015 548 break;
993ba8e5 549 case 20:
6b464321 550 paifa |= 0x0;
e88ba015
MB		 551 paifb |= WM8580_AIF_LENGTH_20;
552 break;
993ba8e5 553 case 24:
6b464321 554 paifa |= 0x0;
e88ba015
MB		 555 paifb |= WM8580_AIF_LENGTH_24;
556 break;
993ba8e5 557 case 32:
6b464321
JB		 558 paifa |= 0x0;
559 paifb |= WM8580_AIF_LENGTH_32;
e88ba015
MB		 560 break;
561 default:
562 return -EINVAL;
563 }
564
c5607d8e 565 /* Look up the SYSCLK ratio; accept only exact matches */
06286938 566 ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
c5607d8e
MB		 567 for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
568 if (ratio == wm8580_sysclk_ratios[i])
569 break;
570 if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
8f5a5935 571 dev_err(component->dev, "Invalid clock ratio %d/%d\n",
06286938 572 wm8580->sysclk[dai->driver->id], params_rate(params));
c5607d8e
MB		 573 return -EINVAL;
574 }
575 paifa |= i;
8f5a5935 576 dev_dbg(component->dev, "Running at %dfs with %dHz clock\n",
c5607d8e
MB		 577 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
578
6bfb6aa9
MB		 579 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
580 switch (ratio) {
581 case 128:
582 case 192:
583 osr = WM8580_DACOSR;
8f5a5935 584 dev_dbg(component->dev, "Selecting 64x OSR\n");
6bfb6aa9
MB		 585 break;
586 default:
587 osr = 0;
8f5a5935 588 dev_dbg(component->dev, "Selecting 128x OSR\n");
6bfb6aa9
MB		 589 break;
590 }
591
8f5a5935 592 snd_soc_component_update_bits(component, WM8580_PAIF3, WM8580_DACOSR, osr);
6bfb6aa9
MB		 593 }
594
8f5a5935 595 snd_soc_component_update_bits(component, WM8580_PAIF1 + dai->driver->id,
ba2772ed
MB		 596 WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
597 paifa);
8f5a5935 598 snd_soc_component_update_bits(component, WM8580_PAIF3 + dai->driver->id,
e231cab0 599 WM8580_AIF_LENGTH_MASK, paifb);
e88ba015
MB		 600 return 0;
601}
602
603static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
604 unsigned int fmt)
605{
8f5a5935 606 struct snd_soc_component *component = codec_dai->component;
e88ba015
MB		 607 unsigned int aifa;
608 unsigned int aifb;
609 int can_invert_lrclk;
610
6d75dfc3
KM		 611 aifa = snd_soc_component_read(component, WM8580_PAIF1 + codec_dai->driver->id);
612 aifb = snd_soc_component_read(component, WM8580_PAIF3 + codec_dai->driver->id);
e88ba015
MB		 613
614 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
615
616 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
617 case SND_SOC_DAIFMT_CBS_CFS:
618 aifa &= ~WM8580_AIF_MS;
619 break;
620 case SND_SOC_DAIFMT_CBM_CFM:
621 aifa |= WM8580_AIF_MS;
622 break;
623 default:
624 return -EINVAL;
625 }
626
627 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
628 case SND_SOC_DAIFMT_I2S:
629 can_invert_lrclk = 1;
630 aifb |= WM8580_AIF_FMT_I2S;
631 break;
632 case SND_SOC_DAIFMT_RIGHT_J:
633 can_invert_lrclk = 1;
634 aifb |= WM8580_AIF_FMT_RIGHTJ;
635 break;
636 case SND_SOC_DAIFMT_LEFT_J:
637 can_invert_lrclk = 1;
638 aifb |= WM8580_AIF_FMT_LEFTJ;
639 break;
640 case SND_SOC_DAIFMT_DSP_A:
641 can_invert_lrclk = 0;
642 aifb |= WM8580_AIF_FMT_DSP;
643 break;
644 case SND_SOC_DAIFMT_DSP_B:
645 can_invert_lrclk = 0;
646 aifb |= WM8580_AIF_FMT_DSP;
647 aifb |= WM8580_AIF_LRP;
648 break;
649 default:
650 return -EINVAL;
651 }
652
653 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
654 case SND_SOC_DAIFMT_NB_NF:
655 break;
656
657 case SND_SOC_DAIFMT_IB_IF:
658 if (!can_invert_lrclk)
659 return -EINVAL;
660 aifb |= WM8580_AIF_BCP;
661 aifb |= WM8580_AIF_LRP;
662 break;
663
664 case SND_SOC_DAIFMT_IB_NF:
665 aifb |= WM8580_AIF_BCP;
666 break;
667
668 case SND_SOC_DAIFMT_NB_IF:
669 if (!can_invert_lrclk)
670 return -EINVAL;
671 aifb |= WM8580_AIF_LRP;
672 break;
673
674 default:
675 return -EINVAL;
676 }
677
8f5a5935
KM		 678 snd_soc_component_write(component, WM8580_PAIF1 + codec_dai->driver->id, aifa);
679 snd_soc_component_write(component, WM8580_PAIF3 + codec_dai->driver->id, aifb);
e88ba015
MB		 680
681 return 0;
682}
683
684static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
685 int div_id, int div)
686{
8f5a5935 687 struct snd_soc_component *component = codec_dai->component;
e88ba015
MB		 688 unsigned int reg;
689
690 switch (div_id) {
691 case WM8580_MCLK:
6d75dfc3 692 reg = snd_soc_component_read(component, WM8580_PLLB4);
e88ba015
MB		 693 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
694
695 switch (div) {
696 case WM8580_CLKSRC_MCLK:
697 /* Input */
698 break;
699
700 case WM8580_CLKSRC_PLLA:
701 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
702 break;
703 case WM8580_CLKSRC_PLLB:
704 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
705 break;
706
707 case WM8580_CLKSRC_OSC:
708 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
709 break;
710
711 default:
712 return -EINVAL;
713 }
8f5a5935 714 snd_soc_component_write(component, WM8580_PLLB4, reg);
e88ba015
MB		 715 break;
716
e88ba015 717 case WM8580_CLKOUTSRC:
6d75dfc3 718 reg = snd_soc_component_read(component, WM8580_PLLB4);
e88ba015
MB		 719 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
720
721 switch (div) {
722 case WM8580_CLKSRC_NONE:
723 break;
724
725 case WM8580_CLKSRC_PLLA:
726 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
727 break;
728
729 case WM8580_CLKSRC_PLLB:
730 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
731 break;
732
733 case WM8580_CLKSRC_OSC:
734 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
735 break;
736
737 default:
738 return -EINVAL;
739 }
8f5a5935 740 snd_soc_component_write(component, WM8580_PLLB4, reg);
e88ba015
MB		 741 break;
742
743 default:
744 return -EINVAL;
745 }
746
747 return 0;
748}
749
c5607d8e
MB		 750static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
751 unsigned int freq, int dir)
752{
8f5a5935
KM		 753 struct snd_soc_component *component = dai->component;
754 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
748b2178 755 int ret, sel, sel_mask, sel_shift;
c5607d8e
MB		 756
757 switch (dai->driver->id) {
c25edef8 758 case WM8580_DAI_PAIFRX:
c5607d8e
MB		 759 sel_mask = 0x3;
760 sel_shift = 0;
761 break;
762
c25edef8 763 case WM8580_DAI_PAIFTX:
c5607d8e
MB		 764 sel_mask = 0xc;
765 sel_shift = 2;
766 break;
767
768 default:
4a9e0f91 769 WARN(1, "Unknown DAI driver ID\n");
c5607d8e
MB		 770 return -EINVAL;
771 }
772
773 switch (clk_id) {
774 case WM8580_CLKSRC_ADCMCLK:
06286938 775 if (dai->driver->id != WM8580_DAI_PAIFTX)
c5607d8e
MB		 776 return -EINVAL;
777 sel = 0 << sel_shift;
778 break;
779 case WM8580_CLKSRC_PLLA:
780 sel = 1 << sel_shift;
781 break;
782 case WM8580_CLKSRC_PLLB:
783 sel = 2 << sel_shift;
784 break;
785 case WM8580_CLKSRC_MCLK:
786 sel = 3 << sel_shift;
787 break;
788 default:
8f5a5935 789 dev_err(component->dev, "Unknown clock %d\n", clk_id);
c5607d8e
MB		 790 return -EINVAL;
791 }
792
793 /* We really should validate PLL settings but not yet */
06286938 794 wm8580->sysclk[dai->driver->id] = freq;
c5607d8e 795
8f5a5935 796 ret = snd_soc_component_update_bits(component, WM8580_CLKSEL, sel_mask, sel);
748b2178
AL		 797 if (ret < 0)
798 return ret;
799
800 return 0;
c5607d8e
MB		 801}
802
26d3c16e 803static int wm8580_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
e88ba015 804{
8f5a5935 805 struct snd_soc_component *component = codec_dai->component;
e88ba015
MB		 806 unsigned int reg;
807
6d75dfc3 808 reg = snd_soc_component_read(component, WM8580_DAC_CONTROL5);
e88ba015
MB		 809
810 if (mute)
811 reg |= WM8580_DAC_CONTROL5_MUTEALL;
812 else
813 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
814
8f5a5935 815 snd_soc_component_write(component, WM8580_DAC_CONTROL5, reg);
e88ba015
MB		 816
817 return 0;
818}
819
8f5a5935 820static int wm8580_set_bias_level(struct snd_soc_component *component,
e88ba015
MB		 821 enum snd_soc_bias_level level)
822{
e88ba015
MB		 823 switch (level) {
824 case SND_SOC_BIAS_ON:
825 case SND_SOC_BIAS_PREPARE:
6f7cb44b
MB		 826 break;
827
e88ba015 828 case SND_SOC_BIAS_STANDBY:
8f5a5935 829 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
6f7cb44b 830 /* Power up and get individual control of the DACs */
8f5a5935 831 snd_soc_component_update_bits(component, WM8580_PWRDN1,
a6785d7d
AL		 832 WM8580_PWRDN1_PWDN |
833 WM8580_PWRDN1_ALLDACPD, 0);
6f7cb44b 834
25985edc 835 /* Make VMID high impedance */
8f5a5935 836 snd_soc_component_update_bits(component, WM8580_ADC_CONTROL1,
a6785d7d 837 0x100, 0);
6f7cb44b 838 }
e88ba015 839 break;
6f7cb44b 840
e88ba015 841 case SND_SOC_BIAS_OFF:
8f5a5935 842 snd_soc_component_update_bits(component, WM8580_PWRDN1,
a6785d7d 843 WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
e88ba015
MB		 844 break;
845 }
e88ba015
MB		 846 return 0;
847}
848
028f5a5b
MF		 849static int wm8580_playback_startup(struct snd_pcm_substream *substream,
850 struct snd_soc_dai *dai)
851{
8f5a5935
KM		 852 struct snd_soc_component *component = dai->component;
853 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
028f5a5b
MF		 854
855 return snd_pcm_hw_constraint_minmax(substream->runtime,
856 SNDRV_PCM_HW_PARAM_CHANNELS, 1, wm8580->drvdata->num_dacs * 2);
857}
858
e88ba015
MB		 859#define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
860 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
861
85e7652d 862static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
028f5a5b 863 .startup = wm8580_playback_startup,
c5607d8e 864 .set_sysclk = wm8580_set_sysclk,
6335d055
EM		 865 .hw_params = wm8580_paif_hw_params,
866 .set_fmt = wm8580_set_paif_dai_fmt,
867 .set_clkdiv = wm8580_set_dai_clkdiv,
868 .set_pll = wm8580_set_dai_pll,
26d3c16e
KM		 869 .mute_stream = wm8580_mute,
870 .no_capture_mute = 1,
6335d055
EM		 871};
872
85e7652d 873static const struct snd_soc_dai_ops wm8580_dai_ops_capture = {
c5607d8e 874 .set_sysclk = wm8580_set_sysclk,
6335d055
EM		 875 .hw_params = wm8580_paif_hw_params,
876 .set_fmt = wm8580_set_paif_dai_fmt,
877 .set_clkdiv = wm8580_set_dai_clkdiv,
878 .set_pll = wm8580_set_dai_pll,
879};
880
f0fba2ad 881static struct snd_soc_dai_driver wm8580_dai[] = {
e88ba015 882 {
f0fba2ad
LG		 883 .name = "wm8580-hifi-playback",
884 .id = WM8580_DAI_PAIFRX,
e88ba015
MB		 885 .playback = {
886 .stream_name = "Playback",
887 .channels_min = 1,
e88ba015
MB		 888 .rates = SNDRV_PCM_RATE_8000_192000,
889 .formats = WM8580_FORMATS,
890 },
6335d055 891 .ops = &wm8580_dai_ops_playback,
e88ba015
MB		 892 },
893 {
f0fba2ad
LG		 894 .name = "wm8580-hifi-capture",
895 .id = WM8580_DAI_PAIFTX,
e88ba015
MB		 896 .capture = {
897 .stream_name = "Capture",
898 .channels_min = 2,
899 .channels_max = 2,
900 .rates = SNDRV_PCM_RATE_8000_192000,
901 .formats = WM8580_FORMATS,
902 },
6335d055 903 .ops = &wm8580_dai_ops_capture,
e88ba015
MB		 904 },
905};
e88ba015 906
8f5a5935 907static int wm8580_probe(struct snd_soc_component *component)
e88ba015 908{
8f5a5935
KM		 909 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
910 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
18273b05 911 int ret = 0;
6f7cb44b 912
028f5a5b
MF		 913 switch (wm8580->drvdata->num_dacs) {
914 case 4:
8f5a5935 915 snd_soc_add_component_controls(component, wm8581_snd_controls,
028f5a5b
MF		 916 ARRAY_SIZE(wm8581_snd_controls));
917 snd_soc_dapm_new_controls(dapm, wm8581_dapm_widgets,
918 ARRAY_SIZE(wm8581_dapm_widgets));
919 snd_soc_dapm_add_routes(dapm, wm8581_dapm_routes,
920 ARRAY_SIZE(wm8581_dapm_routes));
921 break;
922 default:
923 break;
924 }
925
a583cd53
MB		 926 ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
927 wm8580->supplies);
928 if (ret != 0) {
8f5a5935 929 dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
a583cd53
MB		 930 goto err_regulator_get;
931 }
932
6f7cb44b 933 /* Get the codec into a known state */
8f5a5935 934 ret = snd_soc_component_write(component, WM8580_RESET, 0);
6f7cb44b 935 if (ret != 0) {
8f5a5935 936 dev_err(component->dev, "Failed to reset component: %d\n", ret);
a583cd53 937 goto err_regulator_enable;
6f7cb44b
MB		 938 }
939
6f7cb44b
MB		 940 return 0;
941
a583cd53
MB		 942err_regulator_enable:
943 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
944err_regulator_get:
6f7cb44b
MB		 945 return ret;
946}
947
f0fba2ad 948/* power down chip */
8f5a5935 949static void wm8580_remove(struct snd_soc_component *component)
6f7cb44b 950{
8f5a5935 951 struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
f0fba2ad 952
a583cd53 953 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
6f7cb44b
MB		 954}
955
8f5a5935
KM		 956static const struct snd_soc_component_driver soc_component_dev_wm8580 = {
957 .probe = wm8580_probe,
958 .remove = wm8580_remove,
959 .set_bias_level = wm8580_set_bias_level,
960 .controls = wm8580_snd_controls,
961 .num_controls = ARRAY_SIZE(wm8580_snd_controls),
962 .dapm_widgets = wm8580_dapm_widgets,
963 .num_dapm_widgets = ARRAY_SIZE(wm8580_dapm_widgets),
964 .dapm_routes = wm8580_dapm_routes,
965 .num_dapm_routes = ARRAY_SIZE(wm8580_dapm_routes),
966 .idle_bias_on = 1,
967 .use_pmdown_time = 1,
968 .endianness = 1,
969 .non_legacy_dai_naming = 1,
f0fba2ad
LG		 970};
971
b689d9f9
MB		 972static const struct regmap_config wm8580_regmap = {
973 .reg_bits = 7,
974 .val_bits = 9,
975 .max_register = WM8580_MAX_REGISTER,
976
977 .reg_defaults = wm8580_reg_defaults,
978 .num_reg_defaults = ARRAY_SIZE(wm8580_reg_defaults),
979 .cache_type = REGCACHE_RBTREE,
980
981 .volatile_reg = wm8580_volatile,
982};
983
2f3d1b65 984static const struct wm8580_driver_data wm8580_data = {
028f5a5b
MF		 985 .num_dacs = 3,
986};
987
2f3d1b65 988static const struct wm8580_driver_data wm8581_data = {
028f5a5b
MF		 989 .num_dacs = 4,
990};
991
992static const struct of_device_id wm8580_of_match[] = {
993 { .compatible = "wlf,wm8580", .data = &wm8580_data },
994 { .compatible = "wlf,wm8581", .data = &wm8581_data },
995 { },
996};
997MODULE_DEVICE_TABLE(of, wm8580_of_match);
998
17be5522
JD		 999static int wm8580_i2c_probe(struct i2c_client *i2c,
1000 const struct i2c_device_id *id)
e88ba015 1001{
028f5a5b 1002 const struct of_device_id *of_id;
6f7cb44b 1003 struct wm8580_priv *wm8580;
18273b05 1004 int ret, i;
6f7cb44b 1005
398c02f6
MB		 1006 wm8580 = devm_kzalloc(&i2c->dev, sizeof(struct wm8580_priv),
1007 GFP_KERNEL);
6f7cb44b
MB		 1008 if (wm8580 == NULL)
1009 return -ENOMEM;
1010
b689d9f9
MB		 1011 wm8580->regmap = devm_regmap_init_i2c(i2c, &wm8580_regmap);
1012 if (IS_ERR(wm8580->regmap))
1013 return PTR_ERR(wm8580->regmap);
1014
18273b05
MB		 1015 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
1016 wm8580->supplies[i].supply = wm8580_supply_names[i];
1017
1018 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8580->supplies),
1019 wm8580->supplies);
1020 if (ret != 0) {
1021 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1022 return ret;
1023 }
1024
6f7cb44b 1025 i2c_set_clientdata(i2c, wm8580);
6f7cb44b 1026
028f5a5b
MF		 1027 of_id = of_match_device(wm8580_of_match, &i2c->dev);
1028 if (of_id)
1029 wm8580->drvdata = of_id->data;
1030
1031 if (!wm8580->drvdata) {
1032 dev_err(&i2c->dev, "failed to find driver data\n");
1033 return -EINVAL;
1034 }
1035
8f5a5935
KM		 1036 ret = devm_snd_soc_register_component(&i2c->dev,
1037 &soc_component_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
398c02f6 1038
f0fba2ad 1039 return ret;
e88ba015
MB		 1040}
1041
17be5522 1042static const struct i2c_device_id wm8580_i2c_id[] = {
028f5a5b
MF		 1043 { "wm8580", (kernel_ulong_t)&wm8580_data },
1044 { "wm8581", (kernel_ulong_t)&wm8581_data },
17be5522
JD		 1045 { }
1046};
1047MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
e88ba015 1048
e88ba015
MB		 1049static struct i2c_driver wm8580_i2c_driver = {
1050 .driver = {
722d0daf 1051 .name = "wm8580",
733eef3e 1052 .of_match_table = wm8580_of_match,
e88ba015 1053 },
17be5522 1054 .probe = wm8580_i2c_probe,
17be5522 1055 .id_table = wm8580_i2c_id,
e88ba015
MB		 1056};
1057
60bc6173 1058module_i2c_driver(wm8580_i2c_driver);
64089b84 1059
e88ba015
MB		 1060MODULE_DESCRIPTION("ASoC WM8580 driver");
1061MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
028f5a5b 1062MODULE_AUTHOR("Matt Flax <flatmax@flatmax.org>");
e88ba015 1063MODULE_LICENSE("GPL");
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