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ASoC: multi-component - ASoC Multi-Component Support
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8753.c
CommitLineData
1f53aee0
LG		 1/*
2 * wm8753.c -- WM8753 ALSA Soc Audio driver
3 *
4 * Copyright 2003 Wolfson Microelectronics PLC.
d331124d 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
1f53aee0
LG		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * Notes:
13 * The WM8753 is a low power, high quality stereo codec with integrated PCM
14 * codec designed for portable digital telephony applications.
15 *
16 * Dual DAI:-
17 *
18 * This driver support 2 DAI PCM's. This makes the default PCM available for
19 * HiFi audio (e.g. MP3, ogg) playback/capture and the other PCM available for
20 * voice.
21 *
22 * Please note that the voice PCM can be connected directly to a Bluetooth
23 * codec or GSM modem and thus cannot be read or written to, although it is
24 * available to be configured with snd_hw_params(), etc and kcontrols in the
25 * normal alsa manner.
26 *
27 * Fast DAI switching:-
28 *
29 * The driver can now fast switch between the DAI configurations via a
30 * an alsa kcontrol. This allows the PCM to remain open.
31 *
32 */
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
1f53aee0
LG		 36#include <linux/kernel.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
41#include <linux/platform_device.h>
dd0c0c80 42#include <linux/spi/spi.h>
5a0e3ad6 43#include <linux/slab.h>
1f53aee0
LG		 44#include <sound/core.h>
45#include <sound/pcm.h>
46#include <sound/pcm_params.h>
47#include <sound/soc.h>
48#include <sound/soc-dapm.h>
49#include <sound/initval.h>
2d6a4ac9 50#include <sound/tlv.h>
1f53aee0
LG		 51#include <asm/div64.h>
52
53#include "wm8753.h"
54
1f53aee0
LG		 55static int caps_charge = 2000;
56module_param(caps_charge, int, 0);
57MODULE_PARM_DESC(caps_charge, "WM8753 cap charge time (msecs)");
58
59static void wm8753_set_dai_mode(struct snd_soc_codec *codec,
f0fba2ad 60 struct snd_soc_dai *dai, unsigned int hifi);
1f53aee0 61
1f53aee0
LG		 62/*
63 * wm8753 register cache
64 * We can't read the WM8753 register space when we
65 * are using 2 wire for device control, so we cache them instead.
66 */
67static const u16 wm8753_reg[] = {
68 0x0008, 0x0000, 0x000a, 0x000a,
69 0x0033, 0x0000, 0x0007, 0x00ff,
70 0x00ff, 0x000f, 0x000f, 0x007b,
71 0x0000, 0x0032, 0x0000, 0x00c3,
72 0x00c3, 0x00c0, 0x0000, 0x0000,
73 0x0000, 0x0000, 0x0000, 0x0000,
74 0x0000, 0x0000, 0x0000, 0x0000,
75 0x0000, 0x0000, 0x0000, 0x0055,
76 0x0005, 0x0050, 0x0055, 0x0050,
77 0x0055, 0x0050, 0x0055, 0x0079,
78 0x0079, 0x0079, 0x0079, 0x0079,
79 0x0000, 0x0000, 0x0000, 0x0000,
80 0x0097, 0x0097, 0x0000, 0x0004,
81 0x0000, 0x0083, 0x0024, 0x01ba,
82 0x0000, 0x0083, 0x0024, 0x01ba,
637a935a 83 0x0000, 0x0000, 0x0000
1f53aee0
LG		 84};
85
c2bac160
MB		 86/* codec private data */
87struct wm8753_priv {
f0fba2ad
LG		 88 enum snd_soc_control_type control_type;
89 void *control_data;
c2bac160
MB		 90 unsigned int sysclk;
91 unsigned int pcmclk;
c2bac160 92 u16 reg_cache[ARRAY_SIZE(wm8753_reg)];
f0fba2ad 93 int dai_func;
c2bac160
MB		 94};
95
1f53aee0
LG		 96/*
97 * read wm8753 register cache
98 */
99static inline unsigned int wm8753_read_reg_cache(struct snd_soc_codec *codec,
100 unsigned int reg)
101{
102 u16 *cache = codec->reg_cache;
91432e97 103 if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1))
1f53aee0
LG		 104 return -1;
105 return cache[reg - 1];
106}
107
108/*
109 * write wm8753 register cache
110 */
111static inline void wm8753_write_reg_cache(struct snd_soc_codec *codec,
112 unsigned int reg, unsigned int value)
113{
114 u16 *cache = codec->reg_cache;
91432e97 115 if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1))
1f53aee0
LG		 116 return;
117 cache[reg - 1] = value;
118}
119
120/*
121 * write to the WM8753 register space
122 */
123static int wm8753_write(struct snd_soc_codec *codec, unsigned int reg,
124 unsigned int value)
125{
126 u8 data[2];
127
128 /* data is
129 * D15..D9 WM8753 register offset
130 * D8...D0 register data
131 */
132 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
133 data[1] = value & 0x00ff;
134
60fc684a 135 wm8753_write_reg_cache(codec, reg, value);
1f53aee0
LG		 136 if (codec->hw_write(codec->control_data, data, 2) == 2)
137 return 0;
138 else
139 return -EIO;
140}
141
142#define wm8753_reset(c) wm8753_write(c, WM8753_RESET, 0)
143
144/*
145 * WM8753 Controls
146 */
147static const char *wm8753_base[] = {"Linear Control", "Adaptive Boost"};
148static const char *wm8753_base_filter[] =
149 {"130Hz @ 48kHz", "200Hz @ 48kHz", "100Hz @ 16kHz", "400Hz @ 48kHz",
150 "100Hz @ 8kHz", "200Hz @ 8kHz"};
151static const char *wm8753_treble[] = {"8kHz", "4kHz"};
152static const char *wm8753_alc_func[] = {"Off", "Right", "Left", "Stereo"};
153static const char *wm8753_ng_type[] = {"Constant PGA Gain", "Mute ADC Output"};
154static const char *wm8753_3d_func[] = {"Capture", "Playback"};
155static const char *wm8753_3d_uc[] = {"2.2kHz", "1.5kHz"};
156static const char *wm8753_3d_lc[] = {"200Hz", "500Hz"};
157static const char *wm8753_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz"};
158static const char *wm8753_mono_mix[] = {"Stereo", "Left", "Right", "Mono"};
159static const char *wm8753_dac_phase[] = {"Non Inverted", "Inverted"};
160static const char *wm8753_line_mix[] = {"Line 1 + 2", "Line 1 - 2",
161 "Line 1", "Line 2"};
162static const char *wm8753_mono_mux[] = {"Line Mix", "Rx Mix"};
163static const char *wm8753_right_mux[] = {"Line 2", "Rx Mix"};
164static const char *wm8753_left_mux[] = {"Line 1", "Rx Mix"};
165static const char *wm8753_rxmsel[] = {"RXP - RXN", "RXP + RXN", "RXP", "RXN"};
166static const char *wm8753_sidetone_mux[] = {"Left PGA", "Mic 1", "Mic 2",
167 "Right PGA"};
168static const char *wm8753_mono2_src[] = {"Inverted Mono 1", "Left", "Right",
169 "Left + Right"};
170static const char *wm8753_out3[] = {"VREF", "ROUT2", "Left + Right"};
171static const char *wm8753_out4[] = {"VREF", "Capture ST", "LOUT2"};
172static const char *wm8753_radcsel[] = {"PGA", "Line or RXP-RXN", "Sidetone"};
173static const char *wm8753_ladcsel[] = {"PGA", "Line or RXP-RXN", "Line"};
174static const char *wm8753_mono_adc[] = {"Stereo", "Analogue Mix Left",
175 "Analogue Mix Right", "Digital Mono Mix"};
176static const char *wm8753_adc_hp[] = {"3.4Hz @ 48kHz", "82Hz @ 16k",
177 "82Hz @ 8kHz", "170Hz @ 8kHz"};
178static const char *wm8753_adc_filter[] = {"HiFi", "Voice"};
179static const char *wm8753_mic_sel[] = {"Mic 1", "Mic 2", "Mic 3"};
180static const char *wm8753_dai_mode[] = {"DAI 0", "DAI 1", "DAI 2", "DAI 3"};
181static const char *wm8753_dat_sel[] = {"Stereo", "Left ADC", "Right ADC",
182 "Channel Swap"};
ae092c9e 183static const char *wm8753_rout2_phase[] = {"Non Inverted", "Inverted"};
1f53aee0
LG		 184
185static const struct soc_enum wm8753_enum[] = {
186SOC_ENUM_SINGLE(WM8753_BASS, 7, 2, wm8753_base),
187SOC_ENUM_SINGLE(WM8753_BASS, 4, 6, wm8753_base_filter),
188SOC_ENUM_SINGLE(WM8753_TREBLE, 6, 2, wm8753_treble),
189SOC_ENUM_SINGLE(WM8753_ALC1, 7, 4, wm8753_alc_func),
190SOC_ENUM_SINGLE(WM8753_NGATE, 1, 2, wm8753_ng_type),
191SOC_ENUM_SINGLE(WM8753_3D, 7, 2, wm8753_3d_func),
192SOC_ENUM_SINGLE(WM8753_3D, 6, 2, wm8753_3d_uc),
193SOC_ENUM_SINGLE(WM8753_3D, 5, 2, wm8753_3d_lc),
194SOC_ENUM_SINGLE(WM8753_DAC, 1, 4, wm8753_deemp),
195SOC_ENUM_SINGLE(WM8753_DAC, 4, 4, wm8753_mono_mix),
196SOC_ENUM_SINGLE(WM8753_DAC, 6, 2, wm8753_dac_phase),
197SOC_ENUM_SINGLE(WM8753_INCTL1, 3, 4, wm8753_line_mix),
198SOC_ENUM_SINGLE(WM8753_INCTL1, 2, 2, wm8753_mono_mux),
199SOC_ENUM_SINGLE(WM8753_INCTL1, 1, 2, wm8753_right_mux),
200SOC_ENUM_SINGLE(WM8753_INCTL1, 0, 2, wm8753_left_mux),
201SOC_ENUM_SINGLE(WM8753_INCTL2, 6, 4, wm8753_rxmsel),
202SOC_ENUM_SINGLE(WM8753_INCTL2, 4, 4, wm8753_sidetone_mux),
203SOC_ENUM_SINGLE(WM8753_OUTCTL, 7, 4, wm8753_mono2_src),
204SOC_ENUM_SINGLE(WM8753_OUTCTL, 0, 3, wm8753_out3),
205SOC_ENUM_SINGLE(WM8753_ADCTL2, 7, 3, wm8753_out4),
206SOC_ENUM_SINGLE(WM8753_ADCIN, 2, 3, wm8753_radcsel),
207SOC_ENUM_SINGLE(WM8753_ADCIN, 0, 3, wm8753_ladcsel),
208SOC_ENUM_SINGLE(WM8753_ADCIN, 4, 4, wm8753_mono_adc),
209SOC_ENUM_SINGLE(WM8753_ADC, 2, 4, wm8753_adc_hp),
210SOC_ENUM_SINGLE(WM8753_ADC, 4, 2, wm8753_adc_filter),
211SOC_ENUM_SINGLE(WM8753_MICBIAS, 6, 3, wm8753_mic_sel),
212SOC_ENUM_SINGLE(WM8753_IOCTL, 2, 4, wm8753_dai_mode),
213SOC_ENUM_SINGLE(WM8753_ADC, 7, 4, wm8753_dat_sel),
ae092c9e 214SOC_ENUM_SINGLE(WM8753_OUTCTL, 2, 2, wm8753_rout2_phase),
1f53aee0
LG		 215};
216
217
218static int wm8753_get_dai(struct snd_kcontrol *kcontrol,
219 struct snd_ctl_elem_value *ucontrol)
220{
221 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
222 int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL);
223
224 ucontrol->value.integer.value[0] = (mode & 0xc) >> 2;
225 return 0;
226}
227
228static int wm8753_set_dai(struct snd_kcontrol *kcontrol,
229 struct snd_ctl_elem_value *ucontrol)
230{
231 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
232 int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL);
f0fba2ad 233 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0 234
60fc684a 235 if (((mode & 0xc) >> 2) == ucontrol->value.integer.value[0])
1f53aee0
LG		 236 return 0;
237
238 mode &= 0xfff3;
239 mode |= (ucontrol->value.integer.value[0] << 2);
240
f0fba2ad 241 wm8753->dai_func = ucontrol->value.integer.value[0];
1f53aee0
LG		 242 return 1;
243}
244
2cc8c609
MM		 245static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 300, 0);
246static const DECLARE_TLV_DB_SCALE(mic_preamp_tlv, 1200, 600, 0);
247static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
248static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
249static const unsigned int out_tlv[] = {
250 TLV_DB_RANGE_HEAD(2),
251 /* 0000000 - 0101111 = "Analogue mute" */
252 0, 48, TLV_DB_SCALE_ITEM(-25500, 0, 0),
253 48, 127, TLV_DB_SCALE_ITEM(-7300, 100, 0),
254};
255static const DECLARE_TLV_DB_SCALE(mix_tlv, -1500, 300, 0);
256static const DECLARE_TLV_DB_SCALE(voice_mix_tlv, -1200, 300, 0);
257static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
2d6a4ac9 258
1f53aee0 259static const struct snd_kcontrol_new wm8753_snd_controls[] = {
2cc8c609
MM		 260SOC_DOUBLE_R_TLV("PCM Volume", WM8753_LDAC, WM8753_RDAC, 0, 255, 0, dac_tlv),
261
262SOC_DOUBLE_R_TLV("ADC Capture Volume", WM8753_LADC, WM8753_RADC, 0, 255, 0,
263 adc_tlv),
264
265SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8753_LOUT1V, WM8753_ROUT1V,
266 0, 127, 0, out_tlv),
267SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8753_LOUT2V, WM8753_ROUT2V, 0,
268 127, 0, out_tlv),
269
270SOC_SINGLE_TLV("Mono Playback Volume", WM8753_MOUTV, 0, 127, 0, out_tlv),
271
272SOC_DOUBLE_R_TLV("Bypass Playback Volume", WM8753_LOUTM1, WM8753_ROUTM1, 4, 7,
273 1, mix_tlv),
274SOC_DOUBLE_R_TLV("Sidetone Playback Volume", WM8753_LOUTM2, WM8753_ROUTM2, 4,
275 7, 1, mix_tlv),
276SOC_DOUBLE_R_TLV("Voice Playback Volume", WM8753_LOUTM2, WM8753_ROUTM2, 0, 7,
277 1, voice_mix_tlv),
278
279SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8753_LOUT1V, WM8753_ROUT1V, 7,
280 1, 0),
281SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8753_LOUT2V, WM8753_ROUT2V, 7,
282 1, 0),
283
284SOC_SINGLE_TLV("Mono Bypass Playback Volume", WM8753_MOUTM1, 4, 7, 1, mix_tlv),
285SOC_SINGLE_TLV("Mono Sidetone Playback Volume", WM8753_MOUTM2, 4, 7, 1,
286 mix_tlv),
287SOC_SINGLE_TLV("Mono Voice Playback Volume", WM8753_MOUTM2, 0, 7, 1,
288 voice_mix_tlv),
1f53aee0
LG		 289SOC_SINGLE("Mono Playback ZC Switch", WM8753_MOUTV, 7, 1, 0),
290
291SOC_ENUM("Bass Boost", wm8753_enum[0]),
292SOC_ENUM("Bass Filter", wm8753_enum[1]),
293SOC_SINGLE("Bass Volume", WM8753_BASS, 0, 15, 1),
294
295SOC_SINGLE("Treble Volume", WM8753_TREBLE, 0, 15, 1),
296SOC_ENUM("Treble Cut-off", wm8753_enum[2]),
297
2cc8c609
MM		 298SOC_DOUBLE_TLV("Sidetone Capture Volume", WM8753_RECMIX1, 0, 4, 7, 1,
299 rec_mix_tlv),
300SOC_SINGLE_TLV("Voice Sidetone Capture Volume", WM8753_RECMIX2, 0, 7, 1,
301 rec_mix_tlv),
1f53aee0 302
2cc8c609
MM		 303SOC_DOUBLE_R_TLV("Capture Volume", WM8753_LINVOL, WM8753_RINVOL, 0, 63, 0,
304 pga_tlv),
1f53aee0
LG		 305SOC_DOUBLE_R("Capture ZC Switch", WM8753_LINVOL, WM8753_RINVOL, 6, 1, 0),
306SOC_DOUBLE_R("Capture Switch", WM8753_LINVOL, WM8753_RINVOL, 7, 1, 1),
307
308SOC_ENUM("Capture Filter Select", wm8753_enum[23]),
309SOC_ENUM("Capture Filter Cut-off", wm8753_enum[24]),
310SOC_SINGLE("Capture Filter Switch", WM8753_ADC, 0, 1, 1),
311
312SOC_SINGLE("ALC Capture Target Volume", WM8753_ALC1, 0, 7, 0),
313SOC_SINGLE("ALC Capture Max Volume", WM8753_ALC1, 4, 7, 0),
314SOC_ENUM("ALC Capture Function", wm8753_enum[3]),
315SOC_SINGLE("ALC Capture ZC Switch", WM8753_ALC2, 8, 1, 0),
316SOC_SINGLE("ALC Capture Hold Time", WM8753_ALC2, 0, 15, 1),
317SOC_SINGLE("ALC Capture Decay Time", WM8753_ALC3, 4, 15, 1),
318SOC_SINGLE("ALC Capture Attack Time", WM8753_ALC3, 0, 15, 0),
319SOC_SINGLE("ALC Capture NG Threshold", WM8753_NGATE, 3, 31, 0),
320SOC_ENUM("ALC Capture NG Type", wm8753_enum[4]),
321SOC_SINGLE("ALC Capture NG Switch", WM8753_NGATE, 0, 1, 0),
322
323SOC_ENUM("3D Function", wm8753_enum[5]),
324SOC_ENUM("3D Upper Cut-off", wm8753_enum[6]),
325SOC_ENUM("3D Lower Cut-off", wm8753_enum[7]),
326SOC_SINGLE("3D Volume", WM8753_3D, 1, 15, 0),
327SOC_SINGLE("3D Switch", WM8753_3D, 0, 1, 0),
328
329SOC_SINGLE("Capture 6dB Attenuate", WM8753_ADCTL1, 2, 1, 0),
330SOC_SINGLE("Playback 6dB Attenuate", WM8753_ADCTL1, 1, 1, 0),
331
332SOC_ENUM("De-emphasis", wm8753_enum[8]),
333SOC_ENUM("Playback Mono Mix", wm8753_enum[9]),
334SOC_ENUM("Playback Phase", wm8753_enum[10]),
335
2cc8c609
MM		 336SOC_SINGLE_TLV("Mic2 Capture Volume", WM8753_INCTL1, 7, 3, 0, mic_preamp_tlv),
337SOC_SINGLE_TLV("Mic1 Capture Volume", WM8753_INCTL1, 5, 3, 0, mic_preamp_tlv),
1f53aee0
LG		 338
339SOC_ENUM_EXT("DAI Mode", wm8753_enum[26], wm8753_get_dai, wm8753_set_dai),
340
341SOC_ENUM("ADC Data Select", wm8753_enum[27]),
ae092c9e 342SOC_ENUM("ROUT2 Phase", wm8753_enum[28]),
1f53aee0
LG		 343};
344
1f53aee0
LG		 345/*
346 * _DAPM_ Controls
347 */
348
349/* Left Mixer */
350static const struct snd_kcontrol_new wm8753_left_mixer_controls[] = {
351SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_LOUTM2, 8, 1, 0),
352SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_LOUTM2, 7, 1, 0),
353SOC_DAPM_SINGLE("Left Playback Switch", WM8753_LOUTM1, 8, 1, 0),
354SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_LOUTM1, 7, 1, 0),
355};
356
357/* Right mixer */
358static const struct snd_kcontrol_new wm8753_right_mixer_controls[] = {
359SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_ROUTM2, 8, 1, 0),
360SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_ROUTM2, 7, 1, 0),
361SOC_DAPM_SINGLE("Right Playback Switch", WM8753_ROUTM1, 8, 1, 0),
362SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_ROUTM1, 7, 1, 0),
363};
364
365/* Mono mixer */
366static const struct snd_kcontrol_new wm8753_mono_mixer_controls[] = {
367SOC_DAPM_SINGLE("Left Playback Switch", WM8753_MOUTM1, 8, 1, 0),
368SOC_DAPM_SINGLE("Right Playback Switch", WM8753_MOUTM2, 8, 1, 0),
369SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_MOUTM2, 3, 1, 0),
370SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_MOUTM2, 7, 1, 0),
371SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_MOUTM1, 7, 1, 0),
372};
373
374/* Mono 2 Mux */
375static const struct snd_kcontrol_new wm8753_mono2_controls =
376SOC_DAPM_ENUM("Route", wm8753_enum[17]);
377
378/* Out 3 Mux */
379static const struct snd_kcontrol_new wm8753_out3_controls =
380SOC_DAPM_ENUM("Route", wm8753_enum[18]);
381
382/* Out 4 Mux */
383static const struct snd_kcontrol_new wm8753_out4_controls =
384SOC_DAPM_ENUM("Route", wm8753_enum[19]);
385
386/* ADC Mono Mix */
387static const struct snd_kcontrol_new wm8753_adc_mono_controls =
388SOC_DAPM_ENUM("Route", wm8753_enum[22]);
389
390/* Record mixer */
391static const struct snd_kcontrol_new wm8753_record_mixer_controls[] = {
392SOC_DAPM_SINGLE("Voice Capture Switch", WM8753_RECMIX2, 3, 1, 0),
393SOC_DAPM_SINGLE("Left Capture Switch", WM8753_RECMIX1, 3, 1, 0),
394SOC_DAPM_SINGLE("Right Capture Switch", WM8753_RECMIX1, 7, 1, 0),
395};
396
397/* Left ADC mux */
398static const struct snd_kcontrol_new wm8753_adc_left_controls =
399SOC_DAPM_ENUM("Route", wm8753_enum[21]);
400
401/* Right ADC mux */
402static const struct snd_kcontrol_new wm8753_adc_right_controls =
403SOC_DAPM_ENUM("Route", wm8753_enum[20]);
404
405/* MIC mux */
406static const struct snd_kcontrol_new wm8753_mic_mux_controls =
407SOC_DAPM_ENUM("Route", wm8753_enum[16]);
408
409/* ALC mixer */
410static const struct snd_kcontrol_new wm8753_alc_mixer_controls[] = {
411SOC_DAPM_SINGLE("Line Capture Switch", WM8753_INCTL2, 3, 1, 0),
412SOC_DAPM_SINGLE("Mic2 Capture Switch", WM8753_INCTL2, 2, 1, 0),
413SOC_DAPM_SINGLE("Mic1 Capture Switch", WM8753_INCTL2, 1, 1, 0),
414SOC_DAPM_SINGLE("Rx Capture Switch", WM8753_INCTL2, 0, 1, 0),
415};
416
417/* Left Line mux */
418static const struct snd_kcontrol_new wm8753_line_left_controls =
419SOC_DAPM_ENUM("Route", wm8753_enum[14]);
420
421/* Right Line mux */
422static const struct snd_kcontrol_new wm8753_line_right_controls =
423SOC_DAPM_ENUM("Route", wm8753_enum[13]);
424
425/* Mono Line mux */
426static const struct snd_kcontrol_new wm8753_line_mono_controls =
427SOC_DAPM_ENUM("Route", wm8753_enum[12]);
428
429/* Line mux and mixer */
430static const struct snd_kcontrol_new wm8753_line_mux_mix_controls =
431SOC_DAPM_ENUM("Route", wm8753_enum[11]);
432
433/* Rx mux and mixer */
434static const struct snd_kcontrol_new wm8753_rx_mux_mix_controls =
435SOC_DAPM_ENUM("Route", wm8753_enum[15]);
436
437/* Mic Selector Mux */
438static const struct snd_kcontrol_new wm8753_mic_sel_mux_controls =
439SOC_DAPM_ENUM("Route", wm8753_enum[25]);
440
441static const struct snd_soc_dapm_widget wm8753_dapm_widgets[] = {
442SND_SOC_DAPM_MICBIAS("Mic Bias", WM8753_PWR1, 5, 0),
443SND_SOC_DAPM_MIXER("Left Mixer", WM8753_PWR4, 0, 0,
444 &wm8753_left_mixer_controls[0], ARRAY_SIZE(wm8753_left_mixer_controls)),
445SND_SOC_DAPM_PGA("Left Out 1", WM8753_PWR3, 8, 0, NULL, 0),
446SND_SOC_DAPM_PGA("Left Out 2", WM8753_PWR3, 6, 0, NULL, 0),
447SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", WM8753_PWR1, 3, 0),
448SND_SOC_DAPM_OUTPUT("LOUT1"),
449SND_SOC_DAPM_OUTPUT("LOUT2"),
450SND_SOC_DAPM_MIXER("Right Mixer", WM8753_PWR4, 1, 0,
451 &wm8753_right_mixer_controls[0], ARRAY_SIZE(wm8753_right_mixer_controls)),
452SND_SOC_DAPM_PGA("Right Out 1", WM8753_PWR3, 7, 0, NULL, 0),
453SND_SOC_DAPM_PGA("Right Out 2", WM8753_PWR3, 5, 0, NULL, 0),
454SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", WM8753_PWR1, 2, 0),
455SND_SOC_DAPM_OUTPUT("ROUT1"),
456SND_SOC_DAPM_OUTPUT("ROUT2"),
457SND_SOC_DAPM_MIXER("Mono Mixer", WM8753_PWR4, 2, 0,
458 &wm8753_mono_mixer_controls[0], ARRAY_SIZE(wm8753_mono_mixer_controls)),
459SND_SOC_DAPM_PGA("Mono Out 1", WM8753_PWR3, 2, 0, NULL, 0),
460SND_SOC_DAPM_PGA("Mono Out 2", WM8753_PWR3, 1, 0, NULL, 0),
461SND_SOC_DAPM_DAC("Voice DAC", "Voice Playback", WM8753_PWR1, 4, 0),
462SND_SOC_DAPM_OUTPUT("MONO1"),
463SND_SOC_DAPM_MUX("Mono 2 Mux", SND_SOC_NOPM, 0, 0, &wm8753_mono2_controls),
464SND_SOC_DAPM_OUTPUT("MONO2"),
465SND_SOC_DAPM_MIXER("Out3 Left + Right", -1, 0, 0, NULL, 0),
466SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8753_out3_controls),
467SND_SOC_DAPM_PGA("Out 3", WM8753_PWR3, 4, 0, NULL, 0),
468SND_SOC_DAPM_OUTPUT("OUT3"),
469SND_SOC_DAPM_MUX("Out4 Mux", SND_SOC_NOPM, 0, 0, &wm8753_out4_controls),
470SND_SOC_DAPM_PGA("Out 4", WM8753_PWR3, 3, 0, NULL, 0),
471SND_SOC_DAPM_OUTPUT("OUT4"),
472SND_SOC_DAPM_MIXER("Playback Mixer", WM8753_PWR4, 3, 0,
473 &wm8753_record_mixer_controls[0],
474 ARRAY_SIZE(wm8753_record_mixer_controls)),
475SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8753_PWR2, 3, 0),
476SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8753_PWR2, 2, 0),
477SND_SOC_DAPM_MUX("Capture Left Mixer", SND_SOC_NOPM, 0, 0,
478 &wm8753_adc_mono_controls),
479SND_SOC_DAPM_MUX("Capture Right Mixer", SND_SOC_NOPM, 0, 0,
480 &wm8753_adc_mono_controls),
481SND_SOC_DAPM_MUX("Capture Left Mux", SND_SOC_NOPM, 0, 0,
482 &wm8753_adc_left_controls),
483SND_SOC_DAPM_MUX("Capture Right Mux", SND_SOC_NOPM, 0, 0,
484 &wm8753_adc_right_controls),
485SND_SOC_DAPM_MUX("Mic Sidetone Mux", SND_SOC_NOPM, 0, 0,
486 &wm8753_mic_mux_controls),
487SND_SOC_DAPM_PGA("Left Capture Volume", WM8753_PWR2, 5, 0, NULL, 0),
488SND_SOC_DAPM_PGA("Right Capture Volume", WM8753_PWR2, 4, 0, NULL, 0),
489SND_SOC_DAPM_MIXER("ALC Mixer", WM8753_PWR2, 6, 0,
490 &wm8753_alc_mixer_controls[0], ARRAY_SIZE(wm8753_alc_mixer_controls)),
491SND_SOC_DAPM_MUX("Line Left Mux", SND_SOC_NOPM, 0, 0,
492 &wm8753_line_left_controls),
493SND_SOC_DAPM_MUX("Line Right Mux", SND_SOC_NOPM, 0, 0,
494 &wm8753_line_right_controls),
495SND_SOC_DAPM_MUX("Line Mono Mux", SND_SOC_NOPM, 0, 0,
496 &wm8753_line_mono_controls),
497SND_SOC_DAPM_MUX("Line Mixer", WM8753_PWR2, 0, 0,
498 &wm8753_line_mux_mix_controls),
499SND_SOC_DAPM_MUX("Rx Mixer", WM8753_PWR2, 1, 0,
500 &wm8753_rx_mux_mix_controls),
501SND_SOC_DAPM_PGA("Mic 1 Volume", WM8753_PWR2, 8, 0, NULL, 0),
502SND_SOC_DAPM_PGA("Mic 2 Volume", WM8753_PWR2, 7, 0, NULL, 0),
503SND_SOC_DAPM_MUX("Mic Selection Mux", SND_SOC_NOPM, 0, 0,
504 &wm8753_mic_sel_mux_controls),
505SND_SOC_DAPM_INPUT("LINE1"),
506SND_SOC_DAPM_INPUT("LINE2"),
507SND_SOC_DAPM_INPUT("RXP"),
508SND_SOC_DAPM_INPUT("RXN"),
509SND_SOC_DAPM_INPUT("ACIN"),
510SND_SOC_DAPM_OUTPUT("ACOP"),
511SND_SOC_DAPM_INPUT("MIC1N"),
512SND_SOC_DAPM_INPUT("MIC1"),
513SND_SOC_DAPM_INPUT("MIC2N"),
514SND_SOC_DAPM_INPUT("MIC2"),
515SND_SOC_DAPM_VMID("VREF"),
516};
517
a65f0568 518static const struct snd_soc_dapm_route audio_map[] = {
1f53aee0
LG		 519 /* left mixer */
520 {"Left Mixer", "Left Playback Switch", "Left DAC"},
521 {"Left Mixer", "Voice Playback Switch", "Voice DAC"},
522 {"Left Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
523 {"Left Mixer", "Bypass Playback Switch", "Line Left Mux"},
524
525 /* right mixer */
526 {"Right Mixer", "Right Playback Switch", "Right DAC"},
527 {"Right Mixer", "Voice Playback Switch", "Voice DAC"},
528 {"Right Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
529 {"Right Mixer", "Bypass Playback Switch", "Line Right Mux"},
530
531 /* mono mixer */
532 {"Mono Mixer", "Voice Playback Switch", "Voice DAC"},
533 {"Mono Mixer", "Left Playback Switch", "Left DAC"},
534 {"Mono Mixer", "Right Playback Switch", "Right DAC"},
535 {"Mono Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
536 {"Mono Mixer", "Bypass Playback Switch", "Line Mono Mux"},
537
538 /* left out */
539 {"Left Out 1", NULL, "Left Mixer"},
540 {"Left Out 2", NULL, "Left Mixer"},
541 {"LOUT1", NULL, "Left Out 1"},
542 {"LOUT2", NULL, "Left Out 2"},
543
544 /* right out */
545 {"Right Out 1", NULL, "Right Mixer"},
546 {"Right Out 2", NULL, "Right Mixer"},
547 {"ROUT1", NULL, "Right Out 1"},
548 {"ROUT2", NULL, "Right Out 2"},
549
550 /* mono 1 out */
551 {"Mono Out 1", NULL, "Mono Mixer"},
552 {"MONO1", NULL, "Mono Out 1"},
553
554 /* mono 2 out */
555 {"Mono 2 Mux", "Left + Right", "Out3 Left + Right"},
556 {"Mono 2 Mux", "Inverted Mono 1", "MONO1"},
557 {"Mono 2 Mux", "Left", "Left Mixer"},
558 {"Mono 2 Mux", "Right", "Right Mixer"},
559 {"Mono Out 2", NULL, "Mono 2 Mux"},
560 {"MONO2", NULL, "Mono Out 2"},
561
562 /* out 3 */
563 {"Out3 Left + Right", NULL, "Left Mixer"},
564 {"Out3 Left + Right", NULL, "Right Mixer"},
565 {"Out3 Mux", "VREF", "VREF"},
566 {"Out3 Mux", "Left + Right", "Out3 Left + Right"},
567 {"Out3 Mux", "ROUT2", "ROUT2"},
568 {"Out 3", NULL, "Out3 Mux"},
569 {"OUT3", NULL, "Out 3"},
570
571 /* out 4 */
572 {"Out4 Mux", "VREF", "VREF"},
4037314a 573 {"Out4 Mux", "Capture ST", "Playback Mixer"},
1f53aee0
LG		 574 {"Out4 Mux", "LOUT2", "LOUT2"},
575 {"Out 4", NULL, "Out4 Mux"},
576 {"OUT4", NULL, "Out 4"},
577
578 /* record mixer */
579 {"Playback Mixer", "Left Capture Switch", "Left Mixer"},
580 {"Playback Mixer", "Voice Capture Switch", "Mono Mixer"},
581 {"Playback Mixer", "Right Capture Switch", "Right Mixer"},
582
583 /* Mic/SideTone Mux */
584 {"Mic Sidetone Mux", "Left PGA", "Left Capture Volume"},
585 {"Mic Sidetone Mux", "Right PGA", "Right Capture Volume"},
586 {"Mic Sidetone Mux", "Mic 1", "Mic 1 Volume"},
587 {"Mic Sidetone Mux", "Mic 2", "Mic 2 Volume"},
588
589 /* Capture Left Mux */
590 {"Capture Left Mux", "PGA", "Left Capture Volume"},
591 {"Capture Left Mux", "Line or RXP-RXN", "Line Left Mux"},
592 {"Capture Left Mux", "Line", "LINE1"},
593
594 /* Capture Right Mux */
595 {"Capture Right Mux", "PGA", "Right Capture Volume"},
596 {"Capture Right Mux", "Line or RXP-RXN", "Line Right Mux"},
4037314a 597 {"Capture Right Mux", "Sidetone", "Playback Mixer"},
1f53aee0
LG		 598
599 /* Mono Capture mixer-mux */
600 {"Capture Right Mixer", "Stereo", "Capture Right Mux"},
877ae707 601 {"Capture Left Mixer", "Stereo", "Capture Left Mux"},
1f53aee0
LG		 602 {"Capture Left Mixer", "Analogue Mix Left", "Capture Left Mux"},
603 {"Capture Left Mixer", "Analogue Mix Left", "Capture Right Mux"},
604 {"Capture Right Mixer", "Analogue Mix Right", "Capture Left Mux"},
605 {"Capture Right Mixer", "Analogue Mix Right", "Capture Right Mux"},
606 {"Capture Left Mixer", "Digital Mono Mix", "Capture Left Mux"},
607 {"Capture Left Mixer", "Digital Mono Mix", "Capture Right Mux"},
608 {"Capture Right Mixer", "Digital Mono Mix", "Capture Left Mux"},
609 {"Capture Right Mixer", "Digital Mono Mix", "Capture Right Mux"},
610
611 /* ADC */
612 {"Left ADC", NULL, "Capture Left Mixer"},
613 {"Right ADC", NULL, "Capture Right Mixer"},
614
615 /* Left Capture Volume */
616 {"Left Capture Volume", NULL, "ACIN"},
617
618 /* Right Capture Volume */
619 {"Right Capture Volume", NULL, "Mic 2 Volume"},
620
621 /* ALC Mixer */
622 {"ALC Mixer", "Line Capture Switch", "Line Mixer"},
623 {"ALC Mixer", "Mic2 Capture Switch", "Mic 2 Volume"},
624 {"ALC Mixer", "Mic1 Capture Switch", "Mic 1 Volume"},
625 {"ALC Mixer", "Rx Capture Switch", "Rx Mixer"},
626
627 /* Line Left Mux */
628 {"Line Left Mux", "Line 1", "LINE1"},
629 {"Line Left Mux", "Rx Mix", "Rx Mixer"},
630
631 /* Line Right Mux */
632 {"Line Right Mux", "Line 2", "LINE2"},
633 {"Line Right Mux", "Rx Mix", "Rx Mixer"},
634
635 /* Line Mono Mux */
636 {"Line Mono Mux", "Line Mix", "Line Mixer"},
637 {"Line Mono Mux", "Rx Mix", "Rx Mixer"},
638
639 /* Line Mixer/Mux */
640 {"Line Mixer", "Line 1 + 2", "LINE1"},
641 {"Line Mixer", "Line 1 - 2", "LINE1"},
642 {"Line Mixer", "Line 1 + 2", "LINE2"},
643 {"Line Mixer", "Line 1 - 2", "LINE2"},
644 {"Line Mixer", "Line 1", "LINE1"},
645 {"Line Mixer", "Line 2", "LINE2"},
646
647 /* Rx Mixer/Mux */
648 {"Rx Mixer", "RXP - RXN", "RXP"},
649 {"Rx Mixer", "RXP + RXN", "RXP"},
650 {"Rx Mixer", "RXP - RXN", "RXN"},
651 {"Rx Mixer", "RXP + RXN", "RXN"},
652 {"Rx Mixer", "RXP", "RXP"},
653 {"Rx Mixer", "RXN", "RXN"},
654
655 /* Mic 1 Volume */
656 {"Mic 1 Volume", NULL, "MIC1N"},
657 {"Mic 1 Volume", NULL, "Mic Selection Mux"},
658
659 /* Mic 2 Volume */
660 {"Mic 2 Volume", NULL, "MIC2N"},
661 {"Mic 2 Volume", NULL, "MIC2"},
662
663 /* Mic Selector Mux */
664 {"Mic Selection Mux", "Mic 1", "MIC1"},
665 {"Mic Selection Mux", "Mic 2", "MIC2N"},
666 {"Mic Selection Mux", "Mic 3", "MIC2"},
667
668 /* ACOP */
669 {"ACOP", NULL, "ALC Mixer"},
1f53aee0
LG		 670};
671
672static int wm8753_add_widgets(struct snd_soc_codec *codec)
673{
a65f0568
MB		 674 snd_soc_dapm_new_controls(codec, wm8753_dapm_widgets,
675 ARRAY_SIZE(wm8753_dapm_widgets));
1f53aee0 676
a65f0568 677 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
1f53aee0 678
1f53aee0
LG		 679 return 0;
680}
681
682/* PLL divisors */
683struct _pll_div {
684 u32 div2:1;
685 u32 n:4;
686 u32 k:24;
687};
688
689/* The size in bits of the pll divide multiplied by 10
690 * to allow rounding later */
691#define FIXED_PLL_SIZE ((1 << 22) * 10)
692
693static void pll_factors(struct _pll_div *pll_div, unsigned int target,
694 unsigned int source)
695{
696 u64 Kpart;
697 unsigned int K, Ndiv, Nmod;
698
699 Ndiv = target / source;
700 if (Ndiv < 6) {
701 source >>= 1;
702 pll_div->div2 = 1;
703 Ndiv = target / source;
704 } else
705 pll_div->div2 = 0;
706
707 if ((Ndiv < 6) || (Ndiv > 12))
708 printk(KERN_WARNING
449bd54d 709 "wm8753: unsupported N = %u\n", Ndiv);
1f53aee0
LG		 710
711 pll_div->n = Ndiv;
712 Nmod = target % source;
713 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
714
715 do_div(Kpart, source);
716
717 K = Kpart & 0xFFFFFFFF;
718
719 /* Check if we need to round */
720 if ((K % 10) >= 5)
721 K += 5;
722
723 /* Move down to proper range now rounding is done */
724 K /= 10;
725
726 pll_div->k = K;
727}
728
85488037
MB		 729static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
730 int source, unsigned int freq_in, unsigned int freq_out)
1f53aee0
LG		 731{
732 u16 reg, enable;
733 int offset;
734 struct snd_soc_codec *codec = codec_dai->codec;
735
736 if (pll_id < WM8753_PLL1 || pll_id > WM8753_PLL2)
737 return -ENODEV;
738
739 if (pll_id == WM8753_PLL1) {
740 offset = 0;
741 enable = 0x10;
742 reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xffef;
743 } else {
744 offset = 4;
745 enable = 0x8;
746 reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfff7;
747 }
748
749 if (!freq_in || !freq_out) {
750 /* disable PLL */
751 wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0026);
752 wm8753_write(codec, WM8753_CLOCK, reg);
753 return 0;
754 } else {
755 u16 value = 0;
756 struct _pll_div pll_div;
757
758 pll_factors(&pll_div, freq_out * 8, freq_in);
759
760 /* set up N and K PLL divisor ratios */
761 /* bits 8:5 = PLL_N, bits 3:0 = PLL_K[21:18] */
762 value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18);
763 wm8753_write(codec, WM8753_PLL1CTL2 + offset, value);
764
765 /* bits 8:0 = PLL_K[17:9] */
766 value = (pll_div.k & 0x03fe00) >> 9;
767 wm8753_write(codec, WM8753_PLL1CTL3 + offset, value);
768
769 /* bits 8:0 = PLL_K[8:0] */
770 value = pll_div.k & 0x0001ff;
771 wm8753_write(codec, WM8753_PLL1CTL4 + offset, value);
772
773 /* set PLL as input and enable */
774 wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0027 |
775 (pll_div.div2 << 3));
776 wm8753_write(codec, WM8753_CLOCK, reg | enable);
777 }
778 return 0;
779}
780
781struct _coeff_div {
782 u32 mclk;
783 u32 rate;
784 u8 sr:5;
785 u8 usb:1;
786};
787
788/* codec hifi mclk (after PLL) clock divider coefficients */
789static const struct _coeff_div coeff_div[] = {
790 /* 8k */
791 {12288000, 8000, 0x6, 0x0},
792 {11289600, 8000, 0x16, 0x0},
793 {18432000, 8000, 0x7, 0x0},
794 {16934400, 8000, 0x17, 0x0},
795 {12000000, 8000, 0x6, 0x1},
796
797 /* 11.025k */
798 {11289600, 11025, 0x18, 0x0},
799 {16934400, 11025, 0x19, 0x0},
800 {12000000, 11025, 0x19, 0x1},
801
802 /* 16k */
803 {12288000, 16000, 0xa, 0x0},
804 {18432000, 16000, 0xb, 0x0},
805 {12000000, 16000, 0xa, 0x1},
806
807 /* 22.05k */
808 {11289600, 22050, 0x1a, 0x0},
809 {16934400, 22050, 0x1b, 0x0},
810 {12000000, 22050, 0x1b, 0x1},
811
812 /* 32k */
813 {12288000, 32000, 0xc, 0x0},
814 {18432000, 32000, 0xd, 0x0},
815 {12000000, 32000, 0xa, 0x1},
816
817 /* 44.1k */
818 {11289600, 44100, 0x10, 0x0},
819 {16934400, 44100, 0x11, 0x0},
820 {12000000, 44100, 0x11, 0x1},
821
822 /* 48k */
823 {12288000, 48000, 0x0, 0x0},
824 {18432000, 48000, 0x1, 0x0},
825 {12000000, 48000, 0x0, 0x1},
826
827 /* 88.2k */
828 {11289600, 88200, 0x1e, 0x0},
829 {16934400, 88200, 0x1f, 0x0},
830 {12000000, 88200, 0x1f, 0x1},
831
832 /* 96k */
833 {12288000, 96000, 0xe, 0x0},
834 {18432000, 96000, 0xf, 0x0},
835 {12000000, 96000, 0xe, 0x1},
836};
837
838static int get_coeff(int mclk, int rate)
839{
840 int i;
841
842 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
843 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
844 return i;
845 }
846 return -EINVAL;
847}
848
849/*
850 * Clock after PLL and dividers
851 */
e550e17f 852static int wm8753_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 853 int clk_id, unsigned int freq, int dir)
854{
855 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 856 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 857
858 switch (freq) {
859 case 11289600:
860 case 12000000:
861 case 12288000:
862 case 16934400:
863 case 18432000:
864 if (clk_id == WM8753_MCLK) {
865 wm8753->sysclk = freq;
866 return 0;
867 } else if (clk_id == WM8753_PCMCLK) {
868 wm8753->pcmclk = freq;
869 return 0;
870 }
871 break;
872 }
873 return -EINVAL;
874}
875
876/*
877 * Set's ADC and Voice DAC format.
878 */
e550e17f 879static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 880 unsigned int fmt)
881{
882 struct snd_soc_codec *codec = codec_dai->codec;
883 u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01ec;
884
885 /* interface format */
886 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
887 case SND_SOC_DAIFMT_I2S:
888 voice |= 0x0002;
889 break;
890 case SND_SOC_DAIFMT_RIGHT_J:
891 break;
892 case SND_SOC_DAIFMT_LEFT_J:
893 voice |= 0x0001;
894 break;
895 case SND_SOC_DAIFMT_DSP_A:
896 voice |= 0x0003;
897 break;
898 case SND_SOC_DAIFMT_DSP_B:
899 voice |= 0x0013;
900 break;
901 default:
902 return -EINVAL;
903 }
904
905 wm8753_write(codec, WM8753_PCM, voice);
906 return 0;
907}
908
f0fba2ad
LG		 909static int wm8753_pcm_startup(struct snd_pcm_substream *substream,
910 struct snd_soc_dai *dai)
911{
912 wm8753_set_dai_mode(dai->codec, dai, 0);
913 return 0;
914}
915
1f53aee0
LG		 916/*
917 * Set PCM DAI bit size and sample rate.
918 */
919static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 920 struct snd_pcm_hw_params *params,
921 struct snd_soc_dai *dai)
1f53aee0
LG		 922{
923 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 924 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 925 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 926 u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01f3;
927 u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x017f;
928
929 /* bit size */
930 switch (params_format(params)) {
931 case SNDRV_PCM_FORMAT_S16_LE:
932 break;
933 case SNDRV_PCM_FORMAT_S20_3LE:
934 voice |= 0x0004;
935 break;
936 case SNDRV_PCM_FORMAT_S24_LE:
937 voice |= 0x0008;
938 break;
939 case SNDRV_PCM_FORMAT_S32_LE:
940 voice |= 0x000c;
941 break;
942 }
943
944 /* sample rate */
945 if (params_rate(params) * 384 == wm8753->pcmclk)
946 srate |= 0x80;
947 wm8753_write(codec, WM8753_SRATE1, srate);
948
949 wm8753_write(codec, WM8753_PCM, voice);
950 return 0;
951}
952
953/*
954 * Set's PCM dai fmt and BCLK.
955 */
e550e17f 956static int wm8753_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 957 unsigned int fmt)
958{
959 struct snd_soc_codec *codec = codec_dai->codec;
960 u16 voice, ioctl;
961
962 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x011f;
963 ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x015d;
964
965 /* set master/slave audio interface */
966 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
967 case SND_SOC_DAIFMT_CBS_CFS:
968 break;
969 case SND_SOC_DAIFMT_CBM_CFM:
970 ioctl |= 0x2;
971 case SND_SOC_DAIFMT_CBM_CFS:
972 voice |= 0x0040;
973 break;
974 default:
975 return -EINVAL;
976 }
977
978 /* clock inversion */
979 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
980 case SND_SOC_DAIFMT_DSP_A:
981 case SND_SOC_DAIFMT_DSP_B:
982 /* frame inversion not valid for DSP modes */
983 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
984 case SND_SOC_DAIFMT_NB_NF:
985 break;
986 case SND_SOC_DAIFMT_IB_NF:
987 voice |= 0x0080;
988 break;
989 default:
990 return -EINVAL;
991 }
992 break;
993 case SND_SOC_DAIFMT_I2S:
994 case SND_SOC_DAIFMT_RIGHT_J:
995 case SND_SOC_DAIFMT_LEFT_J:
996 voice &= ~0x0010;
997 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
998 case SND_SOC_DAIFMT_NB_NF:
999 break;
1000 case SND_SOC_DAIFMT_IB_IF:
1001 voice |= 0x0090;
1002 break;
1003 case SND_SOC_DAIFMT_IB_NF:
1004 voice |= 0x0080;
1005 break;
1006 case SND_SOC_DAIFMT_NB_IF:
1007 voice |= 0x0010;
1008 break;
1009 default:
1010 return -EINVAL;
1011 }
1012 break;
1013 default:
1014 return -EINVAL;
1015 }
1016
1017 wm8753_write(codec, WM8753_PCM, voice);
1018 wm8753_write(codec, WM8753_IOCTL, ioctl);
1019 return 0;
1020}
1021
e550e17f 1022static int wm8753_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1023 int div_id, int div)
1024{
1025 struct snd_soc_codec *codec = codec_dai->codec;
1026 u16 reg;
1027
1028 switch (div_id) {
1029 case WM8753_PCMDIV:
1030 reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0x003f;
1031 wm8753_write(codec, WM8753_CLOCK, reg | div);
1032 break;
1033 case WM8753_BCLKDIV:
1034 reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x01c7;
1035 wm8753_write(codec, WM8753_SRATE2, reg | div);
1036 break;
1037 case WM8753_VXCLKDIV:
1038 reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x003f;
1039 wm8753_write(codec, WM8753_SRATE2, reg | div);
1040 break;
1041 default:
1042 return -EINVAL;
1043 }
1044 return 0;
1045}
1046
1047/*
1048 * Set's HiFi DAC format.
1049 */
e550e17f 1050static int wm8753_hdac_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1051 unsigned int fmt)
1052{
1053 struct snd_soc_codec *codec = codec_dai->codec;
1054 u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01e0;
1055
1056 /* interface format */
1057 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1058 case SND_SOC_DAIFMT_I2S:
1059 hifi |= 0x0002;
1060 break;
1061 case SND_SOC_DAIFMT_RIGHT_J:
1062 break;
1063 case SND_SOC_DAIFMT_LEFT_J:
1064 hifi |= 0x0001;
1065 break;
1066 case SND_SOC_DAIFMT_DSP_A:
1067 hifi |= 0x0003;
1068 break;
1069 case SND_SOC_DAIFMT_DSP_B:
1070 hifi |= 0x0013;
1071 break;
1072 default:
1073 return -EINVAL;
1074 }
1075
1076 wm8753_write(codec, WM8753_HIFI, hifi);
1077 return 0;
1078}
1079
1080/*
1081 * Set's I2S DAI format.
1082 */
e550e17f 1083static int wm8753_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1084 unsigned int fmt)
1085{
1086 struct snd_soc_codec *codec = codec_dai->codec;
1087 u16 ioctl, hifi;
1088
1089 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x011f;
1090 ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x00ae;
1091
1092 /* set master/slave audio interface */
1093 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1094 case SND_SOC_DAIFMT_CBS_CFS:
1095 break;
1096 case SND_SOC_DAIFMT_CBM_CFM:
1097 ioctl |= 0x1;
1098 case SND_SOC_DAIFMT_CBM_CFS:
1099 hifi |= 0x0040;
1100 break;
1101 default:
1102 return -EINVAL;
1103 }
1104
1105 /* clock inversion */
1106 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1107 case SND_SOC_DAIFMT_DSP_A:
1108 case SND_SOC_DAIFMT_DSP_B:
1109 /* frame inversion not valid for DSP modes */
1110 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1111 case SND_SOC_DAIFMT_NB_NF:
1112 break;
1113 case SND_SOC_DAIFMT_IB_NF:
1114 hifi |= 0x0080;
1115 break;
1116 default:
1117 return -EINVAL;
1118 }
1119 break;
1120 case SND_SOC_DAIFMT_I2S:
1121 case SND_SOC_DAIFMT_RIGHT_J:
1122 case SND_SOC_DAIFMT_LEFT_J:
1123 hifi &= ~0x0010;
1124 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1125 case SND_SOC_DAIFMT_NB_NF:
1126 break;
1127 case SND_SOC_DAIFMT_IB_IF:
1128 hifi |= 0x0090;
1129 break;
1130 case SND_SOC_DAIFMT_IB_NF:
1131 hifi |= 0x0080;
1132 break;
1133 case SND_SOC_DAIFMT_NB_IF:
1134 hifi |= 0x0010;
1135 break;
1136 default:
1137 return -EINVAL;
1138 }
1139 break;
1140 default:
1141 return -EINVAL;
1142 }
1143
1144 wm8753_write(codec, WM8753_HIFI, hifi);
1145 wm8753_write(codec, WM8753_IOCTL, ioctl);
1146 return 0;
1147}
1148
f0fba2ad
LG		 1149static int wm8753_i2s_startup(struct snd_pcm_substream *substream,
1150 struct snd_soc_dai *dai)
1151{
1152 wm8753_set_dai_mode(dai->codec, dai, 1);
1153 return 0;
1154}
1155
1f53aee0
LG		 1156/*
1157 * Set PCM DAI bit size and sample rate.
1158 */
1159static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1160 struct snd_pcm_hw_params *params,
1161 struct snd_soc_dai *dai)
1f53aee0
LG		 1162{
1163 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1164 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1165 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 1166 u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x01c0;
1167 u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01f3;
1168 int coeff;
1169
1170 /* is digital filter coefficient valid ? */
1171 coeff = get_coeff(wm8753->sysclk, params_rate(params));
1172 if (coeff < 0) {
1173 printk(KERN_ERR "wm8753 invalid MCLK or rate\n");
1174 return coeff;
1175 }
1176 wm8753_write(codec, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) |
1177 coeff_div[coeff].usb);
1178
1179 /* bit size */
1180 switch (params_format(params)) {
1181 case SNDRV_PCM_FORMAT_S16_LE:
1182 break;
1183 case SNDRV_PCM_FORMAT_S20_3LE:
1184 hifi |= 0x0004;
1185 break;
1186 case SNDRV_PCM_FORMAT_S24_LE:
1187 hifi |= 0x0008;
1188 break;
1189 case SNDRV_PCM_FORMAT_S32_LE:
1190 hifi |= 0x000c;
1191 break;
1192 }
1193
1194 wm8753_write(codec, WM8753_HIFI, hifi);
1195 return 0;
1196}
1197
e550e17f 1198static int wm8753_mode1v_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1199 unsigned int fmt)
1200{
1201 struct snd_soc_codec *codec = codec_dai->codec;
1202 u16 clock;
1203
1204 /* set clk source as pcmclk */
1205 clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb;
1206 wm8753_write(codec, WM8753_CLOCK, clock);
1207
1208 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
1209 return -EINVAL;
1210 return wm8753_pcm_set_dai_fmt(codec_dai, fmt);
1211}
1212
e550e17f 1213static int wm8753_mode1h_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1214 unsigned int fmt)
1215{
1216 if (wm8753_hdac_set_dai_fmt(codec_dai, fmt) < 0)
1217 return -EINVAL;
1218 return wm8753_i2s_set_dai_fmt(codec_dai, fmt);
1219}
1220
e550e17f 1221static int wm8753_mode2_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1222 unsigned int fmt)
1223{
1224 struct snd_soc_codec *codec = codec_dai->codec;
1225 u16 clock;
1226
1227 /* set clk source as pcmclk */
1228 clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb;
1229 wm8753_write(codec, WM8753_CLOCK, clock);
1230
1231 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
1232 return -EINVAL;
1233 return wm8753_i2s_set_dai_fmt(codec_dai, fmt);
1234}
1235
e550e17f 1236static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1237 unsigned int fmt)
1238{
1239 struct snd_soc_codec *codec = codec_dai->codec;
1240 u16 clock;
1241
1242 /* set clk source as mclk */
1243 clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb;
1244 wm8753_write(codec, WM8753_CLOCK, clock | 0x4);
1245
1246 if (wm8753_hdac_set_dai_fmt(codec_dai, fmt) < 0)
1247 return -EINVAL;
1248 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
1249 return -EINVAL;
1250 return wm8753_i2s_set_dai_fmt(codec_dai, fmt);
1251}
1252
e550e17f 1253static int wm8753_mute(struct snd_soc_dai *dai, int mute)
1f53aee0
LG		 1254{
1255 struct snd_soc_codec *codec = dai->codec;
1256 u16 mute_reg = wm8753_read_reg_cache(codec, WM8753_DAC) & 0xfff7;
f0fba2ad 1257 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 1258
1259 /* the digital mute covers the HiFi and Voice DAC's on the WM8753.
1260 * make sure we check if they are not both active when we mute */
f0fba2ad
LG		 1261 if (mute && wm8753->dai_func == 1) {
1262 if (!codec->active)
1f53aee0
LG		 1263 wm8753_write(codec, WM8753_DAC, mute_reg | 0x8);
1264 } else {
1265 if (mute)
1266 wm8753_write(codec, WM8753_DAC, mute_reg | 0x8);
1267 else
1268 wm8753_write(codec, WM8753_DAC, mute_reg);
1269 }
1270
1271 return 0;
1272}
1273
0be9898a
MB		 1274static int wm8753_set_bias_level(struct snd_soc_codec *codec,
1275 enum snd_soc_bias_level level)
1f53aee0
LG		 1276{
1277 u16 pwr_reg = wm8753_read_reg_cache(codec, WM8753_PWR1) & 0xfe3e;
1278
0be9898a
MB		 1279 switch (level) {
1280 case SND_SOC_BIAS_ON:
1f53aee0
LG		 1281 /* set vmid to 50k and unmute dac */
1282 wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x00c0);
1283 break;
0be9898a 1284 case SND_SOC_BIAS_PREPARE:
1f53aee0
LG		 1285 /* set vmid to 5k for quick power up */
1286 wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x01c1);
1287 break;
0be9898a 1288 case SND_SOC_BIAS_STANDBY:
1f53aee0
LG		 1289 /* mute dac and set vmid to 500k, enable VREF */
1290 wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x0141);
1291 break;
0be9898a 1292 case SND_SOC_BIAS_OFF:
1f53aee0
LG		 1293 wm8753_write(codec, WM8753_PWR1, 0x0001);
1294 break;
1295 }
0be9898a 1296 codec->bias_level = level;
1f53aee0
LG		 1297 return 0;
1298}
1299
1300#define WM8753_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
60fc684a
MB		 1301 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1302 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1303 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
1f53aee0
LG		 1304
1305#define WM8753_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1306 SNDRV_PCM_FMTBIT_S24_LE)
1307
1308/*
1309 * The WM8753 supports upto 4 different and mutually exclusive DAI
1310 * configurations. This gives 2 PCM's available for use, hifi and voice.
1311 * NOTE: The Voice PCM cannot play or capture audio to the CPU as it's DAI
1312 * is connected between the wm8753 and a BT codec or GSM modem.
1313 *
1314 * 1. Voice over PCM DAI - HIFI DAC over HIFI DAI
1315 * 2. Voice over HIFI DAI - HIFI disabled
1316 * 3. Voice disabled - HIFI over HIFI
1317 * 4. Voice disabled - HIFI over HIFI, uses voice DAI LRC for capture
1318 */
6335d055 1319static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode1 = {
f0fba2ad 1320 .startup = wm8753_i2s_startup,
6335d055
EM		 1321 .hw_params = wm8753_i2s_hw_params,
1322 .digital_mute = wm8753_mute,
1323 .set_fmt = wm8753_mode1h_set_dai_fmt,
1324 .set_clkdiv = wm8753_set_dai_clkdiv,
1325 .set_pll = wm8753_set_dai_pll,
1326 .set_sysclk = wm8753_set_dai_sysclk,
1327};
1328
1329static struct snd_soc_dai_ops wm8753_dai_ops_voice_mode1 = {
f0fba2ad 1330 .startup = wm8753_pcm_startup,
6335d055
EM		 1331 .hw_params = wm8753_pcm_hw_params,
1332 .digital_mute = wm8753_mute,
1333 .set_fmt = wm8753_mode1v_set_dai_fmt,
1334 .set_clkdiv = wm8753_set_dai_clkdiv,
1335 .set_pll = wm8753_set_dai_pll,
1336 .set_sysclk = wm8753_set_dai_sysclk,
1337};
1338
1339static struct snd_soc_dai_ops wm8753_dai_ops_voice_mode2 = {
f0fba2ad 1340 .startup = wm8753_pcm_startup,
6335d055
EM		 1341 .hw_params = wm8753_pcm_hw_params,
1342 .digital_mute = wm8753_mute,
1343 .set_fmt = wm8753_mode2_set_dai_fmt,
1344 .set_clkdiv = wm8753_set_dai_clkdiv,
1345 .set_pll = wm8753_set_dai_pll,
1346 .set_sysclk = wm8753_set_dai_sysclk,
1347};
1348
1349static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode3 = {
f0fba2ad 1350 .startup = wm8753_i2s_startup,
6335d055
EM		 1351 .hw_params = wm8753_i2s_hw_params,
1352 .digital_mute = wm8753_mute,
1353 .set_fmt = wm8753_mode3_4_set_dai_fmt,
1354 .set_clkdiv = wm8753_set_dai_clkdiv,
1355 .set_pll = wm8753_set_dai_pll,
1356 .set_sysclk = wm8753_set_dai_sysclk,
1357};
1358
1359static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode4 = {
f0fba2ad 1360 .startup = wm8753_i2s_startup,
6335d055
EM		 1361 .hw_params = wm8753_i2s_hw_params,
1362 .digital_mute = wm8753_mute,
1363 .set_fmt = wm8753_mode3_4_set_dai_fmt,
1364 .set_clkdiv = wm8753_set_dai_clkdiv,
1365 .set_pll = wm8753_set_dai_pll,
1366 .set_sysclk = wm8753_set_dai_sysclk,
1367};
1368
f0fba2ad 1369static struct snd_soc_dai_driver wm8753_all_dai[] = {
1f53aee0 1370/* DAI HiFi mode 1 */
f0fba2ad 1371{ .name = "wm8753-hifi",
1f53aee0
LG		 1372 .playback = {
1373 .stream_name = "HiFi Playback",
1374 .channels_min = 1,
1375 .channels_max = 2,
1376 .rates = WM8753_RATES,
dee89c4d 1377 .formats = WM8753_FORMATS},
1f53aee0
LG		 1378 .capture = { /* dummy for fast DAI switching */
1379 .stream_name = "Capture",
1380 .channels_min = 1,
1381 .channels_max = 2,
1382 .rates = WM8753_RATES,
dee89c4d 1383 .formats = WM8753_FORMATS},
6335d055 1384 .ops = &wm8753_dai_ops_hifi_mode1,
1f53aee0
LG		 1385},
1386/* DAI Voice mode 1 */
f0fba2ad 1387{ .name = "wm8753-voice",
1f53aee0
LG		 1388 .playback = {
1389 .stream_name = "Voice Playback",
1390 .channels_min = 1,
1391 .channels_max = 1,
1392 .rates = WM8753_RATES,
1393 .formats = WM8753_FORMATS,},
1394 .capture = {
1395 .stream_name = "Capture",
1396 .channels_min = 1,
1397 .channels_max = 2,
1398 .rates = WM8753_RATES,
1399 .formats = WM8753_FORMATS,},
6335d055 1400 .ops = &wm8753_dai_ops_voice_mode1,
1f53aee0
LG		 1401},
1402/* DAI HiFi mode 2 - dummy */
f0fba2ad 1403{ .name = "wm8753-hifi",
1f53aee0
LG		 1404},
1405/* DAI Voice mode 2 */
f0fba2ad 1406{ .name = "wm8753-voice",
1f53aee0
LG		 1407 .playback = {
1408 .stream_name = "Voice Playback",
1409 .channels_min = 1,
1410 .channels_max = 1,
1411 .rates = WM8753_RATES,
1412 .formats = WM8753_FORMATS,},
1413 .capture = {
1414 .stream_name = "Capture",
1415 .channels_min = 1,
1416 .channels_max = 2,
1417 .rates = WM8753_RATES,
1418 .formats = WM8753_FORMATS,},
6335d055 1419 .ops = &wm8753_dai_ops_voice_mode2,
1f53aee0
LG		 1420},
1421/* DAI HiFi mode 3 */
f0fba2ad 1422{ .name = "wm8753-hifi",
1f53aee0
LG		 1423 .playback = {
1424 .stream_name = "HiFi Playback",
1425 .channels_min = 1,
1426 .channels_max = 2,
1427 .rates = WM8753_RATES,
1428 .formats = WM8753_FORMATS,},
1429 .capture = {
1430 .stream_name = "Capture",
1431 .channels_min = 1,
1432 .channels_max = 2,
1433 .rates = WM8753_RATES,
1434 .formats = WM8753_FORMATS,},
6335d055 1435 .ops = &wm8753_dai_ops_hifi_mode3,
1f53aee0
LG		 1436},
1437/* DAI Voice mode 3 - dummy */
f0fba2ad 1438{ .name = "wm8753-voice",
1f53aee0
LG		 1439},
1440/* DAI HiFi mode 4 */
f0fba2ad 1441{ .name = "wm8753-hifi",
1f53aee0
LG		 1442 .playback = {
1443 .stream_name = "HiFi Playback",
1444 .channels_min = 1,
1445 .channels_max = 2,
1446 .rates = WM8753_RATES,
1447 .formats = WM8753_FORMATS,},
1448 .capture = {
1449 .stream_name = "Capture",
1450 .channels_min = 1,
1451 .channels_max = 2,
1452 .rates = WM8753_RATES,
1453 .formats = WM8753_FORMATS,},
6335d055 1454 .ops = &wm8753_dai_ops_hifi_mode4,
1f53aee0
LG		 1455},
1456/* DAI Voice mode 4 - dummy */
f0fba2ad 1457{ .name = "wm8753-voice",
1f53aee0
LG		 1458},
1459};
1460
f0fba2ad 1461static struct snd_soc_dai_driver wm8753_dai[] = {
9e70c1f0 1462 {
f0fba2ad 1463 .name = "wm8753-aif0",
9e70c1f0
MB		 1464 },
1465 {
f0fba2ad 1466 .name = "wm8753-aif1",
9e70c1f0
MB		 1467 },
1468};
1f53aee0 1469
f0fba2ad
LG		 1470static void wm8753_set_dai_mode(struct snd_soc_codec *codec,
1471 struct snd_soc_dai *dai, unsigned int hifi)
1f53aee0 1472{
f0fba2ad
LG		 1473 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1474
1475 if (wm8753->dai_func < 4) {
1476 if (hifi)
1477 dai->driver = &wm8753_all_dai[wm8753->dai_func << 1];
1478 else
1479 dai->driver = &wm8753_all_dai[(wm8753->dai_func << 1) + 1];
1f53aee0 1480 }
f0fba2ad 1481 wm8753_write(codec, WM8753_IOCTL, wm8753->dai_func);
1f53aee0
LG		 1482}
1483
1484static void wm8753_work(struct work_struct *work)
1485{
1486 struct snd_soc_codec *codec =
1487 container_of(work, struct snd_soc_codec, delayed_work.work);
0be9898a 1488 wm8753_set_bias_level(codec, codec->bias_level);
1f53aee0
LG		 1489}
1490
f0fba2ad 1491static int wm8753_suspend(struct snd_soc_codec *codec, pm_message_t state)
1f53aee0 1492{
0be9898a 1493 wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF);
1f53aee0
LG		 1494 return 0;
1495}
1496
f0fba2ad 1497static int wm8753_resume(struct snd_soc_codec *codec)
1f53aee0 1498{
1f53aee0
LG		 1499 int i;
1500 u8 data[2];
1501 u16 *cache = codec->reg_cache;
1502
1f53aee0
LG		 1503 /* Sync reg_cache with the hardware */
1504 for (i = 0; i < ARRAY_SIZE(wm8753_reg); i++) {
1505 if (i + 1 == WM8753_RESET)
1506 continue;
e611bd82
MB		 1507
1508 /* No point in writing hardware default values back */
1509 if (cache[i] == wm8753_reg[i])
1510 continue;
1511
1f53aee0
LG		 1512 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
1513 data[1] = cache[i] & 0x00ff;
1514 codec->hw_write(codec->control_data, data, 2);
1515 }
1516
0be9898a 1517 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1f53aee0
LG		 1518
1519 /* charge wm8753 caps */
0be9898a
MB		 1520 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) {
1521 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1522 codec->bias_level = SND_SOC_BIAS_ON;
1f53aee0
LG		 1523 schedule_delayed_work(&codec->delayed_work,
1524 msecs_to_jiffies(caps_charge));
1525 }
1526
1527 return 0;
1528}
1529
1f53aee0
LG		 1530/*
1531 * This function forces any delayed work to be queued and run.
1532 */
1533static int run_delayed_work(struct delayed_work *dwork)
1534{
1535 int ret;
1536
1537 /* cancel any work waiting to be queued. */
1538 ret = cancel_delayed_work(dwork);
1539
1540 /* if there was any work waiting then we run it now and
1541 * wait for it's completion */
1542 if (ret) {
1543 schedule_delayed_work(dwork, 0);
1544 flush_scheduled_work();
1545 }
1546 return ret;
1547}
1548
f0fba2ad 1549static int wm8753_probe(struct snd_soc_codec *codec)
1f53aee0 1550{
f0fba2ad
LG		 1551 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1552 int ret = 0, reg;
1f53aee0 1553
f0fba2ad
LG		 1554 codec->bias_level = SND_SOC_BIAS_OFF,
1555 codec->control_data = wm8753->control_data;
1556 INIT_DELAYED_WORK(&codec->delayed_work, wm8753_work);
c2bac160 1557
f0fba2ad
LG		 1558 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8753->control_type);
1559 if (ret < 0) {
1560 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1561 return ret;
c2bac160
MB		 1562 }
1563
c2bac160
MB		 1564 ret = wm8753_reset(codec);
1565 if (ret < 0) {
f0fba2ad
LG		 1566 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1567 return ret;
c2bac160
MB		 1568 }
1569
f0fba2ad
LG		 1570 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1571 wm8753->dai_func = 0;
1572
c2bac160
MB		 1573 /* charge output caps */
1574 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1575 schedule_delayed_work(&codec->delayed_work,
1576 msecs_to_jiffies(caps_charge));
1577
1578 /* set the update bits */
1579 reg = wm8753_read_reg_cache(codec, WM8753_LDAC);
1580 wm8753_write(codec, WM8753_LDAC, reg | 0x0100);
1581 reg = wm8753_read_reg_cache(codec, WM8753_RDAC);
1582 wm8753_write(codec, WM8753_RDAC, reg | 0x0100);
1583 reg = wm8753_read_reg_cache(codec, WM8753_LADC);
1584 wm8753_write(codec, WM8753_LADC, reg | 0x0100);
1585 reg = wm8753_read_reg_cache(codec, WM8753_RADC);
1586 wm8753_write(codec, WM8753_RADC, reg | 0x0100);
1587 reg = wm8753_read_reg_cache(codec, WM8753_LOUT1V);
1588 wm8753_write(codec, WM8753_LOUT1V, reg | 0x0100);
1589 reg = wm8753_read_reg_cache(codec, WM8753_ROUT1V);
1590 wm8753_write(codec, WM8753_ROUT1V, reg | 0x0100);
1591 reg = wm8753_read_reg_cache(codec, WM8753_LOUT2V);
1592 wm8753_write(codec, WM8753_LOUT2V, reg | 0x0100);
1593 reg = wm8753_read_reg_cache(codec, WM8753_ROUT2V);
1594 wm8753_write(codec, WM8753_ROUT2V, reg | 0x0100);
1595 reg = wm8753_read_reg_cache(codec, WM8753_LINVOL);
1596 wm8753_write(codec, WM8753_LINVOL, reg | 0x0100);
1597 reg = wm8753_read_reg_cache(codec, WM8753_RINVOL);
1598 wm8753_write(codec, WM8753_RINVOL, reg | 0x0100);
1599
f0fba2ad
LG		 1600 snd_soc_add_controls(codec, wm8753_snd_controls,
1601 ARRAY_SIZE(wm8753_snd_controls));
1602 wm8753_add_widgets(codec);
c2bac160
MB		 1603
1604 return 0;
1605
c2bac160 1606 run_delayed_work(&codec->delayed_work);
c2bac160
MB		 1607 return ret;
1608}
1609
f0fba2ad
LG		 1610/* power down chip */
1611static int wm8753_remove(struct snd_soc_codec *codec)
c2bac160 1612{
f0fba2ad
LG		 1613 run_delayed_work(&codec->delayed_work);
1614 wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF);
1615
1616 return 0;
c2bac160
MB		 1617}
1618
f0fba2ad
LG		 1619static struct snd_soc_codec_driver soc_codec_dev_wm8753 = {
1620 .probe = wm8753_probe,
1621 .remove = wm8753_remove,
1622 .suspend = wm8753_suspend,
1623 .resume = wm8753_resume,
1624 .set_bias_level = wm8753_set_bias_level,
1625 .reg_cache_size = sizeof(wm8753_reg),
1626 .reg_word_size = sizeof(u16),
1627 .reg_cache_default = wm8753_reg,
1628};
69e169da 1629
f0fba2ad
LG		 1630#if defined(CONFIG_SPI_MASTER)
1631static int __devinit wm8753_spi_probe(struct spi_device *spi)
69e169da 1632{
c2bac160 1633 struct wm8753_priv *wm8753;
f0fba2ad 1634 int ret;
69e169da 1635
c2bac160
MB		 1636 wm8753 = kzalloc(sizeof(struct wm8753_priv), GFP_KERNEL);
1637 if (wm8753 == NULL)
1638 return -ENOMEM;
69e169da 1639
f0fba2ad
LG		 1640 wm8753->control_data = spi;
1641 wm8753->control_type = SND_SOC_SPI;
1642 spi_set_drvdata(spi, wm8753);
c2bac160 1643
f0fba2ad
LG		 1644 ret = snd_soc_register_codec(&spi->dev,
1645 &soc_codec_dev_wm8753, wm8753_dai, ARRAY_SIZE(wm8753_dai));
1646 if (ret < 0)
1647 kfree(wm8753);
1648 return ret;
69e169da
MB		 1649}
1650
f0fba2ad 1651static int __devexit wm8753_spi_remove(struct spi_device *spi)
69e169da 1652{
f0fba2ad
LG		 1653 snd_soc_unregister_codec(&spi->dev);
1654 kfree(spi_get_drvdata(spi));
1655 return 0;
69e169da
MB		 1656}
1657
f0fba2ad 1658static struct spi_driver wm8753_spi_driver = {
69e169da 1659 .driver = {
f0fba2ad
LG		 1660 .name = "wm8753-codec",
1661 .bus = &spi_bus_type,
1662 .owner = THIS_MODULE,
69e169da 1663 },
f0fba2ad
LG		 1664 .probe = wm8753_spi_probe,
1665 .remove = __devexit_p(wm8753_spi_remove),
69e169da 1666};
f0fba2ad 1667#endif /* CONFIG_SPI_MASTER */
69e169da 1668
f0fba2ad
LG		 1669#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1670static __devinit int wm8753_i2c_probe(struct i2c_client *i2c,
1671 const struct i2c_device_id *id)
69e169da 1672{
c2bac160 1673 struct wm8753_priv *wm8753;
f0fba2ad 1674 int ret;
c2bac160
MB		 1675
1676 wm8753 = kzalloc(sizeof(struct wm8753_priv), GFP_KERNEL);
1677 if (wm8753 == NULL)
1678 return -ENOMEM;
69e169da 1679
f0fba2ad
LG		 1680 i2c_set_clientdata(i2c, wm8753);
1681 wm8753->control_data = i2c;
1682 wm8753->control_type = SND_SOC_I2C;
69e169da 1683
f0fba2ad
LG		 1684 ret = snd_soc_register_codec(&i2c->dev,
1685 &soc_codec_dev_wm8753, wm8753_dai, ARRAY_SIZE(wm8753_dai));
1686 if (ret < 0)
1687 kfree(wm8753);
1688 return ret;
69e169da
MB		 1689}
1690
f0fba2ad 1691static __devexit int wm8753_i2c_remove(struct i2c_client *client)
69e169da 1692{
f0fba2ad
LG		 1693 snd_soc_unregister_codec(&client->dev);
1694 kfree(i2c_get_clientdata(client));
69e169da
MB		 1695 return 0;
1696}
1697
f0fba2ad
LG		 1698static const struct i2c_device_id wm8753_i2c_id[] = {
1699 { "wm8753", 0 },
1700 { }
1701};
1702MODULE_DEVICE_TABLE(i2c, wm8753_i2c_id);
1703
1704static struct i2c_driver wm8753_i2c_driver = {
69e169da 1705 .driver = {
f0fba2ad
LG		 1706 .name = "wm8753-codec",
1707 .owner = THIS_MODULE,
69e169da 1708 },
f0fba2ad
LG		 1709 .probe = wm8753_i2c_probe,
1710 .remove = __devexit_p(wm8753_i2c_remove),
1711 .id_table = wm8753_i2c_id,
69e169da
MB		 1712};
1713#endif
1714
c9b3a40f 1715static int __init wm8753_modinit(void)
64089b84 1716{
f0fba2ad 1717 int ret = 0;
c2bac160
MB		 1718#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1719 ret = i2c_add_driver(&wm8753_i2c_driver);
f0fba2ad
LG		 1720 if (ret != 0) {
1721 printk(KERN_ERR "Failed to register wm8753 I2C driver: %d\n",
1722 ret);
1723 }
c2bac160
MB		 1724#endif
1725#if defined(CONFIG_SPI_MASTER)
1726 ret = spi_register_driver(&wm8753_spi_driver);
f0fba2ad
LG		 1727 if (ret != 0) {
1728 printk(KERN_ERR "Failed to register wm8753 SPI driver: %d\n",
1729 ret);
1730 }
c2bac160 1731#endif
f0fba2ad 1732 return ret;
64089b84
MB		 1733}
1734module_init(wm8753_modinit);
1735
1736static void __exit wm8753_exit(void)
1737{
c2bac160
MB		 1738#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1739 i2c_del_driver(&wm8753_i2c_driver);
1740#endif
1741#if defined(CONFIG_SPI_MASTER)
1742 spi_unregister_driver(&wm8753_spi_driver);
1743#endif
64089b84
MB		 1744}
1745module_exit(wm8753_exit);
1746
1f53aee0
LG		 1747MODULE_DESCRIPTION("ASoC WM8753 driver");
1748MODULE_AUTHOR("Liam Girdwood");
1749MODULE_LICENSE("GPL");
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