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Commit | Line | Data |
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f1c0a02f MB |
1 | /* |
2 | * wm8903.c -- WM8903 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2008 Wolfson Microelectronics | |
7cfe5617 | 5 | * Copyright 2011 NVIDIA, Inc. |
f1c0a02f MB |
6 | * |
7 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * TODO: | |
14 | * - TDM mode configuration. | |
f1c0a02f | 15 | * - Digital microphone support. |
f1c0a02f MB |
16 | */ |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/moduleparam.h> | |
20 | #include <linux/init.h> | |
8abd16a6 | 21 | #include <linux/completion.h> |
f1c0a02f | 22 | #include <linux/delay.h> |
7cfe5617 | 23 | #include <linux/gpio.h> |
f1c0a02f MB |
24 | #include <linux/pm.h> |
25 | #include <linux/i2c.h> | |
26 | #include <linux/platform_device.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
f1c0a02f | 28 | #include <sound/core.h> |
7245387e | 29 | #include <sound/jack.h> |
f1c0a02f MB |
30 | #include <sound/pcm.h> |
31 | #include <sound/pcm_params.h> | |
32 | #include <sound/tlv.h> | |
33 | #include <sound/soc.h> | |
f1c0a02f | 34 | #include <sound/initval.h> |
8abd16a6 | 35 | #include <sound/wm8903.h> |
2bbb5d66 | 36 | #include <trace/events/asoc.h> |
f1c0a02f MB |
37 | |
38 | #include "wm8903.h" | |
39 | ||
f1c0a02f MB |
40 | /* Register defaults at reset */ |
41 | static u16 wm8903_reg_defaults[] = { | |
42 | 0x8903, /* R0 - SW Reset and ID */ | |
43 | 0x0000, /* R1 - Revision Number */ | |
44 | 0x0000, /* R2 */ | |
45 | 0x0000, /* R3 */ | |
46 | 0x0018, /* R4 - Bias Control 0 */ | |
47 | 0x0000, /* R5 - VMID Control 0 */ | |
48 | 0x0000, /* R6 - Mic Bias Control 0 */ | |
49 | 0x0000, /* R7 */ | |
50 | 0x0001, /* R8 - Analogue DAC 0 */ | |
51 | 0x0000, /* R9 */ | |
52 | 0x0001, /* R10 - Analogue ADC 0 */ | |
53 | 0x0000, /* R11 */ | |
54 | 0x0000, /* R12 - Power Management 0 */ | |
55 | 0x0000, /* R13 - Power Management 1 */ | |
56 | 0x0000, /* R14 - Power Management 2 */ | |
57 | 0x0000, /* R15 - Power Management 3 */ | |
58 | 0x0000, /* R16 - Power Management 4 */ | |
59 | 0x0000, /* R17 - Power Management 5 */ | |
60 | 0x0000, /* R18 - Power Management 6 */ | |
61 | 0x0000, /* R19 */ | |
62 | 0x0400, /* R20 - Clock Rates 0 */ | |
63 | 0x0D07, /* R21 - Clock Rates 1 */ | |
64 | 0x0000, /* R22 - Clock Rates 2 */ | |
65 | 0x0000, /* R23 */ | |
66 | 0x0050, /* R24 - Audio Interface 0 */ | |
67 | 0x0242, /* R25 - Audio Interface 1 */ | |
68 | 0x0008, /* R26 - Audio Interface 2 */ | |
69 | 0x0022, /* R27 - Audio Interface 3 */ | |
70 | 0x0000, /* R28 */ | |
71 | 0x0000, /* R29 */ | |
72 | 0x00C0, /* R30 - DAC Digital Volume Left */ | |
73 | 0x00C0, /* R31 - DAC Digital Volume Right */ | |
74 | 0x0000, /* R32 - DAC Digital 0 */ | |
75 | 0x0000, /* R33 - DAC Digital 1 */ | |
76 | 0x0000, /* R34 */ | |
77 | 0x0000, /* R35 */ | |
78 | 0x00C0, /* R36 - ADC Digital Volume Left */ | |
79 | 0x00C0, /* R37 - ADC Digital Volume Right */ | |
80 | 0x0000, /* R38 - ADC Digital 0 */ | |
81 | 0x0073, /* R39 - Digital Microphone 0 */ | |
82 | 0x09BF, /* R40 - DRC 0 */ | |
83 | 0x3241, /* R41 - DRC 1 */ | |
84 | 0x0020, /* R42 - DRC 2 */ | |
85 | 0x0000, /* R43 - DRC 3 */ | |
86 | 0x0085, /* R44 - Analogue Left Input 0 */ | |
87 | 0x0085, /* R45 - Analogue Right Input 0 */ | |
88 | 0x0044, /* R46 - Analogue Left Input 1 */ | |
89 | 0x0044, /* R47 - Analogue Right Input 1 */ | |
90 | 0x0000, /* R48 */ | |
91 | 0x0000, /* R49 */ | |
92 | 0x0008, /* R50 - Analogue Left Mix 0 */ | |
93 | 0x0004, /* R51 - Analogue Right Mix 0 */ | |
94 | 0x0000, /* R52 - Analogue Spk Mix Left 0 */ | |
95 | 0x0000, /* R53 - Analogue Spk Mix Left 1 */ | |
96 | 0x0000, /* R54 - Analogue Spk Mix Right 0 */ | |
97 | 0x0000, /* R55 - Analogue Spk Mix Right 1 */ | |
98 | 0x0000, /* R56 */ | |
99 | 0x002D, /* R57 - Analogue OUT1 Left */ | |
100 | 0x002D, /* R58 - Analogue OUT1 Right */ | |
101 | 0x0039, /* R59 - Analogue OUT2 Left */ | |
102 | 0x0039, /* R60 - Analogue OUT2 Right */ | |
103 | 0x0100, /* R61 */ | |
104 | 0x0139, /* R62 - Analogue OUT3 Left */ | |
105 | 0x0139, /* R63 - Analogue OUT3 Right */ | |
106 | 0x0000, /* R64 */ | |
107 | 0x0000, /* R65 - Analogue SPK Output Control 0 */ | |
108 | 0x0000, /* R66 */ | |
109 | 0x0010, /* R67 - DC Servo 0 */ | |
110 | 0x0100, /* R68 */ | |
111 | 0x00A4, /* R69 - DC Servo 2 */ | |
112 | 0x0807, /* R70 */ | |
113 | 0x0000, /* R71 */ | |
114 | 0x0000, /* R72 */ | |
115 | 0x0000, /* R73 */ | |
116 | 0x0000, /* R74 */ | |
117 | 0x0000, /* R75 */ | |
118 | 0x0000, /* R76 */ | |
119 | 0x0000, /* R77 */ | |
120 | 0x0000, /* R78 */ | |
121 | 0x000E, /* R79 */ | |
122 | 0x0000, /* R80 */ | |
123 | 0x0000, /* R81 */ | |
124 | 0x0000, /* R82 */ | |
125 | 0x0000, /* R83 */ | |
126 | 0x0000, /* R84 */ | |
127 | 0x0000, /* R85 */ | |
128 | 0x0000, /* R86 */ | |
129 | 0x0006, /* R87 */ | |
130 | 0x0000, /* R88 */ | |
131 | 0x0000, /* R89 */ | |
132 | 0x0000, /* R90 - Analogue HP 0 */ | |
133 | 0x0060, /* R91 */ | |
134 | 0x0000, /* R92 */ | |
135 | 0x0000, /* R93 */ | |
136 | 0x0000, /* R94 - Analogue Lineout 0 */ | |
137 | 0x0060, /* R95 */ | |
138 | 0x0000, /* R96 */ | |
139 | 0x0000, /* R97 */ | |
140 | 0x0000, /* R98 - Charge Pump 0 */ | |
141 | 0x1F25, /* R99 */ | |
142 | 0x2B19, /* R100 */ | |
143 | 0x01C0, /* R101 */ | |
144 | 0x01EF, /* R102 */ | |
145 | 0x2B00, /* R103 */ | |
146 | 0x0000, /* R104 - Class W 0 */ | |
147 | 0x01C0, /* R105 */ | |
148 | 0x1C10, /* R106 */ | |
149 | 0x0000, /* R107 */ | |
150 | 0x0000, /* R108 - Write Sequencer 0 */ | |
151 | 0x0000, /* R109 - Write Sequencer 1 */ | |
152 | 0x0000, /* R110 - Write Sequencer 2 */ | |
153 | 0x0000, /* R111 - Write Sequencer 3 */ | |
154 | 0x0000, /* R112 - Write Sequencer 4 */ | |
155 | 0x0000, /* R113 */ | |
156 | 0x0000, /* R114 - Control Interface */ | |
157 | 0x0000, /* R115 */ | |
158 | 0x00A8, /* R116 - GPIO Control 1 */ | |
159 | 0x00A8, /* R117 - GPIO Control 2 */ | |
160 | 0x00A8, /* R118 - GPIO Control 3 */ | |
161 | 0x0220, /* R119 - GPIO Control 4 */ | |
162 | 0x01A0, /* R120 - GPIO Control 5 */ | |
163 | 0x0000, /* R121 - Interrupt Status 1 */ | |
164 | 0xFFFF, /* R122 - Interrupt Status 1 Mask */ | |
165 | 0x0000, /* R123 - Interrupt Polarity 1 */ | |
166 | 0x0000, /* R124 */ | |
167 | 0x0003, /* R125 */ | |
168 | 0x0000, /* R126 - Interrupt Control */ | |
169 | 0x0000, /* R127 */ | |
170 | 0x0005, /* R128 */ | |
171 | 0x0000, /* R129 - Control Interface Test 1 */ | |
172 | 0x0000, /* R130 */ | |
173 | 0x0000, /* R131 */ | |
174 | 0x0000, /* R132 */ | |
175 | 0x0000, /* R133 */ | |
176 | 0x0000, /* R134 */ | |
177 | 0x03FF, /* R135 */ | |
178 | 0x0007, /* R136 */ | |
179 | 0x0040, /* R137 */ | |
180 | 0x0000, /* R138 */ | |
181 | 0x0000, /* R139 */ | |
182 | 0x0000, /* R140 */ | |
183 | 0x0000, /* R141 */ | |
184 | 0x0000, /* R142 */ | |
185 | 0x0000, /* R143 */ | |
186 | 0x0000, /* R144 */ | |
187 | 0x0000, /* R145 */ | |
188 | 0x0000, /* R146 */ | |
189 | 0x0000, /* R147 */ | |
190 | 0x4000, /* R148 */ | |
191 | 0x6810, /* R149 - Charge Pump Test 1 */ | |
192 | 0x0004, /* R150 */ | |
193 | 0x0000, /* R151 */ | |
194 | 0x0000, /* R152 */ | |
195 | 0x0000, /* R153 */ | |
196 | 0x0000, /* R154 */ | |
197 | 0x0000, /* R155 */ | |
198 | 0x0000, /* R156 */ | |
199 | 0x0000, /* R157 */ | |
200 | 0x0000, /* R158 */ | |
201 | 0x0000, /* R159 */ | |
202 | 0x0000, /* R160 */ | |
203 | 0x0000, /* R161 */ | |
204 | 0x0000, /* R162 */ | |
205 | 0x0000, /* R163 */ | |
206 | 0x0028, /* R164 - Clock Rate Test 4 */ | |
207 | 0x0004, /* R165 */ | |
208 | 0x0000, /* R166 */ | |
209 | 0x0060, /* R167 */ | |
210 | 0x0000, /* R168 */ | |
211 | 0x0000, /* R169 */ | |
212 | 0x0000, /* R170 */ | |
213 | 0x0000, /* R171 */ | |
214 | 0x0000, /* R172 - Analogue Output Bias 0 */ | |
215 | }; | |
216 | ||
d58d5d55 | 217 | struct wm8903_priv { |
7cfe5617 | 218 | struct snd_soc_codec *codec; |
f0fba2ad | 219 | |
d58d5d55 | 220 | int sysclk; |
f0fba2ad | 221 | int irq; |
d58d5d55 | 222 | |
69fff9bb MB |
223 | int fs; |
224 | int deemph; | |
225 | ||
c5b6a9fe MB |
226 | int dcs_pending; |
227 | int dcs_cache[4]; | |
228 | ||
f2c1fe09 | 229 | /* Reference count */ |
d58d5d55 | 230 | int class_w_users; |
d58d5d55 | 231 | |
7245387e MB |
232 | struct snd_soc_jack *mic_jack; |
233 | int mic_det; | |
234 | int mic_short; | |
235 | int mic_last_report; | |
236 | int mic_delay; | |
7cfe5617 SW |
237 | |
238 | #ifdef CONFIG_GPIOLIB | |
239 | struct gpio_chip gpio_chip; | |
240 | #endif | |
d58d5d55 MB |
241 | }; |
242 | ||
d4754ec9 | 243 | static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg) |
f1c0a02f MB |
244 | { |
245 | switch (reg) { | |
246 | case WM8903_SW_RESET_AND_ID: | |
247 | case WM8903_REVISION_NUMBER: | |
248 | case WM8903_INTERRUPT_STATUS_1: | |
249 | case WM8903_WRITE_SEQUENCER_4: | |
c5b6a9fe MB |
250 | case WM8903_DC_SERVO_READBACK_1: |
251 | case WM8903_DC_SERVO_READBACK_2: | |
252 | case WM8903_DC_SERVO_READBACK_3: | |
253 | case WM8903_DC_SERVO_READBACK_4: | |
8d50e447 | 254 | return 1; |
f1c0a02f MB |
255 | |
256 | default: | |
f1c0a02f | 257 | return 0; |
8d50e447 | 258 | } |
f1c0a02f MB |
259 | } |
260 | ||
f1c0a02f MB |
261 | static void wm8903_reset(struct snd_soc_codec *codec) |
262 | { | |
8d50e447 | 263 | snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0); |
d58d5d55 MB |
264 | memcpy(codec->reg_cache, wm8903_reg_defaults, |
265 | sizeof(wm8903_reg_defaults)); | |
f1c0a02f MB |
266 | } |
267 | ||
42768a12 MB |
268 | static int wm8903_cp_event(struct snd_soc_dapm_widget *w, |
269 | struct snd_kcontrol *kcontrol, int event) | |
270 | { | |
271 | WARN_ON(event != SND_SOC_DAPM_POST_PMU); | |
272 | mdelay(4); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
c5b6a9fe MB |
277 | static int wm8903_dcs_event(struct snd_soc_dapm_widget *w, |
278 | struct snd_kcontrol *kcontrol, int event) | |
279 | { | |
280 | struct snd_soc_codec *codec = w->codec; | |
281 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
282 | ||
283 | switch (event) { | |
284 | case SND_SOC_DAPM_POST_PMU: | |
285 | wm8903->dcs_pending |= 1 << w->shift; | |
286 | break; | |
287 | case SND_SOC_DAPM_PRE_PMD: | |
288 | snd_soc_update_bits(codec, WM8903_DC_SERVO_0, | |
289 | 1 << w->shift, 0); | |
290 | break; | |
291 | } | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | #define WM8903_DCS_MODE_WRITE_STOP 0 | |
297 | #define WM8903_DCS_MODE_START_STOP 2 | |
298 | ||
299 | static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm, | |
300 | enum snd_soc_dapm_type event, int subseq) | |
301 | { | |
302 | struct snd_soc_codec *codec = container_of(dapm, | |
303 | struct snd_soc_codec, dapm); | |
304 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
305 | int dcs_mode = WM8903_DCS_MODE_WRITE_STOP; | |
306 | int i, val; | |
307 | ||
308 | /* Complete any pending DC servo starts */ | |
309 | if (wm8903->dcs_pending) { | |
310 | dev_dbg(codec->dev, "Starting DC servo for %x\n", | |
311 | wm8903->dcs_pending); | |
312 | ||
313 | /* If we've no cached values then we need to do startup */ | |
314 | for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { | |
315 | if (!(wm8903->dcs_pending & (1 << i))) | |
316 | continue; | |
317 | ||
318 | if (wm8903->dcs_cache[i]) { | |
319 | dev_dbg(codec->dev, | |
320 | "Restore DC servo %d value %x\n", | |
321 | 3 - i, wm8903->dcs_cache[i]); | |
322 | ||
323 | snd_soc_write(codec, WM8903_DC_SERVO_4 + i, | |
324 | wm8903->dcs_cache[i] & 0xff); | |
325 | } else { | |
326 | dev_dbg(codec->dev, | |
327 | "Calibrate DC servo %d\n", 3 - i); | |
328 | dcs_mode = WM8903_DCS_MODE_START_STOP; | |
329 | } | |
330 | } | |
331 | ||
332 | /* Don't trust the cache for analogue */ | |
333 | if (wm8903->class_w_users) | |
334 | dcs_mode = WM8903_DCS_MODE_START_STOP; | |
335 | ||
336 | snd_soc_update_bits(codec, WM8903_DC_SERVO_2, | |
337 | WM8903_DCS_MODE_MASK, dcs_mode); | |
338 | ||
339 | snd_soc_update_bits(codec, WM8903_DC_SERVO_0, | |
340 | WM8903_DCS_ENA_MASK, wm8903->dcs_pending); | |
341 | ||
342 | switch (dcs_mode) { | |
343 | case WM8903_DCS_MODE_WRITE_STOP: | |
344 | break; | |
345 | ||
346 | case WM8903_DCS_MODE_START_STOP: | |
347 | msleep(270); | |
348 | ||
349 | /* Cache the measured offsets for digital */ | |
350 | if (wm8903->class_w_users) | |
351 | break; | |
352 | ||
353 | for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { | |
354 | if (!(wm8903->dcs_pending & (1 << i))) | |
355 | continue; | |
356 | ||
357 | val = snd_soc_read(codec, | |
358 | WM8903_DC_SERVO_READBACK_1 + i); | |
359 | dev_dbg(codec->dev, "DC servo %d: %x\n", | |
360 | 3 - i, val); | |
361 | wm8903->dcs_cache[i] = val; | |
362 | } | |
363 | break; | |
364 | ||
365 | default: | |
366 | pr_warn("DCS mode %d delay not set\n", dcs_mode); | |
367 | break; | |
368 | } | |
369 | ||
370 | wm8903->dcs_pending = 0; | |
371 | } | |
372 | } | |
373 | ||
f1c0a02f MB |
374 | /* |
375 | * When used with DAC outputs only the WM8903 charge pump supports | |
376 | * operation in class W mode, providing very low power consumption | |
377 | * when used with digital sources. Enable and disable this mode | |
378 | * automatically depending on the mixer configuration. | |
379 | * | |
380 | * All the relevant controls are simple switches. | |
381 | */ | |
382 | static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, | |
383 | struct snd_ctl_elem_value *ucontrol) | |
384 | { | |
385 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); | |
386 | struct snd_soc_codec *codec = widget->codec; | |
b2c812e2 | 387 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
f1c0a02f MB |
388 | u16 reg; |
389 | int ret; | |
390 | ||
8d50e447 | 391 | reg = snd_soc_read(codec, WM8903_CLASS_W_0); |
f1c0a02f MB |
392 | |
393 | /* Turn it off if we're about to enable bypass */ | |
394 | if (ucontrol->value.integer.value[0]) { | |
395 | if (wm8903->class_w_users == 0) { | |
f0fba2ad | 396 | dev_dbg(codec->dev, "Disabling Class W\n"); |
8d50e447 | 397 | snd_soc_write(codec, WM8903_CLASS_W_0, reg & |
f1c0a02f MB |
398 | ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); |
399 | } | |
400 | wm8903->class_w_users++; | |
401 | } | |
402 | ||
403 | /* Implement the change */ | |
404 | ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); | |
405 | ||
406 | /* If we've just disabled the last bypass path turn Class W on */ | |
407 | if (!ucontrol->value.integer.value[0]) { | |
408 | if (wm8903->class_w_users == 1) { | |
f0fba2ad | 409 | dev_dbg(codec->dev, "Enabling Class W\n"); |
8d50e447 | 410 | snd_soc_write(codec, WM8903_CLASS_W_0, reg | |
f1c0a02f MB |
411 | WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); |
412 | } | |
413 | wm8903->class_w_users--; | |
414 | } | |
415 | ||
f0fba2ad | 416 | dev_dbg(codec->dev, "Bypass use count now %d\n", |
f1c0a02f MB |
417 | wm8903->class_w_users); |
418 | ||
419 | return ret; | |
420 | } | |
421 | ||
422 | #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ | |
423 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
424 | .info = snd_soc_info_volsw, \ | |
425 | .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \ | |
426 | .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } | |
427 | ||
428 | ||
69fff9bb MB |
429 | static int wm8903_deemph[] = { 0, 32000, 44100, 48000 }; |
430 | ||
431 | static int wm8903_set_deemph(struct snd_soc_codec *codec) | |
432 | { | |
433 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
434 | int val, i, best; | |
435 | ||
436 | /* If we're using deemphasis select the nearest available sample | |
437 | * rate. | |
438 | */ | |
439 | if (wm8903->deemph) { | |
440 | best = 1; | |
441 | for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) { | |
442 | if (abs(wm8903_deemph[i] - wm8903->fs) < | |
443 | abs(wm8903_deemph[best] - wm8903->fs)) | |
444 | best = i; | |
445 | } | |
446 | ||
447 | val = best << WM8903_DEEMPH_SHIFT; | |
448 | } else { | |
449 | best = 0; | |
450 | val = 0; | |
451 | } | |
452 | ||
453 | dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n", | |
454 | best, wm8903_deemph[best]); | |
455 | ||
456 | return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1, | |
457 | WM8903_DEEMPH_MASK, val); | |
458 | } | |
459 | ||
460 | static int wm8903_get_deemph(struct snd_kcontrol *kcontrol, | |
461 | struct snd_ctl_elem_value *ucontrol) | |
462 | { | |
463 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
464 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
465 | ||
466 | ucontrol->value.enumerated.item[0] = wm8903->deemph; | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
471 | static int wm8903_put_deemph(struct snd_kcontrol *kcontrol, | |
472 | struct snd_ctl_elem_value *ucontrol) | |
473 | { | |
474 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
475 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
476 | int deemph = ucontrol->value.enumerated.item[0]; | |
477 | int ret = 0; | |
478 | ||
479 | if (deemph > 1) | |
480 | return -EINVAL; | |
481 | ||
482 | mutex_lock(&codec->mutex); | |
483 | if (wm8903->deemph != deemph) { | |
484 | wm8903->deemph = deemph; | |
485 | ||
486 | wm8903_set_deemph(codec); | |
487 | ||
488 | ret = 1; | |
489 | } | |
490 | mutex_unlock(&codec->mutex); | |
491 | ||
492 | return ret; | |
493 | } | |
494 | ||
f1c0a02f MB |
495 | /* ALSA can only do steps of .01dB */ |
496 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
497 | ||
291ce18c | 498 | static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); |
f1c0a02f MB |
499 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); |
500 | ||
501 | static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); | |
502 | static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); | |
503 | static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); | |
504 | static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); | |
505 | static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); | |
506 | ||
460f4aae MB |
507 | static const char *hpf_mode_text[] = { |
508 | "Hi-fi", "Voice 1", "Voice 2", "Voice 3" | |
509 | }; | |
510 | ||
511 | static const struct soc_enum hpf_mode = | |
512 | SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text); | |
513 | ||
dcf9ada3 MB |
514 | static const char *osr_text[] = { |
515 | "Low power", "High performance" | |
516 | }; | |
517 | ||
518 | static const struct soc_enum adc_osr = | |
519 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text); | |
520 | ||
521 | static const struct soc_enum dac_osr = | |
522 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text); | |
523 | ||
f1c0a02f MB |
524 | static const char *drc_slope_text[] = { |
525 | "1", "1/2", "1/4", "1/8", "1/16", "0" | |
526 | }; | |
527 | ||
528 | static const struct soc_enum drc_slope_r0 = | |
529 | SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text); | |
530 | ||
531 | static const struct soc_enum drc_slope_r1 = | |
532 | SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text); | |
533 | ||
534 | static const char *drc_attack_text[] = { | |
535 | "instantaneous", | |
536 | "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", | |
537 | "46.4ms", "92.8ms", "185.6ms" | |
538 | }; | |
539 | ||
540 | static const struct soc_enum drc_attack = | |
541 | SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text); | |
542 | ||
543 | static const char *drc_decay_text[] = { | |
544 | "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", | |
545 | "23.87s", "47.56s" | |
546 | }; | |
547 | ||
548 | static const struct soc_enum drc_decay = | |
549 | SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text); | |
550 | ||
551 | static const char *drc_ff_delay_text[] = { | |
552 | "5 samples", "9 samples" | |
553 | }; | |
554 | ||
555 | static const struct soc_enum drc_ff_delay = | |
556 | SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text); | |
557 | ||
558 | static const char *drc_qr_decay_text[] = { | |
559 | "0.725ms", "1.45ms", "5.8ms" | |
560 | }; | |
561 | ||
562 | static const struct soc_enum drc_qr_decay = | |
563 | SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text); | |
564 | ||
565 | static const char *drc_smoothing_text[] = { | |
566 | "Low", "Medium", "High" | |
567 | }; | |
568 | ||
569 | static const struct soc_enum drc_smoothing = | |
570 | SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text); | |
571 | ||
572 | static const char *soft_mute_text[] = { | |
573 | "Fast (fs/2)", "Slow (fs/32)" | |
574 | }; | |
575 | ||
576 | static const struct soc_enum soft_mute = | |
577 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text); | |
578 | ||
579 | static const char *mute_mode_text[] = { | |
580 | "Hard", "Soft" | |
581 | }; | |
582 | ||
583 | static const struct soc_enum mute_mode = | |
584 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); | |
585 | ||
f1c0a02f MB |
586 | static const char *companding_text[] = { |
587 | "ulaw", "alaw" | |
588 | }; | |
589 | ||
590 | static const struct soc_enum dac_companding = | |
591 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text); | |
592 | ||
593 | static const struct soc_enum adc_companding = | |
594 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text); | |
595 | ||
596 | static const char *input_mode_text[] = { | |
597 | "Single-Ended", "Differential Line", "Differential Mic" | |
598 | }; | |
599 | ||
600 | static const struct soc_enum linput_mode_enum = | |
601 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); | |
602 | ||
603 | static const struct soc_enum rinput_mode_enum = | |
604 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); | |
605 | ||
606 | static const char *linput_mux_text[] = { | |
607 | "IN1L", "IN2L", "IN3L" | |
608 | }; | |
609 | ||
610 | static const struct soc_enum linput_enum = | |
611 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text); | |
612 | ||
613 | static const struct soc_enum linput_inv_enum = | |
614 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text); | |
615 | ||
616 | static const char *rinput_mux_text[] = { | |
617 | "IN1R", "IN2R", "IN3R" | |
618 | }; | |
619 | ||
620 | static const struct soc_enum rinput_enum = | |
621 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text); | |
622 | ||
623 | static const struct soc_enum rinput_inv_enum = | |
624 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); | |
625 | ||
626 | ||
291ce18c MB |
627 | static const char *sidetone_text[] = { |
628 | "None", "Left", "Right" | |
629 | }; | |
630 | ||
631 | static const struct soc_enum lsidetone_enum = | |
632 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text); | |
633 | ||
634 | static const struct soc_enum rsidetone_enum = | |
635 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text); | |
636 | ||
1e113bf9 MB |
637 | static const char *aif_text[] = { |
638 | "Left", "Right" | |
639 | }; | |
640 | ||
641 | static const struct soc_enum lcapture_enum = | |
642 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text); | |
643 | ||
644 | static const struct soc_enum rcapture_enum = | |
645 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text); | |
646 | ||
647 | static const struct soc_enum lplay_enum = | |
648 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text); | |
649 | ||
650 | static const struct soc_enum rplay_enum = | |
651 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text); | |
652 | ||
f1c0a02f MB |
653 | static const struct snd_kcontrol_new wm8903_snd_controls[] = { |
654 | ||
655 | /* Input PGAs - No TLV since the scale depends on PGA mode */ | |
656 | SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, | |
5715952b | 657 | 7, 1, 1), |
f1c0a02f MB |
658 | SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, |
659 | 0, 31, 0), | |
660 | SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, | |
661 | 6, 1, 0), | |
662 | ||
663 | SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, | |
5715952b | 664 | 7, 1, 1), |
f1c0a02f MB |
665 | SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, |
666 | 0, 31, 0), | |
667 | SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, | |
668 | 6, 1, 0), | |
669 | ||
670 | /* ADCs */ | |
dcf9ada3 | 671 | SOC_ENUM("ADC OSR", adc_osr), |
460f4aae MB |
672 | SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0), |
673 | SOC_ENUM("HPF Mode", hpf_mode), | |
f1c0a02f MB |
674 | SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), |
675 | SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), | |
676 | SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), | |
af901ca1 | 677 | SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, |
f1c0a02f MB |
678 | drc_tlv_thresh), |
679 | SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), | |
680 | SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), | |
681 | SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), | |
682 | SOC_ENUM("DRC Attack Rate", drc_attack), | |
683 | SOC_ENUM("DRC Decay Rate", drc_decay), | |
684 | SOC_ENUM("DRC FF Delay", drc_ff_delay), | |
685 | SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), | |
686 | SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), | |
af901ca1 | 687 | SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), |
f1c0a02f MB |
688 | SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), |
689 | SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), | |
690 | SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), | |
af901ca1 | 691 | SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), |
f1c0a02f MB |
692 | SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), |
693 | ||
694 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, | |
61bf35b9 | 695 | WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), |
f1c0a02f MB |
696 | SOC_ENUM("ADC Companding Mode", adc_companding), |
697 | SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), | |
698 | ||
291ce18c MB |
699 | SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, |
700 | 12, 0, digital_sidetone_tlv), | |
701 | ||
f1c0a02f | 702 | /* DAC */ |
dcf9ada3 | 703 | SOC_ENUM("DAC OSR", dac_osr), |
f1c0a02f MB |
704 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, |
705 | WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), | |
706 | SOC_ENUM("DAC Soft Mute Rate", soft_mute), | |
707 | SOC_ENUM("DAC Mute Mode", mute_mode), | |
708 | SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), | |
f1c0a02f MB |
709 | SOC_ENUM("DAC Companding Mode", dac_companding), |
710 | SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), | |
69fff9bb MB |
711 | SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0, |
712 | wm8903_get_deemph, wm8903_put_deemph), | |
f1c0a02f MB |
713 | |
714 | /* Headphones */ | |
715 | SOC_DOUBLE_R("Headphone Switch", | |
716 | WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, | |
717 | 8, 1, 1), | |
718 | SOC_DOUBLE_R("Headphone ZC Switch", | |
719 | WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, | |
720 | 6, 1, 0), | |
721 | SOC_DOUBLE_R_TLV("Headphone Volume", | |
722 | WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, | |
723 | 0, 63, 0, out_tlv), | |
724 | ||
725 | /* Line out */ | |
726 | SOC_DOUBLE_R("Line Out Switch", | |
727 | WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, | |
728 | 8, 1, 1), | |
729 | SOC_DOUBLE_R("Line Out ZC Switch", | |
730 | WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, | |
731 | 6, 1, 0), | |
732 | SOC_DOUBLE_R_TLV("Line Out Volume", | |
733 | WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, | |
734 | 0, 63, 0, out_tlv), | |
735 | ||
736 | /* Speaker */ | |
737 | SOC_DOUBLE_R("Speaker Switch", | |
738 | WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), | |
739 | SOC_DOUBLE_R("Speaker ZC Switch", | |
740 | WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), | |
741 | SOC_DOUBLE_R_TLV("Speaker Volume", | |
742 | WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, | |
743 | 0, 63, 0, out_tlv), | |
744 | }; | |
745 | ||
f1c0a02f MB |
746 | static const struct snd_kcontrol_new linput_mode_mux = |
747 | SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); | |
748 | ||
749 | static const struct snd_kcontrol_new rinput_mode_mux = | |
750 | SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); | |
751 | ||
752 | static const struct snd_kcontrol_new linput_mux = | |
753 | SOC_DAPM_ENUM("Left Input Mux", linput_enum); | |
754 | ||
755 | static const struct snd_kcontrol_new linput_inv_mux = | |
756 | SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); | |
757 | ||
758 | static const struct snd_kcontrol_new rinput_mux = | |
759 | SOC_DAPM_ENUM("Right Input Mux", rinput_enum); | |
760 | ||
761 | static const struct snd_kcontrol_new rinput_inv_mux = | |
762 | SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); | |
763 | ||
291ce18c MB |
764 | static const struct snd_kcontrol_new lsidetone_mux = |
765 | SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); | |
766 | ||
767 | static const struct snd_kcontrol_new rsidetone_mux = | |
768 | SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); | |
769 | ||
1e113bf9 MB |
770 | static const struct snd_kcontrol_new lcapture_mux = |
771 | SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum); | |
772 | ||
773 | static const struct snd_kcontrol_new rcapture_mux = | |
774 | SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum); | |
775 | ||
776 | static const struct snd_kcontrol_new lplay_mux = | |
777 | SOC_DAPM_ENUM("Left Playback Mux", lplay_enum); | |
778 | ||
779 | static const struct snd_kcontrol_new rplay_mux = | |
780 | SOC_DAPM_ENUM("Right Playback Mux", rplay_enum); | |
781 | ||
f1c0a02f MB |
782 | static const struct snd_kcontrol_new left_output_mixer[] = { |
783 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), | |
784 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), | |
785 | SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), | |
4b4fffdd | 786 | SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), |
f1c0a02f MB |
787 | }; |
788 | ||
789 | static const struct snd_kcontrol_new right_output_mixer[] = { | |
790 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), | |
791 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), | |
792 | SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), | |
4b4fffdd | 793 | SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), |
f1c0a02f MB |
794 | }; |
795 | ||
796 | static const struct snd_kcontrol_new left_speaker_mixer[] = { | |
797 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), | |
798 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), | |
799 | SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), | |
800 | SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, | |
4b4fffdd | 801 | 0, 1, 0), |
f1c0a02f MB |
802 | }; |
803 | ||
804 | static const struct snd_kcontrol_new right_speaker_mixer[] = { | |
805 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), | |
806 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), | |
807 | SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, | |
808 | 1, 1, 0), | |
809 | SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, | |
4b4fffdd | 810 | 0, 1, 0), |
f1c0a02f MB |
811 | }; |
812 | ||
813 | static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { | |
814 | SND_SOC_DAPM_INPUT("IN1L"), | |
815 | SND_SOC_DAPM_INPUT("IN1R"), | |
816 | SND_SOC_DAPM_INPUT("IN2L"), | |
817 | SND_SOC_DAPM_INPUT("IN2R"), | |
818 | SND_SOC_DAPM_INPUT("IN3L"), | |
819 | SND_SOC_DAPM_INPUT("IN3R"), | |
820 | ||
821 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
822 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
823 | SND_SOC_DAPM_OUTPUT("LINEOUTL"), | |
824 | SND_SOC_DAPM_OUTPUT("LINEOUTR"), | |
825 | SND_SOC_DAPM_OUTPUT("LOP"), | |
826 | SND_SOC_DAPM_OUTPUT("LON"), | |
827 | SND_SOC_DAPM_OUTPUT("ROP"), | |
828 | SND_SOC_DAPM_OUTPUT("RON"), | |
829 | ||
830 | SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0), | |
831 | ||
832 | SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), | |
833 | SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, | |
834 | &linput_inv_mux), | |
835 | SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), | |
836 | ||
837 | SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), | |
838 | SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, | |
839 | &rinput_inv_mux), | |
840 | SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), | |
841 | ||
842 | SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), | |
843 | SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), | |
844 | ||
1e113bf9 MB |
845 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0), |
846 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0), | |
847 | ||
848 | SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux), | |
849 | SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux), | |
850 | ||
851 | SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0), | |
852 | SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0), | |
f1c0a02f | 853 | |
291ce18c MB |
854 | SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), |
855 | SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), | |
856 | ||
1e113bf9 MB |
857 | SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0), |
858 | SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0), | |
859 | ||
860 | SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux), | |
861 | SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux), | |
862 | ||
863 | SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0), | |
864 | SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0), | |
f1c0a02f MB |
865 | |
866 | SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, | |
867 | left_output_mixer, ARRAY_SIZE(left_output_mixer)), | |
868 | SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, | |
869 | right_output_mixer, ARRAY_SIZE(right_output_mixer)), | |
870 | ||
871 | SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, | |
872 | left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), | |
873 | SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, | |
874 | right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), | |
875 | ||
1b877cb5 DL |
876 | SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, |
877 | 1, 0, NULL, 0), | |
878 | SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, | |
13a9983e MB |
879 | 0, 0, NULL, 0), |
880 | ||
1b877cb5 | 881 | SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0, |
13a9983e | 882 | NULL, 0), |
1b877cb5 | 883 | SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0, |
13a9983e MB |
884 | NULL, 0), |
885 | ||
886 | SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0), | |
887 | SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0), | |
1b877cb5 DL |
888 | SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0), |
889 | SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0), | |
13a9983e MB |
890 | SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0), |
891 | SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0), | |
1b877cb5 DL |
892 | SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0), |
893 | SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0), | |
13a9983e MB |
894 | |
895 | SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0, | |
896 | NULL, 0), | |
897 | SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0, | |
898 | NULL, 0), | |
1b877cb5 DL |
899 | SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0, |
900 | NULL, 0), | |
901 | SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0, | |
13a9983e MB |
902 | NULL, 0), |
903 | SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0, | |
904 | NULL, 0), | |
905 | SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0, | |
906 | NULL, 0), | |
1b877cb5 DL |
907 | SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0, |
908 | NULL, 0), | |
909 | SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0, | |
13a9983e MB |
910 | NULL, 0), |
911 | ||
c5b6a9fe MB |
912 | SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0), |
913 | SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event, | |
914 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
915 | SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event, | |
916 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
917 | SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event, | |
918 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
919 | SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event, | |
920 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
f1c0a02f MB |
921 | |
922 | SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, | |
923 | NULL, 0), | |
924 | SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, | |
925 | NULL, 0), | |
926 | ||
42768a12 MB |
927 | SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, |
928 | wm8903_cp_event, SND_SOC_DAPM_POST_PMU), | |
c2aef4ff | 929 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), |
2c8be5a2 | 930 | SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0), |
f1c0a02f MB |
931 | }; |
932 | ||
933 | static const struct snd_soc_dapm_route intercon[] = { | |
934 | ||
2c8be5a2 MB |
935 | { "CLK_DSP", NULL, "CLK_SYS" }, |
936 | { "Mic Bias", NULL, "CLK_SYS" }, | |
937 | { "HPL_DCS", NULL, "CLK_SYS" }, | |
938 | { "HPR_DCS", NULL, "CLK_SYS" }, | |
939 | { "LINEOUTL_DCS", NULL, "CLK_SYS" }, | |
940 | { "LINEOUTR_DCS", NULL, "CLK_SYS" }, | |
941 | ||
f1c0a02f MB |
942 | { "Left Input Mux", "IN1L", "IN1L" }, |
943 | { "Left Input Mux", "IN2L", "IN2L" }, | |
944 | { "Left Input Mux", "IN3L", "IN3L" }, | |
945 | ||
946 | { "Left Input Inverting Mux", "IN1L", "IN1L" }, | |
947 | { "Left Input Inverting Mux", "IN2L", "IN2L" }, | |
948 | { "Left Input Inverting Mux", "IN3L", "IN3L" }, | |
949 | ||
950 | { "Right Input Mux", "IN1R", "IN1R" }, | |
951 | { "Right Input Mux", "IN2R", "IN2R" }, | |
952 | { "Right Input Mux", "IN3R", "IN3R" }, | |
953 | ||
954 | { "Right Input Inverting Mux", "IN1R", "IN1R" }, | |
955 | { "Right Input Inverting Mux", "IN2R", "IN2R" }, | |
956 | { "Right Input Inverting Mux", "IN3R", "IN3R" }, | |
957 | ||
958 | { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, | |
959 | { "Left Input Mode Mux", "Differential Line", | |
960 | "Left Input Mux" }, | |
961 | { "Left Input Mode Mux", "Differential Line", | |
962 | "Left Input Inverting Mux" }, | |
963 | { "Left Input Mode Mux", "Differential Mic", | |
964 | "Left Input Mux" }, | |
965 | { "Left Input Mode Mux", "Differential Mic", | |
966 | "Left Input Inverting Mux" }, | |
967 | ||
968 | { "Right Input Mode Mux", "Single-Ended", | |
969 | "Right Input Inverting Mux" }, | |
970 | { "Right Input Mode Mux", "Differential Line", | |
971 | "Right Input Mux" }, | |
972 | { "Right Input Mode Mux", "Differential Line", | |
973 | "Right Input Inverting Mux" }, | |
974 | { "Right Input Mode Mux", "Differential Mic", | |
975 | "Right Input Mux" }, | |
976 | { "Right Input Mode Mux", "Differential Mic", | |
977 | "Right Input Inverting Mux" }, | |
978 | ||
979 | { "Left Input PGA", NULL, "Left Input Mode Mux" }, | |
980 | { "Right Input PGA", NULL, "Right Input Mode Mux" }, | |
981 | ||
1e113bf9 MB |
982 | { "Left Capture Mux", "Left", "ADCL" }, |
983 | { "Left Capture Mux", "Right", "ADCR" }, | |
984 | ||
985 | { "Right Capture Mux", "Left", "ADCL" }, | |
986 | { "Right Capture Mux", "Right", "ADCR" }, | |
987 | ||
988 | { "AIFTXL", NULL, "Left Capture Mux" }, | |
989 | { "AIFTXR", NULL, "Right Capture Mux" }, | |
990 | ||
f1c0a02f | 991 | { "ADCL", NULL, "Left Input PGA" }, |
c2aef4ff | 992 | { "ADCL", NULL, "CLK_DSP" }, |
f1c0a02f | 993 | { "ADCR", NULL, "Right Input PGA" }, |
c2aef4ff MB |
994 | { "ADCR", NULL, "CLK_DSP" }, |
995 | ||
1e113bf9 MB |
996 | { "Left Playback Mux", "Left", "AIFRXL" }, |
997 | { "Left Playback Mux", "Right", "AIFRXR" }, | |
998 | ||
999 | { "Right Playback Mux", "Left", "AIFRXL" }, | |
1000 | { "Right Playback Mux", "Right", "AIFRXR" }, | |
1001 | ||
291ce18c MB |
1002 | { "DACL Sidetone", "Left", "ADCL" }, |
1003 | { "DACL Sidetone", "Right", "ADCR" }, | |
1004 | { "DACR Sidetone", "Left", "ADCL" }, | |
1005 | { "DACR Sidetone", "Right", "ADCR" }, | |
1006 | ||
1e113bf9 | 1007 | { "DACL", NULL, "Left Playback Mux" }, |
291ce18c | 1008 | { "DACL", NULL, "DACL Sidetone" }, |
c2aef4ff | 1009 | { "DACL", NULL, "CLK_DSP" }, |
1e113bf9 MB |
1010 | |
1011 | { "DACR", NULL, "Right Playback Mux" }, | |
291ce18c | 1012 | { "DACR", NULL, "DACR Sidetone" }, |
c2aef4ff | 1013 | { "DACR", NULL, "CLK_DSP" }, |
f1c0a02f MB |
1014 | |
1015 | { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
1016 | { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
1017 | { "Left Output Mixer", "DACL Switch", "DACL" }, | |
1018 | { "Left Output Mixer", "DACR Switch", "DACR" }, | |
1019 | ||
1020 | { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
1021 | { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
1022 | { "Right Output Mixer", "DACL Switch", "DACL" }, | |
1023 | { "Right Output Mixer", "DACR Switch", "DACR" }, | |
1024 | ||
1025 | { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
1026 | { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
1027 | { "Left Speaker Mixer", "DACL Switch", "DACL" }, | |
1028 | { "Left Speaker Mixer", "DACR Switch", "DACR" }, | |
1029 | ||
1030 | { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
1031 | { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
1032 | { "Right Speaker Mixer", "DACL Switch", "DACL" }, | |
1033 | { "Right Speaker Mixer", "DACR Switch", "DACR" }, | |
1034 | ||
1035 | { "Left Line Output PGA", NULL, "Left Output Mixer" }, | |
1036 | { "Right Line Output PGA", NULL, "Right Output Mixer" }, | |
1037 | ||
1038 | { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, | |
1039 | { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, | |
1040 | ||
1041 | { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, | |
1042 | { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, | |
1043 | ||
1b877cb5 DL |
1044 | { "HPL_ENA", NULL, "Left Headphone Output PGA" }, |
1045 | { "HPR_ENA", NULL, "Right Headphone Output PGA" }, | |
1046 | { "HPL_ENA_DLY", NULL, "HPL_ENA" }, | |
1047 | { "HPR_ENA_DLY", NULL, "HPR_ENA" }, | |
1048 | { "LINEOUTL_ENA", NULL, "Left Line Output PGA" }, | |
1049 | { "LINEOUTR_ENA", NULL, "Right Line Output PGA" }, | |
1050 | { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" }, | |
1051 | { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" }, | |
13a9983e | 1052 | |
c5b6a9fe MB |
1053 | { "HPL_DCS", NULL, "DCS Master" }, |
1054 | { "HPR_DCS", NULL, "DCS Master" }, | |
1055 | { "LINEOUTL_DCS", NULL, "DCS Master" }, | |
1056 | { "LINEOUTR_DCS", NULL, "DCS Master" }, | |
1057 | ||
13a9983e MB |
1058 | { "HPL_DCS", NULL, "HPL_ENA_DLY" }, |
1059 | { "HPR_DCS", NULL, "HPR_ENA_DLY" }, | |
1060 | { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" }, | |
1061 | { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" }, | |
1062 | ||
1063 | { "HPL_ENA_OUTP", NULL, "HPL_DCS" }, | |
1064 | { "HPR_ENA_OUTP", NULL, "HPR_DCS" }, | |
1065 | { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" }, | |
1066 | { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" }, | |
1067 | ||
1068 | { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" }, | |
1069 | { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" }, | |
1070 | { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" }, | |
1071 | { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" }, | |
1072 | ||
1073 | { "HPOUTL", NULL, "HPL_RMV_SHORT" }, | |
1074 | { "HPOUTR", NULL, "HPR_RMV_SHORT" }, | |
1075 | { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" }, | |
1076 | { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" }, | |
f1c0a02f MB |
1077 | |
1078 | { "LOP", NULL, "Left Speaker PGA" }, | |
1079 | { "LON", NULL, "Left Speaker PGA" }, | |
1080 | ||
1081 | { "ROP", NULL, "Right Speaker PGA" }, | |
1082 | { "RON", NULL, "Right Speaker PGA" }, | |
42768a12 MB |
1083 | |
1084 | { "Left Headphone Output PGA", NULL, "Charge Pump" }, | |
1085 | { "Right Headphone Output PGA", NULL, "Charge Pump" }, | |
1086 | { "Left Line Output PGA", NULL, "Charge Pump" }, | |
1087 | { "Right Line Output PGA", NULL, "Charge Pump" }, | |
f1c0a02f MB |
1088 | }; |
1089 | ||
1090 | static int wm8903_add_widgets(struct snd_soc_codec *codec) | |
1091 | { | |
ce6120cc | 1092 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
f1c0a02f | 1093 | |
ce6120cc LG |
1094 | snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets, |
1095 | ARRAY_SIZE(wm8903_dapm_widgets)); | |
1096 | snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); | |
f1c0a02f | 1097 | |
f1c0a02f MB |
1098 | return 0; |
1099 | } | |
1100 | ||
1101 | static int wm8903_set_bias_level(struct snd_soc_codec *codec, | |
1102 | enum snd_soc_bias_level level) | |
1103 | { | |
f1c0a02f MB |
1104 | switch (level) { |
1105 | case SND_SOC_BIAS_ON: | |
66daaa59 | 1106 | break; |
22f226dd | 1107 | |
f1c0a02f | 1108 | case SND_SOC_BIAS_PREPARE: |
66daaa59 MB |
1109 | snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, |
1110 | WM8903_VMID_RES_MASK, | |
1111 | WM8903_VMID_RES_50K); | |
f1c0a02f MB |
1112 | break; |
1113 | ||
1114 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 1115 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
22f226dd MB |
1116 | snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, |
1117 | WM8903_POBCTRL | WM8903_ISEL_MASK | | |
1118 | WM8903_STARTUP_BIAS_ENA | | |
1119 | WM8903_BIAS_ENA, | |
1120 | WM8903_POBCTRL | | |
1121 | (2 << WM8903_ISEL_SHIFT) | | |
1122 | WM8903_STARTUP_BIAS_ENA); | |
1123 | ||
1124 | snd_soc_update_bits(codec, | |
1125 | WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, | |
1126 | WM8903_SPK_DISCHARGE, | |
1127 | WM8903_SPK_DISCHARGE); | |
1128 | ||
1129 | msleep(33); | |
1130 | ||
1131 | snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, | |
1132 | WM8903_SPKL_ENA | WM8903_SPKR_ENA, | |
1133 | WM8903_SPKL_ENA | WM8903_SPKR_ENA); | |
1134 | ||
1135 | snd_soc_update_bits(codec, | |
1136 | WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, | |
1137 | WM8903_SPK_DISCHARGE, 0); | |
1138 | ||
1139 | snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, | |
1140 | WM8903_VMID_TIE_ENA | | |
1141 | WM8903_BUFIO_ENA | | |
1142 | WM8903_VMID_IO_ENA | | |
1143 | WM8903_VMID_SOFT_MASK | | |
1144 | WM8903_VMID_RES_MASK | | |
1145 | WM8903_VMID_BUF_ENA, | |
1146 | WM8903_VMID_TIE_ENA | | |
1147 | WM8903_BUFIO_ENA | | |
1148 | WM8903_VMID_IO_ENA | | |
1149 | (2 << WM8903_VMID_SOFT_SHIFT) | | |
1150 | WM8903_VMID_RES_250K | | |
1151 | WM8903_VMID_BUF_ENA); | |
1152 | ||
1153 | msleep(129); | |
1154 | ||
1155 | snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, | |
1156 | WM8903_SPKL_ENA | WM8903_SPKR_ENA, | |
1157 | 0); | |
1158 | ||
1159 | snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, | |
1160 | WM8903_VMID_SOFT_MASK, 0); | |
1161 | ||
1162 | snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, | |
1163 | WM8903_VMID_RES_MASK, | |
1164 | WM8903_VMID_RES_50K); | |
1165 | ||
1166 | snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, | |
1167 | WM8903_BIAS_ENA | WM8903_POBCTRL, | |
1168 | WM8903_BIAS_ENA); | |
f1c0a02f | 1169 | |
f1c0a02f MB |
1170 | /* By default no bypass paths are enabled so |
1171 | * enable Class W support. | |
1172 | */ | |
f0fba2ad | 1173 | dev_dbg(codec->dev, "Enabling Class W\n"); |
524d7692 MB |
1174 | snd_soc_update_bits(codec, WM8903_CLASS_W_0, |
1175 | WM8903_CP_DYN_FREQ | | |
1176 | WM8903_CP_DYN_V, | |
1177 | WM8903_CP_DYN_FREQ | | |
1178 | WM8903_CP_DYN_V); | |
f1c0a02f MB |
1179 | } |
1180 | ||
66daaa59 MB |
1181 | snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, |
1182 | WM8903_VMID_RES_MASK, | |
1183 | WM8903_VMID_RES_250K); | |
f1c0a02f MB |
1184 | break; |
1185 | ||
1186 | case SND_SOC_BIAS_OFF: | |
b4d06f45 MB |
1187 | snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, |
1188 | WM8903_BIAS_ENA, 0); | |
1189 | ||
1190 | snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, | |
1191 | WM8903_VMID_SOFT_MASK, | |
1192 | 2 << WM8903_VMID_SOFT_SHIFT); | |
1193 | ||
1194 | snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, | |
1195 | WM8903_VMID_BUF_ENA, 0); | |
1196 | ||
1197 | msleep(290); | |
1198 | ||
1199 | snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, | |
1200 | WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA | | |
1201 | WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK | | |
1202 | WM8903_VMID_SOFT_MASK | | |
1203 | WM8903_VMID_BUF_ENA, 0); | |
1204 | ||
1205 | snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, | |
1206 | WM8903_STARTUP_BIAS_ENA, 0); | |
f1c0a02f MB |
1207 | break; |
1208 | } | |
1209 | ||
ce6120cc | 1210 | codec->dapm.bias_level = level; |
f1c0a02f MB |
1211 | |
1212 | return 0; | |
1213 | } | |
1214 | ||
1215 | static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1216 | int clk_id, unsigned int freq, int dir) | |
1217 | { | |
1218 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1219 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
f1c0a02f MB |
1220 | |
1221 | wm8903->sysclk = freq; | |
1222 | ||
1223 | return 0; | |
1224 | } | |
1225 | ||
1226 | static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1227 | unsigned int fmt) | |
1228 | { | |
1229 | struct snd_soc_codec *codec = codec_dai->codec; | |
8d50e447 | 1230 | u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); |
f1c0a02f MB |
1231 | |
1232 | aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | | |
1233 | WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); | |
1234 | ||
1235 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1236 | case SND_SOC_DAIFMT_CBS_CFS: | |
1237 | break; | |
1238 | case SND_SOC_DAIFMT_CBS_CFM: | |
1239 | aif1 |= WM8903_LRCLK_DIR; | |
1240 | break; | |
1241 | case SND_SOC_DAIFMT_CBM_CFM: | |
1242 | aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; | |
1243 | break; | |
1244 | case SND_SOC_DAIFMT_CBM_CFS: | |
1245 | aif1 |= WM8903_BCLK_DIR; | |
1246 | break; | |
1247 | default: | |
1248 | return -EINVAL; | |
1249 | } | |
1250 | ||
1251 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1252 | case SND_SOC_DAIFMT_DSP_A: | |
1253 | aif1 |= 0x3; | |
1254 | break; | |
1255 | case SND_SOC_DAIFMT_DSP_B: | |
1256 | aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; | |
1257 | break; | |
1258 | case SND_SOC_DAIFMT_I2S: | |
1259 | aif1 |= 0x2; | |
1260 | break; | |
1261 | case SND_SOC_DAIFMT_RIGHT_J: | |
1262 | aif1 |= 0x1; | |
1263 | break; | |
1264 | case SND_SOC_DAIFMT_LEFT_J: | |
1265 | break; | |
1266 | default: | |
1267 | return -EINVAL; | |
1268 | } | |
1269 | ||
1270 | /* Clock inversion */ | |
1271 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1272 | case SND_SOC_DAIFMT_DSP_A: | |
1273 | case SND_SOC_DAIFMT_DSP_B: | |
1274 | /* frame inversion not valid for DSP modes */ | |
1275 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1276 | case SND_SOC_DAIFMT_NB_NF: | |
1277 | break; | |
1278 | case SND_SOC_DAIFMT_IB_NF: | |
1279 | aif1 |= WM8903_AIF_BCLK_INV; | |
1280 | break; | |
1281 | default: | |
1282 | return -EINVAL; | |
1283 | } | |
1284 | break; | |
1285 | case SND_SOC_DAIFMT_I2S: | |
1286 | case SND_SOC_DAIFMT_RIGHT_J: | |
1287 | case SND_SOC_DAIFMT_LEFT_J: | |
1288 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1289 | case SND_SOC_DAIFMT_NB_NF: | |
1290 | break; | |
1291 | case SND_SOC_DAIFMT_IB_IF: | |
1292 | aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; | |
1293 | break; | |
1294 | case SND_SOC_DAIFMT_IB_NF: | |
1295 | aif1 |= WM8903_AIF_BCLK_INV; | |
1296 | break; | |
1297 | case SND_SOC_DAIFMT_NB_IF: | |
1298 | aif1 |= WM8903_AIF_LRCLK_INV; | |
1299 | break; | |
1300 | default: | |
1301 | return -EINVAL; | |
1302 | } | |
1303 | break; | |
1304 | default: | |
1305 | return -EINVAL; | |
1306 | } | |
1307 | ||
8d50e447 | 1308 | snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); |
f1c0a02f MB |
1309 | |
1310 | return 0; | |
1311 | } | |
1312 | ||
1313 | static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
1314 | { | |
1315 | struct snd_soc_codec *codec = codec_dai->codec; | |
1316 | u16 reg; | |
1317 | ||
8d50e447 | 1318 | reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); |
f1c0a02f MB |
1319 | |
1320 | if (mute) | |
1321 | reg |= WM8903_DAC_MUTE; | |
1322 | else | |
1323 | reg &= ~WM8903_DAC_MUTE; | |
1324 | ||
8d50e447 | 1325 | snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg); |
f1c0a02f MB |
1326 | |
1327 | return 0; | |
1328 | } | |
1329 | ||
1330 | /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended | |
1331 | * for optimal performance so we list the lower rates first and match | |
1332 | * on the last match we find. */ | |
1333 | static struct { | |
1334 | int div; | |
1335 | int rate; | |
1336 | int mode; | |
1337 | int mclk_div; | |
1338 | } clk_sys_ratios[] = { | |
1339 | { 64, 0x0, 0x0, 1 }, | |
1340 | { 68, 0x0, 0x1, 1 }, | |
1341 | { 125, 0x0, 0x2, 1 }, | |
1342 | { 128, 0x1, 0x0, 1 }, | |
1343 | { 136, 0x1, 0x1, 1 }, | |
1344 | { 192, 0x2, 0x0, 1 }, | |
1345 | { 204, 0x2, 0x1, 1 }, | |
1346 | ||
1347 | { 64, 0x0, 0x0, 2 }, | |
1348 | { 68, 0x0, 0x1, 2 }, | |
1349 | { 125, 0x0, 0x2, 2 }, | |
1350 | { 128, 0x1, 0x0, 2 }, | |
1351 | { 136, 0x1, 0x1, 2 }, | |
1352 | { 192, 0x2, 0x0, 2 }, | |
1353 | { 204, 0x2, 0x1, 2 }, | |
1354 | ||
1355 | { 250, 0x2, 0x2, 1 }, | |
1356 | { 256, 0x3, 0x0, 1 }, | |
1357 | { 272, 0x3, 0x1, 1 }, | |
1358 | { 384, 0x4, 0x0, 1 }, | |
1359 | { 408, 0x4, 0x1, 1 }, | |
1360 | { 375, 0x4, 0x2, 1 }, | |
1361 | { 512, 0x5, 0x0, 1 }, | |
1362 | { 544, 0x5, 0x1, 1 }, | |
1363 | { 500, 0x5, 0x2, 1 }, | |
1364 | { 768, 0x6, 0x0, 1 }, | |
1365 | { 816, 0x6, 0x1, 1 }, | |
1366 | { 750, 0x6, 0x2, 1 }, | |
1367 | { 1024, 0x7, 0x0, 1 }, | |
1368 | { 1088, 0x7, 0x1, 1 }, | |
1369 | { 1000, 0x7, 0x2, 1 }, | |
1370 | { 1408, 0x8, 0x0, 1 }, | |
1371 | { 1496, 0x8, 0x1, 1 }, | |
1372 | { 1536, 0x9, 0x0, 1 }, | |
1373 | { 1632, 0x9, 0x1, 1 }, | |
1374 | { 1500, 0x9, 0x2, 1 }, | |
1375 | ||
1376 | { 250, 0x2, 0x2, 2 }, | |
1377 | { 256, 0x3, 0x0, 2 }, | |
1378 | { 272, 0x3, 0x1, 2 }, | |
1379 | { 384, 0x4, 0x0, 2 }, | |
1380 | { 408, 0x4, 0x1, 2 }, | |
1381 | { 375, 0x4, 0x2, 2 }, | |
1382 | { 512, 0x5, 0x0, 2 }, | |
1383 | { 544, 0x5, 0x1, 2 }, | |
1384 | { 500, 0x5, 0x2, 2 }, | |
1385 | { 768, 0x6, 0x0, 2 }, | |
1386 | { 816, 0x6, 0x1, 2 }, | |
1387 | { 750, 0x6, 0x2, 2 }, | |
1388 | { 1024, 0x7, 0x0, 2 }, | |
1389 | { 1088, 0x7, 0x1, 2 }, | |
1390 | { 1000, 0x7, 0x2, 2 }, | |
1391 | { 1408, 0x8, 0x0, 2 }, | |
1392 | { 1496, 0x8, 0x1, 2 }, | |
1393 | { 1536, 0x9, 0x0, 2 }, | |
1394 | { 1632, 0x9, 0x1, 2 }, | |
1395 | { 1500, 0x9, 0x2, 2 }, | |
1396 | }; | |
1397 | ||
1398 | /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ | |
1399 | static struct { | |
1400 | int ratio; | |
1401 | int div; | |
1402 | } bclk_divs[] = { | |
1403 | { 10, 0 }, | |
f1c0a02f MB |
1404 | { 20, 2 }, |
1405 | { 30, 3 }, | |
1406 | { 40, 4 }, | |
1407 | { 50, 5 }, | |
f1c0a02f MB |
1408 | { 60, 7 }, |
1409 | { 80, 8 }, | |
1410 | { 100, 9 }, | |
f1c0a02f MB |
1411 | { 120, 11 }, |
1412 | { 160, 12 }, | |
1413 | { 200, 13 }, | |
1414 | { 220, 14 }, | |
1415 | { 240, 15 }, | |
f1c0a02f MB |
1416 | { 300, 17 }, |
1417 | { 320, 18 }, | |
1418 | { 440, 19 }, | |
1419 | { 480, 20 }, | |
1420 | }; | |
1421 | ||
1422 | /* Sample rates for DSP */ | |
1423 | static struct { | |
1424 | int rate; | |
1425 | int value; | |
1426 | } sample_rates[] = { | |
1427 | { 8000, 0 }, | |
1428 | { 11025, 1 }, | |
1429 | { 12000, 2 }, | |
1430 | { 16000, 3 }, | |
1431 | { 22050, 4 }, | |
1432 | { 24000, 5 }, | |
1433 | { 32000, 6 }, | |
1434 | { 44100, 7 }, | |
1435 | { 48000, 8 }, | |
1436 | { 88200, 9 }, | |
1437 | { 96000, 10 }, | |
1438 | { 0, 0 }, | |
1439 | }; | |
1440 | ||
f1c0a02f | 1441 | static int wm8903_hw_params(struct snd_pcm_substream *substream, |
dee89c4d MB |
1442 | struct snd_pcm_hw_params *params, |
1443 | struct snd_soc_dai *dai) | |
f1c0a02f MB |
1444 | { |
1445 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 1446 | struct snd_soc_codec *codec =rtd->codec; |
b2c812e2 | 1447 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
f1c0a02f MB |
1448 | int fs = params_rate(params); |
1449 | int bclk; | |
1450 | int bclk_div; | |
1451 | int i; | |
1452 | int dsp_config; | |
1453 | int clk_config; | |
1454 | int best_val; | |
1455 | int cur_val; | |
1456 | int clk_sys; | |
1457 | ||
8d50e447 MB |
1458 | u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); |
1459 | u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2); | |
1460 | u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3); | |
1461 | u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0); | |
1462 | u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); | |
1463 | u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); | |
f1c0a02f | 1464 | |
9e79261f MB |
1465 | /* Enable sloping stopband filter for low sample rates */ |
1466 | if (fs <= 24000) | |
1467 | dac_digital1 |= WM8903_DAC_SB_FILT; | |
1468 | else | |
1469 | dac_digital1 &= ~WM8903_DAC_SB_FILT; | |
1470 | ||
f1c0a02f MB |
1471 | /* Configure sample rate logic for DSP - choose nearest rate */ |
1472 | dsp_config = 0; | |
1473 | best_val = abs(sample_rates[dsp_config].rate - fs); | |
1474 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1475 | cur_val = abs(sample_rates[i].rate - fs); | |
1476 | if (cur_val <= best_val) { | |
1477 | dsp_config = i; | |
1478 | best_val = cur_val; | |
1479 | } | |
1480 | } | |
1481 | ||
f0fba2ad | 1482 | dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); |
f1c0a02f MB |
1483 | clock1 &= ~WM8903_SAMPLE_RATE_MASK; |
1484 | clock1 |= sample_rates[dsp_config].value; | |
1485 | ||
1486 | aif1 &= ~WM8903_AIF_WL_MASK; | |
1487 | bclk = 2 * fs; | |
1488 | switch (params_format(params)) { | |
1489 | case SNDRV_PCM_FORMAT_S16_LE: | |
1490 | bclk *= 16; | |
1491 | break; | |
1492 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1493 | bclk *= 20; | |
1494 | aif1 |= 0x4; | |
1495 | break; | |
1496 | case SNDRV_PCM_FORMAT_S24_LE: | |
1497 | bclk *= 24; | |
1498 | aif1 |= 0x8; | |
1499 | break; | |
1500 | case SNDRV_PCM_FORMAT_S32_LE: | |
1501 | bclk *= 32; | |
1502 | aif1 |= 0xc; | |
1503 | break; | |
1504 | default: | |
1505 | return -EINVAL; | |
1506 | } | |
1507 | ||
f0fba2ad | 1508 | dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n", |
f1c0a02f MB |
1509 | wm8903->sysclk, fs); |
1510 | ||
1511 | /* We may not have an MCLK which allows us to generate exactly | |
1512 | * the clock we want, particularly with USB derived inputs, so | |
1513 | * approximate. | |
1514 | */ | |
1515 | clk_config = 0; | |
1516 | best_val = abs((wm8903->sysclk / | |
1517 | (clk_sys_ratios[0].mclk_div * | |
1518 | clk_sys_ratios[0].div)) - fs); | |
1519 | for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { | |
1520 | cur_val = abs((wm8903->sysclk / | |
1521 | (clk_sys_ratios[i].mclk_div * | |
1522 | clk_sys_ratios[i].div)) - fs); | |
1523 | ||
1524 | if (cur_val <= best_val) { | |
1525 | clk_config = i; | |
1526 | best_val = cur_val; | |
1527 | } | |
1528 | } | |
1529 | ||
1530 | if (clk_sys_ratios[clk_config].mclk_div == 2) { | |
1531 | clock0 |= WM8903_MCLKDIV2; | |
1532 | clk_sys = wm8903->sysclk / 2; | |
1533 | } else { | |
1534 | clock0 &= ~WM8903_MCLKDIV2; | |
1535 | clk_sys = wm8903->sysclk; | |
1536 | } | |
1537 | ||
1538 | clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | | |
1539 | WM8903_CLK_SYS_MODE_MASK); | |
1540 | clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; | |
1541 | clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; | |
1542 | ||
f0fba2ad | 1543 | dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", |
f1c0a02f MB |
1544 | clk_sys_ratios[clk_config].rate, |
1545 | clk_sys_ratios[clk_config].mode, | |
1546 | clk_sys_ratios[clk_config].div); | |
1547 | ||
f0fba2ad | 1548 | dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys); |
f1c0a02f MB |
1549 | |
1550 | /* We may not get quite the right frequency if using | |
1551 | * approximate clocks so look for the closest match that is | |
1552 | * higher than the target (we need to ensure that there enough | |
1553 | * BCLKs to clock out the samples). | |
1554 | */ | |
1555 | bclk_div = 0; | |
1556 | best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; | |
1557 | i = 1; | |
1558 | while (i < ARRAY_SIZE(bclk_divs)) { | |
1559 | cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; | |
1560 | if (cur_val < 0) /* BCLK table is sorted */ | |
1561 | break; | |
1562 | bclk_div = i; | |
1563 | best_val = cur_val; | |
1564 | i++; | |
1565 | } | |
1566 | ||
1567 | aif2 &= ~WM8903_BCLK_DIV_MASK; | |
1568 | aif3 &= ~WM8903_LRCLK_RATE_MASK; | |
1569 | ||
f0fba2ad | 1570 | dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", |
f1c0a02f MB |
1571 | bclk_divs[bclk_div].ratio / 10, bclk, |
1572 | (clk_sys * 10) / bclk_divs[bclk_div].ratio); | |
1573 | ||
1574 | aif2 |= bclk_divs[bclk_div].div; | |
1575 | aif3 |= bclk / fs; | |
1576 | ||
69fff9bb MB |
1577 | wm8903->fs = params_rate(params); |
1578 | wm8903_set_deemph(codec); | |
1579 | ||
8d50e447 MB |
1580 | snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); |
1581 | snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); | |
1582 | snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); | |
1583 | snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); | |
1584 | snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); | |
1585 | snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); | |
f1c0a02f MB |
1586 | |
1587 | return 0; | |
1588 | } | |
1589 | ||
7245387e MB |
1590 | /** |
1591 | * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ | |
1592 | * | |
1593 | * @codec: WM8903 codec | |
1594 | * @jack: jack to report detection events on | |
1595 | * @det: value to report for presence detection | |
1596 | * @shrt: value to report for short detection | |
1597 | * | |
1598 | * Enable microphone detection via IRQ on the WM8903. If GPIOs are | |
1599 | * being used to bring out signals to the processor then only platform | |
1600 | * data configuration is needed for WM8903 and processor GPIOs should | |
1601 | * be configured using snd_soc_jack_add_gpios() instead. | |
1602 | * | |
1603 | * The current threasholds for detection should be configured using | |
1604 | * micdet_cfg in the platform data. Using this function will force on | |
1605 | * the microphone bias for the device. | |
1606 | */ | |
1607 | int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, | |
1608 | int det, int shrt) | |
1609 | { | |
b2c812e2 | 1610 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
69266866 | 1611 | int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; |
7245387e MB |
1612 | |
1613 | dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n", | |
1614 | det, shrt); | |
1615 | ||
1616 | /* Store the configuration */ | |
1617 | wm8903->mic_jack = jack; | |
1618 | wm8903->mic_det = det; | |
1619 | wm8903->mic_short = shrt; | |
1620 | ||
1621 | /* Enable interrupts we've got a report configured for */ | |
1622 | if (det) | |
1623 | irq_mask &= ~WM8903_MICDET_EINT; | |
1624 | if (shrt) | |
1625 | irq_mask &= ~WM8903_MICSHRT_EINT; | |
1626 | ||
1627 | snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, | |
1628 | WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, | |
1629 | irq_mask); | |
1630 | ||
3088e3b4 | 1631 | if (det || shrt) { |
69266866 MB |
1632 | /* Enable mic detection, this may not have been set through |
1633 | * platform data (eg, if the defaults are OK). */ | |
1634 | snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, | |
1635 | WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); | |
1636 | snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, | |
1637 | WM8903_MICDET_ENA, WM8903_MICDET_ENA); | |
1638 | } else { | |
1639 | snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, | |
1640 | WM8903_MICDET_ENA, 0); | |
1641 | } | |
7245387e MB |
1642 | |
1643 | return 0; | |
1644 | } | |
1645 | EXPORT_SYMBOL_GPL(wm8903_mic_detect); | |
1646 | ||
8abd16a6 MB |
1647 | static irqreturn_t wm8903_irq(int irq, void *data) |
1648 | { | |
f0fba2ad LG |
1649 | struct snd_soc_codec *codec = data; |
1650 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
7245387e MB |
1651 | int mic_report; |
1652 | int int_pol; | |
1653 | int int_val = 0; | |
1654 | int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK); | |
8abd16a6 | 1655 | |
7245387e | 1656 | int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask; |
8abd16a6 | 1657 | |
7245387e | 1658 | if (int_val & WM8903_WSEQ_BUSY_EINT) { |
b4d06f45 | 1659 | dev_warn(codec->dev, "Write sequencer done\n"); |
8abd16a6 MB |
1660 | } |
1661 | ||
7245387e MB |
1662 | /* |
1663 | * The rest is microphone jack detection. We need to manually | |
1664 | * invert the polarity of the interrupt after each event - to | |
1665 | * simplify the code keep track of the last state we reported | |
1666 | * and just invert the relevant bits in both the report and | |
1667 | * the polarity register. | |
1668 | */ | |
1669 | mic_report = wm8903->mic_last_report; | |
1670 | int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); | |
1671 | ||
1435b940 | 1672 | #ifndef CONFIG_SND_SOC_WM8903_MODULE |
2bbb5d66 MB |
1673 | if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) |
1674 | trace_snd_soc_jack_irq(dev_name(codec->dev)); | |
1435b940 | 1675 | #endif |
2bbb5d66 | 1676 | |
7245387e MB |
1677 | if (int_val & WM8903_MICSHRT_EINT) { |
1678 | dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); | |
1679 | ||
1680 | mic_report ^= wm8903->mic_short; | |
1681 | int_pol ^= WM8903_MICSHRT_INV; | |
1682 | } | |
1683 | ||
1684 | if (int_val & WM8903_MICDET_EINT) { | |
1685 | dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol); | |
1686 | ||
1687 | mic_report ^= wm8903->mic_det; | |
1688 | int_pol ^= WM8903_MICDET_INV; | |
1689 | ||
1690 | msleep(wm8903->mic_delay); | |
1691 | } | |
1692 | ||
1693 | snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1, | |
1694 | WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); | |
1695 | ||
1696 | snd_soc_jack_report(wm8903->mic_jack, mic_report, | |
1697 | wm8903->mic_short | wm8903->mic_det); | |
1698 | ||
1699 | wm8903->mic_last_report = mic_report; | |
1700 | ||
8abd16a6 MB |
1701 | return IRQ_HANDLED; |
1702 | } | |
1703 | ||
f1c0a02f MB |
1704 | #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ |
1705 | SNDRV_PCM_RATE_11025 | \ | |
1706 | SNDRV_PCM_RATE_16000 | \ | |
1707 | SNDRV_PCM_RATE_22050 | \ | |
1708 | SNDRV_PCM_RATE_32000 | \ | |
1709 | SNDRV_PCM_RATE_44100 | \ | |
1710 | SNDRV_PCM_RATE_48000 | \ | |
1711 | SNDRV_PCM_RATE_88200 | \ | |
1712 | SNDRV_PCM_RATE_96000) | |
1713 | ||
1714 | #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ | |
1715 | SNDRV_PCM_RATE_11025 | \ | |
1716 | SNDRV_PCM_RATE_16000 | \ | |
1717 | SNDRV_PCM_RATE_22050 | \ | |
1718 | SNDRV_PCM_RATE_32000 | \ | |
1719 | SNDRV_PCM_RATE_44100 | \ | |
1720 | SNDRV_PCM_RATE_48000) | |
1721 | ||
1722 | #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
1723 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1724 | SNDRV_PCM_FMTBIT_S24_LE) | |
1725 | ||
6335d055 | 1726 | static struct snd_soc_dai_ops wm8903_dai_ops = { |
6335d055 EM |
1727 | .hw_params = wm8903_hw_params, |
1728 | .digital_mute = wm8903_digital_mute, | |
1729 | .set_fmt = wm8903_set_dai_fmt, | |
1730 | .set_sysclk = wm8903_set_dai_sysclk, | |
1731 | }; | |
1732 | ||
f0fba2ad LG |
1733 | static struct snd_soc_dai_driver wm8903_dai = { |
1734 | .name = "wm8903-hifi", | |
f1c0a02f MB |
1735 | .playback = { |
1736 | .stream_name = "Playback", | |
1737 | .channels_min = 2, | |
1738 | .channels_max = 2, | |
1739 | .rates = WM8903_PLAYBACK_RATES, | |
1740 | .formats = WM8903_FORMATS, | |
1741 | }, | |
1742 | .capture = { | |
1743 | .stream_name = "Capture", | |
1744 | .channels_min = 2, | |
1745 | .channels_max = 2, | |
1746 | .rates = WM8903_CAPTURE_RATES, | |
1747 | .formats = WM8903_FORMATS, | |
1748 | }, | |
6335d055 | 1749 | .ops = &wm8903_dai_ops, |
0d960e88 | 1750 | .symmetric_rates = 1, |
f1c0a02f | 1751 | }; |
f1c0a02f | 1752 | |
f0fba2ad | 1753 | static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state) |
f1c0a02f | 1754 | { |
f1c0a02f MB |
1755 | wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); |
1756 | ||
1757 | return 0; | |
1758 | } | |
1759 | ||
f0fba2ad | 1760 | static int wm8903_resume(struct snd_soc_codec *codec) |
f1c0a02f | 1761 | { |
f1c0a02f MB |
1762 | int i; |
1763 | u16 *reg_cache = codec->reg_cache; | |
40aa7030 | 1764 | u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults), |
f1c0a02f MB |
1765 | GFP_KERNEL); |
1766 | ||
1767 | /* Bring the codec back up to standby first to minimise pop/clicks */ | |
1768 | wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
f1c0a02f MB |
1769 | |
1770 | /* Sync back everything else */ | |
1771 | if (tmp_cache) { | |
1772 | for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++) | |
1773 | if (tmp_cache[i] != reg_cache[i]) | |
8d50e447 | 1774 | snd_soc_write(codec, i, tmp_cache[i]); |
40aa7030 | 1775 | kfree(tmp_cache); |
f1c0a02f | 1776 | } else { |
f0fba2ad | 1777 | dev_err(codec->dev, "Failed to allocate temporary cache\n"); |
f1c0a02f MB |
1778 | } |
1779 | ||
1780 | return 0; | |
1781 | } | |
1782 | ||
7cfe5617 SW |
1783 | #ifdef CONFIG_GPIOLIB |
1784 | static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip) | |
1785 | { | |
1786 | return container_of(chip, struct wm8903_priv, gpio_chip); | |
1787 | } | |
1788 | ||
1789 | static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset) | |
1790 | { | |
1791 | if (offset >= WM8903_NUM_GPIO) | |
1792 | return -EINVAL; | |
1793 | ||
1794 | return 0; | |
1795 | } | |
1796 | ||
1797 | static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset) | |
1798 | { | |
1799 | struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); | |
1800 | struct snd_soc_codec *codec = wm8903->codec; | |
1801 | unsigned int mask, val; | |
1802 | ||
1803 | mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK; | |
1804 | val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) | | |
1805 | WM8903_GP1_DIR; | |
1806 | ||
1807 | return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset, | |
1808 | mask, val); | |
1809 | } | |
1810 | ||
1811 | static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset) | |
1812 | { | |
1813 | struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); | |
1814 | struct snd_soc_codec *codec = wm8903->codec; | |
1815 | int reg; | |
1816 | ||
1817 | reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset); | |
1818 | ||
1819 | return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT; | |
1820 | } | |
1821 | ||
1822 | static int wm8903_gpio_direction_out(struct gpio_chip *chip, | |
1823 | unsigned offset, int value) | |
1824 | { | |
1825 | struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); | |
1826 | struct snd_soc_codec *codec = wm8903->codec; | |
1827 | unsigned int mask, val; | |
1828 | ||
1829 | mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK; | |
1830 | val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) | | |
1831 | (value << WM8903_GP2_LVL_SHIFT); | |
1832 | ||
1833 | return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset, | |
1834 | mask, val); | |
1835 | } | |
1836 | ||
1837 | static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1838 | { | |
1839 | struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); | |
1840 | struct snd_soc_codec *codec = wm8903->codec; | |
1841 | ||
1842 | snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset, | |
c8059930 MB |
1843 | WM8903_GP1_LVL_MASK, |
1844 | !!value << WM8903_GP1_LVL_SHIFT); | |
7cfe5617 SW |
1845 | } |
1846 | ||
1847 | static struct gpio_chip wm8903_template_chip = { | |
1848 | .label = "wm8903", | |
1849 | .owner = THIS_MODULE, | |
1850 | .request = wm8903_gpio_request, | |
1851 | .direction_input = wm8903_gpio_direction_in, | |
1852 | .get = wm8903_gpio_get, | |
1853 | .direction_output = wm8903_gpio_direction_out, | |
1854 | .set = wm8903_gpio_set, | |
1855 | .can_sleep = 1, | |
1856 | }; | |
1857 | ||
1858 | static void wm8903_init_gpio(struct snd_soc_codec *codec) | |
1859 | { | |
1860 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
1861 | struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev); | |
1862 | int ret; | |
1863 | ||
1864 | wm8903->gpio_chip = wm8903_template_chip; | |
1865 | wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO; | |
1866 | wm8903->gpio_chip.dev = codec->dev; | |
1867 | ||
1868 | if (pdata && pdata->gpio_base) | |
1869 | wm8903->gpio_chip.base = pdata->gpio_base; | |
1870 | else | |
1871 | wm8903->gpio_chip.base = -1; | |
1872 | ||
1873 | ret = gpiochip_add(&wm8903->gpio_chip); | |
1874 | if (ret != 0) | |
1875 | dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); | |
1876 | } | |
1877 | ||
1878 | static void wm8903_free_gpio(struct snd_soc_codec *codec) | |
1879 | { | |
1880 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
1881 | int ret; | |
1882 | ||
1883 | ret = gpiochip_remove(&wm8903->gpio_chip); | |
1884 | if (ret != 0) | |
1885 | dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); | |
1886 | } | |
1887 | #else | |
1888 | static void wm8903_init_gpio(struct snd_soc_codec *codec) | |
1889 | { | |
1890 | } | |
1891 | ||
1892 | static void wm8903_free_gpio(struct snd_soc_codec *codec) | |
1893 | { | |
1894 | } | |
1895 | #endif | |
1896 | ||
f0fba2ad | 1897 | static int wm8903_probe(struct snd_soc_codec *codec) |
f1c0a02f | 1898 | { |
f0fba2ad LG |
1899 | struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev); |
1900 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
73b34ead | 1901 | int ret, i; |
8abd16a6 | 1902 | int trigger, irq_pol; |
f1c0a02f MB |
1903 | u16 val; |
1904 | ||
7cfe5617 | 1905 | wm8903->codec = codec; |
d58d5d55 | 1906 | |
8d50e447 MB |
1907 | ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); |
1908 | if (ret != 0) { | |
f0fba2ad LG |
1909 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); |
1910 | return ret; | |
8d50e447 MB |
1911 | } |
1912 | ||
1913 | val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID); | |
d58d5d55 | 1914 | if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) { |
f0fba2ad | 1915 | dev_err(codec->dev, |
d58d5d55 MB |
1916 | "Device with ID register %x is not a WM8903\n", val); |
1917 | return -ENODEV; | |
f1c0a02f MB |
1918 | } |
1919 | ||
8d50e447 | 1920 | val = snd_soc_read(codec, WM8903_REVISION_NUMBER); |
1d8d62d6 MB |
1921 | dev_info(codec->dev, "WM8903 revision %c\n", |
1922 | (val & WM8903_CHIP_REV_MASK) + 'A'); | |
f1c0a02f MB |
1923 | |
1924 | wm8903_reset(codec); | |
1925 | ||
37f88e84 | 1926 | /* Set up GPIOs and microphone detection */ |
73b34ead | 1927 | if (pdata) { |
905f6952 MB |
1928 | bool mic_gpio = false; |
1929 | ||
73b34ead | 1930 | for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { |
7cfe5617 | 1931 | if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG) |
73b34ead MB |
1932 | continue; |
1933 | ||
1934 | snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i, | |
1935 | pdata->gpio_cfg[i] & 0xffff); | |
905f6952 MB |
1936 | |
1937 | val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK) | |
1938 | >> WM8903_GP1_FN_SHIFT; | |
1939 | ||
1940 | switch (val) { | |
1941 | case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT: | |
1942 | case WM8903_GPn_FN_MICBIAS_SHORT_DETECT: | |
1943 | mic_gpio = true; | |
1944 | break; | |
1945 | default: | |
1946 | break; | |
1947 | } | |
73b34ead | 1948 | } |
37f88e84 MB |
1949 | |
1950 | snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, | |
1951 | pdata->micdet_cfg); | |
1952 | ||
1953 | /* Microphone detection needs the WSEQ clock */ | |
1954 | if (pdata->micdet_cfg) | |
1955 | snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, | |
1956 | WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); | |
1957 | ||
905f6952 MB |
1958 | /* If microphone detection is enabled by pdata but |
1959 | * detected via IRQ then interrupts can be lost before | |
1960 | * the machine driver has set up microphone detection | |
1961 | * IRQs as the IRQs are clear on read. The detection | |
1962 | * will be enabled when the machine driver configures. | |
1963 | */ | |
1964 | WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA)); | |
1965 | ||
37f88e84 | 1966 | wm8903->mic_delay = pdata->micdet_delay; |
73b34ead | 1967 | } |
8abd16a6 | 1968 | |
f0fba2ad | 1969 | if (wm8903->irq) { |
8abd16a6 MB |
1970 | if (pdata && pdata->irq_active_low) { |
1971 | trigger = IRQF_TRIGGER_LOW; | |
1972 | irq_pol = WM8903_IRQ_POL; | |
1973 | } else { | |
1974 | trigger = IRQF_TRIGGER_HIGH; | |
1975 | irq_pol = 0; | |
1976 | } | |
1977 | ||
1978 | snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL, | |
1979 | WM8903_IRQ_POL, irq_pol); | |
1980 | ||
f0fba2ad | 1981 | ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq, |
8abd16a6 | 1982 | trigger | IRQF_ONESHOT, |
f0fba2ad | 1983 | "wm8903", codec); |
8abd16a6 | 1984 | if (ret != 0) { |
f0fba2ad | 1985 | dev_err(codec->dev, "Failed to request IRQ: %d\n", |
8abd16a6 | 1986 | ret); |
f0fba2ad | 1987 | return ret; |
8abd16a6 MB |
1988 | } |
1989 | ||
1990 | /* Enable write sequencer interrupts */ | |
1991 | snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, | |
1992 | WM8903_IM_WSEQ_BUSY_EINT, 0); | |
1993 | } | |
73b34ead | 1994 | |
f1c0a02f MB |
1995 | /* power on device */ |
1996 | wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1997 | ||
1998 | /* Latch volume update bits */ | |
8d50e447 | 1999 | val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); |
f1c0a02f | 2000 | val |= WM8903_ADCVU; |
8d50e447 MB |
2001 | snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); |
2002 | snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); | |
f1c0a02f | 2003 | |
8d50e447 | 2004 | val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); |
f1c0a02f | 2005 | val |= WM8903_DACVU; |
8d50e447 MB |
2006 | snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); |
2007 | snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); | |
f1c0a02f | 2008 | |
8d50e447 | 2009 | val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT); |
f1c0a02f | 2010 | val |= WM8903_HPOUTVU; |
8d50e447 MB |
2011 | snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); |
2012 | snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); | |
f1c0a02f | 2013 | |
8d50e447 | 2014 | val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT); |
f1c0a02f | 2015 | val |= WM8903_LINEOUTVU; |
8d50e447 MB |
2016 | snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); |
2017 | snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); | |
f1c0a02f | 2018 | |
8d50e447 | 2019 | val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT); |
f1c0a02f | 2020 | val |= WM8903_SPKVU; |
8d50e447 MB |
2021 | snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); |
2022 | snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); | |
f1c0a02f MB |
2023 | |
2024 | /* Enable DAC soft mute by default */ | |
e12adab0 MB |
2025 | snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1, |
2026 | WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE, | |
2027 | WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE); | |
f1c0a02f | 2028 | |
f0fba2ad LG |
2029 | snd_soc_add_controls(codec, wm8903_snd_controls, |
2030 | ARRAY_SIZE(wm8903_snd_controls)); | |
2031 | wm8903_add_widgets(codec); | |
f1c0a02f | 2032 | |
7cfe5617 SW |
2033 | wm8903_init_gpio(codec); |
2034 | ||
f1c0a02f MB |
2035 | return ret; |
2036 | } | |
2037 | ||
f0fba2ad LG |
2038 | /* power down chip */ |
2039 | static int wm8903_remove(struct snd_soc_codec *codec) | |
f1c0a02f | 2040 | { |
7cfe5617 | 2041 | wm8903_free_gpio(codec); |
f0fba2ad LG |
2042 | wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); |
2043 | return 0; | |
2044 | } | |
f1c0a02f | 2045 | |
f0fba2ad LG |
2046 | static struct snd_soc_codec_driver soc_codec_dev_wm8903 = { |
2047 | .probe = wm8903_probe, | |
2048 | .remove = wm8903_remove, | |
2049 | .suspend = wm8903_suspend, | |
2050 | .resume = wm8903_resume, | |
2051 | .set_bias_level = wm8903_set_bias_level, | |
2052 | .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults), | |
2053 | .reg_word_size = sizeof(u16), | |
2054 | .reg_cache_default = wm8903_reg_defaults, | |
2055 | .volatile_register = wm8903_volatile_register, | |
c5b6a9fe | 2056 | .seq_notifier = wm8903_seq_notifier, |
f0fba2ad | 2057 | }; |
f1c0a02f | 2058 | |
f0fba2ad LG |
2059 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
2060 | static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, | |
2061 | const struct i2c_device_id *id) | |
2062 | { | |
2063 | struct wm8903_priv *wm8903; | |
2064 | int ret; | |
f1c0a02f | 2065 | |
f0fba2ad LG |
2066 | wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL); |
2067 | if (wm8903 == NULL) | |
2068 | return -ENOMEM; | |
8abd16a6 | 2069 | |
f0fba2ad | 2070 | i2c_set_clientdata(i2c, wm8903); |
f0fba2ad | 2071 | wm8903->irq = i2c->irq; |
d58d5d55 | 2072 | |
f0fba2ad LG |
2073 | ret = snd_soc_register_codec(&i2c->dev, |
2074 | &soc_codec_dev_wm8903, &wm8903_dai, 1); | |
2075 | if (ret < 0) | |
2076 | kfree(wm8903); | |
2077 | return ret; | |
2078 | } | |
f1c0a02f | 2079 | |
f0fba2ad LG |
2080 | static __devexit int wm8903_i2c_remove(struct i2c_client *client) |
2081 | { | |
2082 | snd_soc_unregister_codec(&client->dev); | |
2083 | kfree(i2c_get_clientdata(client)); | |
f1c0a02f MB |
2084 | return 0; |
2085 | } | |
2086 | ||
f1c0a02f | 2087 | static const struct i2c_device_id wm8903_i2c_id[] = { |
f0fba2ad LG |
2088 | { "wm8903", 0 }, |
2089 | { } | |
f1c0a02f MB |
2090 | }; |
2091 | MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); | |
2092 | ||
2093 | static struct i2c_driver wm8903_i2c_driver = { | |
2094 | .driver = { | |
4b592c91 | 2095 | .name = "wm8903", |
f1c0a02f MB |
2096 | .owner = THIS_MODULE, |
2097 | }, | |
f0fba2ad LG |
2098 | .probe = wm8903_i2c_probe, |
2099 | .remove = __devexit_p(wm8903_i2c_remove), | |
f1c0a02f MB |
2100 | .id_table = wm8903_i2c_id, |
2101 | }; | |
f0fba2ad | 2102 | #endif |
f1c0a02f | 2103 | |
f0fba2ad | 2104 | static int __init wm8903_modinit(void) |
f1c0a02f | 2105 | { |
f1c0a02f | 2106 | int ret = 0; |
f0fba2ad LG |
2107 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
2108 | ret = i2c_add_driver(&wm8903_i2c_driver); | |
2109 | if (ret != 0) { | |
2110 | printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n", | |
2111 | ret); | |
f1c0a02f | 2112 | } |
f0fba2ad | 2113 | #endif |
f1c0a02f | 2114 | return ret; |
64089b84 MB |
2115 | } |
2116 | module_init(wm8903_modinit); | |
2117 | ||
2118 | static void __exit wm8903_exit(void) | |
2119 | { | |
f0fba2ad | 2120 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
d58d5d55 | 2121 | i2c_del_driver(&wm8903_i2c_driver); |
f0fba2ad | 2122 | #endif |
64089b84 MB |
2123 | } |
2124 | module_exit(wm8903_exit); | |
2125 | ||
f1c0a02f MB |
2126 | MODULE_DESCRIPTION("ASoC WM8903 driver"); |
2127 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); | |
2128 | MODULE_LICENSE("GPL"); |