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f1c0a02f MB |
1 | /* |
2 | * wm8903.c -- WM8903 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2008 Wolfson Microelectronics | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * TODO: | |
13 | * - TDM mode configuration. | |
14 | * - Mic detect. | |
15 | * - Digital microphone support. | |
16 | * - Interrupt support (mic detect and sequencer). | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/pm.h> | |
24 | #include <linux/i2c.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <sound/core.h> | |
27 | #include <sound/pcm.h> | |
28 | #include <sound/pcm_params.h> | |
29 | #include <sound/tlv.h> | |
30 | #include <sound/soc.h> | |
31 | #include <sound/soc-dapm.h> | |
32 | #include <sound/initval.h> | |
33 | ||
34 | #include "wm8903.h" | |
35 | ||
f1c0a02f MB |
36 | /* Register defaults at reset */ |
37 | static u16 wm8903_reg_defaults[] = { | |
38 | 0x8903, /* R0 - SW Reset and ID */ | |
39 | 0x0000, /* R1 - Revision Number */ | |
40 | 0x0000, /* R2 */ | |
41 | 0x0000, /* R3 */ | |
42 | 0x0018, /* R4 - Bias Control 0 */ | |
43 | 0x0000, /* R5 - VMID Control 0 */ | |
44 | 0x0000, /* R6 - Mic Bias Control 0 */ | |
45 | 0x0000, /* R7 */ | |
46 | 0x0001, /* R8 - Analogue DAC 0 */ | |
47 | 0x0000, /* R9 */ | |
48 | 0x0001, /* R10 - Analogue ADC 0 */ | |
49 | 0x0000, /* R11 */ | |
50 | 0x0000, /* R12 - Power Management 0 */ | |
51 | 0x0000, /* R13 - Power Management 1 */ | |
52 | 0x0000, /* R14 - Power Management 2 */ | |
53 | 0x0000, /* R15 - Power Management 3 */ | |
54 | 0x0000, /* R16 - Power Management 4 */ | |
55 | 0x0000, /* R17 - Power Management 5 */ | |
56 | 0x0000, /* R18 - Power Management 6 */ | |
57 | 0x0000, /* R19 */ | |
58 | 0x0400, /* R20 - Clock Rates 0 */ | |
59 | 0x0D07, /* R21 - Clock Rates 1 */ | |
60 | 0x0000, /* R22 - Clock Rates 2 */ | |
61 | 0x0000, /* R23 */ | |
62 | 0x0050, /* R24 - Audio Interface 0 */ | |
63 | 0x0242, /* R25 - Audio Interface 1 */ | |
64 | 0x0008, /* R26 - Audio Interface 2 */ | |
65 | 0x0022, /* R27 - Audio Interface 3 */ | |
66 | 0x0000, /* R28 */ | |
67 | 0x0000, /* R29 */ | |
68 | 0x00C0, /* R30 - DAC Digital Volume Left */ | |
69 | 0x00C0, /* R31 - DAC Digital Volume Right */ | |
70 | 0x0000, /* R32 - DAC Digital 0 */ | |
71 | 0x0000, /* R33 - DAC Digital 1 */ | |
72 | 0x0000, /* R34 */ | |
73 | 0x0000, /* R35 */ | |
74 | 0x00C0, /* R36 - ADC Digital Volume Left */ | |
75 | 0x00C0, /* R37 - ADC Digital Volume Right */ | |
76 | 0x0000, /* R38 - ADC Digital 0 */ | |
77 | 0x0073, /* R39 - Digital Microphone 0 */ | |
78 | 0x09BF, /* R40 - DRC 0 */ | |
79 | 0x3241, /* R41 - DRC 1 */ | |
80 | 0x0020, /* R42 - DRC 2 */ | |
81 | 0x0000, /* R43 - DRC 3 */ | |
82 | 0x0085, /* R44 - Analogue Left Input 0 */ | |
83 | 0x0085, /* R45 - Analogue Right Input 0 */ | |
84 | 0x0044, /* R46 - Analogue Left Input 1 */ | |
85 | 0x0044, /* R47 - Analogue Right Input 1 */ | |
86 | 0x0000, /* R48 */ | |
87 | 0x0000, /* R49 */ | |
88 | 0x0008, /* R50 - Analogue Left Mix 0 */ | |
89 | 0x0004, /* R51 - Analogue Right Mix 0 */ | |
90 | 0x0000, /* R52 - Analogue Spk Mix Left 0 */ | |
91 | 0x0000, /* R53 - Analogue Spk Mix Left 1 */ | |
92 | 0x0000, /* R54 - Analogue Spk Mix Right 0 */ | |
93 | 0x0000, /* R55 - Analogue Spk Mix Right 1 */ | |
94 | 0x0000, /* R56 */ | |
95 | 0x002D, /* R57 - Analogue OUT1 Left */ | |
96 | 0x002D, /* R58 - Analogue OUT1 Right */ | |
97 | 0x0039, /* R59 - Analogue OUT2 Left */ | |
98 | 0x0039, /* R60 - Analogue OUT2 Right */ | |
99 | 0x0100, /* R61 */ | |
100 | 0x0139, /* R62 - Analogue OUT3 Left */ | |
101 | 0x0139, /* R63 - Analogue OUT3 Right */ | |
102 | 0x0000, /* R64 */ | |
103 | 0x0000, /* R65 - Analogue SPK Output Control 0 */ | |
104 | 0x0000, /* R66 */ | |
105 | 0x0010, /* R67 - DC Servo 0 */ | |
106 | 0x0100, /* R68 */ | |
107 | 0x00A4, /* R69 - DC Servo 2 */ | |
108 | 0x0807, /* R70 */ | |
109 | 0x0000, /* R71 */ | |
110 | 0x0000, /* R72 */ | |
111 | 0x0000, /* R73 */ | |
112 | 0x0000, /* R74 */ | |
113 | 0x0000, /* R75 */ | |
114 | 0x0000, /* R76 */ | |
115 | 0x0000, /* R77 */ | |
116 | 0x0000, /* R78 */ | |
117 | 0x000E, /* R79 */ | |
118 | 0x0000, /* R80 */ | |
119 | 0x0000, /* R81 */ | |
120 | 0x0000, /* R82 */ | |
121 | 0x0000, /* R83 */ | |
122 | 0x0000, /* R84 */ | |
123 | 0x0000, /* R85 */ | |
124 | 0x0000, /* R86 */ | |
125 | 0x0006, /* R87 */ | |
126 | 0x0000, /* R88 */ | |
127 | 0x0000, /* R89 */ | |
128 | 0x0000, /* R90 - Analogue HP 0 */ | |
129 | 0x0060, /* R91 */ | |
130 | 0x0000, /* R92 */ | |
131 | 0x0000, /* R93 */ | |
132 | 0x0000, /* R94 - Analogue Lineout 0 */ | |
133 | 0x0060, /* R95 */ | |
134 | 0x0000, /* R96 */ | |
135 | 0x0000, /* R97 */ | |
136 | 0x0000, /* R98 - Charge Pump 0 */ | |
137 | 0x1F25, /* R99 */ | |
138 | 0x2B19, /* R100 */ | |
139 | 0x01C0, /* R101 */ | |
140 | 0x01EF, /* R102 */ | |
141 | 0x2B00, /* R103 */ | |
142 | 0x0000, /* R104 - Class W 0 */ | |
143 | 0x01C0, /* R105 */ | |
144 | 0x1C10, /* R106 */ | |
145 | 0x0000, /* R107 */ | |
146 | 0x0000, /* R108 - Write Sequencer 0 */ | |
147 | 0x0000, /* R109 - Write Sequencer 1 */ | |
148 | 0x0000, /* R110 - Write Sequencer 2 */ | |
149 | 0x0000, /* R111 - Write Sequencer 3 */ | |
150 | 0x0000, /* R112 - Write Sequencer 4 */ | |
151 | 0x0000, /* R113 */ | |
152 | 0x0000, /* R114 - Control Interface */ | |
153 | 0x0000, /* R115 */ | |
154 | 0x00A8, /* R116 - GPIO Control 1 */ | |
155 | 0x00A8, /* R117 - GPIO Control 2 */ | |
156 | 0x00A8, /* R118 - GPIO Control 3 */ | |
157 | 0x0220, /* R119 - GPIO Control 4 */ | |
158 | 0x01A0, /* R120 - GPIO Control 5 */ | |
159 | 0x0000, /* R121 - Interrupt Status 1 */ | |
160 | 0xFFFF, /* R122 - Interrupt Status 1 Mask */ | |
161 | 0x0000, /* R123 - Interrupt Polarity 1 */ | |
162 | 0x0000, /* R124 */ | |
163 | 0x0003, /* R125 */ | |
164 | 0x0000, /* R126 - Interrupt Control */ | |
165 | 0x0000, /* R127 */ | |
166 | 0x0005, /* R128 */ | |
167 | 0x0000, /* R129 - Control Interface Test 1 */ | |
168 | 0x0000, /* R130 */ | |
169 | 0x0000, /* R131 */ | |
170 | 0x0000, /* R132 */ | |
171 | 0x0000, /* R133 */ | |
172 | 0x0000, /* R134 */ | |
173 | 0x03FF, /* R135 */ | |
174 | 0x0007, /* R136 */ | |
175 | 0x0040, /* R137 */ | |
176 | 0x0000, /* R138 */ | |
177 | 0x0000, /* R139 */ | |
178 | 0x0000, /* R140 */ | |
179 | 0x0000, /* R141 */ | |
180 | 0x0000, /* R142 */ | |
181 | 0x0000, /* R143 */ | |
182 | 0x0000, /* R144 */ | |
183 | 0x0000, /* R145 */ | |
184 | 0x0000, /* R146 */ | |
185 | 0x0000, /* R147 */ | |
186 | 0x4000, /* R148 */ | |
187 | 0x6810, /* R149 - Charge Pump Test 1 */ | |
188 | 0x0004, /* R150 */ | |
189 | 0x0000, /* R151 */ | |
190 | 0x0000, /* R152 */ | |
191 | 0x0000, /* R153 */ | |
192 | 0x0000, /* R154 */ | |
193 | 0x0000, /* R155 */ | |
194 | 0x0000, /* R156 */ | |
195 | 0x0000, /* R157 */ | |
196 | 0x0000, /* R158 */ | |
197 | 0x0000, /* R159 */ | |
198 | 0x0000, /* R160 */ | |
199 | 0x0000, /* R161 */ | |
200 | 0x0000, /* R162 */ | |
201 | 0x0000, /* R163 */ | |
202 | 0x0028, /* R164 - Clock Rate Test 4 */ | |
203 | 0x0004, /* R165 */ | |
204 | 0x0000, /* R166 */ | |
205 | 0x0060, /* R167 */ | |
206 | 0x0000, /* R168 */ | |
207 | 0x0000, /* R169 */ | |
208 | 0x0000, /* R170 */ | |
209 | 0x0000, /* R171 */ | |
210 | 0x0000, /* R172 - Analogue Output Bias 0 */ | |
211 | }; | |
212 | ||
d58d5d55 MB |
213 | struct wm8903_priv { |
214 | struct snd_soc_codec codec; | |
215 | u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)]; | |
216 | ||
217 | int sysclk; | |
218 | ||
219 | /* Reference counts */ | |
d58d5d55 MB |
220 | int class_w_users; |
221 | int playback_active; | |
222 | int capture_active; | |
223 | ||
224 | struct snd_pcm_substream *master_substream; | |
225 | struct snd_pcm_substream *slave_substream; | |
226 | }; | |
227 | ||
228 | ||
f1c0a02f MB |
229 | static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec, |
230 | unsigned int reg) | |
231 | { | |
232 | u16 *cache = codec->reg_cache; | |
233 | ||
234 | BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults)); | |
235 | ||
236 | return cache[reg]; | |
237 | } | |
238 | ||
239 | static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg) | |
240 | { | |
241 | struct i2c_msg xfer[2]; | |
242 | u16 data; | |
243 | int ret; | |
244 | struct i2c_client *client = codec->control_data; | |
245 | ||
246 | /* Write register */ | |
247 | xfer[0].addr = client->addr; | |
248 | xfer[0].flags = 0; | |
249 | xfer[0].len = 1; | |
250 | xfer[0].buf = ® | |
251 | ||
252 | /* Read data */ | |
253 | xfer[1].addr = client->addr; | |
254 | xfer[1].flags = I2C_M_RD; | |
255 | xfer[1].len = 2; | |
256 | xfer[1].buf = (u8 *)&data; | |
257 | ||
258 | ret = i2c_transfer(client->adapter, xfer, 2); | |
259 | if (ret != 2) { | |
260 | pr_err("i2c_transfer returned %d\n", ret); | |
261 | return 0; | |
262 | } | |
263 | ||
264 | return (data >> 8) | ((data & 0xff) << 8); | |
265 | } | |
266 | ||
267 | static unsigned int wm8903_read(struct snd_soc_codec *codec, | |
268 | unsigned int reg) | |
269 | { | |
270 | switch (reg) { | |
271 | case WM8903_SW_RESET_AND_ID: | |
272 | case WM8903_REVISION_NUMBER: | |
273 | case WM8903_INTERRUPT_STATUS_1: | |
274 | case WM8903_WRITE_SEQUENCER_4: | |
275 | return wm8903_hw_read(codec, reg); | |
276 | ||
277 | default: | |
278 | return wm8903_read_reg_cache(codec, reg); | |
279 | } | |
280 | } | |
281 | ||
282 | static void wm8903_write_reg_cache(struct snd_soc_codec *codec, | |
283 | u16 reg, unsigned int value) | |
284 | { | |
285 | u16 *cache = codec->reg_cache; | |
286 | ||
287 | BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults)); | |
288 | ||
289 | switch (reg) { | |
290 | case WM8903_SW_RESET_AND_ID: | |
291 | case WM8903_REVISION_NUMBER: | |
292 | break; | |
293 | ||
294 | default: | |
295 | cache[reg] = value; | |
296 | break; | |
297 | } | |
298 | } | |
299 | ||
300 | static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg, | |
301 | unsigned int value) | |
302 | { | |
303 | u8 data[3]; | |
304 | ||
305 | wm8903_write_reg_cache(codec, reg, value); | |
306 | ||
307 | /* Data format is 1 byte of address followed by 2 bytes of data */ | |
308 | data[0] = reg; | |
309 | data[1] = (value >> 8) & 0xff; | |
310 | data[2] = value & 0xff; | |
311 | ||
312 | if (codec->hw_write(codec->control_data, data, 3) == 2) | |
313 | return 0; | |
314 | else | |
315 | return -EIO; | |
316 | } | |
317 | ||
318 | static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start) | |
319 | { | |
320 | u16 reg[5]; | |
321 | struct i2c_client *i2c = codec->control_data; | |
322 | ||
323 | BUG_ON(start > 48); | |
324 | ||
325 | /* Enable the sequencer */ | |
326 | reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0); | |
327 | reg[0] |= WM8903_WSEQ_ENA; | |
328 | wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]); | |
329 | ||
330 | dev_dbg(&i2c->dev, "Starting sequence at %d\n", start); | |
331 | ||
332 | wm8903_write(codec, WM8903_WRITE_SEQUENCER_3, | |
333 | start | WM8903_WSEQ_START); | |
334 | ||
335 | /* Wait for it to complete. If we have the interrupt wired up then | |
336 | * we could block waiting for an interrupt, though polling may still | |
337 | * be desirable for diagnostic purposes. | |
338 | */ | |
339 | do { | |
340 | msleep(10); | |
341 | ||
342 | reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4); | |
343 | } while (reg[4] & WM8903_WSEQ_BUSY); | |
344 | ||
345 | dev_dbg(&i2c->dev, "Sequence complete\n"); | |
346 | ||
347 | /* Disable the sequencer again */ | |
348 | wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, | |
349 | reg[0] & ~WM8903_WSEQ_ENA); | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache) | |
355 | { | |
356 | int i; | |
357 | ||
358 | /* There really ought to be something better we can do here :/ */ | |
359 | for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++) | |
360 | cache[i] = wm8903_hw_read(codec, i); | |
361 | } | |
362 | ||
363 | static void wm8903_reset(struct snd_soc_codec *codec) | |
364 | { | |
365 | wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0); | |
d58d5d55 MB |
366 | memcpy(codec->reg_cache, wm8903_reg_defaults, |
367 | sizeof(wm8903_reg_defaults)); | |
f1c0a02f MB |
368 | } |
369 | ||
370 | #define WM8903_OUTPUT_SHORT 0x8 | |
371 | #define WM8903_OUTPUT_OUT 0x4 | |
372 | #define WM8903_OUTPUT_INT 0x2 | |
373 | #define WM8903_OUTPUT_IN 0x1 | |
374 | ||
42768a12 MB |
375 | static int wm8903_cp_event(struct snd_soc_dapm_widget *w, |
376 | struct snd_kcontrol *kcontrol, int event) | |
377 | { | |
378 | WARN_ON(event != SND_SOC_DAPM_POST_PMU); | |
379 | mdelay(4); | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
f1c0a02f MB |
384 | /* |
385 | * Event for headphone and line out amplifier power changes. Special | |
386 | * power up/down sequences are required in order to maximise pop/click | |
387 | * performance. | |
388 | */ | |
389 | static int wm8903_output_event(struct snd_soc_dapm_widget *w, | |
390 | struct snd_kcontrol *kcontrol, int event) | |
391 | { | |
392 | struct snd_soc_codec *codec = w->codec; | |
f1c0a02f | 393 | u16 val; |
0bc286e2 | 394 | u16 reg; |
d7d5c547 MB |
395 | u16 dcs_reg; |
396 | u16 dcs_bit; | |
0bc286e2 | 397 | int shift; |
f1c0a02f MB |
398 | |
399 | switch (w->reg) { | |
400 | case WM8903_POWER_MANAGEMENT_2: | |
401 | reg = WM8903_ANALOGUE_HP_0; | |
d7d5c547 | 402 | dcs_bit = 0 + w->shift; |
f1c0a02f MB |
403 | break; |
404 | case WM8903_POWER_MANAGEMENT_3: | |
405 | reg = WM8903_ANALOGUE_LINEOUT_0; | |
d7d5c547 | 406 | dcs_bit = 2 + w->shift; |
f1c0a02f MB |
407 | break; |
408 | default: | |
409 | BUG(); | |
1e297a19 | 410 | return -EINVAL; /* Spurious warning from some compilers */ |
f1c0a02f MB |
411 | } |
412 | ||
413 | switch (w->shift) { | |
414 | case 0: | |
415 | shift = 0; | |
416 | break; | |
417 | case 1: | |
418 | shift = 4; | |
419 | break; | |
420 | default: | |
421 | BUG(); | |
1e297a19 | 422 | return -EINVAL; /* Spurious warning from some compilers */ |
f1c0a02f MB |
423 | } |
424 | ||
425 | if (event & SND_SOC_DAPM_PRE_PMU) { | |
426 | val = wm8903_read(codec, reg); | |
427 | ||
428 | /* Short the output */ | |
429 | val &= ~(WM8903_OUTPUT_SHORT << shift); | |
430 | wm8903_write(codec, reg, val); | |
f1c0a02f MB |
431 | } |
432 | ||
433 | if (event & SND_SOC_DAPM_POST_PMU) { | |
434 | val = wm8903_read(codec, reg); | |
435 | ||
436 | val |= (WM8903_OUTPUT_IN << shift); | |
437 | wm8903_write(codec, reg, val); | |
438 | ||
439 | val |= (WM8903_OUTPUT_INT << shift); | |
440 | wm8903_write(codec, reg, val); | |
441 | ||
442 | /* Turn on the output ENA_OUTP */ | |
443 | val |= (WM8903_OUTPUT_OUT << shift); | |
444 | wm8903_write(codec, reg, val); | |
445 | ||
d7d5c547 MB |
446 | /* Enable the DC servo */ |
447 | dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0); | |
448 | dcs_reg |= dcs_bit; | |
449 | wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg); | |
450 | ||
f1c0a02f MB |
451 | /* Remove the short */ |
452 | val |= (WM8903_OUTPUT_SHORT << shift); | |
453 | wm8903_write(codec, reg, val); | |
454 | } | |
455 | ||
456 | if (event & SND_SOC_DAPM_PRE_PMD) { | |
457 | val = wm8903_read(codec, reg); | |
458 | ||
459 | /* Short the output */ | |
460 | val &= ~(WM8903_OUTPUT_SHORT << shift); | |
461 | wm8903_write(codec, reg, val); | |
462 | ||
d7d5c547 MB |
463 | /* Disable the DC servo */ |
464 | dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0); | |
465 | dcs_reg &= ~dcs_bit; | |
466 | wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg); | |
467 | ||
f1c0a02f MB |
468 | /* Then disable the intermediate and output stages */ |
469 | val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT | | |
470 | WM8903_OUTPUT_IN) << shift); | |
471 | wm8903_write(codec, reg, val); | |
472 | } | |
473 | ||
f1c0a02f MB |
474 | return 0; |
475 | } | |
476 | ||
477 | /* | |
478 | * When used with DAC outputs only the WM8903 charge pump supports | |
479 | * operation in class W mode, providing very low power consumption | |
480 | * when used with digital sources. Enable and disable this mode | |
481 | * automatically depending on the mixer configuration. | |
482 | * | |
483 | * All the relevant controls are simple switches. | |
484 | */ | |
485 | static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, | |
486 | struct snd_ctl_elem_value *ucontrol) | |
487 | { | |
488 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); | |
489 | struct snd_soc_codec *codec = widget->codec; | |
490 | struct wm8903_priv *wm8903 = codec->private_data; | |
491 | struct i2c_client *i2c = codec->control_data; | |
492 | u16 reg; | |
493 | int ret; | |
494 | ||
495 | reg = wm8903_read(codec, WM8903_CLASS_W_0); | |
496 | ||
497 | /* Turn it off if we're about to enable bypass */ | |
498 | if (ucontrol->value.integer.value[0]) { | |
499 | if (wm8903->class_w_users == 0) { | |
500 | dev_dbg(&i2c->dev, "Disabling Class W\n"); | |
501 | wm8903_write(codec, WM8903_CLASS_W_0, reg & | |
502 | ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); | |
503 | } | |
504 | wm8903->class_w_users++; | |
505 | } | |
506 | ||
507 | /* Implement the change */ | |
508 | ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); | |
509 | ||
510 | /* If we've just disabled the last bypass path turn Class W on */ | |
511 | if (!ucontrol->value.integer.value[0]) { | |
512 | if (wm8903->class_w_users == 1) { | |
513 | dev_dbg(&i2c->dev, "Enabling Class W\n"); | |
514 | wm8903_write(codec, WM8903_CLASS_W_0, reg | | |
515 | WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); | |
516 | } | |
517 | wm8903->class_w_users--; | |
518 | } | |
519 | ||
520 | dev_dbg(&i2c->dev, "Bypass use count now %d\n", | |
521 | wm8903->class_w_users); | |
522 | ||
523 | return ret; | |
524 | } | |
525 | ||
526 | #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ | |
527 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
528 | .info = snd_soc_info_volsw, \ | |
529 | .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \ | |
530 | .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } | |
531 | ||
532 | ||
533 | /* ALSA can only do steps of .01dB */ | |
534 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
535 | ||
291ce18c | 536 | static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); |
f1c0a02f MB |
537 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); |
538 | ||
539 | static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); | |
540 | static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); | |
541 | static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); | |
542 | static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); | |
543 | static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); | |
544 | ||
545 | static const char *drc_slope_text[] = { | |
546 | "1", "1/2", "1/4", "1/8", "1/16", "0" | |
547 | }; | |
548 | ||
549 | static const struct soc_enum drc_slope_r0 = | |
550 | SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text); | |
551 | ||
552 | static const struct soc_enum drc_slope_r1 = | |
553 | SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text); | |
554 | ||
555 | static const char *drc_attack_text[] = { | |
556 | "instantaneous", | |
557 | "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", | |
558 | "46.4ms", "92.8ms", "185.6ms" | |
559 | }; | |
560 | ||
561 | static const struct soc_enum drc_attack = | |
562 | SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text); | |
563 | ||
564 | static const char *drc_decay_text[] = { | |
565 | "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", | |
566 | "23.87s", "47.56s" | |
567 | }; | |
568 | ||
569 | static const struct soc_enum drc_decay = | |
570 | SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text); | |
571 | ||
572 | static const char *drc_ff_delay_text[] = { | |
573 | "5 samples", "9 samples" | |
574 | }; | |
575 | ||
576 | static const struct soc_enum drc_ff_delay = | |
577 | SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text); | |
578 | ||
579 | static const char *drc_qr_decay_text[] = { | |
580 | "0.725ms", "1.45ms", "5.8ms" | |
581 | }; | |
582 | ||
583 | static const struct soc_enum drc_qr_decay = | |
584 | SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text); | |
585 | ||
586 | static const char *drc_smoothing_text[] = { | |
587 | "Low", "Medium", "High" | |
588 | }; | |
589 | ||
590 | static const struct soc_enum drc_smoothing = | |
591 | SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text); | |
592 | ||
593 | static const char *soft_mute_text[] = { | |
594 | "Fast (fs/2)", "Slow (fs/32)" | |
595 | }; | |
596 | ||
597 | static const struct soc_enum soft_mute = | |
598 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text); | |
599 | ||
600 | static const char *mute_mode_text[] = { | |
601 | "Hard", "Soft" | |
602 | }; | |
603 | ||
604 | static const struct soc_enum mute_mode = | |
605 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); | |
606 | ||
607 | static const char *dac_deemphasis_text[] = { | |
608 | "Disabled", "32kHz", "44.1kHz", "48kHz" | |
609 | }; | |
610 | ||
611 | static const struct soc_enum dac_deemphasis = | |
612 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text); | |
613 | ||
614 | static const char *companding_text[] = { | |
615 | "ulaw", "alaw" | |
616 | }; | |
617 | ||
618 | static const struct soc_enum dac_companding = | |
619 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text); | |
620 | ||
621 | static const struct soc_enum adc_companding = | |
622 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text); | |
623 | ||
624 | static const char *input_mode_text[] = { | |
625 | "Single-Ended", "Differential Line", "Differential Mic" | |
626 | }; | |
627 | ||
628 | static const struct soc_enum linput_mode_enum = | |
629 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); | |
630 | ||
631 | static const struct soc_enum rinput_mode_enum = | |
632 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); | |
633 | ||
634 | static const char *linput_mux_text[] = { | |
635 | "IN1L", "IN2L", "IN3L" | |
636 | }; | |
637 | ||
638 | static const struct soc_enum linput_enum = | |
639 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text); | |
640 | ||
641 | static const struct soc_enum linput_inv_enum = | |
642 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text); | |
643 | ||
644 | static const char *rinput_mux_text[] = { | |
645 | "IN1R", "IN2R", "IN3R" | |
646 | }; | |
647 | ||
648 | static const struct soc_enum rinput_enum = | |
649 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text); | |
650 | ||
651 | static const struct soc_enum rinput_inv_enum = | |
652 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); | |
653 | ||
654 | ||
291ce18c MB |
655 | static const char *sidetone_text[] = { |
656 | "None", "Left", "Right" | |
657 | }; | |
658 | ||
659 | static const struct soc_enum lsidetone_enum = | |
660 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text); | |
661 | ||
662 | static const struct soc_enum rsidetone_enum = | |
663 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text); | |
664 | ||
f1c0a02f MB |
665 | static const struct snd_kcontrol_new wm8903_snd_controls[] = { |
666 | ||
667 | /* Input PGAs - No TLV since the scale depends on PGA mode */ | |
668 | SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, | |
5715952b | 669 | 7, 1, 1), |
f1c0a02f MB |
670 | SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, |
671 | 0, 31, 0), | |
672 | SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, | |
673 | 6, 1, 0), | |
674 | ||
675 | SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, | |
5715952b | 676 | 7, 1, 1), |
f1c0a02f MB |
677 | SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, |
678 | 0, 31, 0), | |
679 | SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, | |
680 | 6, 1, 0), | |
681 | ||
682 | /* ADCs */ | |
683 | SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), | |
684 | SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), | |
685 | SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), | |
686 | SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1, | |
687 | drc_tlv_thresh), | |
688 | SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), | |
689 | SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), | |
690 | SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), | |
691 | SOC_ENUM("DRC Attack Rate", drc_attack), | |
692 | SOC_ENUM("DRC Decay Rate", drc_decay), | |
693 | SOC_ENUM("DRC FF Delay", drc_ff_delay), | |
694 | SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), | |
695 | SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), | |
696 | SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), | |
697 | SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), | |
698 | SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), | |
699 | SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), | |
700 | SOC_ENUM("DRC Smoothing Threashold", drc_smoothing), | |
701 | SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), | |
702 | ||
703 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, | |
704 | WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), | |
705 | SOC_ENUM("ADC Companding Mode", adc_companding), | |
706 | SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), | |
707 | ||
291ce18c MB |
708 | SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, |
709 | 12, 0, digital_sidetone_tlv), | |
710 | ||
f1c0a02f MB |
711 | /* DAC */ |
712 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, | |
713 | WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), | |
714 | SOC_ENUM("DAC Soft Mute Rate", soft_mute), | |
715 | SOC_ENUM("DAC Mute Mode", mute_mode), | |
716 | SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), | |
717 | SOC_ENUM("DAC De-emphasis", dac_deemphasis), | |
718 | SOC_SINGLE("DAC Sloping Stopband Filter Switch", | |
719 | WM8903_DAC_DIGITAL_1, 11, 1, 0), | |
720 | SOC_ENUM("DAC Companding Mode", dac_companding), | |
721 | SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), | |
722 | ||
723 | /* Headphones */ | |
724 | SOC_DOUBLE_R("Headphone Switch", | |
725 | WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, | |
726 | 8, 1, 1), | |
727 | SOC_DOUBLE_R("Headphone ZC Switch", | |
728 | WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, | |
729 | 6, 1, 0), | |
730 | SOC_DOUBLE_R_TLV("Headphone Volume", | |
731 | WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, | |
732 | 0, 63, 0, out_tlv), | |
733 | ||
734 | /* Line out */ | |
735 | SOC_DOUBLE_R("Line Out Switch", | |
736 | WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, | |
737 | 8, 1, 1), | |
738 | SOC_DOUBLE_R("Line Out ZC Switch", | |
739 | WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, | |
740 | 6, 1, 0), | |
741 | SOC_DOUBLE_R_TLV("Line Out Volume", | |
742 | WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, | |
743 | 0, 63, 0, out_tlv), | |
744 | ||
745 | /* Speaker */ | |
746 | SOC_DOUBLE_R("Speaker Switch", | |
747 | WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), | |
748 | SOC_DOUBLE_R("Speaker ZC Switch", | |
749 | WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), | |
750 | SOC_DOUBLE_R_TLV("Speaker Volume", | |
751 | WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, | |
752 | 0, 63, 0, out_tlv), | |
753 | }; | |
754 | ||
f1c0a02f MB |
755 | static const struct snd_kcontrol_new linput_mode_mux = |
756 | SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); | |
757 | ||
758 | static const struct snd_kcontrol_new rinput_mode_mux = | |
759 | SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); | |
760 | ||
761 | static const struct snd_kcontrol_new linput_mux = | |
762 | SOC_DAPM_ENUM("Left Input Mux", linput_enum); | |
763 | ||
764 | static const struct snd_kcontrol_new linput_inv_mux = | |
765 | SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); | |
766 | ||
767 | static const struct snd_kcontrol_new rinput_mux = | |
768 | SOC_DAPM_ENUM("Right Input Mux", rinput_enum); | |
769 | ||
770 | static const struct snd_kcontrol_new rinput_inv_mux = | |
771 | SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); | |
772 | ||
291ce18c MB |
773 | static const struct snd_kcontrol_new lsidetone_mux = |
774 | SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); | |
775 | ||
776 | static const struct snd_kcontrol_new rsidetone_mux = | |
777 | SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); | |
778 | ||
f1c0a02f MB |
779 | static const struct snd_kcontrol_new left_output_mixer[] = { |
780 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), | |
781 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), | |
782 | SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), | |
4b4fffdd | 783 | SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), |
f1c0a02f MB |
784 | }; |
785 | ||
786 | static const struct snd_kcontrol_new right_output_mixer[] = { | |
787 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), | |
788 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), | |
789 | SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), | |
4b4fffdd | 790 | SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), |
f1c0a02f MB |
791 | }; |
792 | ||
793 | static const struct snd_kcontrol_new left_speaker_mixer[] = { | |
794 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), | |
795 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), | |
796 | SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), | |
797 | SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, | |
4b4fffdd | 798 | 0, 1, 0), |
f1c0a02f MB |
799 | }; |
800 | ||
801 | static const struct snd_kcontrol_new right_speaker_mixer[] = { | |
802 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), | |
803 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), | |
804 | SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, | |
805 | 1, 1, 0), | |
806 | SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, | |
4b4fffdd | 807 | 0, 1, 0), |
f1c0a02f MB |
808 | }; |
809 | ||
810 | static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { | |
811 | SND_SOC_DAPM_INPUT("IN1L"), | |
812 | SND_SOC_DAPM_INPUT("IN1R"), | |
813 | SND_SOC_DAPM_INPUT("IN2L"), | |
814 | SND_SOC_DAPM_INPUT("IN2R"), | |
815 | SND_SOC_DAPM_INPUT("IN3L"), | |
816 | SND_SOC_DAPM_INPUT("IN3R"), | |
817 | ||
818 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
819 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
820 | SND_SOC_DAPM_OUTPUT("LINEOUTL"), | |
821 | SND_SOC_DAPM_OUTPUT("LINEOUTR"), | |
822 | SND_SOC_DAPM_OUTPUT("LOP"), | |
823 | SND_SOC_DAPM_OUTPUT("LON"), | |
824 | SND_SOC_DAPM_OUTPUT("ROP"), | |
825 | SND_SOC_DAPM_OUTPUT("RON"), | |
826 | ||
827 | SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0), | |
828 | ||
829 | SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), | |
830 | SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, | |
831 | &linput_inv_mux), | |
832 | SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), | |
833 | ||
834 | SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), | |
835 | SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, | |
836 | &rinput_inv_mux), | |
837 | SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), | |
838 | ||
839 | SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), | |
840 | SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), | |
841 | ||
842 | SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0), | |
843 | SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0), | |
844 | ||
291ce18c MB |
845 | SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), |
846 | SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), | |
847 | ||
f1c0a02f MB |
848 | SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0), |
849 | SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0), | |
850 | ||
851 | SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, | |
852 | left_output_mixer, ARRAY_SIZE(left_output_mixer)), | |
853 | SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, | |
854 | right_output_mixer, ARRAY_SIZE(right_output_mixer)), | |
855 | ||
856 | SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, | |
857 | left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), | |
858 | SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, | |
859 | right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), | |
860 | ||
861 | SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, | |
862 | 1, 0, NULL, 0, wm8903_output_event, | |
863 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
42768a12 | 864 | SND_SOC_DAPM_PRE_PMD), |
f1c0a02f MB |
865 | SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, |
866 | 0, 0, NULL, 0, wm8903_output_event, | |
867 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
42768a12 | 868 | SND_SOC_DAPM_PRE_PMD), |
f1c0a02f MB |
869 | |
870 | SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0, | |
871 | NULL, 0, wm8903_output_event, | |
872 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
42768a12 | 873 | SND_SOC_DAPM_PRE_PMD), |
f1c0a02f MB |
874 | SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0, |
875 | NULL, 0, wm8903_output_event, | |
876 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
42768a12 | 877 | SND_SOC_DAPM_PRE_PMD), |
f1c0a02f MB |
878 | |
879 | SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, | |
880 | NULL, 0), | |
881 | SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, | |
882 | NULL, 0), | |
883 | ||
42768a12 MB |
884 | SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, |
885 | wm8903_cp_event, SND_SOC_DAPM_POST_PMU), | |
c2aef4ff | 886 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), |
f1c0a02f MB |
887 | }; |
888 | ||
889 | static const struct snd_soc_dapm_route intercon[] = { | |
890 | ||
891 | { "Left Input Mux", "IN1L", "IN1L" }, | |
892 | { "Left Input Mux", "IN2L", "IN2L" }, | |
893 | { "Left Input Mux", "IN3L", "IN3L" }, | |
894 | ||
895 | { "Left Input Inverting Mux", "IN1L", "IN1L" }, | |
896 | { "Left Input Inverting Mux", "IN2L", "IN2L" }, | |
897 | { "Left Input Inverting Mux", "IN3L", "IN3L" }, | |
898 | ||
899 | { "Right Input Mux", "IN1R", "IN1R" }, | |
900 | { "Right Input Mux", "IN2R", "IN2R" }, | |
901 | { "Right Input Mux", "IN3R", "IN3R" }, | |
902 | ||
903 | { "Right Input Inverting Mux", "IN1R", "IN1R" }, | |
904 | { "Right Input Inverting Mux", "IN2R", "IN2R" }, | |
905 | { "Right Input Inverting Mux", "IN3R", "IN3R" }, | |
906 | ||
907 | { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, | |
908 | { "Left Input Mode Mux", "Differential Line", | |
909 | "Left Input Mux" }, | |
910 | { "Left Input Mode Mux", "Differential Line", | |
911 | "Left Input Inverting Mux" }, | |
912 | { "Left Input Mode Mux", "Differential Mic", | |
913 | "Left Input Mux" }, | |
914 | { "Left Input Mode Mux", "Differential Mic", | |
915 | "Left Input Inverting Mux" }, | |
916 | ||
917 | { "Right Input Mode Mux", "Single-Ended", | |
918 | "Right Input Inverting Mux" }, | |
919 | { "Right Input Mode Mux", "Differential Line", | |
920 | "Right Input Mux" }, | |
921 | { "Right Input Mode Mux", "Differential Line", | |
922 | "Right Input Inverting Mux" }, | |
923 | { "Right Input Mode Mux", "Differential Mic", | |
924 | "Right Input Mux" }, | |
925 | { "Right Input Mode Mux", "Differential Mic", | |
926 | "Right Input Inverting Mux" }, | |
927 | ||
928 | { "Left Input PGA", NULL, "Left Input Mode Mux" }, | |
929 | { "Right Input PGA", NULL, "Right Input Mode Mux" }, | |
930 | ||
931 | { "ADCL", NULL, "Left Input PGA" }, | |
c2aef4ff | 932 | { "ADCL", NULL, "CLK_DSP" }, |
f1c0a02f | 933 | { "ADCR", NULL, "Right Input PGA" }, |
c2aef4ff MB |
934 | { "ADCR", NULL, "CLK_DSP" }, |
935 | ||
291ce18c MB |
936 | { "DACL Sidetone", "Left", "ADCL" }, |
937 | { "DACL Sidetone", "Right", "ADCR" }, | |
938 | { "DACR Sidetone", "Left", "ADCL" }, | |
939 | { "DACR Sidetone", "Right", "ADCR" }, | |
940 | ||
941 | { "DACL", NULL, "DACL Sidetone" }, | |
c2aef4ff | 942 | { "DACL", NULL, "CLK_DSP" }, |
291ce18c | 943 | { "DACR", NULL, "DACR Sidetone" }, |
c2aef4ff | 944 | { "DACR", NULL, "CLK_DSP" }, |
f1c0a02f MB |
945 | |
946 | { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
947 | { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
948 | { "Left Output Mixer", "DACL Switch", "DACL" }, | |
949 | { "Left Output Mixer", "DACR Switch", "DACR" }, | |
950 | ||
951 | { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
952 | { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
953 | { "Right Output Mixer", "DACL Switch", "DACL" }, | |
954 | { "Right Output Mixer", "DACR Switch", "DACR" }, | |
955 | ||
956 | { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
957 | { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
958 | { "Left Speaker Mixer", "DACL Switch", "DACL" }, | |
959 | { "Left Speaker Mixer", "DACR Switch", "DACR" }, | |
960 | ||
961 | { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
962 | { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
963 | { "Right Speaker Mixer", "DACL Switch", "DACL" }, | |
964 | { "Right Speaker Mixer", "DACR Switch", "DACR" }, | |
965 | ||
966 | { "Left Line Output PGA", NULL, "Left Output Mixer" }, | |
967 | { "Right Line Output PGA", NULL, "Right Output Mixer" }, | |
968 | ||
969 | { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, | |
970 | { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, | |
971 | ||
972 | { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, | |
973 | { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, | |
974 | ||
975 | { "HPOUTL", NULL, "Left Headphone Output PGA" }, | |
976 | { "HPOUTR", NULL, "Right Headphone Output PGA" }, | |
977 | ||
978 | { "LINEOUTL", NULL, "Left Line Output PGA" }, | |
979 | { "LINEOUTR", NULL, "Right Line Output PGA" }, | |
980 | ||
981 | { "LOP", NULL, "Left Speaker PGA" }, | |
982 | { "LON", NULL, "Left Speaker PGA" }, | |
983 | ||
984 | { "ROP", NULL, "Right Speaker PGA" }, | |
985 | { "RON", NULL, "Right Speaker PGA" }, | |
42768a12 MB |
986 | |
987 | { "Left Headphone Output PGA", NULL, "Charge Pump" }, | |
988 | { "Right Headphone Output PGA", NULL, "Charge Pump" }, | |
989 | { "Left Line Output PGA", NULL, "Charge Pump" }, | |
990 | { "Right Line Output PGA", NULL, "Charge Pump" }, | |
f1c0a02f MB |
991 | }; |
992 | ||
993 | static int wm8903_add_widgets(struct snd_soc_codec *codec) | |
994 | { | |
995 | snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets, | |
996 | ARRAY_SIZE(wm8903_dapm_widgets)); | |
997 | ||
998 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); | |
999 | ||
1000 | snd_soc_dapm_new_widgets(codec); | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static int wm8903_set_bias_level(struct snd_soc_codec *codec, | |
1006 | enum snd_soc_bias_level level) | |
1007 | { | |
1008 | struct i2c_client *i2c = codec->control_data; | |
1009 | u16 reg, reg2; | |
1010 | ||
1011 | switch (level) { | |
1012 | case SND_SOC_BIAS_ON: | |
1013 | case SND_SOC_BIAS_PREPARE: | |
1014 | reg = wm8903_read(codec, WM8903_VMID_CONTROL_0); | |
1015 | reg &= ~(WM8903_VMID_RES_MASK); | |
1016 | reg |= WM8903_VMID_RES_50K; | |
1017 | wm8903_write(codec, WM8903_VMID_CONTROL_0, reg); | |
1018 | break; | |
1019 | ||
1020 | case SND_SOC_BIAS_STANDBY: | |
1021 | if (codec->bias_level == SND_SOC_BIAS_OFF) { | |
3b1228ab MB |
1022 | wm8903_write(codec, WM8903_CLOCK_RATES_2, |
1023 | WM8903_CLK_SYS_ENA); | |
1024 | ||
4dbfe809 MB |
1025 | /* Change DC servo dither level in startup sequence */ |
1026 | wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11); | |
1027 | wm8903_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257); | |
1028 | wm8903_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2); | |
1029 | ||
f1c0a02f MB |
1030 | wm8903_run_sequence(codec, 0); |
1031 | wm8903_sync_reg_cache(codec, codec->reg_cache); | |
1032 | ||
1033 | /* Enable low impedence charge pump output */ | |
1034 | reg = wm8903_read(codec, | |
1035 | WM8903_CONTROL_INTERFACE_TEST_1); | |
1036 | wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, | |
1037 | reg | WM8903_TEST_KEY); | |
1038 | reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1); | |
1039 | wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1, | |
1040 | reg2 | WM8903_CP_SW_KELVIN_MODE_MASK); | |
1041 | wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, | |
1042 | reg); | |
1043 | ||
1044 | /* By default no bypass paths are enabled so | |
1045 | * enable Class W support. | |
1046 | */ | |
1047 | dev_dbg(&i2c->dev, "Enabling Class W\n"); | |
1048 | wm8903_write(codec, WM8903_CLASS_W_0, reg | | |
1049 | WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); | |
1050 | } | |
1051 | ||
1052 | reg = wm8903_read(codec, WM8903_VMID_CONTROL_0); | |
1053 | reg &= ~(WM8903_VMID_RES_MASK); | |
1054 | reg |= WM8903_VMID_RES_250K; | |
1055 | wm8903_write(codec, WM8903_VMID_CONTROL_0, reg); | |
1056 | break; | |
1057 | ||
1058 | case SND_SOC_BIAS_OFF: | |
1059 | wm8903_run_sequence(codec, 32); | |
3b1228ab MB |
1060 | reg = wm8903_read(codec, WM8903_CLOCK_RATES_2); |
1061 | reg &= ~WM8903_CLK_SYS_ENA; | |
1062 | wm8903_write(codec, WM8903_CLOCK_RATES_2, reg); | |
f1c0a02f MB |
1063 | break; |
1064 | } | |
1065 | ||
1066 | codec->bias_level = level; | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
1071 | static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1072 | int clk_id, unsigned int freq, int dir) | |
1073 | { | |
1074 | struct snd_soc_codec *codec = codec_dai->codec; | |
1075 | struct wm8903_priv *wm8903 = codec->private_data; | |
1076 | ||
1077 | wm8903->sysclk = freq; | |
1078 | ||
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1083 | unsigned int fmt) | |
1084 | { | |
1085 | struct snd_soc_codec *codec = codec_dai->codec; | |
1086 | u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1); | |
1087 | ||
1088 | aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | | |
1089 | WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); | |
1090 | ||
1091 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1092 | case SND_SOC_DAIFMT_CBS_CFS: | |
1093 | break; | |
1094 | case SND_SOC_DAIFMT_CBS_CFM: | |
1095 | aif1 |= WM8903_LRCLK_DIR; | |
1096 | break; | |
1097 | case SND_SOC_DAIFMT_CBM_CFM: | |
1098 | aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; | |
1099 | break; | |
1100 | case SND_SOC_DAIFMT_CBM_CFS: | |
1101 | aif1 |= WM8903_BCLK_DIR; | |
1102 | break; | |
1103 | default: | |
1104 | return -EINVAL; | |
1105 | } | |
1106 | ||
1107 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1108 | case SND_SOC_DAIFMT_DSP_A: | |
1109 | aif1 |= 0x3; | |
1110 | break; | |
1111 | case SND_SOC_DAIFMT_DSP_B: | |
1112 | aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; | |
1113 | break; | |
1114 | case SND_SOC_DAIFMT_I2S: | |
1115 | aif1 |= 0x2; | |
1116 | break; | |
1117 | case SND_SOC_DAIFMT_RIGHT_J: | |
1118 | aif1 |= 0x1; | |
1119 | break; | |
1120 | case SND_SOC_DAIFMT_LEFT_J: | |
1121 | break; | |
1122 | default: | |
1123 | return -EINVAL; | |
1124 | } | |
1125 | ||
1126 | /* Clock inversion */ | |
1127 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1128 | case SND_SOC_DAIFMT_DSP_A: | |
1129 | case SND_SOC_DAIFMT_DSP_B: | |
1130 | /* frame inversion not valid for DSP modes */ | |
1131 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1132 | case SND_SOC_DAIFMT_NB_NF: | |
1133 | break; | |
1134 | case SND_SOC_DAIFMT_IB_NF: | |
1135 | aif1 |= WM8903_AIF_BCLK_INV; | |
1136 | break; | |
1137 | default: | |
1138 | return -EINVAL; | |
1139 | } | |
1140 | break; | |
1141 | case SND_SOC_DAIFMT_I2S: | |
1142 | case SND_SOC_DAIFMT_RIGHT_J: | |
1143 | case SND_SOC_DAIFMT_LEFT_J: | |
1144 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1145 | case SND_SOC_DAIFMT_NB_NF: | |
1146 | break; | |
1147 | case SND_SOC_DAIFMT_IB_IF: | |
1148 | aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; | |
1149 | break; | |
1150 | case SND_SOC_DAIFMT_IB_NF: | |
1151 | aif1 |= WM8903_AIF_BCLK_INV; | |
1152 | break; | |
1153 | case SND_SOC_DAIFMT_NB_IF: | |
1154 | aif1 |= WM8903_AIF_LRCLK_INV; | |
1155 | break; | |
1156 | default: | |
1157 | return -EINVAL; | |
1158 | } | |
1159 | break; | |
1160 | default: | |
1161 | return -EINVAL; | |
1162 | } | |
1163 | ||
1164 | wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); | |
1165 | ||
1166 | return 0; | |
1167 | } | |
1168 | ||
1169 | static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
1170 | { | |
1171 | struct snd_soc_codec *codec = codec_dai->codec; | |
1172 | u16 reg; | |
1173 | ||
1174 | reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1); | |
1175 | ||
1176 | if (mute) | |
1177 | reg |= WM8903_DAC_MUTE; | |
1178 | else | |
1179 | reg &= ~WM8903_DAC_MUTE; | |
1180 | ||
1181 | wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg); | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended | |
1187 | * for optimal performance so we list the lower rates first and match | |
1188 | * on the last match we find. */ | |
1189 | static struct { | |
1190 | int div; | |
1191 | int rate; | |
1192 | int mode; | |
1193 | int mclk_div; | |
1194 | } clk_sys_ratios[] = { | |
1195 | { 64, 0x0, 0x0, 1 }, | |
1196 | { 68, 0x0, 0x1, 1 }, | |
1197 | { 125, 0x0, 0x2, 1 }, | |
1198 | { 128, 0x1, 0x0, 1 }, | |
1199 | { 136, 0x1, 0x1, 1 }, | |
1200 | { 192, 0x2, 0x0, 1 }, | |
1201 | { 204, 0x2, 0x1, 1 }, | |
1202 | ||
1203 | { 64, 0x0, 0x0, 2 }, | |
1204 | { 68, 0x0, 0x1, 2 }, | |
1205 | { 125, 0x0, 0x2, 2 }, | |
1206 | { 128, 0x1, 0x0, 2 }, | |
1207 | { 136, 0x1, 0x1, 2 }, | |
1208 | { 192, 0x2, 0x0, 2 }, | |
1209 | { 204, 0x2, 0x1, 2 }, | |
1210 | ||
1211 | { 250, 0x2, 0x2, 1 }, | |
1212 | { 256, 0x3, 0x0, 1 }, | |
1213 | { 272, 0x3, 0x1, 1 }, | |
1214 | { 384, 0x4, 0x0, 1 }, | |
1215 | { 408, 0x4, 0x1, 1 }, | |
1216 | { 375, 0x4, 0x2, 1 }, | |
1217 | { 512, 0x5, 0x0, 1 }, | |
1218 | { 544, 0x5, 0x1, 1 }, | |
1219 | { 500, 0x5, 0x2, 1 }, | |
1220 | { 768, 0x6, 0x0, 1 }, | |
1221 | { 816, 0x6, 0x1, 1 }, | |
1222 | { 750, 0x6, 0x2, 1 }, | |
1223 | { 1024, 0x7, 0x0, 1 }, | |
1224 | { 1088, 0x7, 0x1, 1 }, | |
1225 | { 1000, 0x7, 0x2, 1 }, | |
1226 | { 1408, 0x8, 0x0, 1 }, | |
1227 | { 1496, 0x8, 0x1, 1 }, | |
1228 | { 1536, 0x9, 0x0, 1 }, | |
1229 | { 1632, 0x9, 0x1, 1 }, | |
1230 | { 1500, 0x9, 0x2, 1 }, | |
1231 | ||
1232 | { 250, 0x2, 0x2, 2 }, | |
1233 | { 256, 0x3, 0x0, 2 }, | |
1234 | { 272, 0x3, 0x1, 2 }, | |
1235 | { 384, 0x4, 0x0, 2 }, | |
1236 | { 408, 0x4, 0x1, 2 }, | |
1237 | { 375, 0x4, 0x2, 2 }, | |
1238 | { 512, 0x5, 0x0, 2 }, | |
1239 | { 544, 0x5, 0x1, 2 }, | |
1240 | { 500, 0x5, 0x2, 2 }, | |
1241 | { 768, 0x6, 0x0, 2 }, | |
1242 | { 816, 0x6, 0x1, 2 }, | |
1243 | { 750, 0x6, 0x2, 2 }, | |
1244 | { 1024, 0x7, 0x0, 2 }, | |
1245 | { 1088, 0x7, 0x1, 2 }, | |
1246 | { 1000, 0x7, 0x2, 2 }, | |
1247 | { 1408, 0x8, 0x0, 2 }, | |
1248 | { 1496, 0x8, 0x1, 2 }, | |
1249 | { 1536, 0x9, 0x0, 2 }, | |
1250 | { 1632, 0x9, 0x1, 2 }, | |
1251 | { 1500, 0x9, 0x2, 2 }, | |
1252 | }; | |
1253 | ||
1254 | /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ | |
1255 | static struct { | |
1256 | int ratio; | |
1257 | int div; | |
1258 | } bclk_divs[] = { | |
1259 | { 10, 0 }, | |
1260 | { 15, 1 }, | |
1261 | { 20, 2 }, | |
1262 | { 30, 3 }, | |
1263 | { 40, 4 }, | |
1264 | { 50, 5 }, | |
1265 | { 55, 6 }, | |
1266 | { 60, 7 }, | |
1267 | { 80, 8 }, | |
1268 | { 100, 9 }, | |
1269 | { 110, 10 }, | |
1270 | { 120, 11 }, | |
1271 | { 160, 12 }, | |
1272 | { 200, 13 }, | |
1273 | { 220, 14 }, | |
1274 | { 240, 15 }, | |
1275 | { 250, 16 }, | |
1276 | { 300, 17 }, | |
1277 | { 320, 18 }, | |
1278 | { 440, 19 }, | |
1279 | { 480, 20 }, | |
1280 | }; | |
1281 | ||
1282 | /* Sample rates for DSP */ | |
1283 | static struct { | |
1284 | int rate; | |
1285 | int value; | |
1286 | } sample_rates[] = { | |
1287 | { 8000, 0 }, | |
1288 | { 11025, 1 }, | |
1289 | { 12000, 2 }, | |
1290 | { 16000, 3 }, | |
1291 | { 22050, 4 }, | |
1292 | { 24000, 5 }, | |
1293 | { 32000, 6 }, | |
1294 | { 44100, 7 }, | |
1295 | { 48000, 8 }, | |
1296 | { 88200, 9 }, | |
1297 | { 96000, 10 }, | |
1298 | { 0, 0 }, | |
1299 | }; | |
1300 | ||
dee89c4d MB |
1301 | static int wm8903_startup(struct snd_pcm_substream *substream, |
1302 | struct snd_soc_dai *dai) | |
f1c0a02f MB |
1303 | { |
1304 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1305 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 1306 | struct snd_soc_codec *codec = socdev->card->codec; |
f1c0a02f MB |
1307 | struct wm8903_priv *wm8903 = codec->private_data; |
1308 | struct i2c_client *i2c = codec->control_data; | |
1309 | struct snd_pcm_runtime *master_runtime; | |
1310 | ||
1311 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1312 | wm8903->playback_active++; | |
1313 | else | |
1314 | wm8903->capture_active++; | |
1315 | ||
1316 | /* The DAI has shared clocks so if we already have a playback or | |
1317 | * capture going then constrain this substream to match it. | |
1318 | */ | |
1319 | if (wm8903->master_substream) { | |
1320 | master_runtime = wm8903->master_substream->runtime; | |
1321 | ||
727fb909 MB |
1322 | dev_dbg(&i2c->dev, "Constraining to %d bits\n", |
1323 | master_runtime->sample_bits); | |
f1c0a02f MB |
1324 | |
1325 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1326 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1327 | master_runtime->sample_bits, | |
1328 | master_runtime->sample_bits); | |
1329 | ||
1330 | wm8903->slave_substream = substream; | |
1331 | } else | |
1332 | wm8903->master_substream = substream; | |
1333 | ||
1334 | return 0; | |
1335 | } | |
1336 | ||
dee89c4d MB |
1337 | static void wm8903_shutdown(struct snd_pcm_substream *substream, |
1338 | struct snd_soc_dai *dai) | |
f1c0a02f MB |
1339 | { |
1340 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1341 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 1342 | struct snd_soc_codec *codec = socdev->card->codec; |
f1c0a02f MB |
1343 | struct wm8903_priv *wm8903 = codec->private_data; |
1344 | ||
1345 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1346 | wm8903->playback_active--; | |
1347 | else | |
1348 | wm8903->capture_active--; | |
1349 | ||
1350 | if (wm8903->master_substream == substream) | |
1351 | wm8903->master_substream = wm8903->slave_substream; | |
1352 | ||
1353 | wm8903->slave_substream = NULL; | |
1354 | } | |
1355 | ||
1356 | static int wm8903_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
1357 | struct snd_pcm_hw_params *params, |
1358 | struct snd_soc_dai *dai) | |
f1c0a02f MB |
1359 | { |
1360 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1361 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 1362 | struct snd_soc_codec *codec = socdev->card->codec; |
f1c0a02f MB |
1363 | struct wm8903_priv *wm8903 = codec->private_data; |
1364 | struct i2c_client *i2c = codec->control_data; | |
1365 | int fs = params_rate(params); | |
1366 | int bclk; | |
1367 | int bclk_div; | |
1368 | int i; | |
1369 | int dsp_config; | |
1370 | int clk_config; | |
1371 | int best_val; | |
1372 | int cur_val; | |
1373 | int clk_sys; | |
1374 | ||
1375 | u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1); | |
1376 | u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2); | |
1377 | u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3); | |
1378 | u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0); | |
1379 | u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1); | |
1380 | ||
1381 | if (substream == wm8903->slave_substream) { | |
1382 | dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n"); | |
1383 | return 0; | |
1384 | } | |
1385 | ||
1386 | /* Configure sample rate logic for DSP - choose nearest rate */ | |
1387 | dsp_config = 0; | |
1388 | best_val = abs(sample_rates[dsp_config].rate - fs); | |
1389 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1390 | cur_val = abs(sample_rates[i].rate - fs); | |
1391 | if (cur_val <= best_val) { | |
1392 | dsp_config = i; | |
1393 | best_val = cur_val; | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | /* Constraints should stop us hitting this but let's make sure */ | |
1398 | if (wm8903->capture_active) | |
1399 | switch (sample_rates[dsp_config].rate) { | |
1400 | case 88200: | |
1401 | case 96000: | |
1402 | dev_err(&i2c->dev, "%dHz unsupported by ADC\n", | |
1403 | fs); | |
1404 | return -EINVAL; | |
1405 | ||
1406 | default: | |
1407 | break; | |
1408 | } | |
1409 | ||
1410 | dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); | |
1411 | clock1 &= ~WM8903_SAMPLE_RATE_MASK; | |
1412 | clock1 |= sample_rates[dsp_config].value; | |
1413 | ||
1414 | aif1 &= ~WM8903_AIF_WL_MASK; | |
1415 | bclk = 2 * fs; | |
1416 | switch (params_format(params)) { | |
1417 | case SNDRV_PCM_FORMAT_S16_LE: | |
1418 | bclk *= 16; | |
1419 | break; | |
1420 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1421 | bclk *= 20; | |
1422 | aif1 |= 0x4; | |
1423 | break; | |
1424 | case SNDRV_PCM_FORMAT_S24_LE: | |
1425 | bclk *= 24; | |
1426 | aif1 |= 0x8; | |
1427 | break; | |
1428 | case SNDRV_PCM_FORMAT_S32_LE: | |
1429 | bclk *= 32; | |
1430 | aif1 |= 0xc; | |
1431 | break; | |
1432 | default: | |
1433 | return -EINVAL; | |
1434 | } | |
1435 | ||
1436 | dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n", | |
1437 | wm8903->sysclk, fs); | |
1438 | ||
1439 | /* We may not have an MCLK which allows us to generate exactly | |
1440 | * the clock we want, particularly with USB derived inputs, so | |
1441 | * approximate. | |
1442 | */ | |
1443 | clk_config = 0; | |
1444 | best_val = abs((wm8903->sysclk / | |
1445 | (clk_sys_ratios[0].mclk_div * | |
1446 | clk_sys_ratios[0].div)) - fs); | |
1447 | for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { | |
1448 | cur_val = abs((wm8903->sysclk / | |
1449 | (clk_sys_ratios[i].mclk_div * | |
1450 | clk_sys_ratios[i].div)) - fs); | |
1451 | ||
1452 | if (cur_val <= best_val) { | |
1453 | clk_config = i; | |
1454 | best_val = cur_val; | |
1455 | } | |
1456 | } | |
1457 | ||
1458 | if (clk_sys_ratios[clk_config].mclk_div == 2) { | |
1459 | clock0 |= WM8903_MCLKDIV2; | |
1460 | clk_sys = wm8903->sysclk / 2; | |
1461 | } else { | |
1462 | clock0 &= ~WM8903_MCLKDIV2; | |
1463 | clk_sys = wm8903->sysclk; | |
1464 | } | |
1465 | ||
1466 | clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | | |
1467 | WM8903_CLK_SYS_MODE_MASK); | |
1468 | clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; | |
1469 | clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; | |
1470 | ||
1471 | dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", | |
1472 | clk_sys_ratios[clk_config].rate, | |
1473 | clk_sys_ratios[clk_config].mode, | |
1474 | clk_sys_ratios[clk_config].div); | |
1475 | ||
1476 | dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys); | |
1477 | ||
1478 | /* We may not get quite the right frequency if using | |
1479 | * approximate clocks so look for the closest match that is | |
1480 | * higher than the target (we need to ensure that there enough | |
1481 | * BCLKs to clock out the samples). | |
1482 | */ | |
1483 | bclk_div = 0; | |
1484 | best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; | |
1485 | i = 1; | |
1486 | while (i < ARRAY_SIZE(bclk_divs)) { | |
1487 | cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; | |
1488 | if (cur_val < 0) /* BCLK table is sorted */ | |
1489 | break; | |
1490 | bclk_div = i; | |
1491 | best_val = cur_val; | |
1492 | i++; | |
1493 | } | |
1494 | ||
1495 | aif2 &= ~WM8903_BCLK_DIV_MASK; | |
1496 | aif3 &= ~WM8903_LRCLK_RATE_MASK; | |
1497 | ||
1498 | dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", | |
1499 | bclk_divs[bclk_div].ratio / 10, bclk, | |
1500 | (clk_sys * 10) / bclk_divs[bclk_div].ratio); | |
1501 | ||
1502 | aif2 |= bclk_divs[bclk_div].div; | |
1503 | aif3 |= bclk / fs; | |
1504 | ||
1505 | wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0); | |
1506 | wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1); | |
1507 | wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); | |
1508 | wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); | |
1509 | wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); | |
1510 | ||
1511 | return 0; | |
1512 | } | |
1513 | ||
1514 | #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ | |
1515 | SNDRV_PCM_RATE_11025 | \ | |
1516 | SNDRV_PCM_RATE_16000 | \ | |
1517 | SNDRV_PCM_RATE_22050 | \ | |
1518 | SNDRV_PCM_RATE_32000 | \ | |
1519 | SNDRV_PCM_RATE_44100 | \ | |
1520 | SNDRV_PCM_RATE_48000 | \ | |
1521 | SNDRV_PCM_RATE_88200 | \ | |
1522 | SNDRV_PCM_RATE_96000) | |
1523 | ||
1524 | #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ | |
1525 | SNDRV_PCM_RATE_11025 | \ | |
1526 | SNDRV_PCM_RATE_16000 | \ | |
1527 | SNDRV_PCM_RATE_22050 | \ | |
1528 | SNDRV_PCM_RATE_32000 | \ | |
1529 | SNDRV_PCM_RATE_44100 | \ | |
1530 | SNDRV_PCM_RATE_48000) | |
1531 | ||
1532 | #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
1533 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1534 | SNDRV_PCM_FMTBIT_S24_LE) | |
1535 | ||
6335d055 EM |
1536 | static struct snd_soc_dai_ops wm8903_dai_ops = { |
1537 | .startup = wm8903_startup, | |
1538 | .shutdown = wm8903_shutdown, | |
1539 | .hw_params = wm8903_hw_params, | |
1540 | .digital_mute = wm8903_digital_mute, | |
1541 | .set_fmt = wm8903_set_dai_fmt, | |
1542 | .set_sysclk = wm8903_set_dai_sysclk, | |
1543 | }; | |
1544 | ||
f1c0a02f MB |
1545 | struct snd_soc_dai wm8903_dai = { |
1546 | .name = "WM8903", | |
1547 | .playback = { | |
1548 | .stream_name = "Playback", | |
1549 | .channels_min = 2, | |
1550 | .channels_max = 2, | |
1551 | .rates = WM8903_PLAYBACK_RATES, | |
1552 | .formats = WM8903_FORMATS, | |
1553 | }, | |
1554 | .capture = { | |
1555 | .stream_name = "Capture", | |
1556 | .channels_min = 2, | |
1557 | .channels_max = 2, | |
1558 | .rates = WM8903_CAPTURE_RATES, | |
1559 | .formats = WM8903_FORMATS, | |
1560 | }, | |
6335d055 | 1561 | .ops = &wm8903_dai_ops, |
0d960e88 | 1562 | .symmetric_rates = 1, |
f1c0a02f MB |
1563 | }; |
1564 | EXPORT_SYMBOL_GPL(wm8903_dai); | |
1565 | ||
1566 | static int wm8903_suspend(struct platform_device *pdev, pm_message_t state) | |
1567 | { | |
1568 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1569 | struct snd_soc_codec *codec = socdev->card->codec; |
f1c0a02f MB |
1570 | |
1571 | wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | static int wm8903_resume(struct platform_device *pdev) | |
1577 | { | |
1578 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1579 | struct snd_soc_codec *codec = socdev->card->codec; |
f1c0a02f MB |
1580 | struct i2c_client *i2c = codec->control_data; |
1581 | int i; | |
1582 | u16 *reg_cache = codec->reg_cache; | |
1583 | u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults), | |
1584 | GFP_KERNEL); | |
1585 | ||
1586 | /* Bring the codec back up to standby first to minimise pop/clicks */ | |
1587 | wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1588 | wm8903_set_bias_level(codec, codec->suspend_bias_level); | |
1589 | ||
1590 | /* Sync back everything else */ | |
1591 | if (tmp_cache) { | |
1592 | for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++) | |
1593 | if (tmp_cache[i] != reg_cache[i]) | |
1594 | wm8903_write(codec, i, tmp_cache[i]); | |
1595 | } else { | |
1596 | dev_err(&i2c->dev, "Failed to allocate temporary cache\n"); | |
1597 | } | |
1598 | ||
1599 | return 0; | |
1600 | } | |
1601 | ||
d58d5d55 MB |
1602 | static struct snd_soc_codec *wm8903_codec; |
1603 | ||
c6f29811 MB |
1604 | static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, |
1605 | const struct i2c_device_id *id) | |
f1c0a02f | 1606 | { |
d58d5d55 MB |
1607 | struct wm8903_priv *wm8903; |
1608 | struct snd_soc_codec *codec; | |
1609 | int ret; | |
f1c0a02f MB |
1610 | u16 val; |
1611 | ||
d58d5d55 MB |
1612 | wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL); |
1613 | if (wm8903 == NULL) | |
1614 | return -ENOMEM; | |
f1c0a02f | 1615 | |
d58d5d55 MB |
1616 | codec = &wm8903->codec; |
1617 | ||
1618 | mutex_init(&codec->mutex); | |
1619 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
1620 | INIT_LIST_HEAD(&codec->dapm_paths); | |
1621 | ||
1622 | codec->dev = &i2c->dev; | |
f1c0a02f MB |
1623 | codec->name = "WM8903"; |
1624 | codec->owner = THIS_MODULE; | |
1625 | codec->read = wm8903_read; | |
1626 | codec->write = wm8903_write; | |
d58d5d55 | 1627 | codec->hw_write = (hw_write_t)i2c_master_send; |
f1c0a02f MB |
1628 | codec->bias_level = SND_SOC_BIAS_OFF; |
1629 | codec->set_bias_level = wm8903_set_bias_level; | |
1630 | codec->dai = &wm8903_dai; | |
1631 | codec->num_dai = 1; | |
d58d5d55 MB |
1632 | codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache); |
1633 | codec->reg_cache = &wm8903->reg_cache[0]; | |
1634 | codec->private_data = wm8903; | |
1635 | ||
1636 | i2c_set_clientdata(i2c, codec); | |
1637 | codec->control_data = i2c; | |
1638 | ||
1639 | val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID); | |
1640 | if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) { | |
1641 | dev_err(&i2c->dev, | |
1642 | "Device with ID register %x is not a WM8903\n", val); | |
1643 | return -ENODEV; | |
f1c0a02f MB |
1644 | } |
1645 | ||
1646 | val = wm8903_read(codec, WM8903_REVISION_NUMBER); | |
1647 | dev_info(&i2c->dev, "WM8903 revision %d\n", | |
1648 | val & WM8903_CHIP_REV_MASK); | |
1649 | ||
1650 | wm8903_reset(codec); | |
1651 | ||
f1c0a02f MB |
1652 | /* power on device */ |
1653 | wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1654 | ||
1655 | /* Latch volume update bits */ | |
1656 | val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); | |
1657 | val |= WM8903_ADCVU; | |
1658 | wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); | |
1659 | wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); | |
1660 | ||
1661 | val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); | |
1662 | val |= WM8903_DACVU; | |
1663 | wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); | |
1664 | wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); | |
1665 | ||
1666 | val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT); | |
1667 | val |= WM8903_HPOUTVU; | |
1668 | wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); | |
1669 | wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); | |
1670 | ||
1671 | val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT); | |
1672 | val |= WM8903_LINEOUTVU; | |
1673 | wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); | |
1674 | wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); | |
1675 | ||
1676 | val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT); | |
1677 | val |= WM8903_SPKVU; | |
1678 | wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); | |
1679 | wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); | |
1680 | ||
1681 | /* Enable DAC soft mute by default */ | |
1682 | val = wm8903_read(codec, WM8903_DAC_DIGITAL_1); | |
1683 | val |= WM8903_DAC_MUTEMODE; | |
1684 | wm8903_write(codec, WM8903_DAC_DIGITAL_1, val); | |
1685 | ||
d58d5d55 MB |
1686 | wm8903_dai.dev = &i2c->dev; |
1687 | wm8903_codec = codec; | |
1688 | ||
1689 | ret = snd_soc_register_codec(codec); | |
1690 | if (ret != 0) { | |
1691 | dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); | |
1692 | goto err; | |
1693 | } | |
1694 | ||
1695 | ret = snd_soc_register_dai(&wm8903_dai); | |
1696 | if (ret != 0) { | |
1697 | dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret); | |
1698 | goto err_codec; | |
f1c0a02f MB |
1699 | } |
1700 | ||
1701 | return ret; | |
1702 | ||
d58d5d55 MB |
1703 | err_codec: |
1704 | snd_soc_unregister_codec(codec); | |
1705 | err: | |
1706 | wm8903_codec = NULL; | |
1707 | kfree(wm8903); | |
f1c0a02f MB |
1708 | return ret; |
1709 | } | |
1710 | ||
c6f29811 | 1711 | static __devexit int wm8903_i2c_remove(struct i2c_client *client) |
f1c0a02f | 1712 | { |
d58d5d55 | 1713 | struct snd_soc_codec *codec = i2c_get_clientdata(client); |
f1c0a02f | 1714 | |
d58d5d55 MB |
1715 | snd_soc_unregister_dai(&wm8903_dai); |
1716 | snd_soc_unregister_codec(codec); | |
f1c0a02f | 1717 | |
d58d5d55 | 1718 | wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); |
f1c0a02f | 1719 | |
d58d5d55 MB |
1720 | kfree(codec->private_data); |
1721 | ||
1722 | wm8903_codec = NULL; | |
1723 | wm8903_dai.dev = NULL; | |
f1c0a02f | 1724 | |
f1c0a02f MB |
1725 | return 0; |
1726 | } | |
1727 | ||
1728 | /* i2c codec control layer */ | |
1729 | static const struct i2c_device_id wm8903_i2c_id[] = { | |
1730 | { "wm8903", 0 }, | |
1731 | { } | |
1732 | }; | |
1733 | MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); | |
1734 | ||
1735 | static struct i2c_driver wm8903_i2c_driver = { | |
1736 | .driver = { | |
1737 | .name = "WM8903", | |
1738 | .owner = THIS_MODULE, | |
1739 | }, | |
1740 | .probe = wm8903_i2c_probe, | |
c6f29811 | 1741 | .remove = __devexit_p(wm8903_i2c_remove), |
f1c0a02f MB |
1742 | .id_table = wm8903_i2c_id, |
1743 | }; | |
1744 | ||
f1c0a02f MB |
1745 | static int wm8903_probe(struct platform_device *pdev) |
1746 | { | |
1747 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
f1c0a02f MB |
1748 | int ret = 0; |
1749 | ||
d58d5d55 MB |
1750 | if (!wm8903_codec) { |
1751 | dev_err(&pdev->dev, "I2C device not yet probed\n"); | |
1752 | goto err; | |
f1c0a02f MB |
1753 | } |
1754 | ||
6627a653 | 1755 | socdev->card->codec = wm8903_codec; |
f1c0a02f | 1756 | |
d58d5d55 MB |
1757 | /* register pcms */ |
1758 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
1759 | if (ret < 0) { | |
1760 | dev_err(&pdev->dev, "failed to create pcms\n"); | |
1761 | goto err; | |
f1c0a02f MB |
1762 | } |
1763 | ||
6627a653 | 1764 | snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls, |
3e8e1952 | 1765 | ARRAY_SIZE(wm8903_snd_controls)); |
6627a653 | 1766 | wm8903_add_widgets(socdev->card->codec); |
f1c0a02f | 1767 | |
d58d5d55 MB |
1768 | ret = snd_soc_init_card(socdev); |
1769 | if (ret < 0) { | |
1770 | dev_err(&pdev->dev, "wm8903: failed to register card\n"); | |
1771 | goto card_err; | |
f1c0a02f MB |
1772 | } |
1773 | ||
1774 | return ret; | |
1775 | ||
d58d5d55 MB |
1776 | card_err: |
1777 | snd_soc_free_pcms(socdev); | |
1778 | snd_soc_dapm_free(socdev); | |
1779 | err: | |
f1c0a02f MB |
1780 | return ret; |
1781 | } | |
1782 | ||
1783 | /* power down chip */ | |
1784 | static int wm8903_remove(struct platform_device *pdev) | |
1785 | { | |
1786 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1787 | struct snd_soc_codec *codec = socdev->card->codec; |
f1c0a02f MB |
1788 | |
1789 | if (codec->control_data) | |
1790 | wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1791 | ||
1792 | snd_soc_free_pcms(socdev); | |
1793 | snd_soc_dapm_free(socdev); | |
f1c0a02f MB |
1794 | |
1795 | return 0; | |
1796 | } | |
1797 | ||
1798 | struct snd_soc_codec_device soc_codec_dev_wm8903 = { | |
1799 | .probe = wm8903_probe, | |
1800 | .remove = wm8903_remove, | |
1801 | .suspend = wm8903_suspend, | |
1802 | .resume = wm8903_resume, | |
1803 | }; | |
1804 | EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903); | |
1805 | ||
c9b3a40f | 1806 | static int __init wm8903_modinit(void) |
64089b84 | 1807 | { |
d58d5d55 | 1808 | return i2c_add_driver(&wm8903_i2c_driver); |
64089b84 MB |
1809 | } |
1810 | module_init(wm8903_modinit); | |
1811 | ||
1812 | static void __exit wm8903_exit(void) | |
1813 | { | |
d58d5d55 | 1814 | i2c_del_driver(&wm8903_i2c_driver); |
64089b84 MB |
1815 | } |
1816 | module_exit(wm8903_exit); | |
1817 | ||
f1c0a02f MB |
1818 | MODULE_DESCRIPTION("ASoC WM8903 driver"); |
1819 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); | |
1820 | MODULE_LICENSE("GPL"); |