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1 | /* |
2 | * wm8904.c -- WM8904 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/i2c.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/consumer.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
a91eb199 MB |
23 | #include <sound/core.h> |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
27 | #include <sound/soc-dapm.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/tlv.h> | |
30 | #include <sound/wm8904.h> | |
31 | ||
32 | #include "wm8904.h" | |
33 | ||
8c126474 MB |
34 | enum wm8904_type { |
35 | WM8904, | |
36 | WM8912, | |
37 | }; | |
38 | ||
a91eb199 MB |
39 | #define WM8904_NUM_DCS_CHANNELS 4 |
40 | ||
41 | #define WM8904_NUM_SUPPLIES 5 | |
42 | static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { | |
43 | "DCVDD", | |
44 | "DBVDD", | |
45 | "AVDD", | |
46 | "CPVDD", | |
47 | "MICVDD", | |
48 | }; | |
49 | ||
50 | /* codec private data */ | |
51 | struct wm8904_priv { | |
f0fba2ad | 52 | |
a91eb199 MB |
53 | u16 reg_cache[WM8904_MAX_REGISTER + 1]; |
54 | ||
8c126474 | 55 | enum wm8904_type devtype; |
f0fba2ad | 56 | void *control_data; |
8c126474 | 57 | |
a91eb199 MB |
58 | struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; |
59 | ||
60 | struct wm8904_pdata *pdata; | |
61 | ||
62 | int deemph; | |
63 | ||
64 | /* Platform provided DRC configuration */ | |
65 | const char **drc_texts; | |
66 | int drc_cfg; | |
67 | struct soc_enum drc_enum; | |
68 | ||
69 | /* Platform provided ReTune mobile configuration */ | |
70 | int num_retune_mobile_texts; | |
71 | const char **retune_mobile_texts; | |
72 | int retune_mobile_cfg; | |
73 | struct soc_enum retune_mobile_enum; | |
74 | ||
75 | /* FLL setup */ | |
76 | int fll_src; | |
77 | int fll_fref; | |
78 | int fll_fout; | |
79 | ||
80 | /* Clocking configuration */ | |
81 | unsigned int mclk_rate; | |
82 | int sysclk_src; | |
83 | unsigned int sysclk_rate; | |
84 | ||
85 | int tdm_width; | |
86 | int tdm_slots; | |
87 | int bclk; | |
88 | int fs; | |
89 | ||
90 | /* DC servo configuration - cached offset values */ | |
91 | int dcs_state[WM8904_NUM_DCS_CHANNELS]; | |
92 | }; | |
93 | ||
94 | static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = { | |
95 | 0x8904, /* R0 - SW Reset and ID */ | |
96 | 0x0000, /* R1 - Revision */ | |
97 | 0x0000, /* R2 */ | |
98 | 0x0000, /* R3 */ | |
99 | 0x0018, /* R4 - Bias Control 0 */ | |
100 | 0x0000, /* R5 - VMID Control 0 */ | |
101 | 0x0000, /* R6 - Mic Bias Control 0 */ | |
102 | 0x0000, /* R7 - Mic Bias Control 1 */ | |
103 | 0x0001, /* R8 - Analogue DAC 0 */ | |
104 | 0x9696, /* R9 - mic Filter Control */ | |
105 | 0x0001, /* R10 - Analogue ADC 0 */ | |
106 | 0x0000, /* R11 */ | |
107 | 0x0000, /* R12 - Power Management 0 */ | |
108 | 0x0000, /* R13 */ | |
109 | 0x0000, /* R14 - Power Management 2 */ | |
110 | 0x0000, /* R15 - Power Management 3 */ | |
111 | 0x0000, /* R16 */ | |
112 | 0x0000, /* R17 */ | |
113 | 0x0000, /* R18 - Power Management 6 */ | |
114 | 0x0000, /* R19 */ | |
115 | 0x945E, /* R20 - Clock Rates 0 */ | |
116 | 0x0C05, /* R21 - Clock Rates 1 */ | |
117 | 0x0006, /* R22 - Clock Rates 2 */ | |
118 | 0x0000, /* R23 */ | |
119 | 0x0050, /* R24 - Audio Interface 0 */ | |
120 | 0x000A, /* R25 - Audio Interface 1 */ | |
121 | 0x00E4, /* R26 - Audio Interface 2 */ | |
122 | 0x0040, /* R27 - Audio Interface 3 */ | |
123 | 0x0000, /* R28 */ | |
124 | 0x0000, /* R29 */ | |
125 | 0x00C0, /* R30 - DAC Digital Volume Left */ | |
126 | 0x00C0, /* R31 - DAC Digital Volume Right */ | |
127 | 0x0000, /* R32 - DAC Digital 0 */ | |
128 | 0x0008, /* R33 - DAC Digital 1 */ | |
129 | 0x0000, /* R34 */ | |
130 | 0x0000, /* R35 */ | |
131 | 0x00C0, /* R36 - ADC Digital Volume Left */ | |
132 | 0x00C0, /* R37 - ADC Digital Volume Right */ | |
133 | 0x0010, /* R38 - ADC Digital 0 */ | |
134 | 0x0000, /* R39 - Digital Microphone 0 */ | |
135 | 0x01AF, /* R40 - DRC 0 */ | |
136 | 0x3248, /* R41 - DRC 1 */ | |
137 | 0x0000, /* R42 - DRC 2 */ | |
138 | 0x0000, /* R43 - DRC 3 */ | |
139 | 0x0085, /* R44 - Analogue Left Input 0 */ | |
140 | 0x0085, /* R45 - Analogue Right Input 0 */ | |
141 | 0x0044, /* R46 - Analogue Left Input 1 */ | |
142 | 0x0044, /* R47 - Analogue Right Input 1 */ | |
143 | 0x0000, /* R48 */ | |
144 | 0x0000, /* R49 */ | |
145 | 0x0000, /* R50 */ | |
146 | 0x0000, /* R51 */ | |
147 | 0x0000, /* R52 */ | |
148 | 0x0000, /* R53 */ | |
149 | 0x0000, /* R54 */ | |
150 | 0x0000, /* R55 */ | |
151 | 0x0000, /* R56 */ | |
152 | 0x002D, /* R57 - Analogue OUT1 Left */ | |
153 | 0x002D, /* R58 - Analogue OUT1 Right */ | |
154 | 0x0039, /* R59 - Analogue OUT2 Left */ | |
155 | 0x0039, /* R60 - Analogue OUT2 Right */ | |
156 | 0x0000, /* R61 - Analogue OUT12 ZC */ | |
157 | 0x0000, /* R62 */ | |
158 | 0x0000, /* R63 */ | |
159 | 0x0000, /* R64 */ | |
160 | 0x0000, /* R65 */ | |
161 | 0x0000, /* R66 */ | |
162 | 0x0000, /* R67 - DC Servo 0 */ | |
163 | 0x0000, /* R68 - DC Servo 1 */ | |
164 | 0xAAAA, /* R69 - DC Servo 2 */ | |
165 | 0x0000, /* R70 */ | |
166 | 0xAAAA, /* R71 - DC Servo 4 */ | |
167 | 0xAAAA, /* R72 - DC Servo 5 */ | |
168 | 0x0000, /* R73 - DC Servo 6 */ | |
169 | 0x0000, /* R74 - DC Servo 7 */ | |
170 | 0x0000, /* R75 - DC Servo 8 */ | |
171 | 0x0000, /* R76 - DC Servo 9 */ | |
172 | 0x0000, /* R77 - DC Servo Readback 0 */ | |
173 | 0x0000, /* R78 */ | |
174 | 0x0000, /* R79 */ | |
175 | 0x0000, /* R80 */ | |
176 | 0x0000, /* R81 */ | |
177 | 0x0000, /* R82 */ | |
178 | 0x0000, /* R83 */ | |
179 | 0x0000, /* R84 */ | |
180 | 0x0000, /* R85 */ | |
181 | 0x0000, /* R86 */ | |
182 | 0x0000, /* R87 */ | |
183 | 0x0000, /* R88 */ | |
184 | 0x0000, /* R89 */ | |
185 | 0x0000, /* R90 - Analogue HP 0 */ | |
186 | 0x0000, /* R91 */ | |
187 | 0x0000, /* R92 */ | |
188 | 0x0000, /* R93 */ | |
189 | 0x0000, /* R94 - Analogue Lineout 0 */ | |
190 | 0x0000, /* R95 */ | |
191 | 0x0000, /* R96 */ | |
192 | 0x0000, /* R97 */ | |
193 | 0x0000, /* R98 - Charge Pump 0 */ | |
194 | 0x0000, /* R99 */ | |
195 | 0x0000, /* R100 */ | |
196 | 0x0000, /* R101 */ | |
197 | 0x0000, /* R102 */ | |
198 | 0x0000, /* R103 */ | |
199 | 0x0004, /* R104 - Class W 0 */ | |
200 | 0x0000, /* R105 */ | |
201 | 0x0000, /* R106 */ | |
202 | 0x0000, /* R107 */ | |
203 | 0x0000, /* R108 - Write Sequencer 0 */ | |
204 | 0x0000, /* R109 - Write Sequencer 1 */ | |
205 | 0x0000, /* R110 - Write Sequencer 2 */ | |
206 | 0x0000, /* R111 - Write Sequencer 3 */ | |
207 | 0x0000, /* R112 - Write Sequencer 4 */ | |
208 | 0x0000, /* R113 */ | |
209 | 0x0000, /* R114 */ | |
210 | 0x0000, /* R115 */ | |
211 | 0x0000, /* R116 - FLL Control 1 */ | |
212 | 0x0007, /* R117 - FLL Control 2 */ | |
213 | 0x0000, /* R118 - FLL Control 3 */ | |
214 | 0x2EE0, /* R119 - FLL Control 4 */ | |
215 | 0x0004, /* R120 - FLL Control 5 */ | |
216 | 0x0014, /* R121 - GPIO Control 1 */ | |
217 | 0x0010, /* R122 - GPIO Control 2 */ | |
218 | 0x0010, /* R123 - GPIO Control 3 */ | |
219 | 0x0000, /* R124 - GPIO Control 4 */ | |
220 | 0x0000, /* R125 */ | |
221 | 0x0000, /* R126 - Digital Pulls */ | |
222 | 0x0000, /* R127 - Interrupt Status */ | |
223 | 0xFFFF, /* R128 - Interrupt Status Mask */ | |
224 | 0x0000, /* R129 - Interrupt Polarity */ | |
225 | 0x0000, /* R130 - Interrupt Debounce */ | |
226 | 0x0000, /* R131 */ | |
227 | 0x0000, /* R132 */ | |
228 | 0x0000, /* R133 */ | |
229 | 0x0000, /* R134 - EQ1 */ | |
230 | 0x000C, /* R135 - EQ2 */ | |
231 | 0x000C, /* R136 - EQ3 */ | |
232 | 0x000C, /* R137 - EQ4 */ | |
233 | 0x000C, /* R138 - EQ5 */ | |
234 | 0x000C, /* R139 - EQ6 */ | |
235 | 0x0FCA, /* R140 - EQ7 */ | |
236 | 0x0400, /* R141 - EQ8 */ | |
237 | 0x00D8, /* R142 - EQ9 */ | |
238 | 0x1EB5, /* R143 - EQ10 */ | |
239 | 0xF145, /* R144 - EQ11 */ | |
240 | 0x0B75, /* R145 - EQ12 */ | |
241 | 0x01C5, /* R146 - EQ13 */ | |
242 | 0x1C58, /* R147 - EQ14 */ | |
243 | 0xF373, /* R148 - EQ15 */ | |
244 | 0x0A54, /* R149 - EQ16 */ | |
245 | 0x0558, /* R150 - EQ17 */ | |
246 | 0x168E, /* R151 - EQ18 */ | |
247 | 0xF829, /* R152 - EQ19 */ | |
248 | 0x07AD, /* R153 - EQ20 */ | |
249 | 0x1103, /* R154 - EQ21 */ | |
250 | 0x0564, /* R155 - EQ22 */ | |
251 | 0x0559, /* R156 - EQ23 */ | |
252 | 0x4000, /* R157 - EQ24 */ | |
253 | 0x0000, /* R158 */ | |
254 | 0x0000, /* R159 */ | |
255 | 0x0000, /* R160 */ | |
256 | 0x0000, /* R161 - Control Interface Test 1 */ | |
257 | 0x0000, /* R162 */ | |
258 | 0x0000, /* R163 */ | |
259 | 0x0000, /* R164 */ | |
260 | 0x0000, /* R165 */ | |
261 | 0x0000, /* R166 */ | |
262 | 0x0000, /* R167 */ | |
263 | 0x0000, /* R168 */ | |
264 | 0x0000, /* R169 */ | |
265 | 0x0000, /* R170 */ | |
266 | 0x0000, /* R171 */ | |
267 | 0x0000, /* R172 */ | |
268 | 0x0000, /* R173 */ | |
269 | 0x0000, /* R174 */ | |
270 | 0x0000, /* R175 */ | |
271 | 0x0000, /* R176 */ | |
272 | 0x0000, /* R177 */ | |
273 | 0x0000, /* R178 */ | |
274 | 0x0000, /* R179 */ | |
275 | 0x0000, /* R180 */ | |
276 | 0x0000, /* R181 */ | |
277 | 0x0000, /* R182 */ | |
278 | 0x0000, /* R183 */ | |
279 | 0x0000, /* R184 */ | |
280 | 0x0000, /* R185 */ | |
281 | 0x0000, /* R186 */ | |
282 | 0x0000, /* R187 */ | |
283 | 0x0000, /* R188 */ | |
284 | 0x0000, /* R189 */ | |
285 | 0x0000, /* R190 */ | |
286 | 0x0000, /* R191 */ | |
287 | 0x0000, /* R192 */ | |
288 | 0x0000, /* R193 */ | |
289 | 0x0000, /* R194 */ | |
290 | 0x0000, /* R195 */ | |
291 | 0x0000, /* R196 */ | |
292 | 0x0000, /* R197 */ | |
293 | 0x0000, /* R198 */ | |
294 | 0x0000, /* R199 */ | |
295 | 0x0000, /* R200 */ | |
296 | 0x0000, /* R201 */ | |
297 | 0x0000, /* R202 */ | |
298 | 0x0000, /* R203 */ | |
299 | 0x0000, /* R204 - Analogue Output Bias 0 */ | |
300 | 0x0000, /* R205 */ | |
301 | 0x0000, /* R206 */ | |
302 | 0x0000, /* R207 */ | |
303 | 0x0000, /* R208 */ | |
304 | 0x0000, /* R209 */ | |
305 | 0x0000, /* R210 */ | |
306 | 0x0000, /* R211 */ | |
307 | 0x0000, /* R212 */ | |
308 | 0x0000, /* R213 */ | |
309 | 0x0000, /* R214 */ | |
310 | 0x0000, /* R215 */ | |
311 | 0x0000, /* R216 */ | |
312 | 0x0000, /* R217 */ | |
313 | 0x0000, /* R218 */ | |
314 | 0x0000, /* R219 */ | |
315 | 0x0000, /* R220 */ | |
316 | 0x0000, /* R221 */ | |
317 | 0x0000, /* R222 */ | |
318 | 0x0000, /* R223 */ | |
319 | 0x0000, /* R224 */ | |
320 | 0x0000, /* R225 */ | |
321 | 0x0000, /* R226 */ | |
322 | 0x0000, /* R227 */ | |
323 | 0x0000, /* R228 */ | |
324 | 0x0000, /* R229 */ | |
325 | 0x0000, /* R230 */ | |
326 | 0x0000, /* R231 */ | |
327 | 0x0000, /* R232 */ | |
328 | 0x0000, /* R233 */ | |
329 | 0x0000, /* R234 */ | |
330 | 0x0000, /* R235 */ | |
331 | 0x0000, /* R236 */ | |
332 | 0x0000, /* R237 */ | |
333 | 0x0000, /* R238 */ | |
334 | 0x0000, /* R239 */ | |
335 | 0x0000, /* R240 */ | |
336 | 0x0000, /* R241 */ | |
337 | 0x0000, /* R242 */ | |
338 | 0x0000, /* R243 */ | |
339 | 0x0000, /* R244 */ | |
340 | 0x0000, /* R245 */ | |
341 | 0x0000, /* R246 */ | |
342 | 0x0000, /* R247 - FLL NCO Test 0 */ | |
343 | 0x0019, /* R248 - FLL NCO Test 1 */ | |
344 | }; | |
345 | ||
346 | static struct { | |
347 | int readable; | |
348 | int writable; | |
349 | int vol; | |
350 | } wm8904_access[] = { | |
351 | { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */ | |
352 | { 0x0000, 0x0000, 0 }, /* R1 - Revision */ | |
353 | { 0x0000, 0x0000, 0 }, /* R2 */ | |
354 | { 0x0000, 0x0000, 0 }, /* R3 */ | |
355 | { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */ | |
356 | { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */ | |
357 | { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */ | |
358 | { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */ | |
359 | { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */ | |
360 | { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */ | |
361 | { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */ | |
362 | { 0x0000, 0x0000, 0 }, /* R11 */ | |
363 | { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */ | |
364 | { 0x0000, 0x0000, 0 }, /* R13 */ | |
365 | { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */ | |
366 | { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */ | |
367 | { 0x0000, 0x0000, 0 }, /* R16 */ | |
368 | { 0x0000, 0x0000, 0 }, /* R17 */ | |
369 | { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */ | |
370 | { 0x0000, 0x0000, 0 }, /* R19 */ | |
371 | { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */ | |
372 | { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */ | |
373 | { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */ | |
374 | { 0x0000, 0x0000, 0 }, /* R23 */ | |
375 | { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */ | |
376 | { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */ | |
377 | { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */ | |
378 | { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */ | |
379 | { 0x0000, 0x0000, 0 }, /* R28 */ | |
380 | { 0x0000, 0x0000, 0 }, /* R29 */ | |
381 | { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */ | |
382 | { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */ | |
383 | { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */ | |
384 | { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */ | |
385 | { 0x0000, 0x0000, 0 }, /* R34 */ | |
386 | { 0x0000, 0x0000, 0 }, /* R35 */ | |
387 | { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */ | |
388 | { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */ | |
389 | { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */ | |
390 | { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */ | |
391 | { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */ | |
392 | { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */ | |
393 | { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */ | |
394 | { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */ | |
395 | { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */ | |
396 | { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */ | |
397 | { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */ | |
398 | { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */ | |
399 | { 0x0000, 0x0000, 0 }, /* R48 */ | |
400 | { 0x0000, 0x0000, 0 }, /* R49 */ | |
401 | { 0x0000, 0x0000, 0 }, /* R50 */ | |
402 | { 0x0000, 0x0000, 0 }, /* R51 */ | |
403 | { 0x0000, 0x0000, 0 }, /* R52 */ | |
404 | { 0x0000, 0x0000, 0 }, /* R53 */ | |
405 | { 0x0000, 0x0000, 0 }, /* R54 */ | |
406 | { 0x0000, 0x0000, 0 }, /* R55 */ | |
407 | { 0x0000, 0x0000, 0 }, /* R56 */ | |
408 | { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */ | |
409 | { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */ | |
410 | { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */ | |
411 | { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */ | |
412 | { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */ | |
413 | { 0x0000, 0x0000, 0 }, /* R62 */ | |
414 | { 0x0000, 0x0000, 0 }, /* R63 */ | |
415 | { 0x0000, 0x0000, 0 }, /* R64 */ | |
416 | { 0x0000, 0x0000, 0 }, /* R65 */ | |
417 | { 0x0000, 0x0000, 0 }, /* R66 */ | |
418 | { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */ | |
419 | { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */ | |
420 | { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */ | |
421 | { 0x0000, 0x0000, 0 }, /* R70 */ | |
422 | { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */ | |
423 | { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */ | |
424 | { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */ | |
425 | { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */ | |
426 | { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */ | |
427 | { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */ | |
428 | { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */ | |
429 | { 0x0000, 0x0000, 0 }, /* R78 */ | |
430 | { 0x0000, 0x0000, 0 }, /* R79 */ | |
431 | { 0x0000, 0x0000, 0 }, /* R80 */ | |
432 | { 0x0000, 0x0000, 0 }, /* R81 */ | |
433 | { 0x0000, 0x0000, 0 }, /* R82 */ | |
434 | { 0x0000, 0x0000, 0 }, /* R83 */ | |
435 | { 0x0000, 0x0000, 0 }, /* R84 */ | |
436 | { 0x0000, 0x0000, 0 }, /* R85 */ | |
437 | { 0x0000, 0x0000, 0 }, /* R86 */ | |
438 | { 0x0000, 0x0000, 0 }, /* R87 */ | |
439 | { 0x0000, 0x0000, 0 }, /* R88 */ | |
440 | { 0x0000, 0x0000, 0 }, /* R89 */ | |
441 | { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */ | |
442 | { 0x0000, 0x0000, 0 }, /* R91 */ | |
443 | { 0x0000, 0x0000, 0 }, /* R92 */ | |
444 | { 0x0000, 0x0000, 0 }, /* R93 */ | |
445 | { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */ | |
446 | { 0x0000, 0x0000, 0 }, /* R95 */ | |
447 | { 0x0000, 0x0000, 0 }, /* R96 */ | |
448 | { 0x0000, 0x0000, 0 }, /* R97 */ | |
449 | { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */ | |
450 | { 0x0000, 0x0000, 0 }, /* R99 */ | |
451 | { 0x0000, 0x0000, 0 }, /* R100 */ | |
452 | { 0x0000, 0x0000, 0 }, /* R101 */ | |
453 | { 0x0000, 0x0000, 0 }, /* R102 */ | |
454 | { 0x0000, 0x0000, 0 }, /* R103 */ | |
455 | { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */ | |
456 | { 0x0000, 0x0000, 0 }, /* R105 */ | |
457 | { 0x0000, 0x0000, 0 }, /* R106 */ | |
458 | { 0x0000, 0x0000, 0 }, /* R107 */ | |
459 | { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */ | |
460 | { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */ | |
461 | { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */ | |
462 | { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */ | |
463 | { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */ | |
464 | { 0x0000, 0x0000, 0 }, /* R113 */ | |
465 | { 0x0000, 0x0000, 0 }, /* R114 */ | |
466 | { 0x0000, 0x0000, 0 }, /* R115 */ | |
467 | { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */ | |
468 | { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */ | |
469 | { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */ | |
470 | { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */ | |
471 | { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */ | |
472 | { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */ | |
473 | { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */ | |
474 | { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */ | |
475 | { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */ | |
476 | { 0x0000, 0x0000, 0 }, /* R125 */ | |
477 | { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */ | |
478 | { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */ | |
479 | { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */ | |
480 | { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */ | |
481 | { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */ | |
482 | { 0x0000, 0x0000, 0 }, /* R131 */ | |
483 | { 0x0000, 0x0000, 0 }, /* R132 */ | |
484 | { 0x0000, 0x0000, 0 }, /* R133 */ | |
485 | { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */ | |
486 | { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */ | |
487 | { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */ | |
488 | { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */ | |
489 | { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */ | |
490 | { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */ | |
491 | { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */ | |
492 | { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */ | |
493 | { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */ | |
494 | { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */ | |
495 | { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */ | |
496 | { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */ | |
497 | { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */ | |
498 | { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */ | |
499 | { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */ | |
500 | { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */ | |
501 | { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */ | |
502 | { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */ | |
503 | { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */ | |
504 | { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */ | |
505 | { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */ | |
506 | { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */ | |
507 | { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */ | |
508 | { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */ | |
509 | { 0x0000, 0x0000, 0 }, /* R158 */ | |
510 | { 0x0000, 0x0000, 0 }, /* R159 */ | |
511 | { 0x0000, 0x0000, 0 }, /* R160 */ | |
512 | { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */ | |
513 | { 0x0000, 0x0000, 0 }, /* R162 */ | |
514 | { 0x0000, 0x0000, 0 }, /* R163 */ | |
515 | { 0x0000, 0x0000, 0 }, /* R164 */ | |
516 | { 0x0000, 0x0000, 0 }, /* R165 */ | |
517 | { 0x0000, 0x0000, 0 }, /* R166 */ | |
518 | { 0x0000, 0x0000, 0 }, /* R167 */ | |
519 | { 0x0000, 0x0000, 0 }, /* R168 */ | |
520 | { 0x0000, 0x0000, 0 }, /* R169 */ | |
521 | { 0x0000, 0x0000, 0 }, /* R170 */ | |
522 | { 0x0000, 0x0000, 0 }, /* R171 */ | |
523 | { 0x0000, 0x0000, 0 }, /* R172 */ | |
524 | { 0x0000, 0x0000, 0 }, /* R173 */ | |
525 | { 0x0000, 0x0000, 0 }, /* R174 */ | |
526 | { 0x0000, 0x0000, 0 }, /* R175 */ | |
527 | { 0x0000, 0x0000, 0 }, /* R176 */ | |
528 | { 0x0000, 0x0000, 0 }, /* R177 */ | |
529 | { 0x0000, 0x0000, 0 }, /* R178 */ | |
530 | { 0x0000, 0x0000, 0 }, /* R179 */ | |
531 | { 0x0000, 0x0000, 0 }, /* R180 */ | |
532 | { 0x0000, 0x0000, 0 }, /* R181 */ | |
533 | { 0x0000, 0x0000, 0 }, /* R182 */ | |
534 | { 0x0000, 0x0000, 0 }, /* R183 */ | |
535 | { 0x0000, 0x0000, 0 }, /* R184 */ | |
536 | { 0x0000, 0x0000, 0 }, /* R185 */ | |
537 | { 0x0000, 0x0000, 0 }, /* R186 */ | |
538 | { 0x0000, 0x0000, 0 }, /* R187 */ | |
539 | { 0x0000, 0x0000, 0 }, /* R188 */ | |
540 | { 0x0000, 0x0000, 0 }, /* R189 */ | |
541 | { 0x0000, 0x0000, 0 }, /* R190 */ | |
542 | { 0x0000, 0x0000, 0 }, /* R191 */ | |
543 | { 0x0000, 0x0000, 0 }, /* R192 */ | |
544 | { 0x0000, 0x0000, 0 }, /* R193 */ | |
545 | { 0x0000, 0x0000, 0 }, /* R194 */ | |
546 | { 0x0000, 0x0000, 0 }, /* R195 */ | |
547 | { 0x0000, 0x0000, 0 }, /* R196 */ | |
548 | { 0x0000, 0x0000, 0 }, /* R197 */ | |
549 | { 0x0000, 0x0000, 0 }, /* R198 */ | |
550 | { 0x0000, 0x0000, 0 }, /* R199 */ | |
551 | { 0x0000, 0x0000, 0 }, /* R200 */ | |
552 | { 0x0000, 0x0000, 0 }, /* R201 */ | |
553 | { 0x0000, 0x0000, 0 }, /* R202 */ | |
554 | { 0x0000, 0x0000, 0 }, /* R203 */ | |
555 | { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */ | |
556 | { 0x0000, 0x0000, 0 }, /* R205 */ | |
557 | { 0x0000, 0x0000, 0 }, /* R206 */ | |
558 | { 0x0000, 0x0000, 0 }, /* R207 */ | |
559 | { 0x0000, 0x0000, 0 }, /* R208 */ | |
560 | { 0x0000, 0x0000, 0 }, /* R209 */ | |
561 | { 0x0000, 0x0000, 0 }, /* R210 */ | |
562 | { 0x0000, 0x0000, 0 }, /* R211 */ | |
563 | { 0x0000, 0x0000, 0 }, /* R212 */ | |
564 | { 0x0000, 0x0000, 0 }, /* R213 */ | |
565 | { 0x0000, 0x0000, 0 }, /* R214 */ | |
566 | { 0x0000, 0x0000, 0 }, /* R215 */ | |
567 | { 0x0000, 0x0000, 0 }, /* R216 */ | |
568 | { 0x0000, 0x0000, 0 }, /* R217 */ | |
569 | { 0x0000, 0x0000, 0 }, /* R218 */ | |
570 | { 0x0000, 0x0000, 0 }, /* R219 */ | |
571 | { 0x0000, 0x0000, 0 }, /* R220 */ | |
572 | { 0x0000, 0x0000, 0 }, /* R221 */ | |
573 | { 0x0000, 0x0000, 0 }, /* R222 */ | |
574 | { 0x0000, 0x0000, 0 }, /* R223 */ | |
575 | { 0x0000, 0x0000, 0 }, /* R224 */ | |
576 | { 0x0000, 0x0000, 0 }, /* R225 */ | |
577 | { 0x0000, 0x0000, 0 }, /* R226 */ | |
578 | { 0x0000, 0x0000, 0 }, /* R227 */ | |
579 | { 0x0000, 0x0000, 0 }, /* R228 */ | |
580 | { 0x0000, 0x0000, 0 }, /* R229 */ | |
581 | { 0x0000, 0x0000, 0 }, /* R230 */ | |
582 | { 0x0000, 0x0000, 0 }, /* R231 */ | |
583 | { 0x0000, 0x0000, 0 }, /* R232 */ | |
584 | { 0x0000, 0x0000, 0 }, /* R233 */ | |
585 | { 0x0000, 0x0000, 0 }, /* R234 */ | |
586 | { 0x0000, 0x0000, 0 }, /* R235 */ | |
587 | { 0x0000, 0x0000, 0 }, /* R236 */ | |
588 | { 0x0000, 0x0000, 0 }, /* R237 */ | |
589 | { 0x0000, 0x0000, 0 }, /* R238 */ | |
590 | { 0x0000, 0x0000, 0 }, /* R239 */ | |
591 | { 0x0000, 0x0000, 0 }, /* R240 */ | |
592 | { 0x0000, 0x0000, 0 }, /* R241 */ | |
593 | { 0x0000, 0x0000, 0 }, /* R242 */ | |
594 | { 0x0000, 0x0000, 0 }, /* R243 */ | |
595 | { 0x0000, 0x0000, 0 }, /* R244 */ | |
596 | { 0x0000, 0x0000, 0 }, /* R245 */ | |
597 | { 0x0000, 0x0000, 0 }, /* R246 */ | |
598 | { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */ | |
599 | { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */ | |
600 | }; | |
601 | ||
602 | static int wm8904_volatile_register(unsigned int reg) | |
603 | { | |
604 | return wm8904_access[reg].vol; | |
605 | } | |
606 | ||
607 | static int wm8904_reset(struct snd_soc_codec *codec) | |
608 | { | |
609 | return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0); | |
610 | } | |
611 | ||
612 | static int wm8904_configure_clocking(struct snd_soc_codec *codec) | |
613 | { | |
b2c812e2 | 614 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
615 | unsigned int clock0, clock2, rate; |
616 | ||
617 | /* Gate the clock while we're updating to avoid misclocking */ | |
618 | clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); | |
619 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
620 | WM8904_SYSCLK_SRC, 0); | |
621 | ||
622 | /* This should be done on init() for bypass paths */ | |
623 | switch (wm8904->sysclk_src) { | |
624 | case WM8904_CLK_MCLK: | |
625 | dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); | |
626 | ||
627 | clock2 &= ~WM8904_SYSCLK_SRC; | |
628 | rate = wm8904->mclk_rate; | |
629 | ||
630 | /* Ensure the FLL is stopped */ | |
631 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
632 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
633 | break; | |
634 | ||
635 | case WM8904_CLK_FLL: | |
636 | dev_dbg(codec->dev, "Using %dHz FLL clock\n", | |
637 | wm8904->fll_fout); | |
638 | ||
639 | clock2 |= WM8904_SYSCLK_SRC; | |
640 | rate = wm8904->fll_fout; | |
641 | break; | |
642 | ||
643 | default: | |
644 | dev_err(codec->dev, "System clock not configured\n"); | |
645 | return -EINVAL; | |
646 | } | |
647 | ||
648 | /* SYSCLK shouldn't be over 13.5MHz */ | |
649 | if (rate > 13500000) { | |
650 | clock0 = WM8904_MCLK_DIV; | |
651 | wm8904->sysclk_rate = rate / 2; | |
652 | } else { | |
653 | clock0 = 0; | |
654 | wm8904->sysclk_rate = rate; | |
655 | } | |
656 | ||
657 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, | |
658 | clock0); | |
659 | ||
660 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
661 | WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); | |
662 | ||
663 | dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
668 | static void wm8904_set_drc(struct snd_soc_codec *codec) | |
669 | { | |
b2c812e2 | 670 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
671 | struct wm8904_pdata *pdata = wm8904->pdata; |
672 | int save, i; | |
673 | ||
674 | /* Save any enables; the configuration should clear them. */ | |
675 | save = snd_soc_read(codec, WM8904_DRC_0); | |
676 | ||
677 | for (i = 0; i < WM8904_DRC_REGS; i++) | |
678 | snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff, | |
679 | pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); | |
680 | ||
681 | /* Reenable the DRC */ | |
682 | snd_soc_update_bits(codec, WM8904_DRC_0, | |
683 | WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); | |
684 | } | |
685 | ||
686 | static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, | |
687 | struct snd_ctl_elem_value *ucontrol) | |
688 | { | |
689 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 690 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
691 | struct wm8904_pdata *pdata = wm8904->pdata; |
692 | int value = ucontrol->value.integer.value[0]; | |
693 | ||
694 | if (value >= pdata->num_drc_cfgs) | |
695 | return -EINVAL; | |
696 | ||
697 | wm8904->drc_cfg = value; | |
698 | ||
699 | wm8904_set_drc(codec); | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
704 | static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, | |
705 | struct snd_ctl_elem_value *ucontrol) | |
706 | { | |
707 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 708 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
709 | |
710 | ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
715 | static void wm8904_set_retune_mobile(struct snd_soc_codec *codec) | |
716 | { | |
b2c812e2 | 717 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
718 | struct wm8904_pdata *pdata = wm8904->pdata; |
719 | int best, best_val, save, i, cfg; | |
720 | ||
721 | if (!pdata || !wm8904->num_retune_mobile_texts) | |
722 | return; | |
723 | ||
724 | /* Find the version of the currently selected configuration | |
725 | * with the nearest sample rate. */ | |
726 | cfg = wm8904->retune_mobile_cfg; | |
727 | best = 0; | |
728 | best_val = INT_MAX; | |
729 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
730 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
731 | wm8904->retune_mobile_texts[cfg]) == 0 && | |
732 | abs(pdata->retune_mobile_cfgs[i].rate | |
733 | - wm8904->fs) < best_val) { | |
734 | best = i; | |
735 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
736 | - wm8904->fs); | |
737 | } | |
738 | } | |
739 | ||
740 | dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", | |
741 | pdata->retune_mobile_cfgs[best].name, | |
742 | pdata->retune_mobile_cfgs[best].rate, | |
743 | wm8904->fs); | |
744 | ||
745 | /* The EQ will be disabled while reconfiguring it, remember the | |
746 | * current configuration. | |
747 | */ | |
748 | save = snd_soc_read(codec, WM8904_EQ1); | |
749 | ||
750 | for (i = 0; i < WM8904_EQ_REGS; i++) | |
751 | snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff, | |
752 | pdata->retune_mobile_cfgs[best].regs[i]); | |
753 | ||
754 | snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save); | |
755 | } | |
756 | ||
757 | static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
758 | struct snd_ctl_elem_value *ucontrol) | |
759 | { | |
760 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 761 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
762 | struct wm8904_pdata *pdata = wm8904->pdata; |
763 | int value = ucontrol->value.integer.value[0]; | |
764 | ||
765 | if (value >= pdata->num_retune_mobile_cfgs) | |
766 | return -EINVAL; | |
767 | ||
768 | wm8904->retune_mobile_cfg = value; | |
769 | ||
770 | wm8904_set_retune_mobile(codec); | |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
775 | static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
776 | struct snd_ctl_elem_value *ucontrol) | |
777 | { | |
778 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 779 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
780 | |
781 | ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
786 | static int deemph_settings[] = { 0, 32000, 44100, 48000 }; | |
787 | ||
788 | static int wm8904_set_deemph(struct snd_soc_codec *codec) | |
789 | { | |
b2c812e2 | 790 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
791 | int val, i, best; |
792 | ||
793 | /* If we're using deemphasis select the nearest available sample | |
794 | * rate. | |
795 | */ | |
796 | if (wm8904->deemph) { | |
797 | best = 1; | |
798 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
799 | if (abs(deemph_settings[i] - wm8904->fs) < | |
800 | abs(deemph_settings[best] - wm8904->fs)) | |
801 | best = i; | |
802 | } | |
803 | ||
804 | val = best << WM8904_DEEMPH_SHIFT; | |
805 | } else { | |
806 | val = 0; | |
807 | } | |
808 | ||
809 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); | |
810 | ||
811 | return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, | |
812 | WM8904_DEEMPH_MASK, val); | |
813 | } | |
814 | ||
815 | static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, | |
816 | struct snd_ctl_elem_value *ucontrol) | |
817 | { | |
818 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 819 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
820 | |
821 | return wm8904->deemph; | |
822 | } | |
823 | ||
824 | static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, | |
825 | struct snd_ctl_elem_value *ucontrol) | |
826 | { | |
827 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 828 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
829 | int deemph = ucontrol->value.enumerated.item[0]; |
830 | ||
831 | if (deemph > 1) | |
832 | return -EINVAL; | |
833 | ||
834 | wm8904->deemph = deemph; | |
835 | ||
836 | return wm8904_set_deemph(codec); | |
837 | } | |
838 | ||
839 | static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); | |
840 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
841 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); | |
842 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); | |
843 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
844 | ||
845 | static const char *input_mode_text[] = { | |
846 | "Single-Ended", "Differential Line", "Differential Mic" | |
847 | }; | |
848 | ||
849 | static const struct soc_enum lin_mode = | |
850 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); | |
851 | ||
852 | static const struct soc_enum rin_mode = | |
853 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); | |
854 | ||
855 | static const char *hpf_mode_text[] = { | |
856 | "Hi-fi", "Voice 1", "Voice 2", "Voice 3" | |
857 | }; | |
858 | ||
859 | static const struct soc_enum hpf_mode = | |
860 | SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text); | |
861 | ||
862 | static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { | |
863 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, | |
864 | WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), | |
865 | ||
866 | SOC_ENUM("Left Caputure Mode", lin_mode), | |
867 | SOC_ENUM("Right Capture Mode", rin_mode), | |
868 | ||
869 | /* No TLV since it depends on mode */ | |
870 | SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, | |
871 | WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), | |
872 | SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, | |
873 | WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0), | |
874 | ||
875 | SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), | |
876 | SOC_ENUM("High Pass Filter Mode", hpf_mode), | |
877 | ||
878 | SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0), | |
879 | }; | |
880 | ||
881 | static const char *drc_path_text[] = { | |
882 | "ADC", "DAC" | |
883 | }; | |
884 | ||
885 | static const struct soc_enum drc_path = | |
886 | SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text); | |
887 | ||
888 | static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { | |
889 | SOC_SINGLE_TLV("Digital Playback Boost Volume", | |
890 | WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), | |
891 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, | |
892 | WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), | |
893 | ||
894 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, | |
895 | WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), | |
896 | SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
897 | WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), | |
898 | SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
899 | WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), | |
900 | ||
901 | SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, | |
902 | WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), | |
903 | SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
904 | WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), | |
905 | SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
906 | WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), | |
907 | ||
908 | SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), | |
909 | SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), | |
910 | SOC_ENUM("DRC Path", drc_path), | |
911 | SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), | |
912 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, | |
913 | wm8904_get_deemph, wm8904_put_deemph), | |
914 | }; | |
915 | ||
916 | static const struct snd_kcontrol_new wm8904_snd_controls[] = { | |
917 | SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, | |
918 | sidetone_tlv), | |
919 | }; | |
920 | ||
921 | static const struct snd_kcontrol_new wm8904_eq_controls[] = { | |
922 | SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), | |
923 | SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), | |
924 | SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), | |
925 | SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), | |
926 | SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), | |
927 | }; | |
928 | ||
929 | static int cp_event(struct snd_soc_dapm_widget *w, | |
930 | struct snd_kcontrol *kcontrol, int event) | |
931 | { | |
932 | BUG_ON(event != SND_SOC_DAPM_POST_PMU); | |
933 | ||
934 | /* Maximum startup time */ | |
935 | udelay(500); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static int sysclk_event(struct snd_soc_dapm_widget *w, | |
941 | struct snd_kcontrol *kcontrol, int event) | |
942 | { | |
943 | struct snd_soc_codec *codec = w->codec; | |
b2c812e2 | 944 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
945 | |
946 | switch (event) { | |
947 | case SND_SOC_DAPM_PRE_PMU: | |
948 | /* If we're using the FLL then we only start it when | |
949 | * required; we assume that the configuration has been | |
950 | * done previously and all we need to do is kick it | |
951 | * off. | |
952 | */ | |
953 | switch (wm8904->sysclk_src) { | |
954 | case WM8904_CLK_FLL: | |
955 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
956 | WM8904_FLL_OSC_ENA, | |
957 | WM8904_FLL_OSC_ENA); | |
958 | ||
959 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
960 | WM8904_FLL_ENA, | |
961 | WM8904_FLL_ENA); | |
962 | break; | |
963 | ||
964 | default: | |
965 | break; | |
966 | } | |
967 | break; | |
968 | ||
969 | case SND_SOC_DAPM_POST_PMD: | |
970 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
971 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
972 | break; | |
973 | } | |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
978 | static int out_pga_event(struct snd_soc_dapm_widget *w, | |
979 | struct snd_kcontrol *kcontrol, int event) | |
980 | { | |
981 | struct snd_soc_codec *codec = w->codec; | |
b2c812e2 | 982 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
983 | int reg, val; |
984 | int dcs_mask; | |
985 | int dcs_l, dcs_r; | |
986 | int dcs_l_reg, dcs_r_reg; | |
987 | int timeout; | |
e4bc6696 | 988 | int pwr_reg; |
a91eb199 MB |
989 | |
990 | /* This code is shared between HP and LINEOUT; we do all our | |
991 | * power management in stereo pairs to avoid latency issues so | |
992 | * we reuse shift to identify which rather than strcmp() the | |
993 | * name. */ | |
994 | reg = w->shift; | |
995 | ||
996 | switch (reg) { | |
997 | case WM8904_ANALOGUE_HP_0: | |
e4bc6696 | 998 | pwr_reg = WM8904_POWER_MANAGEMENT_2; |
a91eb199 MB |
999 | dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; |
1000 | dcs_r_reg = WM8904_DC_SERVO_8; | |
1001 | dcs_l_reg = WM8904_DC_SERVO_9; | |
1002 | dcs_l = 0; | |
1003 | dcs_r = 1; | |
1004 | break; | |
1005 | case WM8904_ANALOGUE_LINEOUT_0: | |
e4bc6696 | 1006 | pwr_reg = WM8904_POWER_MANAGEMENT_3; |
a91eb199 MB |
1007 | dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; |
1008 | dcs_r_reg = WM8904_DC_SERVO_6; | |
1009 | dcs_l_reg = WM8904_DC_SERVO_7; | |
1010 | dcs_l = 2; | |
1011 | dcs_r = 3; | |
1012 | break; | |
1013 | default: | |
1014 | BUG(); | |
1015 | return -EINVAL; | |
1016 | } | |
1017 | ||
1018 | switch (event) { | |
e4bc6696 MB |
1019 | case SND_SOC_DAPM_PRE_PMU: |
1020 | /* Power on the PGAs */ | |
1021 | snd_soc_update_bits(codec, pwr_reg, | |
1022 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, | |
1023 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); | |
1024 | ||
a91eb199 MB |
1025 | /* Power on the amplifier */ |
1026 | snd_soc_update_bits(codec, reg, | |
1027 | WM8904_HPL_ENA | WM8904_HPR_ENA, | |
1028 | WM8904_HPL_ENA | WM8904_HPR_ENA); | |
1029 | ||
e4bc6696 | 1030 | |
a91eb199 MB |
1031 | /* Enable the first stage */ |
1032 | snd_soc_update_bits(codec, reg, | |
1033 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, | |
1034 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); | |
1035 | ||
1036 | /* Power up the DC servo */ | |
1037 | snd_soc_update_bits(codec, WM8904_DC_SERVO_0, | |
1038 | dcs_mask, dcs_mask); | |
1039 | ||
1040 | /* Either calibrate the DC servo or restore cached state | |
1041 | * if we have that. | |
1042 | */ | |
1043 | if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { | |
1044 | dev_dbg(codec->dev, "Restoring DC servo state\n"); | |
1045 | ||
1046 | snd_soc_write(codec, dcs_l_reg, | |
1047 | wm8904->dcs_state[dcs_l]); | |
1048 | snd_soc_write(codec, dcs_r_reg, | |
1049 | wm8904->dcs_state[dcs_r]); | |
1050 | ||
1051 | snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask); | |
1052 | ||
1053 | timeout = 20; | |
1054 | } else { | |
1055 | dev_dbg(codec->dev, "Calibrating DC servo\n"); | |
1056 | ||
1057 | snd_soc_write(codec, WM8904_DC_SERVO_1, | |
1058 | dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); | |
1059 | ||
1060 | timeout = 500; | |
1061 | } | |
1062 | ||
1063 | /* Wait for DC servo to complete */ | |
1064 | dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; | |
1065 | do { | |
1066 | val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0); | |
1067 | if ((val & dcs_mask) == dcs_mask) | |
1068 | break; | |
1069 | ||
1070 | msleep(1); | |
1071 | } while (--timeout); | |
1072 | ||
1073 | if ((val & dcs_mask) != dcs_mask) | |
1074 | dev_warn(codec->dev, "DC servo timed out\n"); | |
1075 | else | |
1076 | dev_dbg(codec->dev, "DC servo ready\n"); | |
1077 | ||
1078 | /* Enable the output stage */ | |
1079 | snd_soc_update_bits(codec, reg, | |
1080 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, | |
1081 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); | |
e4bc6696 | 1082 | break; |
a91eb199 | 1083 | |
e4bc6696 | 1084 | case SND_SOC_DAPM_POST_PMU: |
a91eb199 MB |
1085 | /* Unshort the output itself */ |
1086 | snd_soc_update_bits(codec, reg, | |
1087 | WM8904_HPL_RMV_SHORT | | |
1088 | WM8904_HPR_RMV_SHORT, | |
1089 | WM8904_HPL_RMV_SHORT | | |
1090 | WM8904_HPR_RMV_SHORT); | |
1091 | ||
1092 | break; | |
1093 | ||
1094 | case SND_SOC_DAPM_PRE_PMD: | |
1095 | /* Short the output */ | |
1096 | snd_soc_update_bits(codec, reg, | |
1097 | WM8904_HPL_RMV_SHORT | | |
1098 | WM8904_HPR_RMV_SHORT, 0); | |
e4bc6696 | 1099 | break; |
a91eb199 | 1100 | |
e4bc6696 | 1101 | case SND_SOC_DAPM_POST_PMD: |
a91eb199 MB |
1102 | /* Cache the DC servo configuration; this will be |
1103 | * invalidated if we change the configuration. */ | |
1104 | wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg); | |
1105 | wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg); | |
1106 | ||
1107 | snd_soc_update_bits(codec, WM8904_DC_SERVO_0, | |
1108 | dcs_mask, 0); | |
1109 | ||
1110 | /* Disable the amplifier input and output stages */ | |
1111 | snd_soc_update_bits(codec, reg, | |
1112 | WM8904_HPL_ENA | WM8904_HPR_ENA | | |
1113 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | | |
1114 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, | |
1115 | 0); | |
e4bc6696 MB |
1116 | |
1117 | /* PGAs too */ | |
1118 | snd_soc_update_bits(codec, pwr_reg, | |
1119 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, | |
1120 | 0); | |
a91eb199 MB |
1121 | break; |
1122 | } | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | static const char *lin_text[] = { | |
1128 | "IN1L", "IN2L", "IN3L" | |
1129 | }; | |
1130 | ||
1131 | static const struct soc_enum lin_enum = | |
1132 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text); | |
1133 | ||
1134 | static const struct snd_kcontrol_new lin_mux = | |
1135 | SOC_DAPM_ENUM("Left Capture Mux", lin_enum); | |
1136 | ||
1137 | static const struct soc_enum lin_inv_enum = | |
1138 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text); | |
1139 | ||
1140 | static const struct snd_kcontrol_new lin_inv_mux = | |
1141 | SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); | |
1142 | ||
1143 | static const char *rin_text[] = { | |
1144 | "IN1R", "IN2R", "IN3R" | |
1145 | }; | |
1146 | ||
1147 | static const struct soc_enum rin_enum = | |
1148 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text); | |
1149 | ||
1150 | static const struct snd_kcontrol_new rin_mux = | |
1151 | SOC_DAPM_ENUM("Right Capture Mux", rin_enum); | |
1152 | ||
1153 | static const struct soc_enum rin_inv_enum = | |
1154 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text); | |
1155 | ||
1156 | static const struct snd_kcontrol_new rin_inv_mux = | |
1157 | SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); | |
1158 | ||
1159 | static const char *aif_text[] = { | |
1160 | "Left", "Right" | |
1161 | }; | |
1162 | ||
1163 | static const struct soc_enum aifoutl_enum = | |
1164 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text); | |
1165 | ||
1166 | static const struct snd_kcontrol_new aifoutl_mux = | |
1167 | SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); | |
1168 | ||
1169 | static const struct soc_enum aifoutr_enum = | |
1170 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text); | |
1171 | ||
1172 | static const struct snd_kcontrol_new aifoutr_mux = | |
1173 | SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); | |
1174 | ||
1175 | static const struct soc_enum aifinl_enum = | |
1176 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text); | |
1177 | ||
1178 | static const struct snd_kcontrol_new aifinl_mux = | |
1179 | SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); | |
1180 | ||
1181 | static const struct soc_enum aifinr_enum = | |
1182 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text); | |
1183 | ||
1184 | static const struct snd_kcontrol_new aifinr_mux = | |
1185 | SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); | |
1186 | ||
1187 | static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { | |
1188 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, | |
1189 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
1190 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), | |
1191 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), | |
1192 | }; | |
1193 | ||
1194 | static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { | |
1195 | SND_SOC_DAPM_INPUT("IN1L"), | |
1196 | SND_SOC_DAPM_INPUT("IN1R"), | |
1197 | SND_SOC_DAPM_INPUT("IN2L"), | |
1198 | SND_SOC_DAPM_INPUT("IN2R"), | |
1199 | SND_SOC_DAPM_INPUT("IN3L"), | |
1200 | SND_SOC_DAPM_INPUT("IN3R"), | |
1201 | ||
1202 | SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0), | |
1203 | ||
1204 | SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), | |
1205 | SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
1206 | &lin_inv_mux), | |
1207 | SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), | |
1208 | SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
1209 | &rin_inv_mux), | |
1210 | ||
1211 | SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, | |
1212 | NULL, 0), | |
1213 | SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, | |
1214 | NULL, 0), | |
1215 | ||
1216 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), | |
1217 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), | |
1218 | ||
1219 | SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), | |
1220 | SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), | |
1221 | ||
1222 | SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), | |
1223 | SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), | |
1224 | }; | |
1225 | ||
1226 | static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { | |
1227 | SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), | |
1228 | SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), | |
1229 | ||
1230 | SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), | |
1231 | SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), | |
1232 | ||
1233 | SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), | |
1234 | SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), | |
1235 | ||
1236 | SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, | |
1237 | SND_SOC_DAPM_POST_PMU), | |
1238 | ||
e4bc6696 MB |
1239 | SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
1240 | SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 | 1241 | |
e4bc6696 MB |
1242 | SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
1243 | SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 MB |
1244 | |
1245 | SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, | |
1246 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
1247 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1248 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
1249 | SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, |
1250 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
1251 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1252 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
1253 | |
1254 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
1255 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
1256 | SND_SOC_DAPM_OUTPUT("LINEOUTL"), | |
1257 | SND_SOC_DAPM_OUTPUT("LINEOUTR"), | |
1258 | }; | |
1259 | ||
1260 | static const char *out_mux_text[] = { | |
1261 | "DAC", "Bypass" | |
1262 | }; | |
1263 | ||
1264 | static const struct soc_enum hpl_enum = | |
1265 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text); | |
1266 | ||
1267 | static const struct snd_kcontrol_new hpl_mux = | |
1268 | SOC_DAPM_ENUM("HPL Mux", hpl_enum); | |
1269 | ||
1270 | static const struct soc_enum hpr_enum = | |
1271 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text); | |
1272 | ||
1273 | static const struct snd_kcontrol_new hpr_mux = | |
1274 | SOC_DAPM_ENUM("HPR Mux", hpr_enum); | |
1275 | ||
1276 | static const struct soc_enum linel_enum = | |
1277 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text); | |
1278 | ||
1279 | static const struct snd_kcontrol_new linel_mux = | |
1280 | SOC_DAPM_ENUM("LINEL Mux", linel_enum); | |
1281 | ||
1282 | static const struct soc_enum liner_enum = | |
1283 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text); | |
1284 | ||
1285 | static const struct snd_kcontrol_new liner_mux = | |
1286 | SOC_DAPM_ENUM("LINEL Mux", liner_enum); | |
1287 | ||
1288 | static const char *sidetone_text[] = { | |
1289 | "None", "Left", "Right" | |
1290 | }; | |
1291 | ||
1292 | static const struct soc_enum dacl_sidetone_enum = | |
1293 | SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text); | |
1294 | ||
1295 | static const struct snd_kcontrol_new dacl_sidetone_mux = | |
1296 | SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); | |
1297 | ||
1298 | static const struct soc_enum dacr_sidetone_enum = | |
1299 | SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text); | |
1300 | ||
1301 | static const struct snd_kcontrol_new dacr_sidetone_mux = | |
1302 | SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); | |
1303 | ||
1304 | static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { | |
1305 | SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), | |
1306 | SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1307 | SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1308 | ||
1309 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), | |
1310 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), | |
1311 | ||
1312 | SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), | |
1313 | SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), | |
1314 | SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), | |
1315 | SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), | |
1316 | }; | |
1317 | ||
1318 | static const struct snd_soc_dapm_route core_intercon[] = { | |
1319 | { "CLK_DSP", NULL, "SYSCLK" }, | |
1320 | { "TOCLK", NULL, "SYSCLK" }, | |
1321 | }; | |
1322 | ||
1323 | static const struct snd_soc_dapm_route adc_intercon[] = { | |
1324 | { "Left Capture Mux", "IN1L", "IN1L" }, | |
1325 | { "Left Capture Mux", "IN2L", "IN2L" }, | |
1326 | { "Left Capture Mux", "IN3L", "IN3L" }, | |
1327 | ||
1328 | { "Left Capture Inverting Mux", "IN1L", "IN1L" }, | |
1329 | { "Left Capture Inverting Mux", "IN2L", "IN2L" }, | |
1330 | { "Left Capture Inverting Mux", "IN3L", "IN3L" }, | |
1331 | ||
1332 | { "Right Capture Mux", "IN1R", "IN1R" }, | |
1333 | { "Right Capture Mux", "IN2R", "IN2R" }, | |
1334 | { "Right Capture Mux", "IN3R", "IN3R" }, | |
1335 | ||
1336 | { "Right Capture Inverting Mux", "IN1R", "IN1R" }, | |
1337 | { "Right Capture Inverting Mux", "IN2R", "IN2R" }, | |
1338 | { "Right Capture Inverting Mux", "IN3R", "IN3R" }, | |
1339 | ||
1340 | { "Left Capture PGA", NULL, "Left Capture Mux" }, | |
1341 | { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, | |
1342 | ||
1343 | { "Right Capture PGA", NULL, "Right Capture Mux" }, | |
1344 | { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, | |
1345 | ||
1346 | { "AIFOUTL", "Left", "ADCL" }, | |
1347 | { "AIFOUTL", "Right", "ADCR" }, | |
1348 | { "AIFOUTR", "Left", "ADCL" }, | |
1349 | { "AIFOUTR", "Right", "ADCR" }, | |
1350 | ||
1351 | { "ADCL", NULL, "CLK_DSP" }, | |
1352 | { "ADCL", NULL, "Left Capture PGA" }, | |
1353 | ||
1354 | { "ADCR", NULL, "CLK_DSP" }, | |
1355 | { "ADCR", NULL, "Right Capture PGA" }, | |
1356 | }; | |
1357 | ||
1358 | static const struct snd_soc_dapm_route dac_intercon[] = { | |
1359 | { "DACL", "Right", "AIFINR" }, | |
1360 | { "DACL", "Left", "AIFINL" }, | |
1361 | { "DACL", NULL, "CLK_DSP" }, | |
1362 | ||
1363 | { "DACR", "Right", "AIFINR" }, | |
1364 | { "DACR", "Left", "AIFINL" }, | |
1365 | { "DACR", NULL, "CLK_DSP" }, | |
1366 | ||
1367 | { "Charge pump", NULL, "SYSCLK" }, | |
1368 | ||
1369 | { "Headphone Output", NULL, "HPL PGA" }, | |
1370 | { "Headphone Output", NULL, "HPR PGA" }, | |
1371 | { "Headphone Output", NULL, "Charge pump" }, | |
1372 | { "Headphone Output", NULL, "TOCLK" }, | |
1373 | ||
1374 | { "Line Output", NULL, "LINEL PGA" }, | |
1375 | { "Line Output", NULL, "LINER PGA" }, | |
1376 | { "Line Output", NULL, "Charge pump" }, | |
1377 | { "Line Output", NULL, "TOCLK" }, | |
1378 | ||
1379 | { "HPOUTL", NULL, "Headphone Output" }, | |
1380 | { "HPOUTR", NULL, "Headphone Output" }, | |
1381 | ||
1382 | { "LINEOUTL", NULL, "Line Output" }, | |
1383 | { "LINEOUTR", NULL, "Line Output" }, | |
1384 | }; | |
1385 | ||
1386 | static const struct snd_soc_dapm_route wm8904_intercon[] = { | |
1387 | { "Left Sidetone", "Left", "ADCL" }, | |
1388 | { "Left Sidetone", "Right", "ADCR" }, | |
1389 | { "DACL", NULL, "Left Sidetone" }, | |
1390 | ||
1391 | { "Right Sidetone", "Left", "ADCL" }, | |
1392 | { "Right Sidetone", "Right", "ADCR" }, | |
1393 | { "DACR", NULL, "Right Sidetone" }, | |
1394 | ||
1395 | { "Left Bypass", NULL, "Class G" }, | |
1396 | { "Left Bypass", NULL, "Left Capture PGA" }, | |
1397 | ||
1398 | { "Right Bypass", NULL, "Class G" }, | |
1399 | { "Right Bypass", NULL, "Right Capture PGA" }, | |
1400 | ||
1401 | { "HPL Mux", "DAC", "DACL" }, | |
1402 | { "HPL Mux", "Bypass", "Left Bypass" }, | |
1403 | ||
1404 | { "HPR Mux", "DAC", "DACR" }, | |
1405 | { "HPR Mux", "Bypass", "Right Bypass" }, | |
1406 | ||
1407 | { "LINEL Mux", "DAC", "DACL" }, | |
1408 | { "LINEL Mux", "Bypass", "Left Bypass" }, | |
1409 | ||
1410 | { "LINER Mux", "DAC", "DACR" }, | |
1411 | { "LINER Mux", "Bypass", "Right Bypass" }, | |
1412 | ||
1413 | { "HPL PGA", NULL, "HPL Mux" }, | |
1414 | { "HPR PGA", NULL, "HPR Mux" }, | |
1415 | ||
1416 | { "LINEL PGA", NULL, "LINEL Mux" }, | |
1417 | { "LINER PGA", NULL, "LINER Mux" }, | |
1418 | }; | |
1419 | ||
8c126474 MB |
1420 | static const struct snd_soc_dapm_route wm8912_intercon[] = { |
1421 | { "HPL PGA", NULL, "DACL" }, | |
1422 | { "HPR PGA", NULL, "DACR" }, | |
1423 | ||
1424 | { "LINEL PGA", NULL, "DACL" }, | |
1425 | { "LINER PGA", NULL, "DACR" }, | |
1426 | }; | |
1427 | ||
a91eb199 MB |
1428 | static int wm8904_add_widgets(struct snd_soc_codec *codec) |
1429 | { | |
b2c812e2 | 1430 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1431 | |
1432 | snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets, | |
1433 | ARRAY_SIZE(wm8904_core_dapm_widgets)); | |
a91eb199 MB |
1434 | snd_soc_dapm_add_routes(codec, core_intercon, |
1435 | ARRAY_SIZE(core_intercon)); | |
8c126474 MB |
1436 | |
1437 | switch (wm8904->devtype) { | |
1438 | case WM8904: | |
1439 | snd_soc_add_controls(codec, wm8904_adc_snd_controls, | |
1440 | ARRAY_SIZE(wm8904_adc_snd_controls)); | |
1441 | snd_soc_add_controls(codec, wm8904_dac_snd_controls, | |
1442 | ARRAY_SIZE(wm8904_dac_snd_controls)); | |
1443 | snd_soc_add_controls(codec, wm8904_snd_controls, | |
1444 | ARRAY_SIZE(wm8904_snd_controls)); | |
1445 | ||
1446 | snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets, | |
1447 | ARRAY_SIZE(wm8904_adc_dapm_widgets)); | |
1448 | snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, | |
1449 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); | |
1450 | snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets, | |
1451 | ARRAY_SIZE(wm8904_dapm_widgets)); | |
1452 | ||
1453 | snd_soc_dapm_add_routes(codec, core_intercon, | |
1454 | ARRAY_SIZE(core_intercon)); | |
1455 | snd_soc_dapm_add_routes(codec, adc_intercon, | |
1456 | ARRAY_SIZE(adc_intercon)); | |
1457 | snd_soc_dapm_add_routes(codec, dac_intercon, | |
1458 | ARRAY_SIZE(dac_intercon)); | |
1459 | snd_soc_dapm_add_routes(codec, wm8904_intercon, | |
1460 | ARRAY_SIZE(wm8904_intercon)); | |
1461 | break; | |
1462 | ||
1463 | case WM8912: | |
1464 | snd_soc_add_controls(codec, wm8904_dac_snd_controls, | |
1465 | ARRAY_SIZE(wm8904_dac_snd_controls)); | |
1466 | ||
1467 | snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, | |
1468 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); | |
1469 | ||
1470 | snd_soc_dapm_add_routes(codec, dac_intercon, | |
1471 | ARRAY_SIZE(dac_intercon)); | |
1472 | snd_soc_dapm_add_routes(codec, wm8912_intercon, | |
1473 | ARRAY_SIZE(wm8912_intercon)); | |
1474 | break; | |
1475 | } | |
a91eb199 MB |
1476 | |
1477 | snd_soc_dapm_new_widgets(codec); | |
1478 | return 0; | |
1479 | } | |
1480 | ||
1481 | static struct { | |
1482 | int ratio; | |
1483 | unsigned int clk_sys_rate; | |
1484 | } clk_sys_rates[] = { | |
1485 | { 64, 0 }, | |
1486 | { 128, 1 }, | |
1487 | { 192, 2 }, | |
1488 | { 256, 3 }, | |
1489 | { 384, 4 }, | |
1490 | { 512, 5 }, | |
1491 | { 786, 6 }, | |
1492 | { 1024, 7 }, | |
1493 | { 1408, 8 }, | |
1494 | { 1536, 9 }, | |
1495 | }; | |
1496 | ||
1497 | static struct { | |
1498 | int rate; | |
1499 | int sample_rate; | |
1500 | } sample_rates[] = { | |
1501 | { 8000, 0 }, | |
1502 | { 11025, 1 }, | |
1503 | { 12000, 1 }, | |
1504 | { 16000, 2 }, | |
1505 | { 22050, 3 }, | |
1506 | { 24000, 3 }, | |
1507 | { 32000, 4 }, | |
1508 | { 44100, 5 }, | |
1509 | { 48000, 5 }, | |
1510 | }; | |
1511 | ||
1512 | static struct { | |
1513 | int div; /* *10 due to .5s */ | |
1514 | int bclk_div; | |
1515 | } bclk_divs[] = { | |
1516 | { 10, 0 }, | |
1517 | { 15, 1 }, | |
1518 | { 20, 2 }, | |
1519 | { 30, 3 }, | |
1520 | { 40, 4 }, | |
1521 | { 50, 5 }, | |
1522 | { 55, 6 }, | |
1523 | { 60, 7 }, | |
1524 | { 80, 8 }, | |
1525 | { 100, 9 }, | |
1526 | { 110, 10 }, | |
1527 | { 120, 11 }, | |
1528 | { 160, 12 }, | |
1529 | { 200, 13 }, | |
1530 | { 220, 14 }, | |
1531 | { 240, 16 }, | |
1532 | { 200, 17 }, | |
1533 | { 320, 18 }, | |
1534 | { 440, 19 }, | |
1535 | { 480, 20 }, | |
1536 | }; | |
1537 | ||
1538 | ||
1539 | static int wm8904_hw_params(struct snd_pcm_substream *substream, | |
1540 | struct snd_pcm_hw_params *params, | |
1541 | struct snd_soc_dai *dai) | |
1542 | { | |
1543 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1544 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1545 | int ret, i, best, best_val, cur_val; |
1546 | unsigned int aif1 = 0; | |
1547 | unsigned int aif2 = 0; | |
1548 | unsigned int aif3 = 0; | |
1549 | unsigned int clock1 = 0; | |
1550 | unsigned int dac_digital1 = 0; | |
1551 | ||
1552 | /* What BCLK do we need? */ | |
1553 | wm8904->fs = params_rate(params); | |
1554 | if (wm8904->tdm_slots) { | |
1555 | dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", | |
1556 | wm8904->tdm_slots, wm8904->tdm_width); | |
1557 | wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, | |
1558 | wm8904->tdm_width, 2, | |
1559 | wm8904->tdm_slots); | |
1560 | } else { | |
1561 | wm8904->bclk = snd_soc_params_to_bclk(params); | |
1562 | } | |
1563 | ||
56927eb0 MB |
1564 | switch (params_format(params)) { |
1565 | case SNDRV_PCM_FORMAT_S16_LE: | |
1566 | break; | |
1567 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1568 | aif1 |= 0x40; | |
1569 | break; | |
1570 | case SNDRV_PCM_FORMAT_S24_LE: | |
1571 | aif1 |= 0x80; | |
1572 | break; | |
1573 | case SNDRV_PCM_FORMAT_S32_LE: | |
1574 | aif1 |= 0xc0; | |
1575 | break; | |
1576 | default: | |
1577 | return -EINVAL; | |
1578 | } | |
1579 | ||
1580 | ||
a91eb199 MB |
1581 | dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); |
1582 | ||
1583 | ret = wm8904_configure_clocking(codec); | |
1584 | if (ret != 0) | |
1585 | return ret; | |
1586 | ||
1587 | /* Select nearest CLK_SYS_RATE */ | |
1588 | best = 0; | |
1589 | best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) | |
1590 | - wm8904->fs); | |
1591 | for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { | |
1592 | cur_val = abs((wm8904->sysclk_rate / | |
1593 | clk_sys_rates[i].ratio) - wm8904->fs);; | |
1594 | if (cur_val < best_val) { | |
1595 | best = i; | |
1596 | best_val = cur_val; | |
1597 | } | |
1598 | } | |
1599 | dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", | |
1600 | clk_sys_rates[best].ratio); | |
1601 | clock1 |= (clk_sys_rates[best].clk_sys_rate | |
1602 | << WM8904_CLK_SYS_RATE_SHIFT); | |
1603 | ||
1604 | /* SAMPLE_RATE */ | |
1605 | best = 0; | |
1606 | best_val = abs(wm8904->fs - sample_rates[0].rate); | |
1607 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1608 | /* Closest match */ | |
1609 | cur_val = abs(wm8904->fs - sample_rates[i].rate); | |
1610 | if (cur_val < best_val) { | |
1611 | best = i; | |
1612 | best_val = cur_val; | |
1613 | } | |
1614 | } | |
1615 | dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", | |
1616 | sample_rates[best].rate); | |
1617 | clock1 |= (sample_rates[best].sample_rate | |
1618 | << WM8904_SAMPLE_RATE_SHIFT); | |
1619 | ||
1620 | /* Enable sloping stopband filter for low sample rates */ | |
1621 | if (wm8904->fs <= 24000) | |
1622 | dac_digital1 |= WM8904_DAC_SB_FILT; | |
1623 | ||
1624 | /* BCLK_DIV */ | |
1625 | best = 0; | |
1626 | best_val = INT_MAX; | |
1627 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1628 | cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) | |
1629 | - wm8904->bclk; | |
1630 | if (cur_val < 0) /* Table is sorted */ | |
1631 | break; | |
1632 | if (cur_val < best_val) { | |
1633 | best = i; | |
1634 | best_val = cur_val; | |
1635 | } | |
1636 | } | |
1637 | wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; | |
1638 | dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", | |
1639 | bclk_divs[best].div, wm8904->bclk); | |
1640 | aif2 |= bclk_divs[best].bclk_div; | |
1641 | ||
1642 | /* LRCLK is a simple fraction of BCLK */ | |
1643 | dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); | |
1644 | aif3 |= wm8904->bclk / wm8904->fs; | |
1645 | ||
1646 | /* Apply the settings */ | |
1647 | snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, | |
1648 | WM8904_DAC_SB_FILT, dac_digital1); | |
1649 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1650 | WM8904_AIF_WL_MASK, aif1); | |
1651 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2, | |
1652 | WM8904_BCLK_DIV_MASK, aif2); | |
1653 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, | |
1654 | WM8904_LRCLK_RATE_MASK, aif3); | |
1655 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1, | |
1656 | WM8904_SAMPLE_RATE_MASK | | |
1657 | WM8904_CLK_SYS_RATE_MASK, clock1); | |
1658 | ||
1659 | /* Update filters for the new settings */ | |
1660 | wm8904_set_retune_mobile(codec); | |
1661 | wm8904_set_deemph(codec); | |
1662 | ||
1663 | return 0; | |
1664 | } | |
1665 | ||
1666 | ||
1667 | static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, | |
1668 | unsigned int freq, int dir) | |
1669 | { | |
1670 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1671 | struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1672 | |
1673 | switch (clk_id) { | |
1674 | case WM8904_CLK_MCLK: | |
1675 | priv->sysclk_src = clk_id; | |
1676 | priv->mclk_rate = freq; | |
1677 | break; | |
1678 | ||
1679 | case WM8904_CLK_FLL: | |
1680 | priv->sysclk_src = clk_id; | |
1681 | break; | |
1682 | ||
1683 | default: | |
1684 | return -EINVAL; | |
1685 | } | |
1686 | ||
1687 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
1688 | ||
1689 | wm8904_configure_clocking(codec); | |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
1694 | static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1695 | { | |
1696 | struct snd_soc_codec *codec = dai->codec; | |
1697 | unsigned int aif1 = 0; | |
1698 | unsigned int aif3 = 0; | |
1699 | ||
1700 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1701 | case SND_SOC_DAIFMT_CBS_CFS: | |
1702 | break; | |
1703 | case SND_SOC_DAIFMT_CBS_CFM: | |
1704 | aif3 |= WM8904_LRCLK_DIR; | |
1705 | break; | |
1706 | case SND_SOC_DAIFMT_CBM_CFS: | |
1707 | aif1 |= WM8904_BCLK_DIR; | |
1708 | break; | |
1709 | case SND_SOC_DAIFMT_CBM_CFM: | |
1710 | aif1 |= WM8904_BCLK_DIR; | |
1711 | aif3 |= WM8904_LRCLK_DIR; | |
1712 | break; | |
1713 | default: | |
1714 | return -EINVAL; | |
1715 | } | |
1716 | ||
1717 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1718 | case SND_SOC_DAIFMT_DSP_B: | |
1719 | aif1 |= WM8904_AIF_LRCLK_INV; | |
1720 | case SND_SOC_DAIFMT_DSP_A: | |
1721 | aif1 |= 0x3; | |
1722 | break; | |
1723 | case SND_SOC_DAIFMT_I2S: | |
1724 | aif1 |= 0x2; | |
1725 | break; | |
1726 | case SND_SOC_DAIFMT_RIGHT_J: | |
1727 | break; | |
1728 | case SND_SOC_DAIFMT_LEFT_J: | |
1729 | aif1 |= 0x1; | |
1730 | break; | |
1731 | default: | |
1732 | return -EINVAL; | |
1733 | } | |
1734 | ||
1735 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1736 | case SND_SOC_DAIFMT_DSP_A: | |
1737 | case SND_SOC_DAIFMT_DSP_B: | |
1738 | /* frame inversion not valid for DSP modes */ | |
1739 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1740 | case SND_SOC_DAIFMT_NB_NF: | |
1741 | break; | |
1742 | case SND_SOC_DAIFMT_IB_NF: | |
1743 | aif1 |= WM8904_AIF_BCLK_INV; | |
1744 | break; | |
1745 | default: | |
1746 | return -EINVAL; | |
1747 | } | |
1748 | break; | |
1749 | ||
1750 | case SND_SOC_DAIFMT_I2S: | |
1751 | case SND_SOC_DAIFMT_RIGHT_J: | |
1752 | case SND_SOC_DAIFMT_LEFT_J: | |
1753 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1754 | case SND_SOC_DAIFMT_NB_NF: | |
1755 | break; | |
1756 | case SND_SOC_DAIFMT_IB_IF: | |
1757 | aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; | |
1758 | break; | |
1759 | case SND_SOC_DAIFMT_IB_NF: | |
1760 | aif1 |= WM8904_AIF_BCLK_INV; | |
1761 | break; | |
1762 | case SND_SOC_DAIFMT_NB_IF: | |
1763 | aif1 |= WM8904_AIF_LRCLK_INV; | |
1764 | break; | |
1765 | default: | |
1766 | return -EINVAL; | |
1767 | } | |
1768 | break; | |
1769 | default: | |
1770 | return -EINVAL; | |
1771 | } | |
1772 | ||
1773 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1774 | WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | | |
1775 | WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); | |
1776 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, | |
1777 | WM8904_LRCLK_DIR, aif3); | |
1778 | ||
1779 | return 0; | |
1780 | } | |
1781 | ||
1782 | ||
1783 | static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, | |
1784 | unsigned int rx_mask, int slots, int slot_width) | |
1785 | { | |
1786 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1787 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1788 | int aif1 = 0; |
1789 | ||
1790 | /* Don't need to validate anything if we're turning off TDM */ | |
1791 | if (slots == 0) | |
1792 | goto out; | |
1793 | ||
1794 | /* Note that we allow configurations we can't handle ourselves - | |
1795 | * for example, we can generate clocks for slots 2 and up even if | |
1796 | * we can't use those slots ourselves. | |
1797 | */ | |
1798 | aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; | |
1799 | ||
1800 | switch (rx_mask) { | |
1801 | case 3: | |
1802 | break; | |
1803 | case 0xc: | |
1804 | aif1 |= WM8904_AIFADC_TDM_CHAN; | |
1805 | break; | |
1806 | default: | |
1807 | return -EINVAL; | |
1808 | } | |
1809 | ||
1810 | ||
1811 | switch (tx_mask) { | |
1812 | case 3: | |
1813 | break; | |
1814 | case 0xc: | |
1815 | aif1 |= WM8904_AIFDAC_TDM_CHAN; | |
1816 | break; | |
1817 | default: | |
1818 | return -EINVAL; | |
1819 | } | |
1820 | ||
1821 | out: | |
1822 | wm8904->tdm_width = slot_width; | |
1823 | wm8904->tdm_slots = slots / 2; | |
1824 | ||
1825 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1826 | WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | | |
1827 | WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); | |
1828 | ||
1829 | return 0; | |
1830 | } | |
1831 | ||
1832 | struct _fll_div { | |
1833 | u16 fll_fratio; | |
1834 | u16 fll_outdiv; | |
1835 | u16 fll_clk_ref_div; | |
1836 | u16 n; | |
1837 | u16 k; | |
1838 | }; | |
1839 | ||
1840 | /* The size in bits of the FLL divide multiplied by 10 | |
1841 | * to allow rounding later */ | |
1842 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1843 | ||
1844 | static struct { | |
1845 | unsigned int min; | |
1846 | unsigned int max; | |
1847 | u16 fll_fratio; | |
1848 | int ratio; | |
1849 | } fll_fratios[] = { | |
1850 | { 0, 64000, 4, 16 }, | |
1851 | { 64000, 128000, 3, 8 }, | |
1852 | { 128000, 256000, 2, 4 }, | |
1853 | { 256000, 1000000, 1, 2 }, | |
1854 | { 1000000, 13500000, 0, 1 }, | |
1855 | }; | |
1856 | ||
1857 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
1858 | unsigned int Fout) | |
1859 | { | |
1860 | u64 Kpart; | |
1861 | unsigned int K, Ndiv, Nmod, target; | |
1862 | unsigned int div; | |
1863 | int i; | |
1864 | ||
1865 | /* Fref must be <=13.5MHz */ | |
1866 | div = 1; | |
1867 | fll_div->fll_clk_ref_div = 0; | |
1868 | while ((Fref / div) > 13500000) { | |
1869 | div *= 2; | |
1870 | fll_div->fll_clk_ref_div++; | |
1871 | ||
1872 | if (div > 8) { | |
1873 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
1874 | Fref); | |
1875 | return -EINVAL; | |
1876 | } | |
1877 | } | |
1878 | ||
1879 | pr_debug("Fref=%u Fout=%u\n", Fref, Fout); | |
1880 | ||
1881 | /* Apply the division for our remaining calculations */ | |
1882 | Fref /= div; | |
1883 | ||
1884 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
1885 | div = 4; | |
1886 | while (Fout * div < 90000000) { | |
1887 | div++; | |
1888 | if (div > 64) { | |
1889 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
1890 | Fout); | |
1891 | return -EINVAL; | |
1892 | } | |
1893 | } | |
1894 | target = Fout * div; | |
1895 | fll_div->fll_outdiv = div - 1; | |
1896 | ||
1897 | pr_debug("Fvco=%dHz\n", target); | |
1898 | ||
1899 | /* Find an appropraite FLL_FRATIO and factor it out of the target */ | |
1900 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { | |
1901 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
1902 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
1903 | target /= fll_fratios[i].ratio; | |
1904 | break; | |
1905 | } | |
1906 | } | |
1907 | if (i == ARRAY_SIZE(fll_fratios)) { | |
1908 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
1909 | return -EINVAL; | |
1910 | } | |
1911 | ||
1912 | /* Now, calculate N.K */ | |
1913 | Ndiv = target / Fref; | |
1914 | ||
1915 | fll_div->n = Ndiv; | |
1916 | Nmod = target % Fref; | |
1917 | pr_debug("Nmod=%d\n", Nmod); | |
1918 | ||
1919 | /* Calculate fractional part - scale up so we can round. */ | |
1920 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1921 | ||
1922 | do_div(Kpart, Fref); | |
1923 | ||
1924 | K = Kpart & 0xFFFFFFFF; | |
1925 | ||
1926 | if ((K % 10) >= 5) | |
1927 | K += 5; | |
1928 | ||
1929 | /* Move down to proper range now rounding is done */ | |
1930 | fll_div->k = K / 10; | |
1931 | ||
1932 | pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", | |
1933 | fll_div->n, fll_div->k, | |
1934 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
1935 | fll_div->fll_clk_ref_div); | |
1936 | ||
1937 | return 0; | |
1938 | } | |
1939 | ||
1940 | static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, | |
1941 | unsigned int Fref, unsigned int Fout) | |
1942 | { | |
1943 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1944 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1945 | struct _fll_div fll_div; |
1946 | int ret, val; | |
1947 | int clock2, fll1; | |
1948 | ||
1949 | /* Any change? */ | |
1950 | if (source == wm8904->fll_src && Fref == wm8904->fll_fref && | |
1951 | Fout == wm8904->fll_fout) | |
1952 | return 0; | |
1953 | ||
18240b67 MB |
1954 | clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); |
1955 | ||
a91eb199 MB |
1956 | if (Fout == 0) { |
1957 | dev_dbg(codec->dev, "FLL disabled\n"); | |
1958 | ||
1959 | wm8904->fll_fref = 0; | |
1960 | wm8904->fll_fout = 0; | |
1961 | ||
1962 | /* Gate SYSCLK to avoid glitches */ | |
1963 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
1964 | WM8904_CLK_SYS_ENA, 0); | |
1965 | ||
1966 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
1967 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
1968 | ||
1969 | goto out; | |
1970 | } | |
1971 | ||
1972 | /* Validate the FLL ID */ | |
1973 | switch (source) { | |
1974 | case WM8904_FLL_MCLK: | |
1975 | case WM8904_FLL_LRCLK: | |
1976 | case WM8904_FLL_BCLK: | |
1977 | ret = fll_factors(&fll_div, Fref, Fout); | |
1978 | if (ret != 0) | |
1979 | return ret; | |
1980 | break; | |
1981 | ||
1982 | case WM8904_FLL_FREE_RUNNING: | |
1983 | dev_dbg(codec->dev, "Using free running FLL\n"); | |
1984 | /* Force 12MHz and output/4 for now */ | |
1985 | Fout = 12000000; | |
1986 | Fref = 12000000; | |
1987 | ||
1988 | memset(&fll_div, 0, sizeof(fll_div)); | |
1989 | fll_div.fll_outdiv = 3; | |
1990 | break; | |
1991 | ||
1992 | default: | |
1993 | dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); | |
1994 | return -EINVAL; | |
1995 | } | |
1996 | ||
1997 | /* Save current state then disable the FLL and SYSCLK to avoid | |
1998 | * misclocking */ | |
a91eb199 MB |
1999 | fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1); |
2000 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
2001 | WM8904_CLK_SYS_ENA, 0); | |
2002 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2003 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
2004 | ||
2005 | /* Unlock forced oscilator control to switch it on/off */ | |
2006 | snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, | |
2007 | WM8904_USER_KEY, WM8904_USER_KEY); | |
2008 | ||
2009 | if (fll_id == WM8904_FLL_FREE_RUNNING) { | |
2010 | val = WM8904_FLL_FRC_NCO; | |
2011 | } else { | |
2012 | val = 0; | |
2013 | } | |
2014 | ||
2015 | snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, | |
2016 | val); | |
2017 | snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, | |
2018 | WM8904_USER_KEY, 0); | |
2019 | ||
2020 | switch (fll_id) { | |
2021 | case WM8904_FLL_MCLK: | |
2022 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2023 | WM8904_FLL_CLK_REF_SRC_MASK, 0); | |
2024 | break; | |
2025 | ||
2026 | case WM8904_FLL_LRCLK: | |
2027 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2028 | WM8904_FLL_CLK_REF_SRC_MASK, 1); | |
2029 | break; | |
2030 | ||
2031 | case WM8904_FLL_BCLK: | |
2032 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2033 | WM8904_FLL_CLK_REF_SRC_MASK, 2); | |
2034 | break; | |
2035 | } | |
2036 | ||
2037 | if (fll_div.k) | |
2038 | val = WM8904_FLL_FRACN_ENA; | |
2039 | else | |
2040 | val = 0; | |
2041 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2042 | WM8904_FLL_FRACN_ENA, val); | |
2043 | ||
2044 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2, | |
2045 | WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, | |
2046 | (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | | |
2047 | (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); | |
2048 | ||
2049 | snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k); | |
2050 | ||
2051 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, | |
2052 | fll_div.n << WM8904_FLL_N_SHIFT); | |
2053 | ||
2054 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2055 | WM8904_FLL_CLK_REF_DIV_MASK, | |
2056 | fll_div.fll_clk_ref_div | |
2057 | << WM8904_FLL_CLK_REF_DIV_SHIFT); | |
2058 | ||
2059 | dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); | |
2060 | ||
2061 | wm8904->fll_fref = Fref; | |
2062 | wm8904->fll_fout = Fout; | |
2063 | wm8904->fll_src = source; | |
2064 | ||
2065 | /* Enable the FLL if it was previously active */ | |
2066 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2067 | WM8904_FLL_OSC_ENA, fll1); | |
2068 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2069 | WM8904_FLL_ENA, fll1); | |
2070 | ||
2071 | out: | |
2072 | /* Reenable SYSCLK if it was previously active */ | |
2073 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
2074 | WM8904_CLK_SYS_ENA, clock2); | |
2075 | ||
2076 | return 0; | |
2077 | } | |
2078 | ||
2079 | static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
2080 | { | |
2081 | struct snd_soc_codec *codec = codec_dai->codec; | |
2082 | int val; | |
2083 | ||
2084 | if (mute) | |
2085 | val = WM8904_DAC_MUTE; | |
2086 | else | |
2087 | val = 0; | |
2088 | ||
2089 | snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); | |
2090 | ||
2091 | return 0; | |
2092 | } | |
2093 | ||
c1334218 MB |
2094 | static void wm8904_sync_cache(struct snd_soc_codec *codec) |
2095 | { | |
b2c812e2 | 2096 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
c1334218 MB |
2097 | int i; |
2098 | ||
2099 | if (!codec->cache_sync) | |
2100 | return; | |
2101 | ||
2102 | codec->cache_only = 0; | |
2103 | ||
2104 | /* Sync back cached values if they're different from the | |
2105 | * hardware default. | |
2106 | */ | |
2107 | for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) { | |
2108 | if (!wm8904_access[i].writable) | |
2109 | continue; | |
2110 | ||
2111 | if (wm8904->reg_cache[i] == wm8904_reg[i]) | |
2112 | continue; | |
2113 | ||
2114 | snd_soc_write(codec, i, wm8904->reg_cache[i]); | |
2115 | } | |
2116 | ||
2117 | codec->cache_sync = 0; | |
2118 | } | |
2119 | ||
a91eb199 MB |
2120 | static int wm8904_set_bias_level(struct snd_soc_codec *codec, |
2121 | enum snd_soc_bias_level level) | |
2122 | { | |
b2c812e2 | 2123 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
c1334218 | 2124 | int ret; |
a91eb199 MB |
2125 | |
2126 | switch (level) { | |
2127 | case SND_SOC_BIAS_ON: | |
2128 | break; | |
2129 | ||
2130 | case SND_SOC_BIAS_PREPARE: | |
2131 | /* VMID resistance 2*50k */ | |
2132 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2133 | WM8904_VMID_RES_MASK, | |
2134 | 0x1 << WM8904_VMID_RES_SHIFT); | |
2135 | ||
2136 | /* Normal bias current */ | |
2137 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2138 | WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); | |
2139 | break; | |
2140 | ||
2141 | case SND_SOC_BIAS_STANDBY: | |
2142 | if (codec->bias_level == SND_SOC_BIAS_OFF) { | |
2143 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), | |
2144 | wm8904->supplies); | |
2145 | if (ret != 0) { | |
2146 | dev_err(codec->dev, | |
2147 | "Failed to enable supplies: %d\n", | |
2148 | ret); | |
2149 | return ret; | |
2150 | } | |
2151 | ||
c1334218 | 2152 | wm8904_sync_cache(codec); |
a91eb199 MB |
2153 | |
2154 | /* Enable bias */ | |
2155 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2156 | WM8904_BIAS_ENA, WM8904_BIAS_ENA); | |
2157 | ||
2158 | /* Enable VMID, VMID buffering, 2*5k resistance */ | |
2159 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2160 | WM8904_VMID_ENA | | |
2161 | WM8904_VMID_RES_MASK, | |
2162 | WM8904_VMID_ENA | | |
2163 | 0x3 << WM8904_VMID_RES_SHIFT); | |
2164 | ||
2165 | /* Let VMID ramp */ | |
2166 | msleep(1); | |
2167 | } | |
2168 | ||
2169 | /* Maintain VMID with 2*250k */ | |
2170 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2171 | WM8904_VMID_RES_MASK, | |
2172 | 0x2 << WM8904_VMID_RES_SHIFT); | |
2173 | ||
2174 | /* Bias current *0.5 */ | |
2175 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2176 | WM8904_ISEL_MASK, 0); | |
2177 | break; | |
2178 | ||
2179 | case SND_SOC_BIAS_OFF: | |
2180 | /* Turn off VMID */ | |
2181 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2182 | WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); | |
2183 | ||
2184 | /* Stop bias generation */ | |
2185 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2186 | WM8904_BIAS_ENA, 0); | |
2187 | ||
c1334218 MB |
2188 | #ifdef CONFIG_REGULATOR |
2189 | /* Post 2.6.34 we will be able to get a callback when | |
2190 | * the regulators are disabled which we can use but | |
2191 | * for now just assume that the power will be cut if | |
2192 | * the regulator API is in use. | |
2193 | */ | |
2194 | codec->cache_sync = 1; | |
2195 | #endif | |
2196 | ||
a91eb199 MB |
2197 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), |
2198 | wm8904->supplies); | |
2199 | break; | |
2200 | } | |
2201 | codec->bias_level = level; | |
2202 | return 0; | |
2203 | } | |
2204 | ||
2205 | #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 | |
2206 | ||
2207 | #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
2208 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
2209 | ||
2210 | static struct snd_soc_dai_ops wm8904_dai_ops = { | |
2211 | .set_sysclk = wm8904_set_sysclk, | |
2212 | .set_fmt = wm8904_set_fmt, | |
2213 | .set_tdm_slot = wm8904_set_tdm_slot, | |
2214 | .set_pll = wm8904_set_fll, | |
2215 | .hw_params = wm8904_hw_params, | |
2216 | .digital_mute = wm8904_digital_mute, | |
2217 | }; | |
2218 | ||
f0fba2ad LG |
2219 | static struct snd_soc_dai_driver wm8904_dai = { |
2220 | .name = "wm8904-hifi", | |
a91eb199 MB |
2221 | .playback = { |
2222 | .stream_name = "Playback", | |
2223 | .channels_min = 2, | |
2224 | .channels_max = 2, | |
2225 | .rates = WM8904_RATES, | |
2226 | .formats = WM8904_FORMATS, | |
2227 | }, | |
2228 | .capture = { | |
2229 | .stream_name = "Capture", | |
2230 | .channels_min = 2, | |
2231 | .channels_max = 2, | |
2232 | .rates = WM8904_RATES, | |
2233 | .formats = WM8904_FORMATS, | |
2234 | }, | |
2235 | .ops = &wm8904_dai_ops, | |
2236 | .symmetric_rates = 1, | |
2237 | }; | |
a91eb199 MB |
2238 | |
2239 | #ifdef CONFIG_PM | |
f0fba2ad | 2240 | static int wm8904_suspend(struct snd_soc_codec *codec, pm_message_t state) |
a91eb199 | 2241 | { |
a91eb199 MB |
2242 | wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); |
2243 | ||
2244 | return 0; | |
2245 | } | |
2246 | ||
f0fba2ad | 2247 | static int wm8904_resume(struct snd_soc_codec *codec) |
a91eb199 | 2248 | { |
a91eb199 MB |
2249 | wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
2250 | ||
2251 | return 0; | |
2252 | } | |
2253 | #else | |
2254 | #define wm8904_suspend NULL | |
2255 | #define wm8904_resume NULL | |
2256 | #endif | |
2257 | ||
f0fba2ad | 2258 | static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec) |
a91eb199 | 2259 | { |
f0fba2ad | 2260 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
2261 | struct wm8904_pdata *pdata = wm8904->pdata; |
2262 | struct snd_kcontrol_new control = | |
2263 | SOC_ENUM_EXT("EQ Mode", | |
2264 | wm8904->retune_mobile_enum, | |
2265 | wm8904_get_retune_mobile_enum, | |
2266 | wm8904_put_retune_mobile_enum); | |
2267 | int ret, i, j; | |
2268 | const char **t; | |
2269 | ||
2270 | /* We need an array of texts for the enum API but the number | |
2271 | * of texts is likely to be less than the number of | |
2272 | * configurations due to the sample rate dependency of the | |
2273 | * configurations. */ | |
2274 | wm8904->num_retune_mobile_texts = 0; | |
2275 | wm8904->retune_mobile_texts = NULL; | |
2276 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
2277 | for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { | |
2278 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
2279 | wm8904->retune_mobile_texts[j]) == 0) | |
2280 | break; | |
2281 | } | |
2282 | ||
2283 | if (j != wm8904->num_retune_mobile_texts) | |
2284 | continue; | |
2285 | ||
2286 | /* Expand the array... */ | |
2287 | t = krealloc(wm8904->retune_mobile_texts, | |
2288 | sizeof(char *) * | |
2289 | (wm8904->num_retune_mobile_texts + 1), | |
2290 | GFP_KERNEL); | |
2291 | if (t == NULL) | |
2292 | continue; | |
2293 | ||
2294 | /* ...store the new entry... */ | |
2295 | t[wm8904->num_retune_mobile_texts] = | |
2296 | pdata->retune_mobile_cfgs[i].name; | |
2297 | ||
2298 | /* ...and remember the new version. */ | |
2299 | wm8904->num_retune_mobile_texts++; | |
2300 | wm8904->retune_mobile_texts = t; | |
2301 | } | |
2302 | ||
2303 | dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", | |
2304 | wm8904->num_retune_mobile_texts); | |
2305 | ||
2306 | wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts; | |
2307 | wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; | |
2308 | ||
f0fba2ad | 2309 | ret = snd_soc_add_controls(codec, &control, 1); |
a91eb199 | 2310 | if (ret != 0) |
f0fba2ad | 2311 | dev_err(codec->dev, |
a91eb199 MB |
2312 | "Failed to add ReTune Mobile control: %d\n", ret); |
2313 | } | |
2314 | ||
f0fba2ad | 2315 | static void wm8904_handle_pdata(struct snd_soc_codec *codec) |
a91eb199 | 2316 | { |
f0fba2ad | 2317 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
2318 | struct wm8904_pdata *pdata = wm8904->pdata; |
2319 | int ret, i; | |
2320 | ||
2321 | if (!pdata) { | |
f0fba2ad | 2322 | snd_soc_add_controls(codec, wm8904_eq_controls, |
a91eb199 MB |
2323 | ARRAY_SIZE(wm8904_eq_controls)); |
2324 | return; | |
2325 | } | |
2326 | ||
2327 | dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); | |
2328 | ||
2329 | if (pdata->num_drc_cfgs) { | |
2330 | struct snd_kcontrol_new control = | |
2331 | SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, | |
2332 | wm8904_get_drc_enum, wm8904_put_drc_enum); | |
2333 | ||
2334 | /* We need an array of texts for the enum API */ | |
2335 | wm8904->drc_texts = kmalloc(sizeof(char *) | |
2336 | * pdata->num_drc_cfgs, GFP_KERNEL); | |
2337 | if (!wm8904->drc_texts) { | |
f0fba2ad | 2338 | dev_err(codec->dev, |
a91eb199 MB |
2339 | "Failed to allocate %d DRC config texts\n", |
2340 | pdata->num_drc_cfgs); | |
2341 | return; | |
2342 | } | |
2343 | ||
2344 | for (i = 0; i < pdata->num_drc_cfgs; i++) | |
2345 | wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; | |
2346 | ||
2347 | wm8904->drc_enum.max = pdata->num_drc_cfgs; | |
2348 | wm8904->drc_enum.texts = wm8904->drc_texts; | |
2349 | ||
f0fba2ad | 2350 | ret = snd_soc_add_controls(codec, &control, 1); |
a91eb199 | 2351 | if (ret != 0) |
f0fba2ad | 2352 | dev_err(codec->dev, |
a91eb199 MB |
2353 | "Failed to add DRC mode control: %d\n", ret); |
2354 | ||
2355 | wm8904_set_drc(codec); | |
2356 | } | |
2357 | ||
2358 | dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", | |
2359 | pdata->num_retune_mobile_cfgs); | |
2360 | ||
2361 | if (pdata->num_retune_mobile_cfgs) | |
f0fba2ad | 2362 | wm8904_handle_retune_mobile_pdata(codec); |
a91eb199 | 2363 | else |
f0fba2ad | 2364 | snd_soc_add_controls(codec, wm8904_eq_controls, |
a91eb199 MB |
2365 | ARRAY_SIZE(wm8904_eq_controls)); |
2366 | } | |
2367 | ||
a91eb199 | 2368 | |
f0fba2ad | 2369 | static int wm8904_probe(struct snd_soc_codec *codec) |
a91eb199 | 2370 | { |
f0fba2ad | 2371 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
cdce4e9b | 2372 | struct wm8904_pdata *pdata = wm8904->pdata; |
f0fba2ad | 2373 | int ret, i; |
a91eb199 | 2374 | |
c1334218 MB |
2375 | codec->cache_sync = 1; |
2376 | codec->idle_bias_off = 1; | |
a91eb199 | 2377 | |
8c126474 MB |
2378 | switch (wm8904->devtype) { |
2379 | case WM8904: | |
2380 | break; | |
2381 | case WM8912: | |
2382 | memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); | |
2383 | break; | |
2384 | default: | |
2385 | dev_err(codec->dev, "Unknown device type %d\n", | |
2386 | wm8904->devtype); | |
f0fba2ad | 2387 | return -EINVAL; |
8c126474 MB |
2388 | } |
2389 | ||
f0fba2ad | 2390 | ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); |
a91eb199 MB |
2391 | if (ret != 0) { |
2392 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
f0fba2ad | 2393 | return ret; |
a91eb199 MB |
2394 | } |
2395 | ||
2396 | for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) | |
2397 | wm8904->supplies[i].supply = wm8904_supply_names[i]; | |
2398 | ||
2399 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies), | |
2400 | wm8904->supplies); | |
2401 | if (ret != 0) { | |
2402 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
f0fba2ad | 2403 | return ret; |
a91eb199 MB |
2404 | } |
2405 | ||
2406 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), | |
2407 | wm8904->supplies); | |
2408 | if (ret != 0) { | |
2409 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
2410 | goto err_get; | |
2411 | } | |
2412 | ||
2413 | ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID); | |
2414 | if (ret < 0) { | |
2415 | dev_err(codec->dev, "Failed to read ID register\n"); | |
2416 | goto err_enable; | |
2417 | } | |
2418 | if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) { | |
2419 | dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret); | |
2420 | ret = -EINVAL; | |
2421 | goto err_enable; | |
2422 | } | |
2423 | ||
2424 | ret = snd_soc_read(codec, WM8904_REVISION); | |
2425 | if (ret < 0) { | |
2426 | dev_err(codec->dev, "Failed to read device revision: %d\n", | |
2427 | ret); | |
2428 | goto err_enable; | |
2429 | } | |
2430 | dev_info(codec->dev, "revision %c\n", ret + 'A'); | |
2431 | ||
2432 | ret = wm8904_reset(codec); | |
2433 | if (ret < 0) { | |
2434 | dev_err(codec->dev, "Failed to issue reset\n"); | |
2435 | goto err_enable; | |
2436 | } | |
2437 | ||
a91eb199 MB |
2438 | /* Change some default settings - latch VU and enable ZC */ |
2439 | wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU; | |
2440 | wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU; | |
2441 | wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU; | |
2442 | wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU; | |
2443 | wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU | | |
2444 | WM8904_HPOUTLZC; | |
2445 | wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU | | |
2446 | WM8904_HPOUTRZC; | |
2447 | wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU | | |
2448 | WM8904_LINEOUTLZC; | |
2449 | wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU | | |
2450 | WM8904_LINEOUTRZC; | |
2451 | wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; | |
2452 | ||
cdce4e9b MB |
2453 | /* Apply configuration from the platform data. */ |
2454 | if (wm8904->pdata) { | |
2455 | for (i = 0; i < WM8904_GPIO_REGS; i++) { | |
2456 | if (!pdata->gpio_cfg[i]) | |
2457 | continue; | |
2458 | ||
2459 | wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i] | |
2460 | = pdata->gpio_cfg[i] & 0xffff; | |
2461 | } | |
fbc2dae8 MB |
2462 | |
2463 | /* Zero is the default value for these anyway */ | |
2464 | for (i = 0; i < WM8904_MIC_REGS; i++) | |
2465 | wm8904->reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] | |
2466 | = pdata->mic_cfg[i]; | |
cdce4e9b MB |
2467 | } |
2468 | ||
a91eb199 MB |
2469 | /* Set Class W by default - this will be managed by the Class |
2470 | * G widget at runtime where bypass paths are available. | |
2471 | */ | |
2472 | wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR; | |
2473 | ||
2474 | /* Use normal bias source */ | |
2475 | wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL; | |
2476 | ||
2477 | wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2478 | ||
2479 | /* Bias level configuration will have done an extra enable */ | |
2480 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2481 | ||
f0fba2ad | 2482 | wm8904_handle_pdata(codec); |
a91eb199 | 2483 | |
f0fba2ad | 2484 | wm8904_add_widgets(codec); |
a91eb199 MB |
2485 | |
2486 | return 0; | |
2487 | ||
2488 | err_enable: | |
2489 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2490 | err_get: | |
2491 | regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
a91eb199 MB |
2492 | return ret; |
2493 | } | |
2494 | ||
f0fba2ad | 2495 | static int wm8904_remove(struct snd_soc_codec *codec) |
a91eb199 | 2496 | { |
f0fba2ad LG |
2497 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
2498 | ||
2499 | wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
a91eb199 | 2500 | regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); |
f0fba2ad LG |
2501 | |
2502 | return 0; | |
a91eb199 MB |
2503 | } |
2504 | ||
f0fba2ad LG |
2505 | static struct snd_soc_codec_driver soc_codec_dev_wm8904 = { |
2506 | .probe = wm8904_probe, | |
2507 | .remove = wm8904_remove, | |
2508 | .suspend = wm8904_suspend, | |
2509 | .resume = wm8904_resume, | |
2510 | .set_bias_level = wm8904_set_bias_level, | |
2511 | .reg_cache_size = ARRAY_SIZE(wm8904_reg), | |
2512 | .reg_word_size = sizeof(u16), | |
2513 | .reg_cache_default = wm8904_reg, | |
2514 | .volatile_register = wm8904_volatile_register, | |
2515 | }; | |
2516 | ||
a91eb199 MB |
2517 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
2518 | static __devinit int wm8904_i2c_probe(struct i2c_client *i2c, | |
2519 | const struct i2c_device_id *id) | |
2520 | { | |
2521 | struct wm8904_priv *wm8904; | |
f0fba2ad | 2522 | int ret; |
a91eb199 MB |
2523 | |
2524 | wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL); | |
2525 | if (wm8904 == NULL) | |
2526 | return -ENOMEM; | |
2527 | ||
8c126474 | 2528 | wm8904->devtype = id->driver_data; |
a91eb199 | 2529 | i2c_set_clientdata(i2c, wm8904); |
f0fba2ad | 2530 | wm8904->control_data = i2c; |
a91eb199 MB |
2531 | wm8904->pdata = i2c->dev.platform_data; |
2532 | ||
f0fba2ad LG |
2533 | ret = snd_soc_register_codec(&i2c->dev, |
2534 | &soc_codec_dev_wm8904, &wm8904_dai, 1); | |
2535 | if (ret < 0) | |
2536 | kfree(wm8904); | |
2537 | return ret; | |
a91eb199 MB |
2538 | } |
2539 | ||
2540 | static __devexit int wm8904_i2c_remove(struct i2c_client *client) | |
2541 | { | |
f0fba2ad LG |
2542 | snd_soc_unregister_codec(&client->dev); |
2543 | kfree(i2c_get_clientdata(client)); | |
a91eb199 MB |
2544 | return 0; |
2545 | } | |
2546 | ||
2547 | static const struct i2c_device_id wm8904_i2c_id[] = { | |
8c126474 MB |
2548 | { "wm8904", WM8904 }, |
2549 | { "wm8912", WM8912 }, | |
a91eb199 MB |
2550 | { } |
2551 | }; | |
2552 | MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); | |
2553 | ||
2554 | static struct i2c_driver wm8904_i2c_driver = { | |
2555 | .driver = { | |
f0fba2ad | 2556 | .name = "wm8904-codec", |
a91eb199 MB |
2557 | .owner = THIS_MODULE, |
2558 | }, | |
2559 | .probe = wm8904_i2c_probe, | |
2560 | .remove = __devexit_p(wm8904_i2c_remove), | |
2561 | .id_table = wm8904_i2c_id, | |
2562 | }; | |
2563 | #endif | |
2564 | ||
2565 | static int __init wm8904_modinit(void) | |
2566 | { | |
f0fba2ad | 2567 | int ret = 0; |
a91eb199 MB |
2568 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
2569 | ret = i2c_add_driver(&wm8904_i2c_driver); | |
2570 | if (ret != 0) { | |
f0fba2ad | 2571 | printk(KERN_ERR "Failed to register wm8904 I2C driver: %d\n", |
a91eb199 MB |
2572 | ret); |
2573 | } | |
2574 | #endif | |
f0fba2ad | 2575 | return ret; |
a91eb199 MB |
2576 | } |
2577 | module_init(wm8904_modinit); | |
2578 | ||
2579 | static void __exit wm8904_exit(void) | |
2580 | { | |
2581 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
2582 | i2c_del_driver(&wm8904_i2c_driver); | |
2583 | #endif | |
2584 | } | |
2585 | module_exit(wm8904_exit); | |
2586 | ||
2587 | MODULE_DESCRIPTION("ASoC WM8904 driver"); | |
2588 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
2589 | MODULE_LICENSE("GPL"); |