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1 | /* |
2 | * wm8904.c -- WM8904 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/i2c.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/consumer.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
a91eb199 MB |
23 | #include <sound/core.h> |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
27 | #include <sound/soc-dapm.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/tlv.h> | |
30 | #include <sound/wm8904.h> | |
31 | ||
32 | #include "wm8904.h" | |
33 | ||
8c126474 MB |
34 | enum wm8904_type { |
35 | WM8904, | |
36 | WM8912, | |
37 | }; | |
38 | ||
a91eb199 MB |
39 | #define WM8904_NUM_DCS_CHANNELS 4 |
40 | ||
41 | #define WM8904_NUM_SUPPLIES 5 | |
42 | static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { | |
43 | "DCVDD", | |
44 | "DBVDD", | |
45 | "AVDD", | |
46 | "CPVDD", | |
47 | "MICVDD", | |
48 | }; | |
49 | ||
50 | /* codec private data */ | |
51 | struct wm8904_priv { | |
f0fba2ad | 52 | |
8c126474 | 53 | enum wm8904_type devtype; |
f0fba2ad | 54 | void *control_data; |
8c126474 | 55 | |
a91eb199 MB |
56 | struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; |
57 | ||
58 | struct wm8904_pdata *pdata; | |
59 | ||
60 | int deemph; | |
61 | ||
62 | /* Platform provided DRC configuration */ | |
63 | const char **drc_texts; | |
64 | int drc_cfg; | |
65 | struct soc_enum drc_enum; | |
66 | ||
67 | /* Platform provided ReTune mobile configuration */ | |
68 | int num_retune_mobile_texts; | |
69 | const char **retune_mobile_texts; | |
70 | int retune_mobile_cfg; | |
71 | struct soc_enum retune_mobile_enum; | |
72 | ||
73 | /* FLL setup */ | |
74 | int fll_src; | |
75 | int fll_fref; | |
76 | int fll_fout; | |
77 | ||
78 | /* Clocking configuration */ | |
79 | unsigned int mclk_rate; | |
80 | int sysclk_src; | |
81 | unsigned int sysclk_rate; | |
82 | ||
83 | int tdm_width; | |
84 | int tdm_slots; | |
85 | int bclk; | |
86 | int fs; | |
87 | ||
88 | /* DC servo configuration - cached offset values */ | |
89 | int dcs_state[WM8904_NUM_DCS_CHANNELS]; | |
90 | }; | |
91 | ||
92 | static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = { | |
93 | 0x8904, /* R0 - SW Reset and ID */ | |
94 | 0x0000, /* R1 - Revision */ | |
95 | 0x0000, /* R2 */ | |
96 | 0x0000, /* R3 */ | |
97 | 0x0018, /* R4 - Bias Control 0 */ | |
98 | 0x0000, /* R5 - VMID Control 0 */ | |
99 | 0x0000, /* R6 - Mic Bias Control 0 */ | |
100 | 0x0000, /* R7 - Mic Bias Control 1 */ | |
101 | 0x0001, /* R8 - Analogue DAC 0 */ | |
102 | 0x9696, /* R9 - mic Filter Control */ | |
103 | 0x0001, /* R10 - Analogue ADC 0 */ | |
104 | 0x0000, /* R11 */ | |
105 | 0x0000, /* R12 - Power Management 0 */ | |
106 | 0x0000, /* R13 */ | |
107 | 0x0000, /* R14 - Power Management 2 */ | |
108 | 0x0000, /* R15 - Power Management 3 */ | |
109 | 0x0000, /* R16 */ | |
110 | 0x0000, /* R17 */ | |
111 | 0x0000, /* R18 - Power Management 6 */ | |
112 | 0x0000, /* R19 */ | |
113 | 0x945E, /* R20 - Clock Rates 0 */ | |
114 | 0x0C05, /* R21 - Clock Rates 1 */ | |
115 | 0x0006, /* R22 - Clock Rates 2 */ | |
116 | 0x0000, /* R23 */ | |
117 | 0x0050, /* R24 - Audio Interface 0 */ | |
118 | 0x000A, /* R25 - Audio Interface 1 */ | |
119 | 0x00E4, /* R26 - Audio Interface 2 */ | |
120 | 0x0040, /* R27 - Audio Interface 3 */ | |
121 | 0x0000, /* R28 */ | |
122 | 0x0000, /* R29 */ | |
123 | 0x00C0, /* R30 - DAC Digital Volume Left */ | |
124 | 0x00C0, /* R31 - DAC Digital Volume Right */ | |
125 | 0x0000, /* R32 - DAC Digital 0 */ | |
126 | 0x0008, /* R33 - DAC Digital 1 */ | |
127 | 0x0000, /* R34 */ | |
128 | 0x0000, /* R35 */ | |
129 | 0x00C0, /* R36 - ADC Digital Volume Left */ | |
130 | 0x00C0, /* R37 - ADC Digital Volume Right */ | |
131 | 0x0010, /* R38 - ADC Digital 0 */ | |
132 | 0x0000, /* R39 - Digital Microphone 0 */ | |
133 | 0x01AF, /* R40 - DRC 0 */ | |
134 | 0x3248, /* R41 - DRC 1 */ | |
135 | 0x0000, /* R42 - DRC 2 */ | |
136 | 0x0000, /* R43 - DRC 3 */ | |
137 | 0x0085, /* R44 - Analogue Left Input 0 */ | |
138 | 0x0085, /* R45 - Analogue Right Input 0 */ | |
139 | 0x0044, /* R46 - Analogue Left Input 1 */ | |
140 | 0x0044, /* R47 - Analogue Right Input 1 */ | |
141 | 0x0000, /* R48 */ | |
142 | 0x0000, /* R49 */ | |
143 | 0x0000, /* R50 */ | |
144 | 0x0000, /* R51 */ | |
145 | 0x0000, /* R52 */ | |
146 | 0x0000, /* R53 */ | |
147 | 0x0000, /* R54 */ | |
148 | 0x0000, /* R55 */ | |
149 | 0x0000, /* R56 */ | |
150 | 0x002D, /* R57 - Analogue OUT1 Left */ | |
151 | 0x002D, /* R58 - Analogue OUT1 Right */ | |
152 | 0x0039, /* R59 - Analogue OUT2 Left */ | |
153 | 0x0039, /* R60 - Analogue OUT2 Right */ | |
154 | 0x0000, /* R61 - Analogue OUT12 ZC */ | |
155 | 0x0000, /* R62 */ | |
156 | 0x0000, /* R63 */ | |
157 | 0x0000, /* R64 */ | |
158 | 0x0000, /* R65 */ | |
159 | 0x0000, /* R66 */ | |
160 | 0x0000, /* R67 - DC Servo 0 */ | |
161 | 0x0000, /* R68 - DC Servo 1 */ | |
162 | 0xAAAA, /* R69 - DC Servo 2 */ | |
163 | 0x0000, /* R70 */ | |
164 | 0xAAAA, /* R71 - DC Servo 4 */ | |
165 | 0xAAAA, /* R72 - DC Servo 5 */ | |
166 | 0x0000, /* R73 - DC Servo 6 */ | |
167 | 0x0000, /* R74 - DC Servo 7 */ | |
168 | 0x0000, /* R75 - DC Servo 8 */ | |
169 | 0x0000, /* R76 - DC Servo 9 */ | |
170 | 0x0000, /* R77 - DC Servo Readback 0 */ | |
171 | 0x0000, /* R78 */ | |
172 | 0x0000, /* R79 */ | |
173 | 0x0000, /* R80 */ | |
174 | 0x0000, /* R81 */ | |
175 | 0x0000, /* R82 */ | |
176 | 0x0000, /* R83 */ | |
177 | 0x0000, /* R84 */ | |
178 | 0x0000, /* R85 */ | |
179 | 0x0000, /* R86 */ | |
180 | 0x0000, /* R87 */ | |
181 | 0x0000, /* R88 */ | |
182 | 0x0000, /* R89 */ | |
183 | 0x0000, /* R90 - Analogue HP 0 */ | |
184 | 0x0000, /* R91 */ | |
185 | 0x0000, /* R92 */ | |
186 | 0x0000, /* R93 */ | |
187 | 0x0000, /* R94 - Analogue Lineout 0 */ | |
188 | 0x0000, /* R95 */ | |
189 | 0x0000, /* R96 */ | |
190 | 0x0000, /* R97 */ | |
191 | 0x0000, /* R98 - Charge Pump 0 */ | |
192 | 0x0000, /* R99 */ | |
193 | 0x0000, /* R100 */ | |
194 | 0x0000, /* R101 */ | |
195 | 0x0000, /* R102 */ | |
196 | 0x0000, /* R103 */ | |
197 | 0x0004, /* R104 - Class W 0 */ | |
198 | 0x0000, /* R105 */ | |
199 | 0x0000, /* R106 */ | |
200 | 0x0000, /* R107 */ | |
201 | 0x0000, /* R108 - Write Sequencer 0 */ | |
202 | 0x0000, /* R109 - Write Sequencer 1 */ | |
203 | 0x0000, /* R110 - Write Sequencer 2 */ | |
204 | 0x0000, /* R111 - Write Sequencer 3 */ | |
205 | 0x0000, /* R112 - Write Sequencer 4 */ | |
206 | 0x0000, /* R113 */ | |
207 | 0x0000, /* R114 */ | |
208 | 0x0000, /* R115 */ | |
209 | 0x0000, /* R116 - FLL Control 1 */ | |
210 | 0x0007, /* R117 - FLL Control 2 */ | |
211 | 0x0000, /* R118 - FLL Control 3 */ | |
212 | 0x2EE0, /* R119 - FLL Control 4 */ | |
213 | 0x0004, /* R120 - FLL Control 5 */ | |
214 | 0x0014, /* R121 - GPIO Control 1 */ | |
215 | 0x0010, /* R122 - GPIO Control 2 */ | |
216 | 0x0010, /* R123 - GPIO Control 3 */ | |
217 | 0x0000, /* R124 - GPIO Control 4 */ | |
218 | 0x0000, /* R125 */ | |
219 | 0x0000, /* R126 - Digital Pulls */ | |
220 | 0x0000, /* R127 - Interrupt Status */ | |
221 | 0xFFFF, /* R128 - Interrupt Status Mask */ | |
222 | 0x0000, /* R129 - Interrupt Polarity */ | |
223 | 0x0000, /* R130 - Interrupt Debounce */ | |
224 | 0x0000, /* R131 */ | |
225 | 0x0000, /* R132 */ | |
226 | 0x0000, /* R133 */ | |
227 | 0x0000, /* R134 - EQ1 */ | |
228 | 0x000C, /* R135 - EQ2 */ | |
229 | 0x000C, /* R136 - EQ3 */ | |
230 | 0x000C, /* R137 - EQ4 */ | |
231 | 0x000C, /* R138 - EQ5 */ | |
232 | 0x000C, /* R139 - EQ6 */ | |
233 | 0x0FCA, /* R140 - EQ7 */ | |
234 | 0x0400, /* R141 - EQ8 */ | |
235 | 0x00D8, /* R142 - EQ9 */ | |
236 | 0x1EB5, /* R143 - EQ10 */ | |
237 | 0xF145, /* R144 - EQ11 */ | |
238 | 0x0B75, /* R145 - EQ12 */ | |
239 | 0x01C5, /* R146 - EQ13 */ | |
240 | 0x1C58, /* R147 - EQ14 */ | |
241 | 0xF373, /* R148 - EQ15 */ | |
242 | 0x0A54, /* R149 - EQ16 */ | |
243 | 0x0558, /* R150 - EQ17 */ | |
244 | 0x168E, /* R151 - EQ18 */ | |
245 | 0xF829, /* R152 - EQ19 */ | |
246 | 0x07AD, /* R153 - EQ20 */ | |
247 | 0x1103, /* R154 - EQ21 */ | |
248 | 0x0564, /* R155 - EQ22 */ | |
249 | 0x0559, /* R156 - EQ23 */ | |
250 | 0x4000, /* R157 - EQ24 */ | |
251 | 0x0000, /* R158 */ | |
252 | 0x0000, /* R159 */ | |
253 | 0x0000, /* R160 */ | |
254 | 0x0000, /* R161 - Control Interface Test 1 */ | |
255 | 0x0000, /* R162 */ | |
256 | 0x0000, /* R163 */ | |
257 | 0x0000, /* R164 */ | |
258 | 0x0000, /* R165 */ | |
259 | 0x0000, /* R166 */ | |
260 | 0x0000, /* R167 */ | |
261 | 0x0000, /* R168 */ | |
262 | 0x0000, /* R169 */ | |
263 | 0x0000, /* R170 */ | |
264 | 0x0000, /* R171 */ | |
265 | 0x0000, /* R172 */ | |
266 | 0x0000, /* R173 */ | |
267 | 0x0000, /* R174 */ | |
268 | 0x0000, /* R175 */ | |
269 | 0x0000, /* R176 */ | |
270 | 0x0000, /* R177 */ | |
271 | 0x0000, /* R178 */ | |
272 | 0x0000, /* R179 */ | |
273 | 0x0000, /* R180 */ | |
274 | 0x0000, /* R181 */ | |
275 | 0x0000, /* R182 */ | |
276 | 0x0000, /* R183 */ | |
277 | 0x0000, /* R184 */ | |
278 | 0x0000, /* R185 */ | |
279 | 0x0000, /* R186 */ | |
280 | 0x0000, /* R187 */ | |
281 | 0x0000, /* R188 */ | |
282 | 0x0000, /* R189 */ | |
283 | 0x0000, /* R190 */ | |
284 | 0x0000, /* R191 */ | |
285 | 0x0000, /* R192 */ | |
286 | 0x0000, /* R193 */ | |
287 | 0x0000, /* R194 */ | |
288 | 0x0000, /* R195 */ | |
289 | 0x0000, /* R196 */ | |
290 | 0x0000, /* R197 */ | |
291 | 0x0000, /* R198 */ | |
292 | 0x0000, /* R199 */ | |
293 | 0x0000, /* R200 */ | |
294 | 0x0000, /* R201 */ | |
295 | 0x0000, /* R202 */ | |
296 | 0x0000, /* R203 */ | |
297 | 0x0000, /* R204 - Analogue Output Bias 0 */ | |
298 | 0x0000, /* R205 */ | |
299 | 0x0000, /* R206 */ | |
300 | 0x0000, /* R207 */ | |
301 | 0x0000, /* R208 */ | |
302 | 0x0000, /* R209 */ | |
303 | 0x0000, /* R210 */ | |
304 | 0x0000, /* R211 */ | |
305 | 0x0000, /* R212 */ | |
306 | 0x0000, /* R213 */ | |
307 | 0x0000, /* R214 */ | |
308 | 0x0000, /* R215 */ | |
309 | 0x0000, /* R216 */ | |
310 | 0x0000, /* R217 */ | |
311 | 0x0000, /* R218 */ | |
312 | 0x0000, /* R219 */ | |
313 | 0x0000, /* R220 */ | |
314 | 0x0000, /* R221 */ | |
315 | 0x0000, /* R222 */ | |
316 | 0x0000, /* R223 */ | |
317 | 0x0000, /* R224 */ | |
318 | 0x0000, /* R225 */ | |
319 | 0x0000, /* R226 */ | |
320 | 0x0000, /* R227 */ | |
321 | 0x0000, /* R228 */ | |
322 | 0x0000, /* R229 */ | |
323 | 0x0000, /* R230 */ | |
324 | 0x0000, /* R231 */ | |
325 | 0x0000, /* R232 */ | |
326 | 0x0000, /* R233 */ | |
327 | 0x0000, /* R234 */ | |
328 | 0x0000, /* R235 */ | |
329 | 0x0000, /* R236 */ | |
330 | 0x0000, /* R237 */ | |
331 | 0x0000, /* R238 */ | |
332 | 0x0000, /* R239 */ | |
333 | 0x0000, /* R240 */ | |
334 | 0x0000, /* R241 */ | |
335 | 0x0000, /* R242 */ | |
336 | 0x0000, /* R243 */ | |
337 | 0x0000, /* R244 */ | |
338 | 0x0000, /* R245 */ | |
339 | 0x0000, /* R246 */ | |
340 | 0x0000, /* R247 - FLL NCO Test 0 */ | |
341 | 0x0019, /* R248 - FLL NCO Test 1 */ | |
342 | }; | |
343 | ||
344 | static struct { | |
345 | int readable; | |
346 | int writable; | |
347 | int vol; | |
348 | } wm8904_access[] = { | |
349 | { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */ | |
350 | { 0x0000, 0x0000, 0 }, /* R1 - Revision */ | |
351 | { 0x0000, 0x0000, 0 }, /* R2 */ | |
352 | { 0x0000, 0x0000, 0 }, /* R3 */ | |
353 | { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */ | |
354 | { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */ | |
355 | { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */ | |
356 | { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */ | |
357 | { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */ | |
358 | { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */ | |
359 | { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */ | |
360 | { 0x0000, 0x0000, 0 }, /* R11 */ | |
361 | { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */ | |
362 | { 0x0000, 0x0000, 0 }, /* R13 */ | |
363 | { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */ | |
364 | { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */ | |
365 | { 0x0000, 0x0000, 0 }, /* R16 */ | |
366 | { 0x0000, 0x0000, 0 }, /* R17 */ | |
367 | { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */ | |
368 | { 0x0000, 0x0000, 0 }, /* R19 */ | |
369 | { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */ | |
370 | { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */ | |
371 | { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */ | |
372 | { 0x0000, 0x0000, 0 }, /* R23 */ | |
373 | { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */ | |
374 | { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */ | |
375 | { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */ | |
376 | { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */ | |
377 | { 0x0000, 0x0000, 0 }, /* R28 */ | |
378 | { 0x0000, 0x0000, 0 }, /* R29 */ | |
379 | { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */ | |
380 | { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */ | |
381 | { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */ | |
382 | { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */ | |
383 | { 0x0000, 0x0000, 0 }, /* R34 */ | |
384 | { 0x0000, 0x0000, 0 }, /* R35 */ | |
385 | { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */ | |
386 | { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */ | |
387 | { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */ | |
388 | { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */ | |
389 | { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */ | |
390 | { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */ | |
391 | { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */ | |
392 | { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */ | |
393 | { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */ | |
394 | { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */ | |
395 | { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */ | |
396 | { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */ | |
397 | { 0x0000, 0x0000, 0 }, /* R48 */ | |
398 | { 0x0000, 0x0000, 0 }, /* R49 */ | |
399 | { 0x0000, 0x0000, 0 }, /* R50 */ | |
400 | { 0x0000, 0x0000, 0 }, /* R51 */ | |
401 | { 0x0000, 0x0000, 0 }, /* R52 */ | |
402 | { 0x0000, 0x0000, 0 }, /* R53 */ | |
403 | { 0x0000, 0x0000, 0 }, /* R54 */ | |
404 | { 0x0000, 0x0000, 0 }, /* R55 */ | |
405 | { 0x0000, 0x0000, 0 }, /* R56 */ | |
406 | { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */ | |
407 | { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */ | |
408 | { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */ | |
409 | { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */ | |
410 | { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */ | |
411 | { 0x0000, 0x0000, 0 }, /* R62 */ | |
412 | { 0x0000, 0x0000, 0 }, /* R63 */ | |
413 | { 0x0000, 0x0000, 0 }, /* R64 */ | |
414 | { 0x0000, 0x0000, 0 }, /* R65 */ | |
415 | { 0x0000, 0x0000, 0 }, /* R66 */ | |
416 | { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */ | |
417 | { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */ | |
418 | { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */ | |
419 | { 0x0000, 0x0000, 0 }, /* R70 */ | |
420 | { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */ | |
421 | { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */ | |
422 | { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */ | |
423 | { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */ | |
424 | { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */ | |
425 | { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */ | |
426 | { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */ | |
427 | { 0x0000, 0x0000, 0 }, /* R78 */ | |
428 | { 0x0000, 0x0000, 0 }, /* R79 */ | |
429 | { 0x0000, 0x0000, 0 }, /* R80 */ | |
430 | { 0x0000, 0x0000, 0 }, /* R81 */ | |
431 | { 0x0000, 0x0000, 0 }, /* R82 */ | |
432 | { 0x0000, 0x0000, 0 }, /* R83 */ | |
433 | { 0x0000, 0x0000, 0 }, /* R84 */ | |
434 | { 0x0000, 0x0000, 0 }, /* R85 */ | |
435 | { 0x0000, 0x0000, 0 }, /* R86 */ | |
436 | { 0x0000, 0x0000, 0 }, /* R87 */ | |
437 | { 0x0000, 0x0000, 0 }, /* R88 */ | |
438 | { 0x0000, 0x0000, 0 }, /* R89 */ | |
439 | { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */ | |
440 | { 0x0000, 0x0000, 0 }, /* R91 */ | |
441 | { 0x0000, 0x0000, 0 }, /* R92 */ | |
442 | { 0x0000, 0x0000, 0 }, /* R93 */ | |
443 | { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */ | |
444 | { 0x0000, 0x0000, 0 }, /* R95 */ | |
445 | { 0x0000, 0x0000, 0 }, /* R96 */ | |
446 | { 0x0000, 0x0000, 0 }, /* R97 */ | |
447 | { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */ | |
448 | { 0x0000, 0x0000, 0 }, /* R99 */ | |
449 | { 0x0000, 0x0000, 0 }, /* R100 */ | |
450 | { 0x0000, 0x0000, 0 }, /* R101 */ | |
451 | { 0x0000, 0x0000, 0 }, /* R102 */ | |
452 | { 0x0000, 0x0000, 0 }, /* R103 */ | |
453 | { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */ | |
454 | { 0x0000, 0x0000, 0 }, /* R105 */ | |
455 | { 0x0000, 0x0000, 0 }, /* R106 */ | |
456 | { 0x0000, 0x0000, 0 }, /* R107 */ | |
457 | { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */ | |
458 | { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */ | |
459 | { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */ | |
460 | { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */ | |
461 | { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */ | |
462 | { 0x0000, 0x0000, 0 }, /* R113 */ | |
463 | { 0x0000, 0x0000, 0 }, /* R114 */ | |
464 | { 0x0000, 0x0000, 0 }, /* R115 */ | |
465 | { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */ | |
466 | { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */ | |
467 | { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */ | |
468 | { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */ | |
469 | { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */ | |
470 | { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */ | |
471 | { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */ | |
472 | { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */ | |
473 | { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */ | |
474 | { 0x0000, 0x0000, 0 }, /* R125 */ | |
475 | { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */ | |
476 | { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */ | |
477 | { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */ | |
478 | { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */ | |
479 | { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */ | |
480 | { 0x0000, 0x0000, 0 }, /* R131 */ | |
481 | { 0x0000, 0x0000, 0 }, /* R132 */ | |
482 | { 0x0000, 0x0000, 0 }, /* R133 */ | |
483 | { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */ | |
484 | { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */ | |
485 | { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */ | |
486 | { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */ | |
487 | { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */ | |
488 | { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */ | |
489 | { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */ | |
490 | { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */ | |
491 | { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */ | |
492 | { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */ | |
493 | { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */ | |
494 | { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */ | |
495 | { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */ | |
496 | { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */ | |
497 | { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */ | |
498 | { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */ | |
499 | { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */ | |
500 | { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */ | |
501 | { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */ | |
502 | { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */ | |
503 | { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */ | |
504 | { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */ | |
505 | { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */ | |
506 | { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */ | |
507 | { 0x0000, 0x0000, 0 }, /* R158 */ | |
508 | { 0x0000, 0x0000, 0 }, /* R159 */ | |
509 | { 0x0000, 0x0000, 0 }, /* R160 */ | |
510 | { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */ | |
511 | { 0x0000, 0x0000, 0 }, /* R162 */ | |
512 | { 0x0000, 0x0000, 0 }, /* R163 */ | |
513 | { 0x0000, 0x0000, 0 }, /* R164 */ | |
514 | { 0x0000, 0x0000, 0 }, /* R165 */ | |
515 | { 0x0000, 0x0000, 0 }, /* R166 */ | |
516 | { 0x0000, 0x0000, 0 }, /* R167 */ | |
517 | { 0x0000, 0x0000, 0 }, /* R168 */ | |
518 | { 0x0000, 0x0000, 0 }, /* R169 */ | |
519 | { 0x0000, 0x0000, 0 }, /* R170 */ | |
520 | { 0x0000, 0x0000, 0 }, /* R171 */ | |
521 | { 0x0000, 0x0000, 0 }, /* R172 */ | |
522 | { 0x0000, 0x0000, 0 }, /* R173 */ | |
523 | { 0x0000, 0x0000, 0 }, /* R174 */ | |
524 | { 0x0000, 0x0000, 0 }, /* R175 */ | |
525 | { 0x0000, 0x0000, 0 }, /* R176 */ | |
526 | { 0x0000, 0x0000, 0 }, /* R177 */ | |
527 | { 0x0000, 0x0000, 0 }, /* R178 */ | |
528 | { 0x0000, 0x0000, 0 }, /* R179 */ | |
529 | { 0x0000, 0x0000, 0 }, /* R180 */ | |
530 | { 0x0000, 0x0000, 0 }, /* R181 */ | |
531 | { 0x0000, 0x0000, 0 }, /* R182 */ | |
532 | { 0x0000, 0x0000, 0 }, /* R183 */ | |
533 | { 0x0000, 0x0000, 0 }, /* R184 */ | |
534 | { 0x0000, 0x0000, 0 }, /* R185 */ | |
535 | { 0x0000, 0x0000, 0 }, /* R186 */ | |
536 | { 0x0000, 0x0000, 0 }, /* R187 */ | |
537 | { 0x0000, 0x0000, 0 }, /* R188 */ | |
538 | { 0x0000, 0x0000, 0 }, /* R189 */ | |
539 | { 0x0000, 0x0000, 0 }, /* R190 */ | |
540 | { 0x0000, 0x0000, 0 }, /* R191 */ | |
541 | { 0x0000, 0x0000, 0 }, /* R192 */ | |
542 | { 0x0000, 0x0000, 0 }, /* R193 */ | |
543 | { 0x0000, 0x0000, 0 }, /* R194 */ | |
544 | { 0x0000, 0x0000, 0 }, /* R195 */ | |
545 | { 0x0000, 0x0000, 0 }, /* R196 */ | |
546 | { 0x0000, 0x0000, 0 }, /* R197 */ | |
547 | { 0x0000, 0x0000, 0 }, /* R198 */ | |
548 | { 0x0000, 0x0000, 0 }, /* R199 */ | |
549 | { 0x0000, 0x0000, 0 }, /* R200 */ | |
550 | { 0x0000, 0x0000, 0 }, /* R201 */ | |
551 | { 0x0000, 0x0000, 0 }, /* R202 */ | |
552 | { 0x0000, 0x0000, 0 }, /* R203 */ | |
553 | { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */ | |
554 | { 0x0000, 0x0000, 0 }, /* R205 */ | |
555 | { 0x0000, 0x0000, 0 }, /* R206 */ | |
556 | { 0x0000, 0x0000, 0 }, /* R207 */ | |
557 | { 0x0000, 0x0000, 0 }, /* R208 */ | |
558 | { 0x0000, 0x0000, 0 }, /* R209 */ | |
559 | { 0x0000, 0x0000, 0 }, /* R210 */ | |
560 | { 0x0000, 0x0000, 0 }, /* R211 */ | |
561 | { 0x0000, 0x0000, 0 }, /* R212 */ | |
562 | { 0x0000, 0x0000, 0 }, /* R213 */ | |
563 | { 0x0000, 0x0000, 0 }, /* R214 */ | |
564 | { 0x0000, 0x0000, 0 }, /* R215 */ | |
565 | { 0x0000, 0x0000, 0 }, /* R216 */ | |
566 | { 0x0000, 0x0000, 0 }, /* R217 */ | |
567 | { 0x0000, 0x0000, 0 }, /* R218 */ | |
568 | { 0x0000, 0x0000, 0 }, /* R219 */ | |
569 | { 0x0000, 0x0000, 0 }, /* R220 */ | |
570 | { 0x0000, 0x0000, 0 }, /* R221 */ | |
571 | { 0x0000, 0x0000, 0 }, /* R222 */ | |
572 | { 0x0000, 0x0000, 0 }, /* R223 */ | |
573 | { 0x0000, 0x0000, 0 }, /* R224 */ | |
574 | { 0x0000, 0x0000, 0 }, /* R225 */ | |
575 | { 0x0000, 0x0000, 0 }, /* R226 */ | |
576 | { 0x0000, 0x0000, 0 }, /* R227 */ | |
577 | { 0x0000, 0x0000, 0 }, /* R228 */ | |
578 | { 0x0000, 0x0000, 0 }, /* R229 */ | |
579 | { 0x0000, 0x0000, 0 }, /* R230 */ | |
580 | { 0x0000, 0x0000, 0 }, /* R231 */ | |
581 | { 0x0000, 0x0000, 0 }, /* R232 */ | |
582 | { 0x0000, 0x0000, 0 }, /* R233 */ | |
583 | { 0x0000, 0x0000, 0 }, /* R234 */ | |
584 | { 0x0000, 0x0000, 0 }, /* R235 */ | |
585 | { 0x0000, 0x0000, 0 }, /* R236 */ | |
586 | { 0x0000, 0x0000, 0 }, /* R237 */ | |
587 | { 0x0000, 0x0000, 0 }, /* R238 */ | |
588 | { 0x0000, 0x0000, 0 }, /* R239 */ | |
589 | { 0x0000, 0x0000, 0 }, /* R240 */ | |
590 | { 0x0000, 0x0000, 0 }, /* R241 */ | |
591 | { 0x0000, 0x0000, 0 }, /* R242 */ | |
592 | { 0x0000, 0x0000, 0 }, /* R243 */ | |
593 | { 0x0000, 0x0000, 0 }, /* R244 */ | |
594 | { 0x0000, 0x0000, 0 }, /* R245 */ | |
595 | { 0x0000, 0x0000, 0 }, /* R246 */ | |
596 | { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */ | |
597 | { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */ | |
598 | }; | |
599 | ||
600 | static int wm8904_volatile_register(unsigned int reg) | |
601 | { | |
602 | return wm8904_access[reg].vol; | |
603 | } | |
604 | ||
605 | static int wm8904_reset(struct snd_soc_codec *codec) | |
606 | { | |
607 | return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0); | |
608 | } | |
609 | ||
610 | static int wm8904_configure_clocking(struct snd_soc_codec *codec) | |
611 | { | |
b2c812e2 | 612 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
613 | unsigned int clock0, clock2, rate; |
614 | ||
615 | /* Gate the clock while we're updating to avoid misclocking */ | |
616 | clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); | |
617 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
618 | WM8904_SYSCLK_SRC, 0); | |
619 | ||
620 | /* This should be done on init() for bypass paths */ | |
621 | switch (wm8904->sysclk_src) { | |
622 | case WM8904_CLK_MCLK: | |
623 | dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); | |
624 | ||
625 | clock2 &= ~WM8904_SYSCLK_SRC; | |
626 | rate = wm8904->mclk_rate; | |
627 | ||
628 | /* Ensure the FLL is stopped */ | |
629 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
630 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
631 | break; | |
632 | ||
633 | case WM8904_CLK_FLL: | |
634 | dev_dbg(codec->dev, "Using %dHz FLL clock\n", | |
635 | wm8904->fll_fout); | |
636 | ||
637 | clock2 |= WM8904_SYSCLK_SRC; | |
638 | rate = wm8904->fll_fout; | |
639 | break; | |
640 | ||
641 | default: | |
642 | dev_err(codec->dev, "System clock not configured\n"); | |
643 | return -EINVAL; | |
644 | } | |
645 | ||
646 | /* SYSCLK shouldn't be over 13.5MHz */ | |
647 | if (rate > 13500000) { | |
648 | clock0 = WM8904_MCLK_DIV; | |
649 | wm8904->sysclk_rate = rate / 2; | |
650 | } else { | |
651 | clock0 = 0; | |
652 | wm8904->sysclk_rate = rate; | |
653 | } | |
654 | ||
655 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, | |
656 | clock0); | |
657 | ||
658 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
659 | WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); | |
660 | ||
661 | dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); | |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
666 | static void wm8904_set_drc(struct snd_soc_codec *codec) | |
667 | { | |
b2c812e2 | 668 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
669 | struct wm8904_pdata *pdata = wm8904->pdata; |
670 | int save, i; | |
671 | ||
672 | /* Save any enables; the configuration should clear them. */ | |
673 | save = snd_soc_read(codec, WM8904_DRC_0); | |
674 | ||
675 | for (i = 0; i < WM8904_DRC_REGS; i++) | |
676 | snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff, | |
677 | pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); | |
678 | ||
679 | /* Reenable the DRC */ | |
680 | snd_soc_update_bits(codec, WM8904_DRC_0, | |
681 | WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); | |
682 | } | |
683 | ||
684 | static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, | |
685 | struct snd_ctl_elem_value *ucontrol) | |
686 | { | |
687 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 688 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
689 | struct wm8904_pdata *pdata = wm8904->pdata; |
690 | int value = ucontrol->value.integer.value[0]; | |
691 | ||
692 | if (value >= pdata->num_drc_cfgs) | |
693 | return -EINVAL; | |
694 | ||
695 | wm8904->drc_cfg = value; | |
696 | ||
697 | wm8904_set_drc(codec); | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
702 | static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, | |
703 | struct snd_ctl_elem_value *ucontrol) | |
704 | { | |
705 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 706 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
707 | |
708 | ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | static void wm8904_set_retune_mobile(struct snd_soc_codec *codec) | |
714 | { | |
b2c812e2 | 715 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
716 | struct wm8904_pdata *pdata = wm8904->pdata; |
717 | int best, best_val, save, i, cfg; | |
718 | ||
719 | if (!pdata || !wm8904->num_retune_mobile_texts) | |
720 | return; | |
721 | ||
722 | /* Find the version of the currently selected configuration | |
723 | * with the nearest sample rate. */ | |
724 | cfg = wm8904->retune_mobile_cfg; | |
725 | best = 0; | |
726 | best_val = INT_MAX; | |
727 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
728 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
729 | wm8904->retune_mobile_texts[cfg]) == 0 && | |
730 | abs(pdata->retune_mobile_cfgs[i].rate | |
731 | - wm8904->fs) < best_val) { | |
732 | best = i; | |
733 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
734 | - wm8904->fs); | |
735 | } | |
736 | } | |
737 | ||
738 | dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", | |
739 | pdata->retune_mobile_cfgs[best].name, | |
740 | pdata->retune_mobile_cfgs[best].rate, | |
741 | wm8904->fs); | |
742 | ||
743 | /* The EQ will be disabled while reconfiguring it, remember the | |
744 | * current configuration. | |
745 | */ | |
746 | save = snd_soc_read(codec, WM8904_EQ1); | |
747 | ||
748 | for (i = 0; i < WM8904_EQ_REGS; i++) | |
749 | snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff, | |
750 | pdata->retune_mobile_cfgs[best].regs[i]); | |
751 | ||
752 | snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save); | |
753 | } | |
754 | ||
755 | static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
756 | struct snd_ctl_elem_value *ucontrol) | |
757 | { | |
758 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 759 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
760 | struct wm8904_pdata *pdata = wm8904->pdata; |
761 | int value = ucontrol->value.integer.value[0]; | |
762 | ||
763 | if (value >= pdata->num_retune_mobile_cfgs) | |
764 | return -EINVAL; | |
765 | ||
766 | wm8904->retune_mobile_cfg = value; | |
767 | ||
768 | wm8904_set_retune_mobile(codec); | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
773 | static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
774 | struct snd_ctl_elem_value *ucontrol) | |
775 | { | |
776 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 777 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
778 | |
779 | ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
784 | static int deemph_settings[] = { 0, 32000, 44100, 48000 }; | |
785 | ||
786 | static int wm8904_set_deemph(struct snd_soc_codec *codec) | |
787 | { | |
b2c812e2 | 788 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
789 | int val, i, best; |
790 | ||
791 | /* If we're using deemphasis select the nearest available sample | |
792 | * rate. | |
793 | */ | |
794 | if (wm8904->deemph) { | |
795 | best = 1; | |
796 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
797 | if (abs(deemph_settings[i] - wm8904->fs) < | |
798 | abs(deemph_settings[best] - wm8904->fs)) | |
799 | best = i; | |
800 | } | |
801 | ||
802 | val = best << WM8904_DEEMPH_SHIFT; | |
803 | } else { | |
804 | val = 0; | |
805 | } | |
806 | ||
807 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); | |
808 | ||
809 | return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, | |
810 | WM8904_DEEMPH_MASK, val); | |
811 | } | |
812 | ||
813 | static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, | |
814 | struct snd_ctl_elem_value *ucontrol) | |
815 | { | |
816 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 817 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 | 818 | |
3f343f85 DA |
819 | ucontrol->value.enumerated.item[0] = wm8904->deemph; |
820 | return 0; | |
a91eb199 MB |
821 | } |
822 | ||
823 | static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, | |
824 | struct snd_ctl_elem_value *ucontrol) | |
825 | { | |
826 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 827 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
828 | int deemph = ucontrol->value.enumerated.item[0]; |
829 | ||
830 | if (deemph > 1) | |
831 | return -EINVAL; | |
832 | ||
833 | wm8904->deemph = deemph; | |
834 | ||
835 | return wm8904_set_deemph(codec); | |
836 | } | |
837 | ||
838 | static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); | |
839 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
840 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); | |
841 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); | |
842 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
843 | ||
844 | static const char *input_mode_text[] = { | |
845 | "Single-Ended", "Differential Line", "Differential Mic" | |
846 | }; | |
847 | ||
848 | static const struct soc_enum lin_mode = | |
849 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); | |
850 | ||
851 | static const struct soc_enum rin_mode = | |
852 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); | |
853 | ||
854 | static const char *hpf_mode_text[] = { | |
855 | "Hi-fi", "Voice 1", "Voice 2", "Voice 3" | |
856 | }; | |
857 | ||
858 | static const struct soc_enum hpf_mode = | |
859 | SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text); | |
860 | ||
861 | static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { | |
862 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, | |
863 | WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), | |
864 | ||
865 | SOC_ENUM("Left Caputure Mode", lin_mode), | |
866 | SOC_ENUM("Right Capture Mode", rin_mode), | |
867 | ||
868 | /* No TLV since it depends on mode */ | |
869 | SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, | |
870 | WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), | |
871 | SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, | |
872 | WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0), | |
873 | ||
874 | SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), | |
875 | SOC_ENUM("High Pass Filter Mode", hpf_mode), | |
876 | ||
877 | SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0), | |
878 | }; | |
879 | ||
880 | static const char *drc_path_text[] = { | |
881 | "ADC", "DAC" | |
882 | }; | |
883 | ||
884 | static const struct soc_enum drc_path = | |
885 | SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text); | |
886 | ||
887 | static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { | |
888 | SOC_SINGLE_TLV("Digital Playback Boost Volume", | |
889 | WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), | |
890 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, | |
891 | WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), | |
892 | ||
893 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, | |
894 | WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), | |
895 | SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
896 | WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), | |
897 | SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
898 | WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), | |
899 | ||
900 | SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, | |
901 | WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), | |
902 | SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
903 | WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), | |
904 | SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
905 | WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), | |
906 | ||
907 | SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), | |
908 | SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), | |
909 | SOC_ENUM("DRC Path", drc_path), | |
910 | SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), | |
911 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, | |
912 | wm8904_get_deemph, wm8904_put_deemph), | |
913 | }; | |
914 | ||
915 | static const struct snd_kcontrol_new wm8904_snd_controls[] = { | |
916 | SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, | |
917 | sidetone_tlv), | |
918 | }; | |
919 | ||
920 | static const struct snd_kcontrol_new wm8904_eq_controls[] = { | |
921 | SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), | |
922 | SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), | |
923 | SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), | |
924 | SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), | |
925 | SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), | |
926 | }; | |
927 | ||
928 | static int cp_event(struct snd_soc_dapm_widget *w, | |
929 | struct snd_kcontrol *kcontrol, int event) | |
930 | { | |
931 | BUG_ON(event != SND_SOC_DAPM_POST_PMU); | |
932 | ||
933 | /* Maximum startup time */ | |
934 | udelay(500); | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | static int sysclk_event(struct snd_soc_dapm_widget *w, | |
940 | struct snd_kcontrol *kcontrol, int event) | |
941 | { | |
942 | struct snd_soc_codec *codec = w->codec; | |
b2c812e2 | 943 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
944 | |
945 | switch (event) { | |
946 | case SND_SOC_DAPM_PRE_PMU: | |
947 | /* If we're using the FLL then we only start it when | |
948 | * required; we assume that the configuration has been | |
949 | * done previously and all we need to do is kick it | |
950 | * off. | |
951 | */ | |
952 | switch (wm8904->sysclk_src) { | |
953 | case WM8904_CLK_FLL: | |
954 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
955 | WM8904_FLL_OSC_ENA, | |
956 | WM8904_FLL_OSC_ENA); | |
957 | ||
958 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
959 | WM8904_FLL_ENA, | |
960 | WM8904_FLL_ENA); | |
961 | break; | |
962 | ||
963 | default: | |
964 | break; | |
965 | } | |
966 | break; | |
967 | ||
968 | case SND_SOC_DAPM_POST_PMD: | |
969 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
970 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
971 | break; | |
972 | } | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
977 | static int out_pga_event(struct snd_soc_dapm_widget *w, | |
978 | struct snd_kcontrol *kcontrol, int event) | |
979 | { | |
980 | struct snd_soc_codec *codec = w->codec; | |
b2c812e2 | 981 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
982 | int reg, val; |
983 | int dcs_mask; | |
984 | int dcs_l, dcs_r; | |
985 | int dcs_l_reg, dcs_r_reg; | |
986 | int timeout; | |
e4bc6696 | 987 | int pwr_reg; |
a91eb199 MB |
988 | |
989 | /* This code is shared between HP and LINEOUT; we do all our | |
990 | * power management in stereo pairs to avoid latency issues so | |
991 | * we reuse shift to identify which rather than strcmp() the | |
992 | * name. */ | |
993 | reg = w->shift; | |
994 | ||
995 | switch (reg) { | |
996 | case WM8904_ANALOGUE_HP_0: | |
e4bc6696 | 997 | pwr_reg = WM8904_POWER_MANAGEMENT_2; |
a91eb199 MB |
998 | dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; |
999 | dcs_r_reg = WM8904_DC_SERVO_8; | |
1000 | dcs_l_reg = WM8904_DC_SERVO_9; | |
1001 | dcs_l = 0; | |
1002 | dcs_r = 1; | |
1003 | break; | |
1004 | case WM8904_ANALOGUE_LINEOUT_0: | |
e4bc6696 | 1005 | pwr_reg = WM8904_POWER_MANAGEMENT_3; |
a91eb199 MB |
1006 | dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; |
1007 | dcs_r_reg = WM8904_DC_SERVO_6; | |
1008 | dcs_l_reg = WM8904_DC_SERVO_7; | |
1009 | dcs_l = 2; | |
1010 | dcs_r = 3; | |
1011 | break; | |
1012 | default: | |
1013 | BUG(); | |
1014 | return -EINVAL; | |
1015 | } | |
1016 | ||
1017 | switch (event) { | |
e4bc6696 MB |
1018 | case SND_SOC_DAPM_PRE_PMU: |
1019 | /* Power on the PGAs */ | |
1020 | snd_soc_update_bits(codec, pwr_reg, | |
1021 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, | |
1022 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); | |
1023 | ||
a91eb199 MB |
1024 | /* Power on the amplifier */ |
1025 | snd_soc_update_bits(codec, reg, | |
1026 | WM8904_HPL_ENA | WM8904_HPR_ENA, | |
1027 | WM8904_HPL_ENA | WM8904_HPR_ENA); | |
1028 | ||
e4bc6696 | 1029 | |
a91eb199 MB |
1030 | /* Enable the first stage */ |
1031 | snd_soc_update_bits(codec, reg, | |
1032 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, | |
1033 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); | |
1034 | ||
1035 | /* Power up the DC servo */ | |
1036 | snd_soc_update_bits(codec, WM8904_DC_SERVO_0, | |
1037 | dcs_mask, dcs_mask); | |
1038 | ||
1039 | /* Either calibrate the DC servo or restore cached state | |
1040 | * if we have that. | |
1041 | */ | |
1042 | if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { | |
1043 | dev_dbg(codec->dev, "Restoring DC servo state\n"); | |
1044 | ||
1045 | snd_soc_write(codec, dcs_l_reg, | |
1046 | wm8904->dcs_state[dcs_l]); | |
1047 | snd_soc_write(codec, dcs_r_reg, | |
1048 | wm8904->dcs_state[dcs_r]); | |
1049 | ||
1050 | snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask); | |
1051 | ||
1052 | timeout = 20; | |
1053 | } else { | |
1054 | dev_dbg(codec->dev, "Calibrating DC servo\n"); | |
1055 | ||
1056 | snd_soc_write(codec, WM8904_DC_SERVO_1, | |
1057 | dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); | |
1058 | ||
1059 | timeout = 500; | |
1060 | } | |
1061 | ||
1062 | /* Wait for DC servo to complete */ | |
1063 | dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; | |
1064 | do { | |
1065 | val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0); | |
1066 | if ((val & dcs_mask) == dcs_mask) | |
1067 | break; | |
1068 | ||
1069 | msleep(1); | |
1070 | } while (--timeout); | |
1071 | ||
1072 | if ((val & dcs_mask) != dcs_mask) | |
1073 | dev_warn(codec->dev, "DC servo timed out\n"); | |
1074 | else | |
1075 | dev_dbg(codec->dev, "DC servo ready\n"); | |
1076 | ||
1077 | /* Enable the output stage */ | |
1078 | snd_soc_update_bits(codec, reg, | |
1079 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, | |
1080 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); | |
e4bc6696 | 1081 | break; |
a91eb199 | 1082 | |
e4bc6696 | 1083 | case SND_SOC_DAPM_POST_PMU: |
a91eb199 MB |
1084 | /* Unshort the output itself */ |
1085 | snd_soc_update_bits(codec, reg, | |
1086 | WM8904_HPL_RMV_SHORT | | |
1087 | WM8904_HPR_RMV_SHORT, | |
1088 | WM8904_HPL_RMV_SHORT | | |
1089 | WM8904_HPR_RMV_SHORT); | |
1090 | ||
1091 | break; | |
1092 | ||
1093 | case SND_SOC_DAPM_PRE_PMD: | |
1094 | /* Short the output */ | |
1095 | snd_soc_update_bits(codec, reg, | |
1096 | WM8904_HPL_RMV_SHORT | | |
1097 | WM8904_HPR_RMV_SHORT, 0); | |
e4bc6696 | 1098 | break; |
a91eb199 | 1099 | |
e4bc6696 | 1100 | case SND_SOC_DAPM_POST_PMD: |
a91eb199 MB |
1101 | /* Cache the DC servo configuration; this will be |
1102 | * invalidated if we change the configuration. */ | |
1103 | wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg); | |
1104 | wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg); | |
1105 | ||
1106 | snd_soc_update_bits(codec, WM8904_DC_SERVO_0, | |
1107 | dcs_mask, 0); | |
1108 | ||
1109 | /* Disable the amplifier input and output stages */ | |
1110 | snd_soc_update_bits(codec, reg, | |
1111 | WM8904_HPL_ENA | WM8904_HPR_ENA | | |
1112 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | | |
1113 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, | |
1114 | 0); | |
e4bc6696 MB |
1115 | |
1116 | /* PGAs too */ | |
1117 | snd_soc_update_bits(codec, pwr_reg, | |
1118 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, | |
1119 | 0); | |
a91eb199 MB |
1120 | break; |
1121 | } | |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | static const char *lin_text[] = { | |
1127 | "IN1L", "IN2L", "IN3L" | |
1128 | }; | |
1129 | ||
1130 | static const struct soc_enum lin_enum = | |
1131 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text); | |
1132 | ||
1133 | static const struct snd_kcontrol_new lin_mux = | |
1134 | SOC_DAPM_ENUM("Left Capture Mux", lin_enum); | |
1135 | ||
1136 | static const struct soc_enum lin_inv_enum = | |
1137 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text); | |
1138 | ||
1139 | static const struct snd_kcontrol_new lin_inv_mux = | |
1140 | SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); | |
1141 | ||
1142 | static const char *rin_text[] = { | |
1143 | "IN1R", "IN2R", "IN3R" | |
1144 | }; | |
1145 | ||
1146 | static const struct soc_enum rin_enum = | |
1147 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text); | |
1148 | ||
1149 | static const struct snd_kcontrol_new rin_mux = | |
1150 | SOC_DAPM_ENUM("Right Capture Mux", rin_enum); | |
1151 | ||
1152 | static const struct soc_enum rin_inv_enum = | |
1153 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text); | |
1154 | ||
1155 | static const struct snd_kcontrol_new rin_inv_mux = | |
1156 | SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); | |
1157 | ||
1158 | static const char *aif_text[] = { | |
1159 | "Left", "Right" | |
1160 | }; | |
1161 | ||
1162 | static const struct soc_enum aifoutl_enum = | |
1163 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text); | |
1164 | ||
1165 | static const struct snd_kcontrol_new aifoutl_mux = | |
1166 | SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); | |
1167 | ||
1168 | static const struct soc_enum aifoutr_enum = | |
1169 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text); | |
1170 | ||
1171 | static const struct snd_kcontrol_new aifoutr_mux = | |
1172 | SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); | |
1173 | ||
1174 | static const struct soc_enum aifinl_enum = | |
1175 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text); | |
1176 | ||
1177 | static const struct snd_kcontrol_new aifinl_mux = | |
1178 | SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); | |
1179 | ||
1180 | static const struct soc_enum aifinr_enum = | |
1181 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text); | |
1182 | ||
1183 | static const struct snd_kcontrol_new aifinr_mux = | |
1184 | SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); | |
1185 | ||
1186 | static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { | |
1187 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, | |
1188 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
1189 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), | |
1190 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), | |
1191 | }; | |
1192 | ||
1193 | static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { | |
1194 | SND_SOC_DAPM_INPUT("IN1L"), | |
1195 | SND_SOC_DAPM_INPUT("IN1R"), | |
1196 | SND_SOC_DAPM_INPUT("IN2L"), | |
1197 | SND_SOC_DAPM_INPUT("IN2R"), | |
1198 | SND_SOC_DAPM_INPUT("IN3L"), | |
1199 | SND_SOC_DAPM_INPUT("IN3R"), | |
1200 | ||
1201 | SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0), | |
1202 | ||
1203 | SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), | |
1204 | SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
1205 | &lin_inv_mux), | |
1206 | SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), | |
1207 | SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
1208 | &rin_inv_mux), | |
1209 | ||
1210 | SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, | |
1211 | NULL, 0), | |
1212 | SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, | |
1213 | NULL, 0), | |
1214 | ||
1215 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), | |
1216 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), | |
1217 | ||
1218 | SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), | |
1219 | SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), | |
1220 | ||
1221 | SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), | |
1222 | SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), | |
1223 | }; | |
1224 | ||
1225 | static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { | |
1226 | SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), | |
1227 | SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), | |
1228 | ||
1229 | SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), | |
1230 | SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), | |
1231 | ||
1232 | SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), | |
1233 | SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), | |
1234 | ||
1235 | SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, | |
1236 | SND_SOC_DAPM_POST_PMU), | |
1237 | ||
e4bc6696 MB |
1238 | SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
1239 | SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 | 1240 | |
e4bc6696 MB |
1241 | SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
1242 | SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 MB |
1243 | |
1244 | SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, | |
1245 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
1246 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1247 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
1248 | SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, |
1249 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
1250 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1251 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
1252 | |
1253 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
1254 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
1255 | SND_SOC_DAPM_OUTPUT("LINEOUTL"), | |
1256 | SND_SOC_DAPM_OUTPUT("LINEOUTR"), | |
1257 | }; | |
1258 | ||
1259 | static const char *out_mux_text[] = { | |
1260 | "DAC", "Bypass" | |
1261 | }; | |
1262 | ||
1263 | static const struct soc_enum hpl_enum = | |
1264 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text); | |
1265 | ||
1266 | static const struct snd_kcontrol_new hpl_mux = | |
1267 | SOC_DAPM_ENUM("HPL Mux", hpl_enum); | |
1268 | ||
1269 | static const struct soc_enum hpr_enum = | |
1270 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text); | |
1271 | ||
1272 | static const struct snd_kcontrol_new hpr_mux = | |
1273 | SOC_DAPM_ENUM("HPR Mux", hpr_enum); | |
1274 | ||
1275 | static const struct soc_enum linel_enum = | |
1276 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text); | |
1277 | ||
1278 | static const struct snd_kcontrol_new linel_mux = | |
1279 | SOC_DAPM_ENUM("LINEL Mux", linel_enum); | |
1280 | ||
1281 | static const struct soc_enum liner_enum = | |
1282 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text); | |
1283 | ||
1284 | static const struct snd_kcontrol_new liner_mux = | |
1285 | SOC_DAPM_ENUM("LINEL Mux", liner_enum); | |
1286 | ||
1287 | static const char *sidetone_text[] = { | |
1288 | "None", "Left", "Right" | |
1289 | }; | |
1290 | ||
1291 | static const struct soc_enum dacl_sidetone_enum = | |
1292 | SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text); | |
1293 | ||
1294 | static const struct snd_kcontrol_new dacl_sidetone_mux = | |
1295 | SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); | |
1296 | ||
1297 | static const struct soc_enum dacr_sidetone_enum = | |
1298 | SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text); | |
1299 | ||
1300 | static const struct snd_kcontrol_new dacr_sidetone_mux = | |
1301 | SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); | |
1302 | ||
1303 | static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { | |
1304 | SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), | |
1305 | SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1306 | SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1307 | ||
1308 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), | |
1309 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), | |
1310 | ||
1311 | SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), | |
1312 | SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), | |
1313 | SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), | |
1314 | SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), | |
1315 | }; | |
1316 | ||
1317 | static const struct snd_soc_dapm_route core_intercon[] = { | |
1318 | { "CLK_DSP", NULL, "SYSCLK" }, | |
1319 | { "TOCLK", NULL, "SYSCLK" }, | |
1320 | }; | |
1321 | ||
1322 | static const struct snd_soc_dapm_route adc_intercon[] = { | |
1323 | { "Left Capture Mux", "IN1L", "IN1L" }, | |
1324 | { "Left Capture Mux", "IN2L", "IN2L" }, | |
1325 | { "Left Capture Mux", "IN3L", "IN3L" }, | |
1326 | ||
1327 | { "Left Capture Inverting Mux", "IN1L", "IN1L" }, | |
1328 | { "Left Capture Inverting Mux", "IN2L", "IN2L" }, | |
1329 | { "Left Capture Inverting Mux", "IN3L", "IN3L" }, | |
1330 | ||
1331 | { "Right Capture Mux", "IN1R", "IN1R" }, | |
1332 | { "Right Capture Mux", "IN2R", "IN2R" }, | |
1333 | { "Right Capture Mux", "IN3R", "IN3R" }, | |
1334 | ||
1335 | { "Right Capture Inverting Mux", "IN1R", "IN1R" }, | |
1336 | { "Right Capture Inverting Mux", "IN2R", "IN2R" }, | |
1337 | { "Right Capture Inverting Mux", "IN3R", "IN3R" }, | |
1338 | ||
1339 | { "Left Capture PGA", NULL, "Left Capture Mux" }, | |
1340 | { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, | |
1341 | ||
1342 | { "Right Capture PGA", NULL, "Right Capture Mux" }, | |
1343 | { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, | |
1344 | ||
1345 | { "AIFOUTL", "Left", "ADCL" }, | |
1346 | { "AIFOUTL", "Right", "ADCR" }, | |
1347 | { "AIFOUTR", "Left", "ADCL" }, | |
1348 | { "AIFOUTR", "Right", "ADCR" }, | |
1349 | ||
1350 | { "ADCL", NULL, "CLK_DSP" }, | |
1351 | { "ADCL", NULL, "Left Capture PGA" }, | |
1352 | ||
1353 | { "ADCR", NULL, "CLK_DSP" }, | |
1354 | { "ADCR", NULL, "Right Capture PGA" }, | |
1355 | }; | |
1356 | ||
1357 | static const struct snd_soc_dapm_route dac_intercon[] = { | |
1358 | { "DACL", "Right", "AIFINR" }, | |
1359 | { "DACL", "Left", "AIFINL" }, | |
1360 | { "DACL", NULL, "CLK_DSP" }, | |
1361 | ||
1362 | { "DACR", "Right", "AIFINR" }, | |
1363 | { "DACR", "Left", "AIFINL" }, | |
1364 | { "DACR", NULL, "CLK_DSP" }, | |
1365 | ||
1366 | { "Charge pump", NULL, "SYSCLK" }, | |
1367 | ||
1368 | { "Headphone Output", NULL, "HPL PGA" }, | |
1369 | { "Headphone Output", NULL, "HPR PGA" }, | |
1370 | { "Headphone Output", NULL, "Charge pump" }, | |
1371 | { "Headphone Output", NULL, "TOCLK" }, | |
1372 | ||
1373 | { "Line Output", NULL, "LINEL PGA" }, | |
1374 | { "Line Output", NULL, "LINER PGA" }, | |
1375 | { "Line Output", NULL, "Charge pump" }, | |
1376 | { "Line Output", NULL, "TOCLK" }, | |
1377 | ||
1378 | { "HPOUTL", NULL, "Headphone Output" }, | |
1379 | { "HPOUTR", NULL, "Headphone Output" }, | |
1380 | ||
1381 | { "LINEOUTL", NULL, "Line Output" }, | |
1382 | { "LINEOUTR", NULL, "Line Output" }, | |
1383 | }; | |
1384 | ||
1385 | static const struct snd_soc_dapm_route wm8904_intercon[] = { | |
1386 | { "Left Sidetone", "Left", "ADCL" }, | |
1387 | { "Left Sidetone", "Right", "ADCR" }, | |
1388 | { "DACL", NULL, "Left Sidetone" }, | |
1389 | ||
1390 | { "Right Sidetone", "Left", "ADCL" }, | |
1391 | { "Right Sidetone", "Right", "ADCR" }, | |
1392 | { "DACR", NULL, "Right Sidetone" }, | |
1393 | ||
1394 | { "Left Bypass", NULL, "Class G" }, | |
1395 | { "Left Bypass", NULL, "Left Capture PGA" }, | |
1396 | ||
1397 | { "Right Bypass", NULL, "Class G" }, | |
1398 | { "Right Bypass", NULL, "Right Capture PGA" }, | |
1399 | ||
1400 | { "HPL Mux", "DAC", "DACL" }, | |
1401 | { "HPL Mux", "Bypass", "Left Bypass" }, | |
1402 | ||
1403 | { "HPR Mux", "DAC", "DACR" }, | |
1404 | { "HPR Mux", "Bypass", "Right Bypass" }, | |
1405 | ||
1406 | { "LINEL Mux", "DAC", "DACL" }, | |
1407 | { "LINEL Mux", "Bypass", "Left Bypass" }, | |
1408 | ||
1409 | { "LINER Mux", "DAC", "DACR" }, | |
1410 | { "LINER Mux", "Bypass", "Right Bypass" }, | |
1411 | ||
1412 | { "HPL PGA", NULL, "HPL Mux" }, | |
1413 | { "HPR PGA", NULL, "HPR Mux" }, | |
1414 | ||
1415 | { "LINEL PGA", NULL, "LINEL Mux" }, | |
1416 | { "LINER PGA", NULL, "LINER Mux" }, | |
1417 | }; | |
1418 | ||
8c126474 MB |
1419 | static const struct snd_soc_dapm_route wm8912_intercon[] = { |
1420 | { "HPL PGA", NULL, "DACL" }, | |
1421 | { "HPR PGA", NULL, "DACR" }, | |
1422 | ||
1423 | { "LINEL PGA", NULL, "DACL" }, | |
1424 | { "LINER PGA", NULL, "DACR" }, | |
1425 | }; | |
1426 | ||
a91eb199 MB |
1427 | static int wm8904_add_widgets(struct snd_soc_codec *codec) |
1428 | { | |
b2c812e2 | 1429 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1430 | |
1431 | snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets, | |
1432 | ARRAY_SIZE(wm8904_core_dapm_widgets)); | |
a91eb199 MB |
1433 | snd_soc_dapm_add_routes(codec, core_intercon, |
1434 | ARRAY_SIZE(core_intercon)); | |
8c126474 MB |
1435 | |
1436 | switch (wm8904->devtype) { | |
1437 | case WM8904: | |
1438 | snd_soc_add_controls(codec, wm8904_adc_snd_controls, | |
1439 | ARRAY_SIZE(wm8904_adc_snd_controls)); | |
1440 | snd_soc_add_controls(codec, wm8904_dac_snd_controls, | |
1441 | ARRAY_SIZE(wm8904_dac_snd_controls)); | |
1442 | snd_soc_add_controls(codec, wm8904_snd_controls, | |
1443 | ARRAY_SIZE(wm8904_snd_controls)); | |
1444 | ||
1445 | snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets, | |
1446 | ARRAY_SIZE(wm8904_adc_dapm_widgets)); | |
1447 | snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, | |
1448 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); | |
1449 | snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets, | |
1450 | ARRAY_SIZE(wm8904_dapm_widgets)); | |
1451 | ||
1452 | snd_soc_dapm_add_routes(codec, core_intercon, | |
1453 | ARRAY_SIZE(core_intercon)); | |
1454 | snd_soc_dapm_add_routes(codec, adc_intercon, | |
1455 | ARRAY_SIZE(adc_intercon)); | |
1456 | snd_soc_dapm_add_routes(codec, dac_intercon, | |
1457 | ARRAY_SIZE(dac_intercon)); | |
1458 | snd_soc_dapm_add_routes(codec, wm8904_intercon, | |
1459 | ARRAY_SIZE(wm8904_intercon)); | |
1460 | break; | |
1461 | ||
1462 | case WM8912: | |
1463 | snd_soc_add_controls(codec, wm8904_dac_snd_controls, | |
1464 | ARRAY_SIZE(wm8904_dac_snd_controls)); | |
1465 | ||
1466 | snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, | |
1467 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); | |
1468 | ||
1469 | snd_soc_dapm_add_routes(codec, dac_intercon, | |
1470 | ARRAY_SIZE(dac_intercon)); | |
1471 | snd_soc_dapm_add_routes(codec, wm8912_intercon, | |
1472 | ARRAY_SIZE(wm8912_intercon)); | |
1473 | break; | |
1474 | } | |
a91eb199 MB |
1475 | |
1476 | snd_soc_dapm_new_widgets(codec); | |
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | static struct { | |
1481 | int ratio; | |
1482 | unsigned int clk_sys_rate; | |
1483 | } clk_sys_rates[] = { | |
1484 | { 64, 0 }, | |
1485 | { 128, 1 }, | |
1486 | { 192, 2 }, | |
1487 | { 256, 3 }, | |
1488 | { 384, 4 }, | |
1489 | { 512, 5 }, | |
1490 | { 786, 6 }, | |
1491 | { 1024, 7 }, | |
1492 | { 1408, 8 }, | |
1493 | { 1536, 9 }, | |
1494 | }; | |
1495 | ||
1496 | static struct { | |
1497 | int rate; | |
1498 | int sample_rate; | |
1499 | } sample_rates[] = { | |
1500 | { 8000, 0 }, | |
1501 | { 11025, 1 }, | |
1502 | { 12000, 1 }, | |
1503 | { 16000, 2 }, | |
1504 | { 22050, 3 }, | |
1505 | { 24000, 3 }, | |
1506 | { 32000, 4 }, | |
1507 | { 44100, 5 }, | |
1508 | { 48000, 5 }, | |
1509 | }; | |
1510 | ||
1511 | static struct { | |
1512 | int div; /* *10 due to .5s */ | |
1513 | int bclk_div; | |
1514 | } bclk_divs[] = { | |
1515 | { 10, 0 }, | |
1516 | { 15, 1 }, | |
1517 | { 20, 2 }, | |
1518 | { 30, 3 }, | |
1519 | { 40, 4 }, | |
1520 | { 50, 5 }, | |
1521 | { 55, 6 }, | |
1522 | { 60, 7 }, | |
1523 | { 80, 8 }, | |
1524 | { 100, 9 }, | |
1525 | { 110, 10 }, | |
1526 | { 120, 11 }, | |
1527 | { 160, 12 }, | |
1528 | { 200, 13 }, | |
1529 | { 220, 14 }, | |
1530 | { 240, 16 }, | |
1531 | { 200, 17 }, | |
1532 | { 320, 18 }, | |
1533 | { 440, 19 }, | |
1534 | { 480, 20 }, | |
1535 | }; | |
1536 | ||
1537 | ||
1538 | static int wm8904_hw_params(struct snd_pcm_substream *substream, | |
1539 | struct snd_pcm_hw_params *params, | |
1540 | struct snd_soc_dai *dai) | |
1541 | { | |
1542 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1543 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1544 | int ret, i, best, best_val, cur_val; |
1545 | unsigned int aif1 = 0; | |
1546 | unsigned int aif2 = 0; | |
1547 | unsigned int aif3 = 0; | |
1548 | unsigned int clock1 = 0; | |
1549 | unsigned int dac_digital1 = 0; | |
1550 | ||
1551 | /* What BCLK do we need? */ | |
1552 | wm8904->fs = params_rate(params); | |
1553 | if (wm8904->tdm_slots) { | |
1554 | dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", | |
1555 | wm8904->tdm_slots, wm8904->tdm_width); | |
1556 | wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, | |
1557 | wm8904->tdm_width, 2, | |
1558 | wm8904->tdm_slots); | |
1559 | } else { | |
1560 | wm8904->bclk = snd_soc_params_to_bclk(params); | |
1561 | } | |
1562 | ||
56927eb0 MB |
1563 | switch (params_format(params)) { |
1564 | case SNDRV_PCM_FORMAT_S16_LE: | |
1565 | break; | |
1566 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1567 | aif1 |= 0x40; | |
1568 | break; | |
1569 | case SNDRV_PCM_FORMAT_S24_LE: | |
1570 | aif1 |= 0x80; | |
1571 | break; | |
1572 | case SNDRV_PCM_FORMAT_S32_LE: | |
1573 | aif1 |= 0xc0; | |
1574 | break; | |
1575 | default: | |
1576 | return -EINVAL; | |
1577 | } | |
1578 | ||
1579 | ||
a91eb199 MB |
1580 | dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); |
1581 | ||
1582 | ret = wm8904_configure_clocking(codec); | |
1583 | if (ret != 0) | |
1584 | return ret; | |
1585 | ||
1586 | /* Select nearest CLK_SYS_RATE */ | |
1587 | best = 0; | |
1588 | best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) | |
1589 | - wm8904->fs); | |
1590 | for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { | |
1591 | cur_val = abs((wm8904->sysclk_rate / | |
1592 | clk_sys_rates[i].ratio) - wm8904->fs);; | |
1593 | if (cur_val < best_val) { | |
1594 | best = i; | |
1595 | best_val = cur_val; | |
1596 | } | |
1597 | } | |
1598 | dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", | |
1599 | clk_sys_rates[best].ratio); | |
1600 | clock1 |= (clk_sys_rates[best].clk_sys_rate | |
1601 | << WM8904_CLK_SYS_RATE_SHIFT); | |
1602 | ||
1603 | /* SAMPLE_RATE */ | |
1604 | best = 0; | |
1605 | best_val = abs(wm8904->fs - sample_rates[0].rate); | |
1606 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1607 | /* Closest match */ | |
1608 | cur_val = abs(wm8904->fs - sample_rates[i].rate); | |
1609 | if (cur_val < best_val) { | |
1610 | best = i; | |
1611 | best_val = cur_val; | |
1612 | } | |
1613 | } | |
1614 | dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", | |
1615 | sample_rates[best].rate); | |
1616 | clock1 |= (sample_rates[best].sample_rate | |
1617 | << WM8904_SAMPLE_RATE_SHIFT); | |
1618 | ||
1619 | /* Enable sloping stopband filter for low sample rates */ | |
1620 | if (wm8904->fs <= 24000) | |
1621 | dac_digital1 |= WM8904_DAC_SB_FILT; | |
1622 | ||
1623 | /* BCLK_DIV */ | |
1624 | best = 0; | |
1625 | best_val = INT_MAX; | |
1626 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1627 | cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) | |
1628 | - wm8904->bclk; | |
1629 | if (cur_val < 0) /* Table is sorted */ | |
1630 | break; | |
1631 | if (cur_val < best_val) { | |
1632 | best = i; | |
1633 | best_val = cur_val; | |
1634 | } | |
1635 | } | |
1636 | wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; | |
1637 | dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", | |
1638 | bclk_divs[best].div, wm8904->bclk); | |
1639 | aif2 |= bclk_divs[best].bclk_div; | |
1640 | ||
1641 | /* LRCLK is a simple fraction of BCLK */ | |
1642 | dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); | |
1643 | aif3 |= wm8904->bclk / wm8904->fs; | |
1644 | ||
1645 | /* Apply the settings */ | |
1646 | snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, | |
1647 | WM8904_DAC_SB_FILT, dac_digital1); | |
1648 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1649 | WM8904_AIF_WL_MASK, aif1); | |
1650 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2, | |
1651 | WM8904_BCLK_DIV_MASK, aif2); | |
1652 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, | |
1653 | WM8904_LRCLK_RATE_MASK, aif3); | |
1654 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1, | |
1655 | WM8904_SAMPLE_RATE_MASK | | |
1656 | WM8904_CLK_SYS_RATE_MASK, clock1); | |
1657 | ||
1658 | /* Update filters for the new settings */ | |
1659 | wm8904_set_retune_mobile(codec); | |
1660 | wm8904_set_deemph(codec); | |
1661 | ||
1662 | return 0; | |
1663 | } | |
1664 | ||
1665 | ||
1666 | static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, | |
1667 | unsigned int freq, int dir) | |
1668 | { | |
1669 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1670 | struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1671 | |
1672 | switch (clk_id) { | |
1673 | case WM8904_CLK_MCLK: | |
1674 | priv->sysclk_src = clk_id; | |
1675 | priv->mclk_rate = freq; | |
1676 | break; | |
1677 | ||
1678 | case WM8904_CLK_FLL: | |
1679 | priv->sysclk_src = clk_id; | |
1680 | break; | |
1681 | ||
1682 | default: | |
1683 | return -EINVAL; | |
1684 | } | |
1685 | ||
1686 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
1687 | ||
1688 | wm8904_configure_clocking(codec); | |
1689 | ||
1690 | return 0; | |
1691 | } | |
1692 | ||
1693 | static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1694 | { | |
1695 | struct snd_soc_codec *codec = dai->codec; | |
1696 | unsigned int aif1 = 0; | |
1697 | unsigned int aif3 = 0; | |
1698 | ||
1699 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1700 | case SND_SOC_DAIFMT_CBS_CFS: | |
1701 | break; | |
1702 | case SND_SOC_DAIFMT_CBS_CFM: | |
1703 | aif3 |= WM8904_LRCLK_DIR; | |
1704 | break; | |
1705 | case SND_SOC_DAIFMT_CBM_CFS: | |
1706 | aif1 |= WM8904_BCLK_DIR; | |
1707 | break; | |
1708 | case SND_SOC_DAIFMT_CBM_CFM: | |
1709 | aif1 |= WM8904_BCLK_DIR; | |
1710 | aif3 |= WM8904_LRCLK_DIR; | |
1711 | break; | |
1712 | default: | |
1713 | return -EINVAL; | |
1714 | } | |
1715 | ||
1716 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1717 | case SND_SOC_DAIFMT_DSP_B: | |
1718 | aif1 |= WM8904_AIF_LRCLK_INV; | |
1719 | case SND_SOC_DAIFMT_DSP_A: | |
1720 | aif1 |= 0x3; | |
1721 | break; | |
1722 | case SND_SOC_DAIFMT_I2S: | |
1723 | aif1 |= 0x2; | |
1724 | break; | |
1725 | case SND_SOC_DAIFMT_RIGHT_J: | |
1726 | break; | |
1727 | case SND_SOC_DAIFMT_LEFT_J: | |
1728 | aif1 |= 0x1; | |
1729 | break; | |
1730 | default: | |
1731 | return -EINVAL; | |
1732 | } | |
1733 | ||
1734 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1735 | case SND_SOC_DAIFMT_DSP_A: | |
1736 | case SND_SOC_DAIFMT_DSP_B: | |
1737 | /* frame inversion not valid for DSP modes */ | |
1738 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1739 | case SND_SOC_DAIFMT_NB_NF: | |
1740 | break; | |
1741 | case SND_SOC_DAIFMT_IB_NF: | |
1742 | aif1 |= WM8904_AIF_BCLK_INV; | |
1743 | break; | |
1744 | default: | |
1745 | return -EINVAL; | |
1746 | } | |
1747 | break; | |
1748 | ||
1749 | case SND_SOC_DAIFMT_I2S: | |
1750 | case SND_SOC_DAIFMT_RIGHT_J: | |
1751 | case SND_SOC_DAIFMT_LEFT_J: | |
1752 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1753 | case SND_SOC_DAIFMT_NB_NF: | |
1754 | break; | |
1755 | case SND_SOC_DAIFMT_IB_IF: | |
1756 | aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; | |
1757 | break; | |
1758 | case SND_SOC_DAIFMT_IB_NF: | |
1759 | aif1 |= WM8904_AIF_BCLK_INV; | |
1760 | break; | |
1761 | case SND_SOC_DAIFMT_NB_IF: | |
1762 | aif1 |= WM8904_AIF_LRCLK_INV; | |
1763 | break; | |
1764 | default: | |
1765 | return -EINVAL; | |
1766 | } | |
1767 | break; | |
1768 | default: | |
1769 | return -EINVAL; | |
1770 | } | |
1771 | ||
1772 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1773 | WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | | |
1774 | WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); | |
1775 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, | |
1776 | WM8904_LRCLK_DIR, aif3); | |
1777 | ||
1778 | return 0; | |
1779 | } | |
1780 | ||
1781 | ||
1782 | static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, | |
1783 | unsigned int rx_mask, int slots, int slot_width) | |
1784 | { | |
1785 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1786 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1787 | int aif1 = 0; |
1788 | ||
1789 | /* Don't need to validate anything if we're turning off TDM */ | |
1790 | if (slots == 0) | |
1791 | goto out; | |
1792 | ||
1793 | /* Note that we allow configurations we can't handle ourselves - | |
1794 | * for example, we can generate clocks for slots 2 and up even if | |
1795 | * we can't use those slots ourselves. | |
1796 | */ | |
1797 | aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; | |
1798 | ||
1799 | switch (rx_mask) { | |
1800 | case 3: | |
1801 | break; | |
1802 | case 0xc: | |
1803 | aif1 |= WM8904_AIFADC_TDM_CHAN; | |
1804 | break; | |
1805 | default: | |
1806 | return -EINVAL; | |
1807 | } | |
1808 | ||
1809 | ||
1810 | switch (tx_mask) { | |
1811 | case 3: | |
1812 | break; | |
1813 | case 0xc: | |
1814 | aif1 |= WM8904_AIFDAC_TDM_CHAN; | |
1815 | break; | |
1816 | default: | |
1817 | return -EINVAL; | |
1818 | } | |
1819 | ||
1820 | out: | |
1821 | wm8904->tdm_width = slot_width; | |
1822 | wm8904->tdm_slots = slots / 2; | |
1823 | ||
1824 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1825 | WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | | |
1826 | WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); | |
1827 | ||
1828 | return 0; | |
1829 | } | |
1830 | ||
1831 | struct _fll_div { | |
1832 | u16 fll_fratio; | |
1833 | u16 fll_outdiv; | |
1834 | u16 fll_clk_ref_div; | |
1835 | u16 n; | |
1836 | u16 k; | |
1837 | }; | |
1838 | ||
1839 | /* The size in bits of the FLL divide multiplied by 10 | |
1840 | * to allow rounding later */ | |
1841 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1842 | ||
1843 | static struct { | |
1844 | unsigned int min; | |
1845 | unsigned int max; | |
1846 | u16 fll_fratio; | |
1847 | int ratio; | |
1848 | } fll_fratios[] = { | |
1849 | { 0, 64000, 4, 16 }, | |
1850 | { 64000, 128000, 3, 8 }, | |
1851 | { 128000, 256000, 2, 4 }, | |
1852 | { 256000, 1000000, 1, 2 }, | |
1853 | { 1000000, 13500000, 0, 1 }, | |
1854 | }; | |
1855 | ||
1856 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
1857 | unsigned int Fout) | |
1858 | { | |
1859 | u64 Kpart; | |
1860 | unsigned int K, Ndiv, Nmod, target; | |
1861 | unsigned int div; | |
1862 | int i; | |
1863 | ||
1864 | /* Fref must be <=13.5MHz */ | |
1865 | div = 1; | |
1866 | fll_div->fll_clk_ref_div = 0; | |
1867 | while ((Fref / div) > 13500000) { | |
1868 | div *= 2; | |
1869 | fll_div->fll_clk_ref_div++; | |
1870 | ||
1871 | if (div > 8) { | |
1872 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
1873 | Fref); | |
1874 | return -EINVAL; | |
1875 | } | |
1876 | } | |
1877 | ||
1878 | pr_debug("Fref=%u Fout=%u\n", Fref, Fout); | |
1879 | ||
1880 | /* Apply the division for our remaining calculations */ | |
1881 | Fref /= div; | |
1882 | ||
1883 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
1884 | div = 4; | |
1885 | while (Fout * div < 90000000) { | |
1886 | div++; | |
1887 | if (div > 64) { | |
1888 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
1889 | Fout); | |
1890 | return -EINVAL; | |
1891 | } | |
1892 | } | |
1893 | target = Fout * div; | |
1894 | fll_div->fll_outdiv = div - 1; | |
1895 | ||
1896 | pr_debug("Fvco=%dHz\n", target); | |
1897 | ||
1898 | /* Find an appropraite FLL_FRATIO and factor it out of the target */ | |
1899 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { | |
1900 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
1901 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
1902 | target /= fll_fratios[i].ratio; | |
1903 | break; | |
1904 | } | |
1905 | } | |
1906 | if (i == ARRAY_SIZE(fll_fratios)) { | |
1907 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
1908 | return -EINVAL; | |
1909 | } | |
1910 | ||
1911 | /* Now, calculate N.K */ | |
1912 | Ndiv = target / Fref; | |
1913 | ||
1914 | fll_div->n = Ndiv; | |
1915 | Nmod = target % Fref; | |
1916 | pr_debug("Nmod=%d\n", Nmod); | |
1917 | ||
1918 | /* Calculate fractional part - scale up so we can round. */ | |
1919 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1920 | ||
1921 | do_div(Kpart, Fref); | |
1922 | ||
1923 | K = Kpart & 0xFFFFFFFF; | |
1924 | ||
1925 | if ((K % 10) >= 5) | |
1926 | K += 5; | |
1927 | ||
1928 | /* Move down to proper range now rounding is done */ | |
1929 | fll_div->k = K / 10; | |
1930 | ||
1931 | pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", | |
1932 | fll_div->n, fll_div->k, | |
1933 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
1934 | fll_div->fll_clk_ref_div); | |
1935 | ||
1936 | return 0; | |
1937 | } | |
1938 | ||
1939 | static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, | |
1940 | unsigned int Fref, unsigned int Fout) | |
1941 | { | |
1942 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1943 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1944 | struct _fll_div fll_div; |
1945 | int ret, val; | |
1946 | int clock2, fll1; | |
1947 | ||
1948 | /* Any change? */ | |
1949 | if (source == wm8904->fll_src && Fref == wm8904->fll_fref && | |
1950 | Fout == wm8904->fll_fout) | |
1951 | return 0; | |
1952 | ||
18240b67 MB |
1953 | clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); |
1954 | ||
a91eb199 MB |
1955 | if (Fout == 0) { |
1956 | dev_dbg(codec->dev, "FLL disabled\n"); | |
1957 | ||
1958 | wm8904->fll_fref = 0; | |
1959 | wm8904->fll_fout = 0; | |
1960 | ||
1961 | /* Gate SYSCLK to avoid glitches */ | |
1962 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
1963 | WM8904_CLK_SYS_ENA, 0); | |
1964 | ||
1965 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
1966 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
1967 | ||
1968 | goto out; | |
1969 | } | |
1970 | ||
1971 | /* Validate the FLL ID */ | |
1972 | switch (source) { | |
1973 | case WM8904_FLL_MCLK: | |
1974 | case WM8904_FLL_LRCLK: | |
1975 | case WM8904_FLL_BCLK: | |
1976 | ret = fll_factors(&fll_div, Fref, Fout); | |
1977 | if (ret != 0) | |
1978 | return ret; | |
1979 | break; | |
1980 | ||
1981 | case WM8904_FLL_FREE_RUNNING: | |
1982 | dev_dbg(codec->dev, "Using free running FLL\n"); | |
1983 | /* Force 12MHz and output/4 for now */ | |
1984 | Fout = 12000000; | |
1985 | Fref = 12000000; | |
1986 | ||
1987 | memset(&fll_div, 0, sizeof(fll_div)); | |
1988 | fll_div.fll_outdiv = 3; | |
1989 | break; | |
1990 | ||
1991 | default: | |
1992 | dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); | |
1993 | return -EINVAL; | |
1994 | } | |
1995 | ||
1996 | /* Save current state then disable the FLL and SYSCLK to avoid | |
1997 | * misclocking */ | |
a91eb199 MB |
1998 | fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1); |
1999 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
2000 | WM8904_CLK_SYS_ENA, 0); | |
2001 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2002 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
2003 | ||
2004 | /* Unlock forced oscilator control to switch it on/off */ | |
2005 | snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, | |
2006 | WM8904_USER_KEY, WM8904_USER_KEY); | |
2007 | ||
2008 | if (fll_id == WM8904_FLL_FREE_RUNNING) { | |
2009 | val = WM8904_FLL_FRC_NCO; | |
2010 | } else { | |
2011 | val = 0; | |
2012 | } | |
2013 | ||
2014 | snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, | |
2015 | val); | |
2016 | snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, | |
2017 | WM8904_USER_KEY, 0); | |
2018 | ||
2019 | switch (fll_id) { | |
2020 | case WM8904_FLL_MCLK: | |
2021 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2022 | WM8904_FLL_CLK_REF_SRC_MASK, 0); | |
2023 | break; | |
2024 | ||
2025 | case WM8904_FLL_LRCLK: | |
2026 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2027 | WM8904_FLL_CLK_REF_SRC_MASK, 1); | |
2028 | break; | |
2029 | ||
2030 | case WM8904_FLL_BCLK: | |
2031 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2032 | WM8904_FLL_CLK_REF_SRC_MASK, 2); | |
2033 | break; | |
2034 | } | |
2035 | ||
2036 | if (fll_div.k) | |
2037 | val = WM8904_FLL_FRACN_ENA; | |
2038 | else | |
2039 | val = 0; | |
2040 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2041 | WM8904_FLL_FRACN_ENA, val); | |
2042 | ||
2043 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2, | |
2044 | WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, | |
2045 | (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | | |
2046 | (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); | |
2047 | ||
2048 | snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k); | |
2049 | ||
2050 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, | |
2051 | fll_div.n << WM8904_FLL_N_SHIFT); | |
2052 | ||
2053 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2054 | WM8904_FLL_CLK_REF_DIV_MASK, | |
2055 | fll_div.fll_clk_ref_div | |
2056 | << WM8904_FLL_CLK_REF_DIV_SHIFT); | |
2057 | ||
2058 | dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); | |
2059 | ||
2060 | wm8904->fll_fref = Fref; | |
2061 | wm8904->fll_fout = Fout; | |
2062 | wm8904->fll_src = source; | |
2063 | ||
2064 | /* Enable the FLL if it was previously active */ | |
2065 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2066 | WM8904_FLL_OSC_ENA, fll1); | |
2067 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2068 | WM8904_FLL_ENA, fll1); | |
2069 | ||
2070 | out: | |
2071 | /* Reenable SYSCLK if it was previously active */ | |
2072 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
2073 | WM8904_CLK_SYS_ENA, clock2); | |
2074 | ||
2075 | return 0; | |
2076 | } | |
2077 | ||
2078 | static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
2079 | { | |
2080 | struct snd_soc_codec *codec = codec_dai->codec; | |
2081 | int val; | |
2082 | ||
2083 | if (mute) | |
2084 | val = WM8904_DAC_MUTE; | |
2085 | else | |
2086 | val = 0; | |
2087 | ||
2088 | snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); | |
2089 | ||
2090 | return 0; | |
2091 | } | |
2092 | ||
c1334218 MB |
2093 | static void wm8904_sync_cache(struct snd_soc_codec *codec) |
2094 | { | |
f578a188 | 2095 | u16 *reg_cache = codec->reg_cache; |
c1334218 MB |
2096 | int i; |
2097 | ||
2098 | if (!codec->cache_sync) | |
2099 | return; | |
2100 | ||
2101 | codec->cache_only = 0; | |
2102 | ||
2103 | /* Sync back cached values if they're different from the | |
2104 | * hardware default. | |
2105 | */ | |
f578a188 | 2106 | for (i = 1; i < codec->driver->reg_cache_size; i++) { |
c1334218 MB |
2107 | if (!wm8904_access[i].writable) |
2108 | continue; | |
2109 | ||
f578a188 | 2110 | if (reg_cache[i] == wm8904_reg[i]) |
c1334218 MB |
2111 | continue; |
2112 | ||
f578a188 | 2113 | snd_soc_write(codec, i, reg_cache[i]); |
c1334218 MB |
2114 | } |
2115 | ||
2116 | codec->cache_sync = 0; | |
2117 | } | |
2118 | ||
a91eb199 MB |
2119 | static int wm8904_set_bias_level(struct snd_soc_codec *codec, |
2120 | enum snd_soc_bias_level level) | |
2121 | { | |
b2c812e2 | 2122 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
c1334218 | 2123 | int ret; |
a91eb199 MB |
2124 | |
2125 | switch (level) { | |
2126 | case SND_SOC_BIAS_ON: | |
2127 | break; | |
2128 | ||
2129 | case SND_SOC_BIAS_PREPARE: | |
2130 | /* VMID resistance 2*50k */ | |
2131 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2132 | WM8904_VMID_RES_MASK, | |
2133 | 0x1 << WM8904_VMID_RES_SHIFT); | |
2134 | ||
2135 | /* Normal bias current */ | |
2136 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2137 | WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); | |
2138 | break; | |
2139 | ||
2140 | case SND_SOC_BIAS_STANDBY: | |
2141 | if (codec->bias_level == SND_SOC_BIAS_OFF) { | |
2142 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), | |
2143 | wm8904->supplies); | |
2144 | if (ret != 0) { | |
2145 | dev_err(codec->dev, | |
2146 | "Failed to enable supplies: %d\n", | |
2147 | ret); | |
2148 | return ret; | |
2149 | } | |
2150 | ||
c1334218 | 2151 | wm8904_sync_cache(codec); |
a91eb199 MB |
2152 | |
2153 | /* Enable bias */ | |
2154 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2155 | WM8904_BIAS_ENA, WM8904_BIAS_ENA); | |
2156 | ||
2157 | /* Enable VMID, VMID buffering, 2*5k resistance */ | |
2158 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2159 | WM8904_VMID_ENA | | |
2160 | WM8904_VMID_RES_MASK, | |
2161 | WM8904_VMID_ENA | | |
2162 | 0x3 << WM8904_VMID_RES_SHIFT); | |
2163 | ||
2164 | /* Let VMID ramp */ | |
2165 | msleep(1); | |
2166 | } | |
2167 | ||
2168 | /* Maintain VMID with 2*250k */ | |
2169 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2170 | WM8904_VMID_RES_MASK, | |
2171 | 0x2 << WM8904_VMID_RES_SHIFT); | |
2172 | ||
2173 | /* Bias current *0.5 */ | |
2174 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2175 | WM8904_ISEL_MASK, 0); | |
2176 | break; | |
2177 | ||
2178 | case SND_SOC_BIAS_OFF: | |
2179 | /* Turn off VMID */ | |
2180 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2181 | WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); | |
2182 | ||
2183 | /* Stop bias generation */ | |
2184 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2185 | WM8904_BIAS_ENA, 0); | |
2186 | ||
c1334218 MB |
2187 | #ifdef CONFIG_REGULATOR |
2188 | /* Post 2.6.34 we will be able to get a callback when | |
2189 | * the regulators are disabled which we can use but | |
2190 | * for now just assume that the power will be cut if | |
2191 | * the regulator API is in use. | |
2192 | */ | |
2193 | codec->cache_sync = 1; | |
2194 | #endif | |
2195 | ||
a91eb199 MB |
2196 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), |
2197 | wm8904->supplies); | |
2198 | break; | |
2199 | } | |
2200 | codec->bias_level = level; | |
2201 | return 0; | |
2202 | } | |
2203 | ||
2204 | #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 | |
2205 | ||
2206 | #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
2207 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
2208 | ||
2209 | static struct snd_soc_dai_ops wm8904_dai_ops = { | |
2210 | .set_sysclk = wm8904_set_sysclk, | |
2211 | .set_fmt = wm8904_set_fmt, | |
2212 | .set_tdm_slot = wm8904_set_tdm_slot, | |
2213 | .set_pll = wm8904_set_fll, | |
2214 | .hw_params = wm8904_hw_params, | |
2215 | .digital_mute = wm8904_digital_mute, | |
2216 | }; | |
2217 | ||
f0fba2ad LG |
2218 | static struct snd_soc_dai_driver wm8904_dai = { |
2219 | .name = "wm8904-hifi", | |
a91eb199 MB |
2220 | .playback = { |
2221 | .stream_name = "Playback", | |
2222 | .channels_min = 2, | |
2223 | .channels_max = 2, | |
2224 | .rates = WM8904_RATES, | |
2225 | .formats = WM8904_FORMATS, | |
2226 | }, | |
2227 | .capture = { | |
2228 | .stream_name = "Capture", | |
2229 | .channels_min = 2, | |
2230 | .channels_max = 2, | |
2231 | .rates = WM8904_RATES, | |
2232 | .formats = WM8904_FORMATS, | |
2233 | }, | |
2234 | .ops = &wm8904_dai_ops, | |
2235 | .symmetric_rates = 1, | |
2236 | }; | |
a91eb199 MB |
2237 | |
2238 | #ifdef CONFIG_PM | |
f0fba2ad | 2239 | static int wm8904_suspend(struct snd_soc_codec *codec, pm_message_t state) |
a91eb199 | 2240 | { |
a91eb199 MB |
2241 | wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); |
2242 | ||
2243 | return 0; | |
2244 | } | |
2245 | ||
f0fba2ad | 2246 | static int wm8904_resume(struct snd_soc_codec *codec) |
a91eb199 | 2247 | { |
a91eb199 MB |
2248 | wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
2249 | ||
2250 | return 0; | |
2251 | } | |
2252 | #else | |
2253 | #define wm8904_suspend NULL | |
2254 | #define wm8904_resume NULL | |
2255 | #endif | |
2256 | ||
f0fba2ad | 2257 | static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec) |
a91eb199 | 2258 | { |
f0fba2ad | 2259 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
2260 | struct wm8904_pdata *pdata = wm8904->pdata; |
2261 | struct snd_kcontrol_new control = | |
2262 | SOC_ENUM_EXT("EQ Mode", | |
2263 | wm8904->retune_mobile_enum, | |
2264 | wm8904_get_retune_mobile_enum, | |
2265 | wm8904_put_retune_mobile_enum); | |
2266 | int ret, i, j; | |
2267 | const char **t; | |
2268 | ||
2269 | /* We need an array of texts for the enum API but the number | |
2270 | * of texts is likely to be less than the number of | |
2271 | * configurations due to the sample rate dependency of the | |
2272 | * configurations. */ | |
2273 | wm8904->num_retune_mobile_texts = 0; | |
2274 | wm8904->retune_mobile_texts = NULL; | |
2275 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
2276 | for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { | |
2277 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
2278 | wm8904->retune_mobile_texts[j]) == 0) | |
2279 | break; | |
2280 | } | |
2281 | ||
2282 | if (j != wm8904->num_retune_mobile_texts) | |
2283 | continue; | |
2284 | ||
2285 | /* Expand the array... */ | |
2286 | t = krealloc(wm8904->retune_mobile_texts, | |
2287 | sizeof(char *) * | |
2288 | (wm8904->num_retune_mobile_texts + 1), | |
2289 | GFP_KERNEL); | |
2290 | if (t == NULL) | |
2291 | continue; | |
2292 | ||
2293 | /* ...store the new entry... */ | |
2294 | t[wm8904->num_retune_mobile_texts] = | |
2295 | pdata->retune_mobile_cfgs[i].name; | |
2296 | ||
2297 | /* ...and remember the new version. */ | |
2298 | wm8904->num_retune_mobile_texts++; | |
2299 | wm8904->retune_mobile_texts = t; | |
2300 | } | |
2301 | ||
2302 | dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", | |
2303 | wm8904->num_retune_mobile_texts); | |
2304 | ||
2305 | wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts; | |
2306 | wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; | |
2307 | ||
f0fba2ad | 2308 | ret = snd_soc_add_controls(codec, &control, 1); |
a91eb199 | 2309 | if (ret != 0) |
f0fba2ad | 2310 | dev_err(codec->dev, |
a91eb199 MB |
2311 | "Failed to add ReTune Mobile control: %d\n", ret); |
2312 | } | |
2313 | ||
f0fba2ad | 2314 | static void wm8904_handle_pdata(struct snd_soc_codec *codec) |
a91eb199 | 2315 | { |
f0fba2ad | 2316 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
2317 | struct wm8904_pdata *pdata = wm8904->pdata; |
2318 | int ret, i; | |
2319 | ||
2320 | if (!pdata) { | |
f0fba2ad | 2321 | snd_soc_add_controls(codec, wm8904_eq_controls, |
a91eb199 MB |
2322 | ARRAY_SIZE(wm8904_eq_controls)); |
2323 | return; | |
2324 | } | |
2325 | ||
2326 | dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); | |
2327 | ||
2328 | if (pdata->num_drc_cfgs) { | |
2329 | struct snd_kcontrol_new control = | |
2330 | SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, | |
2331 | wm8904_get_drc_enum, wm8904_put_drc_enum); | |
2332 | ||
2333 | /* We need an array of texts for the enum API */ | |
2334 | wm8904->drc_texts = kmalloc(sizeof(char *) | |
2335 | * pdata->num_drc_cfgs, GFP_KERNEL); | |
2336 | if (!wm8904->drc_texts) { | |
f0fba2ad | 2337 | dev_err(codec->dev, |
a91eb199 MB |
2338 | "Failed to allocate %d DRC config texts\n", |
2339 | pdata->num_drc_cfgs); | |
2340 | return; | |
2341 | } | |
2342 | ||
2343 | for (i = 0; i < pdata->num_drc_cfgs; i++) | |
2344 | wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; | |
2345 | ||
2346 | wm8904->drc_enum.max = pdata->num_drc_cfgs; | |
2347 | wm8904->drc_enum.texts = wm8904->drc_texts; | |
2348 | ||
f0fba2ad | 2349 | ret = snd_soc_add_controls(codec, &control, 1); |
a91eb199 | 2350 | if (ret != 0) |
f0fba2ad | 2351 | dev_err(codec->dev, |
a91eb199 MB |
2352 | "Failed to add DRC mode control: %d\n", ret); |
2353 | ||
2354 | wm8904_set_drc(codec); | |
2355 | } | |
2356 | ||
2357 | dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", | |
2358 | pdata->num_retune_mobile_cfgs); | |
2359 | ||
2360 | if (pdata->num_retune_mobile_cfgs) | |
f0fba2ad | 2361 | wm8904_handle_retune_mobile_pdata(codec); |
a91eb199 | 2362 | else |
f0fba2ad | 2363 | snd_soc_add_controls(codec, wm8904_eq_controls, |
a91eb199 MB |
2364 | ARRAY_SIZE(wm8904_eq_controls)); |
2365 | } | |
2366 | ||
a91eb199 | 2367 | |
f0fba2ad | 2368 | static int wm8904_probe(struct snd_soc_codec *codec) |
a91eb199 | 2369 | { |
f0fba2ad | 2370 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
cdce4e9b | 2371 | struct wm8904_pdata *pdata = wm8904->pdata; |
f578a188 | 2372 | u16 *reg_cache = codec->reg_cache; |
f0fba2ad | 2373 | int ret, i; |
a91eb199 | 2374 | |
c1334218 MB |
2375 | codec->cache_sync = 1; |
2376 | codec->idle_bias_off = 1; | |
a91eb199 | 2377 | |
8c126474 MB |
2378 | switch (wm8904->devtype) { |
2379 | case WM8904: | |
2380 | break; | |
2381 | case WM8912: | |
2382 | memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); | |
2383 | break; | |
2384 | default: | |
2385 | dev_err(codec->dev, "Unknown device type %d\n", | |
2386 | wm8904->devtype); | |
f0fba2ad | 2387 | return -EINVAL; |
8c126474 MB |
2388 | } |
2389 | ||
f0fba2ad | 2390 | ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); |
a91eb199 MB |
2391 | if (ret != 0) { |
2392 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
f0fba2ad | 2393 | return ret; |
a91eb199 MB |
2394 | } |
2395 | ||
2396 | for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) | |
2397 | wm8904->supplies[i].supply = wm8904_supply_names[i]; | |
2398 | ||
2399 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies), | |
2400 | wm8904->supplies); | |
2401 | if (ret != 0) { | |
2402 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
f0fba2ad | 2403 | return ret; |
a91eb199 MB |
2404 | } |
2405 | ||
2406 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), | |
2407 | wm8904->supplies); | |
2408 | if (ret != 0) { | |
2409 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
2410 | goto err_get; | |
2411 | } | |
2412 | ||
2413 | ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID); | |
2414 | if (ret < 0) { | |
2415 | dev_err(codec->dev, "Failed to read ID register\n"); | |
2416 | goto err_enable; | |
2417 | } | |
2418 | if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) { | |
2419 | dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret); | |
2420 | ret = -EINVAL; | |
2421 | goto err_enable; | |
2422 | } | |
2423 | ||
2424 | ret = snd_soc_read(codec, WM8904_REVISION); | |
2425 | if (ret < 0) { | |
2426 | dev_err(codec->dev, "Failed to read device revision: %d\n", | |
2427 | ret); | |
2428 | goto err_enable; | |
2429 | } | |
2430 | dev_info(codec->dev, "revision %c\n", ret + 'A'); | |
2431 | ||
2432 | ret = wm8904_reset(codec); | |
2433 | if (ret < 0) { | |
2434 | dev_err(codec->dev, "Failed to issue reset\n"); | |
2435 | goto err_enable; | |
2436 | } | |
2437 | ||
a91eb199 | 2438 | /* Change some default settings - latch VU and enable ZC */ |
f578a188 LPC |
2439 | reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU; |
2440 | reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU; | |
2441 | reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU; | |
2442 | reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU; | |
2443 | reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU | | |
a91eb199 | 2444 | WM8904_HPOUTLZC; |
f578a188 | 2445 | reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU | |
a91eb199 | 2446 | WM8904_HPOUTRZC; |
f578a188 | 2447 | reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU | |
a91eb199 | 2448 | WM8904_LINEOUTLZC; |
f578a188 | 2449 | reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU | |
a91eb199 | 2450 | WM8904_LINEOUTRZC; |
f578a188 | 2451 | reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; |
a91eb199 | 2452 | |
cdce4e9b MB |
2453 | /* Apply configuration from the platform data. */ |
2454 | if (wm8904->pdata) { | |
2455 | for (i = 0; i < WM8904_GPIO_REGS; i++) { | |
2456 | if (!pdata->gpio_cfg[i]) | |
2457 | continue; | |
2458 | ||
f578a188 | 2459 | reg_cache[WM8904_GPIO_CONTROL_1 + i] |
cdce4e9b MB |
2460 | = pdata->gpio_cfg[i] & 0xffff; |
2461 | } | |
fbc2dae8 MB |
2462 | |
2463 | /* Zero is the default value for these anyway */ | |
2464 | for (i = 0; i < WM8904_MIC_REGS; i++) | |
f578a188 | 2465 | reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] |
fbc2dae8 | 2466 | = pdata->mic_cfg[i]; |
cdce4e9b MB |
2467 | } |
2468 | ||
a91eb199 MB |
2469 | /* Set Class W by default - this will be managed by the Class |
2470 | * G widget at runtime where bypass paths are available. | |
2471 | */ | |
f578a188 | 2472 | reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR; |
a91eb199 MB |
2473 | |
2474 | /* Use normal bias source */ | |
f578a188 | 2475 | reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL; |
a91eb199 MB |
2476 | |
2477 | wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2478 | ||
2479 | /* Bias level configuration will have done an extra enable */ | |
2480 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2481 | ||
f0fba2ad | 2482 | wm8904_handle_pdata(codec); |
a91eb199 | 2483 | |
f0fba2ad | 2484 | wm8904_add_widgets(codec); |
a91eb199 MB |
2485 | |
2486 | return 0; | |
2487 | ||
2488 | err_enable: | |
2489 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2490 | err_get: | |
2491 | regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
a91eb199 MB |
2492 | return ret; |
2493 | } | |
2494 | ||
f0fba2ad | 2495 | static int wm8904_remove(struct snd_soc_codec *codec) |
a91eb199 | 2496 | { |
f0fba2ad LG |
2497 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
2498 | ||
2499 | wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
a91eb199 | 2500 | regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); |
cd70978c AL |
2501 | kfree(wm8904->retune_mobile_texts); |
2502 | kfree(wm8904->drc_texts); | |
f0fba2ad LG |
2503 | |
2504 | return 0; | |
a91eb199 MB |
2505 | } |
2506 | ||
f0fba2ad LG |
2507 | static struct snd_soc_codec_driver soc_codec_dev_wm8904 = { |
2508 | .probe = wm8904_probe, | |
2509 | .remove = wm8904_remove, | |
2510 | .suspend = wm8904_suspend, | |
2511 | .resume = wm8904_resume, | |
2512 | .set_bias_level = wm8904_set_bias_level, | |
2513 | .reg_cache_size = ARRAY_SIZE(wm8904_reg), | |
2514 | .reg_word_size = sizeof(u16), | |
2515 | .reg_cache_default = wm8904_reg, | |
2516 | .volatile_register = wm8904_volatile_register, | |
2517 | }; | |
2518 | ||
a91eb199 MB |
2519 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
2520 | static __devinit int wm8904_i2c_probe(struct i2c_client *i2c, | |
2521 | const struct i2c_device_id *id) | |
2522 | { | |
2523 | struct wm8904_priv *wm8904; | |
f0fba2ad | 2524 | int ret; |
a91eb199 MB |
2525 | |
2526 | wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL); | |
2527 | if (wm8904 == NULL) | |
2528 | return -ENOMEM; | |
2529 | ||
8c126474 | 2530 | wm8904->devtype = id->driver_data; |
a91eb199 | 2531 | i2c_set_clientdata(i2c, wm8904); |
f0fba2ad | 2532 | wm8904->control_data = i2c; |
a91eb199 MB |
2533 | wm8904->pdata = i2c->dev.platform_data; |
2534 | ||
f0fba2ad LG |
2535 | ret = snd_soc_register_codec(&i2c->dev, |
2536 | &soc_codec_dev_wm8904, &wm8904_dai, 1); | |
2537 | if (ret < 0) | |
2538 | kfree(wm8904); | |
2539 | return ret; | |
a91eb199 MB |
2540 | } |
2541 | ||
2542 | static __devexit int wm8904_i2c_remove(struct i2c_client *client) | |
2543 | { | |
f0fba2ad LG |
2544 | snd_soc_unregister_codec(&client->dev); |
2545 | kfree(i2c_get_clientdata(client)); | |
a91eb199 MB |
2546 | return 0; |
2547 | } | |
2548 | ||
2549 | static const struct i2c_device_id wm8904_i2c_id[] = { | |
8c126474 MB |
2550 | { "wm8904", WM8904 }, |
2551 | { "wm8912", WM8912 }, | |
a91eb199 MB |
2552 | { } |
2553 | }; | |
2554 | MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); | |
2555 | ||
2556 | static struct i2c_driver wm8904_i2c_driver = { | |
2557 | .driver = { | |
f0fba2ad | 2558 | .name = "wm8904-codec", |
a91eb199 MB |
2559 | .owner = THIS_MODULE, |
2560 | }, | |
2561 | .probe = wm8904_i2c_probe, | |
2562 | .remove = __devexit_p(wm8904_i2c_remove), | |
2563 | .id_table = wm8904_i2c_id, | |
2564 | }; | |
2565 | #endif | |
2566 | ||
2567 | static int __init wm8904_modinit(void) | |
2568 | { | |
f0fba2ad | 2569 | int ret = 0; |
a91eb199 MB |
2570 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
2571 | ret = i2c_add_driver(&wm8904_i2c_driver); | |
2572 | if (ret != 0) { | |
f0fba2ad | 2573 | printk(KERN_ERR "Failed to register wm8904 I2C driver: %d\n", |
a91eb199 MB |
2574 | ret); |
2575 | } | |
2576 | #endif | |
f0fba2ad | 2577 | return ret; |
a91eb199 MB |
2578 | } |
2579 | module_init(wm8904_modinit); | |
2580 | ||
2581 | static void __exit wm8904_exit(void) | |
2582 | { | |
2583 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
2584 | i2c_del_driver(&wm8904_i2c_driver); | |
2585 | #endif | |
2586 | } | |
2587 | module_exit(wm8904_exit); | |
2588 | ||
2589 | MODULE_DESCRIPTION("ASoC WM8904 driver"); | |
2590 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
2591 | MODULE_LICENSE("GPL"); |