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c93993ac MB |
1 | /* |
2 | * wm8915.c - WM8915 audio codec interface | |
3 | * | |
4 | * Copyright 2011 Wolfson Microelectronics PLC. | |
5 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/completion.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/gcd.h> | |
20 | #include <linux/gpio.h> | |
21 | #include <linux/i2c.h> | |
c93993ac MB |
22 | #include <linux/regulator/consumer.h> |
23 | #include <linux/slab.h> | |
24 | #include <linux/workqueue.h> | |
25 | #include <sound/core.h> | |
26 | #include <sound/jack.h> | |
27 | #include <sound/pcm.h> | |
28 | #include <sound/pcm_params.h> | |
29 | #include <sound/soc.h> | |
30 | #include <sound/initval.h> | |
31 | #include <sound/tlv.h> | |
32 | #include <trace/events/asoc.h> | |
33 | ||
34 | #include <sound/wm8915.h> | |
35 | #include "wm8915.h" | |
36 | ||
37 | #define WM8915_AIFS 2 | |
38 | ||
39 | #define HPOUT1L 1 | |
40 | #define HPOUT1R 2 | |
41 | #define HPOUT2L 4 | |
42 | #define HPOUT2R 8 | |
43 | ||
cf4a3910 | 44 | #define WM8915_NUM_SUPPLIES 4 |
c93993ac | 45 | static const char *wm8915_supply_names[WM8915_NUM_SUPPLIES] = { |
c93993ac MB |
46 | "DBVDD", |
47 | "AVDD1", | |
48 | "AVDD2", | |
49 | "CPVDD", | |
c93993ac MB |
50 | }; |
51 | ||
52 | struct wm8915_priv { | |
53 | struct snd_soc_codec *codec; | |
54 | ||
55 | int ldo1ena; | |
56 | ||
57 | int sysclk; | |
ea7b4378 | 58 | int sysclk_src; |
c93993ac MB |
59 | |
60 | int fll_src; | |
61 | int fll_fref; | |
62 | int fll_fout; | |
63 | ||
64 | struct completion fll_lock; | |
65 | ||
66 | u16 dcs_pending; | |
67 | struct completion dcs_done; | |
68 | ||
69 | u16 hpout_ena; | |
70 | u16 hpout_pending; | |
71 | ||
72 | struct regulator_bulk_data supplies[WM8915_NUM_SUPPLIES]; | |
73 | struct notifier_block disable_nb[WM8915_NUM_SUPPLIES]; | |
74 | ||
75 | struct wm8915_pdata pdata; | |
76 | ||
77 | int rx_rate[WM8915_AIFS]; | |
6dffdea7 | 78 | int bclk_rate[WM8915_AIFS]; |
c93993ac MB |
79 | |
80 | /* Platform dependant ReTune mobile configuration */ | |
81 | int num_retune_mobile_texts; | |
82 | const char **retune_mobile_texts; | |
83 | int retune_mobile_cfg[2]; | |
84 | struct soc_enum retune_mobile_enum; | |
85 | ||
86 | struct snd_soc_jack *jack; | |
87 | bool detecting; | |
88 | bool jack_mic; | |
89 | wm8915_polarity_fn polarity_cb; | |
90 | ||
91 | #ifdef CONFIG_GPIOLIB | |
92 | struct gpio_chip gpio_chip; | |
93 | #endif | |
94 | }; | |
95 | ||
96 | /* We can't use the same notifier block for more than one supply and | |
97 | * there's no way I can see to get from a callback to the caller | |
98 | * except container_of(). | |
99 | */ | |
100 | #define WM8915_REGULATOR_EVENT(n) \ | |
101 | static int wm8915_regulator_event_##n(struct notifier_block *nb, \ | |
102 | unsigned long event, void *data) \ | |
103 | { \ | |
104 | struct wm8915_priv *wm8915 = container_of(nb, struct wm8915_priv, \ | |
105 | disable_nb[n]); \ | |
106 | if (event & REGULATOR_EVENT_DISABLE) { \ | |
107 | wm8915->codec->cache_sync = 1; \ | |
108 | } \ | |
109 | return 0; \ | |
110 | } | |
111 | ||
112 | WM8915_REGULATOR_EVENT(0) | |
113 | WM8915_REGULATOR_EVENT(1) | |
114 | WM8915_REGULATOR_EVENT(2) | |
115 | WM8915_REGULATOR_EVENT(3) | |
c93993ac MB |
116 | |
117 | static const u16 wm8915_reg[WM8915_MAX_REGISTER] = { | |
118 | [WM8915_SOFTWARE_RESET] = 0x8915, | |
119 | [WM8915_POWER_MANAGEMENT_7] = 0x10, | |
120 | [WM8915_DAC1_HPOUT1_VOLUME] = 0x88, | |
121 | [WM8915_DAC2_HPOUT2_VOLUME] = 0x88, | |
122 | [WM8915_DAC1_LEFT_VOLUME] = 0x2c0, | |
123 | [WM8915_DAC1_RIGHT_VOLUME] = 0x2c0, | |
124 | [WM8915_DAC2_LEFT_VOLUME] = 0x2c0, | |
125 | [WM8915_DAC2_RIGHT_VOLUME] = 0x2c0, | |
126 | [WM8915_OUTPUT1_LEFT_VOLUME] = 0x80, | |
127 | [WM8915_OUTPUT1_RIGHT_VOLUME] = 0x80, | |
128 | [WM8915_OUTPUT2_LEFT_VOLUME] = 0x80, | |
129 | [WM8915_OUTPUT2_RIGHT_VOLUME] = 0x80, | |
130 | [WM8915_MICBIAS_1] = 0x39, | |
131 | [WM8915_MICBIAS_2] = 0x39, | |
132 | [WM8915_LDO_1] = 0x3, | |
133 | [WM8915_LDO_2] = 0x13, | |
134 | [WM8915_ACCESSORY_DETECT_MODE_1] = 0x4, | |
135 | [WM8915_HEADPHONE_DETECT_1] = 0x20, | |
136 | [WM8915_MIC_DETECT_1] = 0x7600, | |
137 | [WM8915_MIC_DETECT_2] = 0xbf, | |
138 | [WM8915_CHARGE_PUMP_1] = 0x1f25, | |
139 | [WM8915_CHARGE_PUMP_2] = 0xab19, | |
140 | [WM8915_DC_SERVO_5] = 0x2a2a, | |
141 | [WM8915_CONTROL_INTERFACE_1] = 0x8004, | |
142 | [WM8915_CLOCKING_1] = 0x10, | |
143 | [WM8915_AIF_RATE] = 0x83, | |
144 | [WM8915_FLL_CONTROL_4] = 0x5dc0, | |
145 | [WM8915_FLL_CONTROL_5] = 0xc84, | |
146 | [WM8915_FLL_EFS_2] = 0x2, | |
147 | [WM8915_AIF1_TX_LRCLK_1] = 0x80, | |
148 | [WM8915_AIF1_TX_LRCLK_2] = 0x8, | |
149 | [WM8915_AIF1_RX_LRCLK_1] = 0x80, | |
150 | [WM8915_AIF1TX_DATA_CONFIGURATION_1] = 0x1818, | |
151 | [WM8915_AIF1RX_DATA_CONFIGURATION] = 0x1818, | |
152 | [WM8915_AIF1TX_TEST] = 0x7, | |
153 | [WM8915_AIF2_TX_LRCLK_1] = 0x80, | |
154 | [WM8915_AIF2_TX_LRCLK_2] = 0x8, | |
155 | [WM8915_AIF2_RX_LRCLK_1] = 0x80, | |
156 | [WM8915_AIF2TX_DATA_CONFIGURATION_1] = 0x1818, | |
157 | [WM8915_AIF2RX_DATA_CONFIGURATION] = 0x1818, | |
158 | [WM8915_AIF2TX_TEST] = 0x1, | |
159 | [WM8915_DSP1_TX_LEFT_VOLUME] = 0xc0, | |
160 | [WM8915_DSP1_TX_RIGHT_VOLUME] = 0xc0, | |
161 | [WM8915_DSP1_RX_LEFT_VOLUME] = 0xc0, | |
162 | [WM8915_DSP1_RX_RIGHT_VOLUME] = 0xc0, | |
163 | [WM8915_DSP1_TX_FILTERS] = 0x2000, | |
164 | [WM8915_DSP1_RX_FILTERS_1] = 0x200, | |
165 | [WM8915_DSP1_RX_FILTERS_2] = 0x10, | |
166 | [WM8915_DSP1_DRC_1] = 0x98, | |
167 | [WM8915_DSP1_DRC_2] = 0x845, | |
168 | [WM8915_DSP1_RX_EQ_GAINS_1] = 0x6318, | |
169 | [WM8915_DSP1_RX_EQ_GAINS_2] = 0x6300, | |
170 | [WM8915_DSP1_RX_EQ_BAND_1_A] = 0xfca, | |
171 | [WM8915_DSP1_RX_EQ_BAND_1_B] = 0x400, | |
172 | [WM8915_DSP1_RX_EQ_BAND_1_PG] = 0xd8, | |
173 | [WM8915_DSP1_RX_EQ_BAND_2_A] = 0x1eb5, | |
174 | [WM8915_DSP1_RX_EQ_BAND_2_B] = 0xf145, | |
175 | [WM8915_DSP1_RX_EQ_BAND_2_C] = 0xb75, | |
176 | [WM8915_DSP1_RX_EQ_BAND_2_PG] = 0x1c5, | |
177 | [WM8915_DSP1_RX_EQ_BAND_3_A] = 0x1c58, | |
178 | [WM8915_DSP1_RX_EQ_BAND_3_B] = 0xf373, | |
179 | [WM8915_DSP1_RX_EQ_BAND_3_C] = 0xa54, | |
180 | [WM8915_DSP1_RX_EQ_BAND_3_PG] = 0x558, | |
181 | [WM8915_DSP1_RX_EQ_BAND_4_A] = 0x168e, | |
182 | [WM8915_DSP1_RX_EQ_BAND_4_B] = 0xf829, | |
183 | [WM8915_DSP1_RX_EQ_BAND_4_C] = 0x7ad, | |
184 | [WM8915_DSP1_RX_EQ_BAND_4_PG] = 0x1103, | |
185 | [WM8915_DSP1_RX_EQ_BAND_5_A] = 0x564, | |
186 | [WM8915_DSP1_RX_EQ_BAND_5_B] = 0x559, | |
187 | [WM8915_DSP1_RX_EQ_BAND_5_PG] = 0x4000, | |
188 | [WM8915_DSP2_TX_LEFT_VOLUME] = 0xc0, | |
189 | [WM8915_DSP2_TX_RIGHT_VOLUME] = 0xc0, | |
190 | [WM8915_DSP2_RX_LEFT_VOLUME] = 0xc0, | |
191 | [WM8915_DSP2_RX_RIGHT_VOLUME] = 0xc0, | |
192 | [WM8915_DSP2_TX_FILTERS] = 0x2000, | |
193 | [WM8915_DSP2_RX_FILTERS_1] = 0x200, | |
194 | [WM8915_DSP2_RX_FILTERS_2] = 0x10, | |
195 | [WM8915_DSP2_DRC_1] = 0x98, | |
196 | [WM8915_DSP2_DRC_2] = 0x845, | |
197 | [WM8915_DSP2_RX_EQ_GAINS_1] = 0x6318, | |
198 | [WM8915_DSP2_RX_EQ_GAINS_2] = 0x6300, | |
199 | [WM8915_DSP2_RX_EQ_BAND_1_A] = 0xfca, | |
200 | [WM8915_DSP2_RX_EQ_BAND_1_B] = 0x400, | |
201 | [WM8915_DSP2_RX_EQ_BAND_1_PG] = 0xd8, | |
202 | [WM8915_DSP2_RX_EQ_BAND_2_A] = 0x1eb5, | |
203 | [WM8915_DSP2_RX_EQ_BAND_2_B] = 0xf145, | |
204 | [WM8915_DSP2_RX_EQ_BAND_2_C] = 0xb75, | |
205 | [WM8915_DSP2_RX_EQ_BAND_2_PG] = 0x1c5, | |
206 | [WM8915_DSP2_RX_EQ_BAND_3_A] = 0x1c58, | |
207 | [WM8915_DSP2_RX_EQ_BAND_3_B] = 0xf373, | |
208 | [WM8915_DSP2_RX_EQ_BAND_3_C] = 0xa54, | |
209 | [WM8915_DSP2_RX_EQ_BAND_3_PG] = 0x558, | |
210 | [WM8915_DSP2_RX_EQ_BAND_4_A] = 0x168e, | |
211 | [WM8915_DSP2_RX_EQ_BAND_4_B] = 0xf829, | |
212 | [WM8915_DSP2_RX_EQ_BAND_4_C] = 0x7ad, | |
213 | [WM8915_DSP2_RX_EQ_BAND_4_PG] = 0x1103, | |
214 | [WM8915_DSP2_RX_EQ_BAND_5_A] = 0x564, | |
215 | [WM8915_DSP2_RX_EQ_BAND_5_B] = 0x559, | |
216 | [WM8915_DSP2_RX_EQ_BAND_5_PG] = 0x4000, | |
217 | [WM8915_OVERSAMPLING] = 0xd, | |
218 | [WM8915_SIDETONE] = 0x1040, | |
219 | [WM8915_GPIO_1] = 0xa101, | |
220 | [WM8915_GPIO_2] = 0xa101, | |
221 | [WM8915_GPIO_3] = 0xa101, | |
222 | [WM8915_GPIO_4] = 0xa101, | |
223 | [WM8915_GPIO_5] = 0xa101, | |
224 | [WM8915_PULL_CONTROL_2] = 0x140, | |
225 | [WM8915_INTERRUPT_STATUS_1_MASK] = 0x1f, | |
226 | [WM8915_INTERRUPT_STATUS_2_MASK] = 0x1ecf, | |
227 | [WM8915_RIGHT_PDM_SPEAKER] = 0x1, | |
228 | [WM8915_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69, | |
229 | [WM8915_PDM_SPEAKER_VOLUME] = 0x66, | |
230 | [WM8915_WRITE_SEQUENCER_0] = 0x1, | |
231 | [WM8915_WRITE_SEQUENCER_1] = 0x1, | |
232 | [WM8915_WRITE_SEQUENCER_3] = 0x6, | |
233 | [WM8915_WRITE_SEQUENCER_4] = 0x40, | |
234 | [WM8915_WRITE_SEQUENCER_5] = 0x1, | |
235 | [WM8915_WRITE_SEQUENCER_6] = 0xf, | |
236 | [WM8915_WRITE_SEQUENCER_7] = 0x6, | |
237 | [WM8915_WRITE_SEQUENCER_8] = 0x1, | |
238 | [WM8915_WRITE_SEQUENCER_9] = 0x3, | |
239 | [WM8915_WRITE_SEQUENCER_10] = 0x104, | |
240 | [WM8915_WRITE_SEQUENCER_12] = 0x60, | |
241 | [WM8915_WRITE_SEQUENCER_13] = 0x11, | |
242 | [WM8915_WRITE_SEQUENCER_14] = 0x401, | |
243 | [WM8915_WRITE_SEQUENCER_16] = 0x50, | |
244 | [WM8915_WRITE_SEQUENCER_17] = 0x3, | |
245 | [WM8915_WRITE_SEQUENCER_18] = 0x100, | |
246 | [WM8915_WRITE_SEQUENCER_20] = 0x51, | |
247 | [WM8915_WRITE_SEQUENCER_21] = 0x3, | |
248 | [WM8915_WRITE_SEQUENCER_22] = 0x104, | |
249 | [WM8915_WRITE_SEQUENCER_23] = 0xa, | |
250 | [WM8915_WRITE_SEQUENCER_24] = 0x60, | |
251 | [WM8915_WRITE_SEQUENCER_25] = 0x3b, | |
252 | [WM8915_WRITE_SEQUENCER_26] = 0x502, | |
253 | [WM8915_WRITE_SEQUENCER_27] = 0x100, | |
254 | [WM8915_WRITE_SEQUENCER_28] = 0x2fff, | |
255 | [WM8915_WRITE_SEQUENCER_32] = 0x2fff, | |
256 | [WM8915_WRITE_SEQUENCER_36] = 0x2fff, | |
257 | [WM8915_WRITE_SEQUENCER_40] = 0x2fff, | |
258 | [WM8915_WRITE_SEQUENCER_44] = 0x2fff, | |
259 | [WM8915_WRITE_SEQUENCER_48] = 0x2fff, | |
260 | [WM8915_WRITE_SEQUENCER_52] = 0x2fff, | |
261 | [WM8915_WRITE_SEQUENCER_56] = 0x2fff, | |
262 | [WM8915_WRITE_SEQUENCER_60] = 0x2fff, | |
263 | [WM8915_WRITE_SEQUENCER_64] = 0x1, | |
264 | [WM8915_WRITE_SEQUENCER_65] = 0x1, | |
265 | [WM8915_WRITE_SEQUENCER_67] = 0x6, | |
266 | [WM8915_WRITE_SEQUENCER_68] = 0x40, | |
267 | [WM8915_WRITE_SEQUENCER_69] = 0x1, | |
268 | [WM8915_WRITE_SEQUENCER_70] = 0xf, | |
269 | [WM8915_WRITE_SEQUENCER_71] = 0x6, | |
270 | [WM8915_WRITE_SEQUENCER_72] = 0x1, | |
271 | [WM8915_WRITE_SEQUENCER_73] = 0x3, | |
272 | [WM8915_WRITE_SEQUENCER_74] = 0x104, | |
273 | [WM8915_WRITE_SEQUENCER_76] = 0x60, | |
274 | [WM8915_WRITE_SEQUENCER_77] = 0x11, | |
275 | [WM8915_WRITE_SEQUENCER_78] = 0x401, | |
276 | [WM8915_WRITE_SEQUENCER_80] = 0x50, | |
277 | [WM8915_WRITE_SEQUENCER_81] = 0x3, | |
278 | [WM8915_WRITE_SEQUENCER_82] = 0x100, | |
279 | [WM8915_WRITE_SEQUENCER_84] = 0x60, | |
280 | [WM8915_WRITE_SEQUENCER_85] = 0x3b, | |
281 | [WM8915_WRITE_SEQUENCER_86] = 0x502, | |
282 | [WM8915_WRITE_SEQUENCER_87] = 0x100, | |
283 | [WM8915_WRITE_SEQUENCER_88] = 0x2fff, | |
284 | [WM8915_WRITE_SEQUENCER_92] = 0x2fff, | |
285 | [WM8915_WRITE_SEQUENCER_96] = 0x2fff, | |
286 | [WM8915_WRITE_SEQUENCER_100] = 0x2fff, | |
287 | [WM8915_WRITE_SEQUENCER_104] = 0x2fff, | |
288 | [WM8915_WRITE_SEQUENCER_108] = 0x2fff, | |
289 | [WM8915_WRITE_SEQUENCER_112] = 0x2fff, | |
290 | [WM8915_WRITE_SEQUENCER_116] = 0x2fff, | |
291 | [WM8915_WRITE_SEQUENCER_120] = 0x2fff, | |
292 | [WM8915_WRITE_SEQUENCER_124] = 0x2fff, | |
293 | [WM8915_WRITE_SEQUENCER_128] = 0x1, | |
294 | [WM8915_WRITE_SEQUENCER_129] = 0x1, | |
295 | [WM8915_WRITE_SEQUENCER_131] = 0x6, | |
296 | [WM8915_WRITE_SEQUENCER_132] = 0x40, | |
297 | [WM8915_WRITE_SEQUENCER_133] = 0x1, | |
298 | [WM8915_WRITE_SEQUENCER_134] = 0xf, | |
299 | [WM8915_WRITE_SEQUENCER_135] = 0x6, | |
300 | [WM8915_WRITE_SEQUENCER_136] = 0x1, | |
301 | [WM8915_WRITE_SEQUENCER_137] = 0x3, | |
302 | [WM8915_WRITE_SEQUENCER_138] = 0x106, | |
303 | [WM8915_WRITE_SEQUENCER_140] = 0x61, | |
304 | [WM8915_WRITE_SEQUENCER_141] = 0x11, | |
305 | [WM8915_WRITE_SEQUENCER_142] = 0x401, | |
306 | [WM8915_WRITE_SEQUENCER_144] = 0x50, | |
307 | [WM8915_WRITE_SEQUENCER_145] = 0x3, | |
308 | [WM8915_WRITE_SEQUENCER_146] = 0x102, | |
309 | [WM8915_WRITE_SEQUENCER_148] = 0x51, | |
310 | [WM8915_WRITE_SEQUENCER_149] = 0x3, | |
311 | [WM8915_WRITE_SEQUENCER_150] = 0x106, | |
312 | [WM8915_WRITE_SEQUENCER_151] = 0xa, | |
313 | [WM8915_WRITE_SEQUENCER_152] = 0x61, | |
314 | [WM8915_WRITE_SEQUENCER_153] = 0x3b, | |
315 | [WM8915_WRITE_SEQUENCER_154] = 0x502, | |
316 | [WM8915_WRITE_SEQUENCER_155] = 0x100, | |
317 | [WM8915_WRITE_SEQUENCER_156] = 0x2fff, | |
318 | [WM8915_WRITE_SEQUENCER_160] = 0x2fff, | |
319 | [WM8915_WRITE_SEQUENCER_164] = 0x2fff, | |
320 | [WM8915_WRITE_SEQUENCER_168] = 0x2fff, | |
321 | [WM8915_WRITE_SEQUENCER_172] = 0x2fff, | |
322 | [WM8915_WRITE_SEQUENCER_176] = 0x2fff, | |
323 | [WM8915_WRITE_SEQUENCER_180] = 0x2fff, | |
324 | [WM8915_WRITE_SEQUENCER_184] = 0x2fff, | |
325 | [WM8915_WRITE_SEQUENCER_188] = 0x2fff, | |
326 | [WM8915_WRITE_SEQUENCER_192] = 0x1, | |
327 | [WM8915_WRITE_SEQUENCER_193] = 0x1, | |
328 | [WM8915_WRITE_SEQUENCER_195] = 0x6, | |
329 | [WM8915_WRITE_SEQUENCER_196] = 0x40, | |
330 | [WM8915_WRITE_SEQUENCER_197] = 0x1, | |
331 | [WM8915_WRITE_SEQUENCER_198] = 0xf, | |
332 | [WM8915_WRITE_SEQUENCER_199] = 0x6, | |
333 | [WM8915_WRITE_SEQUENCER_200] = 0x1, | |
334 | [WM8915_WRITE_SEQUENCER_201] = 0x3, | |
335 | [WM8915_WRITE_SEQUENCER_202] = 0x106, | |
336 | [WM8915_WRITE_SEQUENCER_204] = 0x61, | |
337 | [WM8915_WRITE_SEQUENCER_205] = 0x11, | |
338 | [WM8915_WRITE_SEQUENCER_206] = 0x401, | |
339 | [WM8915_WRITE_SEQUENCER_208] = 0x50, | |
340 | [WM8915_WRITE_SEQUENCER_209] = 0x3, | |
341 | [WM8915_WRITE_SEQUENCER_210] = 0x102, | |
342 | [WM8915_WRITE_SEQUENCER_212] = 0x61, | |
343 | [WM8915_WRITE_SEQUENCER_213] = 0x3b, | |
344 | [WM8915_WRITE_SEQUENCER_214] = 0x502, | |
345 | [WM8915_WRITE_SEQUENCER_215] = 0x100, | |
346 | [WM8915_WRITE_SEQUENCER_216] = 0x2fff, | |
347 | [WM8915_WRITE_SEQUENCER_220] = 0x2fff, | |
348 | [WM8915_WRITE_SEQUENCER_224] = 0x2fff, | |
349 | [WM8915_WRITE_SEQUENCER_228] = 0x2fff, | |
350 | [WM8915_WRITE_SEQUENCER_232] = 0x2fff, | |
351 | [WM8915_WRITE_SEQUENCER_236] = 0x2fff, | |
352 | [WM8915_WRITE_SEQUENCER_240] = 0x2fff, | |
353 | [WM8915_WRITE_SEQUENCER_244] = 0x2fff, | |
354 | [WM8915_WRITE_SEQUENCER_248] = 0x2fff, | |
355 | [WM8915_WRITE_SEQUENCER_252] = 0x2fff, | |
356 | [WM8915_WRITE_SEQUENCER_256] = 0x60, | |
357 | [WM8915_WRITE_SEQUENCER_258] = 0x601, | |
358 | [WM8915_WRITE_SEQUENCER_260] = 0x50, | |
359 | [WM8915_WRITE_SEQUENCER_262] = 0x100, | |
360 | [WM8915_WRITE_SEQUENCER_264] = 0x1, | |
361 | [WM8915_WRITE_SEQUENCER_266] = 0x104, | |
362 | [WM8915_WRITE_SEQUENCER_267] = 0x100, | |
363 | [WM8915_WRITE_SEQUENCER_268] = 0x2fff, | |
364 | [WM8915_WRITE_SEQUENCER_272] = 0x2fff, | |
365 | [WM8915_WRITE_SEQUENCER_276] = 0x2fff, | |
366 | [WM8915_WRITE_SEQUENCER_280] = 0x2fff, | |
367 | [WM8915_WRITE_SEQUENCER_284] = 0x2fff, | |
368 | [WM8915_WRITE_SEQUENCER_288] = 0x2fff, | |
369 | [WM8915_WRITE_SEQUENCER_292] = 0x2fff, | |
370 | [WM8915_WRITE_SEQUENCER_296] = 0x2fff, | |
371 | [WM8915_WRITE_SEQUENCER_300] = 0x2fff, | |
372 | [WM8915_WRITE_SEQUENCER_304] = 0x2fff, | |
373 | [WM8915_WRITE_SEQUENCER_308] = 0x2fff, | |
374 | [WM8915_WRITE_SEQUENCER_312] = 0x2fff, | |
375 | [WM8915_WRITE_SEQUENCER_316] = 0x2fff, | |
376 | [WM8915_WRITE_SEQUENCER_320] = 0x61, | |
377 | [WM8915_WRITE_SEQUENCER_322] = 0x601, | |
378 | [WM8915_WRITE_SEQUENCER_324] = 0x50, | |
379 | [WM8915_WRITE_SEQUENCER_326] = 0x102, | |
380 | [WM8915_WRITE_SEQUENCER_328] = 0x1, | |
381 | [WM8915_WRITE_SEQUENCER_330] = 0x106, | |
382 | [WM8915_WRITE_SEQUENCER_331] = 0x100, | |
383 | [WM8915_WRITE_SEQUENCER_332] = 0x2fff, | |
384 | [WM8915_WRITE_SEQUENCER_336] = 0x2fff, | |
385 | [WM8915_WRITE_SEQUENCER_340] = 0x2fff, | |
386 | [WM8915_WRITE_SEQUENCER_344] = 0x2fff, | |
387 | [WM8915_WRITE_SEQUENCER_348] = 0x2fff, | |
388 | [WM8915_WRITE_SEQUENCER_352] = 0x2fff, | |
389 | [WM8915_WRITE_SEQUENCER_356] = 0x2fff, | |
390 | [WM8915_WRITE_SEQUENCER_360] = 0x2fff, | |
391 | [WM8915_WRITE_SEQUENCER_364] = 0x2fff, | |
392 | [WM8915_WRITE_SEQUENCER_368] = 0x2fff, | |
393 | [WM8915_WRITE_SEQUENCER_372] = 0x2fff, | |
394 | [WM8915_WRITE_SEQUENCER_376] = 0x2fff, | |
395 | [WM8915_WRITE_SEQUENCER_380] = 0x2fff, | |
396 | [WM8915_WRITE_SEQUENCER_384] = 0x60, | |
397 | [WM8915_WRITE_SEQUENCER_386] = 0x601, | |
398 | [WM8915_WRITE_SEQUENCER_388] = 0x61, | |
399 | [WM8915_WRITE_SEQUENCER_390] = 0x601, | |
400 | [WM8915_WRITE_SEQUENCER_392] = 0x50, | |
401 | [WM8915_WRITE_SEQUENCER_394] = 0x300, | |
402 | [WM8915_WRITE_SEQUENCER_396] = 0x1, | |
403 | [WM8915_WRITE_SEQUENCER_398] = 0x304, | |
404 | [WM8915_WRITE_SEQUENCER_400] = 0x40, | |
405 | [WM8915_WRITE_SEQUENCER_402] = 0xf, | |
406 | [WM8915_WRITE_SEQUENCER_404] = 0x1, | |
407 | [WM8915_WRITE_SEQUENCER_407] = 0x100, | |
408 | }; | |
409 | ||
410 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0); | |
411 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); | |
412 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
413 | static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0); | |
414 | static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0); | |
415 | static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0); | |
416 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
417 | ||
418 | static const char *sidetone_hpf_text[] = { | |
419 | "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz" | |
420 | }; | |
421 | ||
422 | static const struct soc_enum sidetone_hpf = | |
423 | SOC_ENUM_SINGLE(WM8915_SIDETONE, 7, 6, sidetone_hpf_text); | |
424 | ||
425 | static const char *hpf_mode_text[] = { | |
426 | "HiFi", "Custom", "Voice" | |
427 | }; | |
428 | ||
429 | static const struct soc_enum dsp1tx_hpf_mode = | |
430 | SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 3, 3, hpf_mode_text); | |
431 | ||
432 | static const struct soc_enum dsp2tx_hpf_mode = | |
433 | SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 3, 3, hpf_mode_text); | |
434 | ||
435 | static const char *hpf_cutoff_text[] = { | |
436 | "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" | |
437 | }; | |
438 | ||
439 | static const struct soc_enum dsp1tx_hpf_cutoff = | |
440 | SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text); | |
441 | ||
442 | static const struct soc_enum dsp2tx_hpf_cutoff = | |
443 | SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text); | |
444 | ||
445 | static void wm8915_set_retune_mobile(struct snd_soc_codec *codec, int block) | |
446 | { | |
447 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
448 | struct wm8915_pdata *pdata = &wm8915->pdata; | |
449 | int base, best, best_val, save, i, cfg, iface; | |
450 | ||
451 | if (!wm8915->num_retune_mobile_texts) | |
452 | return; | |
453 | ||
454 | switch (block) { | |
455 | case 0: | |
456 | base = WM8915_DSP1_RX_EQ_GAINS_1; | |
457 | if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) & | |
458 | WM8915_DSP1RX_SRC) | |
459 | iface = 1; | |
460 | else | |
461 | iface = 0; | |
462 | break; | |
463 | case 1: | |
464 | base = WM8915_DSP1_RX_EQ_GAINS_2; | |
465 | if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) & | |
466 | WM8915_DSP2RX_SRC) | |
467 | iface = 1; | |
468 | else | |
469 | iface = 0; | |
470 | break; | |
471 | default: | |
472 | return; | |
473 | } | |
474 | ||
475 | /* Find the version of the currently selected configuration | |
476 | * with the nearest sample rate. */ | |
477 | cfg = wm8915->retune_mobile_cfg[block]; | |
478 | best = 0; | |
479 | best_val = INT_MAX; | |
480 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
481 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
482 | wm8915->retune_mobile_texts[cfg]) == 0 && | |
483 | abs(pdata->retune_mobile_cfgs[i].rate | |
484 | - wm8915->rx_rate[iface]) < best_val) { | |
485 | best = i; | |
486 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
487 | - wm8915->rx_rate[iface]); | |
488 | } | |
489 | } | |
490 | ||
491 | dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", | |
492 | block, | |
493 | pdata->retune_mobile_cfgs[best].name, | |
494 | pdata->retune_mobile_cfgs[best].rate, | |
495 | wm8915->rx_rate[iface]); | |
496 | ||
497 | /* The EQ will be disabled while reconfiguring it, remember the | |
498 | * current configuration. | |
499 | */ | |
500 | save = snd_soc_read(codec, base); | |
501 | save &= WM8915_DSP1RX_EQ_ENA; | |
502 | ||
503 | for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++) | |
504 | snd_soc_update_bits(codec, base + i, 0xffff, | |
505 | pdata->retune_mobile_cfgs[best].regs[i]); | |
506 | ||
507 | snd_soc_update_bits(codec, base, WM8915_DSP1RX_EQ_ENA, save); | |
508 | } | |
509 | ||
510 | /* Icky as hell but saves code duplication */ | |
511 | static int wm8915_get_retune_mobile_block(const char *name) | |
512 | { | |
513 | if (strcmp(name, "DSP1 EQ Mode") == 0) | |
514 | return 0; | |
515 | if (strcmp(name, "DSP2 EQ Mode") == 0) | |
516 | return 1; | |
517 | return -EINVAL; | |
518 | } | |
519 | ||
520 | static int wm8915_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
521 | struct snd_ctl_elem_value *ucontrol) | |
522 | { | |
523 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
524 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
525 | struct wm8915_pdata *pdata = &wm8915->pdata; | |
526 | int block = wm8915_get_retune_mobile_block(kcontrol->id.name); | |
527 | int value = ucontrol->value.integer.value[0]; | |
528 | ||
529 | if (block < 0) | |
530 | return block; | |
531 | ||
532 | if (value >= pdata->num_retune_mobile_cfgs) | |
533 | return -EINVAL; | |
534 | ||
535 | wm8915->retune_mobile_cfg[block] = value; | |
536 | ||
537 | wm8915_set_retune_mobile(codec, block); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | static int wm8915_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
543 | struct snd_ctl_elem_value *ucontrol) | |
544 | { | |
545 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
546 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
547 | int block = wm8915_get_retune_mobile_block(kcontrol->id.name); | |
548 | ||
549 | ucontrol->value.enumerated.item[0] = wm8915->retune_mobile_cfg[block]; | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | static const struct snd_kcontrol_new wm8915_snd_controls[] = { | |
555 | SOC_DOUBLE_R_TLV("Capture Volume", WM8915_LEFT_LINE_INPUT_VOLUME, | |
556 | WM8915_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv), | |
557 | SOC_DOUBLE_R("Capture ZC Switch", WM8915_LEFT_LINE_INPUT_VOLUME, | |
558 | WM8915_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0), | |
559 | ||
560 | SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8915_DAC1_MIXER_VOLUMES, | |
561 | 0, 5, 24, 0, sidetone_tlv), | |
562 | SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8915_DAC2_MIXER_VOLUMES, | |
563 | 0, 5, 24, 0, sidetone_tlv), | |
564 | SOC_SINGLE("Sidetone LPF Switch", WM8915_SIDETONE, 12, 1, 0), | |
565 | SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf), | |
566 | SOC_SINGLE("Sidetone HPF Switch", WM8915_SIDETONE, 6, 1, 0), | |
567 | ||
568 | SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8915_DSP1_TX_LEFT_VOLUME, | |
569 | WM8915_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
570 | SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8915_DSP2_TX_LEFT_VOLUME, | |
571 | WM8915_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
572 | ||
573 | SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8915_DSP1_TX_FILTERS, | |
574 | 13, 1, 0), | |
575 | SOC_DOUBLE("DSP1 Capture HPF Switch", WM8915_DSP1_TX_FILTERS, 12, 11, 1, 0), | |
576 | SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode), | |
577 | SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff), | |
578 | ||
579 | SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8915_DSP2_TX_FILTERS, | |
580 | 13, 1, 0), | |
581 | SOC_DOUBLE("DSP2 Capture HPF Switch", WM8915_DSP2_TX_FILTERS, 12, 11, 1, 0), | |
582 | SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode), | |
583 | SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff), | |
584 | ||
585 | SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8915_DSP1_RX_LEFT_VOLUME, | |
586 | WM8915_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), | |
587 | SOC_SINGLE("DSP1 Playback Switch", WM8915_DSP1_RX_FILTERS_1, 9, 1, 1), | |
588 | ||
589 | SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8915_DSP2_RX_LEFT_VOLUME, | |
590 | WM8915_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), | |
591 | SOC_SINGLE("DSP2 Playback Switch", WM8915_DSP2_RX_FILTERS_1, 9, 1, 1), | |
592 | ||
593 | SOC_DOUBLE_R_TLV("DAC1 Volume", WM8915_DAC1_LEFT_VOLUME, | |
594 | WM8915_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv), | |
595 | SOC_DOUBLE_R("DAC1 Switch", WM8915_DAC1_LEFT_VOLUME, | |
596 | WM8915_DAC1_RIGHT_VOLUME, 9, 1, 1), | |
597 | ||
598 | SOC_DOUBLE_R_TLV("DAC2 Volume", WM8915_DAC2_LEFT_VOLUME, | |
599 | WM8915_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv), | |
600 | SOC_DOUBLE_R("DAC2 Switch", WM8915_DAC2_LEFT_VOLUME, | |
601 | WM8915_DAC2_RIGHT_VOLUME, 9, 1, 1), | |
602 | ||
603 | SOC_SINGLE("Speaker High Performance Switch", WM8915_OVERSAMPLING, 3, 1, 0), | |
604 | SOC_SINGLE("DMIC High Performance Switch", WM8915_OVERSAMPLING, 2, 1, 0), | |
605 | SOC_SINGLE("ADC High Performance Switch", WM8915_OVERSAMPLING, 1, 1, 0), | |
606 | SOC_SINGLE("DAC High Performance Switch", WM8915_OVERSAMPLING, 0, 1, 0), | |
607 | ||
608 | SOC_SINGLE("DAC Soft Mute Switch", WM8915_DAC_SOFTMUTE, 1, 1, 0), | |
609 | SOC_SINGLE("DAC Slow Soft Mute Switch", WM8915_DAC_SOFTMUTE, 0, 1, 0), | |
610 | ||
611 | SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8915_DAC1_HPOUT1_VOLUME, 0, 4, | |
612 | 8, 0, out_digital_tlv), | |
613 | SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8915_DAC2_HPOUT2_VOLUME, 0, 4, | |
614 | 8, 0, out_digital_tlv), | |
615 | ||
616 | SOC_DOUBLE_R_TLV("Output 1 Volume", WM8915_OUTPUT1_LEFT_VOLUME, | |
617 | WM8915_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv), | |
618 | SOC_DOUBLE_R("Output 1 ZC Switch", WM8915_OUTPUT1_LEFT_VOLUME, | |
619 | WM8915_OUTPUT1_RIGHT_VOLUME, 7, 1, 0), | |
620 | ||
621 | SOC_DOUBLE_R_TLV("Output 2 Volume", WM8915_OUTPUT2_LEFT_VOLUME, | |
622 | WM8915_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv), | |
623 | SOC_DOUBLE_R("Output 2 ZC Switch", WM8915_OUTPUT2_LEFT_VOLUME, | |
624 | WM8915_OUTPUT2_RIGHT_VOLUME, 7, 1, 0), | |
625 | ||
626 | SOC_DOUBLE_TLV("Speaker Volume", WM8915_PDM_SPEAKER_VOLUME, 0, 4, 8, 0, | |
627 | spk_tlv), | |
628 | SOC_DOUBLE_R("Speaker Switch", WM8915_LEFT_PDM_SPEAKER, | |
629 | WM8915_RIGHT_PDM_SPEAKER, 3, 1, 1), | |
630 | SOC_DOUBLE_R("Speaker ZC Switch", WM8915_LEFT_PDM_SPEAKER, | |
631 | WM8915_RIGHT_PDM_SPEAKER, 2, 1, 0), | |
632 | ||
633 | SOC_SINGLE("DSP1 EQ Switch", WM8915_DSP1_RX_EQ_GAINS_1, 0, 1, 0), | |
634 | SOC_SINGLE("DSP2 EQ Switch", WM8915_DSP2_RX_EQ_GAINS_1, 0, 1, 0), | |
635 | }; | |
636 | ||
637 | static const struct snd_kcontrol_new wm8915_eq_controls[] = { | |
638 | SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 11, 31, 0, | |
639 | eq_tlv), | |
640 | SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 6, 31, 0, | |
641 | eq_tlv), | |
642 | SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 1, 31, 0, | |
643 | eq_tlv), | |
644 | SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 11, 31, 0, | |
645 | eq_tlv), | |
646 | SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 6, 31, 0, | |
647 | eq_tlv), | |
648 | ||
649 | SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 11, 31, 0, | |
650 | eq_tlv), | |
651 | SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 6, 31, 0, | |
652 | eq_tlv), | |
653 | SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 1, 31, 0, | |
654 | eq_tlv), | |
655 | SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 11, 31, 0, | |
656 | eq_tlv), | |
657 | SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 6, 31, 0, | |
658 | eq_tlv), | |
659 | }; | |
660 | ||
661 | static int cp_event(struct snd_soc_dapm_widget *w, | |
662 | struct snd_kcontrol *kcontrol, int event) | |
663 | { | |
664 | switch (event) { | |
665 | case SND_SOC_DAPM_POST_PMU: | |
666 | msleep(5); | |
667 | break; | |
668 | default: | |
669 | BUG(); | |
670 | return -EINVAL; | |
671 | } | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
676 | static int rmv_short_event(struct snd_soc_dapm_widget *w, | |
677 | struct snd_kcontrol *kcontrol, int event) | |
678 | { | |
679 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec); | |
680 | ||
681 | /* Record which outputs we enabled */ | |
682 | switch (event) { | |
683 | case SND_SOC_DAPM_PRE_PMD: | |
684 | wm8915->hpout_pending &= ~w->shift; | |
685 | break; | |
686 | case SND_SOC_DAPM_PRE_PMU: | |
687 | wm8915->hpout_pending |= w->shift; | |
688 | break; | |
689 | default: | |
690 | BUG(); | |
691 | return -EINVAL; | |
692 | } | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask) | |
698 | { | |
699 | struct i2c_client *i2c = to_i2c_client(codec->dev); | |
700 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
701 | int i, ret; | |
702 | unsigned long timeout = 200; | |
703 | ||
704 | snd_soc_write(codec, WM8915_DC_SERVO_2, mask); | |
705 | ||
706 | /* Use the interrupt if possible */ | |
707 | do { | |
708 | if (i2c->irq) { | |
709 | timeout = wait_for_completion_timeout(&wm8915->dcs_done, | |
710 | msecs_to_jiffies(200)); | |
711 | if (timeout == 0) | |
712 | dev_err(codec->dev, "DC servo timed out\n"); | |
713 | ||
714 | } else { | |
715 | msleep(1); | |
716 | if (--i) { | |
717 | timeout = 0; | |
718 | break; | |
719 | } | |
720 | } | |
721 | ||
722 | ret = snd_soc_read(codec, WM8915_DC_SERVO_2); | |
723 | dev_dbg(codec->dev, "DC servo state: %x\n", ret); | |
724 | } while (ret & mask); | |
725 | ||
726 | if (timeout == 0) | |
727 | dev_err(codec->dev, "DC servo timed out for %x\n", mask); | |
728 | else | |
729 | dev_dbg(codec->dev, "DC servo complete for %x\n", mask); | |
730 | } | |
731 | ||
732 | static void wm8915_seq_notifier(struct snd_soc_dapm_context *dapm, | |
733 | enum snd_soc_dapm_type event, int subseq) | |
734 | { | |
735 | struct snd_soc_codec *codec = container_of(dapm, | |
736 | struct snd_soc_codec, dapm); | |
737 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
738 | u16 val, mask; | |
739 | ||
740 | /* Complete any pending DC servo starts */ | |
741 | if (wm8915->dcs_pending) { | |
742 | dev_dbg(codec->dev, "Starting DC servo for %x\n", | |
743 | wm8915->dcs_pending); | |
744 | ||
745 | /* Trigger a startup sequence */ | |
746 | wait_for_dc_servo(codec, wm8915->dcs_pending | |
747 | << WM8915_DCS_TRIG_STARTUP_0_SHIFT); | |
748 | ||
749 | wm8915->dcs_pending = 0; | |
750 | } | |
751 | ||
752 | if (wm8915->hpout_pending != wm8915->hpout_ena) { | |
753 | dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n", | |
754 | wm8915->hpout_ena, wm8915->hpout_pending); | |
755 | ||
756 | val = 0; | |
757 | mask = 0; | |
758 | if (wm8915->hpout_pending & HPOUT1L) { | |
759 | val |= WM8915_HPOUT1L_RMV_SHORT; | |
760 | mask |= WM8915_HPOUT1L_RMV_SHORT; | |
761 | } else { | |
762 | mask |= WM8915_HPOUT1L_RMV_SHORT | | |
763 | WM8915_HPOUT1L_OUTP | | |
764 | WM8915_HPOUT1L_DLY; | |
765 | } | |
766 | ||
767 | if (wm8915->hpout_pending & HPOUT1R) { | |
768 | val |= WM8915_HPOUT1R_RMV_SHORT; | |
769 | mask |= WM8915_HPOUT1R_RMV_SHORT; | |
770 | } else { | |
771 | mask |= WM8915_HPOUT1R_RMV_SHORT | | |
772 | WM8915_HPOUT1R_OUTP | | |
773 | WM8915_HPOUT1R_DLY; | |
774 | } | |
775 | ||
776 | snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_1, mask, val); | |
777 | ||
778 | val = 0; | |
779 | mask = 0; | |
780 | if (wm8915->hpout_pending & HPOUT2L) { | |
781 | val |= WM8915_HPOUT2L_RMV_SHORT; | |
782 | mask |= WM8915_HPOUT2L_RMV_SHORT; | |
783 | } else { | |
784 | mask |= WM8915_HPOUT2L_RMV_SHORT | | |
785 | WM8915_HPOUT2L_OUTP | | |
786 | WM8915_HPOUT2L_DLY; | |
787 | } | |
788 | ||
789 | if (wm8915->hpout_pending & HPOUT2R) { | |
790 | val |= WM8915_HPOUT2R_RMV_SHORT; | |
791 | mask |= WM8915_HPOUT2R_RMV_SHORT; | |
792 | } else { | |
793 | mask |= WM8915_HPOUT2R_RMV_SHORT | | |
794 | WM8915_HPOUT2R_OUTP | | |
795 | WM8915_HPOUT2R_DLY; | |
796 | } | |
797 | ||
798 | snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_2, mask, val); | |
799 | ||
800 | wm8915->hpout_ena = wm8915->hpout_pending; | |
801 | } | |
802 | } | |
803 | ||
804 | static int dcs_start(struct snd_soc_dapm_widget *w, | |
805 | struct snd_kcontrol *kcontrol, int event) | |
806 | { | |
807 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec); | |
808 | ||
809 | switch (event) { | |
810 | case SND_SOC_DAPM_POST_PMU: | |
811 | wm8915->dcs_pending |= 1 << w->shift; | |
812 | break; | |
813 | default: | |
814 | BUG(); | |
815 | return -EINVAL; | |
816 | } | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | static const char *sidetone_text[] = { | |
822 | "IN1", "IN2", | |
823 | }; | |
824 | ||
825 | static const struct soc_enum left_sidetone_enum = | |
826 | SOC_ENUM_SINGLE(WM8915_SIDETONE, 0, 2, sidetone_text); | |
827 | ||
828 | static const struct snd_kcontrol_new left_sidetone = | |
829 | SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum); | |
830 | ||
831 | static const struct soc_enum right_sidetone_enum = | |
832 | SOC_ENUM_SINGLE(WM8915_SIDETONE, 1, 2, sidetone_text); | |
833 | ||
834 | static const struct snd_kcontrol_new right_sidetone = | |
835 | SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum); | |
836 | ||
837 | static const char *spk_text[] = { | |
838 | "DAC1L", "DAC1R", "DAC2L", "DAC2R" | |
839 | }; | |
840 | ||
841 | static const struct soc_enum spkl_enum = | |
842 | SOC_ENUM_SINGLE(WM8915_LEFT_PDM_SPEAKER, 0, 4, spk_text); | |
843 | ||
844 | static const struct snd_kcontrol_new spkl_mux = | |
845 | SOC_DAPM_ENUM("SPKL", spkl_enum); | |
846 | ||
847 | static const struct soc_enum spkr_enum = | |
848 | SOC_ENUM_SINGLE(WM8915_RIGHT_PDM_SPEAKER, 0, 4, spk_text); | |
849 | ||
850 | static const struct snd_kcontrol_new spkr_mux = | |
851 | SOC_DAPM_ENUM("SPKR", spkr_enum); | |
852 | ||
853 | static const char *dsp1rx_text[] = { | |
854 | "AIF1", "AIF2" | |
855 | }; | |
856 | ||
857 | static const struct soc_enum dsp1rx_enum = | |
858 | SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text); | |
859 | ||
860 | static const struct snd_kcontrol_new dsp1rx = | |
861 | SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); | |
862 | ||
863 | static const char *dsp2rx_text[] = { | |
864 | "AIF2", "AIF1" | |
865 | }; | |
866 | ||
867 | static const struct soc_enum dsp2rx_enum = | |
868 | SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text); | |
869 | ||
870 | static const struct snd_kcontrol_new dsp2rx = | |
871 | SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); | |
872 | ||
873 | static const char *aif2tx_text[] = { | |
874 | "DSP2", "DSP1", "AIF1" | |
875 | }; | |
876 | ||
877 | static const struct soc_enum aif2tx_enum = | |
878 | SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 6, 3, aif2tx_text); | |
879 | ||
880 | static const struct snd_kcontrol_new aif2tx = | |
881 | SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); | |
882 | ||
883 | static const char *inmux_text[] = { | |
884 | "ADC", "DMIC1", "DMIC2" | |
885 | }; | |
886 | ||
887 | static const struct soc_enum in1_enum = | |
888 | SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 0, 3, inmux_text); | |
889 | ||
890 | static const struct snd_kcontrol_new in1_mux = | |
891 | SOC_DAPM_ENUM("IN1 Mux", in1_enum); | |
892 | ||
893 | static const struct soc_enum in2_enum = | |
894 | SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 4, 3, inmux_text); | |
895 | ||
896 | static const struct snd_kcontrol_new in2_mux = | |
897 | SOC_DAPM_ENUM("IN2 Mux", in2_enum); | |
898 | ||
899 | static const struct snd_kcontrol_new dac2r_mix[] = { | |
900 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, | |
901 | 5, 1, 0), | |
902 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, | |
903 | 4, 1, 0), | |
904 | SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0), | |
905 | SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0), | |
906 | }; | |
907 | ||
908 | static const struct snd_kcontrol_new dac2l_mix[] = { | |
909 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, | |
910 | 5, 1, 0), | |
911 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, | |
912 | 4, 1, 0), | |
913 | SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0), | |
914 | SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0), | |
915 | }; | |
916 | ||
917 | static const struct snd_kcontrol_new dac1r_mix[] = { | |
918 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, | |
919 | 5, 1, 0), | |
920 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, | |
921 | 4, 1, 0), | |
922 | SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0), | |
923 | SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0), | |
924 | }; | |
925 | ||
926 | static const struct snd_kcontrol_new dac1l_mix[] = { | |
927 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, | |
928 | 5, 1, 0), | |
929 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, | |
930 | 4, 1, 0), | |
931 | SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0), | |
932 | SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0), | |
933 | }; | |
934 | ||
935 | static const struct snd_kcontrol_new dsp1txl[] = { | |
936 | SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING, | |
937 | 1, 1, 0), | |
938 | SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING, | |
939 | 0, 1, 0), | |
940 | }; | |
941 | ||
942 | static const struct snd_kcontrol_new dsp1txr[] = { | |
943 | SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING, | |
944 | 1, 1, 0), | |
945 | SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING, | |
946 | 0, 1, 0), | |
947 | }; | |
948 | ||
949 | static const struct snd_kcontrol_new dsp2txl[] = { | |
950 | SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING, | |
951 | 1, 1, 0), | |
952 | SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING, | |
953 | 0, 1, 0), | |
954 | }; | |
955 | ||
956 | static const struct snd_kcontrol_new dsp2txr[] = { | |
957 | SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING, | |
958 | 1, 1, 0), | |
959 | SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING, | |
960 | 0, 1, 0), | |
961 | }; | |
962 | ||
963 | ||
964 | static const struct snd_soc_dapm_widget wm8915_dapm_widgets[] = { | |
965 | SND_SOC_DAPM_INPUT("IN1LN"), | |
966 | SND_SOC_DAPM_INPUT("IN1LP"), | |
967 | SND_SOC_DAPM_INPUT("IN1RN"), | |
968 | SND_SOC_DAPM_INPUT("IN1RP"), | |
969 | ||
970 | SND_SOC_DAPM_INPUT("IN2LN"), | |
971 | SND_SOC_DAPM_INPUT("IN2LP"), | |
972 | SND_SOC_DAPM_INPUT("IN2RN"), | |
973 | SND_SOC_DAPM_INPUT("IN2RP"), | |
974 | ||
975 | SND_SOC_DAPM_INPUT("DMIC1DAT"), | |
976 | SND_SOC_DAPM_INPUT("DMIC2DAT"), | |
977 | ||
978 | SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8915_AIF_CLOCKING_1, 0, 0, NULL, 0), | |
979 | SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8915_CLOCKING_1, 1, 0, NULL, 0), | |
980 | SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8915_CLOCKING_1, 2, 0, NULL, 0), | |
981 | SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8915_CHARGE_PUMP_1, 15, 0, cp_event, | |
982 | SND_SOC_DAPM_POST_PMU), | |
983 | ||
984 | SND_SOC_DAPM_SUPPLY("LDO2", WM8915_POWER_MANAGEMENT_2, 1, 0, NULL, 0), | |
985 | SND_SOC_DAPM_MICBIAS("MICB2", WM8915_POWER_MANAGEMENT_1, 9, 0), | |
986 | SND_SOC_DAPM_MICBIAS("MICB1", WM8915_POWER_MANAGEMENT_1, 8, 0), | |
987 | ||
988 | SND_SOC_DAPM_PGA("IN1L PGA", WM8915_POWER_MANAGEMENT_2, 5, 0, NULL, 0), | |
989 | SND_SOC_DAPM_PGA("IN1R PGA", WM8915_POWER_MANAGEMENT_2, 4, 0, NULL, 0), | |
990 | ||
abc9d5aa MB |
991 | SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &in1_mux), |
992 | SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &in1_mux), | |
993 | SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &in2_mux), | |
994 | SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &in2_mux), | |
c93993ac MB |
995 | |
996 | SND_SOC_DAPM_PGA("IN1L", WM8915_POWER_MANAGEMENT_7, 2, 0, NULL, 0), | |
997 | SND_SOC_DAPM_PGA("IN1R", WM8915_POWER_MANAGEMENT_7, 3, 0, NULL, 0), | |
998 | SND_SOC_DAPM_PGA("IN2L", WM8915_POWER_MANAGEMENT_7, 6, 0, NULL, 0), | |
999 | SND_SOC_DAPM_PGA("IN2R", WM8915_POWER_MANAGEMENT_7, 7, 0, NULL, 0), | |
1000 | ||
c93993ac MB |
1001 | SND_SOC_DAPM_SUPPLY("DMIC2", WM8915_POWER_MANAGEMENT_7, 9, 0, NULL, 0), |
1002 | SND_SOC_DAPM_SUPPLY("DMIC1", WM8915_POWER_MANAGEMENT_7, 8, 0, NULL, 0), | |
1003 | ||
1004 | SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8915_POWER_MANAGEMENT_3, 5, 0), | |
1005 | SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8915_POWER_MANAGEMENT_3, 4, 0), | |
1006 | SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8915_POWER_MANAGEMENT_3, 3, 0), | |
1007 | SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8915_POWER_MANAGEMENT_3, 2, 0), | |
1008 | ||
1009 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8915_POWER_MANAGEMENT_3, 1, 0), | |
1010 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8915_POWER_MANAGEMENT_3, 0, 0), | |
1011 | ||
1012 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone), | |
1013 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone), | |
1014 | ||
1015 | SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 11, 0), | |
1016 | SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 10, 0), | |
1017 | SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 9, 0), | |
1018 | SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 8, 0), | |
1019 | ||
1020 | SND_SOC_DAPM_MIXER("DSP2TXL", WM8915_POWER_MANAGEMENT_5, 11, 0, | |
1021 | dsp2txl, ARRAY_SIZE(dsp2txl)), | |
1022 | SND_SOC_DAPM_MIXER("DSP2TXR", WM8915_POWER_MANAGEMENT_5, 10, 0, | |
1023 | dsp2txr, ARRAY_SIZE(dsp2txr)), | |
1024 | SND_SOC_DAPM_MIXER("DSP1TXL", WM8915_POWER_MANAGEMENT_5, 9, 0, | |
1025 | dsp1txl, ARRAY_SIZE(dsp1txl)), | |
1026 | SND_SOC_DAPM_MIXER("DSP1TXR", WM8915_POWER_MANAGEMENT_5, 8, 0, | |
1027 | dsp1txr, ARRAY_SIZE(dsp1txr)), | |
1028 | ||
1029 | SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0, | |
1030 | dac2l_mix, ARRAY_SIZE(dac2l_mix)), | |
1031 | SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0, | |
1032 | dac2r_mix, ARRAY_SIZE(dac2r_mix)), | |
1033 | SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, | |
1034 | dac1l_mix, ARRAY_SIZE(dac1l_mix)), | |
1035 | SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, | |
1036 | dac1r_mix, ARRAY_SIZE(dac1r_mix)), | |
1037 | ||
1038 | SND_SOC_DAPM_DAC("DAC2L", NULL, WM8915_POWER_MANAGEMENT_5, 3, 0), | |
1039 | SND_SOC_DAPM_DAC("DAC2R", NULL, WM8915_POWER_MANAGEMENT_5, 2, 0), | |
1040 | SND_SOC_DAPM_DAC("DAC1L", NULL, WM8915_POWER_MANAGEMENT_5, 1, 0), | |
1041 | SND_SOC_DAPM_DAC("DAC1R", NULL, WM8915_POWER_MANAGEMENT_5, 0, 0), | |
1042 | ||
1043 | SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1, | |
1044 | WM8915_POWER_MANAGEMENT_4, 9, 0), | |
1045 | SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2, | |
1046 | WM8915_POWER_MANAGEMENT_4, 8, 0), | |
1047 | ||
1048 | SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1, | |
1049 | WM8915_POWER_MANAGEMENT_6, 9, 0), | |
1050 | SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2, | |
1051 | WM8915_POWER_MANAGEMENT_6, 8, 0), | |
1052 | ||
1053 | SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5, | |
1054 | WM8915_POWER_MANAGEMENT_4, 5, 0), | |
1055 | SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4, | |
1056 | WM8915_POWER_MANAGEMENT_4, 4, 0), | |
1057 | SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3, | |
1058 | WM8915_POWER_MANAGEMENT_4, 3, 0), | |
1059 | SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2, | |
1060 | WM8915_POWER_MANAGEMENT_4, 2, 0), | |
1061 | SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1, | |
1062 | WM8915_POWER_MANAGEMENT_4, 1, 0), | |
1063 | SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0, | |
1064 | WM8915_POWER_MANAGEMENT_4, 0, 0), | |
1065 | ||
1066 | SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5, | |
1067 | WM8915_POWER_MANAGEMENT_6, 5, 0), | |
1068 | SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4, | |
1069 | WM8915_POWER_MANAGEMENT_6, 4, 0), | |
1070 | SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3, | |
1071 | WM8915_POWER_MANAGEMENT_6, 3, 0), | |
1072 | SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2, | |
1073 | WM8915_POWER_MANAGEMENT_6, 2, 0), | |
1074 | SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1, | |
1075 | WM8915_POWER_MANAGEMENT_6, 1, 0), | |
1076 | SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0, | |
1077 | WM8915_POWER_MANAGEMENT_6, 0, 0), | |
1078 | ||
1079 | /* We route as stereo pairs so define some dummy widgets to squash | |
1080 | * things down for now. RXA = 0,1, RXB = 2,3 and so on */ | |
1081 | SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1082 | SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1083 | SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1084 | SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1085 | SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1086 | ||
1087 | SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx), | |
1088 | SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx), | |
1089 | SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx), | |
1090 | ||
1091 | SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux), | |
1092 | SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux), | |
1093 | SND_SOC_DAPM_PGA("SPKL PGA", WM8915_LEFT_PDM_SPEAKER, 4, 0, NULL, 0), | |
1094 | SND_SOC_DAPM_PGA("SPKR PGA", WM8915_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0), | |
1095 | ||
1096 | SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8915_POWER_MANAGEMENT_1, 7, 0, NULL, 0), | |
1097 | SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8915_ANALOGUE_HP_2, 5, 0, NULL, 0), | |
1098 | SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8915_DC_SERVO_1, 2, 0, dcs_start, | |
1099 | SND_SOC_DAPM_POST_PMU), | |
1100 | SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8915_ANALOGUE_HP_2, 6, 0, NULL, 0), | |
1101 | SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0, | |
1102 | rmv_short_event, | |
1103 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
1104 | ||
1105 | SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8915_POWER_MANAGEMENT_1, 6, 0,NULL, 0), | |
1106 | SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8915_ANALOGUE_HP_2, 1, 0, NULL, 0), | |
1107 | SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8915_DC_SERVO_1, 3, 0, dcs_start, | |
1108 | SND_SOC_DAPM_POST_PMU), | |
1109 | SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8915_ANALOGUE_HP_2, 2, 0, NULL, 0), | |
1110 | SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0, | |
1111 | rmv_short_event, | |
1112 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
1113 | ||
1114 | SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8915_POWER_MANAGEMENT_1, 5, 0, NULL, 0), | |
1115 | SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8915_ANALOGUE_HP_1, 5, 0, NULL, 0), | |
1116 | SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8915_DC_SERVO_1, 0, 0, dcs_start, | |
1117 | SND_SOC_DAPM_POST_PMU), | |
1118 | SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8915_ANALOGUE_HP_1, 6, 0, NULL, 0), | |
1119 | SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0, | |
1120 | rmv_short_event, | |
1121 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
1122 | ||
1123 | SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8915_POWER_MANAGEMENT_1, 4, 0, NULL, 0), | |
1124 | SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8915_ANALOGUE_HP_1, 1, 0, NULL, 0), | |
1125 | SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8915_DC_SERVO_1, 1, 0, dcs_start, | |
1126 | SND_SOC_DAPM_POST_PMU), | |
1127 | SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8915_ANALOGUE_HP_1, 2, 0, NULL, 0), | |
1128 | SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0, | |
1129 | rmv_short_event, | |
1130 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
1131 | ||
1132 | SND_SOC_DAPM_OUTPUT("HPOUT1L"), | |
1133 | SND_SOC_DAPM_OUTPUT("HPOUT1R"), | |
1134 | SND_SOC_DAPM_OUTPUT("HPOUT2L"), | |
1135 | SND_SOC_DAPM_OUTPUT("HPOUT2R"), | |
1136 | SND_SOC_DAPM_OUTPUT("SPKDAT"), | |
1137 | }; | |
1138 | ||
1139 | static const struct snd_soc_dapm_route wm8915_dapm_routes[] = { | |
1140 | { "AIFCLK", NULL, "SYSCLK" }, | |
1141 | { "SYSDSPCLK", NULL, "SYSCLK" }, | |
1142 | { "Charge Pump", NULL, "SYSCLK" }, | |
1143 | ||
1144 | { "MICB1", NULL, "LDO2" }, | |
1145 | { "MICB2", NULL, "LDO2" }, | |
1146 | ||
1147 | { "IN1L PGA", NULL, "IN2LN" }, | |
1148 | { "IN1L PGA", NULL, "IN2LP" }, | |
1149 | { "IN1L PGA", NULL, "IN1LN" }, | |
1150 | { "IN1L PGA", NULL, "IN1LP" }, | |
1151 | ||
1152 | { "IN1R PGA", NULL, "IN2RN" }, | |
1153 | { "IN1R PGA", NULL, "IN2RP" }, | |
1154 | { "IN1R PGA", NULL, "IN1RN" }, | |
1155 | { "IN1R PGA", NULL, "IN1RP" }, | |
1156 | ||
1157 | { "ADCL", NULL, "IN1L PGA" }, | |
1158 | ||
1159 | { "ADCR", NULL, "IN1R PGA" }, | |
1160 | ||
1161 | { "DMIC1L", NULL, "DMIC1DAT" }, | |
1162 | { "DMIC1R", NULL, "DMIC1DAT" }, | |
1163 | { "DMIC2L", NULL, "DMIC2DAT" }, | |
1164 | { "DMIC2R", NULL, "DMIC2DAT" }, | |
1165 | ||
1166 | { "DMIC2L", NULL, "DMIC2" }, | |
1167 | { "DMIC2R", NULL, "DMIC2" }, | |
1168 | { "DMIC1L", NULL, "DMIC1" }, | |
1169 | { "DMIC1R", NULL, "DMIC1" }, | |
1170 | ||
abc9d5aa MB |
1171 | { "IN1L Mux", "ADC", "ADCL" }, |
1172 | { "IN1L Mux", "DMIC1", "DMIC1L" }, | |
1173 | { "IN1L Mux", "DMIC2", "DMIC2L" }, | |
1174 | ||
1175 | { "IN1R Mux", "ADC", "ADCR" }, | |
1176 | { "IN1R Mux", "DMIC1", "DMIC1R" }, | |
1177 | { "IN1R Mux", "DMIC2", "DMIC2R" }, | |
c93993ac | 1178 | |
abc9d5aa MB |
1179 | { "IN2L Mux", "ADC", "ADCL" }, |
1180 | { "IN2L Mux", "DMIC1", "DMIC1L" }, | |
1181 | { "IN2L Mux", "DMIC2", "DMIC2L" }, | |
c93993ac | 1182 | |
abc9d5aa MB |
1183 | { "IN2R Mux", "ADC", "ADCR" }, |
1184 | { "IN2R Mux", "DMIC1", "DMIC1R" }, | |
1185 | { "IN2R Mux", "DMIC2", "DMIC2R" }, | |
c93993ac | 1186 | |
abc9d5aa MB |
1187 | { "Left Sidetone", "IN1", "IN1L Mux" }, |
1188 | { "Left Sidetone", "IN2", "IN2L Mux" }, | |
c93993ac | 1189 | |
abc9d5aa MB |
1190 | { "Right Sidetone", "IN1", "IN1R Mux" }, |
1191 | { "Right Sidetone", "IN2", "IN2R Mux" }, | |
c93993ac | 1192 | |
abc9d5aa MB |
1193 | { "DSP1TXL", "IN1 Switch", "IN1L Mux" }, |
1194 | { "DSP1TXR", "IN1 Switch", "IN1R Mux" }, | |
c93993ac | 1195 | |
abc9d5aa MB |
1196 | { "DSP2TXL", "IN1 Switch", "IN2L Mux" }, |
1197 | { "DSP2TXR", "IN1 Switch", "IN2R Mux" }, | |
c93993ac MB |
1198 | |
1199 | { "AIF1TX0", NULL, "DSP1TXL" }, | |
1200 | { "AIF1TX1", NULL, "DSP1TXR" }, | |
1201 | { "AIF1TX2", NULL, "DSP2TXL" }, | |
1202 | { "AIF1TX3", NULL, "DSP2TXR" }, | |
1203 | { "AIF1TX4", NULL, "AIF2RX0" }, | |
1204 | { "AIF1TX5", NULL, "AIF2RX1" }, | |
1205 | ||
1206 | { "AIF1RX0", NULL, "AIFCLK" }, | |
1207 | { "AIF1RX1", NULL, "AIFCLK" }, | |
1208 | { "AIF1RX2", NULL, "AIFCLK" }, | |
1209 | { "AIF1RX3", NULL, "AIFCLK" }, | |
1210 | { "AIF1RX4", NULL, "AIFCLK" }, | |
1211 | { "AIF1RX5", NULL, "AIFCLK" }, | |
1212 | ||
1213 | { "AIF2RX0", NULL, "AIFCLK" }, | |
1214 | { "AIF2RX1", NULL, "AIFCLK" }, | |
1215 | ||
1216 | { "DSP1RXL", NULL, "SYSDSPCLK" }, | |
1217 | { "DSP1RXR", NULL, "SYSDSPCLK" }, | |
1218 | { "DSP2RXL", NULL, "SYSDSPCLK" }, | |
1219 | { "DSP2RXR", NULL, "SYSDSPCLK" }, | |
1220 | { "DSP1TXL", NULL, "SYSDSPCLK" }, | |
1221 | { "DSP1TXR", NULL, "SYSDSPCLK" }, | |
1222 | { "DSP2TXL", NULL, "SYSDSPCLK" }, | |
1223 | { "DSP2TXR", NULL, "SYSDSPCLK" }, | |
1224 | ||
1225 | { "AIF1RXA", NULL, "AIF1RX0" }, | |
1226 | { "AIF1RXA", NULL, "AIF1RX1" }, | |
1227 | { "AIF1RXB", NULL, "AIF1RX2" }, | |
1228 | { "AIF1RXB", NULL, "AIF1RX3" }, | |
1229 | { "AIF1RXC", NULL, "AIF1RX4" }, | |
1230 | { "AIF1RXC", NULL, "AIF1RX5" }, | |
1231 | ||
1232 | { "AIF2RX", NULL, "AIF2RX0" }, | |
1233 | { "AIF2RX", NULL, "AIF2RX1" }, | |
1234 | ||
1235 | { "AIF2TX", "DSP2", "DSP2TX" }, | |
1236 | { "AIF2TX", "DSP1", "DSP1RX" }, | |
1237 | { "AIF2TX", "AIF1", "AIF1RXC" }, | |
1238 | ||
1239 | { "DSP1RXL", NULL, "DSP1RX" }, | |
1240 | { "DSP1RXR", NULL, "DSP1RX" }, | |
1241 | { "DSP2RXL", NULL, "DSP2RX" }, | |
1242 | { "DSP2RXR", NULL, "DSP2RX" }, | |
1243 | ||
1244 | { "DSP2TX", NULL, "DSP2TXL" }, | |
1245 | { "DSP2TX", NULL, "DSP2TXR" }, | |
1246 | ||
1247 | { "DSP1RX", "AIF1", "AIF1RXA" }, | |
1248 | { "DSP1RX", "AIF2", "AIF2RX" }, | |
1249 | ||
1250 | { "DSP2RX", "AIF1", "AIF1RXB" }, | |
1251 | { "DSP2RX", "AIF2", "AIF2RX" }, | |
1252 | ||
1253 | { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" }, | |
1254 | { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" }, | |
1255 | { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1256 | { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1257 | ||
1258 | { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" }, | |
1259 | { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" }, | |
1260 | { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1261 | { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1262 | ||
1263 | { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" }, | |
1264 | { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" }, | |
1265 | { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1266 | { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1267 | ||
1268 | { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" }, | |
1269 | { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" }, | |
1270 | { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1271 | { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1272 | ||
1273 | { "DAC1L", NULL, "DAC1L Mixer" }, | |
1274 | { "DAC1R", NULL, "DAC1R Mixer" }, | |
1275 | { "DAC2L", NULL, "DAC2L Mixer" }, | |
1276 | { "DAC2R", NULL, "DAC2R Mixer" }, | |
1277 | ||
1278 | { "HPOUT2L PGA", NULL, "Charge Pump" }, | |
1279 | { "HPOUT2L PGA", NULL, "DAC2L" }, | |
1280 | { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" }, | |
1281 | { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" }, | |
1282 | { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" }, | |
1283 | { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" }, | |
1284 | ||
1285 | { "HPOUT2R PGA", NULL, "Charge Pump" }, | |
1286 | { "HPOUT2R PGA", NULL, "DAC2R" }, | |
1287 | { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" }, | |
1288 | { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" }, | |
1289 | { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" }, | |
1290 | { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" }, | |
1291 | ||
1292 | { "HPOUT1L PGA", NULL, "Charge Pump" }, | |
1293 | { "HPOUT1L PGA", NULL, "DAC1L" }, | |
1294 | { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" }, | |
1295 | { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" }, | |
1296 | { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" }, | |
1297 | { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" }, | |
1298 | ||
1299 | { "HPOUT1R PGA", NULL, "Charge Pump" }, | |
1300 | { "HPOUT1R PGA", NULL, "DAC1R" }, | |
1301 | { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" }, | |
1302 | { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" }, | |
1303 | { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" }, | |
1304 | { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" }, | |
1305 | ||
1306 | { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" }, | |
1307 | { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" }, | |
1308 | { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" }, | |
1309 | { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" }, | |
1310 | ||
1311 | { "SPKL", "DAC1L", "DAC1L" }, | |
1312 | { "SPKL", "DAC1R", "DAC1R" }, | |
1313 | { "SPKL", "DAC2L", "DAC2L" }, | |
1314 | { "SPKL", "DAC2R", "DAC2R" }, | |
1315 | ||
1316 | { "SPKR", "DAC1L", "DAC1L" }, | |
1317 | { "SPKR", "DAC1R", "DAC1R" }, | |
1318 | { "SPKR", "DAC2L", "DAC2L" }, | |
1319 | { "SPKR", "DAC2R", "DAC2R" }, | |
1320 | ||
1321 | { "SPKL PGA", NULL, "SPKL" }, | |
1322 | { "SPKR PGA", NULL, "SPKR" }, | |
1323 | ||
1324 | { "SPKDAT", NULL, "SPKL PGA" }, | |
1325 | { "SPKDAT", NULL, "SPKR PGA" }, | |
1326 | }; | |
1327 | ||
1328 | static int wm8915_readable_register(struct snd_soc_codec *codec, | |
1329 | unsigned int reg) | |
1330 | { | |
1331 | /* Due to the sparseness of the register map the compiler | |
1332 | * output from an explicit switch statement ends up being much | |
1333 | * more efficient than a table. | |
1334 | */ | |
1335 | switch (reg) { | |
1336 | case WM8915_SOFTWARE_RESET: | |
1337 | case WM8915_POWER_MANAGEMENT_1: | |
1338 | case WM8915_POWER_MANAGEMENT_2: | |
1339 | case WM8915_POWER_MANAGEMENT_3: | |
1340 | case WM8915_POWER_MANAGEMENT_4: | |
1341 | case WM8915_POWER_MANAGEMENT_5: | |
1342 | case WM8915_POWER_MANAGEMENT_6: | |
1343 | case WM8915_POWER_MANAGEMENT_7: | |
1344 | case WM8915_POWER_MANAGEMENT_8: | |
1345 | case WM8915_LEFT_LINE_INPUT_VOLUME: | |
1346 | case WM8915_RIGHT_LINE_INPUT_VOLUME: | |
1347 | case WM8915_LINE_INPUT_CONTROL: | |
1348 | case WM8915_DAC1_HPOUT1_VOLUME: | |
1349 | case WM8915_DAC2_HPOUT2_VOLUME: | |
1350 | case WM8915_DAC1_LEFT_VOLUME: | |
1351 | case WM8915_DAC1_RIGHT_VOLUME: | |
1352 | case WM8915_DAC2_LEFT_VOLUME: | |
1353 | case WM8915_DAC2_RIGHT_VOLUME: | |
1354 | case WM8915_OUTPUT1_LEFT_VOLUME: | |
1355 | case WM8915_OUTPUT1_RIGHT_VOLUME: | |
1356 | case WM8915_OUTPUT2_LEFT_VOLUME: | |
1357 | case WM8915_OUTPUT2_RIGHT_VOLUME: | |
1358 | case WM8915_MICBIAS_1: | |
1359 | case WM8915_MICBIAS_2: | |
1360 | case WM8915_LDO_1: | |
1361 | case WM8915_LDO_2: | |
1362 | case WM8915_ACCESSORY_DETECT_MODE_1: | |
1363 | case WM8915_ACCESSORY_DETECT_MODE_2: | |
1364 | case WM8915_HEADPHONE_DETECT_1: | |
1365 | case WM8915_HEADPHONE_DETECT_2: | |
1366 | case WM8915_MIC_DETECT_1: | |
1367 | case WM8915_MIC_DETECT_2: | |
1368 | case WM8915_MIC_DETECT_3: | |
1369 | case WM8915_CHARGE_PUMP_1: | |
1370 | case WM8915_CHARGE_PUMP_2: | |
1371 | case WM8915_DC_SERVO_1: | |
1372 | case WM8915_DC_SERVO_2: | |
1373 | case WM8915_DC_SERVO_3: | |
1374 | case WM8915_DC_SERVO_5: | |
1375 | case WM8915_DC_SERVO_6: | |
1376 | case WM8915_DC_SERVO_7: | |
1377 | case WM8915_DC_SERVO_READBACK_0: | |
1378 | case WM8915_ANALOGUE_HP_1: | |
1379 | case WM8915_ANALOGUE_HP_2: | |
1380 | case WM8915_CHIP_REVISION: | |
1381 | case WM8915_CONTROL_INTERFACE_1: | |
1382 | case WM8915_WRITE_SEQUENCER_CTRL_1: | |
1383 | case WM8915_WRITE_SEQUENCER_CTRL_2: | |
1384 | case WM8915_AIF_CLOCKING_1: | |
1385 | case WM8915_AIF_CLOCKING_2: | |
1386 | case WM8915_CLOCKING_1: | |
1387 | case WM8915_CLOCKING_2: | |
1388 | case WM8915_AIF_RATE: | |
1389 | case WM8915_FLL_CONTROL_1: | |
1390 | case WM8915_FLL_CONTROL_2: | |
1391 | case WM8915_FLL_CONTROL_3: | |
1392 | case WM8915_FLL_CONTROL_4: | |
1393 | case WM8915_FLL_CONTROL_5: | |
1394 | case WM8915_FLL_CONTROL_6: | |
1395 | case WM8915_FLL_EFS_1: | |
1396 | case WM8915_FLL_EFS_2: | |
1397 | case WM8915_AIF1_CONTROL: | |
1398 | case WM8915_AIF1_BCLK: | |
1399 | case WM8915_AIF1_TX_LRCLK_1: | |
1400 | case WM8915_AIF1_TX_LRCLK_2: | |
1401 | case WM8915_AIF1_RX_LRCLK_1: | |
1402 | case WM8915_AIF1_RX_LRCLK_2: | |
1403 | case WM8915_AIF1TX_DATA_CONFIGURATION_1: | |
1404 | case WM8915_AIF1TX_DATA_CONFIGURATION_2: | |
1405 | case WM8915_AIF1RX_DATA_CONFIGURATION: | |
1406 | case WM8915_AIF1TX_CHANNEL_0_CONFIGURATION: | |
1407 | case WM8915_AIF1TX_CHANNEL_1_CONFIGURATION: | |
1408 | case WM8915_AIF1TX_CHANNEL_2_CONFIGURATION: | |
1409 | case WM8915_AIF1TX_CHANNEL_3_CONFIGURATION: | |
1410 | case WM8915_AIF1TX_CHANNEL_4_CONFIGURATION: | |
1411 | case WM8915_AIF1TX_CHANNEL_5_CONFIGURATION: | |
1412 | case WM8915_AIF1RX_CHANNEL_0_CONFIGURATION: | |
1413 | case WM8915_AIF1RX_CHANNEL_1_CONFIGURATION: | |
1414 | case WM8915_AIF1RX_CHANNEL_2_CONFIGURATION: | |
1415 | case WM8915_AIF1RX_CHANNEL_3_CONFIGURATION: | |
1416 | case WM8915_AIF1RX_CHANNEL_4_CONFIGURATION: | |
1417 | case WM8915_AIF1RX_CHANNEL_5_CONFIGURATION: | |
1418 | case WM8915_AIF1RX_MONO_CONFIGURATION: | |
1419 | case WM8915_AIF1TX_TEST: | |
1420 | case WM8915_AIF2_CONTROL: | |
1421 | case WM8915_AIF2_BCLK: | |
1422 | case WM8915_AIF2_TX_LRCLK_1: | |
1423 | case WM8915_AIF2_TX_LRCLK_2: | |
1424 | case WM8915_AIF2_RX_LRCLK_1: | |
1425 | case WM8915_AIF2_RX_LRCLK_2: | |
1426 | case WM8915_AIF2TX_DATA_CONFIGURATION_1: | |
1427 | case WM8915_AIF2TX_DATA_CONFIGURATION_2: | |
1428 | case WM8915_AIF2RX_DATA_CONFIGURATION: | |
1429 | case WM8915_AIF2TX_CHANNEL_0_CONFIGURATION: | |
1430 | case WM8915_AIF2TX_CHANNEL_1_CONFIGURATION: | |
1431 | case WM8915_AIF2RX_CHANNEL_0_CONFIGURATION: | |
1432 | case WM8915_AIF2RX_CHANNEL_1_CONFIGURATION: | |
1433 | case WM8915_AIF2RX_MONO_CONFIGURATION: | |
1434 | case WM8915_AIF2TX_TEST: | |
1435 | case WM8915_DSP1_TX_LEFT_VOLUME: | |
1436 | case WM8915_DSP1_TX_RIGHT_VOLUME: | |
1437 | case WM8915_DSP1_RX_LEFT_VOLUME: | |
1438 | case WM8915_DSP1_RX_RIGHT_VOLUME: | |
1439 | case WM8915_DSP1_TX_FILTERS: | |
1440 | case WM8915_DSP1_RX_FILTERS_1: | |
1441 | case WM8915_DSP1_RX_FILTERS_2: | |
1442 | case WM8915_DSP1_DRC_1: | |
1443 | case WM8915_DSP1_DRC_2: | |
1444 | case WM8915_DSP1_DRC_3: | |
1445 | case WM8915_DSP1_DRC_4: | |
1446 | case WM8915_DSP1_DRC_5: | |
1447 | case WM8915_DSP1_RX_EQ_GAINS_1: | |
1448 | case WM8915_DSP1_RX_EQ_GAINS_2: | |
1449 | case WM8915_DSP1_RX_EQ_BAND_1_A: | |
1450 | case WM8915_DSP1_RX_EQ_BAND_1_B: | |
1451 | case WM8915_DSP1_RX_EQ_BAND_1_PG: | |
1452 | case WM8915_DSP1_RX_EQ_BAND_2_A: | |
1453 | case WM8915_DSP1_RX_EQ_BAND_2_B: | |
1454 | case WM8915_DSP1_RX_EQ_BAND_2_C: | |
1455 | case WM8915_DSP1_RX_EQ_BAND_2_PG: | |
1456 | case WM8915_DSP1_RX_EQ_BAND_3_A: | |
1457 | case WM8915_DSP1_RX_EQ_BAND_3_B: | |
1458 | case WM8915_DSP1_RX_EQ_BAND_3_C: | |
1459 | case WM8915_DSP1_RX_EQ_BAND_3_PG: | |
1460 | case WM8915_DSP1_RX_EQ_BAND_4_A: | |
1461 | case WM8915_DSP1_RX_EQ_BAND_4_B: | |
1462 | case WM8915_DSP1_RX_EQ_BAND_4_C: | |
1463 | case WM8915_DSP1_RX_EQ_BAND_4_PG: | |
1464 | case WM8915_DSP1_RX_EQ_BAND_5_A: | |
1465 | case WM8915_DSP1_RX_EQ_BAND_5_B: | |
1466 | case WM8915_DSP1_RX_EQ_BAND_5_PG: | |
1467 | case WM8915_DSP2_TX_LEFT_VOLUME: | |
1468 | case WM8915_DSP2_TX_RIGHT_VOLUME: | |
1469 | case WM8915_DSP2_RX_LEFT_VOLUME: | |
1470 | case WM8915_DSP2_RX_RIGHT_VOLUME: | |
1471 | case WM8915_DSP2_TX_FILTERS: | |
1472 | case WM8915_DSP2_RX_FILTERS_1: | |
1473 | case WM8915_DSP2_RX_FILTERS_2: | |
1474 | case WM8915_DSP2_DRC_1: | |
1475 | case WM8915_DSP2_DRC_2: | |
1476 | case WM8915_DSP2_DRC_3: | |
1477 | case WM8915_DSP2_DRC_4: | |
1478 | case WM8915_DSP2_DRC_5: | |
1479 | case WM8915_DSP2_RX_EQ_GAINS_1: | |
1480 | case WM8915_DSP2_RX_EQ_GAINS_2: | |
1481 | case WM8915_DSP2_RX_EQ_BAND_1_A: | |
1482 | case WM8915_DSP2_RX_EQ_BAND_1_B: | |
1483 | case WM8915_DSP2_RX_EQ_BAND_1_PG: | |
1484 | case WM8915_DSP2_RX_EQ_BAND_2_A: | |
1485 | case WM8915_DSP2_RX_EQ_BAND_2_B: | |
1486 | case WM8915_DSP2_RX_EQ_BAND_2_C: | |
1487 | case WM8915_DSP2_RX_EQ_BAND_2_PG: | |
1488 | case WM8915_DSP2_RX_EQ_BAND_3_A: | |
1489 | case WM8915_DSP2_RX_EQ_BAND_3_B: | |
1490 | case WM8915_DSP2_RX_EQ_BAND_3_C: | |
1491 | case WM8915_DSP2_RX_EQ_BAND_3_PG: | |
1492 | case WM8915_DSP2_RX_EQ_BAND_4_A: | |
1493 | case WM8915_DSP2_RX_EQ_BAND_4_B: | |
1494 | case WM8915_DSP2_RX_EQ_BAND_4_C: | |
1495 | case WM8915_DSP2_RX_EQ_BAND_4_PG: | |
1496 | case WM8915_DSP2_RX_EQ_BAND_5_A: | |
1497 | case WM8915_DSP2_RX_EQ_BAND_5_B: | |
1498 | case WM8915_DSP2_RX_EQ_BAND_5_PG: | |
1499 | case WM8915_DAC1_MIXER_VOLUMES: | |
1500 | case WM8915_DAC1_LEFT_MIXER_ROUTING: | |
1501 | case WM8915_DAC1_RIGHT_MIXER_ROUTING: | |
1502 | case WM8915_DAC2_MIXER_VOLUMES: | |
1503 | case WM8915_DAC2_LEFT_MIXER_ROUTING: | |
1504 | case WM8915_DAC2_RIGHT_MIXER_ROUTING: | |
1505 | case WM8915_DSP1_TX_LEFT_MIXER_ROUTING: | |
1506 | case WM8915_DSP1_TX_RIGHT_MIXER_ROUTING: | |
1507 | case WM8915_DSP2_TX_LEFT_MIXER_ROUTING: | |
1508 | case WM8915_DSP2_TX_RIGHT_MIXER_ROUTING: | |
1509 | case WM8915_DSP_TX_MIXER_SELECT: | |
1510 | case WM8915_DAC_SOFTMUTE: | |
1511 | case WM8915_OVERSAMPLING: | |
1512 | case WM8915_SIDETONE: | |
1513 | case WM8915_GPIO_1: | |
1514 | case WM8915_GPIO_2: | |
1515 | case WM8915_GPIO_3: | |
1516 | case WM8915_GPIO_4: | |
1517 | case WM8915_GPIO_5: | |
1518 | case WM8915_PULL_CONTROL_1: | |
1519 | case WM8915_PULL_CONTROL_2: | |
1520 | case WM8915_INTERRUPT_STATUS_1: | |
1521 | case WM8915_INTERRUPT_STATUS_2: | |
1522 | case WM8915_INTERRUPT_RAW_STATUS_2: | |
1523 | case WM8915_INTERRUPT_STATUS_1_MASK: | |
1524 | case WM8915_INTERRUPT_STATUS_2_MASK: | |
1525 | case WM8915_INTERRUPT_CONTROL: | |
1526 | case WM8915_LEFT_PDM_SPEAKER: | |
1527 | case WM8915_RIGHT_PDM_SPEAKER: | |
1528 | case WM8915_PDM_SPEAKER_MUTE_SEQUENCE: | |
1529 | case WM8915_PDM_SPEAKER_VOLUME: | |
1530 | return 1; | |
1531 | default: | |
1532 | return 0; | |
1533 | } | |
1534 | } | |
1535 | ||
1536 | static int wm8915_volatile_register(struct snd_soc_codec *codec, | |
1537 | unsigned int reg) | |
1538 | { | |
1539 | switch (reg) { | |
1540 | case WM8915_SOFTWARE_RESET: | |
1541 | case WM8915_CHIP_REVISION: | |
1542 | case WM8915_LDO_1: | |
1543 | case WM8915_LDO_2: | |
1544 | case WM8915_INTERRUPT_STATUS_1: | |
1545 | case WM8915_INTERRUPT_STATUS_2: | |
1546 | case WM8915_INTERRUPT_RAW_STATUS_2: | |
1547 | case WM8915_DC_SERVO_READBACK_0: | |
1548 | case WM8915_DC_SERVO_2: | |
1549 | case WM8915_DC_SERVO_6: | |
1550 | case WM8915_DC_SERVO_7: | |
1551 | case WM8915_FLL_CONTROL_6: | |
1552 | case WM8915_MIC_DETECT_3: | |
1553 | case WM8915_HEADPHONE_DETECT_1: | |
1554 | case WM8915_HEADPHONE_DETECT_2: | |
1555 | return 1; | |
1556 | default: | |
1557 | return 0; | |
1558 | } | |
1559 | } | |
1560 | ||
1561 | static int wm8915_reset(struct snd_soc_codec *codec) | |
1562 | { | |
1563 | return snd_soc_write(codec, WM8915_SOFTWARE_RESET, 0x8915); | |
1564 | } | |
1565 | ||
6dffdea7 MB |
1566 | static const int bclk_divs[] = { |
1567 | 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96 | |
1568 | }; | |
1569 | ||
1570 | static void wm8915_update_bclk(struct snd_soc_codec *codec) | |
1571 | { | |
1572 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
1573 | int aif, best, cur_val, bclk_rate, bclk_reg, i; | |
1574 | ||
1575 | /* Don't bother if we're in a low frequency idle mode that | |
1576 | * can't support audio. | |
1577 | */ | |
1578 | if (wm8915->sysclk < 64000) | |
1579 | return; | |
1580 | ||
1581 | for (aif = 0; aif < WM8915_AIFS; aif++) { | |
1582 | switch (aif) { | |
1583 | case 0: | |
1584 | bclk_reg = WM8915_AIF1_BCLK; | |
1585 | break; | |
1586 | case 1: | |
1587 | bclk_reg = WM8915_AIF2_BCLK; | |
1588 | break; | |
1589 | } | |
1590 | ||
1591 | bclk_rate = wm8915->bclk_rate[aif]; | |
1592 | ||
1593 | /* Pick a divisor for BCLK as close as we can get to ideal */ | |
1594 | best = 0; | |
1595 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1596 | cur_val = (wm8915->sysclk / bclk_divs[i]) - bclk_rate; | |
1597 | if (cur_val < 0) /* BCLK table is sorted */ | |
1598 | break; | |
1599 | best = i; | |
1600 | } | |
1601 | bclk_rate = wm8915->sysclk / bclk_divs[best]; | |
1602 | dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", | |
1603 | bclk_divs[best], bclk_rate); | |
1604 | ||
1605 | snd_soc_update_bits(codec, bclk_reg, | |
1606 | WM8915_AIF1_BCLK_DIV_MASK, best); | |
1607 | } | |
1608 | } | |
1609 | ||
c93993ac MB |
1610 | static int wm8915_set_bias_level(struct snd_soc_codec *codec, |
1611 | enum snd_soc_bias_level level) | |
1612 | { | |
1613 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
1614 | int ret; | |
1615 | ||
1616 | switch (level) { | |
1617 | case SND_SOC_BIAS_ON: | |
1618 | break; | |
1619 | ||
1620 | case SND_SOC_BIAS_PREPARE: | |
1621 | if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { | |
1622 | snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1, | |
1623 | WM8915_BG_ENA, WM8915_BG_ENA); | |
1624 | msleep(2); | |
1625 | } | |
1626 | break; | |
1627 | ||
1628 | case SND_SOC_BIAS_STANDBY: | |
1629 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
1630 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies), | |
1631 | wm8915->supplies); | |
1632 | if (ret != 0) { | |
1633 | dev_err(codec->dev, | |
1634 | "Failed to enable supplies: %d\n", | |
1635 | ret); | |
1636 | return ret; | |
1637 | } | |
1638 | ||
1639 | if (wm8915->pdata.ldo_ena >= 0) { | |
1640 | gpio_set_value_cansleep(wm8915->pdata.ldo_ena, | |
1641 | 1); | |
1642 | msleep(5); | |
1643 | } | |
1644 | ||
1645 | codec->cache_only = false; | |
1646 | snd_soc_cache_sync(codec); | |
1647 | } | |
1648 | ||
1649 | snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1, | |
1650 | WM8915_BG_ENA, 0); | |
1651 | break; | |
1652 | ||
1653 | case SND_SOC_BIAS_OFF: | |
1654 | codec->cache_only = true; | |
1655 | if (wm8915->pdata.ldo_ena >= 0) | |
1656 | gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0); | |
1657 | regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), | |
1658 | wm8915->supplies); | |
1659 | break; | |
1660 | } | |
1661 | ||
1662 | codec->dapm.bias_level = level; | |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | static int wm8915_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1668 | { | |
1669 | struct snd_soc_codec *codec = dai->codec; | |
1670 | int aifctrl = 0; | |
1671 | int bclk = 0; | |
1672 | int lrclk_tx = 0; | |
1673 | int lrclk_rx = 0; | |
1674 | int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg; | |
1675 | ||
1676 | switch (dai->id) { | |
1677 | case 0: | |
1678 | aifctrl_reg = WM8915_AIF1_CONTROL; | |
1679 | bclk_reg = WM8915_AIF1_BCLK; | |
1680 | lrclk_tx_reg = WM8915_AIF1_TX_LRCLK_2; | |
1681 | lrclk_rx_reg = WM8915_AIF1_RX_LRCLK_2; | |
1682 | break; | |
1683 | case 1: | |
1684 | aifctrl_reg = WM8915_AIF2_CONTROL; | |
1685 | bclk_reg = WM8915_AIF2_BCLK; | |
1686 | lrclk_tx_reg = WM8915_AIF2_TX_LRCLK_2; | |
1687 | lrclk_rx_reg = WM8915_AIF2_RX_LRCLK_2; | |
1688 | break; | |
1689 | default: | |
1690 | BUG(); | |
1691 | return -EINVAL; | |
1692 | } | |
1693 | ||
1694 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1695 | case SND_SOC_DAIFMT_NB_NF: | |
1696 | break; | |
1697 | case SND_SOC_DAIFMT_IB_NF: | |
1698 | bclk |= WM8915_AIF1_BCLK_INV; | |
1699 | break; | |
1700 | case SND_SOC_DAIFMT_NB_IF: | |
1701 | lrclk_tx |= WM8915_AIF1TX_LRCLK_INV; | |
1702 | lrclk_rx |= WM8915_AIF1RX_LRCLK_INV; | |
1703 | break; | |
1704 | case SND_SOC_DAIFMT_IB_IF: | |
1705 | bclk |= WM8915_AIF1_BCLK_INV; | |
1706 | lrclk_tx |= WM8915_AIF1TX_LRCLK_INV; | |
1707 | lrclk_rx |= WM8915_AIF1RX_LRCLK_INV; | |
1708 | break; | |
1709 | } | |
1710 | ||
1711 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1712 | case SND_SOC_DAIFMT_CBS_CFS: | |
1713 | break; | |
1714 | case SND_SOC_DAIFMT_CBS_CFM: | |
1715 | lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR; | |
1716 | lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR; | |
1717 | break; | |
1718 | case SND_SOC_DAIFMT_CBM_CFS: | |
1719 | bclk |= WM8915_AIF1_BCLK_MSTR; | |
1720 | break; | |
1721 | case SND_SOC_DAIFMT_CBM_CFM: | |
1722 | bclk |= WM8915_AIF1_BCLK_MSTR; | |
1723 | lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR; | |
1724 | lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR; | |
1725 | break; | |
1726 | default: | |
1727 | return -EINVAL; | |
1728 | } | |
1729 | ||
1730 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1731 | case SND_SOC_DAIFMT_DSP_A: | |
1732 | break; | |
1733 | case SND_SOC_DAIFMT_DSP_B: | |
1734 | aifctrl |= 1; | |
1735 | break; | |
1736 | case SND_SOC_DAIFMT_I2S: | |
1737 | aifctrl |= 2; | |
1738 | break; | |
1739 | case SND_SOC_DAIFMT_LEFT_J: | |
1740 | aifctrl |= 3; | |
1741 | break; | |
1742 | default: | |
1743 | return -EINVAL; | |
1744 | } | |
1745 | ||
1746 | snd_soc_update_bits(codec, aifctrl_reg, WM8915_AIF1_FMT_MASK, aifctrl); | |
1747 | snd_soc_update_bits(codec, bclk_reg, | |
1748 | WM8915_AIF1_BCLK_INV | WM8915_AIF1_BCLK_MSTR, | |
1749 | bclk); | |
1750 | snd_soc_update_bits(codec, lrclk_tx_reg, | |
1751 | WM8915_AIF1TX_LRCLK_INV | | |
1752 | WM8915_AIF1TX_LRCLK_MSTR, | |
1753 | lrclk_tx); | |
1754 | snd_soc_update_bits(codec, lrclk_rx_reg, | |
1755 | WM8915_AIF1RX_LRCLK_INV | | |
1756 | WM8915_AIF1RX_LRCLK_MSTR, | |
1757 | lrclk_rx); | |
1758 | ||
1759 | return 0; | |
1760 | } | |
1761 | ||
c93993ac MB |
1762 | static const int dsp_divs[] = { |
1763 | 48000, 32000, 16000, 8000 | |
1764 | }; | |
1765 | ||
1766 | static int wm8915_hw_params(struct snd_pcm_substream *substream, | |
1767 | struct snd_pcm_hw_params *params, | |
1768 | struct snd_soc_dai *dai) | |
1769 | { | |
1770 | struct snd_soc_codec *codec = dai->codec; | |
1771 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
6dffdea7 | 1772 | int bits, i, bclk_rate; |
c93993ac | 1773 | int aifdata = 0; |
c93993ac MB |
1774 | int lrclk = 0; |
1775 | int dsp = 0; | |
6dffdea7 | 1776 | int aifdata_reg, lrclk_reg, dsp_shift; |
c93993ac MB |
1777 | |
1778 | switch (dai->id) { | |
1779 | case 0: | |
1780 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
1781 | (snd_soc_read(codec, WM8915_GPIO_1)) & WM8915_GP1_FN_MASK) { | |
1782 | aifdata_reg = WM8915_AIF1RX_DATA_CONFIGURATION; | |
1783 | lrclk_reg = WM8915_AIF1_RX_LRCLK_1; | |
1784 | } else { | |
1785 | aifdata_reg = WM8915_AIF1TX_DATA_CONFIGURATION_1; | |
1786 | lrclk_reg = WM8915_AIF1_TX_LRCLK_1; | |
1787 | } | |
c93993ac MB |
1788 | dsp_shift = 0; |
1789 | break; | |
1790 | case 1: | |
1791 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
1792 | (snd_soc_read(codec, WM8915_GPIO_2)) & WM8915_GP2_FN_MASK) { | |
1793 | aifdata_reg = WM8915_AIF2RX_DATA_CONFIGURATION; | |
1794 | lrclk_reg = WM8915_AIF2_RX_LRCLK_1; | |
1795 | } else { | |
1796 | aifdata_reg = WM8915_AIF2TX_DATA_CONFIGURATION_1; | |
1797 | lrclk_reg = WM8915_AIF2_TX_LRCLK_1; | |
1798 | } | |
c93993ac MB |
1799 | dsp_shift = WM8915_DSP2_DIV_SHIFT; |
1800 | break; | |
1801 | default: | |
1802 | BUG(); | |
1803 | return -EINVAL; | |
1804 | } | |
1805 | ||
1806 | bclk_rate = snd_soc_params_to_bclk(params); | |
1807 | if (bclk_rate < 0) { | |
1808 | dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate); | |
1809 | return bclk_rate; | |
1810 | } | |
1811 | ||
6dffdea7 MB |
1812 | wm8915->bclk_rate[dai->id] = bclk_rate; |
1813 | wm8915->rx_rate[dai->id] = params_rate(params); | |
1814 | ||
c93993ac MB |
1815 | /* Needs looking at for TDM */ |
1816 | bits = snd_pcm_format_width(params_format(params)); | |
1817 | if (bits < 0) | |
1818 | return bits; | |
1819 | aifdata |= (bits << WM8915_AIF1TX_WL_SHIFT) | bits; | |
1820 | ||
1821 | for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) { | |
1822 | if (dsp_divs[i] == params_rate(params)) | |
1823 | break; | |
1824 | } | |
1825 | if (i == ARRAY_SIZE(dsp_divs)) { | |
1826 | dev_err(codec->dev, "Unsupported sample rate %dHz\n", | |
1827 | params_rate(params)); | |
1828 | return -EINVAL; | |
1829 | } | |
1830 | dsp |= i << dsp_shift; | |
1831 | ||
6dffdea7 | 1832 | wm8915_update_bclk(codec); |
c93993ac MB |
1833 | |
1834 | lrclk = bclk_rate / params_rate(params); | |
1835 | dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", | |
1836 | lrclk, bclk_rate / lrclk); | |
1837 | ||
1838 | snd_soc_update_bits(codec, aifdata_reg, | |
1839 | WM8915_AIF1TX_WL_MASK | | |
1840 | WM8915_AIF1TX_SLOT_LEN_MASK, | |
1841 | aifdata); | |
c93993ac MB |
1842 | snd_soc_update_bits(codec, lrclk_reg, WM8915_AIF1RX_RATE_MASK, |
1843 | lrclk); | |
1844 | snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_2, | |
1845 | WM8915_DSP1_DIV_SHIFT << dsp_shift, dsp); | |
1846 | ||
c93993ac MB |
1847 | return 0; |
1848 | } | |
1849 | ||
1850 | static int wm8915_set_sysclk(struct snd_soc_dai *dai, | |
1851 | int clk_id, unsigned int freq, int dir) | |
1852 | { | |
1853 | struct snd_soc_codec *codec = dai->codec; | |
1854 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
1855 | int lfclk = 0; | |
c5f336cc | 1856 | int ratediv = 0; |
c93993ac MB |
1857 | int src; |
1858 | int old; | |
1859 | ||
ea7b4378 MB |
1860 | if (freq == wm8915->sysclk && clk_id == wm8915->sysclk_src) |
1861 | return 0; | |
1862 | ||
c93993ac | 1863 | /* Disable SYSCLK while we reconfigure */ |
1622ee18 | 1864 | old = snd_soc_read(codec, WM8915_AIF_CLOCKING_1) & WM8915_SYSCLK_ENA; |
c93993ac MB |
1865 | snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1, |
1866 | WM8915_SYSCLK_ENA, 0); | |
1867 | ||
1868 | switch (clk_id) { | |
1869 | case WM8915_SYSCLK_MCLK1: | |
1870 | wm8915->sysclk = freq; | |
1871 | src = 0; | |
1872 | break; | |
1873 | case WM8915_SYSCLK_MCLK2: | |
1874 | wm8915->sysclk = freq; | |
1875 | src = 1; | |
1876 | break; | |
1877 | case WM8915_SYSCLK_FLL: | |
1878 | wm8915->sysclk = freq; | |
1879 | src = 2; | |
1880 | break; | |
1881 | default: | |
1882 | dev_err(codec->dev, "Unsupported clock source %d\n", clk_id); | |
1883 | return -EINVAL; | |
1884 | } | |
1885 | ||
1886 | switch (wm8915->sysclk) { | |
1887 | case 6144000: | |
1888 | snd_soc_update_bits(codec, WM8915_AIF_RATE, | |
1889 | WM8915_SYSCLK_RATE, 0); | |
1890 | break; | |
c5f336cc MB |
1891 | case 24576000: |
1892 | ratediv = WM8915_SYSCLK_DIV; | |
c93993ac MB |
1893 | case 12288000: |
1894 | snd_soc_update_bits(codec, WM8915_AIF_RATE, | |
1895 | WM8915_SYSCLK_RATE, WM8915_SYSCLK_RATE); | |
1896 | break; | |
1897 | case 32000: | |
1898 | case 32768: | |
1899 | lfclk = WM8915_LFCLK_ENA; | |
1900 | break; | |
1901 | default: | |
1902 | dev_warn(codec->dev, "Unsupported clock rate %dHz\n", | |
1903 | wm8915->sysclk); | |
1904 | return -EINVAL; | |
1905 | } | |
1906 | ||
6dffdea7 MB |
1907 | wm8915_update_bclk(codec); |
1908 | ||
c93993ac | 1909 | snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1, |
c5f336cc MB |
1910 | WM8915_SYSCLK_SRC_MASK | WM8915_SYSCLK_DIV_MASK, |
1911 | src << WM8915_SYSCLK_SRC_SHIFT | ratediv); | |
c93993ac MB |
1912 | snd_soc_update_bits(codec, WM8915_CLOCKING_1, WM8915_LFCLK_ENA, lfclk); |
1913 | snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1, | |
1914 | WM8915_SYSCLK_ENA, old); | |
1915 | ||
ea7b4378 MB |
1916 | wm8915->sysclk_src = clk_id; |
1917 | ||
c93993ac MB |
1918 | return 0; |
1919 | } | |
1920 | ||
1921 | struct _fll_div { | |
1922 | u16 fll_fratio; | |
1923 | u16 fll_outdiv; | |
1924 | u16 fll_refclk_div; | |
1925 | u16 fll_loop_gain; | |
1926 | u16 fll_ref_freq; | |
1927 | u16 n; | |
1928 | u16 theta; | |
1929 | u16 lambda; | |
1930 | }; | |
1931 | ||
1932 | static struct { | |
1933 | unsigned int min; | |
1934 | unsigned int max; | |
1935 | u16 fll_fratio; | |
1936 | int ratio; | |
1937 | } fll_fratios[] = { | |
1938 | { 0, 64000, 4, 16 }, | |
1939 | { 64000, 128000, 3, 8 }, | |
1940 | { 128000, 256000, 2, 4 }, | |
1941 | { 256000, 1000000, 1, 2 }, | |
1942 | { 1000000, 13500000, 0, 1 }, | |
1943 | }; | |
1944 | ||
1945 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
1946 | unsigned int Fout) | |
1947 | { | |
1948 | unsigned int target; | |
1949 | unsigned int div; | |
1950 | unsigned int fratio, gcd_fll; | |
1951 | int i; | |
1952 | ||
1953 | /* Fref must be <=13.5MHz */ | |
1954 | div = 1; | |
1955 | fll_div->fll_refclk_div = 0; | |
1956 | while ((Fref / div) > 13500000) { | |
1957 | div *= 2; | |
1958 | fll_div->fll_refclk_div++; | |
1959 | ||
1960 | if (div > 8) { | |
1961 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
1962 | Fref); | |
1963 | return -EINVAL; | |
1964 | } | |
1965 | } | |
1966 | ||
1967 | pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); | |
1968 | ||
1969 | /* Apply the division for our remaining calculations */ | |
1970 | Fref /= div; | |
1971 | ||
1972 | if (Fref >= 3000000) | |
1973 | fll_div->fll_loop_gain = 5; | |
1974 | else | |
1975 | fll_div->fll_loop_gain = 0; | |
1976 | ||
1977 | if (Fref >= 48000) | |
1978 | fll_div->fll_ref_freq = 0; | |
1979 | else | |
1980 | fll_div->fll_ref_freq = 1; | |
1981 | ||
1982 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
1983 | div = 2; | |
1984 | while (Fout * div < 90000000) { | |
1985 | div++; | |
1986 | if (div > 64) { | |
1987 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
1988 | Fout); | |
1989 | return -EINVAL; | |
1990 | } | |
1991 | } | |
1992 | target = Fout * div; | |
1993 | fll_div->fll_outdiv = div - 1; | |
1994 | ||
1995 | pr_debug("FLL Fvco=%dHz\n", target); | |
1996 | ||
1997 | /* Find an appropraite FLL_FRATIO and factor it out of the target */ | |
1998 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { | |
1999 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
2000 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
2001 | fratio = fll_fratios[i].ratio; | |
2002 | break; | |
2003 | } | |
2004 | } | |
2005 | if (i == ARRAY_SIZE(fll_fratios)) { | |
2006 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
2007 | return -EINVAL; | |
2008 | } | |
2009 | ||
2010 | fll_div->n = target / (fratio * Fref); | |
2011 | ||
2012 | if (target % Fref == 0) { | |
2013 | fll_div->theta = 0; | |
2014 | fll_div->lambda = 0; | |
2015 | } else { | |
2016 | gcd_fll = gcd(target, fratio * Fref); | |
2017 | ||
2018 | fll_div->theta = (target - (fll_div->n * fratio * Fref)) | |
2019 | / gcd_fll; | |
2020 | fll_div->lambda = (fratio * Fref) / gcd_fll; | |
2021 | } | |
2022 | ||
2023 | pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", | |
2024 | fll_div->n, fll_div->theta, fll_div->lambda); | |
2025 | pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", | |
2026 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
2027 | fll_div->fll_refclk_div); | |
2028 | ||
2029 | return 0; | |
2030 | } | |
2031 | ||
01b07e2d | 2032 | static int wm8915_set_fll(struct snd_soc_codec *codec, int fll_id, int source, |
c93993ac MB |
2033 | unsigned int Fref, unsigned int Fout) |
2034 | { | |
c93993ac | 2035 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); |
51b3b5ca | 2036 | struct i2c_client *i2c = to_i2c_client(codec->dev); |
c93993ac MB |
2037 | struct _fll_div fll_div; |
2038 | unsigned long timeout; | |
2039 | int ret, reg; | |
2040 | ||
2041 | /* Any change? */ | |
2042 | if (source == wm8915->fll_src && Fref == wm8915->fll_fref && | |
2043 | Fout == wm8915->fll_fout) | |
2044 | return 0; | |
2045 | ||
2046 | if (Fout == 0) { | |
2047 | dev_dbg(codec->dev, "FLL disabled\n"); | |
2048 | ||
2049 | wm8915->fll_fref = 0; | |
2050 | wm8915->fll_fout = 0; | |
2051 | ||
2052 | snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1, | |
2053 | WM8915_FLL_ENA, 0); | |
2054 | ||
2055 | return 0; | |
2056 | } | |
2057 | ||
2058 | ret = fll_factors(&fll_div, Fref, Fout); | |
2059 | if (ret != 0) | |
2060 | return ret; | |
2061 | ||
2062 | switch (source) { | |
2063 | case WM8915_FLL_MCLK1: | |
2064 | reg = 0; | |
2065 | break; | |
2066 | case WM8915_FLL_MCLK2: | |
2067 | reg = 1; | |
6ac34062 | 2068 | break; |
c93993ac MB |
2069 | case WM8915_FLL_DACLRCLK1: |
2070 | reg = 2; | |
2071 | break; | |
2072 | case WM8915_FLL_BCLK1: | |
2073 | reg = 3; | |
2074 | break; | |
2075 | default: | |
2076 | dev_err(codec->dev, "Unknown FLL source %d\n", ret); | |
2077 | return -EINVAL; | |
2078 | } | |
2079 | ||
2080 | reg |= fll_div.fll_refclk_div << WM8915_FLL_REFCLK_DIV_SHIFT; | |
2081 | reg |= fll_div.fll_ref_freq << WM8915_FLL_REF_FREQ_SHIFT; | |
2082 | ||
2083 | snd_soc_update_bits(codec, WM8915_FLL_CONTROL_5, | |
2084 | WM8915_FLL_REFCLK_DIV_MASK | WM8915_FLL_REF_FREQ | | |
2085 | WM8915_FLL_REFCLK_SRC_MASK, reg); | |
2086 | ||
2087 | reg = 0; | |
2088 | if (fll_div.theta || fll_div.lambda) | |
2089 | reg |= WM8915_FLL_EFS_ENA | (3 << WM8915_FLL_LFSR_SEL_SHIFT); | |
2090 | else | |
2091 | reg |= 1 << WM8915_FLL_LFSR_SEL_SHIFT; | |
2092 | snd_soc_write(codec, WM8915_FLL_EFS_2, reg); | |
2093 | ||
2094 | snd_soc_update_bits(codec, WM8915_FLL_CONTROL_2, | |
2095 | WM8915_FLL_OUTDIV_MASK | | |
2096 | WM8915_FLL_FRATIO_MASK, | |
2097 | (fll_div.fll_outdiv << WM8915_FLL_OUTDIV_SHIFT) | | |
2098 | (fll_div.fll_fratio)); | |
2099 | ||
2100 | snd_soc_write(codec, WM8915_FLL_CONTROL_3, fll_div.theta); | |
2101 | ||
2102 | snd_soc_update_bits(codec, WM8915_FLL_CONTROL_4, | |
2103 | WM8915_FLL_N_MASK | WM8915_FLL_LOOP_GAIN_MASK, | |
2104 | (fll_div.n << WM8915_FLL_N_SHIFT) | | |
2105 | fll_div.fll_loop_gain); | |
2106 | ||
2107 | snd_soc_write(codec, WM8915_FLL_EFS_1, fll_div.lambda); | |
2108 | ||
2109 | snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1, | |
2110 | WM8915_FLL_ENA, WM8915_FLL_ENA); | |
2111 | ||
2112 | /* The FLL supports live reconfiguration - kick that in case we were | |
2113 | * already enabled. | |
2114 | */ | |
2115 | snd_soc_write(codec, WM8915_FLL_CONTROL_6, WM8915_FLL_SWITCH_CLK); | |
2116 | ||
2117 | /* Wait for the FLL to lock, using the interrupt if possible */ | |
2118 | if (Fref > 1000000) | |
2119 | timeout = usecs_to_jiffies(300); | |
2120 | else | |
2121 | timeout = msecs_to_jiffies(2); | |
2122 | ||
51b3b5ca MB |
2123 | /* Allow substantially longer if we've actually got the IRQ */ |
2124 | if (i2c->irq) | |
2125 | timeout *= 1000; | |
2126 | ||
2127 | ret = wait_for_completion_timeout(&wm8915->fll_lock, timeout); | |
2128 | ||
2129 | if (ret == 0 && i2c->irq) { | |
2130 | dev_err(codec->dev, "Timed out waiting for FLL\n"); | |
2131 | ret = -ETIMEDOUT; | |
2132 | } else { | |
2133 | ret = 0; | |
2134 | } | |
c93993ac MB |
2135 | |
2136 | dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); | |
2137 | ||
2138 | wm8915->fll_fref = Fref; | |
2139 | wm8915->fll_fout = Fout; | |
2140 | wm8915->fll_src = source; | |
2141 | ||
51b3b5ca | 2142 | return ret; |
c93993ac MB |
2143 | } |
2144 | ||
2145 | #ifdef CONFIG_GPIOLIB | |
2146 | static inline struct wm8915_priv *gpio_to_wm8915(struct gpio_chip *chip) | |
2147 | { | |
2148 | return container_of(chip, struct wm8915_priv, gpio_chip); | |
2149 | } | |
2150 | ||
2151 | static void wm8915_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
2152 | { | |
2153 | struct wm8915_priv *wm8915 = gpio_to_wm8915(chip); | |
2154 | struct snd_soc_codec *codec = wm8915->codec; | |
2155 | ||
2156 | snd_soc_update_bits(codec, WM8915_GPIO_1 + offset, | |
2157 | WM8915_GP1_LVL, !!value << WM8915_GP1_LVL_SHIFT); | |
2158 | } | |
2159 | ||
2160 | static int wm8915_gpio_direction_out(struct gpio_chip *chip, | |
2161 | unsigned offset, int value) | |
2162 | { | |
2163 | struct wm8915_priv *wm8915 = gpio_to_wm8915(chip); | |
2164 | struct snd_soc_codec *codec = wm8915->codec; | |
2165 | int val; | |
2166 | ||
2167 | val = (1 << WM8915_GP1_FN_SHIFT) | (!!value << WM8915_GP1_LVL_SHIFT); | |
2168 | ||
2169 | return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset, | |
2170 | WM8915_GP1_FN_MASK | WM8915_GP1_DIR | | |
2171 | WM8915_GP1_LVL, val); | |
2172 | } | |
2173 | ||
2174 | static int wm8915_gpio_get(struct gpio_chip *chip, unsigned offset) | |
2175 | { | |
2176 | struct wm8915_priv *wm8915 = gpio_to_wm8915(chip); | |
2177 | struct snd_soc_codec *codec = wm8915->codec; | |
2178 | int ret; | |
2179 | ||
2180 | ret = snd_soc_read(codec, WM8915_GPIO_1 + offset); | |
2181 | if (ret < 0) | |
2182 | return ret; | |
2183 | ||
2184 | return (ret & WM8915_GP1_LVL) != 0; | |
2185 | } | |
2186 | ||
2187 | static int wm8915_gpio_direction_in(struct gpio_chip *chip, unsigned offset) | |
2188 | { | |
2189 | struct wm8915_priv *wm8915 = gpio_to_wm8915(chip); | |
2190 | struct snd_soc_codec *codec = wm8915->codec; | |
2191 | ||
2192 | return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset, | |
2193 | WM8915_GP1_FN_MASK | WM8915_GP1_DIR, | |
2194 | (1 << WM8915_GP1_FN_SHIFT) | | |
2195 | (1 << WM8915_GP1_DIR_SHIFT)); | |
2196 | } | |
2197 | ||
2198 | static struct gpio_chip wm8915_template_chip = { | |
2199 | .label = "wm8915", | |
2200 | .owner = THIS_MODULE, | |
2201 | .direction_output = wm8915_gpio_direction_out, | |
2202 | .set = wm8915_gpio_set, | |
2203 | .direction_input = wm8915_gpio_direction_in, | |
2204 | .get = wm8915_gpio_get, | |
2205 | .can_sleep = 1, | |
2206 | }; | |
2207 | ||
2208 | static void wm8915_init_gpio(struct snd_soc_codec *codec) | |
2209 | { | |
2210 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
2211 | int ret; | |
2212 | ||
2213 | wm8915->gpio_chip = wm8915_template_chip; | |
2214 | wm8915->gpio_chip.ngpio = 5; | |
2215 | wm8915->gpio_chip.dev = codec->dev; | |
2216 | ||
2217 | if (wm8915->pdata.gpio_base) | |
2218 | wm8915->gpio_chip.base = wm8915->pdata.gpio_base; | |
2219 | else | |
2220 | wm8915->gpio_chip.base = -1; | |
2221 | ||
2222 | ret = gpiochip_add(&wm8915->gpio_chip); | |
2223 | if (ret != 0) | |
2224 | dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); | |
2225 | } | |
2226 | ||
2227 | static void wm8915_free_gpio(struct snd_soc_codec *codec) | |
2228 | { | |
2229 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
2230 | int ret; | |
2231 | ||
2232 | ret = gpiochip_remove(&wm8915->gpio_chip); | |
2233 | if (ret != 0) | |
2234 | dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); | |
2235 | } | |
2236 | #else | |
2237 | static void wm8915_init_gpio(struct snd_soc_codec *codec) | |
2238 | { | |
2239 | } | |
2240 | ||
2241 | static void wm8915_free_gpio(struct snd_soc_codec *codec) | |
2242 | { | |
2243 | } | |
2244 | #endif | |
2245 | ||
2246 | /** | |
2247 | * wm8915_detect - Enable default WM8915 jack detection | |
2248 | * | |
2249 | * The WM8915 has advanced accessory detection support for headsets. | |
2250 | * This function provides a default implementation which integrates | |
2251 | * the majority of this functionality with minimal user configuration. | |
2252 | * | |
2253 | * This will detect headset, headphone and short circuit button and | |
2254 | * will also detect inverted microphone ground connections and update | |
2255 | * the polarity of the connections. | |
2256 | */ | |
2257 | int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, | |
2258 | wm8915_polarity_fn polarity_cb) | |
2259 | { | |
2260 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
2261 | ||
2262 | wm8915->jack = jack; | |
2263 | wm8915->detecting = true; | |
2264 | wm8915->polarity_cb = polarity_cb; | |
2265 | ||
2266 | if (wm8915->polarity_cb) | |
2267 | wm8915->polarity_cb(codec, 0); | |
2268 | ||
2269 | /* Clear discarge to avoid noise during detection */ | |
2270 | snd_soc_update_bits(codec, WM8915_MICBIAS_1, | |
2271 | WM8915_MICB1_DISCH, 0); | |
2272 | snd_soc_update_bits(codec, WM8915_MICBIAS_2, | |
2273 | WM8915_MICB2_DISCH, 0); | |
2274 | ||
2275 | /* LDO2 powers the microphones, SYSCLK clocks detection */ | |
2276 | snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); | |
2277 | snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); | |
2278 | ||
2279 | /* We start off just enabling microphone detection - even a | |
2280 | * plain headphone will trigger detection. | |
2281 | */ | |
2282 | snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, | |
2283 | WM8915_MICD_ENA, WM8915_MICD_ENA); | |
2284 | ||
2285 | /* Slowest detection rate, gives debounce for initial detection */ | |
2286 | snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, | |
2287 | WM8915_MICD_RATE_MASK, | |
2288 | WM8915_MICD_RATE_MASK); | |
2289 | ||
2290 | /* Enable interrupts and we're off */ | |
2291 | snd_soc_update_bits(codec, WM8915_INTERRUPT_STATUS_2_MASK, | |
2292 | WM8915_IM_MICD_EINT, 0); | |
2293 | ||
2294 | return 0; | |
2295 | } | |
2296 | EXPORT_SYMBOL_GPL(wm8915_detect); | |
2297 | ||
2298 | static void wm8915_micd(struct snd_soc_codec *codec) | |
2299 | { | |
2300 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
2301 | int val, reg; | |
2302 | ||
2303 | val = snd_soc_read(codec, WM8915_MIC_DETECT_3); | |
2304 | ||
2305 | dev_dbg(codec->dev, "Microphone event: %x\n", val); | |
2306 | ||
2307 | if (!(val & WM8915_MICD_VALID)) { | |
2308 | dev_warn(codec->dev, "Microphone detection state invalid\n"); | |
2309 | return; | |
2310 | } | |
2311 | ||
2312 | /* No accessory, reset everything and report removal */ | |
2313 | if (!(val & WM8915_MICD_STS)) { | |
2314 | dev_dbg(codec->dev, "Jack removal detected\n"); | |
2315 | wm8915->jack_mic = false; | |
2316 | wm8915->detecting = true; | |
2317 | snd_soc_jack_report(wm8915->jack, 0, | |
2318 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
2319 | snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, | |
2320 | WM8915_MICD_RATE_MASK, | |
2321 | WM8915_MICD_RATE_MASK); | |
2322 | return; | |
2323 | } | |
2324 | ||
2325 | /* If the measurement is very high we've got a microphone but | |
2326 | * do a little debounce to account for mechanical issues. | |
2327 | */ | |
2328 | if (val & 0x400) { | |
2329 | dev_dbg(codec->dev, "Microphone detected\n"); | |
2330 | snd_soc_jack_report(wm8915->jack, SND_JACK_HEADSET, | |
2331 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
2332 | wm8915->jack_mic = true; | |
2333 | wm8915->detecting = false; | |
e6a9be0b MB |
2334 | |
2335 | /* Increase poll rate to give better responsiveness | |
2336 | * for buttons */ | |
2337 | snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, | |
2338 | WM8915_MICD_RATE_MASK, | |
2339 | 5 << WM8915_MICD_RATE_SHIFT); | |
c93993ac MB |
2340 | } |
2341 | ||
2342 | /* If we detected a lower impedence during initial startup | |
2343 | * then we probably have the wrong polarity, flip it. Don't | |
2344 | * do this for the lowest impedences to speed up detection of | |
2345 | * plain headphones. | |
2346 | */ | |
2347 | if (wm8915->detecting && (val & 0x3f0)) { | |
2348 | reg = snd_soc_read(codec, WM8915_ACCESSORY_DETECT_MODE_2); | |
2349 | reg ^= WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC | | |
2350 | WM8915_MICD_BIAS_SRC; | |
2351 | snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2, | |
2352 | WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC | | |
2353 | WM8915_MICD_BIAS_SRC, reg); | |
2354 | ||
2355 | if (wm8915->polarity_cb) | |
2356 | wm8915->polarity_cb(codec, | |
2357 | (reg & WM8915_MICD_SRC) != 0); | |
2358 | ||
2359 | dev_dbg(codec->dev, "Set microphone polarity to %d\n", | |
2360 | (reg & WM8915_MICD_SRC) != 0); | |
2361 | ||
2362 | return; | |
2363 | } | |
2364 | ||
2365 | /* Don't distinguish between buttons, just report any low | |
2366 | * impedence as BTN_0. | |
2367 | */ | |
2368 | if (val & 0x3fc) { | |
2369 | if (wm8915->jack_mic) { | |
2370 | dev_dbg(codec->dev, "Mic button detected\n"); | |
2371 | snd_soc_jack_report(wm8915->jack, | |
2372 | SND_JACK_HEADSET | SND_JACK_BTN_0, | |
2373 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
2374 | } else { | |
2375 | dev_dbg(codec->dev, "Headphone detected\n"); | |
2376 | snd_soc_jack_report(wm8915->jack, | |
2377 | SND_JACK_HEADPHONE, | |
2378 | SND_JACK_HEADSET | | |
2379 | SND_JACK_BTN_0); | |
e6a9be0b MB |
2380 | |
2381 | /* Increase the detection rate a bit for | |
2382 | * responsiveness. | |
2383 | */ | |
2384 | snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, | |
2385 | WM8915_MICD_RATE_MASK, | |
2386 | 7 << WM8915_MICD_RATE_SHIFT); | |
2387 | ||
c93993ac MB |
2388 | wm8915->detecting = false; |
2389 | } | |
2390 | } | |
c93993ac MB |
2391 | } |
2392 | ||
2393 | static irqreturn_t wm8915_irq(int irq, void *data) | |
2394 | { | |
2395 | struct snd_soc_codec *codec = data; | |
2396 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
2397 | int irq_val; | |
2398 | ||
2399 | irq_val = snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2); | |
2400 | if (irq_val < 0) { | |
2401 | dev_err(codec->dev, "Failed to read IRQ status: %d\n", | |
2402 | irq_val); | |
2403 | return IRQ_NONE; | |
2404 | } | |
2405 | irq_val &= ~snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2_MASK); | |
2406 | ||
2407 | if (irq_val & (WM8915_DCS_DONE_01_EINT | WM8915_DCS_DONE_23_EINT)) { | |
2408 | dev_dbg(codec->dev, "DC servo IRQ\n"); | |
2409 | complete(&wm8915->dcs_done); | |
2410 | } | |
2411 | ||
2412 | if (irq_val & WM8915_FIFOS_ERR_EINT) | |
2413 | dev_err(codec->dev, "Digital core FIFO error\n"); | |
2414 | ||
2415 | if (irq_val & WM8915_FLL_LOCK_EINT) { | |
2416 | dev_dbg(codec->dev, "FLL locked\n"); | |
2417 | complete(&wm8915->fll_lock); | |
2418 | } | |
2419 | ||
2420 | if (irq_val & WM8915_MICD_EINT) | |
2421 | wm8915_micd(codec); | |
2422 | ||
2423 | if (irq_val) { | |
2424 | snd_soc_write(codec, WM8915_INTERRUPT_STATUS_2, irq_val); | |
2425 | ||
2426 | return IRQ_HANDLED; | |
2427 | } else { | |
2428 | return IRQ_NONE; | |
2429 | } | |
2430 | } | |
2431 | ||
a1e9adc0 MB |
2432 | static irqreturn_t wm8915_edge_irq(int irq, void *data) |
2433 | { | |
2434 | irqreturn_t ret = IRQ_NONE; | |
2435 | irqreturn_t val; | |
2436 | ||
2437 | do { | |
2438 | val = wm8915_irq(irq, data); | |
2439 | if (val != IRQ_NONE) | |
2440 | ret = val; | |
2441 | } while (val != IRQ_NONE); | |
2442 | ||
2443 | return ret; | |
2444 | } | |
2445 | ||
c93993ac MB |
2446 | static void wm8915_retune_mobile_pdata(struct snd_soc_codec *codec) |
2447 | { | |
2448 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
2449 | struct wm8915_pdata *pdata = &wm8915->pdata; | |
2450 | ||
2451 | struct snd_kcontrol_new controls[] = { | |
2452 | SOC_ENUM_EXT("DSP1 EQ Mode", | |
2453 | wm8915->retune_mobile_enum, | |
2454 | wm8915_get_retune_mobile_enum, | |
2455 | wm8915_put_retune_mobile_enum), | |
2456 | SOC_ENUM_EXT("DSP2 EQ Mode", | |
2457 | wm8915->retune_mobile_enum, | |
2458 | wm8915_get_retune_mobile_enum, | |
2459 | wm8915_put_retune_mobile_enum), | |
2460 | }; | |
2461 | int ret, i, j; | |
2462 | const char **t; | |
2463 | ||
2464 | /* We need an array of texts for the enum API but the number | |
2465 | * of texts is likely to be less than the number of | |
2466 | * configurations due to the sample rate dependency of the | |
2467 | * configurations. */ | |
2468 | wm8915->num_retune_mobile_texts = 0; | |
2469 | wm8915->retune_mobile_texts = NULL; | |
2470 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
2471 | for (j = 0; j < wm8915->num_retune_mobile_texts; j++) { | |
2472 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
2473 | wm8915->retune_mobile_texts[j]) == 0) | |
2474 | break; | |
2475 | } | |
2476 | ||
2477 | if (j != wm8915->num_retune_mobile_texts) | |
2478 | continue; | |
2479 | ||
2480 | /* Expand the array... */ | |
2481 | t = krealloc(wm8915->retune_mobile_texts, | |
2482 | sizeof(char *) * | |
2483 | (wm8915->num_retune_mobile_texts + 1), | |
2484 | GFP_KERNEL); | |
2485 | if (t == NULL) | |
2486 | continue; | |
2487 | ||
2488 | /* ...store the new entry... */ | |
2489 | t[wm8915->num_retune_mobile_texts] = | |
2490 | pdata->retune_mobile_cfgs[i].name; | |
2491 | ||
2492 | /* ...and remember the new version. */ | |
2493 | wm8915->num_retune_mobile_texts++; | |
2494 | wm8915->retune_mobile_texts = t; | |
2495 | } | |
2496 | ||
2497 | dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", | |
2498 | wm8915->num_retune_mobile_texts); | |
2499 | ||
2500 | wm8915->retune_mobile_enum.max = wm8915->num_retune_mobile_texts; | |
2501 | wm8915->retune_mobile_enum.texts = wm8915->retune_mobile_texts; | |
2502 | ||
2503 | ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); | |
2504 | if (ret != 0) | |
2505 | dev_err(codec->dev, | |
2506 | "Failed to add ReTune Mobile controls: %d\n", ret); | |
2507 | } | |
2508 | ||
2509 | static int wm8915_probe(struct snd_soc_codec *codec) | |
2510 | { | |
2511 | int ret; | |
2512 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
2513 | struct i2c_client *i2c = to_i2c_client(codec->dev); | |
2514 | struct snd_soc_dapm_context *dapm = &codec->dapm; | |
2515 | int i, irq_flags; | |
2516 | ||
2517 | wm8915->codec = codec; | |
2518 | ||
2519 | init_completion(&wm8915->dcs_done); | |
2520 | init_completion(&wm8915->fll_lock); | |
2521 | ||
2522 | dapm->idle_bias_off = true; | |
2523 | dapm->bias_level = SND_SOC_BIAS_OFF; | |
2524 | ||
2525 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); | |
2526 | if (ret != 0) { | |
2527 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
2528 | goto err; | |
2529 | } | |
2530 | ||
2531 | for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) | |
2532 | wm8915->supplies[i].supply = wm8915_supply_names[i]; | |
2533 | ||
2534 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8915->supplies), | |
2535 | wm8915->supplies); | |
2536 | if (ret != 0) { | |
2537 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
2538 | goto err; | |
2539 | } | |
2540 | ||
2541 | wm8915->disable_nb[0].notifier_call = wm8915_regulator_event_0; | |
2542 | wm8915->disable_nb[1].notifier_call = wm8915_regulator_event_1; | |
2543 | wm8915->disable_nb[2].notifier_call = wm8915_regulator_event_2; | |
2544 | wm8915->disable_nb[3].notifier_call = wm8915_regulator_event_3; | |
c93993ac MB |
2545 | |
2546 | /* This should really be moved into the regulator core */ | |
2547 | for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) { | |
2548 | ret = regulator_register_notifier(wm8915->supplies[i].consumer, | |
2549 | &wm8915->disable_nb[i]); | |
2550 | if (ret != 0) { | |
2551 | dev_err(codec->dev, | |
2552 | "Failed to register regulator notifier: %d\n", | |
2553 | ret); | |
2554 | } | |
2555 | } | |
2556 | ||
2557 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies), | |
2558 | wm8915->supplies); | |
2559 | if (ret != 0) { | |
2560 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
2561 | goto err_get; | |
2562 | } | |
2563 | ||
2564 | if (wm8915->pdata.ldo_ena >= 0) { | |
2565 | gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 1); | |
2566 | msleep(5); | |
2567 | } | |
2568 | ||
2569 | ret = snd_soc_read(codec, WM8915_SOFTWARE_RESET); | |
2570 | if (ret < 0) { | |
2571 | dev_err(codec->dev, "Failed to read ID register: %d\n", ret); | |
2572 | goto err_enable; | |
2573 | } | |
2574 | if (ret != 0x8915) { | |
2575 | dev_err(codec->dev, "Device is not a WM8915, ID %x\n", ret); | |
2576 | ret = -EINVAL; | |
2577 | goto err_enable; | |
2578 | } | |
2579 | ||
2580 | ret = snd_soc_read(codec, WM8915_CHIP_REVISION); | |
2581 | if (ret < 0) { | |
2582 | dev_err(codec->dev, "Failed to read device revision: %d\n", | |
2583 | ret); | |
2584 | goto err_enable; | |
2585 | } | |
2586 | ||
2587 | dev_info(codec->dev, "revision %c\n", | |
2588 | (ret & WM8915_CHIP_REV_MASK) + 'A'); | |
2589 | ||
2590 | if (wm8915->pdata.ldo_ena >= 0) { | |
2591 | gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0); | |
2592 | } else { | |
2593 | ret = wm8915_reset(codec); | |
2594 | if (ret < 0) { | |
2595 | dev_err(codec->dev, "Failed to issue reset\n"); | |
2596 | goto err_enable; | |
2597 | } | |
2598 | } | |
2599 | ||
2600 | codec->cache_only = true; | |
2601 | ||
2602 | /* Apply platform data settings */ | |
2603 | snd_soc_update_bits(codec, WM8915_LINE_INPUT_CONTROL, | |
2604 | WM8915_INL_MODE_MASK | WM8915_INR_MODE_MASK, | |
2605 | wm8915->pdata.inl_mode << WM8915_INL_MODE_SHIFT | | |
2606 | wm8915->pdata.inr_mode); | |
2607 | ||
2608 | for (i = 0; i < ARRAY_SIZE(wm8915->pdata.gpio_default); i++) { | |
2609 | if (!wm8915->pdata.gpio_default[i]) | |
2610 | continue; | |
2611 | ||
2612 | snd_soc_write(codec, WM8915_GPIO_1 + i, | |
2613 | wm8915->pdata.gpio_default[i] & 0xffff); | |
2614 | } | |
2615 | ||
2616 | if (wm8915->pdata.spkmute_seq) | |
2617 | snd_soc_update_bits(codec, WM8915_PDM_SPEAKER_MUTE_SEQUENCE, | |
2618 | WM8915_SPK_MUTE_ENDIAN | | |
2619 | WM8915_SPK_MUTE_SEQ1_MASK, | |
2620 | wm8915->pdata.spkmute_seq); | |
2621 | ||
2622 | snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2, | |
2623 | WM8915_MICD_BIAS_SRC | WM8915_HPOUT1FB_SRC | | |
2624 | WM8915_MICD_SRC, wm8915->pdata.micdet_def); | |
2625 | ||
2626 | /* Latch volume update bits */ | |
2627 | snd_soc_update_bits(codec, WM8915_LEFT_LINE_INPUT_VOLUME, | |
2628 | WM8915_IN1_VU, WM8915_IN1_VU); | |
2629 | snd_soc_update_bits(codec, WM8915_RIGHT_LINE_INPUT_VOLUME, | |
2630 | WM8915_IN1_VU, WM8915_IN1_VU); | |
2631 | ||
2632 | snd_soc_update_bits(codec, WM8915_DAC1_LEFT_VOLUME, | |
2633 | WM8915_DAC1_VU, WM8915_DAC1_VU); | |
2634 | snd_soc_update_bits(codec, WM8915_DAC1_RIGHT_VOLUME, | |
2635 | WM8915_DAC1_VU, WM8915_DAC1_VU); | |
2636 | snd_soc_update_bits(codec, WM8915_DAC2_LEFT_VOLUME, | |
2637 | WM8915_DAC2_VU, WM8915_DAC2_VU); | |
2638 | snd_soc_update_bits(codec, WM8915_DAC2_RIGHT_VOLUME, | |
2639 | WM8915_DAC2_VU, WM8915_DAC2_VU); | |
2640 | ||
2641 | snd_soc_update_bits(codec, WM8915_OUTPUT1_LEFT_VOLUME, | |
2642 | WM8915_DAC1_VU, WM8915_DAC1_VU); | |
2643 | snd_soc_update_bits(codec, WM8915_OUTPUT1_RIGHT_VOLUME, | |
2644 | WM8915_DAC1_VU, WM8915_DAC1_VU); | |
2645 | snd_soc_update_bits(codec, WM8915_OUTPUT2_LEFT_VOLUME, | |
2646 | WM8915_DAC2_VU, WM8915_DAC2_VU); | |
2647 | snd_soc_update_bits(codec, WM8915_OUTPUT2_RIGHT_VOLUME, | |
2648 | WM8915_DAC2_VU, WM8915_DAC2_VU); | |
2649 | ||
2650 | snd_soc_update_bits(codec, WM8915_DSP1_TX_LEFT_VOLUME, | |
2651 | WM8915_DSP1TX_VU, WM8915_DSP1TX_VU); | |
2652 | snd_soc_update_bits(codec, WM8915_DSP1_TX_RIGHT_VOLUME, | |
2653 | WM8915_DSP1TX_VU, WM8915_DSP1TX_VU); | |
2654 | snd_soc_update_bits(codec, WM8915_DSP2_TX_LEFT_VOLUME, | |
2655 | WM8915_DSP2TX_VU, WM8915_DSP2TX_VU); | |
2656 | snd_soc_update_bits(codec, WM8915_DSP2_TX_RIGHT_VOLUME, | |
2657 | WM8915_DSP2TX_VU, WM8915_DSP2TX_VU); | |
2658 | ||
2659 | snd_soc_update_bits(codec, WM8915_DSP1_RX_LEFT_VOLUME, | |
2660 | WM8915_DSP1RX_VU, WM8915_DSP1RX_VU); | |
2661 | snd_soc_update_bits(codec, WM8915_DSP1_RX_RIGHT_VOLUME, | |
2662 | WM8915_DSP1RX_VU, WM8915_DSP1RX_VU); | |
2663 | snd_soc_update_bits(codec, WM8915_DSP2_RX_LEFT_VOLUME, | |
2664 | WM8915_DSP2RX_VU, WM8915_DSP2RX_VU); | |
2665 | snd_soc_update_bits(codec, WM8915_DSP2_RX_RIGHT_VOLUME, | |
2666 | WM8915_DSP2RX_VU, WM8915_DSP2RX_VU); | |
2667 | ||
2668 | /* No support currently for the underclocked TDM modes and | |
2669 | * pick a default TDM layout with each channel pair working with | |
2670 | * slots 0 and 1. */ | |
2671 | snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_0_CONFIGURATION, | |
2672 | WM8915_AIF1RX_CHAN0_SLOTS_MASK | | |
2673 | WM8915_AIF1RX_CHAN0_START_SLOT_MASK, | |
2674 | 1 << WM8915_AIF1RX_CHAN0_SLOTS_SHIFT | 0); | |
2675 | snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_1_CONFIGURATION, | |
2676 | WM8915_AIF1RX_CHAN1_SLOTS_MASK | | |
2677 | WM8915_AIF1RX_CHAN1_START_SLOT_MASK, | |
2678 | 1 << WM8915_AIF1RX_CHAN1_SLOTS_SHIFT | 1); | |
2679 | snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_2_CONFIGURATION, | |
2680 | WM8915_AIF1RX_CHAN2_SLOTS_MASK | | |
2681 | WM8915_AIF1RX_CHAN2_START_SLOT_MASK, | |
2682 | 1 << WM8915_AIF1RX_CHAN2_SLOTS_SHIFT | 0); | |
2683 | snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_3_CONFIGURATION, | |
2684 | WM8915_AIF1RX_CHAN3_SLOTS_MASK | | |
2685 | WM8915_AIF1RX_CHAN0_START_SLOT_MASK, | |
2686 | 1 << WM8915_AIF1RX_CHAN3_SLOTS_SHIFT | 1); | |
2687 | snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_4_CONFIGURATION, | |
2688 | WM8915_AIF1RX_CHAN4_SLOTS_MASK | | |
2689 | WM8915_AIF1RX_CHAN0_START_SLOT_MASK, | |
2690 | 1 << WM8915_AIF1RX_CHAN4_SLOTS_SHIFT | 0); | |
2691 | snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_5_CONFIGURATION, | |
2692 | WM8915_AIF1RX_CHAN5_SLOTS_MASK | | |
2693 | WM8915_AIF1RX_CHAN0_START_SLOT_MASK, | |
2694 | 1 << WM8915_AIF1RX_CHAN5_SLOTS_SHIFT | 1); | |
2695 | ||
2696 | snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_0_CONFIGURATION, | |
2697 | WM8915_AIF2RX_CHAN0_SLOTS_MASK | | |
2698 | WM8915_AIF2RX_CHAN0_START_SLOT_MASK, | |
2699 | 1 << WM8915_AIF2RX_CHAN0_SLOTS_SHIFT | 0); | |
2700 | snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_1_CONFIGURATION, | |
2701 | WM8915_AIF2RX_CHAN1_SLOTS_MASK | | |
2702 | WM8915_AIF2RX_CHAN1_START_SLOT_MASK, | |
2703 | 1 << WM8915_AIF2RX_CHAN1_SLOTS_SHIFT | 1); | |
2704 | ||
2705 | snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_0_CONFIGURATION, | |
2706 | WM8915_AIF1TX_CHAN0_SLOTS_MASK | | |
2707 | WM8915_AIF1TX_CHAN0_START_SLOT_MASK, | |
2708 | 1 << WM8915_AIF1TX_CHAN0_SLOTS_SHIFT | 0); | |
2709 | snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION, | |
2710 | WM8915_AIF1TX_CHAN1_SLOTS_MASK | | |
2711 | WM8915_AIF1TX_CHAN0_START_SLOT_MASK, | |
2712 | 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1); | |
2713 | snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_2_CONFIGURATION, | |
2714 | WM8915_AIF1TX_CHAN2_SLOTS_MASK | | |
2715 | WM8915_AIF1TX_CHAN0_START_SLOT_MASK, | |
2716 | 1 << WM8915_AIF1TX_CHAN2_SLOTS_SHIFT | 0); | |
2717 | snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_3_CONFIGURATION, | |
2718 | WM8915_AIF1TX_CHAN3_SLOTS_MASK | | |
2719 | WM8915_AIF1TX_CHAN0_START_SLOT_MASK, | |
2720 | 1 << WM8915_AIF1TX_CHAN3_SLOTS_SHIFT | 1); | |
2721 | snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_4_CONFIGURATION, | |
2722 | WM8915_AIF1TX_CHAN4_SLOTS_MASK | | |
2723 | WM8915_AIF1TX_CHAN0_START_SLOT_MASK, | |
2724 | 1 << WM8915_AIF1TX_CHAN4_SLOTS_SHIFT | 0); | |
2725 | snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_5_CONFIGURATION, | |
2726 | WM8915_AIF1TX_CHAN5_SLOTS_MASK | | |
2727 | WM8915_AIF1TX_CHAN0_START_SLOT_MASK, | |
2728 | 1 << WM8915_AIF1TX_CHAN5_SLOTS_SHIFT | 1); | |
2729 | ||
2730 | snd_soc_update_bits(codec, WM8915_AIF2TX_CHANNEL_0_CONFIGURATION, | |
2731 | WM8915_AIF2TX_CHAN0_SLOTS_MASK | | |
2732 | WM8915_AIF2TX_CHAN0_START_SLOT_MASK, | |
2733 | 1 << WM8915_AIF2TX_CHAN0_SLOTS_SHIFT | 0); | |
2734 | snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION, | |
2735 | WM8915_AIF2TX_CHAN1_SLOTS_MASK | | |
2736 | WM8915_AIF2TX_CHAN1_START_SLOT_MASK, | |
2737 | 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1); | |
2738 | ||
2739 | if (wm8915->pdata.num_retune_mobile_cfgs) | |
2740 | wm8915_retune_mobile_pdata(codec); | |
2741 | else | |
2742 | snd_soc_add_controls(codec, wm8915_eq_controls, | |
2743 | ARRAY_SIZE(wm8915_eq_controls)); | |
2744 | ||
2745 | /* If the TX LRCLK pins are not in LRCLK mode configure the | |
2746 | * AIFs to source their clocks from the RX LRCLKs. | |
2747 | */ | |
2748 | if ((snd_soc_read(codec, WM8915_GPIO_1))) | |
2749 | snd_soc_update_bits(codec, WM8915_AIF1_TX_LRCLK_2, | |
2750 | WM8915_AIF1TX_LRCLK_MODE, | |
2751 | WM8915_AIF1TX_LRCLK_MODE); | |
2752 | ||
2753 | if ((snd_soc_read(codec, WM8915_GPIO_2))) | |
2754 | snd_soc_update_bits(codec, WM8915_AIF2_TX_LRCLK_2, | |
2755 | WM8915_AIF2TX_LRCLK_MODE, | |
2756 | WM8915_AIF2TX_LRCLK_MODE); | |
2757 | ||
2758 | regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies); | |
2759 | ||
2760 | wm8915_init_gpio(codec); | |
2761 | ||
2762 | if (i2c->irq) { | |
2763 | if (wm8915->pdata.irq_flags) | |
2764 | irq_flags = wm8915->pdata.irq_flags; | |
2765 | else | |
2766 | irq_flags = IRQF_TRIGGER_LOW; | |
2767 | ||
2768 | irq_flags |= IRQF_ONESHOT; | |
2769 | ||
a1e9adc0 MB |
2770 | if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) |
2771 | ret = request_threaded_irq(i2c->irq, NULL, | |
2772 | wm8915_edge_irq, | |
2773 | irq_flags, "wm8915", codec); | |
2774 | else | |
2775 | ret = request_threaded_irq(i2c->irq, NULL, wm8915_irq, | |
2776 | irq_flags, "wm8915", codec); | |
2777 | ||
c93993ac MB |
2778 | if (ret == 0) { |
2779 | /* Unmask the interrupt */ | |
2780 | snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL, | |
2781 | WM8915_IM_IRQ, 0); | |
2782 | ||
2783 | /* Enable error reporting and DC servo status */ | |
2784 | snd_soc_update_bits(codec, | |
2785 | WM8915_INTERRUPT_STATUS_2_MASK, | |
2786 | WM8915_IM_DCS_DONE_23_EINT | | |
2787 | WM8915_IM_DCS_DONE_01_EINT | | |
2788 | WM8915_IM_FLL_LOCK_EINT | | |
2789 | WM8915_IM_FIFOS_ERR_EINT, | |
2790 | 0); | |
2791 | } else { | |
2792 | dev_err(codec->dev, "Failed to request IRQ: %d\n", | |
2793 | ret); | |
2794 | } | |
2795 | } | |
2796 | ||
2797 | return 0; | |
2798 | ||
2799 | err_enable: | |
2800 | if (wm8915->pdata.ldo_ena >= 0) | |
2801 | gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0); | |
2802 | ||
2803 | regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies); | |
2804 | err_get: | |
2805 | regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies); | |
2806 | err: | |
2807 | return ret; | |
2808 | } | |
2809 | ||
2810 | static int wm8915_remove(struct snd_soc_codec *codec) | |
2811 | { | |
2812 | struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); | |
2813 | struct i2c_client *i2c = to_i2c_client(codec->dev); | |
2814 | int i; | |
2815 | ||
2816 | snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL, | |
2817 | WM8915_IM_IRQ, WM8915_IM_IRQ); | |
2818 | ||
2819 | if (i2c->irq) | |
2820 | free_irq(i2c->irq, codec); | |
2821 | ||
2822 | wm8915_free_gpio(codec); | |
2823 | ||
2824 | for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) | |
2825 | regulator_unregister_notifier(wm8915->supplies[i].consumer, | |
2826 | &wm8915->disable_nb[i]); | |
2827 | regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies); | |
2828 | ||
2829 | return 0; | |
2830 | } | |
2831 | ||
2832 | static struct snd_soc_codec_driver soc_codec_dev_wm8915 = { | |
2833 | .probe = wm8915_probe, | |
2834 | .remove = wm8915_remove, | |
2835 | .set_bias_level = wm8915_set_bias_level, | |
2836 | .seq_notifier = wm8915_seq_notifier, | |
2837 | .reg_cache_size = WM8915_MAX_REGISTER + 1, | |
2838 | .reg_word_size = sizeof(u16), | |
2839 | .reg_cache_default = wm8915_reg, | |
2840 | .volatile_register = wm8915_volatile_register, | |
2841 | .readable_register = wm8915_readable_register, | |
2842 | .compress_type = SND_SOC_RBTREE_COMPRESSION, | |
2843 | .controls = wm8915_snd_controls, | |
2844 | .num_controls = ARRAY_SIZE(wm8915_snd_controls), | |
2845 | .dapm_widgets = wm8915_dapm_widgets, | |
2846 | .num_dapm_widgets = ARRAY_SIZE(wm8915_dapm_widgets), | |
2847 | .dapm_routes = wm8915_dapm_routes, | |
2848 | .num_dapm_routes = ARRAY_SIZE(wm8915_dapm_routes), | |
01b07e2d | 2849 | .set_pll = wm8915_set_fll, |
c93993ac MB |
2850 | }; |
2851 | ||
2852 | #define WM8915_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ | |
2853 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) | |
2854 | #define WM8915_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ | |
2855 | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ | |
2856 | SNDRV_PCM_FMTBIT_S32_LE) | |
2857 | ||
2858 | static struct snd_soc_dai_ops wm8915_dai_ops = { | |
2859 | .set_fmt = wm8915_set_fmt, | |
2860 | .hw_params = wm8915_hw_params, | |
2861 | .set_sysclk = wm8915_set_sysclk, | |
c93993ac MB |
2862 | }; |
2863 | ||
2864 | static struct snd_soc_dai_driver wm8915_dai[] = { | |
2865 | { | |
2866 | .name = "wm8915-aif1", | |
2867 | .playback = { | |
2868 | .stream_name = "AIF1 Playback", | |
2869 | .channels_min = 1, | |
2870 | .channels_max = 6, | |
2871 | .rates = WM8915_RATES, | |
2872 | .formats = WM8915_FORMATS, | |
2873 | }, | |
2874 | .capture = { | |
2875 | .stream_name = "AIF1 Capture", | |
2876 | .channels_min = 1, | |
2877 | .channels_max = 6, | |
2878 | .rates = WM8915_RATES, | |
2879 | .formats = WM8915_FORMATS, | |
2880 | }, | |
2881 | .ops = &wm8915_dai_ops, | |
2882 | }, | |
2883 | { | |
2884 | .name = "wm8915-aif2", | |
2885 | .playback = { | |
2886 | .stream_name = "AIF2 Playback", | |
2887 | .channels_min = 1, | |
2888 | .channels_max = 2, | |
2889 | .rates = WM8915_RATES, | |
2890 | .formats = WM8915_FORMATS, | |
2891 | }, | |
2892 | .capture = { | |
2893 | .stream_name = "AIF2 Capture", | |
2894 | .channels_min = 1, | |
2895 | .channels_max = 2, | |
2896 | .rates = WM8915_RATES, | |
2897 | .formats = WM8915_FORMATS, | |
2898 | }, | |
2899 | .ops = &wm8915_dai_ops, | |
2900 | }, | |
2901 | }; | |
2902 | ||
2903 | static __devinit int wm8915_i2c_probe(struct i2c_client *i2c, | |
2904 | const struct i2c_device_id *id) | |
2905 | { | |
2906 | struct wm8915_priv *wm8915; | |
2907 | int ret; | |
2908 | ||
2909 | wm8915 = kzalloc(sizeof(struct wm8915_priv), GFP_KERNEL); | |
2910 | if (wm8915 == NULL) | |
2911 | return -ENOMEM; | |
2912 | ||
2913 | i2c_set_clientdata(i2c, wm8915); | |
2914 | ||
2915 | if (dev_get_platdata(&i2c->dev)) | |
2916 | memcpy(&wm8915->pdata, dev_get_platdata(&i2c->dev), | |
2917 | sizeof(wm8915->pdata)); | |
2918 | ||
2919 | if (wm8915->pdata.ldo_ena > 0) { | |
2920 | ret = gpio_request_one(wm8915->pdata.ldo_ena, | |
2921 | GPIOF_OUT_INIT_LOW, "WM8915 ENA"); | |
2922 | if (ret < 0) { | |
2923 | dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n", | |
2924 | wm8915->pdata.ldo_ena, ret); | |
2925 | goto err; | |
2926 | } | |
2927 | } | |
2928 | ||
2929 | ret = snd_soc_register_codec(&i2c->dev, | |
2930 | &soc_codec_dev_wm8915, wm8915_dai, | |
2931 | ARRAY_SIZE(wm8915_dai)); | |
2932 | if (ret < 0) | |
2933 | goto err_gpio; | |
2934 | ||
2935 | return ret; | |
2936 | ||
2937 | err_gpio: | |
2938 | if (wm8915->pdata.ldo_ena > 0) | |
2939 | gpio_free(wm8915->pdata.ldo_ena); | |
2940 | err: | |
2941 | kfree(wm8915); | |
2942 | ||
2943 | return ret; | |
2944 | } | |
2945 | ||
2946 | static __devexit int wm8915_i2c_remove(struct i2c_client *client) | |
2947 | { | |
2948 | struct wm8915_priv *wm8915 = i2c_get_clientdata(client); | |
2949 | ||
2950 | snd_soc_unregister_codec(&client->dev); | |
2951 | if (wm8915->pdata.ldo_ena > 0) | |
2952 | gpio_free(wm8915->pdata.ldo_ena); | |
2953 | kfree(i2c_get_clientdata(client)); | |
2954 | return 0; | |
2955 | } | |
2956 | ||
2957 | static const struct i2c_device_id wm8915_i2c_id[] = { | |
2958 | { "wm8915", 0 }, | |
2959 | { } | |
2960 | }; | |
2961 | MODULE_DEVICE_TABLE(i2c, wm8915_i2c_id); | |
2962 | ||
2963 | static struct i2c_driver wm8915_i2c_driver = { | |
2964 | .driver = { | |
2965 | .name = "wm8915", | |
2966 | .owner = THIS_MODULE, | |
2967 | }, | |
2968 | .probe = wm8915_i2c_probe, | |
2969 | .remove = __devexit_p(wm8915_i2c_remove), | |
2970 | .id_table = wm8915_i2c_id, | |
2971 | }; | |
2972 | ||
2973 | static int __init wm8915_modinit(void) | |
2974 | { | |
2975 | int ret; | |
2976 | ||
2977 | ret = i2c_add_driver(&wm8915_i2c_driver); | |
2978 | if (ret != 0) { | |
2979 | printk(KERN_ERR "Failed to register WM8915 I2C driver: %d\n", | |
2980 | ret); | |
2981 | } | |
2982 | ||
2983 | return ret; | |
2984 | } | |
2985 | module_init(wm8915_modinit); | |
2986 | ||
2987 | static void __exit wm8915_exit(void) | |
2988 | { | |
2989 | i2c_del_driver(&wm8915_i2c_driver); | |
2990 | } | |
2991 | module_exit(wm8915_exit); | |
2992 | ||
2993 | MODULE_DESCRIPTION("ASoC WM8915 driver"); | |
2994 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
2995 | MODULE_LICENSE("GPL"); |