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d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
f701a2e5
MB
2/*
3 * wm8958-dsp2.c -- WM8958 DSP2 support
4 *
5 * Copyright 2011 Wolfson Microelectronics plc
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
f701a2e5
MB
8 */
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/pm.h>
15#include <linux/i2c.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18#include <sound/soc.h>
19#include <sound/initval.h>
20#include <sound/tlv.h>
21#include <trace/events/asoc.h>
22
23#include <linux/mfd/wm8994/core.h>
24#include <linux/mfd/wm8994/registers.h>
25#include <linux/mfd/wm8994/pdata.h>
26#include <linux/mfd/wm8994/gpio.h>
27
3ad00f6a
BDC
28#include <asm/unaligned.h>
29
f701a2e5
MB
30#include "wm8994.h"
31
fbbf5920
MB
32#define WM_FW_BLOCK_INFO 0xff
33#define WM_FW_BLOCK_PM 0x00
34#define WM_FW_BLOCK_X 0x01
35#define WM_FW_BLOCK_Y 0x02
36#define WM_FW_BLOCK_Z 0x03
37#define WM_FW_BLOCK_I 0x06
38#define WM_FW_BLOCK_A 0x08
39#define WM_FW_BLOCK_C 0x0c
40
00a6941c 41static int wm8958_dsp2_fw(struct snd_soc_component *component, const char *name,
fbbf5920
MB
42 const struct firmware *fw, bool check)
43{
00a6941c 44 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
fbbf5920
MB
45 u64 data64;
46 u32 data32;
47 const u8 *data;
48 char *str;
49 size_t block_len, len;
50 int ret = 0;
51
52 /* Suppress unneeded downloads */
53 if (wm8994->cur_fw == fw)
54 return 0;
55
56 if (fw->size < 32) {
00a6941c 57 dev_err(component->dev, "%s: firmware too short (%zd bytes)\n",
086834e2 58 name, fw->size);
fbbf5920
MB
59 goto err;
60 }
61
62 if (memcmp(fw->data, "WMFW", 4) != 0) {
3ad00f6a 63 data32 = get_unaligned_be32(fw->data);
00a6941c 64 dev_err(component->dev, "%s: firmware has bad file magic %08x\n",
fbbf5920
MB
65 name, data32);
66 goto err;
67 }
68
3ad00f6a
BDC
69 len = get_unaligned_be32(fw->data + 4);
70 data32 = get_unaligned_be32(fw->data + 8);
fbbf5920 71
fbbf5920 72 if ((data32 >> 24) & 0xff) {
00a6941c 73 dev_err(component->dev, "%s: unsupported firmware version %d\n",
fbbf5920
MB
74 name, (data32 >> 24) & 0xff);
75 goto err;
76 }
77 if ((data32 & 0xffff) != 8958) {
00a6941c 78 dev_err(component->dev, "%s: unsupported target device %d\n",
fbbf5920
MB
79 name, data32 & 0xffff);
80 goto err;
81 }
82 if (((data32 >> 16) & 0xff) != 0xc) {
00a6941c 83 dev_err(component->dev, "%s: unsupported target core %d\n",
fbbf5920
MB
84 name, (data32 >> 16) & 0xff);
85 goto err;
86 }
87
88 if (check) {
3ad00f6a
BDC
89 data64 = get_unaligned_be64(fw->data + 24);
90 dev_info(component->dev, "%s timestamp %llx\n", name, data64);
fbbf5920 91 } else {
00a6941c
KM
92 snd_soc_component_write(component, 0x102, 0x2);
93 snd_soc_component_write(component, 0x900, 0x2);
fbbf5920
MB
94 }
95
96 data = fw->data + len;
97 len = fw->size - len;
98 while (len) {
99 if (len < 12) {
00a6941c 100 dev_err(component->dev, "%s short data block of %zd\n",
fbbf5920
MB
101 name, len);
102 goto err;
103 }
104
3ad00f6a 105 block_len = get_unaligned_be32(data + 4);
fbbf5920 106 if (block_len + 8 > len) {
00a6941c 107 dev_err(component->dev, "%zd byte block longer than file\n",
fbbf5920
MB
108 block_len);
109 goto err;
110 }
111 if (block_len == 0) {
00a6941c 112 dev_err(component->dev, "Zero length block\n");
fbbf5920
MB
113 goto err;
114 }
115
3ad00f6a 116 data32 = get_unaligned_be32(data);
fbbf5920
MB
117
118 switch ((data32 >> 24) & 0xff) {
119 case WM_FW_BLOCK_INFO:
120 /* Informational text */
121 if (!check)
122 break;
123
124 str = kzalloc(block_len + 1, GFP_KERNEL);
125 if (str) {
126 memcpy(str, data + 8, block_len);
00a6941c 127 dev_info(component->dev, "%s: %s\n", name, str);
fbbf5920
MB
128 kfree(str);
129 } else {
00a6941c 130 dev_err(component->dev, "Out of memory\n");
fbbf5920
MB
131 }
132 break;
133 case WM_FW_BLOCK_PM:
134 case WM_FW_BLOCK_X:
135 case WM_FW_BLOCK_Y:
136 case WM_FW_BLOCK_Z:
137 case WM_FW_BLOCK_I:
138 case WM_FW_BLOCK_A:
139 case WM_FW_BLOCK_C:
00a6941c 140 dev_dbg(component->dev, "%s: %zd bytes of %x@%x\n", name,
fbbf5920
MB
141 block_len, (data32 >> 24) & 0xff,
142 data32 & 0xffffff);
143
144 if (check)
145 break;
146
147 data32 &= 0xffffff;
148
548da08f 149 wm8994_bulk_write(wm8994->wm8994,
fbbf5920
MB
150 data32 & 0xffffff,
151 block_len / 2,
152 (void *)(data + 8));
153
154 break;
155 default:
00a6941c 156 dev_warn(component->dev, "%s: unknown block type %d\n",
fbbf5920
MB
157 name, (data32 >> 24) & 0xff);
158 break;
159 }
160
161 /* Round up to the next 32 bit word */
162 block_len += block_len % 4;
163
164 data += block_len + 8;
165 len -= block_len + 8;
166 }
167
168 if (!check) {
00a6941c 169 dev_dbg(component->dev, "%s: download done\n", name);
fbbf5920
MB
170 wm8994->cur_fw = fw;
171 } else {
00a6941c 172 dev_info(component->dev, "%s: got firmware\n", name);
fbbf5920
MB
173 }
174
175 goto ok;
176
177err:
178 ret = -EINVAL;
179ok:
180 if (!check) {
00a6941c
KM
181 snd_soc_component_write(component, 0x900, 0x0);
182 snd_soc_component_write(component, 0x102, 0x0);
fbbf5920
MB
183 }
184
185 return ret;
186}
187
00a6941c 188static void wm8958_dsp_start_mbc(struct snd_soc_component *component, int path)
f701a2e5 189{
00a6941c 190 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
d9dd4ada 191 struct wm8994 *control = wm8994->wm8994;
fbbf5920
MB
192 int i;
193
194 /* If the DSP is already running then noop */
00a6941c 195 if (snd_soc_component_read32(component, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
fbbf5920
MB
196 return;
197
198 /* If we have MBC firmware download it */
199 if (wm8994->mbc)
00a6941c 200 wm8958_dsp2_fw(component, "MBC", wm8994->mbc, false);
fbbf5920 201
00a6941c 202 snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
fbbf5920
MB
203 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
204
205 /* If we've got user supplied MBC settings use them */
d9dd4ada 206 if (control->pdata.num_mbc_cfgs) {
fbbf5920 207 struct wm8958_mbc_cfg *cfg
d9dd4ada 208 = &control->pdata.mbc_cfgs[wm8994->mbc_cfg];
fbbf5920
MB
209
210 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
00a6941c 211 snd_soc_component_write(component, i + WM8958_MBC_BAND_1_K_1,
fbbf5920
MB
212 cfg->coeff_regs[i]);
213
214 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
00a6941c 215 snd_soc_component_write(component,
fbbf5920
MB
216 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
217 cfg->cutoff_regs[i]);
218 }
219
220 /* Run the DSP */
00a6941c 221 snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
fbbf5920
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222 WM8958_DSP2_RUNR);
223
224 /* And we're off! */
00a6941c 225 snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
fbbf5920
MB
226 WM8958_MBC_ENA |
227 WM8958_MBC_SEL_MASK,
228 path << WM8958_MBC_SEL_SHIFT |
229 WM8958_MBC_ENA);
230}
231
00a6941c 232static void wm8958_dsp_start_vss(struct snd_soc_component *component, int path)
09e10d7f 233{
00a6941c 234 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
d9dd4ada 235 struct wm8994 *control = wm8994->wm8994;
09e10d7f
MB
236 int i, ena;
237
238 if (wm8994->mbc_vss)
00a6941c 239 wm8958_dsp2_fw(component, "MBC+VSS", wm8994->mbc_vss, false);
09e10d7f 240
00a6941c 241 snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
09e10d7f
MB
242 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
243
244 /* If we've got user supplied settings use them */
d9dd4ada 245 if (control->pdata.num_mbc_cfgs) {
09e10d7f 246 struct wm8958_mbc_cfg *cfg
d9dd4ada 247 = &control->pdata.mbc_cfgs[wm8994->mbc_cfg];
09e10d7f
MB
248
249 for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
00a6941c 250 snd_soc_component_write(component, i + 0x2800,
09e10d7f
MB
251 cfg->combined_regs[i]);
252 }
253
d9dd4ada 254 if (control->pdata.num_vss_cfgs) {
09e10d7f 255 struct wm8958_vss_cfg *cfg
d9dd4ada 256 = &control->pdata.vss_cfgs[wm8994->vss_cfg];
09e10d7f
MB
257
258 for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
00a6941c 259 snd_soc_component_write(component, i + 0x2600, cfg->regs[i]);
09e10d7f
MB
260 }
261
d9dd4ada 262 if (control->pdata.num_vss_hpf_cfgs) {
09e10d7f 263 struct wm8958_vss_hpf_cfg *cfg
d9dd4ada 264 = &control->pdata.vss_hpf_cfgs[wm8994->vss_hpf_cfg];
09e10d7f
MB
265
266 for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
00a6941c 267 snd_soc_component_write(component, i + 0x2400, cfg->regs[i]);
09e10d7f
MB
268 }
269
270 /* Run the DSP */
00a6941c 271 snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
09e10d7f
MB
272 WM8958_DSP2_RUNR);
273
274 /* Enable the algorithms we've selected */
275 ena = 0;
276 if (wm8994->mbc_ena[path])
277 ena |= 0x8;
278 if (wm8994->hpf2_ena[path])
279 ena |= 0x4;
280 if (wm8994->hpf1_ena[path])
281 ena |= 0x2;
282 if (wm8994->vss_ena[path])
283 ena |= 0x1;
284
00a6941c 285 snd_soc_component_write(component, 0x2201, ena);
09e10d7f
MB
286
287 /* Switch the DSP into the data path */
00a6941c 288 snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
09e10d7f
MB
289 WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
290 path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
291}
292
00a6941c 293static void wm8958_dsp_start_enh_eq(struct snd_soc_component *component, int path)
31215871 294{
00a6941c 295 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
d9dd4ada 296 struct wm8994 *control = wm8994->wm8994;
31215871
MB
297 int i;
298
00a6941c 299 wm8958_dsp2_fw(component, "ENH_EQ", wm8994->enh_eq, false);
31215871 300
00a6941c 301 snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
31215871
MB
302 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
303
304 /* If we've got user supplied settings use them */
d9dd4ada 305 if (control->pdata.num_enh_eq_cfgs) {
31215871 306 struct wm8958_enh_eq_cfg *cfg
d9dd4ada 307 = &control->pdata.enh_eq_cfgs[wm8994->enh_eq_cfg];
31215871
MB
308
309 for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
00a6941c 310 snd_soc_component_write(component, i + 0x2200,
31215871
MB
311 cfg->regs[i]);
312 }
313
314 /* Run the DSP */
00a6941c 315 snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
31215871
MB
316 WM8958_DSP2_RUNR);
317
318 /* Switch the DSP into the data path */
00a6941c 319 snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
31215871
MB
320 WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
321 path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
322}
09e10d7f 323
00a6941c 324static void wm8958_dsp_apply(struct snd_soc_component *component, int path, int start)
fbbf5920 325{
00a6941c
KM
326 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
327 int pwr_reg = snd_soc_component_read32(component, WM8994_POWER_MANAGEMENT_5);
f20d77ce 328 int ena, reg, aif;
f701a2e5 329
f20d77ce 330 switch (path) {
f701a2e5
MB
331 case 0:
332 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
333 aif = 0;
334 break;
335 case 1:
336 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
337 aif = 0;
338 break;
339 case 2:
340 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
341 aif = 1;
342 break;
343 default:
a845d59d 344 WARN(1, "Invalid path %d\n", path);
f701a2e5
MB
345 return;
346 }
347
f20d77ce 348 /* Do we have both an active AIF and an active algorithm? */
09e10d7f 349 ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
31215871
MB
350 wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
351 wm8994->enh_eq_ena[path];
f20d77ce
MB
352 if (!pwr_reg)
353 ena = 0;
f701a2e5 354
00a6941c 355 reg = snd_soc_component_read32(component, WM8958_DSP2_PROGRAM);
f701a2e5 356
00a6941c 357 dev_dbg(component->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
f20d77ce 358 path, wm8994->dsp_active, start, pwr_reg, reg);
f701a2e5
MB
359
360 if (start && ena) {
fa63e477
MB
361 /* If the DSP is already running then noop */
362 if (reg & WM8958_DSP2_ENA)
363 return;
364
f20d77ce 365 /* If either AIFnCLK is not yet enabled postpone */
00a6941c 366 if (!(snd_soc_component_read32(component, WM8994_AIF1_CLOCKING_1)
c6b7b570 367 & WM8994_AIF1CLK_ENA_MASK) &&
00a6941c 368 !(snd_soc_component_read32(component, WM8994_AIF2_CLOCKING_1)
c6b7b570
MB
369 & WM8994_AIF2CLK_ENA_MASK))
370 return;
371
f701a2e5 372 /* Switch the clock over to the appropriate AIF */
00a6941c 373 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
f701a2e5
MB
374 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
375 aif << WM8958_DSP2CLK_SRC_SHIFT |
376 WM8958_DSP2CLK_ENA);
377
31215871 378 if (wm8994->enh_eq_ena[path])
00a6941c 379 wm8958_dsp_start_enh_eq(component, path);
31215871 380 else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
09e10d7f 381 wm8994->hpf2_ena[path])
00a6941c 382 wm8958_dsp_start_vss(component, path);
09e10d7f 383 else if (wm8994->mbc_ena[path])
00a6941c 384 wm8958_dsp_start_mbc(component, path);
f701a2e5 385
09e10d7f
MB
386 wm8994->dsp_active = path;
387
00a6941c 388 dev_dbg(component->dev, "DSP running in path %d\n", path);
09e10d7f
MB
389 }
390
391 if (!start && wm8994->dsp_active == path) {
f701a2e5
MB
392 /* If the DSP is already stopped then noop */
393 if (!(reg & WM8958_DSP2_ENA))
394 return;
395
00a6941c 396 snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
f701a2e5 397 WM8958_MBC_ENA, 0);
00a6941c 398 snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
f20d77ce 399 WM8958_DSP2_STOP);
00a6941c 400 snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
f701a2e5 401 WM8958_DSP2_ENA, 0);
00a6941c 402 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
f701a2e5 403 WM8958_DSP2CLK_ENA, 0);
f20d77ce
MB
404
405 wm8994->dsp_active = -1;
406
00a6941c 407 dev_dbg(component->dev, "DSP stopped\n");
f701a2e5
MB
408 }
409}
410
411int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
412 struct snd_kcontrol *kcontrol, int event)
413{
00a6941c 414 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
c6b7b570 415 int i;
f701a2e5
MB
416
417 switch (event) {
418 case SND_SOC_DAPM_POST_PMU:
c6b7b570
MB
419 case SND_SOC_DAPM_PRE_PMU:
420 for (i = 0; i < 3; i++)
00a6941c 421 wm8958_dsp_apply(component, i, 1);
f701a2e5
MB
422 break;
423 case SND_SOC_DAPM_POST_PMD:
c6b7b570
MB
424 case SND_SOC_DAPM_PRE_PMD:
425 for (i = 0; i < 3; i++)
00a6941c 426 wm8958_dsp_apply(component, i, 0);
f701a2e5
MB
427 break;
428 }
429
430 return 0;
431}
432
f20d77ce
MB
433/* Check if DSP2 is in use on another AIF */
434static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
435{
436 int i;
437
438 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
439 if (i == aif)
440 continue;
09e10d7f
MB
441 if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
442 wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
f20d77ce
MB
443 return 1;
444 }
445
446 return 0;
447}
448
f701a2e5
MB
449static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
450 struct snd_ctl_elem_value *ucontrol)
451{
00a6941c
KM
452 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
453 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
d9dd4ada 454 struct wm8994 *control = wm8994->wm8994;
d0784829 455 int value = ucontrol->value.enumerated.item[0];
f701a2e5
MB
456 int reg;
457
458 /* Don't allow on the fly reconfiguration */
00a6941c 459 reg = snd_soc_component_read32(component, WM8994_CLOCKING_1);
f701a2e5
MB
460 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
461 return -EBUSY;
462
d9dd4ada 463 if (value >= control->pdata.num_mbc_cfgs)
f701a2e5
MB
464 return -EINVAL;
465
466 wm8994->mbc_cfg = value;
467
468 return 0;
469}
470
471static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
472 struct snd_ctl_elem_value *ucontrol)
473{
00a6941c
KM
474 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
475 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
f701a2e5
MB
476
477 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
478
479 return 0;
480}
481
482static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
483 struct snd_ctl_elem_info *uinfo)
484{
485 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
486 uinfo->count = 1;
487 uinfo->value.integer.min = 0;
488 uinfo->value.integer.max = 1;
489 return 0;
490}
491
492static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
493 struct snd_ctl_elem_value *ucontrol)
494{
495 int mbc = kcontrol->private_value;
00a6941c
KM
496 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
497 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
f701a2e5
MB
498
499 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
500
501 return 0;
502}
503
504static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506{
507 int mbc = kcontrol->private_value;
00a6941c
KM
508 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
509 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
f701a2e5 510
d7fdae7c
MB
511 if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
512 return 0;
513
f701a2e5
MB
514 if (ucontrol->value.integer.value[0] > 1)
515 return -EINVAL;
516
f20d77ce 517 if (wm8958_dsp2_busy(wm8994, mbc)) {
00a6941c 518 dev_dbg(component->dev, "DSP2 active on %d already\n", mbc);
f20d77ce 519 return -EBUSY;
f701a2e5
MB
520 }
521
31215871
MB
522 if (wm8994->enh_eq_ena[mbc])
523 return -EBUSY;
524
f701a2e5
MB
525 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
526
00a6941c 527 wm8958_dsp_apply(component, mbc, wm8994->mbc_ena[mbc]);
f701a2e5
MB
528
529 return 0;
530}
531
532#define WM8958_MBC_SWITCH(xname, xval) {\
533 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
534 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
535 .info = wm8958_mbc_info, \
536 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
537 .private_value = xval }
538
09e10d7f
MB
539static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
540 struct snd_ctl_elem_value *ucontrol)
541{
00a6941c
KM
542 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
543 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
d9dd4ada 544 struct wm8994 *control = wm8994->wm8994;
d0784829 545 int value = ucontrol->value.enumerated.item[0];
09e10d7f
MB
546 int reg;
547
548 /* Don't allow on the fly reconfiguration */
00a6941c 549 reg = snd_soc_component_read32(component, WM8994_CLOCKING_1);
09e10d7f
MB
550 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
551 return -EBUSY;
552
d9dd4ada 553 if (value >= control->pdata.num_vss_cfgs)
09e10d7f
MB
554 return -EINVAL;
555
556 wm8994->vss_cfg = value;
557
558 return 0;
559}
560
561static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
562 struct snd_ctl_elem_value *ucontrol)
563{
00a6941c
KM
564 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
565 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
09e10d7f
MB
566
567 ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
568
569 return 0;
570}
571
572static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
573 struct snd_ctl_elem_value *ucontrol)
574{
00a6941c
KM
575 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
576 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
d9dd4ada 577 struct wm8994 *control = wm8994->wm8994;
d0784829 578 int value = ucontrol->value.enumerated.item[0];
09e10d7f
MB
579 int reg;
580
581 /* Don't allow on the fly reconfiguration */
00a6941c 582 reg = snd_soc_component_read32(component, WM8994_CLOCKING_1);
09e10d7f
MB
583 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
584 return -EBUSY;
585
d9dd4ada 586 if (value >= control->pdata.num_vss_hpf_cfgs)
09e10d7f
MB
587 return -EINVAL;
588
589 wm8994->vss_hpf_cfg = value;
590
591 return 0;
592}
593
594static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
595 struct snd_ctl_elem_value *ucontrol)
596{
00a6941c
KM
597 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
598 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
09e10d7f
MB
599
600 ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
601
602 return 0;
603}
604
605static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
606 struct snd_ctl_elem_info *uinfo)
607{
608 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
609 uinfo->count = 1;
610 uinfo->value.integer.min = 0;
611 uinfo->value.integer.max = 1;
612 return 0;
613}
614
615static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
616 struct snd_ctl_elem_value *ucontrol)
617{
618 int vss = kcontrol->private_value;
00a6941c
KM
619 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
620 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
09e10d7f
MB
621
622 ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
623
624 return 0;
625}
626
627static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
628 struct snd_ctl_elem_value *ucontrol)
629{
630 int vss = kcontrol->private_value;
00a6941c
KM
631 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
632 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
09e10d7f 633
d7fdae7c
MB
634 if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
635 return 0;
636
09e10d7f
MB
637 if (ucontrol->value.integer.value[0] > 1)
638 return -EINVAL;
639
640 if (!wm8994->mbc_vss)
641 return -ENODEV;
642
643 if (wm8958_dsp2_busy(wm8994, vss)) {
00a6941c 644 dev_dbg(component->dev, "DSP2 active on %d already\n", vss);
09e10d7f
MB
645 return -EBUSY;
646 }
647
31215871
MB
648 if (wm8994->enh_eq_ena[vss])
649 return -EBUSY;
650
09e10d7f
MB
651 wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
652
00a6941c 653 wm8958_dsp_apply(component, vss, wm8994->vss_ena[vss]);
09e10d7f
MB
654
655 return 0;
656}
657
658
659#define WM8958_VSS_SWITCH(xname, xval) {\
660 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
661 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
662 .info = wm8958_vss_info, \
663 .get = wm8958_vss_get, .put = wm8958_vss_put, \
664 .private_value = xval }
665
666static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
667 struct snd_ctl_elem_info *uinfo)
668{
669 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
670 uinfo->count = 1;
671 uinfo->value.integer.min = 0;
672 uinfo->value.integer.max = 1;
673 return 0;
674}
675
676static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
677 struct snd_ctl_elem_value *ucontrol)
678{
679 int hpf = kcontrol->private_value;
00a6941c
KM
680 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
681 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
09e10d7f
MB
682
683 if (hpf < 3)
684 ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
685 else
686 ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
687
688 return 0;
689}
690
691static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
692 struct snd_ctl_elem_value *ucontrol)
693{
694 int hpf = kcontrol->private_value;
00a6941c
KM
695 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
696 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
09e10d7f 697
d7fdae7c
MB
698 if (hpf < 3) {
699 if (wm8994->hpf1_ena[hpf % 3] ==
700 ucontrol->value.integer.value[0])
701 return 0;
702 } else {
703 if (wm8994->hpf2_ena[hpf % 3] ==
704 ucontrol->value.integer.value[0])
705 return 0;
706 }
707
09e10d7f
MB
708 if (ucontrol->value.integer.value[0] > 1)
709 return -EINVAL;
710
711 if (!wm8994->mbc_vss)
712 return -ENODEV;
713
714 if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
00a6941c 715 dev_dbg(component->dev, "DSP2 active on %d already\n", hpf);
09e10d7f
MB
716 return -EBUSY;
717 }
718
31215871 719 if (wm8994->enh_eq_ena[hpf % 3])
09e10d7f
MB
720 return -EBUSY;
721
722 if (hpf < 3)
723 wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
724 else
725 wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
726
00a6941c 727 wm8958_dsp_apply(component, hpf % 3, ucontrol->value.integer.value[0]);
09e10d7f
MB
728
729 return 0;
730}
731
732#define WM8958_HPF_SWITCH(xname, xval) {\
733 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
734 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
735 .info = wm8958_hpf_info, \
736 .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
737 .private_value = xval }
738
31215871
MB
739static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
740 struct snd_ctl_elem_value *ucontrol)
741{
00a6941c
KM
742 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
743 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
d9dd4ada 744 struct wm8994 *control = wm8994->wm8994;
d0784829 745 int value = ucontrol->value.enumerated.item[0];
31215871
MB
746 int reg;
747
748 /* Don't allow on the fly reconfiguration */
00a6941c 749 reg = snd_soc_component_read32(component, WM8994_CLOCKING_1);
31215871
MB
750 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
751 return -EBUSY;
752
d9dd4ada 753 if (value >= control->pdata.num_enh_eq_cfgs)
31215871
MB
754 return -EINVAL;
755
756 wm8994->enh_eq_cfg = value;
757
758 return 0;
759}
760
761static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
762 struct snd_ctl_elem_value *ucontrol)
763{
00a6941c
KM
764 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
765 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
31215871
MB
766
767 ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
768
769 return 0;
770}
771
772static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
773 struct snd_ctl_elem_info *uinfo)
774{
775 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
776 uinfo->count = 1;
777 uinfo->value.integer.min = 0;
778 uinfo->value.integer.max = 1;
779 return 0;
780}
781
782static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
783 struct snd_ctl_elem_value *ucontrol)
784{
785 int eq = kcontrol->private_value;
00a6941c
KM
786 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
787 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
31215871
MB
788
789 ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
790
791 return 0;
792}
793
794static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
795 struct snd_ctl_elem_value *ucontrol)
796{
797 int eq = kcontrol->private_value;
00a6941c
KM
798 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
799 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
31215871 800
d7fdae7c
MB
801 if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
802 return 0;
803
31215871
MB
804 if (ucontrol->value.integer.value[0] > 1)
805 return -EINVAL;
806
807 if (!wm8994->enh_eq)
808 return -ENODEV;
809
810 if (wm8958_dsp2_busy(wm8994, eq)) {
00a6941c 811 dev_dbg(component->dev, "DSP2 active on %d already\n", eq);
31215871
MB
812 return -EBUSY;
813 }
814
815 if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
816 wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
817 return -EBUSY;
818
819 wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
820
00a6941c 821 wm8958_dsp_apply(component, eq, ucontrol->value.integer.value[0]);
31215871
MB
822
823 return 0;
824}
825
826#define WM8958_ENH_EQ_SWITCH(xname, xval) {\
827 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
828 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
829 .info = wm8958_enh_eq_info, \
830 .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
831 .private_value = xval }
832
f701a2e5
MB
833static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
834WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
835WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
836WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
837};
838
09e10d7f
MB
839static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
840WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
841WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
842WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
843WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
844WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
845WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
846WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
847WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
848WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
849};
850
31215871
MB
851static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
852WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
853WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
854WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
855};
856
857static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
858{
00a6941c
KM
859 struct snd_soc_component *component = context;
860 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
31215871 861
00a6941c 862 if (fw && (wm8958_dsp2_fw(component, "ENH_EQ", fw, true) == 0)) {
fabfad2f 863 mutex_lock(&wm8994->fw_lock);
31215871 864 wm8994->enh_eq = fw;
fabfad2f 865 mutex_unlock(&wm8994->fw_lock);
31215871
MB
866 }
867}
868
09e10d7f 869static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
fbbf5920 870{
00a6941c
KM
871 struct snd_soc_component *component = context;
872 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
fbbf5920 873
00a6941c 874 if (fw && (wm8958_dsp2_fw(component, "MBC+VSS", fw, true) == 0)) {
fabfad2f 875 mutex_lock(&wm8994->fw_lock);
09e10d7f 876 wm8994->mbc_vss = fw;
fabfad2f 877 mutex_unlock(&wm8994->fw_lock);
fbbf5920 878 }
09e10d7f
MB
879}
880
881static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
882{
00a6941c
KM
883 struct snd_soc_component *component = context;
884 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
09e10d7f 885
00a6941c 886 if (fw && (wm8958_dsp2_fw(component, "MBC", fw, true) == 0)) {
fabfad2f 887 mutex_lock(&wm8994->fw_lock);
0ffecd7d 888 wm8994->mbc = fw;
fabfad2f 889 mutex_unlock(&wm8994->fw_lock);
0ffecd7d 890 }
fbbf5920
MB
891}
892
00a6941c 893void wm8958_dsp2_init(struct snd_soc_component *component)
f701a2e5 894{
00a6941c 895 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
d9dd4ada
MB
896 struct wm8994 *control = wm8994->wm8994;
897 struct wm8994_pdata *pdata = &control->pdata;
f701a2e5
MB
898 int ret, i;
899
f20d77ce
MB
900 wm8994->dsp_active = -1;
901
00a6941c 902 snd_soc_add_component_controls(component, wm8958_mbc_snd_controls,
f701a2e5 903 ARRAY_SIZE(wm8958_mbc_snd_controls));
00a6941c 904 snd_soc_add_component_controls(component, wm8958_vss_snd_controls,
09e10d7f 905 ARRAY_SIZE(wm8958_vss_snd_controls));
00a6941c 906 snd_soc_add_component_controls(component, wm8958_enh_eq_snd_controls,
31215871 907 ARRAY_SIZE(wm8958_enh_eq_snd_controls));
09e10d7f 908
f701a2e5 909
f20d77ce 910 /* We don't *require* firmware and don't want to delay boot */
fbbf5920 911 request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
00a6941c
KM
912 "wm8958_mbc.wfw", component->dev, GFP_KERNEL,
913 component, wm8958_mbc_loaded);
0ffecd7d 914 request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
00a6941c
KM
915 "wm8958_mbc_vss.wfw", component->dev, GFP_KERNEL,
916 component, wm8958_mbc_vss_loaded);
0ffecd7d 917 request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
00a6941c
KM
918 "wm8958_enh_eq.wfw", component->dev, GFP_KERNEL,
919 component, wm8958_enh_eq_loaded);
fbbf5920 920
f701a2e5
MB
921 if (pdata->num_mbc_cfgs) {
922 struct snd_kcontrol_new control[] = {
923 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
924 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
925 };
926
927 /* We need an array of texts for the enum API */
6da2ec56
KC
928 wm8994->mbc_texts = kmalloc_array(pdata->num_mbc_cfgs,
929 sizeof(char *),
930 GFP_KERNEL);
2cec4ff7 931 if (!wm8994->mbc_texts)
f701a2e5 932 return;
f701a2e5
MB
933
934 for (i = 0; i < pdata->num_mbc_cfgs; i++)
935 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
936
9a8d38db 937 wm8994->mbc_enum.items = pdata->num_mbc_cfgs;
f701a2e5
MB
938 wm8994->mbc_enum.texts = wm8994->mbc_texts;
939
00a6941c 940 ret = snd_soc_add_component_controls(wm8994->hubs.component,
8cb8e83b 941 control, 1);
f701a2e5 942 if (ret != 0)
00a6941c 943 dev_err(wm8994->hubs.component->dev,
f701a2e5
MB
944 "Failed to add MBC mode controls: %d\n", ret);
945 }
946
09e10d7f
MB
947 if (pdata->num_vss_cfgs) {
948 struct snd_kcontrol_new control[] = {
949 SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
950 wm8958_get_vss_enum, wm8958_put_vss_enum),
951 };
f701a2e5 952
09e10d7f 953 /* We need an array of texts for the enum API */
6da2ec56
KC
954 wm8994->vss_texts = kmalloc_array(pdata->num_vss_cfgs,
955 sizeof(char *),
956 GFP_KERNEL);
2cec4ff7 957 if (!wm8994->vss_texts)
09e10d7f 958 return;
09e10d7f
MB
959
960 for (i = 0; i < pdata->num_vss_cfgs; i++)
961 wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
962
9a8d38db 963 wm8994->vss_enum.items = pdata->num_vss_cfgs;
09e10d7f
MB
964 wm8994->vss_enum.texts = wm8994->vss_texts;
965
00a6941c 966 ret = snd_soc_add_component_controls(wm8994->hubs.component,
8cb8e83b 967 control, 1);
09e10d7f 968 if (ret != 0)
00a6941c 969 dev_err(wm8994->hubs.component->dev,
09e10d7f
MB
970 "Failed to add VSS mode controls: %d\n", ret);
971 }
972
973 if (pdata->num_vss_hpf_cfgs) {
974 struct snd_kcontrol_new control[] = {
975 SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
976 wm8958_get_vss_hpf_enum,
977 wm8958_put_vss_hpf_enum),
978 };
979
980 /* We need an array of texts for the enum API */
6da2ec56
KC
981 wm8994->vss_hpf_texts = kmalloc_array(pdata->num_vss_hpf_cfgs,
982 sizeof(char *),
983 GFP_KERNEL);
2cec4ff7 984 if (!wm8994->vss_hpf_texts)
09e10d7f 985 return;
09e10d7f
MB
986
987 for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
988 wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
989
9a8d38db 990 wm8994->vss_hpf_enum.items = pdata->num_vss_hpf_cfgs;
09e10d7f
MB
991 wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
992
00a6941c 993 ret = snd_soc_add_component_controls(wm8994->hubs.component,
8cb8e83b 994 control, 1);
09e10d7f 995 if (ret != 0)
00a6941c 996 dev_err(wm8994->hubs.component->dev,
09e10d7f
MB
997 "Failed to add VSS HPFmode controls: %d\n",
998 ret);
999 }
31215871
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1000
1001 if (pdata->num_enh_eq_cfgs) {
1002 struct snd_kcontrol_new control[] = {
1003 SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
1004 wm8958_get_enh_eq_enum,
1005 wm8958_put_enh_eq_enum),
1006 };
1007
1008 /* We need an array of texts for the enum API */
6da2ec56
KC
1009 wm8994->enh_eq_texts = kmalloc_array(pdata->num_enh_eq_cfgs,
1010 sizeof(char *),
1011 GFP_KERNEL);
2cec4ff7 1012 if (!wm8994->enh_eq_texts)
31215871 1013 return;
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1014
1015 for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
1016 wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
1017
9a8d38db 1018 wm8994->enh_eq_enum.items = pdata->num_enh_eq_cfgs;
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1019 wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
1020
00a6941c 1021 ret = snd_soc_add_component_controls(wm8994->hubs.component,
8cb8e83b 1022 control, 1);
31215871 1023 if (ret != 0)
00a6941c 1024 dev_err(wm8994->hubs.component->dev,
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1025 "Failed to add enhanced EQ controls: %d\n",
1026 ret);
1027 }
f701a2e5 1028}