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ASoC: wm8960: correct gain value for input PGA and add microphone PGA
[mirror_ubuntu-jammy-kernel.git] / sound / soc / codecs / wm8960.c
CommitLineData
f2644a2c
MB		 1/*
2 * wm8960.c -- WM8960 ALSA SoC Audio driver
3 *
656baaeb
MB		 4 * Copyright 2007-11 Wolfson Microelectronics, plc
5 *
f2644a2c
MB		 6 * Author: Liam Girdwood
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
75aa8868 18#include <linux/clk.h>
f2644a2c 19#include <linux/i2c.h>
5a0e3ad6 20#include <linux/slab.h>
f2644a2c
MB		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
f2644a2c
MB		 25#include <sound/initval.h>
26#include <sound/tlv.h>
b6877a47 27#include <sound/wm8960.h>
f2644a2c
MB		 28
29#include "wm8960.h"
30
f2644a2c 31/* R25 - Power 1 */
913d7b4c 32#define WM8960_VMID_MASK 0x180
f2644a2c
MB		 33#define WM8960_VREF 0x40
34
913d7b4c
MB		 35/* R26 - Power 2 */
36#define WM8960_PWR2_LOUT1 0x40
37#define WM8960_PWR2_ROUT1 0x20
38#define WM8960_PWR2_OUT3 0x02
39
f2644a2c
MB		 40/* R28 - Anti-pop 1 */
41#define WM8960_POBCTRL 0x80
42#define WM8960_BUFDCOPEN 0x10
43#define WM8960_BUFIOEN 0x08
44#define WM8960_SOFT_ST 0x04
45#define WM8960_HPSTBY 0x01
46
47/* R29 - Anti-pop 2 */
48#define WM8960_DISOP 0x40
913d7b4c 49#define WM8960_DRES_MASK 0x30
f2644a2c
MB		 50
51/*
52 * wm8960 register cache
53 * We can't read the WM8960 register space when we are
54 * using 2 wire for device control, so we cache them instead.
55 */
0ebe36c6 56static const struct reg_default wm8960_reg_defaults[] = {
b3df026e
MB		 57 { 0x0, 0x00a7 },
58 { 0x1, 0x00a7 },
0ebe36c6
MB		 59 { 0x2, 0x0000 },
60 { 0x3, 0x0000 },
61 { 0x4, 0x0000 },
62 { 0x5, 0x0008 },
63 { 0x6, 0x0000 },
64 { 0x7, 0x000a },
65 { 0x8, 0x01c0 },
66 { 0x9, 0x0000 },
67 { 0xa, 0x00ff },
68 { 0xb, 0x00ff },
69
70 { 0x10, 0x0000 },
71 { 0x11, 0x007b },
72 { 0x12, 0x0100 },
73 { 0x13, 0x0032 },
74 { 0x14, 0x0000 },
75 { 0x15, 0x00c3 },
76 { 0x16, 0x00c3 },
77 { 0x17, 0x01c0 },
78 { 0x18, 0x0000 },
79 { 0x19, 0x0000 },
80 { 0x1a, 0x0000 },
81 { 0x1b, 0x0000 },
82 { 0x1c, 0x0000 },
83 { 0x1d, 0x0000 },
84
85 { 0x20, 0x0100 },
86 { 0x21, 0x0100 },
87 { 0x22, 0x0050 },
88
89 { 0x25, 0x0050 },
90 { 0x26, 0x0000 },
91 { 0x27, 0x0000 },
92 { 0x28, 0x0000 },
93 { 0x29, 0x0000 },
94 { 0x2a, 0x0040 },
95 { 0x2b, 0x0000 },
96 { 0x2c, 0x0000 },
97 { 0x2d, 0x0050 },
98 { 0x2e, 0x0050 },
99 { 0x2f, 0x0000 },
100 { 0x30, 0x0002 },
101 { 0x31, 0x0037 },
102
103 { 0x33, 0x0080 },
104 { 0x34, 0x0008 },
105 { 0x35, 0x0031 },
106 { 0x36, 0x0026 },
107 { 0x37, 0x00e9 },
f2644a2c
MB		 108};
109
0ebe36c6
MB		 110static bool wm8960_volatile(struct device *dev, unsigned int reg)
111{
112 switch (reg) {
113 case WM8960_RESET:
114 return true;
115 default:
116 return false;
117 }
118}
119
f2644a2c 120struct wm8960_priv {
75aa8868 121 struct clk *mclk;
0ebe36c6 122 struct regmap *regmap;
f0fba2ad
LG		 123 int (*set_bias_level)(struct snd_soc_codec *,
124 enum snd_soc_bias_level level);
913d7b4c
MB		 125 struct snd_soc_dapm_widget *lout1;
126 struct snd_soc_dapm_widget *rout1;
127 struct snd_soc_dapm_widget *out3;
afd6d36a
MB		 128 bool deemph;
129 int playback_fs;
0e50b51a
ZW		 130 int bclk;
131 int sysclk;
e2280c90 132 struct wm8960_data pdata;
f2644a2c
MB		 133};
134
3ad5e861 135#define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0)
f2644a2c
MB		 136
137/* enumerated controls */
f2644a2c
MB		 138static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
139 "Right Inverted", "Stereo Inversion"};
140static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"};
141static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"};
142static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"};
143static const char *wm8960_alcmode[] = {"ALC", "Limiter"};
144
145static const struct soc_enum wm8960_enum[] = {
f2644a2c
MB		 146 SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity),
147 SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity),
148 SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff),
149 SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff),
150 SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc),
151 SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode),
152};
153
afd6d36a
MB		 154static const int deemph_settings[] = { 0, 32000, 44100, 48000 };
155
156static int wm8960_set_deemph(struct snd_soc_codec *codec)
157{
158 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
159 int val, i, best;
160
161 /* If we're using deemphasis select the nearest available sample
162 * rate.
163 */
164 if (wm8960->deemph) {
165 best = 1;
166 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
167 if (abs(deemph_settings[i] - wm8960->playback_fs) <
168 abs(deemph_settings[best] - wm8960->playback_fs))
169 best = i;
170 }
171
172 val = best << 1;
173 } else {
174 val = 0;
175 }
176
177 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
178
179 return snd_soc_update_bits(codec, WM8960_DACCTL1,
180 0x6, val);
181}
182
183static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
184 struct snd_ctl_elem_value *ucontrol)
185{
ea53bf77 186 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
afd6d36a
MB		 187 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
188
b4a18c8b 189 ucontrol->value.integer.value[0] = wm8960->deemph;
3f343f85 190 return 0;
afd6d36a
MB		 191}
192
193static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
194 struct snd_ctl_elem_value *ucontrol)
195{
ea53bf77 196 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
afd6d36a 197 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
b4a18c8b 198 int deemph = ucontrol->value.integer.value[0];
afd6d36a
MB		 199
200 if (deemph > 1)
201 return -EINVAL;
202
203 wm8960->deemph = deemph;
204
205 return wm8960_set_deemph(codec);
206}
207
3758ff5f 208static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
7e90f9b2 209static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1725, 75, 0);
3758ff5f 210static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
f2644a2c
MB		 211static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
212static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
7e90f9b2
ZW		 213static const DECLARE_TLV_DB_SCALE(lineinboost_tlv, -1500, 300, 1);
214static const unsigned int micboost_tlv[] = {
215 TLV_DB_RANGE_HEAD(2),
216 0, 1, TLV_DB_SCALE_ITEM(0, 1300, 0),
217 2, 3, TLV_DB_SCALE_ITEM(2000, 900, 0),
218};
f2644a2c
MB		 219
220static const struct snd_kcontrol_new wm8960_snd_controls[] = {
221SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL,
7e90f9b2 222 0, 63, 0, inpga_tlv),
f2644a2c
MB		 223SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL,
224 6, 1, 0),
225SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL,
226 7, 1, 0),
227
21eb2693 228SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume",
7e90f9b2 229 WM8960_INBMIX1, 4, 7, 0, lineinboost_tlv),
21eb2693 230SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume",
7e90f9b2 231 WM8960_INBMIX1, 1, 7, 0, lineinboost_tlv),
21eb2693 232SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume",
7e90f9b2 233 WM8960_INBMIX2, 4, 7, 0, lineinboost_tlv),
21eb2693 234SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume",
7e90f9b2
ZW		 235 WM8960_INBMIX2, 1, 7, 0, lineinboost_tlv),
236SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT1 Volume",
237 WM8960_RINPATH, 4, 4, 0, micboost_tlv),
238SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT1 Volume",
239 WM8960_LINPATH, 4, 4, 0, micboost_tlv),
21eb2693 240
f2644a2c
MB		 241SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC,
242 0, 255, 0, dac_tlv),
243
244SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1,
245 0, 127, 0, out_tlv),
246SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1,
247 7, 1, 0),
248
249SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2,
250 0, 127, 0, out_tlv),
251SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2,
252 7, 1, 0),
253SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0),
254SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0),
255
256SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0),
4faaa8d9 257SOC_ENUM("ADC Polarity", wm8960_enum[0]),
f2644a2c
MB		 258SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0),
259
a077e81e 260SOC_ENUM("DAC Polarity", wm8960_enum[1]),
afd6d36a
MB		 261SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
262 wm8960_get_deemph, wm8960_put_deemph),
f2644a2c 263
4faaa8d9
MB		 264SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]),
265SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]),
f2644a2c
MB		 266SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0),
267SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0),
268
4faaa8d9 269SOC_ENUM("ALC Function", wm8960_enum[4]),
f2644a2c
MB		 270SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0),
271SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1),
272SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0),
273SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0),
4faaa8d9 274SOC_ENUM("ALC Mode", wm8960_enum[5]),
f2644a2c
MB		 275SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0),
276SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0),
277
278SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0),
279SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0),
280
c324aac0
MH		 281SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC,
282 0, 255, 0, adc_tlv),
f2644a2c
MB		 283
284SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume",
285 WM8960_BYPASS1, 4, 7, 1, bypass_tlv),
286SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume",
287 WM8960_LOUTMIX, 4, 7, 1, bypass_tlv),
288SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume",
289 WM8960_BYPASS2, 4, 7, 1, bypass_tlv),
290SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume",
291 WM8960_ROUTMIX, 4, 7, 1, bypass_tlv),
292};
293
294static const struct snd_kcontrol_new wm8960_lin_boost[] = {
295SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0),
296SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0),
297SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0),
298};
299
300static const struct snd_kcontrol_new wm8960_lin[] = {
301SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0),
302};
303
304static const struct snd_kcontrol_new wm8960_rin_boost[] = {
305SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0),
306SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0),
307SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0),
308};
309
310static const struct snd_kcontrol_new wm8960_rin[] = {
311SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0),
312};
313
314static const struct snd_kcontrol_new wm8960_loutput_mixer[] = {
315SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0),
316SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0),
317SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0),
318};
319
320static const struct snd_kcontrol_new wm8960_routput_mixer[] = {
321SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0),
322SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0),
323SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0),
324};
325
326static const struct snd_kcontrol_new wm8960_mono_out[] = {
327SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0),
328SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0),
329};
330
331static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = {
332SND_SOC_DAPM_INPUT("LINPUT1"),
333SND_SOC_DAPM_INPUT("RINPUT1"),
334SND_SOC_DAPM_INPUT("LINPUT2"),
335SND_SOC_DAPM_INPUT("RINPUT2"),
336SND_SOC_DAPM_INPUT("LINPUT3"),
337SND_SOC_DAPM_INPUT("RINPUT3"),
338
187774cb 339SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0),
f2644a2c
MB		 340
341SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0,
342 wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)),
343SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0,
344 wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)),
345
346SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0,
347 wm8960_lin, ARRAY_SIZE(wm8960_lin)),
348SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0,
349 wm8960_rin, ARRAY_SIZE(wm8960_rin)),
350
44426de4
MB		 351SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0),
352SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0),
f2644a2c
MB		 353
354SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0),
355SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0),
356
357SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0,
358 &wm8960_loutput_mixer[0],
359 ARRAY_SIZE(wm8960_loutput_mixer)),
360SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0,
361 &wm8960_routput_mixer[0],
362 ARRAY_SIZE(wm8960_routput_mixer)),
363
f2644a2c
MB		 364SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0),
365SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0),
366
367SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0),
368SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0),
369
370SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0),
371SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0),
372
373SND_SOC_DAPM_OUTPUT("SPK_LP"),
374SND_SOC_DAPM_OUTPUT("SPK_LN"),
375SND_SOC_DAPM_OUTPUT("HP_L"),
376SND_SOC_DAPM_OUTPUT("HP_R"),
377SND_SOC_DAPM_OUTPUT("SPK_RP"),
378SND_SOC_DAPM_OUTPUT("SPK_RN"),
379SND_SOC_DAPM_OUTPUT("OUT3"),
380};
381
913d7b4c
MB		 382static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = {
383SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0,
384 &wm8960_mono_out[0],
385 ARRAY_SIZE(wm8960_mono_out)),
386};
387
388/* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */
389static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = {
390SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0),
391};
392
f2644a2c
MB		 393static const struct snd_soc_dapm_route audio_paths[] = {
394 { "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" },
395 { "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" },
396 { "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" },
397
398 { "Left Input Mixer", "Boost Switch", "Left Boost Mixer", },
399 { "Left Input Mixer", NULL, "LINPUT1", }, /* Really Boost Switch */
400 { "Left Input Mixer", NULL, "LINPUT2" },
401 { "Left Input Mixer", NULL, "LINPUT3" },
402
403 { "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" },
404 { "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" },
405 { "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" },
406
407 { "Right Input Mixer", "Boost Switch", "Right Boost Mixer", },
408 { "Right Input Mixer", NULL, "RINPUT1", }, /* Really Boost Switch */
409 { "Right Input Mixer", NULL, "RINPUT2" },
85e36a1f 410 { "Right Input Mixer", NULL, "RINPUT3" },
f2644a2c
MB		 411
412 { "Left ADC", NULL, "Left Input Mixer" },
413 { "Right ADC", NULL, "Right Input Mixer" },
414
415 { "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" },
416 { "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer"} ,
417 { "Left Output Mixer", "PCM Playback Switch", "Left DAC" },
418
419 { "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" },
420 { "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" } ,
421 { "Right Output Mixer", "PCM Playback Switch", "Right DAC" },
422
f2644a2c
MB		 423 { "LOUT1 PGA", NULL, "Left Output Mixer" },
424 { "ROUT1 PGA", NULL, "Right Output Mixer" },
425
426 { "HP_L", NULL, "LOUT1 PGA" },
427 { "HP_R", NULL, "ROUT1 PGA" },
428
429 { "Left Speaker PGA", NULL, "Left Output Mixer" },
430 { "Right Speaker PGA", NULL, "Right Output Mixer" },
431
432 { "Left Speaker Output", NULL, "Left Speaker PGA" },
433 { "Right Speaker Output", NULL, "Right Speaker PGA" },
434
435 { "SPK_LN", NULL, "Left Speaker Output" },
436 { "SPK_LP", NULL, "Left Speaker Output" },
437 { "SPK_RN", NULL, "Right Speaker Output" },
438 { "SPK_RP", NULL, "Right Speaker Output" },
913d7b4c
MB		 439};
440
441static const struct snd_soc_dapm_route audio_paths_out3[] = {
442 { "Mono Output Mixer", "Left Switch", "Left Output Mixer" },
443 { "Mono Output Mixer", "Right Switch", "Right Output Mixer" },
f2644a2c
MB		 444
445 { "OUT3", NULL, "Mono Output Mixer", }
446};
447
913d7b4c
MB		 448static const struct snd_soc_dapm_route audio_paths_capless[] = {
449 { "HP_L", NULL, "OUT3 VMID" },
450 { "HP_R", NULL, "OUT3 VMID" },
451
452 { "OUT3 VMID", NULL, "Left Output Mixer" },
453 { "OUT3 VMID", NULL, "Right Output Mixer" },
454};
455
f2644a2c
MB		 456static int wm8960_add_widgets(struct snd_soc_codec *codec)
457{
b2c812e2 458 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
e2280c90 459 struct wm8960_data *pdata = &wm8960->pdata;
93f32f53 460 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
913d7b4c
MB		 461 struct snd_soc_dapm_widget *w;
462
ce6120cc 463 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets,
f2644a2c
MB		 464 ARRAY_SIZE(wm8960_dapm_widgets));
465
ce6120cc 466 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
f2644a2c 467
913d7b4c
MB		 468 /* In capless mode OUT3 is used to provide VMID for the
469 * headphone outputs, otherwise it is used as a mono mixer.
470 */
471 if (pdata && pdata->capless) {
ce6120cc 472 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless,
913d7b4c
MB		 473 ARRAY_SIZE(wm8960_dapm_widgets_capless));
474
ce6120cc 475 snd_soc_dapm_add_routes(dapm, audio_paths_capless,
913d7b4c
MB		 476 ARRAY_SIZE(audio_paths_capless));
477 } else {
ce6120cc 478 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3,
913d7b4c
MB		 479 ARRAY_SIZE(wm8960_dapm_widgets_out3));
480
ce6120cc 481 snd_soc_dapm_add_routes(dapm, audio_paths_out3,
913d7b4c
MB		 482 ARRAY_SIZE(audio_paths_out3));
483 }
484
485 /* We need to power up the headphone output stage out of
486 * sequence for capless mode. To save scanning the widget
487 * list each time to find the desired power state do so now
488 * and save the result.
489 */
00200107 490 list_for_each_entry(w, &codec->component.card->widgets, list) {
93f32f53 491 if (w->dapm != dapm)
97c866de 492 continue;
913d7b4c
MB		 493 if (strcmp(w->name, "LOUT1 PGA") == 0)
494 wm8960->lout1 = w;
495 if (strcmp(w->name, "ROUT1 PGA") == 0)
496 wm8960->rout1 = w;
497 if (strcmp(w->name, "OUT3 VMID") == 0)
498 wm8960->out3 = w;
499 }
500
f2644a2c
MB		 501 return 0;
502}
503
504static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
505 unsigned int fmt)
506{
507 struct snd_soc_codec *codec = codec_dai->codec;
508 u16 iface = 0;
509
510 /* set master/slave audio interface */
511 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
512 case SND_SOC_DAIFMT_CBM_CFM:
513 iface |= 0x0040;
514 break;
515 case SND_SOC_DAIFMT_CBS_CFS:
516 break;
517 default:
518 return -EINVAL;
519 }
520
521 /* interface format */
522 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
523 case SND_SOC_DAIFMT_I2S:
524 iface |= 0x0002;
525 break;
526 case SND_SOC_DAIFMT_RIGHT_J:
527 break;
528 case SND_SOC_DAIFMT_LEFT_J:
529 iface |= 0x0001;
530 break;
531 case SND_SOC_DAIFMT_DSP_A:
532 iface |= 0x0003;
533 break;
534 case SND_SOC_DAIFMT_DSP_B:
535 iface |= 0x0013;
536 break;
537 default:
538 return -EINVAL;
539 }
540
541 /* clock inversion */
542 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
543 case SND_SOC_DAIFMT_NB_NF:
544 break;
545 case SND_SOC_DAIFMT_IB_IF:
546 iface |= 0x0090;
547 break;
548 case SND_SOC_DAIFMT_IB_NF:
549 iface |= 0x0080;
550 break;
551 case SND_SOC_DAIFMT_NB_IF:
552 iface |= 0x0010;
553 break;
554 default:
555 return -EINVAL;
556 }
557
558 /* set iface */
17a52fd6 559 snd_soc_write(codec, WM8960_IFACE1, iface);
f2644a2c
MB		 560 return 0;
561}
562
db059c0f
MB		 563static struct {
564 int rate;
565 unsigned int val;
566} alc_rates[] = {
567 { 48000, 0 },
568 { 44100, 0 },
569 { 32000, 1 },
570 { 22050, 2 },
571 { 24000, 2 },
572 { 16000, 3 },
22ee76da 573 { 11025, 4 },
db059c0f
MB		 574 { 12000, 4 },
575 { 8000, 5 },
576};
577
0e50b51a
ZW		 578/* Multiply 256 for internal 256 div */
579static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 };
580
581/* Multiply 10 to eliminate decimials */
582static const int bclk_divs[] = {
583 10, 15, 20, 30, 40, 55, 60, 80, 110,
584 120, 160, 220, 240, 320, 320, 320
585};
586
587static void wm8960_configure_clocking(struct snd_soc_codec *codec,
588 bool tx, int lrclk)
589{
590 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
591 u16 iface1 = snd_soc_read(codec, WM8960_IFACE1);
592 u16 iface2 = snd_soc_read(codec, WM8960_IFACE2);
593 u32 sysclk;
594 int i, j;
595
596 if (!(iface1 & (1<<6))) {
597 dev_dbg(codec->dev,
598 "Codec is slave mode, no need to configure clock\n");
599 return;
600 }
601
602 if (!wm8960->sysclk) {
603 dev_dbg(codec->dev, "No SYSCLK configured\n");
604 return;
605 }
606
607 if (!wm8960->bclk || !lrclk) {
608 dev_dbg(codec->dev, "No audio clocks configured\n");
609 return;
610 }
611
612 for (i = 0; i < ARRAY_SIZE(dac_divs); ++i) {
613 if (wm8960->sysclk == lrclk * dac_divs[i]) {
614 for (j = 0; j < ARRAY_SIZE(bclk_divs); ++j) {
615 sysclk = wm8960->bclk * bclk_divs[j] / 10;
616 if (wm8960->sysclk == sysclk)
617 break;
618 }
619 if(j != ARRAY_SIZE(bclk_divs))
620 break;
621 }
622 }
623
624 if (i == ARRAY_SIZE(dac_divs)) {
625 dev_err(codec->dev, "Unsupported sysclk %d\n", wm8960->sysclk);
626 return;
627 }
628
629 /*
630 * configure frame clock. If ADCLRC configure as GPIO pin, DACLRC
631 * pin is used as a frame clock for ADCs and DACs.
632 */
633 if (iface2 & (1<<6))
634 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, i << 3);
635 else if (tx)
636 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, i << 3);
637 else if (!tx)
638 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, i << 6);
639
640 /* configure bit clock */
641 snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, j);
642}
643
f2644a2c
MB		 644static int wm8960_hw_params(struct snd_pcm_substream *substream,
645 struct snd_pcm_hw_params *params,
646 struct snd_soc_dai *dai)
647{
e6968a17 648 struct snd_soc_codec *codec = dai->codec;
afd6d36a 649 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
17a52fd6 650 u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3;
0e50b51a 651 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
db059c0f 652 int i;
f2644a2c 653
0e50b51a
ZW		 654 wm8960->bclk = snd_soc_params_to_bclk(params);
655 if (params_channels(params) == 1)
656 wm8960->bclk *= 2;
657
f2644a2c 658 /* bit size */
39e9cc46
MB		 659 switch (params_width(params)) {
660 case 16:
f2644a2c 661 break;
39e9cc46 662 case 20:
f2644a2c
MB		 663 iface |= 0x0004;
664 break;
39e9cc46 665 case 24:
f2644a2c
MB		 666 iface |= 0x0008;
667 break;
7a8c7867
ZW		 668 case 32:
669 /* right justify mode does not support 32 word length */
670 if ((iface & 0x3) != 0) {
671 iface |= 0x000c;
672 break;
673 }
4c2474c0 674 default:
39e9cc46
MB		 675 dev_err(codec->dev, "unsupported width %d\n",
676 params_width(params));
4c2474c0 677 return -EINVAL;
f2644a2c
MB		 678 }
679
afd6d36a
MB		 680 /* Update filters for the new rate */
681 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
682 wm8960->playback_fs = params_rate(params);
683 wm8960_set_deemph(codec);
db059c0f
MB		 684 } else {
685 for (i = 0; i < ARRAY_SIZE(alc_rates); i++)
686 if (alc_rates[i].rate == params_rate(params))
687 snd_soc_update_bits(codec,
688 WM8960_ADDCTL3, 0x7,
689 alc_rates[i].val);
afd6d36a
MB		 690 }
691
f2644a2c 692 /* set iface */
17a52fd6 693 snd_soc_write(codec, WM8960_IFACE1, iface);
0e50b51a
ZW		 694
695 wm8960_configure_clocking(codec, tx, params_rate(params));
696
f2644a2c
MB		 697 return 0;
698}
699
700static int wm8960_mute(struct snd_soc_dai *dai, int mute)
701{
702 struct snd_soc_codec *codec = dai->codec;
f2644a2c
MB		 703
704 if (mute)
16b24881 705 snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0x8);
f2644a2c 706 else
16b24881 707 snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0);
f2644a2c
MB		 708 return 0;
709}
710
913d7b4c
MB		 711static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
712 enum snd_soc_bias_level level)
f2644a2c 713{
0ebe36c6 714 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
75aa8868 715 int ret;
0ebe36c6 716
f2644a2c
MB		 717 switch (level) {
718 case SND_SOC_BIAS_ON:
719 break;
720
721 case SND_SOC_BIAS_PREPARE:
93f32f53 722 switch (snd_soc_codec_get_bias_level(codec)) {
75aa8868
ZW		 723 case SND_SOC_BIAS_STANDBY:
724 if (!IS_ERR(wm8960->mclk)) {
725 ret = clk_prepare_enable(wm8960->mclk);
726 if (ret) {
727 dev_err(codec->dev,
728 "Failed to enable MCLK: %d\n",
729 ret);
730 return ret;
731 }
732 }
733
734 /* Set VMID to 2x50k */
735 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80);
736 break;
737
738 case SND_SOC_BIAS_ON:
739 if (!IS_ERR(wm8960->mclk))
740 clk_disable_unprepare(wm8960->mclk);
741 break;
742
743 default:
744 break;
745 }
746
f2644a2c
MB		 747 break;
748
749 case SND_SOC_BIAS_STANDBY:
93f32f53 750 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
0ebe36c6 751 regcache_sync(wm8960->regmap);
bc45df2d 752
f2644a2c 753 /* Enable anti-pop features */
17a52fd6 754 snd_soc_write(codec, WM8960_APOP1,
913d7b4c
MB		 755 WM8960_POBCTRL | WM8960_SOFT_ST |
756 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
f2644a2c
MB		 757
758 /* Enable & ramp VMID at 2x50k */
16b24881 759 snd_soc_update_bits(codec, WM8960_POWER1, 0x80, 0x80);
f2644a2c
MB		 760 msleep(100);
761
762 /* Enable VREF */
16b24881
AL		 763 snd_soc_update_bits(codec, WM8960_POWER1, WM8960_VREF,
764 WM8960_VREF);
f2644a2c
MB		 765
766 /* Disable anti-pop features */
17a52fd6 767 snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN);
f2644a2c
MB		 768 }
769
770 /* Set VMID to 2x250k */
16b24881 771 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100);
f2644a2c
MB		 772 break;
773
774 case SND_SOC_BIAS_OFF:
775 /* Enable anti-pop features */
17a52fd6 776 snd_soc_write(codec, WM8960_APOP1,
f2644a2c
MB		 777 WM8960_POBCTRL | WM8960_SOFT_ST |
778 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
779
780 /* Disable VMID and VREF, let them discharge */
17a52fd6 781 snd_soc_write(codec, WM8960_POWER1, 0);
f2644a2c 782 msleep(600);
913d7b4c
MB		 783 break;
784 }
785
913d7b4c
MB		 786 return 0;
787}
788
789static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
790 enum snd_soc_bias_level level)
791{
b2c812e2 792 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
75aa8868 793 int reg, ret;
913d7b4c
MB		 794
795 switch (level) {
796 case SND_SOC_BIAS_ON:
797 break;
798
799 case SND_SOC_BIAS_PREPARE:
93f32f53 800 switch (snd_soc_codec_get_bias_level(codec)) {
913d7b4c
MB		 801 case SND_SOC_BIAS_STANDBY:
802 /* Enable anti pop mode */
803 snd_soc_update_bits(codec, WM8960_APOP1,
804 WM8960_POBCTRL | WM8960_SOFT_ST |
805 WM8960_BUFDCOPEN,
806 WM8960_POBCTRL | WM8960_SOFT_ST |
807 WM8960_BUFDCOPEN);
808
809 /* Enable LOUT1, ROUT1 and OUT3 if they're enabled */
810 reg = 0;
811 if (wm8960->lout1 && wm8960->lout1->power)
812 reg |= WM8960_PWR2_LOUT1;
813 if (wm8960->rout1 && wm8960->rout1->power)
814 reg |= WM8960_PWR2_ROUT1;
815 if (wm8960->out3 && wm8960->out3->power)
816 reg |= WM8960_PWR2_OUT3;
817 snd_soc_update_bits(codec, WM8960_POWER2,
818 WM8960_PWR2_LOUT1 |
819 WM8960_PWR2_ROUT1 |
820 WM8960_PWR2_OUT3, reg);
821
822 /* Enable VMID at 2*50k */
823 snd_soc_update_bits(codec, WM8960_POWER1,
824 WM8960_VMID_MASK, 0x80);
825
826 /* Ramp */
827 msleep(100);
828
829 /* Enable VREF */
830 snd_soc_update_bits(codec, WM8960_POWER1,
831 WM8960_VREF, WM8960_VREF);
832
833 msleep(100);
75aa8868
ZW		 834
835 if (!IS_ERR(wm8960->mclk)) {
836 ret = clk_prepare_enable(wm8960->mclk);
837 if (ret) {
838 dev_err(codec->dev,
839 "Failed to enable MCLK: %d\n",
840 ret);
841 return ret;
842 }
843 }
913d7b4c
MB		 844 break;
845
846 case SND_SOC_BIAS_ON:
75aa8868
ZW		 847 if (!IS_ERR(wm8960->mclk))
848 clk_disable_unprepare(wm8960->mclk);
849
913d7b4c
MB		 850 /* Enable anti-pop mode */
851 snd_soc_update_bits(codec, WM8960_APOP1,
852 WM8960_POBCTRL | WM8960_SOFT_ST |
853 WM8960_BUFDCOPEN,
854 WM8960_POBCTRL | WM8960_SOFT_ST |
855 WM8960_BUFDCOPEN);
856
857 /* Disable VMID and VREF */
858 snd_soc_update_bits(codec, WM8960_POWER1,
859 WM8960_VREF | WM8960_VMID_MASK, 0);
860 break;
861
bc45df2d 862 case SND_SOC_BIAS_OFF:
0ebe36c6 863 regcache_sync(wm8960->regmap);
bc45df2d 864 break;
913d7b4c
MB		 865 default:
866 break;
867 }
868 break;
f2644a2c 869
913d7b4c 870 case SND_SOC_BIAS_STANDBY:
93f32f53 871 switch (snd_soc_codec_get_bias_level(codec)) {
913d7b4c
MB		 872 case SND_SOC_BIAS_PREPARE:
873 /* Disable HP discharge */
874 snd_soc_update_bits(codec, WM8960_APOP2,
875 WM8960_DISOP | WM8960_DRES_MASK,
876 0);
877
878 /* Disable anti-pop features */
879 snd_soc_update_bits(codec, WM8960_APOP1,
880 WM8960_POBCTRL | WM8960_SOFT_ST |
881 WM8960_BUFDCOPEN,
882 WM8960_POBCTRL | WM8960_SOFT_ST |
883 WM8960_BUFDCOPEN);
884 break;
885
886 default:
887 break;
888 }
889 break;
f2644a2c 890
913d7b4c 891 case SND_SOC_BIAS_OFF:
f2644a2c
MB		 892 break;
893 }
894
f2644a2c
MB		 895 return 0;
896}
897
898/* PLL divisors */
899struct _pll_div {
900 u32 pre_div:1;
901 u32 n:4;
902 u32 k:24;
903};
904
905/* The size in bits of the pll divide multiplied by 10
906 * to allow rounding later */
907#define FIXED_PLL_SIZE ((1 << 24) * 10)
908
909static int pll_factors(unsigned int source, unsigned int target,
910 struct _pll_div *pll_div)
911{
912 unsigned long long Kpart;
913 unsigned int K, Ndiv, Nmod;
914
915 pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target);
916
917 /* Scale up target to PLL operating frequency */
918 target *= 4;
919
920 Ndiv = target / source;
921 if (Ndiv < 6) {
922 source >>= 1;
923 pll_div->pre_div = 1;
924 Ndiv = target / source;
925 } else
926 pll_div->pre_div = 0;
927
928 if ((Ndiv < 6) || (Ndiv > 12)) {
929 pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv);
930 return -EINVAL;
931 }
932
933 pll_div->n = Ndiv;
934 Nmod = target % source;
935 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
936
937 do_div(Kpart, source);
938
939 K = Kpart & 0xFFFFFFFF;
940
941 /* Check if we need to round */
942 if ((K % 10) >= 5)
943 K += 5;
944
945 /* Move down to proper range now rounding is done */
946 K /= 10;
947
948 pll_div->k = K;
949
950 pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n",
951 pll_div->n, pll_div->k, pll_div->pre_div);
952
953 return 0;
954}
955
85488037
MB		 956static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
957 int source, unsigned int freq_in, unsigned int freq_out)
f2644a2c
MB		 958{
959 struct snd_soc_codec *codec = codec_dai->codec;
960 u16 reg;
961 static struct _pll_div pll_div;
962 int ret;
963
964 if (freq_in && freq_out) {
965 ret = pll_factors(freq_in, freq_out, &pll_div);
966 if (ret != 0)
967 return ret;
968 }
969
970 /* Disable the PLL: even if we are changing the frequency the
971 * PLL needs to be disabled while we do so. */
16b24881
AL		 972 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0);
973 snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0);
f2644a2c
MB		 974
975 if (!freq_in || !freq_out)
976 return 0;
977
17a52fd6 978 reg = snd_soc_read(codec, WM8960_PLL1) & ~0x3f;
f2644a2c
MB		 979 reg |= pll_div.pre_div << 4;
980 reg |= pll_div.n;
981
982 if (pll_div.k) {
983 reg |= 0x20;
984
85fa532b
MD		 985 snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
986 snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
987 snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
f2644a2c 988 }
17a52fd6 989 snd_soc_write(codec, WM8960_PLL1, reg);
f2644a2c
MB		 990
991 /* Turn it on */
16b24881 992 snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0x1);
f2644a2c 993 msleep(250);
16b24881 994 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0x1);
f2644a2c
MB		 995
996 return 0;
997}
998
999static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1000 int div_id, int div)
1001{
1002 struct snd_soc_codec *codec = codec_dai->codec;
1003 u16 reg;
1004
1005 switch (div_id) {
f2644a2c 1006 case WM8960_SYSCLKDIV:
17a52fd6
MB		 1007 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9;
1008 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
f2644a2c
MB		 1009 break;
1010 case WM8960_DACDIV:
17a52fd6
MB		 1011 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7;
1012 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
f2644a2c
MB		 1013 break;
1014 case WM8960_OPCLKDIV:
17a52fd6
MB		 1015 reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f;
1016 snd_soc_write(codec, WM8960_PLL1, reg | div);
f2644a2c
MB		 1017 break;
1018 case WM8960_DCLKDIV:
17a52fd6
MB		 1019 reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f;
1020 snd_soc_write(codec, WM8960_CLOCK2, reg | div);
f2644a2c
MB		 1021 break;
1022 case WM8960_TOCLKSEL:
17a52fd6
MB		 1023 reg = snd_soc_read(codec, WM8960_ADDCTL1) & 0x1fd;
1024 snd_soc_write(codec, WM8960_ADDCTL1, reg | div);
f2644a2c
MB		 1025 break;
1026 default:
1027 return -EINVAL;
1028 }
1029
1030 return 0;
1031}
1032
f0fba2ad
LG		 1033static int wm8960_set_bias_level(struct snd_soc_codec *codec,
1034 enum snd_soc_bias_level level)
1035{
1036 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1037
1038 return wm8960->set_bias_level(codec, level);
1039}
1040
0e50b51a
ZW		 1041static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1042 unsigned int freq, int dir)
1043{
1044 struct snd_soc_codec *codec = dai->codec;
1045 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1046
1047 switch (clk_id) {
1048 case WM8960_SYSCLK_MCLK:
1049 snd_soc_update_bits(codec, WM8960_CLOCK1,
1050 0x1, WM8960_SYSCLK_MCLK);
1051 break;
1052 case WM8960_SYSCLK_PLL:
1053 snd_soc_update_bits(codec, WM8960_CLOCK1,
1054 0x1, WM8960_SYSCLK_PLL);
1055 break;
1056 default:
1057 return -EINVAL;
1058 }
1059
1060 wm8960->sysclk = freq;
1061
1062 return 0;
1063}
1064
f2644a2c
MB		 1065#define WM8960_RATES SNDRV_PCM_RATE_8000_48000
1066
1067#define WM8960_FORMATS \
1068 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
7a8c7867 1069 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
f2644a2c 1070
85e7652d 1071static const struct snd_soc_dai_ops wm8960_dai_ops = {
f2644a2c
MB		 1072 .hw_params = wm8960_hw_params,
1073 .digital_mute = wm8960_mute,
1074 .set_fmt = wm8960_set_dai_fmt,
1075 .set_clkdiv = wm8960_set_dai_clkdiv,
1076 .set_pll = wm8960_set_dai_pll,
0e50b51a 1077 .set_sysclk = wm8960_set_dai_sysclk,
f2644a2c
MB		 1078};
1079
f0fba2ad
LG		 1080static struct snd_soc_dai_driver wm8960_dai = {
1081 .name = "wm8960-hifi",
f2644a2c
MB		 1082 .playback = {
1083 .stream_name = "Playback",
1084 .channels_min = 1,
1085 .channels_max = 2,
1086 .rates = WM8960_RATES,
1087 .formats = WM8960_FORMATS,},
1088 .capture = {
1089 .stream_name = "Capture",
1090 .channels_min = 1,
1091 .channels_max = 2,
1092 .rates = WM8960_RATES,
1093 .formats = WM8960_FORMATS,},
1094 .ops = &wm8960_dai_ops,
1095 .symmetric_rates = 1,
1096};
f2644a2c 1097
f0fba2ad 1098static int wm8960_probe(struct snd_soc_codec *codec)
f2644a2c 1099{
f0fba2ad 1100 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
e2280c90 1101 struct wm8960_data *pdata = &wm8960->pdata;
f2644a2c 1102
e2280c90
ZW		 1103 if (pdata->capless)
1104 wm8960->set_bias_level = wm8960_set_bias_level_capless;
1105 else
1106 wm8960->set_bias_level = wm8960_set_bias_level_out3;
f2644a2c 1107
022658be 1108 snd_soc_add_codec_controls(codec, wm8960_snd_controls,
f0fba2ad
LG		 1109 ARRAY_SIZE(wm8960_snd_controls));
1110 wm8960_add_widgets(codec);
f2644a2c
MB		 1111
1112 return 0;
1113}
1114
f0fba2ad
LG		 1115static struct snd_soc_codec_driver soc_codec_dev_wm8960 = {
1116 .probe = wm8960_probe,
f0fba2ad 1117 .set_bias_level = wm8960_set_bias_level,
0a87a6e1 1118 .suspend_bias_off = true,
0ebe36c6
MB		 1119};
1120
1121static const struct regmap_config wm8960_regmap = {
1122 .reg_bits = 7,
1123 .val_bits = 9,
1124 .max_register = WM8960_PLL4,
1125
1126 .reg_defaults = wm8960_reg_defaults,
1127 .num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults),
1128 .cache_type = REGCACHE_RBTREE,
1129
1130 .volatile_reg = wm8960_volatile,
f0fba2ad
LG		 1131};
1132
e2280c90
ZW		 1133static void wm8960_set_pdata_from_of(struct i2c_client *i2c,
1134 struct wm8960_data *pdata)
1135{
1136 const struct device_node *np = i2c->dev.of_node;
1137
1138 if (of_property_read_bool(np, "wlf,capless"))
1139 pdata->capless = true;
1140
1141 if (of_property_read_bool(np, "wlf,shared-lrclk"))
1142 pdata->shared_lrclk = true;
1143}
1144
7a79e94e
BP		 1145static int wm8960_i2c_probe(struct i2c_client *i2c,
1146 const struct i2c_device_id *id)
f2644a2c 1147{
37061631 1148 struct wm8960_data *pdata = dev_get_platdata(&i2c->dev);
f2644a2c 1149 struct wm8960_priv *wm8960;
f0fba2ad 1150 int ret;
f2644a2c 1151
b9791c01
MB		 1152 wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv),
1153 GFP_KERNEL);
f2644a2c
MB		 1154 if (wm8960 == NULL)
1155 return -ENOMEM;
1156
75aa8868
ZW		 1157 wm8960->mclk = devm_clk_get(&i2c->dev, "mclk");
1158 if (IS_ERR(wm8960->mclk)) {
1159 if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER)
1160 return -EPROBE_DEFER;
1161 }
1162
c5e6f5fa 1163 wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap);
0ebe36c6
MB		 1164 if (IS_ERR(wm8960->regmap))
1165 return PTR_ERR(wm8960->regmap);
1166
e2280c90
ZW		 1167 if (pdata)
1168 memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data));
1169 else if (i2c->dev.of_node)
1170 wm8960_set_pdata_from_of(i2c, &wm8960->pdata);
1171
3ad5e861
ZW		 1172 ret = wm8960_reset(wm8960->regmap);
1173 if (ret != 0) {
1174 dev_err(&i2c->dev, "Failed to issue reset\n");
1175 return ret;
1176 }
1177
1178 if (wm8960->pdata.shared_lrclk) {
37061631
MB		 1179 ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2,
1180 0x4, 0x4);
1181 if (ret != 0) {
1182 dev_err(&i2c->dev, "Failed to enable LRCM: %d\n",
1183 ret);
1184 return ret;
1185 }
1186 }
1187
3ad5e861
ZW		 1188 /* Latch the update bits */
1189 regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100);
1190 regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100);
1191 regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100);
1192 regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100);
1193 regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100);
1194 regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100);
1195 regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100);
1196 regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100);
1197 regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100);
1198 regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100);
1199
f2644a2c 1200 i2c_set_clientdata(i2c, wm8960);
f2644a2c 1201
f0fba2ad
LG		 1202 ret = snd_soc_register_codec(&i2c->dev,
1203 &soc_codec_dev_wm8960, &wm8960_dai, 1);
b9791c01 1204
f0fba2ad 1205 return ret;
f2644a2c
MB		 1206}
1207
7a79e94e 1208static int wm8960_i2c_remove(struct i2c_client *client)
f2644a2c 1209{
f0fba2ad 1210 snd_soc_unregister_codec(&client->dev);
f2644a2c
MB		 1211 return 0;
1212}
1213
1214static const struct i2c_device_id wm8960_i2c_id[] = {
1215 { "wm8960", 0 },
1216 { }
1217};
1218MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
1219
e2280c90
ZW		 1220static const struct of_device_id wm8960_of_match[] = {
1221 { .compatible = "wlf,wm8960", },
1222 { }
1223};
1224MODULE_DEVICE_TABLE(of, wm8960_of_match);
1225
f2644a2c
MB		 1226static struct i2c_driver wm8960_i2c_driver = {
1227 .driver = {
091edccf 1228 .name = "wm8960",
f2644a2c 1229 .owner = THIS_MODULE,
e2280c90 1230 .of_match_table = wm8960_of_match,
f2644a2c
MB		 1231 },
1232 .probe = wm8960_i2c_probe,
7a79e94e 1233 .remove = wm8960_i2c_remove,
f2644a2c
MB		 1234 .id_table = wm8960_i2c_id,
1235};
1236
3c010e60 1237module_i2c_driver(wm8960_i2c_driver);
f2644a2c 1238
f2644a2c
MB		 1239MODULE_DESCRIPTION("ASoC WM8960 driver");
1240MODULE_AUTHOR("Liam Girdwood");
1241MODULE_LICENSE("GPL");
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