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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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2 | /* |
3 | * wm8974.h -- WM8974 Soc Audio driver | |
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4 | */ |
5 | ||
6 | #ifndef _WM8974_H | |
7 | #define _WM8974_H | |
8 | ||
9 | /* WM8974 register space */ | |
10 | ||
11 | #define WM8974_RESET 0x0 | |
12 | #define WM8974_POWER1 0x1 | |
13 | #define WM8974_POWER2 0x2 | |
14 | #define WM8974_POWER3 0x3 | |
15 | #define WM8974_IFACE 0x4 | |
1a55b3f6 | 16 | #define WM8974_COMP 0x5 |
0a1bf553 | 17 | #define WM8974_CLOCK 0x6 |
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18 | #define WM8974_ADD 0x7 |
19 | #define WM8974_GPIO 0x8 | |
20 | #define WM8974_DAC 0xa | |
0a1bf553 | 21 | #define WM8974_DACVOL 0xb |
1a55b3f6 | 22 | #define WM8974_ADC 0xe |
0a1bf553 | 23 | #define WM8974_ADCVOL 0xf |
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24 | #define WM8974_EQ1 0x12 |
25 | #define WM8974_EQ2 0x13 | |
26 | #define WM8974_EQ3 0x14 | |
27 | #define WM8974_EQ4 0x15 | |
28 | #define WM8974_EQ5 0x16 | |
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29 | #define WM8974_DACLIM1 0x18 |
30 | #define WM8974_DACLIM2 0x19 | |
31 | #define WM8974_NOTCH1 0x1b | |
32 | #define WM8974_NOTCH2 0x1c | |
33 | #define WM8974_NOTCH3 0x1d | |
34 | #define WM8974_NOTCH4 0x1e | |
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35 | #define WM8974_ALC1 0x20 |
36 | #define WM8974_ALC2 0x21 | |
37 | #define WM8974_ALC3 0x22 | |
0a1bf553 | 38 | #define WM8974_NGATE 0x23 |
1a55b3f6 | 39 | #define WM8974_PLLN 0x24 |
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40 | #define WM8974_PLLK1 0x25 |
41 | #define WM8974_PLLK2 0x26 | |
42 | #define WM8974_PLLK3 0x27 | |
43 | #define WM8974_ATTEN 0x28 | |
44 | #define WM8974_INPUT 0x2c | |
45 | #define WM8974_INPPGA 0x2d | |
46 | #define WM8974_ADCBOOST 0x2f | |
47 | #define WM8974_OUTPUT 0x31 | |
48 | #define WM8974_SPKMIX 0x32 | |
49 | #define WM8974_SPKVOL 0x36 | |
50 | #define WM8974_MONOMIX 0x38 | |
51 | ||
52 | #define WM8974_CACHEREGNUM 57 | |
53 | ||
54 | /* Clock divider Id's */ | |
55 | #define WM8974_OPCLKDIV 0 | |
56 | #define WM8974_MCLKDIV 1 | |
b2c3e923 | 57 | #define WM8974_BCLKDIV 2 |
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58 | |
59 | /* PLL Out dividers */ | |
60 | #define WM8974_OPCLKDIV_1 (0 << 4) | |
61 | #define WM8974_OPCLKDIV_2 (1 << 4) | |
62 | #define WM8974_OPCLKDIV_3 (2 << 4) | |
63 | #define WM8974_OPCLKDIV_4 (3 << 4) | |
64 | ||
65 | /* BCLK clock dividers */ | |
66 | #define WM8974_BCLKDIV_1 (0 << 2) | |
67 | #define WM8974_BCLKDIV_2 (1 << 2) | |
68 | #define WM8974_BCLKDIV_4 (2 << 2) | |
69 | #define WM8974_BCLKDIV_8 (3 << 2) | |
70 | #define WM8974_BCLKDIV_16 (4 << 2) | |
71 | #define WM8974_BCLKDIV_32 (5 << 2) | |
72 | ||
73 | /* MCLK clock dividers */ | |
74 | #define WM8974_MCLKDIV_1 (0 << 5) | |
75 | #define WM8974_MCLKDIV_1_5 (1 << 5) | |
76 | #define WM8974_MCLKDIV_2 (2 << 5) | |
77 | #define WM8974_MCLKDIV_3 (3 << 5) | |
78 | #define WM8974_MCLKDIV_4 (4 << 5) | |
79 | #define WM8974_MCLKDIV_6 (5 << 5) | |
80 | #define WM8974_MCLKDIV_8 (6 << 5) | |
81 | #define WM8974_MCLKDIV_12 (7 << 5) | |
82 | ||
0a1bf553 | 83 | #endif |