]>
Commit | Line | Data |
---|---|---|
0d34e915 GL |
1 | /* |
2 | * wm8978.c -- WM8978 ALSA SoC Audio Codec driver | |
3 | * | |
4 | * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> | |
5 | * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com> | |
6 | * Copyright 2006-2009 Wolfson Microelectronics PLC. | |
7 | * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/pm.h> | |
20 | #include <linux/i2c.h> | |
21 | #include <linux/platform_device.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
0d34e915 GL |
23 | #include <sound/core.h> |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
0d34e915 GL |
27 | #include <sound/initval.h> |
28 | #include <sound/tlv.h> | |
29 | #include <asm/div64.h> | |
30 | ||
31 | #include "wm8978.h" | |
32 | ||
0d34e915 GL |
33 | /* wm8978 register cache. Note that register 0 is not included in the cache. */ |
34 | static const u16 wm8978_reg[WM8978_CACHEREGNUM] = { | |
35 | 0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */ | |
36 | 0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */ | |
37 | 0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */ | |
38 | 0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */ | |
39 | 0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */ | |
40 | 0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */ | |
41 | 0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */ | |
42 | 0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */ | |
43 | 0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */ | |
44 | 0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */ | |
45 | 0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */ | |
46 | 0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */ | |
47 | 0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */ | |
48 | 0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */ | |
49 | 0x0001, 0x0001, /* 0x38...0x3b */ | |
50 | }; | |
51 | ||
52 | /* codec private data */ | |
53 | struct wm8978_priv { | |
f0fba2ad LG |
54 | enum snd_soc_control_type control_type; |
55 | void *control_data; | |
0d34e915 GL |
56 | unsigned int f_pllout; |
57 | unsigned int f_mclk; | |
58 | unsigned int f_256fs; | |
59 | unsigned int f_opclk; | |
b0580913 | 60 | int mclk_idx; |
0d34e915 | 61 | enum wm8978_sysclk_src sysclk; |
0d34e915 GL |
62 | }; |
63 | ||
64 | static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"}; | |
65 | static const char *wm8978_eqmode[] = {"Capture", "Playback"}; | |
66 | static const char *wm8978_bw[] = {"Narrow", "Wide"}; | |
67 | static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"}; | |
68 | static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"}; | |
69 | static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"}; | |
70 | static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"}; | |
71 | static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"}; | |
72 | static const char *wm8978_alc3[] = {"ALC", "Limiter"}; | |
73 | static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"}; | |
74 | ||
75 | static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1, | |
76 | wm8978_companding); | |
77 | static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3, | |
78 | wm8978_companding); | |
79 | static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode); | |
80 | static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1); | |
81 | static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw); | |
82 | static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2); | |
83 | static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw); | |
84 | static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3); | |
85 | static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw); | |
86 | static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4); | |
87 | static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5); | |
88 | static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3); | |
89 | static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1); | |
90 | ||
91 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); | |
92 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
93 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0); | |
94 | static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0); | |
95 | static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1); | |
1916a2aa | 96 | static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0); |
0d34e915 GL |
97 | |
98 | static const struct snd_kcontrol_new wm8978_snd_controls[] = { | |
99 | ||
100 | SOC_SINGLE("Digital Loopback Switch", | |
101 | WM8978_COMPANDING_CONTROL, 0, 1, 0), | |
102 | ||
103 | SOC_ENUM("ADC Companding", adc_compand), | |
104 | SOC_ENUM("DAC Companding", dac_compand), | |
105 | ||
106 | SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0), | |
107 | ||
108 | SOC_DOUBLE_R_TLV("PCM Volume", | |
109 | WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME, | |
110 | 0, 255, 0, digital_tlv), | |
111 | ||
112 | SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0), | |
113 | SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0), | |
114 | SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0), | |
115 | ||
116 | SOC_DOUBLE_R_TLV("ADC Volume", | |
117 | WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME, | |
118 | 0, 255, 0, digital_tlv), | |
119 | ||
120 | SOC_ENUM("Equaliser Function", eqmode), | |
121 | SOC_ENUM("EQ1 Cut Off", eq1), | |
122 | SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv), | |
123 | ||
124 | SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw), | |
125 | SOC_ENUM("EQ2 Cut Off", eq2), | |
126 | SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv), | |
127 | ||
128 | SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw), | |
129 | SOC_ENUM("EQ3 Cut Off", eq3), | |
130 | SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv), | |
131 | ||
132 | SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw), | |
133 | SOC_ENUM("EQ4 Cut Off", eq4), | |
134 | SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv), | |
135 | ||
136 | SOC_ENUM("EQ5 Cut Off", eq5), | |
137 | SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv), | |
138 | ||
139 | SOC_SINGLE("DAC Playback Limiter Switch", | |
140 | WM8978_DAC_LIMITER_1, 8, 1, 0), | |
141 | SOC_SINGLE("DAC Playback Limiter Decay", | |
142 | WM8978_DAC_LIMITER_1, 4, 15, 0), | |
143 | SOC_SINGLE("DAC Playback Limiter Attack", | |
144 | WM8978_DAC_LIMITER_1, 0, 15, 0), | |
145 | ||
146 | SOC_SINGLE("DAC Playback Limiter Threshold", | |
147 | WM8978_DAC_LIMITER_2, 4, 7, 0), | |
1916a2aa MB |
148 | SOC_SINGLE_TLV("DAC Playback Limiter Volume", |
149 | WM8978_DAC_LIMITER_2, 0, 12, 0, limiter_tlv), | |
0d34e915 GL |
150 | |
151 | SOC_ENUM("ALC Enable Switch", alc1), | |
152 | SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0), | |
153 | SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0), | |
154 | ||
c8fb034c | 155 | SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 10, 0), |
0d34e915 GL |
156 | SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0), |
157 | ||
158 | SOC_ENUM("ALC Capture Mode", alc3), | |
c8fb034c MB |
159 | SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 10, 0), |
160 | SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 10, 0), | |
0d34e915 GL |
161 | |
162 | SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0), | |
163 | SOC_SINGLE("ALC Capture Noise Gate Threshold", | |
164 | WM8978_NOISE_GATE, 0, 7, 0), | |
165 | ||
166 | SOC_DOUBLE_R("Capture PGA ZC Switch", | |
167 | WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL, | |
168 | 7, 1, 0), | |
169 | ||
170 | /* OUT1 - Headphones */ | |
171 | SOC_DOUBLE_R("Headphone Playback ZC Switch", | |
172 | WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0), | |
173 | ||
174 | SOC_DOUBLE_R_TLV("Headphone Playback Volume", | |
175 | WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, | |
176 | 0, 63, 0, spk_tlv), | |
177 | ||
178 | /* OUT2 - Speakers */ | |
179 | SOC_DOUBLE_R("Speaker Playback ZC Switch", | |
180 | WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0), | |
181 | ||
182 | SOC_DOUBLE_R_TLV("Speaker Playback Volume", | |
183 | WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, | |
184 | 0, 63, 0, spk_tlv), | |
185 | ||
186 | /* OUT3/4 - Line Output */ | |
187 | SOC_DOUBLE_R("Line Playback Switch", | |
188 | WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1), | |
189 | ||
190 | /* Mixer #3: Boost (Input) mixer */ | |
191 | SOC_DOUBLE_R("PGA Boost (+20dB)", | |
192 | WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, | |
193 | 8, 1, 0), | |
194 | SOC_DOUBLE_R_TLV("L2/R2 Boost Volume", | |
195 | WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, | |
196 | 4, 7, 0, boost_tlv), | |
197 | SOC_DOUBLE_R_TLV("Aux Boost Volume", | |
198 | WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, | |
199 | 0, 7, 0, boost_tlv), | |
200 | ||
201 | /* Input PGA volume */ | |
202 | SOC_DOUBLE_R_TLV("Input PGA Volume", | |
203 | WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL, | |
204 | 0, 63, 0, inpga_tlv), | |
205 | ||
206 | /* Headphone */ | |
207 | SOC_DOUBLE_R("Headphone Switch", | |
208 | WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1), | |
209 | ||
210 | /* Speaker */ | |
211 | SOC_DOUBLE_R("Speaker Switch", | |
212 | WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1), | |
b2c3e923 GL |
213 | |
214 | /* DAC / ADC oversampling */ | |
c8fb034c MB |
215 | SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, |
216 | 5, 1, 0), | |
217 | SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, | |
218 | 5, 1, 0), | |
0d34e915 GL |
219 | }; |
220 | ||
221 | /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */ | |
222 | static const struct snd_kcontrol_new wm8978_left_out_mixer[] = { | |
223 | SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0), | |
224 | SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0), | |
225 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0), | |
226 | }; | |
227 | ||
228 | static const struct snd_kcontrol_new wm8978_right_out_mixer[] = { | |
229 | SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0), | |
230 | SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0), | |
231 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0), | |
232 | }; | |
233 | ||
234 | /* OUT3/OUT4 Mixer not implemented */ | |
235 | ||
236 | /* Mixer #2: Input PGA Mute */ | |
237 | static const struct snd_kcontrol_new wm8978_left_input_mixer[] = { | |
238 | SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0), | |
239 | SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0), | |
240 | SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0), | |
241 | }; | |
242 | static const struct snd_kcontrol_new wm8978_right_input_mixer[] = { | |
243 | SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0), | |
244 | SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0), | |
245 | SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0), | |
246 | }; | |
247 | ||
248 | static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = { | |
249 | SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", | |
250 | WM8978_POWER_MANAGEMENT_3, 0, 0), | |
251 | SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", | |
252 | WM8978_POWER_MANAGEMENT_3, 1, 0), | |
253 | SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", | |
254 | WM8978_POWER_MANAGEMENT_2, 0, 0), | |
255 | SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", | |
256 | WM8978_POWER_MANAGEMENT_2, 1, 0), | |
257 | ||
258 | /* Mixer #1: OUT1,2 */ | |
259 | SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3, | |
260 | 2, 0, wm8978_left_out_mixer), | |
261 | SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3, | |
262 | 3, 0, wm8978_right_out_mixer), | |
263 | ||
264 | SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2, | |
265 | 2, 0, wm8978_left_input_mixer), | |
266 | SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2, | |
267 | 3, 0, wm8978_right_input_mixer), | |
268 | ||
269 | SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2, | |
270 | 4, 0, NULL, 0), | |
271 | SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2, | |
272 | 5, 0, NULL, 0), | |
273 | ||
274 | SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL, | |
275 | 6, 1, NULL, 0), | |
276 | SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL, | |
277 | 6, 1, NULL, 0), | |
278 | ||
279 | SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2, | |
280 | 7, 0, NULL, 0), | |
281 | SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2, | |
282 | 8, 0, NULL, 0), | |
283 | ||
284 | SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3, | |
285 | 6, 0, NULL, 0), | |
286 | SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3, | |
287 | 5, 0, NULL, 0), | |
288 | ||
289 | SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3, | |
290 | 8, 0, NULL, 0), | |
291 | ||
292 | SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0), | |
293 | ||
294 | SND_SOC_DAPM_INPUT("LMICN"), | |
295 | SND_SOC_DAPM_INPUT("LMICP"), | |
296 | SND_SOC_DAPM_INPUT("RMICN"), | |
297 | SND_SOC_DAPM_INPUT("RMICP"), | |
298 | SND_SOC_DAPM_INPUT("LAUX"), | |
299 | SND_SOC_DAPM_INPUT("RAUX"), | |
300 | SND_SOC_DAPM_INPUT("L2"), | |
301 | SND_SOC_DAPM_INPUT("R2"), | |
302 | SND_SOC_DAPM_OUTPUT("LHP"), | |
303 | SND_SOC_DAPM_OUTPUT("RHP"), | |
304 | SND_SOC_DAPM_OUTPUT("LSPK"), | |
305 | SND_SOC_DAPM_OUTPUT("RSPK"), | |
306 | }; | |
307 | ||
308 | static const struct snd_soc_dapm_route audio_map[] = { | |
309 | /* Output mixer */ | |
310 | {"Right Output Mixer", "PCM Playback Switch", "Right DAC"}, | |
311 | {"Right Output Mixer", "Aux Playback Switch", "RAUX"}, | |
312 | {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"}, | |
313 | ||
314 | {"Left Output Mixer", "PCM Playback Switch", "Left DAC"}, | |
315 | {"Left Output Mixer", "Aux Playback Switch", "LAUX"}, | |
316 | {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"}, | |
317 | ||
318 | /* Outputs */ | |
319 | {"Right Headphone Out", NULL, "Right Output Mixer"}, | |
320 | {"RHP", NULL, "Right Headphone Out"}, | |
321 | ||
322 | {"Left Headphone Out", NULL, "Left Output Mixer"}, | |
323 | {"LHP", NULL, "Left Headphone Out"}, | |
324 | ||
325 | {"Right Speaker Out", NULL, "Right Output Mixer"}, | |
326 | {"RSPK", NULL, "Right Speaker Out"}, | |
327 | ||
328 | {"Left Speaker Out", NULL, "Left Output Mixer"}, | |
329 | {"LSPK", NULL, "Left Speaker Out"}, | |
330 | ||
331 | /* Boost Mixer */ | |
332 | {"Right ADC", NULL, "Right Boost Mixer"}, | |
333 | ||
334 | {"Right Boost Mixer", NULL, "RAUX"}, | |
335 | {"Right Boost Mixer", NULL, "Right Capture PGA"}, | |
336 | {"Right Boost Mixer", NULL, "R2"}, | |
337 | ||
338 | {"Left ADC", NULL, "Left Boost Mixer"}, | |
339 | ||
340 | {"Left Boost Mixer", NULL, "LAUX"}, | |
341 | {"Left Boost Mixer", NULL, "Left Capture PGA"}, | |
342 | {"Left Boost Mixer", NULL, "L2"}, | |
343 | ||
344 | /* Input PGA */ | |
345 | {"Right Capture PGA", NULL, "Right Input Mixer"}, | |
346 | {"Left Capture PGA", NULL, "Left Input Mixer"}, | |
347 | ||
348 | {"Right Input Mixer", "R2 Switch", "R2"}, | |
349 | {"Right Input Mixer", "MicN Switch", "RMICN"}, | |
350 | {"Right Input Mixer", "MicP Switch", "RMICP"}, | |
351 | ||
352 | {"Left Input Mixer", "L2 Switch", "L2"}, | |
353 | {"Left Input Mixer", "MicN Switch", "LMICN"}, | |
354 | {"Left Input Mixer", "MicP Switch", "LMICP"}, | |
355 | }; | |
356 | ||
357 | static int wm8978_add_widgets(struct snd_soc_codec *codec) | |
358 | { | |
ce6120cc | 359 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
0d34e915 | 360 | |
ce6120cc LG |
361 | snd_soc_dapm_new_controls(dapm, wm8978_dapm_widgets, |
362 | ARRAY_SIZE(wm8978_dapm_widgets)); | |
0d34e915 | 363 | /* set up the WM8978 audio map */ |
ce6120cc | 364 | snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); |
0d34e915 GL |
365 | |
366 | return 0; | |
367 | } | |
368 | ||
369 | /* PLL divisors */ | |
370 | struct wm8978_pll_div { | |
371 | u32 k; | |
372 | u8 n; | |
373 | u8 div2; | |
374 | }; | |
375 | ||
376 | #define FIXED_PLL_SIZE (1 << 24) | |
377 | ||
f0fba2ad LG |
378 | static void pll_factors(struct snd_soc_codec *codec, |
379 | struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source) | |
0d34e915 GL |
380 | { |
381 | u64 k_part; | |
382 | unsigned int k, n_div, n_mod; | |
383 | ||
384 | n_div = target / source; | |
385 | if (n_div < 6) { | |
386 | source >>= 1; | |
387 | pll_div->div2 = 1; | |
388 | n_div = target / source; | |
389 | } else { | |
390 | pll_div->div2 = 0; | |
391 | } | |
392 | ||
393 | if (n_div < 6 || n_div > 12) | |
f0fba2ad | 394 | dev_warn(codec->dev, |
0d34e915 GL |
395 | "WM8978 N value exceeds recommended range! N = %u\n", |
396 | n_div); | |
397 | ||
398 | pll_div->n = n_div; | |
399 | n_mod = target - source * n_div; | |
400 | k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2; | |
401 | ||
402 | do_div(k_part, source); | |
403 | ||
404 | k = k_part & 0xFFFFFFFF; | |
405 | ||
406 | pll_div->k = k; | |
407 | } | |
b0580913 GL |
408 | |
409 | /* MCLK dividers */ | |
410 | static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12}; | |
411 | static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1}; | |
412 | ||
413 | /* | |
414 | * find index >= idx, such that, for a given f_out, | |
415 | * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4 | |
416 | * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be | |
417 | * generalised for f_opclk with suitable coefficient arrays, but currently | |
418 | * the OPCLK divisor is calculated directly, not iteratively. | |
419 | */ | |
420 | static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk, | |
421 | unsigned int *f_pllout) | |
422 | { | |
423 | int i; | |
424 | ||
425 | for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) { | |
426 | unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] / | |
427 | mclk_denominator[i]; | |
428 | if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) { | |
429 | *f_pllout = f_pllout_x4 / 4; | |
430 | return i; | |
431 | } | |
432 | } | |
433 | ||
434 | return -EINVAL; | |
435 | } | |
436 | ||
0d34e915 GL |
437 | /* |
438 | * Calculate internal frequencies and dividers, according to Figure 40 | |
439 | * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6 | |
440 | */ | |
441 | static int wm8978_configure_pll(struct snd_soc_codec *codec) | |
442 | { | |
b2c812e2 | 443 | struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); |
0d34e915 GL |
444 | struct wm8978_pll_div pll_div; |
445 | unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk, | |
446 | f_256fs = wm8978->f_256fs; | |
b0580913 | 447 | unsigned int f2; |
0d34e915 GL |
448 | |
449 | if (!f_mclk) | |
450 | return -EINVAL; | |
451 | ||
452 | if (f_opclk) { | |
b0580913 GL |
453 | unsigned int opclk_div; |
454 | /* Cannot set up MCLK divider now, do later */ | |
455 | wm8978->mclk_idx = -1; | |
456 | ||
0d34e915 GL |
457 | /* |
458 | * The user needs OPCLK. Choose OPCLKDIV to put | |
459 | * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4. | |
460 | * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where | |
461 | * prescale = 1, or prescale = 2. Prescale is calculated inside | |
462 | * pll_factors(). We have to select f_PLLOUT, such that | |
463 | * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be | |
464 | * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4. | |
465 | */ | |
466 | if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk) | |
467 | return -EINVAL; | |
468 | ||
469 | if (4 * f_opclk < 3 * f_mclk) | |
470 | /* Have to use OPCLKDIV */ | |
471 | opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk; | |
472 | else | |
473 | opclk_div = 1; | |
474 | ||
475 | dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div); | |
476 | ||
477 | snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30, | |
478 | (opclk_div - 1) << 4); | |
479 | ||
480 | wm8978->f_pllout = f_opclk * opclk_div; | |
481 | } else if (f_256fs) { | |
482 | /* | |
b0580913 | 483 | * Not using OPCLK, but PLL is used for the codec, choose R: |
0d34e915 GL |
484 | * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12. |
485 | * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where | |
486 | * prescale = 1, or prescale = 2. Prescale is calculated inside | |
487 | * pll_factors(). We have to select f_PLLOUT, such that | |
488 | * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be | |
489 | * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK | |
490 | * must be 3.781MHz <= f_MCLK <= 32.768MHz | |
491 | */ | |
b0580913 GL |
492 | int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout); |
493 | if (idx < 0) | |
494 | return idx; | |
0d34e915 | 495 | |
b0580913 | 496 | wm8978->mclk_idx = idx; |
0d34e915 GL |
497 | |
498 | /* GPIO1 into default mode as input - before configuring PLL */ | |
499 | snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0); | |
500 | } else { | |
501 | return -EINVAL; | |
502 | } | |
503 | ||
504 | f2 = wm8978->f_pllout * 4; | |
505 | ||
506 | dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__, | |
507 | wm8978->f_mclk, wm8978->f_pllout); | |
508 | ||
f0fba2ad | 509 | pll_factors(codec, &pll_div, f2, wm8978->f_mclk); |
0d34e915 GL |
510 | |
511 | dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n", | |
512 | __func__, pll_div.n, pll_div.k, pll_div.div2); | |
513 | ||
514 | /* Turn PLL off for configuration... */ | |
515 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0); | |
516 | ||
517 | snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n); | |
518 | snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18); | |
519 | snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff); | |
520 | snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff); | |
521 | ||
522 | /* ...and on again */ | |
523 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20); | |
524 | ||
525 | if (f_opclk) | |
526 | /* Output PLL (OPCLK) to GPIO1 */ | |
527 | snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4); | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
532 | /* | |
533 | * Configure WM8978 clock dividers. | |
534 | */ | |
535 | static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai, | |
536 | int div_id, int div) | |
537 | { | |
538 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 539 | struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); |
0d34e915 GL |
540 | int ret = 0; |
541 | ||
542 | switch (div_id) { | |
543 | case WM8978_OPCLKRATE: | |
544 | wm8978->f_opclk = div; | |
545 | ||
546 | if (wm8978->f_mclk) | |
b0580913 GL |
547 | /* |
548 | * We know the MCLK frequency, the user has requested | |
549 | * OPCLK, configure the PLL based on that and start it | |
550 | * and OPCLK immediately. We will configure PLL to match | |
551 | * user-requested OPCLK frquency as good as possible. | |
552 | * In fact, it is likely, that matching the sampling | |
553 | * rate, when it becomes known, is more important, and | |
554 | * we will not be reconfiguring PLL then, because we | |
555 | * must not interrupt OPCLK. But it should be fine, | |
556 | * because typically the user will request OPCLK to run | |
557 | * at 256fs or 512fs, and for these cases we will also | |
558 | * find an exact MCLK divider configuration - it will | |
559 | * be equal to or double the OPCLK divisor. | |
560 | */ | |
0d34e915 GL |
561 | ret = wm8978_configure_pll(codec); |
562 | break; | |
0d34e915 GL |
563 | case WM8978_BCLKDIV: |
564 | if (div & ~0x1c) | |
565 | return -EINVAL; | |
566 | snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div); | |
567 | break; | |
568 | default: | |
569 | return -EINVAL; | |
570 | } | |
571 | ||
572 | dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div); | |
573 | ||
574 | return ret; | |
575 | } | |
576 | ||
577 | /* | |
578 | * @freq: when .set_pll() us not used, freq is codec MCLK input frequency | |
579 | */ | |
580 | static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, | |
581 | unsigned int freq, int dir) | |
582 | { | |
583 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 584 | struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); |
0d34e915 GL |
585 | int ret = 0; |
586 | ||
587 | dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq); | |
588 | ||
589 | if (freq) { | |
590 | wm8978->f_mclk = freq; | |
591 | ||
592 | /* Even if MCLK is used for system clock, might have to drive OPCLK */ | |
593 | if (wm8978->f_opclk) | |
594 | ret = wm8978_configure_pll(codec); | |
595 | ||
596 | /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */ | |
597 | ||
598 | if (!ret) | |
599 | wm8978->sysclk = clk_id; | |
600 | } | |
601 | ||
602 | if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) { | |
603 | /* Clock CODEC directly from MCLK */ | |
604 | snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0); | |
605 | ||
606 | /* GPIO1 into default mode as input - before configuring PLL */ | |
607 | snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0); | |
608 | ||
609 | /* Turn off PLL */ | |
610 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0); | |
611 | wm8978->sysclk = WM8978_MCLK; | |
612 | wm8978->f_pllout = 0; | |
613 | wm8978->f_opclk = 0; | |
614 | } | |
615 | ||
616 | return ret; | |
617 | } | |
618 | ||
619 | /* | |
620 | * Set ADC and Voice DAC format. | |
621 | */ | |
622 | static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
623 | { | |
624 | struct snd_soc_codec *codec = codec_dai->codec; | |
625 | /* | |
626 | * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80, | |
627 | * Data Format mask = 0x18: all will be calculated anew | |
628 | */ | |
629 | u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198; | |
630 | u16 clk = snd_soc_read(codec, WM8978_CLOCKING); | |
631 | ||
632 | dev_dbg(codec->dev, "%s\n", __func__); | |
633 | ||
634 | /* set master/slave audio interface */ | |
635 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
636 | case SND_SOC_DAIFMT_CBM_CFM: | |
637 | clk |= 1; | |
638 | break; | |
639 | case SND_SOC_DAIFMT_CBS_CFS: | |
640 | clk &= ~1; | |
641 | break; | |
642 | default: | |
643 | return -EINVAL; | |
644 | } | |
645 | ||
646 | /* interface format */ | |
647 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
648 | case SND_SOC_DAIFMT_I2S: | |
649 | iface |= 0x10; | |
650 | break; | |
651 | case SND_SOC_DAIFMT_RIGHT_J: | |
652 | break; | |
653 | case SND_SOC_DAIFMT_LEFT_J: | |
654 | iface |= 0x8; | |
655 | break; | |
656 | case SND_SOC_DAIFMT_DSP_A: | |
657 | iface |= 0x18; | |
658 | break; | |
659 | default: | |
660 | return -EINVAL; | |
661 | } | |
662 | ||
663 | /* clock inversion */ | |
664 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
665 | case SND_SOC_DAIFMT_NB_NF: | |
666 | break; | |
667 | case SND_SOC_DAIFMT_IB_IF: | |
668 | iface |= 0x180; | |
669 | break; | |
670 | case SND_SOC_DAIFMT_IB_NF: | |
671 | iface |= 0x100; | |
672 | break; | |
673 | case SND_SOC_DAIFMT_NB_IF: | |
674 | iface |= 0x80; | |
675 | break; | |
676 | default: | |
677 | return -EINVAL; | |
678 | } | |
679 | ||
680 | snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface); | |
681 | snd_soc_write(codec, WM8978_CLOCKING, clk); | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
0d34e915 GL |
686 | /* |
687 | * Set PCM DAI bit size and sample rate. | |
688 | */ | |
689 | static int wm8978_hw_params(struct snd_pcm_substream *substream, | |
690 | struct snd_pcm_hw_params *params, | |
691 | struct snd_soc_dai *dai) | |
692 | { | |
693 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 694 | struct snd_soc_codec *codec = rtd->codec; |
b2c812e2 | 695 | struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); |
0d34e915 GL |
696 | /* Word length mask = 0x60 */ |
697 | u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60; | |
698 | /* Sampling rate mask = 0xe (for filters) */ | |
699 | u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe; | |
700 | u16 clking = snd_soc_read(codec, WM8978_CLOCKING); | |
701 | enum wm8978_sysclk_src current_clk_id = clking & 0x100 ? | |
702 | WM8978_PLL : WM8978_MCLK; | |
703 | unsigned int f_sel, diff, diff_best = INT_MAX; | |
704 | int i, best = 0; | |
705 | ||
706 | if (!wm8978->f_mclk) | |
707 | return -EINVAL; | |
708 | ||
709 | /* bit size */ | |
710 | switch (params_format(params)) { | |
711 | case SNDRV_PCM_FORMAT_S16_LE: | |
712 | break; | |
713 | case SNDRV_PCM_FORMAT_S20_3LE: | |
714 | iface_ctl |= 0x20; | |
715 | break; | |
716 | case SNDRV_PCM_FORMAT_S24_LE: | |
717 | iface_ctl |= 0x40; | |
718 | break; | |
719 | case SNDRV_PCM_FORMAT_S32_LE: | |
720 | iface_ctl |= 0x60; | |
721 | break; | |
722 | } | |
723 | ||
724 | /* filter coefficient */ | |
725 | switch (params_rate(params)) { | |
726 | case 8000: | |
727 | add_ctl |= 0x5 << 1; | |
728 | break; | |
729 | case 11025: | |
730 | add_ctl |= 0x4 << 1; | |
731 | break; | |
732 | case 16000: | |
733 | add_ctl |= 0x3 << 1; | |
734 | break; | |
735 | case 22050: | |
736 | add_ctl |= 0x2 << 1; | |
737 | break; | |
738 | case 32000: | |
739 | add_ctl |= 0x1 << 1; | |
740 | break; | |
741 | case 44100: | |
742 | case 48000: | |
743 | break; | |
744 | } | |
745 | ||
746 | /* Sampling rate is known now, can configure the MCLK divider */ | |
747 | wm8978->f_256fs = params_rate(params) * 256; | |
748 | ||
749 | if (wm8978->sysclk == WM8978_MCLK) { | |
b0580913 | 750 | wm8978->mclk_idx = -1; |
0d34e915 GL |
751 | f_sel = wm8978->f_mclk; |
752 | } else { | |
753 | if (!wm8978->f_pllout) { | |
b0580913 | 754 | /* We only enter here, if OPCLK is not used */ |
0d34e915 GL |
755 | int ret = wm8978_configure_pll(codec); |
756 | if (ret < 0) | |
757 | return ret; | |
758 | } | |
759 | f_sel = wm8978->f_pllout; | |
760 | } | |
761 | ||
b0580913 GL |
762 | if (wm8978->mclk_idx < 0) { |
763 | /* Either MCLK is used directly, or OPCLK is used */ | |
764 | if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs) | |
765 | return -EINVAL; | |
0d34e915 | 766 | |
b0580913 GL |
767 | for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) { |
768 | diff = abs(wm8978->f_256fs * 3 - | |
769 | f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]); | |
0d34e915 | 770 | |
b0580913 GL |
771 | if (diff < diff_best) { |
772 | diff_best = diff; | |
773 | best = i; | |
774 | } | |
0d34e915 | 775 | |
b0580913 GL |
776 | if (!diff) |
777 | break; | |
778 | } | |
779 | } else { | |
780 | /* OPCLK not used, codec driven by PLL */ | |
781 | best = wm8978->mclk_idx; | |
782 | diff = 0; | |
0d34e915 GL |
783 | } |
784 | ||
785 | if (diff) | |
b0580913 GL |
786 | dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n", |
787 | f_sel * mclk_denominator[best] / mclk_numerator[best] / 256, | |
788 | wm8978->sysclk == WM8978_MCLK ? | |
789 | ", consider using PLL" : ""); | |
0d34e915 GL |
790 | |
791 | dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__, | |
792 | params_format(params), params_rate(params), best); | |
793 | ||
794 | /* MCLK divisor mask = 0xe0 */ | |
795 | snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5); | |
796 | ||
797 | snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl); | |
798 | snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl); | |
799 | ||
800 | if (wm8978->sysclk != current_clk_id) { | |
801 | if (wm8978->sysclk == WM8978_PLL) | |
802 | /* Run CODEC from PLL instead of MCLK */ | |
803 | snd_soc_update_bits(codec, WM8978_CLOCKING, | |
804 | 0x100, 0x100); | |
805 | else | |
806 | /* Clock CODEC directly from MCLK */ | |
807 | snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0); | |
808 | } | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | static int wm8978_mute(struct snd_soc_dai *dai, int mute) | |
814 | { | |
815 | struct snd_soc_codec *codec = dai->codec; | |
816 | ||
817 | dev_dbg(codec->dev, "%s: %d\n", __func__, mute); | |
818 | ||
819 | if (mute) | |
820 | snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40); | |
821 | else | |
822 | snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0); | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | static int wm8978_set_bias_level(struct snd_soc_codec *codec, | |
828 | enum snd_soc_bias_level level) | |
829 | { | |
830 | u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3; | |
831 | ||
832 | switch (level) { | |
833 | case SND_SOC_BIAS_ON: | |
834 | case SND_SOC_BIAS_PREPARE: | |
835 | power1 |= 1; /* VMID 75k */ | |
836 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1); | |
837 | break; | |
838 | case SND_SOC_BIAS_STANDBY: | |
839 | /* bit 3: enable bias, bit 2: enable I/O tie off buffer */ | |
840 | power1 |= 0xc; | |
841 | ||
ce6120cc | 842 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
0d34e915 GL |
843 | /* Initial cap charge at VMID 5k */ |
844 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, | |
845 | power1 | 0x3); | |
846 | mdelay(100); | |
847 | } | |
848 | ||
849 | power1 |= 0x2; /* VMID 500k */ | |
850 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1); | |
851 | break; | |
852 | case SND_SOC_BIAS_OFF: | |
853 | /* Preserve PLL - OPCLK may be used by someone */ | |
854 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0); | |
855 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0); | |
856 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0); | |
857 | break; | |
858 | } | |
859 | ||
860 | dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1); | |
861 | ||
ce6120cc | 862 | codec->dapm.bias_level = level; |
0d34e915 GL |
863 | return 0; |
864 | } | |
865 | ||
866 | #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
867 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
868 | ||
869 | static struct snd_soc_dai_ops wm8978_dai_ops = { | |
870 | .hw_params = wm8978_hw_params, | |
871 | .digital_mute = wm8978_mute, | |
872 | .set_fmt = wm8978_set_dai_fmt, | |
873 | .set_clkdiv = wm8978_set_dai_clkdiv, | |
874 | .set_sysclk = wm8978_set_dai_sysclk, | |
875 | }; | |
876 | ||
877 | /* Also supports 12kHz */ | |
f0fba2ad LG |
878 | static struct snd_soc_dai_driver wm8978_dai = { |
879 | .name = "wm8978-hifi", | |
0d34e915 GL |
880 | .playback = { |
881 | .stream_name = "Playback", | |
882 | .channels_min = 1, | |
883 | .channels_max = 2, | |
884 | .rates = SNDRV_PCM_RATE_8000_48000, | |
885 | .formats = WM8978_FORMATS, | |
886 | }, | |
887 | .capture = { | |
888 | .stream_name = "Capture", | |
889 | .channels_min = 1, | |
890 | .channels_max = 2, | |
891 | .rates = SNDRV_PCM_RATE_8000_48000, | |
892 | .formats = WM8978_FORMATS, | |
893 | }, | |
894 | .ops = &wm8978_dai_ops, | |
895 | }; | |
0d34e915 | 896 | |
f0fba2ad | 897 | static int wm8978_suspend(struct snd_soc_codec *codec, pm_message_t state) |
0d34e915 | 898 | { |
0d34e915 GL |
899 | wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF); |
900 | /* Also switch PLL off */ | |
901 | snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0); | |
0d34e915 GL |
902 | |
903 | return 0; | |
904 | } | |
905 | ||
f0fba2ad | 906 | static int wm8978_resume(struct snd_soc_codec *codec) |
0d34e915 | 907 | { |
b2c812e2 | 908 | struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); |
0d34e915 GL |
909 | int i; |
910 | u16 *cache = codec->reg_cache; | |
911 | ||
0d34e915 GL |
912 | /* Sync reg_cache with the hardware */ |
913 | for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) { | |
914 | if (i == WM8978_RESET) | |
915 | continue; | |
916 | if (cache[i] != wm8978_reg[i]) | |
917 | snd_soc_write(codec, i, cache[i]); | |
918 | } | |
919 | ||
920 | wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
921 | ||
922 | if (wm8978->f_pllout) | |
923 | /* Switch PLL on */ | |
924 | snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20); | |
925 | ||
926 | return 0; | |
927 | } | |
928 | ||
0d34e915 GL |
929 | /* |
930 | * These registers contain an "update" bit - bit 8. This means, for example, | |
931 | * that one can write new DAC digital volume for both channels, but only when | |
932 | * the update bit is set, will also the volume be updated - simultaneously for | |
933 | * both channels. | |
934 | */ | |
935 | static const int update_reg[] = { | |
936 | WM8978_LEFT_DAC_DIGITAL_VOLUME, | |
937 | WM8978_RIGHT_DAC_DIGITAL_VOLUME, | |
938 | WM8978_LEFT_ADC_DIGITAL_VOLUME, | |
939 | WM8978_RIGHT_ADC_DIGITAL_VOLUME, | |
940 | WM8978_LEFT_INP_PGA_CONTROL, | |
941 | WM8978_RIGHT_INP_PGA_CONTROL, | |
942 | WM8978_LOUT1_HP_CONTROL, | |
943 | WM8978_ROUT1_HP_CONTROL, | |
944 | WM8978_LOUT2_SPK_CONTROL, | |
945 | WM8978_ROUT2_SPK_CONTROL, | |
946 | }; | |
947 | ||
f0fba2ad | 948 | static int wm8978_probe(struct snd_soc_codec *codec) |
0d34e915 | 949 | { |
f0fba2ad LG |
950 | struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); |
951 | int ret = 0, i; | |
0d34e915 GL |
952 | |
953 | /* | |
954 | * Set default system clock to PLL, it is more precise, this is also the | |
955 | * default hardware setting | |
956 | */ | |
957 | wm8978->sysclk = WM8978_PLL; | |
f0fba2ad | 958 | codec->control_data = wm8978->control_data; |
0d34e915 GL |
959 | ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C); |
960 | if (ret < 0) { | |
961 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
f0fba2ad | 962 | return ret; |
0d34e915 GL |
963 | } |
964 | ||
0d34e915 GL |
965 | /* |
966 | * Set the update bit in all registers, that have one. This way all | |
967 | * writes to those registers will also cause the update bit to be | |
968 | * written. | |
969 | */ | |
970 | for (i = 0; i < ARRAY_SIZE(update_reg); i++) | |
a1b3b5ee | 971 | snd_soc_update_bits(codec, update_reg[i], 0x100, 0x100); |
0d34e915 GL |
972 | |
973 | /* Reset the codec */ | |
974 | ret = snd_soc_write(codec, WM8978_RESET, 0); | |
975 | if (ret < 0) { | |
976 | dev_err(codec->dev, "Failed to issue reset\n"); | |
f0fba2ad | 977 | return ret; |
0d34e915 GL |
978 | } |
979 | ||
0d34e915 GL |
980 | wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
981 | ||
f0fba2ad LG |
982 | snd_soc_add_controls(codec, wm8978_snd_controls, |
983 | ARRAY_SIZE(wm8978_snd_controls)); | |
984 | wm8978_add_widgets(codec); | |
0d34e915 GL |
985 | |
986 | return 0; | |
0d34e915 GL |
987 | } |
988 | ||
f0fba2ad LG |
989 | /* power down chip */ |
990 | static int wm8978_remove(struct snd_soc_codec *codec) | |
0d34e915 | 991 | { |
f0fba2ad LG |
992 | wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF); |
993 | return 0; | |
0d34e915 GL |
994 | } |
995 | ||
f0fba2ad LG |
996 | static struct snd_soc_codec_driver soc_codec_dev_wm8978 = { |
997 | .probe = wm8978_probe, | |
998 | .remove = wm8978_remove, | |
999 | .suspend = wm8978_suspend, | |
1000 | .resume = wm8978_resume, | |
1001 | .set_bias_level = wm8978_set_bias_level, | |
1002 | .reg_cache_size = ARRAY_SIZE(wm8978_reg), | |
1003 | .reg_word_size = sizeof(u16), | |
1004 | .reg_cache_default = wm8978_reg, | |
1005 | }; | |
1006 | ||
1007 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
0d34e915 GL |
1008 | static __devinit int wm8978_i2c_probe(struct i2c_client *i2c, |
1009 | const struct i2c_device_id *id) | |
1010 | { | |
1011 | struct wm8978_priv *wm8978; | |
f0fba2ad | 1012 | int ret; |
0d34e915 GL |
1013 | |
1014 | wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL); | |
1015 | if (wm8978 == NULL) | |
1016 | return -ENOMEM; | |
1017 | ||
0d34e915 | 1018 | i2c_set_clientdata(i2c, wm8978); |
f0fba2ad | 1019 | wm8978->control_data = i2c; |
0d34e915 | 1020 | |
f0fba2ad LG |
1021 | ret = snd_soc_register_codec(&i2c->dev, |
1022 | &soc_codec_dev_wm8978, &wm8978_dai, 1); | |
d484366b AL |
1023 | if (ret < 0) |
1024 | kfree(wm8978); | |
d484366b | 1025 | return ret; |
0d34e915 GL |
1026 | } |
1027 | ||
1028 | static __devexit int wm8978_i2c_remove(struct i2c_client *client) | |
1029 | { | |
f0fba2ad LG |
1030 | snd_soc_unregister_codec(&client->dev); |
1031 | kfree(i2c_get_clientdata(client)); | |
0d34e915 GL |
1032 | return 0; |
1033 | } | |
1034 | ||
1035 | static const struct i2c_device_id wm8978_i2c_id[] = { | |
1036 | { "wm8978", 0 }, | |
1037 | { } | |
1038 | }; | |
1039 | MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id); | |
1040 | ||
1041 | static struct i2c_driver wm8978_i2c_driver = { | |
1042 | .driver = { | |
5250a503 | 1043 | .name = "wm8978", |
0d34e915 GL |
1044 | .owner = THIS_MODULE, |
1045 | }, | |
1046 | .probe = wm8978_i2c_probe, | |
1047 | .remove = __devexit_p(wm8978_i2c_remove), | |
1048 | .id_table = wm8978_i2c_id, | |
1049 | }; | |
f0fba2ad | 1050 | #endif |
0d34e915 GL |
1051 | |
1052 | static int __init wm8978_modinit(void) | |
1053 | { | |
f0fba2ad LG |
1054 | int ret = 0; |
1055 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1056 | ret = i2c_add_driver(&wm8978_i2c_driver); | |
1057 | if (ret != 0) { | |
1058 | printk(KERN_ERR "Failed to register WM8978 I2C driver: %d\n", | |
1059 | ret); | |
1060 | } | |
1061 | #endif | |
1062 | return ret; | |
0d34e915 GL |
1063 | } |
1064 | module_init(wm8978_modinit); | |
1065 | ||
1066 | static void __exit wm8978_exit(void) | |
1067 | { | |
f0fba2ad | 1068 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
0d34e915 | 1069 | i2c_del_driver(&wm8978_i2c_driver); |
f0fba2ad | 1070 | #endif |
0d34e915 GL |
1071 | } |
1072 | module_exit(wm8978_exit); | |
1073 | ||
1074 | MODULE_DESCRIPTION("ASoC WM8978 codec driver"); | |
1075 | MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); | |
1076 | MODULE_LICENSE("GPL"); |